From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
Shekhar Chauhan <shekhar.chauhan@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Tejas Upadhyay <tejas.upadhyay@intel.com>,
Harish Chegondi <harish.chegondi@intel.com>,
Ashutosh Dixit <ashutosh.dixit@intel.com>
Subject: [PATCH v3 24/24] drm/xe/xe3p: Add xe3p EU stall data format
Date: Thu, 16 Oct 2025 19:26:43 -0700 [thread overview]
Message-ID: <20251016-xe3p-v3-24-3dd173a3097a@intel.com> (raw)
In-Reply-To: <20251016-xe3p-v3-0-3dd173a3097a@intel.com>
From: Harish Chegondi <harish.chegondi@intel.com>
Starting with Xe3p, IP address in EU stall data increases to 61 bits.
While at it, re-order the if-else ladder so the officially supported
platforms come before PVC.
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: reorder the if-else ladder so PVC is the last (Lucas)
---
drivers/gpu/drm/xe/xe_eu_stall.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index f5cfdf29fde34..650e45f6a7c7e 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 {
__u64 unused[6];
} __packed;
+/*
+ * EU stall data format for Xe3p arch GPUs.
+ */
+struct xe_eu_stall_data_xe3p {
+ __u64 ip_addr:61; /* Bits 0 to 60 */
+ __u64 tdr_count:8; /* Bits 61 to 68 */
+ __u64 other_count:8; /* Bits 69 to 76 */
+ __u64 control_count:8; /* Bits 77 to 84 */
+ __u64 pipestall_count:8; /* Bits 85 to 92 */
+ __u64 send_count:8; /* Bits 93 to 100 */
+ __u64 dist_acc_count:8; /* Bits 101 to 108 */
+ __u64 sbid_count:8; /* Bits 109 to 116 */
+ __u64 sync_count:8; /* Bits 117 to 124 */
+ __u64 inst_fetch_count:8; /* Bits 125 to 132 */
+ __u64 active_count:8; /* Bits 133 to 140 */
+ __u64 ex_id:3; /* Bits 141 to 143 */
+ __u64 end_flag:1; /* Bit 144 */
+ __u64 unused_bits:47;
+ __u64 unused[5];
+} __packed;
+
const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7};
/**
@@ -167,10 +188,13 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe)
{
size_t record_size = 0;
- if (xe->info.platform == XE_PVC)
- record_size = sizeof(struct xe_eu_stall_data_pvc);
+ if (GRAPHICS_VER(xe) >= 35)
+ record_size = sizeof(struct xe_eu_stall_data_xe3p);
else if (GRAPHICS_VER(xe) >= 20)
record_size = sizeof(struct xe_eu_stall_data_xe2);
+ else if (xe->info.platform == XE_PVC)
+ record_size = sizeof(struct xe_eu_stall_data_pvc);
+
xe_assert(xe, is_power_of_2(record_size));
--
2.51.0
next prev parent reply other threads:[~2025-10-17 2:27 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 2:26 [PATCH v3 00/24] drm/xe: Add Xe3p support Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 01/24] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05 Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 02/24] drm/xe/xe3p: Add support for media IP versions 35.00 & 35.03 Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 03/24] drm/xe: Drop CTC_MODE register read Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 04/24] drm/xe: Add GT_VER() to check version specific to gt type Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 05/24] drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 06/24] drm/xe/xe3p_lpm: Handle MCR steering Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 07/24] drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 08/24] drm/xe/xe3p: Determine service copy availability from fuse Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 09/24] drm/xe: Dump CURRENT_LRCA register Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 10/24] drm/xe/xe3p: Dump CSMQDEBUG register Lucas De Marchi
2025-10-17 15:55 ` Matt Roper
2025-10-21 16:02 ` Summers, Stuart
2025-10-17 2:26 ` [PATCH v3 11/24] drm/xe/nvl: Define NVL-S platform Lucas De Marchi
2025-10-17 13:05 ` Gustavo Sousa
2025-10-17 2:26 ` [PATCH v3 12/24] drm/xe/nvls: Define GuC firmware for NVL-S Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 13/24] drm/xe/nvls: Attach MOCS table " Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 14/24] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 15/24] drm/xe/xe3p_xpc: Add L3 bank mask Lucas De Marchi
2025-10-17 17:51 ` Matt Roper
2025-10-18 3:18 ` Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 16/24] drm/xe/xe3p_xpc: Add MCR steering Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 17/24] drm/xe/irq: Rename fuse mask variables Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 18/24] drm/xe/irq: Split irq mask per engine class Lucas De Marchi
2025-10-17 16:03 ` Matt Roper
2025-10-17 2:26 ` [PATCH v3 19/24] drm/xe/irq: Rename bits used with all engines Lucas De Marchi
2025-10-17 16:05 ` Matt Roper
2025-10-17 2:26 ` [PATCH v3 20/24] drm/xe/irq: Check fuse mask for media engines Lucas De Marchi
2025-10-17 16:07 ` Matt Roper
2025-10-17 2:26 ` [PATCH v3 21/24] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx Lucas De Marchi
2025-10-17 17:04 ` Matt Roper
2025-10-17 2:26 ` [PATCH v3 22/24] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 23/24] drm/xe/xe3p_xpc: Setup PAT table Lucas De Marchi
2025-10-17 11:05 ` Ville Syrjälä
2025-10-17 17:18 ` Matt Roper
2025-10-17 18:09 ` Ville Syrjälä
2025-10-17 20:33 ` Matt Roper
2025-10-17 2:26 ` Lucas De Marchi [this message]
2025-10-17 2:35 ` ✗ CI.checkpatch: warning for drm/xe: Add Xe3p support (rev3) Patchwork
2025-10-17 2:36 ` ✓ CI.KUnit: success " Patchwork
2025-10-17 3:23 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-18 1:56 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-19 2:55 ` [PATCH v3 00/24] drm/xe: Add Xe3p support Lucas De Marchi
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