Re: [PATCH v3 19/24] drm/xe/irq: Rename bits used with all engines

[Matt Roper <matthew.d.roper@intel.com>]

On Thu, Oct 16, 2025 at 07:26:38PM -0700, Lucas De Marchi wrote:
> Two bit fields have similar functionality across the interrupt vectors
> but are named "RENDER". Rename them to follow the bspec more closely and
> clear any confusion when using them for other engines.
> 
> Bspec: 62353, 62354, 62355, 62346, 62345, 63341
> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_irq_regs.h | 4 ++--
>  drivers/gpu/drm/xe/xe_hw_engine.c     | 2 +-
>  drivers/gpu/drm/xe/xe_irq.c           | 6 +++---
>  drivers/gpu/drm/xe/xe_memirq.c        | 4 ++--
>  4 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 7c2a3a1401424..f6117720963b6 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -80,9 +80,9 @@
>  #define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
>  #define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)
>  #define   GSC_ER_COMPLETE			REG_BIT(5)
> -#define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
> +#define   GT_FLUSH_COMPLETE_INTERRUPT	REG_BIT(4)
>  #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
> -#define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
> +#define   GT_MI_USER_INTERRUPT			REG_BIT(0)
>  
>  /* irqs for OTHER_KCR_INSTANCE */
>  #define   KCR_PXP_STATE_TERMINATED_INTERRUPT		REG_BIT(1)
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 073ecd263e543..6a9e2a4272dde 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -904,7 +904,7 @@ void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec)
>  	if (hwe->irq_handler)
>  		hwe->irq_handler(hwe, intr_vec);
>  
> -	if (intr_vec & GT_RENDER_USER_INTERRUPT)
> +	if (intr_vec & GT_MI_USER_INTERRUPT)
>  		xe_hw_fence_irq_run(hwe->fence_irq);
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 142f422a5d97e..2108c86ed478d 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -147,10 +147,10 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
>  		return;
>  
>  	if (xe_device_uc_enabled(xe)) {
> -		common_mask = GT_RENDER_USER_INTERRUPT |
> -			      GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> +		common_mask = GT_MI_USER_INTERRUPT |
> +			      GT_FLUSH_COMPLETE_INTERRUPT;
>  	} else {
> -		common_mask = GT_RENDER_USER_INTERRUPT |
> +		common_mask = GT_MI_USER_INTERRUPT |
>  			      GT_CS_MASTER_ERROR_INTERRUPT |
>  			      GT_CONTEXT_SWITCH_INTERRUPT |
>  			      GT_WAIT_SEMAPHORE_INTERRUPT;
> diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
> index 2ef9d9aab2649..b0c7ce0a5d1eb 100644
> --- a/drivers/gpu/drm/xe/xe_memirq.c
> +++ b/drivers/gpu/drm/xe/xe_memirq.c
> @@ -434,8 +434,8 @@ static void memirq_dispatch_engine(struct xe_memirq *memirq, struct iosys_map *s
>  {
>  	memirq_debug(memirq, "STATUS %s %*ph\n", hwe->name, 16, status->vaddr);
>  
> -	if (memirq_received(memirq, status, ilog2(GT_RENDER_USER_INTERRUPT), hwe->name))
> -		xe_hw_engine_handle_irq(hwe, GT_RENDER_USER_INTERRUPT);
> +	if (memirq_received(memirq, status, ilog2(GT_MI_USER_INTERRUPT), hwe->name))
> +		xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
>  }
>  
>  static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *status,
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation