From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
Shekhar Chauhan <shekhar.chauhan@intel.com>,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Tejas Upadhyay <tejas.upadhyay@intel.com>
Subject: [PATCH v3 11/24] drm/xe/nvl: Define NVL-S platform
Date: Thu, 16 Oct 2025 19:26:30 -0700 [thread overview]
Message-ID: <20251016-xe3p-v3-11-3dd173a3097a@intel.com> (raw)
In-Reply-To: <20251016-xe3p-v3-0-3dd173a3097a@intel.com>
From: Matt Roper <matthew.d.roper@intel.com>
Provide the basic platform definitions and PCI IDs for NVL-S.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Fix rebase on flags moving to the device descriptor (Gustavo)
---
drivers/gpu/drm/xe/xe_pci.c | 12 ++++++++++++
drivers/gpu/drm/xe/xe_platform_types.h | 1 +
include/drm/intel/pciids.h | 9 +++++++++
3 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index fac46178cebba..0546442e2a631 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -377,6 +377,17 @@ static const struct xe_device_desc ptl_desc = {
.vm_max_level = 4,
};
+static const struct xe_device_desc nvls_desc = {
+ PLATFORM(NOVALAKE_S),
+ .dma_mask_size = 46,
+ .has_display = true,
+ .has_flat_ccs = 1,
+ .max_gt_per_tile = 2,
+ .require_force_probe = true,
+ .va_bits = 48,
+ .vm_max_level = 4,
+};
+
#undef PLATFORM
__diag_pop();
@@ -405,6 +416,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
+ INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
{ }
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index 3e332214c7bb4..78286285c2495 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -24,6 +24,7 @@ enum xe_platform {
XE_LUNARLAKE,
XE_BATTLEMAGE,
XE_PANTHERLAKE,
+ XE_NOVALAKE_S,
};
enum xe_subplatform {
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 452c1de606ff2..13c592e1a28c7 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -887,4 +887,13 @@
MACRO__(0xFD80, ## __VA_ARGS__), \
MACRO__(0xFD81, ## __VA_ARGS__)
+/* NVL-S */
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+ MACRO__(0xD740, ## __VA_ARGS__), \
+ MACRO__(0xD741, ## __VA_ARGS__), \
+ MACRO__(0xD742, ## __VA_ARGS__), \
+ MACRO__(0xD743, ## __VA_ARGS__), \
+ MACRO__(0xD744, ## __VA_ARGS__), \
+ MACRO__(0xD745, ## __VA_ARGS__)
+
#endif /* __PCIIDS_H__ */
--
2.51.0
next prev parent reply other threads:[~2025-10-17 2:27 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 2:26 [PATCH v3 00/24] drm/xe: Add Xe3p support Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 01/24] drm/xe/xe3: Add support for graphics IP versions 30.04 & 30.05 Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 02/24] drm/xe/xe3p: Add support for media IP versions 35.00 & 35.03 Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 03/24] drm/xe: Drop CTC_MODE register read Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 04/24] drm/xe: Add GT_VER() to check version specific to gt type Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 05/24] drm/xe/xe3p_lpm: Skip disabling NOA on unsupported IPs Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 06/24] drm/xe/xe3p_lpm: Handle MCR steering Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 07/24] drm/xe/xe3p: Stop programming RCU_MODE's fixed slice mode setting Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 08/24] drm/xe/xe3p: Determine service copy availability from fuse Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 09/24] drm/xe: Dump CURRENT_LRCA register Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 10/24] drm/xe/xe3p: Dump CSMQDEBUG register Lucas De Marchi
2025-10-17 15:55 ` Matt Roper
2025-10-21 16:02 ` Summers, Stuart
2025-10-17 2:26 ` Lucas De Marchi [this message]
2025-10-17 13:05 ` [PATCH v3 11/24] drm/xe/nvl: Define NVL-S platform Gustavo Sousa
2025-10-17 2:26 ` [PATCH v3 12/24] drm/xe/nvls: Define GuC firmware for NVL-S Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 13/24] drm/xe/nvls: Attach MOCS table " Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 14/24] drm/xe/xe3p_xpc: Add Xe3p_XPC IP definition Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 15/24] drm/xe/xe3p_xpc: Add L3 bank mask Lucas De Marchi
2025-10-17 17:51 ` Matt Roper
2025-10-18 3:18 ` Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 16/24] drm/xe/xe3p_xpc: Add MCR steering Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 17/24] drm/xe/irq: Rename fuse mask variables Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 18/24] drm/xe/irq: Split irq mask per engine class Lucas De Marchi
2025-10-17 16:03 ` Matt Roper
2025-10-17 2:26 ` [PATCH v3 19/24] drm/xe/irq: Rename bits used with all engines Lucas De Marchi
2025-10-17 16:05 ` Matt Roper
2025-10-17 2:26 ` [PATCH v3 20/24] drm/xe/irq: Check fuse mask for media engines Lucas De Marchi
2025-10-17 16:07 ` Matt Roper
2025-10-17 2:26 ` [PATCH v3 21/24] drm/xe/xe3p_xpc: Add support for compute walker for non-MSIx Lucas De Marchi
2025-10-17 17:04 ` Matt Roper
2025-10-17 2:26 ` [PATCH v3 22/24] drm/xe/xe3p_xpc: Skip compression tuning on platforms without flatccs Lucas De Marchi
2025-10-17 2:26 ` [PATCH v3 23/24] drm/xe/xe3p_xpc: Setup PAT table Lucas De Marchi
2025-10-17 11:05 ` Ville Syrjälä
2025-10-17 17:18 ` Matt Roper
2025-10-17 18:09 ` Ville Syrjälä
2025-10-17 20:33 ` Matt Roper
2025-10-17 2:26 ` [PATCH v3 24/24] drm/xe/xe3p: Add xe3p EU stall data format Lucas De Marchi
2025-10-17 2:35 ` ✗ CI.checkpatch: warning for drm/xe: Add Xe3p support (rev3) Patchwork
2025-10-17 2:36 ` ✓ CI.KUnit: success " Patchwork
2025-10-17 3:23 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-18 1:56 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-19 2:55 ` [PATCH v3 00/24] drm/xe: Add Xe3p support Lucas De Marchi
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