[PATCH 0/5] VRAM health check + CCS fix

[PATCH 0/5] VRAM health check + CCS fix

[Matthew Auld]

Add a basic VRAM health check routine, which does some basic sanity
checking on the last VRAM page. This could be extended in the future.
This seems to reproduce the same CCS issue as Linus, on my b570.

This also picks up the fix from Linus. I went with leaving it as-is,
but that means we need to fixup the identity mapping to support 4K
pages for the tail part of usable VRAM.

It doesn't look like anything in our CI actually has the CCS alignment
issue present, so merging the fix from Linus without the identity map
changes likely shouldn't trigger any asserts, if that does end up
coming in via another tree, AFAICT.

-- 
2.55.0

[PATCH 1/5] drm/xe/migrate: support 4K PTEs for identity map

[Matthew Auld]

When VRAM limit (usable_size) is no longer 2M aligned (e.g. because flat
CCS storage size rounds it down to 4K), we must map the tail of the
identity mapping using 4K pages.

This removes the 2M alignment assert (which pops) and introduces a 4K
fallback in the identity map programming loop to handle the last 2M
chunk of usable VRAM.

Might be possible to skip backporting this. The assert that pops should
be harmless and is only on debug builds plus only a stray write would
hit CCS, which technically get mapped.

Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_migrate.c | 57 +++++++++++++++++++++------------
 1 file changed, 37 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 75b83687f1b5..0bf000d7c901 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -87,7 +87,7 @@ struct xe_migrate {
 #define MAX_PREEMPTDISABLE_TRANSFER SZ_8M /* Around 1ms. */
 #define MAX_CCS_LIMITED_TRANSFER SZ_4M /* XE_PAGE_SIZE * (FIELD_MAX(XE2_CCS_SIZE_MASK) + 1) */
 #define NUM_KERNEL_PDE 15
-#define NUM_PT_SLOTS 32
+#define NUM_PT_SLOTS 48
 #define LEVEL0_PAGE_TABLE_ENCODE_SIZE SZ_2M
 #define MAX_NUM_PTE 512
 #define IDENTITY_OFFSET 256ULL
@@ -163,22 +163,20 @@ static u64 xe_migrate_vram_ofs(struct xe_device *xe, u64 addr, bool is_comp_pte)
 }
 
 static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm, struct xe_bo *bo,
-					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs)
+					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs,
+					u64 pt_4k_ofs)
 {
 	struct xe_vram_region *vram = xe->mem.vram;
 	resource_size_t dpa_base = xe_vram_region_dpa_base(vram);
 	u64 pos, ofs, flags;
 	u64 entry;
-	/* XXX: Unclear if this should be usable_size? */
-	u64 vram_limit = xe_vram_region_actual_physical_size(vram) + dpa_base;
+	u64 vram_limit = xe_vram_region_usable_size(vram) + dpa_base;
 	u32 level = 2;
 
 	ofs = map_ofs + XE_PAGE_SIZE * level + vram_offset * 8;
 	flags = vm->pt_ops->pte_encode_addr(xe, 0, pat_index, level,
 					    true, 0);
 
-	xe_assert(xe, IS_ALIGNED(xe_vram_region_usable_size(vram), SZ_2M));
-
 	/*
 	 * Use 1GB pages when possible, last chunk always use 2M
 	 * pages as mixing reserved memory (stolen, WOCPM) with a single
@@ -196,8 +194,24 @@ static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm,
 							    true, 0);
 
 			for (ofs = pt_2m_ofs; pos < vram_limit;
-			     pos += SZ_2M, ofs += 8)
+			     pos += SZ_2M, ofs += 8) {
+				if (pos + SZ_2M > vram_limit) {
+					entry = vm->pt_ops->pde_encode_bo(bo, pt_4k_ofs);
+					xe_map_wr(xe, &bo->vmap, ofs, u64, entry);
+
+					flags = vm->pt_ops->pte_encode_addr(xe, 0,
+									    pat_index,
+									    level - 2,
+									    true, 0);
+
+					for (ofs = pt_4k_ofs; pos < vram_limit;
+					     pos += SZ_4K, ofs += 8)
+						xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
+					break;
+				}
+
 				xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
+			}
 			break;	/* Ensure pos == vram_limit assert correct */
 		}
 
@@ -242,16 +256,17 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 	u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
 	u8 id = tile->id;
 	u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
-#define VRAM_IDENTITY_MAP_COUNT	2
-	u32 num_setup = num_level + VRAM_IDENTITY_MAP_COUNT;
-#undef VRAM_IDENTITY_MAP_COUNT
+#define VRAM_IDENTITY_MAP_PT_COUNT	4
+	u32 num_setup = num_level + VRAM_IDENTITY_MAP_PT_COUNT;
+#undef VRAM_IDENTITY_MAP_PT_COUNT
 	u32 map_ofs, level, i;
 	struct xe_bo *bo = m->pt_bo, *batch = tile->mem.kernel_bb_pool->bo;
-	u64 entry, pt29_ofs;
+	u64 entry;
 
-	/* PT30 & PT31 reserved for 2M identity map */
-	pt29_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
-	entry = vm->pt_ops->pde_encode_bo(bo, pt29_ofs);
+	/* PT44..PT47 reserved for 4K and 2M identity map */
+	u64 l1_pt_ofs = xe_bo_size(bo) - 5 * XE_PAGE_SIZE;
+
+	entry = vm->pt_ops->pde_encode_bo(bo, l1_pt_ofs);
 	xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
 
 	map_ofs = (num_entries - num_setup) * XE_PAGE_SIZE;
@@ -347,11 +362,12 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 
 	/* Identity map the entire vram at 256GiB offset */
 	if (IS_DGFX(xe)) {
-		u64 pt30_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
+		u64 pt46_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
 		resource_size_t actual_phy_size = xe_vram_region_actual_physical_size(xe->mem.vram);
 
+		u64 pt44_ofs = xe_bo_size(bo) - 4 * XE_PAGE_SIZE;
 		xe_migrate_program_identity(xe, vm, bo, map_ofs, IDENTITY_OFFSET,
-					    pat_index, pt30_ofs);
+					    pat_index, pt46_ofs, pt44_ofs);
 		xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET) * SZ_1G);
 
 		/*
@@ -362,12 +378,13 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 			u16 comp_pat_index = xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION);
 			u64 vram_offset = IDENTITY_OFFSET +
 				DIV_ROUND_UP_ULL(actual_phy_size, SZ_1G);
-			u64 pt31_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
+			u64 pt47_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
 
 			xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET -
 							  IDENTITY_OFFSET / 2) * SZ_1G);
+			u64 pt45_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
 			xe_migrate_program_identity(xe, vm, bo, map_ofs, vram_offset,
-						    comp_pat_index, pt31_ofs);
+						    comp_pat_index, pt47_ofs, pt45_ofs);
 		}
 	}
 
@@ -381,8 +398,8 @@ static void xe_migrate_suballoc_manager_init(struct xe_migrate *m, u32 map_ofs)
 	 * Example layout created above, with root level = 3:
 	 * [PT0...PT7]: kernel PT's for copy/clear; 64 or 4KiB PTE's
 	 * [PT8]: Kernel PT for VM_BIND, 4 KiB PTE's
-	 * [PT9...PT26]: Userspace PT's for VM_BIND, 4 KiB PTE's
-	 * [PT27 = PDE 0] [PT28 = PDE 1] [PT29 = PDE 2] [PT30 & PT31 = 2M vram identity map]
+	 * [PT9...PT40]: Userspace PT's for VM_BIND, 4 KiB PTE's
+	 * [PT41 = PDE 0] [PT44...PT47 = 4K and 2M vram identity maps]
 	 *
 	 * This makes the lowest part of the VM point to the pagetables.
 	 * Hence the lowest 2M in the vm should point to itself, with a few writes
-- 
2.55.0

Re: [PATCH 1/5] drm/xe/migrate: support 4K PTEs for identity map

[Matthew Brost]

On Fri, Aug 28, 2026 at 04:14:07PM +0100, Matthew Auld wrote:
> When VRAM limit (usable_size) is no longer 2M aligned (e.g. because flat
> CCS storage size rounds it down to 4K), we must map the tail of the
> identity mapping using 4K pages.
> 
> This removes the 2M alignment assert (which pops) and introduces a 4K
> fallback in the identity map programming loop to handle the last 2M
> chunk of usable VRAM.
> 
> Might be possible to skip backporting this. The assert that pops should
> be harmless and is only on debug builds plus only a stray write would
> hit CCS, which technically get mapped.
> 

This LGTM, better than what I had in mind. One question though.

> Assisted-by: Gemini:gemini-3.1-pro-preview
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_migrate.c | 57 +++++++++++++++++++++------------
>  1 file changed, 37 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 75b83687f1b5..0bf000d7c901 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -87,7 +87,7 @@ struct xe_migrate {
>  #define MAX_PREEMPTDISABLE_TRANSFER SZ_8M /* Around 1ms. */
>  #define MAX_CCS_LIMITED_TRANSFER SZ_4M /* XE_PAGE_SIZE * (FIELD_MAX(XE2_CCS_SIZE_MASK) + 1) */
>  #define NUM_KERNEL_PDE 15
> -#define NUM_PT_SLOTS 32
> +#define NUM_PT_SLOTS 48

Why this change? Can't we just steal more PTs from user-space VM binds?
Did testing show that this was actually a problem?

Also, in general, power-of-two values are preferred.

Eventually, we'll be able to drop the need for these PTs once CPU binds
land as well [1].

Not blocker.

Matt

[1] https://patchwork.freedesktop.org/series/149888/

>  #define LEVEL0_PAGE_TABLE_ENCODE_SIZE SZ_2M
>  #define MAX_NUM_PTE 512
>  #define IDENTITY_OFFSET 256ULL
> @@ -163,22 +163,20 @@ static u64 xe_migrate_vram_ofs(struct xe_device *xe, u64 addr, bool is_comp_pte)
>  }
>  
>  static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm, struct xe_bo *bo,
> -					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs)
> +					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs,
> +					u64 pt_4k_ofs)
>  {
>  	struct xe_vram_region *vram = xe->mem.vram;
>  	resource_size_t dpa_base = xe_vram_region_dpa_base(vram);
>  	u64 pos, ofs, flags;
>  	u64 entry;
> -	/* XXX: Unclear if this should be usable_size? */
> -	u64 vram_limit = xe_vram_region_actual_physical_size(vram) + dpa_base;
> +	u64 vram_limit = xe_vram_region_usable_size(vram) + dpa_base;
>  	u32 level = 2;
>  
>  	ofs = map_ofs + XE_PAGE_SIZE * level + vram_offset * 8;
>  	flags = vm->pt_ops->pte_encode_addr(xe, 0, pat_index, level,
>  					    true, 0);
>  
> -	xe_assert(xe, IS_ALIGNED(xe_vram_region_usable_size(vram), SZ_2M));
> -
>  	/*
>  	 * Use 1GB pages when possible, last chunk always use 2M
>  	 * pages as mixing reserved memory (stolen, WOCPM) with a single
> @@ -196,8 +194,24 @@ static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm,
>  							    true, 0);
>  
>  			for (ofs = pt_2m_ofs; pos < vram_limit;
> -			     pos += SZ_2M, ofs += 8)
> +			     pos += SZ_2M, ofs += 8) {
> +				if (pos + SZ_2M > vram_limit) {
> +					entry = vm->pt_ops->pde_encode_bo(bo, pt_4k_ofs);
> +					xe_map_wr(xe, &bo->vmap, ofs, u64, entry);
> +
> +					flags = vm->pt_ops->pte_encode_addr(xe, 0,
> +									    pat_index,
> +									    level - 2,
> +									    true, 0);
> +
> +					for (ofs = pt_4k_ofs; pos < vram_limit;
> +					     pos += SZ_4K, ofs += 8)
> +						xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
> +					break;
> +				}
> +
>  				xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
> +			}
>  			break;	/* Ensure pos == vram_limit assert correct */
>  		}
>  
> @@ -242,16 +256,17 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
>  	u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
>  	u8 id = tile->id;
>  	u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
> -#define VRAM_IDENTITY_MAP_COUNT	2
> -	u32 num_setup = num_level + VRAM_IDENTITY_MAP_COUNT;
> -#undef VRAM_IDENTITY_MAP_COUNT
> +#define VRAM_IDENTITY_MAP_PT_COUNT	4
> +	u32 num_setup = num_level + VRAM_IDENTITY_MAP_PT_COUNT;
> +#undef VRAM_IDENTITY_MAP_PT_COUNT
>  	u32 map_ofs, level, i;
>  	struct xe_bo *bo = m->pt_bo, *batch = tile->mem.kernel_bb_pool->bo;
> -	u64 entry, pt29_ofs;
> +	u64 entry;
>  
> -	/* PT30 & PT31 reserved for 2M identity map */
> -	pt29_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
> -	entry = vm->pt_ops->pde_encode_bo(bo, pt29_ofs);
> +	/* PT44..PT47 reserved for 4K and 2M identity map */
> +	u64 l1_pt_ofs = xe_bo_size(bo) - 5 * XE_PAGE_SIZE;
> +
> +	entry = vm->pt_ops->pde_encode_bo(bo, l1_pt_ofs);
>  	xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
>  
>  	map_ofs = (num_entries - num_setup) * XE_PAGE_SIZE;
> @@ -347,11 +362,12 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
>  
>  	/* Identity map the entire vram at 256GiB offset */
>  	if (IS_DGFX(xe)) {
> -		u64 pt30_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
> +		u64 pt46_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
>  		resource_size_t actual_phy_size = xe_vram_region_actual_physical_size(xe->mem.vram);
>  
> +		u64 pt44_ofs = xe_bo_size(bo) - 4 * XE_PAGE_SIZE;
>  		xe_migrate_program_identity(xe, vm, bo, map_ofs, IDENTITY_OFFSET,
> -					    pat_index, pt30_ofs);
> +					    pat_index, pt46_ofs, pt44_ofs);
>  		xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET) * SZ_1G);
>  
>  		/*
> @@ -362,12 +378,13 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
>  			u16 comp_pat_index = xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION);
>  			u64 vram_offset = IDENTITY_OFFSET +
>  				DIV_ROUND_UP_ULL(actual_phy_size, SZ_1G);
> -			u64 pt31_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
> +			u64 pt47_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
>  
>  			xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET -
>  							  IDENTITY_OFFSET / 2) * SZ_1G);
> +			u64 pt45_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
>  			xe_migrate_program_identity(xe, vm, bo, map_ofs, vram_offset,
> -						    comp_pat_index, pt31_ofs);
> +						    comp_pat_index, pt47_ofs, pt45_ofs);
>  		}
>  	}
>  
> @@ -381,8 +398,8 @@ static void xe_migrate_suballoc_manager_init(struct xe_migrate *m, u32 map_ofs)
>  	 * Example layout created above, with root level = 3:
>  	 * [PT0...PT7]: kernel PT's for copy/clear; 64 or 4KiB PTE's
>  	 * [PT8]: Kernel PT for VM_BIND, 4 KiB PTE's
> -	 * [PT9...PT26]: Userspace PT's for VM_BIND, 4 KiB PTE's
> -	 * [PT27 = PDE 0] [PT28 = PDE 1] [PT29 = PDE 2] [PT30 & PT31 = 2M vram identity map]
> +	 * [PT9...PT40]: Userspace PT's for VM_BIND, 4 KiB PTE's
> +	 * [PT41 = PDE 0] [PT44...PT47 = 4K and 2M vram identity maps]
>  	 *
>  	 * This makes the lowest part of the VM point to the pagetables.
>  	 * Hence the lowest 2M in the vm should point to itself, with a few writes
> -- 
> 2.55.0
> 

Re: [PATCH 1/5] drm/xe/migrate: support 4K PTEs for identity map

[Matthew Auld]

On 28/08/2026 20:46, Matthew Brost wrote:
> On Fri, Aug 28, 2026 at 04:14:07PM +0100, Matthew Auld wrote:
>> When VRAM limit (usable_size) is no longer 2M aligned (e.g. because flat
>> CCS storage size rounds it down to 4K), we must map the tail of the
>> identity mapping using 4K pages.
>>
>> This removes the 2M alignment assert (which pops) and introduces a 4K
>> fallback in the identity map programming loop to handle the last 2M
>> chunk of usable VRAM.
>>
>> Might be possible to skip backporting this. The assert that pops should
>> be harmless and is only on debug builds plus only a stray write would
>> hit CCS, which technically get mapped.
>>
> 
> This LGTM, better than what I had in mind. One question though.
> 
>> Assisted-by: Gemini:gemini-3.1-pro-preview
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_migrate.c | 57 +++++++++++++++++++++------------
>>   1 file changed, 37 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
>> index 75b83687f1b5..0bf000d7c901 100644
>> --- a/drivers/gpu/drm/xe/xe_migrate.c
>> +++ b/drivers/gpu/drm/xe/xe_migrate.c
>> @@ -87,7 +87,7 @@ struct xe_migrate {
>>   #define MAX_PREEMPTDISABLE_TRANSFER SZ_8M /* Around 1ms. */
>>   #define MAX_CCS_LIMITED_TRANSFER SZ_4M /* XE_PAGE_SIZE * (FIELD_MAX(XE2_CCS_SIZE_MASK) + 1) */
>>   #define NUM_KERNEL_PDE 15
>> -#define NUM_PT_SLOTS 32
>> +#define NUM_PT_SLOTS 48
> 
> Why this change? Can't we just steal more PTs from user-space VM binds?
> Did testing show that this was actually a problem?

Yeah, my local v1 did exactly that. But I got doubts since it felt a bit 
scary taking away slots from userspace and wasn't sure if there could be 
some impact.

Can revert back to that approach if you prefer? It should be somewhere 
in my reflog.

> 
> Also, in general, power-of-two values are preferred.

Yeah, I think it was just the assert:

/* Must be a multiple of 64K to support all platforms */
BUILD_BUG_ON(NUM_PT_SLOTS * XE_PAGE_SIZE % SZ_64K);

So just went with the minimal to satisfy that. Will make this a 
power-of-two instead if preferred.

> 
> Eventually, we'll be able to drop the need for these PTs once CPU binds
> land as well [1].
> 
> Not blocker.
> 
> Matt
> 
> [1] https://patchwork.freedesktop.org/series/149888/
> 
>>   #define LEVEL0_PAGE_TABLE_ENCODE_SIZE SZ_2M
>>   #define MAX_NUM_PTE 512
>>   #define IDENTITY_OFFSET 256ULL
>> @@ -163,22 +163,20 @@ static u64 xe_migrate_vram_ofs(struct xe_device *xe, u64 addr, bool is_comp_pte)
>>   }
>>   
>>   static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm, struct xe_bo *bo,
>> -					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs)
>> +					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs,
>> +					u64 pt_4k_ofs)
>>   {
>>   	struct xe_vram_region *vram = xe->mem.vram;
>>   	resource_size_t dpa_base = xe_vram_region_dpa_base(vram);
>>   	u64 pos, ofs, flags;
>>   	u64 entry;
>> -	/* XXX: Unclear if this should be usable_size? */
>> -	u64 vram_limit = xe_vram_region_actual_physical_size(vram) + dpa_base;
>> +	u64 vram_limit = xe_vram_region_usable_size(vram) + dpa_base;
>>   	u32 level = 2;
>>   
>>   	ofs = map_ofs + XE_PAGE_SIZE * level + vram_offset * 8;
>>   	flags = vm->pt_ops->pte_encode_addr(xe, 0, pat_index, level,
>>   					    true, 0);
>>   
>> -	xe_assert(xe, IS_ALIGNED(xe_vram_region_usable_size(vram), SZ_2M));
>> -
>>   	/*
>>   	 * Use 1GB pages when possible, last chunk always use 2M
>>   	 * pages as mixing reserved memory (stolen, WOCPM) with a single
>> @@ -196,8 +194,24 @@ static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm,
>>   							    true, 0);
>>   
>>   			for (ofs = pt_2m_ofs; pos < vram_limit;
>> -			     pos += SZ_2M, ofs += 8)
>> +			     pos += SZ_2M, ofs += 8) {
>> +				if (pos + SZ_2M > vram_limit) {
>> +					entry = vm->pt_ops->pde_encode_bo(bo, pt_4k_ofs);
>> +					xe_map_wr(xe, &bo->vmap, ofs, u64, entry);
>> +
>> +					flags = vm->pt_ops->pte_encode_addr(xe, 0,
>> +									    pat_index,
>> +									    level - 2,
>> +									    true, 0);
>> +
>> +					for (ofs = pt_4k_ofs; pos < vram_limit;
>> +					     pos += SZ_4K, ofs += 8)
>> +						xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
>> +					break;
>> +				}
>> +
>>   				xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
>> +			}
>>   			break;	/* Ensure pos == vram_limit assert correct */
>>   		}
>>   
>> @@ -242,16 +256,17 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
>>   	u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
>>   	u8 id = tile->id;
>>   	u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
>> -#define VRAM_IDENTITY_MAP_COUNT	2
>> -	u32 num_setup = num_level + VRAM_IDENTITY_MAP_COUNT;
>> -#undef VRAM_IDENTITY_MAP_COUNT
>> +#define VRAM_IDENTITY_MAP_PT_COUNT	4
>> +	u32 num_setup = num_level + VRAM_IDENTITY_MAP_PT_COUNT;
>> +#undef VRAM_IDENTITY_MAP_PT_COUNT
>>   	u32 map_ofs, level, i;
>>   	struct xe_bo *bo = m->pt_bo, *batch = tile->mem.kernel_bb_pool->bo;
>> -	u64 entry, pt29_ofs;
>> +	u64 entry;
>>   
>> -	/* PT30 & PT31 reserved for 2M identity map */
>> -	pt29_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
>> -	entry = vm->pt_ops->pde_encode_bo(bo, pt29_ofs);
>> +	/* PT44..PT47 reserved for 4K and 2M identity map */
>> +	u64 l1_pt_ofs = xe_bo_size(bo) - 5 * XE_PAGE_SIZE;
>> +
>> +	entry = vm->pt_ops->pde_encode_bo(bo, l1_pt_ofs);
>>   	xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
>>   
>>   	map_ofs = (num_entries - num_setup) * XE_PAGE_SIZE;
>> @@ -347,11 +362,12 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
>>   
>>   	/* Identity map the entire vram at 256GiB offset */
>>   	if (IS_DGFX(xe)) {
>> -		u64 pt30_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
>> +		u64 pt46_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
>>   		resource_size_t actual_phy_size = xe_vram_region_actual_physical_size(xe->mem.vram);
>>   
>> +		u64 pt44_ofs = xe_bo_size(bo) - 4 * XE_PAGE_SIZE;
>>   		xe_migrate_program_identity(xe, vm, bo, map_ofs, IDENTITY_OFFSET,
>> -					    pat_index, pt30_ofs);
>> +					    pat_index, pt46_ofs, pt44_ofs);
>>   		xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET) * SZ_1G);
>>   
>>   		/*
>> @@ -362,12 +378,13 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
>>   			u16 comp_pat_index = xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION);
>>   			u64 vram_offset = IDENTITY_OFFSET +
>>   				DIV_ROUND_UP_ULL(actual_phy_size, SZ_1G);
>> -			u64 pt31_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
>> +			u64 pt47_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
>>   
>>   			xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET -
>>   							  IDENTITY_OFFSET / 2) * SZ_1G);
>> +			u64 pt45_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
>>   			xe_migrate_program_identity(xe, vm, bo, map_ofs, vram_offset,
>> -						    comp_pat_index, pt31_ofs);
>> +						    comp_pat_index, pt47_ofs, pt45_ofs);
>>   		}
>>   	}
>>   
>> @@ -381,8 +398,8 @@ static void xe_migrate_suballoc_manager_init(struct xe_migrate *m, u32 map_ofs)
>>   	 * Example layout created above, with root level = 3:
>>   	 * [PT0...PT7]: kernel PT's for copy/clear; 64 or 4KiB PTE's
>>   	 * [PT8]: Kernel PT for VM_BIND, 4 KiB PTE's
>> -	 * [PT9...PT26]: Userspace PT's for VM_BIND, 4 KiB PTE's
>> -	 * [PT27 = PDE 0] [PT28 = PDE 1] [PT29 = PDE 2] [PT30 & PT31 = 2M vram identity map]
>> +	 * [PT9...PT40]: Userspace PT's for VM_BIND, 4 KiB PTE's
>> +	 * [PT41 = PDE 0] [PT44...PT47 = 4K and 2M vram identity maps]
>>   	 *
>>   	 * This makes the lowest part of the VM point to the pagetables.
>>   	 * Hence the lowest 2M in the vm should point to itself, with a few writes
>> -- 
>> 2.55.0
>>

Re: [PATCH 1/5] drm/xe/migrate: support 4K PTEs for identity map

[Matthew Brost]

On Tue, Sep 01, 2026 at 09:48:14AM +0100, Matthew Auld wrote:
> On 28/08/2026 20:46, Matthew Brost wrote:
> > On Fri, Aug 28, 2026 at 04:14:07PM +0100, Matthew Auld wrote:
> > > When VRAM limit (usable_size) is no longer 2M aligned (e.g. because flat
> > > CCS storage size rounds it down to 4K), we must map the tail of the
> > > identity mapping using 4K pages.
> > > 
> > > This removes the 2M alignment assert (which pops) and introduces a 4K
> > > fallback in the identity map programming loop to handle the last 2M
> > > chunk of usable VRAM.
> > > 
> > > Might be possible to skip backporting this. The assert that pops should
> > > be harmless and is only on debug builds plus only a stray write would
> > > hit CCS, which technically get mapped.
> > > 
> > 
> > This LGTM, better than what I had in mind. One question though.
> > 
> > > Assisted-by: Gemini:gemini-3.1-pro-preview
> > > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > > Cc: Matthew Brost <matthew.brost@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >   drivers/gpu/drm/xe/xe_migrate.c | 57 +++++++++++++++++++++------------
> > >   1 file changed, 37 insertions(+), 20 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> > > index 75b83687f1b5..0bf000d7c901 100644
> > > --- a/drivers/gpu/drm/xe/xe_migrate.c
> > > +++ b/drivers/gpu/drm/xe/xe_migrate.c
> > > @@ -87,7 +87,7 @@ struct xe_migrate {
> > >   #define MAX_PREEMPTDISABLE_TRANSFER SZ_8M /* Around 1ms. */
> > >   #define MAX_CCS_LIMITED_TRANSFER SZ_4M /* XE_PAGE_SIZE * (FIELD_MAX(XE2_CCS_SIZE_MASK) + 1) */
> > >   #define NUM_KERNEL_PDE 15
> > > -#define NUM_PT_SLOTS 32
> > > +#define NUM_PT_SLOTS 48
> > 
> > Why this change? Can't we just steal more PTs from user-space VM binds?
> > Did testing show that this was actually a problem?
> 
> Yeah, my local v1 did exactly that. But I got doubts since it felt a bit
> scary taking away slots from userspace and wasn't sure if there could be
> some impact.
> 

Yes, it possible large binds return -ENOBUFS eariler the more PTs one steals.

> Can revert back to that approach if you prefer? It should be somewhere in my
> reflog.

I'm fine either way as CI is passing which it is. We can tweak in place
as needed into follow up.

With that:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> 
> > 
> > Also, in general, power-of-two values are preferred.
> 
> Yeah, I think it was just the assert:
> 
> /* Must be a multiple of 64K to support all platforms */
> BUILD_BUG_ON(NUM_PT_SLOTS * XE_PAGE_SIZE % SZ_64K);
> 
> So just went with the minimal to satisfy that. Will make this a power-of-two
> instead if preferred.
> 
> > 
> > Eventually, we'll be able to drop the need for these PTs once CPU binds
> > land as well [1].
> > 
> > Not blocker.
> > 
> > Matt
> > 
> > [1] https://patchwork.freedesktop.org/series/149888/
> > 
> > >   #define LEVEL0_PAGE_TABLE_ENCODE_SIZE SZ_2M
> > >   #define MAX_NUM_PTE 512
> > >   #define IDENTITY_OFFSET 256ULL
> > > @@ -163,22 +163,20 @@ static u64 xe_migrate_vram_ofs(struct xe_device *xe, u64 addr, bool is_comp_pte)
> > >   }
> > >   static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm, struct xe_bo *bo,
> > > -					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs)
> > > +					u64 map_ofs, u64 vram_offset, u16 pat_index, u64 pt_2m_ofs,
> > > +					u64 pt_4k_ofs)
> > >   {
> > >   	struct xe_vram_region *vram = xe->mem.vram;
> > >   	resource_size_t dpa_base = xe_vram_region_dpa_base(vram);
> > >   	u64 pos, ofs, flags;
> > >   	u64 entry;
> > > -	/* XXX: Unclear if this should be usable_size? */
> > > -	u64 vram_limit = xe_vram_region_actual_physical_size(vram) + dpa_base;
> > > +	u64 vram_limit = xe_vram_region_usable_size(vram) + dpa_base;
> > >   	u32 level = 2;
> > >   	ofs = map_ofs + XE_PAGE_SIZE * level + vram_offset * 8;
> > >   	flags = vm->pt_ops->pte_encode_addr(xe, 0, pat_index, level,
> > >   					    true, 0);
> > > -	xe_assert(xe, IS_ALIGNED(xe_vram_region_usable_size(vram), SZ_2M));
> > > -
> > >   	/*
> > >   	 * Use 1GB pages when possible, last chunk always use 2M
> > >   	 * pages as mixing reserved memory (stolen, WOCPM) with a single
> > > @@ -196,8 +194,24 @@ static void xe_migrate_program_identity(struct xe_device *xe, struct xe_vm *vm,
> > >   							    true, 0);
> > >   			for (ofs = pt_2m_ofs; pos < vram_limit;
> > > -			     pos += SZ_2M, ofs += 8)
> > > +			     pos += SZ_2M, ofs += 8) {
> > > +				if (pos + SZ_2M > vram_limit) {
> > > +					entry = vm->pt_ops->pde_encode_bo(bo, pt_4k_ofs);
> > > +					xe_map_wr(xe, &bo->vmap, ofs, u64, entry);
> > > +
> > > +					flags = vm->pt_ops->pte_encode_addr(xe, 0,
> > > +									    pat_index,
> > > +									    level - 2,
> > > +									    true, 0);
> > > +
> > > +					for (ofs = pt_4k_ofs; pos < vram_limit;
> > > +					     pos += SZ_4K, ofs += 8)
> > > +						xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
> > > +					break;
> > > +				}
> > > +
> > >   				xe_map_wr(xe, &bo->vmap, ofs, u64, pos | flags);
> > > +			}
> > >   			break;	/* Ensure pos == vram_limit assert correct */
> > >   		}
> > > @@ -242,16 +256,17 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
> > >   	u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
> > >   	u8 id = tile->id;
> > >   	u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
> > > -#define VRAM_IDENTITY_MAP_COUNT	2
> > > -	u32 num_setup = num_level + VRAM_IDENTITY_MAP_COUNT;
> > > -#undef VRAM_IDENTITY_MAP_COUNT
> > > +#define VRAM_IDENTITY_MAP_PT_COUNT	4
> > > +	u32 num_setup = num_level + VRAM_IDENTITY_MAP_PT_COUNT;
> > > +#undef VRAM_IDENTITY_MAP_PT_COUNT
> > >   	u32 map_ofs, level, i;
> > >   	struct xe_bo *bo = m->pt_bo, *batch = tile->mem.kernel_bb_pool->bo;
> > > -	u64 entry, pt29_ofs;
> > > +	u64 entry;
> > > -	/* PT30 & PT31 reserved for 2M identity map */
> > > -	pt29_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
> > > -	entry = vm->pt_ops->pde_encode_bo(bo, pt29_ofs);
> > > +	/* PT44..PT47 reserved for 4K and 2M identity map */
> > > +	u64 l1_pt_ofs = xe_bo_size(bo) - 5 * XE_PAGE_SIZE;
> > > +
> > > +	entry = vm->pt_ops->pde_encode_bo(bo, l1_pt_ofs);
> > >   	xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
> > >   	map_ofs = (num_entries - num_setup) * XE_PAGE_SIZE;
> > > @@ -347,11 +362,12 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
> > >   	/* Identity map the entire vram at 256GiB offset */
> > >   	if (IS_DGFX(xe)) {
> > > -		u64 pt30_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
> > > +		u64 pt46_ofs = xe_bo_size(bo) - 2 * XE_PAGE_SIZE;
> > >   		resource_size_t actual_phy_size = xe_vram_region_actual_physical_size(xe->mem.vram);
> > > +		u64 pt44_ofs = xe_bo_size(bo) - 4 * XE_PAGE_SIZE;
> > >   		xe_migrate_program_identity(xe, vm, bo, map_ofs, IDENTITY_OFFSET,
> > > -					    pat_index, pt30_ofs);
> > > +					    pat_index, pt46_ofs, pt44_ofs);
> > >   		xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET) * SZ_1G);
> > >   		/*
> > > @@ -362,12 +378,13 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
> > >   			u16 comp_pat_index = xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION);
> > >   			u64 vram_offset = IDENTITY_OFFSET +
> > >   				DIV_ROUND_UP_ULL(actual_phy_size, SZ_1G);
> > > -			u64 pt31_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
> > > +			u64 pt47_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
> > >   			xe_assert(xe, actual_phy_size <= (MAX_NUM_PTE - IDENTITY_OFFSET -
> > >   							  IDENTITY_OFFSET / 2) * SZ_1G);
> > > +			u64 pt45_ofs = xe_bo_size(bo) - 3 * XE_PAGE_SIZE;
> > >   			xe_migrate_program_identity(xe, vm, bo, map_ofs, vram_offset,
> > > -						    comp_pat_index, pt31_ofs);
> > > +						    comp_pat_index, pt47_ofs, pt45_ofs);
> > >   		}
> > >   	}
> > > @@ -381,8 +398,8 @@ static void xe_migrate_suballoc_manager_init(struct xe_migrate *m, u32 map_ofs)
> > >   	 * Example layout created above, with root level = 3:
> > >   	 * [PT0...PT7]: kernel PT's for copy/clear; 64 or 4KiB PTE's
> > >   	 * [PT8]: Kernel PT for VM_BIND, 4 KiB PTE's
> > > -	 * [PT9...PT26]: Userspace PT's for VM_BIND, 4 KiB PTE's
> > > -	 * [PT27 = PDE 0] [PT28 = PDE 1] [PT29 = PDE 2] [PT30 & PT31 = 2M vram identity map]
> > > +	 * [PT9...PT40]: Userspace PT's for VM_BIND, 4 KiB PTE's
> > > +	 * [PT41 = PDE 0] [PT44...PT47 = 4K and 2M vram identity maps]
> > >   	 *
> > >   	 * This makes the lowest part of the VM point to the pagetables.
> > >   	 * Hence the lowest 2M in the vm should point to itself, with a few writes
> > > -- 
> > > 2.55.0
> > > 
> 

[PATCH 2/5] drm/xe: Don't hand out the flat CCS storage as usable VRAM

[Matthew Auld]

From: Linus Torvalds <torvalds@linux-foundation.org>

get_flat_ccs_offset() reads the base of the flat CCS storage from the
hardware, scales it by the number of enabled L3 nodes, and rounds the
result up to 128K.  Everything below that offset is then handed to the
VRAM allocator as usable memory.

Rounding a limit that means "usable memory ends here" upwards publishes
whatever lies between the real base and the rounded one as free memory,
and that memory belongs to the compression hardware.  The scaled value
has no reason to be 128K aligned, and on a Battlemage G21 with 16 GiB it
is not:

	flat CCS base: raw 0x3fafff800, rounded 0x3fb000000

so the last 2 KiB of page 0x3fafff000 is CCS storage, in the allocator's
pool.  Whatever is allocated there gets that tail overwritten by the
compression hardware, which needs no page-table entry, no buffer object
and no GPU submission to do it, and does it before userspace exists.

On this machine a Mesa VM's level-3 page table landed on that page on
every cold boot.  It lost the entry covering the compositor's
batch-buffer heap, so the compositor's first submission faulted fetching
its batch and gdm restarted it forever: a black screen on an otherwise
working machine.  Restarting gdm cleared it because the next VM's page
tables were allocated somewhere else.

Round down instead, to the page size the allocator works in.  On this
machine that excludes exactly one page.

Reading the reserved page afterwards shows what had been writing it:

	[369] 0xcccc000000000000
	[371] 0xcc77000000000000
	[373] 0xcccc000000000000
	[375] 0xcc77000000000000

compression metadata, two bytes per sixteen, sitting where the driver
used to hand out memory.

The assertion that should have caught this compares the offset against
GSMBASE - ccs_size for equality.  That value is 128K aligned, so it
agrees with the rounded-up offset precisely when the base is not
aligned - the check cannot fail in the case it exists to catch, and is
compiled out unless CONFIG_DRM_XE_DEBUG is set.  Replace it with one
that can fail: CCS storage must not run into GSM.

[ And this was a debug session from hell, enormously helped by an AI
  doing much of the grunt-work.

  I'd like to call it my tireless helper, but the AI several times
  stated flat out that this was impossible and unsolvable and that we
  should just write a report about it.

  I suspect those things have been trained by people who may not be
  quite as stubborn as I am.

  But while the AI was ready to give up several times, it did keep
  adding debug code and analyzing it faithfully when I pushed. So credit
  where credit is due and I let the AI write the commit message above.

  This is basically a one-liner fixing a bogus "round_up()" to a
  "round_down()", but there were 24 patches adding more and more debug
  information to this, and 18 kernel boot to finally narrow it down to
  this.   - Linus ]

Fixes: 37173392741c ("drm/xe/vram: fix ccs offset calculation")
Cc: stable@kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
(cherry picked from commit 818bebeb63dd6bf5f4e07e145f6cdbace520a34c)
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_vram.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 23eb7edbdd57..7b4478fb1697 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -89,12 +89,25 @@ static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
 		offset = offset_hi << 32; /* HW view bits 39:32 */
 		offset |= offset_lo << 6; /* HW view bits 31:6 */
 		offset *= num_enabled; /* convert to SW view */
-		offset = round_up(offset, SZ_128K); /* SW must round up to nearest 128K */
 
-		/* We don't expect any holes */
-		xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(&gt_to_tile(gt)->mmio, GSMBASE) -
-					     ccs_size),
-			      "Hole between CCS and GSM.\n");
+		/*
+		 * Everything below this offset is handed to the VRAM
+		 * allocator, so it has to be the *first* address the
+		 * compression hardware owns, rounded down.  Rounding it up
+		 * publishes CCS storage as free memory.
+		 */
+		offset = round_down(offset, SZ_4K);
+
+		/*
+		 * CCS storage must not run into GSM.  The old check compared
+		 * the offset against GSMBASE - ccs_size for equality, which
+		 * could not fail: that value is 128K aligned, so it agreed
+		 * with the rounded-up offset even when the base was not 128K
+		 * aligned - exactly the case this fixes.
+		 */
+		xe_assert_msg(xe, offset + ccs_size <=
+			      xe_mmio_read64_2x32(&gt_to_tile(gt)->mmio, GSMBASE),
+			      "CCS overlaps GSM.\n");
 	} else {
 		reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
 		offset = (u64)REG_FIELD_GET(XEHP_FLAT_CCS_PTR, reg) * SZ_64K;
-- 
2.55.0

[PATCH 3/5] drm/xe/vram: report FLAT_CCS base misalignment

[Matthew Auld]

So we can easily check if a machine had the CCS bug, when looking back
over bug reports where we have the same machine with newer kernel.

Fixes: 37173392741c ("drm/xe/vram: fix ccs offset calculation")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: stable@kernel.org
---
 drivers/gpu/drm/xe/xe_vram.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 7b4478fb1697..0a2f1ab8416e 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -90,6 +90,9 @@ static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
 		offset |= offset_lo << 6; /* HW view bits 31:6 */
 		offset *= num_enabled; /* convert to SW view */
 
+		if (!IS_ALIGNED(offset, SZ_128K))
+			drm_info(&xe->drm, "FLAT_CCS base misaligned: %llx\n", offset);
+
 		/*
 		 * Everything below this offset is handed to the VRAM
 		 * allocator, so it has to be the *first* address the
-- 
2.55.0

Re: [PATCH 3/5] drm/xe/vram: report FLAT_CCS base misalignment

[Matthew Brost]

On Fri, Aug 28, 2026 at 04:14:09PM +0100, Matthew Auld wrote:
> So we can easily check if a machine had the CCS bug, when looking back
> over bug reports where we have the same machine with newer kernel.
> 

I'm a little confused about how this helps, so I'm thinking out loud here:
 
- On old kernels without Linus's CCS fix or this patch, there is no
  message and we get silent corruption if the affected memory belongs to
  user space. Of course, things fall apart completely if the corruption
  affects kernel memory, as in the case Linus hit.
- On new kernels with Linus's CCS fix plus this patch, does this message
  appear under load on some configurations, or on all configurations?

Is the idea that the first thing we check for is whether this message is
present?
 
Would it be better to simply print the FLAT_CCS base address along with
a field indicating whether it is misaligned? That would let us quickly
determine, across all devices, whether the CCS base is aligned or
misaligned and if the CCS fix is present.

Matt

> Fixes: 37173392741c ("drm/xe/vram: fix ccs offset calculation")
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: stable@kernel.org
> ---
>  drivers/gpu/drm/xe/xe_vram.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> index 7b4478fb1697..0a2f1ab8416e 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
> @@ -90,6 +90,9 @@ static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
>  		offset |= offset_lo << 6; /* HW view bits 31:6 */
>  		offset *= num_enabled; /* convert to SW view */
>  
> +		if (!IS_ALIGNED(offset, SZ_128K))
> +			drm_info(&xe->drm, "FLAT_CCS base misaligned: %llx\n", offset);
> +
>  		/*
>  		 * Everything below this offset is handed to the VRAM
>  		 * allocator, so it has to be the *first* address the
> -- 
> 2.55.0
> 

Re: [PATCH 3/5] drm/xe/vram: report FLAT_CCS base misalignment

[Matthew Auld]

On 28/08/2026 21:10, Matthew Brost wrote:
> On Fri, Aug 28, 2026 at 04:14:09PM +0100, Matthew Auld wrote:
>> So we can easily check if a machine had the CCS bug, when looking back
>> over bug reports where we have the same machine with newer kernel.
>>
> 
> I'm a little confused about how this helps, so I'm thinking out loud here:
>   
> - On old kernels without Linus's CCS fix or this patch, there is no
>    message and we get silent corruption if the affected memory belongs to
>    user space. Of course, things fall apart completely if the corruption
>    affects kernel memory, as in the case Linus hit.
> - On new kernels with Linus's CCS fix plus this patch, does this message
>    appear under load on some configurations, or on all configurations?

Yeah, this is logged before the round_down(offset, 4K). On my b570, for 
example, I get a nice dmesg print to indicate that this machine had the 
bug (fix from Linus also applied). In our CI farm, there is no print, 
since nothing seems to have this bug, also confirms the memtest is not 
just missing the issue somehow. But not sure about wider RIL, I assume 
something in there maybe has this bug.

> 
> Is the idea that the first thing we check for is whether this message is
> present?

Yeah, just a record in dmesg of whether the device had this CCS bug, 
when looking at bug reports. The memtest is also gated behind debug 
builds, for now. For example, some older bug report with impossible 
corruption or other weird stuff, update to latest stable or tip and 
issue seems to go away. Would be good to confirm if this machine had the 
CCS bug. Users might also want to check this.

>   
> Would it be better to simply print the FLAT_CCS base address along with
> a field indicating whether it is misaligned? That would let us quickly
> determine, across all devices, whether the CCS base is aligned or
> misaligned and if the CCS fix is present.

Could print the address also. Happy to do either approach.

> 
> Matt
> 
>> Fixes: 37173392741c ("drm/xe/vram: fix ccs offset calculation")
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: stable@kernel.org
>> ---
>>   drivers/gpu/drm/xe/xe_vram.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
>> index 7b4478fb1697..0a2f1ab8416e 100644
>> --- a/drivers/gpu/drm/xe/xe_vram.c
>> +++ b/drivers/gpu/drm/xe/xe_vram.c
>> @@ -90,6 +90,9 @@ static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
>>   		offset |= offset_lo << 6; /* HW view bits 31:6 */
>>   		offset *= num_enabled; /* convert to SW view */
>>   
>> +		if (!IS_ALIGNED(offset, SZ_128K))
>> +			drm_info(&xe->drm, "FLAT_CCS base misaligned: %llx\n", offset);
>> +
>>   		/*
>>   		 * Everything below this offset is handed to the VRAM
>>   		 * allocator, so it has to be the *first* address the
>> -- 
>> 2.55.0
>>

Re: [PATCH 3/5] drm/xe/vram: report FLAT_CCS base misalignment

[Matthew Brost]

On Tue, Sep 01, 2026 at 09:23:22AM +0100, Matthew Auld wrote:
> On 28/08/2026 21:10, Matthew Brost wrote:
> > On Fri, Aug 28, 2026 at 04:14:09PM +0100, Matthew Auld wrote:
> > > So we can easily check if a machine had the CCS bug, when looking back
> > > over bug reports where we have the same machine with newer kernel.
> > > 
> > 
> > I'm a little confused about how this helps, so I'm thinking out loud here:
> > - On old kernels without Linus's CCS fix or this patch, there is no
> >    message and we get silent corruption if the affected memory belongs to
> >    user space. Of course, things fall apart completely if the corruption
> >    affects kernel memory, as in the case Linus hit.
> > - On new kernels with Linus's CCS fix plus this patch, does this message
> >    appear under load on some configurations, or on all configurations?
> 
> Yeah, this is logged before the round_down(offset, 4K). On my b570, for
> example, I get a nice dmesg print to indicate that this machine had the bug
> (fix from Linus also applied). In our CI farm, there is no print, since
> nothing seems to have this bug, also confirms the memtest is not just
> missing the issue somehow. But not sure about wider RIL, I assume something
> in there maybe has this bug.
> 
> > 
> > Is the idea that the first thing we check for is whether this message is
> > present?
> 
> Yeah, just a record in dmesg of whether the device had this CCS bug, when
> looking at bug reports. The memtest is also gated behind debug builds, for
> now. For example, some older bug report with impossible corruption or other
> weird stuff, update to latest stable or tip and issue seems to go away.
> Would be good to confirm if this machine had the CCS bug. Users might also
> want to check this.
> 
> > Would it be better to simply print the FLAT_CCS base address along with
> > a field indicating whether it is misaligned? That would let us quickly
> > determine, across all devices, whether the CCS base is aligned or
> > misaligned and if the CCS fix is present.
> 
> Could print the address also. Happy to do either approach.
> 

I think just delete the 'if (!IS_ALIGNED(offset, SZ_128K))' gate and
print the CCS info + flag a misalignment.

Matt

> > 
> > Matt
> > 
> > > Fixes: 37173392741c ("drm/xe/vram: fix ccs offset calculation")
> > > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > > Cc: Matthew Brost <matthew.brost@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Cc: stable@kernel.org
> > > ---
> > >   drivers/gpu/drm/xe/xe_vram.c | 3 +++
> > >   1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
> > > index 7b4478fb1697..0a2f1ab8416e 100644
> > > --- a/drivers/gpu/drm/xe/xe_vram.c
> > > +++ b/drivers/gpu/drm/xe/xe_vram.c
> > > @@ -90,6 +90,9 @@ static int get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size, u64 *poffset)
> > >   		offset |= offset_lo << 6; /* HW view bits 31:6 */
> > >   		offset *= num_enabled; /* convert to SW view */
> > > +		if (!IS_ALIGNED(offset, SZ_128K))
> > > +			drm_info(&xe->drm, "FLAT_CCS base misaligned: %llx\n", offset);
> > > +
> > >   		/*
> > >   		 * Everything below this offset is handed to the VRAM
> > >   		 * allocator, so it has to be the *first* address the
> > > -- 
> > > 2.55.0
> > > 
> 

[PATCH 4/5] drm/xe: add force option for global invalidation

[Matthew Auld]

The flush is gated by the WA, since there would no valid use for it
otherwise, but for some very special usecases allow bypassing the WA.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 2 +-
 drivers/gpu/drm/xe/display/xe_fb_pin.c     | 2 +-
 drivers/gpu/drm/xe/xe_device.c             | 6 +++---
 drivers/gpu/drm/xe/xe_device.h             | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
index a7158c73a14c..82974e933e8d 100644
--- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
+++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
@@ -88,7 +88,7 @@ static void xe_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
 	 * both for weak ordering archs and discrete cards.
 	 */
 	xe_device_wmb(xe);
-	xe_device_l2_flush(xe);
+	xe_device_l2_flush(xe, false);
 }
 
 const struct intel_display_dsb_interface xe_display_dsb_interface = {
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 73469ea5f333..b46a2c32ac07 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -203,7 +203,7 @@ static int __xe_pin_fb_vma_dpt(struct drm_gem_object *obj,
 	vma->node = dpt->ggtt_node[tile0->id];
 
 	/* Ensure DPT writes are flushed */
-	xe_device_l2_flush(xe);
+	xe_device_l2_flush(xe, false);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 74d566693dfd..82e0a555fa69 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1270,7 +1270,7 @@ bool xe_device_is_l2_flush_optimized(struct xe_device *xe)
 	return false;
 }
 
-void xe_device_l2_flush(struct xe_device *xe)
+void xe_device_l2_flush(struct xe_device *xe, bool force)
 {
 	struct xe_gt *gt;
 
@@ -1278,7 +1278,7 @@ void xe_device_l2_flush(struct xe_device *xe)
 	if (!gt)
 		return;
 
-	if (!XE_GT_WA(gt, 16023588340))
+	if (!force && !XE_GT_WA(gt, 16023588340))
 		return;
 
 	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
@@ -1333,7 +1333,7 @@ void xe_device_td_flush(struct xe_device *xe)
 
 	if (XE_GT_WA(root_gt, 16023588340)) {
 		/* A transient flush is not sufficient: flush the L2 */
-		xe_device_l2_flush(xe);
+		xe_device_l2_flush(xe, false);
 	} else {
 		xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc);
 		tdf_request_sync(xe);
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 6c4cfaebc44a..6d3d6d5eba29 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -205,7 +205,7 @@ u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
 
 bool xe_device_is_l2_flush_optimized(struct xe_device *xe);
 void xe_device_td_flush(struct xe_device *xe);
-void xe_device_l2_flush(struct xe_device *xe);
+void xe_device_l2_flush(struct xe_device *xe, bool force);
 
 static inline bool xe_device_wedged(struct xe_device *xe)
 {
-- 
2.55.0

Re: [PATCH 4/5] drm/xe: add force option for global invalidation

[Matthew Brost]

On Fri, Aug 28, 2026 at 04:14:10PM +0100, Matthew Auld wrote:
> The flush is gated by the WA, since there would no valid use for it
> otherwise, but for some very special usecases allow bypassing the WA.
> 
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 2 +-
>  drivers/gpu/drm/xe/display/xe_fb_pin.c     | 2 +-
>  drivers/gpu/drm/xe/xe_device.c             | 6 +++---
>  drivers/gpu/drm/xe/xe_device.h             | 2 +-
>  4 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
> index a7158c73a14c..82974e933e8d 100644
> --- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
> +++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
> @@ -88,7 +88,7 @@ static void xe_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
>  	 * both for weak ordering archs and discrete cards.
>  	 */
>  	xe_device_wmb(xe);
> -	xe_device_l2_flush(xe);
> +	xe_device_l2_flush(xe, false);
>  }
>  
>  const struct intel_display_dsb_interface xe_display_dsb_interface = {
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index 73469ea5f333..b46a2c32ac07 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -203,7 +203,7 @@ static int __xe_pin_fb_vma_dpt(struct drm_gem_object *obj,
>  	vma->node = dpt->ggtt_node[tile0->id];
>  
>  	/* Ensure DPT writes are flushed */
> -	xe_device_l2_flush(xe);
> +	xe_device_l2_flush(xe, false);
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 74d566693dfd..82e0a555fa69 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -1270,7 +1270,7 @@ bool xe_device_is_l2_flush_optimized(struct xe_device *xe)
>  	return false;
>  }
>  
> -void xe_device_l2_flush(struct xe_device *xe)
> +void xe_device_l2_flush(struct xe_device *xe, bool force)
>  {
>  	struct xe_gt *gt;
>  
> @@ -1278,7 +1278,7 @@ void xe_device_l2_flush(struct xe_device *xe)
>  	if (!gt)
>  		return;
>  
> -	if (!XE_GT_WA(gt, 16023588340))
> +	if (!force && !XE_GT_WA(gt, 16023588340))
>  		return;
>  
>  	CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT);
> @@ -1333,7 +1333,7 @@ void xe_device_td_flush(struct xe_device *xe)
>  
>  	if (XE_GT_WA(root_gt, 16023588340)) {
>  		/* A transient flush is not sufficient: flush the L2 */
> -		xe_device_l2_flush(xe);
> +		xe_device_l2_flush(xe, false);
>  	} else {
>  		xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc);
>  		tdf_request_sync(xe);
> diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
> index 6c4cfaebc44a..6d3d6d5eba29 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -205,7 +205,7 @@ u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
>  
>  bool xe_device_is_l2_flush_optimized(struct xe_device *xe);
>  void xe_device_td_flush(struct xe_device *xe);
> -void xe_device_l2_flush(struct xe_device *xe);
> +void xe_device_l2_flush(struct xe_device *xe, bool force);
>  
>  static inline bool xe_device_wedged(struct xe_device *xe)
>  {
> -- 
> 2.55.0
> 

[PATCH 5/5] drm/xe/vram: add early VRAM health check

[Matthew Auld]

During early probe, use the last page as a canary for BAR sizing, CCS
sizing, identity map setup etc. If something is wrong the last page is
where we will likely find it. Hit it with everything we have. For now
this is gated behind a debug config option, so shouldn't trigger on
production.

Main motivation is around CCS sizing where on some BMG cards the CCS
offset is programmed misaligned, for whatever reason, and our handling
of that was busted, as found by Linus, leading to some amount of CCS
storage getting pulled into the allocator as normal VRAM.

Nothing in our CI farm has such a misaligned offset it would seem,
however I did get this to pop on my b570, which does also have the
misaligned CCS offset:

  Tile 0: Running VRAM memtest...
  Tile 0: VRAM bounds overlap CCS region! VRAM sizing is incorrect.

With the fix from Linus, this goes away:

  Tile 0: Running VRAM memtest...
  Tile 0: VRAM memtest completed.

Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c     |   8 +
 drivers/gpu/drm/xe/xe_migrate.c    |  64 ++++++++
 drivers/gpu/drm/xe/xe_migrate.h    |   6 +
 drivers/gpu/drm/xe/xe_tile_types.h |   4 +
 drivers/gpu/drm/xe/xe_vram.c       | 241 +++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_vram.h       |  10 ++
 6 files changed, 333 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 82e0a555fa69..80008bf5776c 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1051,6 +1051,10 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		return err;
 
+	err = xe_vram_reserve_memtest_bo(xe);
+	if (err)
+		return err;
+
 	for_each_tile(tile, xe, id) {
 		err = xe_tile_init(tile);
 		if (err)
@@ -1067,6 +1071,10 @@ int xe_device_probe(struct xe_device *xe)
 			return err;
 	}
 
+	err = xe_vram_memtest(xe);
+	if (err)
+		return err;
+
 	err = xe_pagefault_init(xe);
 	if (err)
 		return err;
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 0bf000d7c901..ff45c24d8889 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -2650,3 +2650,67 @@ void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 #include "tests/xe_migrate.c"
 #endif
+
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
+				 struct xe_bo *scratch_bo,
+				 bool write_to_ccs)
+{
+	struct xe_device *xe = tile_to_xe(m->tile);
+	struct xe_gt *gt = m->tile->primary_gt;
+	struct dma_fence *fence;
+	struct xe_bb *bb;
+	struct xe_sched_job *job;
+	u64 first_page_dpa, clear_L0_ofs, scratch_dpa, scratch_L0_ofs;
+
+	if (!xe_device_has_flat_ccs(xe))
+		return -EINVAL;
+
+	first_page_dpa = xe_vram_region_dpa_base(m->tile->mem.vram);
+	clear_L0_ofs = xe_migrate_vram_ofs(xe, first_page_dpa, true);
+
+	scratch_dpa = xe_bo_addr(scratch_bo, 0, XE_PAGE_SIZE);
+	scratch_L0_ofs = xe_migrate_vram_ofs(xe, scratch_dpa, false);
+
+	bb = xe_bb_new(gt, EMIT_COPY_CCS_DW + 1, xe->info.has_usm);
+	if (IS_ERR(bb)) {
+		drm_warn(&xe->drm, "Failed to create bb for VRAM overlap check\n");
+		return PTR_ERR(bb);
+	}
+
+	/* 4MB payload = 8KB CCS metadata */
+	if (write_to_ccs) {
+		emit_copy_ccs(gt, bb, clear_L0_ofs, true,
+			      scratch_L0_ofs, false, SZ_4M);
+	} else {
+		emit_copy_ccs(gt, bb, scratch_L0_ofs, false,
+			      clear_L0_ofs, true, SZ_4M);
+	}
+
+	bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
+
+	job = xe_bb_create_migration_job(m->q, bb,
+					 xe_migrate_batch_base(m, xe->info.has_usm),
+					 0);
+	if (!IS_ERR(job)) {
+		xe_sched_job_add_migrate_flush(job, MI_FLUSH_DW_CCS);
+
+		mutex_lock(&m->job_mutex);
+		xe_sched_job_arm(job);
+
+		fence = dma_fence_get(&job->drm.s_fence->finished);
+		xe_sched_job_push(job);
+		mutex_unlock(&m->job_mutex);
+
+		dma_fence_wait(fence, false);
+		dma_fence_put(fence);
+	} else {
+		drm_warn(&xe->drm, "Failed to create job for VRAM overlap check\n");
+		xe_bb_free(bb, NULL);
+		return PTR_ERR(job);
+	}
+
+	xe_bb_free(bb, NULL);
+	return 0;
+}
+#endif
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index c3a268b01768..a9acc62f78f0 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -182,4 +182,10 @@ static inline void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
 void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue *q);
 void xe_migrate_job_unlock(struct xe_migrate *m, struct xe_exec_queue *q);
 
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
+				 struct xe_bo *scratch_bo,
+				 bool write_to_ccs);
+#endif
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_tile_types.h b/drivers/gpu/drm/xe/xe_tile_types.h
index 0048100ccb72..e1368c04846a 100644
--- a/drivers/gpu/drm/xe/xe_tile_types.h
+++ b/drivers/gpu/drm/xe/xe_tile_types.h
@@ -97,6 +97,10 @@ struct xe_tile {
 		 * Only main GT has page reclaim list allocations.
 		 */
 		struct xe_sa_manager *reclaim_pool;
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+		/** @mem.memtest_bo: VRAM overlap check BO */
+		struct xe_bo *memtest_bo;
+#endif
 	} mem;
 
 	/** @sriov: tile level virtualization data */
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 0a2f1ab8416e..4a79580c5315 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -17,8 +17,11 @@
 #include "xe_device.h"
 #include "xe_force_wake.h"
 #include "xe_gt_mcr.h"
+#include "xe_map.h"
+#include "xe_migrate.h"
 #include "xe_mmio.h"
 #include "xe_sriov.h"
+#include "xe_tile.h"
 #include "xe_tile_sriov_vf.h"
 #include "xe_ttm_vram_mgr.h"
 #include "xe_vram.h"
@@ -403,3 +406,241 @@ resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region
 	return vram ? vram->actual_physical_size : 0;
 }
 EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size);
+
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+static void memtest_bo_cleanup(void *arg)
+{
+	struct xe_device *xe = arg;
+
+	xe_vram_free_memtest_bos(xe);
+}
+
+int xe_vram_reserve_memtest_bo(struct xe_device *xe)
+{
+	struct xe_tile *tile;
+	u8 id;
+
+	if (IS_SRIOV_VF(xe))
+		return 0;
+
+	for_each_tile(tile, xe, id) {
+		u64 vram_size;
+
+		if (!tile->mem.vram)
+			continue;
+
+		if (tile->mem.vram->io_size < tile->mem.vram->usable_size) {
+			drm_info(&xe->drm,
+				 "Tile %d: Small-BAR system detected, skipping VRAM memtest\n",
+				 id);
+			continue;
+		}
+
+		vram_size = tile->mem.vram->usable_size;
+
+		tile->mem.memtest_bo = xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
+								    vram_size - SZ_64K,
+								    ttm_bo_type_kernel,
+								    XE_BO_FLAG_VRAM_IF_DGFX(tile),
+								    0, false);
+		if (IS_ERR(tile->mem.memtest_bo)) {
+			drm_warn(&xe->drm, "Tile %d: Failed to reserve memtest BO\n", id);
+			tile->mem.memtest_bo = NULL;
+			continue;
+		}
+
+		drm_info(&xe->drm, "Tile %d: Reserved memtest BO at offset 0x%llx\n",
+			 id, vram_size - SZ_64K);
+	}
+
+	return devm_add_action_or_reset(xe->drm.dev, memtest_bo_cleanup, xe);
+}
+
+void xe_vram_free_memtest_bos(struct xe_device *xe)
+{
+	struct xe_tile *tile;
+	u8 id;
+
+	for_each_tile(tile, xe, id) {
+		if (tile->mem.memtest_bo) {
+			xe_bo_unpin_map_no_vm(tile->mem.memtest_bo);
+			tile->mem.memtest_bo = NULL;
+		}
+	}
+}
+
+int xe_vram_memtest(struct xe_device *xe)
+{
+	struct xe_tile *tile;
+	u8 id;
+	int err = 0;
+
+	if (IS_SRIOV_VF(xe))
+		return 0;
+
+	for_each_tile(tile, xe, id) {
+		struct xe_bo *last_page_bo = tile->mem.memtest_bo;
+		struct dma_fence *fence;
+		bool overlap = false;
+		int i;
+		u8 val;
+
+		if (!last_page_bo || !tile->migrate)
+			continue;
+
+		drm_info(&xe->drm, "Tile %d: Running VRAM memtest...\n", id);
+
+		/* CPU write and readback first and last byte of the last page */
+		xe_map_wr(xe, &last_page_bo->vmap, 0, u8, 0xA5);
+		xe_map_wr(xe, &last_page_bo->vmap, SZ_64K - 1, u8, 0x5A);
+
+		val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
+		if (drm_WARN(&xe->drm, val != 0xA5,
+			     "Tile %d: CPU memtest failed at offset 0 (expected 0xA5, got 0x%02x)\n",
+			     id, val)) {
+			err = -EIO;
+			goto unpin;
+		}
+
+		val = xe_map_rd(xe, &last_page_bo->vmap, SZ_64K - 1, u8);
+		if (drm_WARN(&xe->drm, val != 0x5A,
+			     "Tile %d: CPU memtest failed at offset 65535 (expected 0x5A, got 0x%02x)\n",
+			     id, val)) {
+			err = -EIO;
+			goto unpin;
+		}
+
+		/* Non-CCS access via GPU on the last page */
+		xe_bo_lock(last_page_bo, false);
+		fence = xe_migrate_clear(tile->migrate, last_page_bo,
+					 last_page_bo->ttm.resource,
+					 XE_MIGRATE_CLEAR_FLAG_BO_DATA);
+		xe_bo_unlock(last_page_bo);
+
+		if (!IS_ERR(fence)) {
+			dma_fence_wait(fence, false);
+			dma_fence_put(fence);
+		} else {
+			err = PTR_ERR(fence);
+			goto unpin;
+		}
+
+		val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
+		if (drm_WARN(&xe->drm, val != 0x00,
+			     "Tile %d: GPU memtest clear failed at offset 0 (expected 0x00, got 0x%02x)\n",
+			     id, val)) {
+			err = -EIO;
+			goto unpin;
+		}
+
+		/*
+		 * Check for CCS overlap on the root tile.
+		 *
+		 * TODO: maybe extend if we ever get multi-tile + CCS. Pay
+		 * special attention to the l2 flush below. Currently that is
+		 * hard coded to the root tile.
+		 */
+		if (!id && xe_device_has_flat_ccs(xe) &&
+		    GRAPHICS_VERx100(xe) >= 2000) {
+			struct xe_bo *scratch_bo_before;
+			struct xe_bo *scratch_bo_after;
+
+			scratch_bo_before = xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
+								      ttm_bo_type_kernel,
+								      XE_BO_FLAG_VRAM_IF_DGFX(tile),
+								      false);
+			if (IS_ERR(scratch_bo_before)) {
+				err = PTR_ERR(scratch_bo_before);
+				goto unpin;
+			}
+
+			scratch_bo_after = xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
+								     ttm_bo_type_kernel,
+								     XE_BO_FLAG_VRAM_IF_DGFX(tile),
+								     false);
+			if (IS_ERR(scratch_bo_after)) {
+				xe_bo_unpin_map_no_vm(scratch_bo_before);
+				err = PTR_ERR(scratch_bo_after);
+				goto unpin;
+			}
+
+			/* Save original CCS metadata for PA 0 + */
+			err = xe_migrate_debug_ccs_overlap(tile->migrate, scratch_bo_before, false);
+			if (err) {
+				xe_bo_unpin_map_no_vm(scratch_bo_before);
+				xe_bo_unpin_map_no_vm(scratch_bo_after);
+				goto unpin;
+			}
+
+			/*
+			 * Fill last page. If there is CCS overlap in the last
+			 * page this will snag the raw CCS storage.
+			 */
+			xe_map_memset(xe, &last_page_bo->vmap, 0, 0x5A, SZ_64K);
+			xe_device_wmb(xe);
+
+			/*
+			 * Global invalidation. Some BMG SKUs will cache the BAR
+			 * writes in the GPU side VRAM cache. Make sure above
+			 * writes are fully flushed out to VRAM, so this is
+			 * hopefully more well behaved with the CCS unit, if
+			 * there is indeed CCS overlap with normal VRAM. Since
+			 * there is a separate CCS cache, the CCS unit might not
+			 * respect the GPU VRAM cache for CCS accesses, so opt
+			 * for being super careful here.
+			 */
+			xe_device_l2_flush(xe, true);
+
+			/* Use GPU to clear CCS state for PA 0 */
+			xe_map_memset(xe, &scratch_bo_after->vmap, 0, 0x00, SZ_64K);
+			err = xe_migrate_debug_ccs_overlap(tile->migrate, scratch_bo_after, true);
+			if (err) {
+				xe_bo_unpin_map_no_vm(scratch_bo_before);
+				xe_bo_unpin_map_no_vm(scratch_bo_after);
+				goto unpin;
+			}
+			/*
+			 * Global invalidation. Ensure CCS caches really are
+			 * nuked and the raw CCS data is visible in VRAM, for
+			 * the below access.
+			 */
+			xe_device_l2_flush(xe, true);
+
+			/* Check if last_page_bo was corrupted by the GPU CCS clear */
+			for (i = 0; i < SZ_64K; i += 8) {
+				u64 payload = xe_map_rd(xe, &last_page_bo->vmap, i, u64);
+
+				if (payload != 0x5A5A5A5A5A5A5A5AULL) {
+					overlap = true;
+					break;
+				}
+			}
+
+			/* Restore original CCS metadata for PA 0 + */
+			err = xe_migrate_debug_ccs_overlap(tile->migrate, scratch_bo_before, true);
+			if (err)
+				drm_warn(&xe->drm, "Failed to restore CCS metadata\n");
+
+			xe_bo_unpin_map_no_vm(scratch_bo_before);
+			xe_bo_unpin_map_no_vm(scratch_bo_after);
+		}
+
+		if (drm_WARN(&xe->drm, overlap,
+			     "Tile %d: VRAM bounds overlap CCS region! VRAM sizing is incorrect.\n",
+			     id)) {
+			err = -EINVAL;
+			goto unpin;
+		}
+
+		drm_info(&xe->drm, "Tile %d: VRAM memtest completed.\n", id);
+
+unpin:
+		if (err)
+			break;
+	}
+
+	xe_vram_free_memtest_bos(xe);
+
+	return err;
+}
+#endif
diff --git a/drivers/gpu/drm/xe/xe_vram.h b/drivers/gpu/drm/xe/xe_vram.h
index dd1c8bf17922..38425d81f777 100644
--- a/drivers/gpu/drm/xe/xe_vram.h
+++ b/drivers/gpu/drm/xe/xe_vram.h
@@ -23,4 +23,14 @@ resource_size_t xe_vram_region_dpa_base(const struct xe_vram_region *vram);
 resource_size_t xe_vram_region_usable_size(const struct xe_vram_region *vram);
 resource_size_t xe_vram_region_actual_physical_size(const struct xe_vram_region *vram);
 
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
+int xe_vram_reserve_memtest_bo(struct xe_device *xe);
+void xe_vram_free_memtest_bos(struct xe_device *xe);
+int xe_vram_memtest(struct xe_device *xe);
+#else
+static inline int xe_vram_reserve_memtest_bo(struct xe_device *xe) { return 0; }
+static inline void xe_vram_free_memtest_bos(struct xe_device *xe) {}
+static inline int xe_vram_memtest(struct xe_device *xe) { return 0; }
+#endif
+
 #endif
-- 
2.55.0

Re: [PATCH 5/5] drm/xe/vram: add early VRAM health check

[Linus Torvalds]

On Fri, 28 Aug 2026 at 08:14, Matthew Auld <matthew.auld@intel.com> wrote:
>
> With the fix from Linus, this goes away:

Side note: I told Greg KH that he should hold off on applying my fix
to stable - because while it looked ObviouslyCorrect(tm) to me, I had
only ever tested it on one single machine.

I'm taking it that the fix has now been tested much more widely and
found no subtle issues? If so, I should let Greg know to go ahead and
put it in the stable queue.

                    Linus

Re: [PATCH 5/5] drm/xe/vram: add early VRAM health check

[Matthew Brost]

On Fri, Aug 28, 2026 at 09:13:07AM -0700, Linus Torvalds wrote:
> On Fri, 28 Aug 2026 at 08:14, Matthew Auld <matthew.auld@intel.com> wrote:
> >
> > With the fix from Linus, this goes away:
> 
> Side note: I told Greg KH that he should hold off on applying my fix
> to stable - because while it looked ObviouslyCorrect(tm) to me, I had
> only ever tested it on one single machine.
> 
> I'm taking it that the fix has now been tested much more widely and
> found no subtle issues? If so, I should let Greg know to go ahead and
> put it in the stable queue.
> 

I think it's OK to go ahead with backporting your patch to stable. I had
an open question about whether we wanted to implement the fix slightly
differently to avoid asserts triggering elsewhere in the code [1], but
Matt Auld has figured that part out while still carrying your fix
verbatim [2]. The asserts are also harmless and only appear in debug
builds. CI is passing as well [3], which should exercise this path
across several configurations.

We should discuss whether we want to backport [1] too.

Matt

[1] https://patchwork.freedesktop.org/patch/749151/?series=172984&rev=1
[2] https://patchwork.freedesktop.org/patch/749152/?series=172984&rev=1
[3] https://patchwork.freedesktop.org/series/172984/

>                     Linus

Re: [PATCH 5/5] drm/xe/vram: add early VRAM health check

[Linus Torvalds]

On Fri, 28 Aug 2026 at 12:58, Matthew Brost <matthew.brost@intel.com> wrote:
>
> I think it's OK to go ahead with backporting your patch to stable. I had
> an open question about whether we wanted to implement the fix slightly
> differently to avoid asserts triggering elsewhere in the code [1]

Hmm. That patch is odd.

It says

 "When VRAM limit (usable_size) is no longer 2M aligned (e.g. because flat
  CCS storage size rounds it down to 4K)," [...]

but that was never true, even before my fix. The usable size was
either 64kB aligned or 128kB aligned - it has *never* been 2M aligned
as far as I can tell.

Now, obviously, if alignment never did anything at all (because CCS
was already completely aligned), then that 2M alignment could be true.

So maybe the 2M alignment existed in practice, but it was certainly
never guaranteed by any code, and any 2M assumptions were completely
bogus long before my fix as far as I can tell.

But that commit is odd in another way: it changes the  code to do
something completely different.

Before, it didn't use "usable_size" at all, it used thje *actual*
physical size. Which really *was* 2M aligned, becuase I don't think
Intel has ever sold any other configurations than 16/24/64GB of
memory.

So I don't think [1] actually exposes anything in my fix and I think
the whole 2M limit wrt that code is actually an entirely separate
issue.

But I admittedly *really* don't know this hardware very well at all.

But yes, this kind of "my fix exposed *another* bug" was why I was
worried about backporting it without further testing.

              Linus

Re: [PATCH 5/5] drm/xe/vram: add early VRAM health check

[Matthew Brost]

On Fri, Aug 28, 2026 at 01:32:31PM -0700, Linus Torvalds wrote:
> On Fri, 28 Aug 2026 at 12:58, Matthew Brost <matthew.brost@intel.com> wrote:
> >
> > I think it's OK to go ahead with backporting your patch to stable. I had
> > an open question about whether we wanted to implement the fix slightly
> > differently to avoid asserts triggering elsewhere in the code [1]
> 
> Hmm. That patch is odd.
> 

Yes, a little.

> It says
> 
>  "When VRAM limit (usable_size) is no longer 2M aligned (e.g. because flat
>   CCS storage size rounds it down to 4K)," [...]
> 
> but that was never true, even before my fix. The usable size was
> either 64kB aligned or 128kB aligned - it has *never* been 2M aligned
> as far as I can tell.
> 
> Now, obviously, if alignment never did anything at all (because CCS
> was already completely aligned), then that 2M alignment could be true.
> 
> So maybe the 2M alignment existed in practice, but it was certainly
> never guaranteed by any code, and any 2M assumptions were completely
> bogus long before my fix as far as I can tell.

Yes, this just happened to be true because of the rounded-up 128K
alignment. Nothing actually enforced it, nor was it required.

> 
> But that commit is odd in another way: it changes the  code to do
> something completely different.
> 
> Before, it didn't use "usable_size" at all, it used thje *actual*
> physical size. Which really *was* 2M aligned, becuase I don't think
> Intel has ever sold any other configurations than 16/24/64GB of
> memory.
> 
> So I don't think [1] actually exposes anything in my fix and I think
> the whole 2M limit wrt that code is actually an entirely separate
> issue.

Also correct. Your change prompted us to audit and clean up our code.
That said, with your fix alone and CONFIG_DRM_XE_DEBUG enabled, our old
bogus assertion will trigger, but it is meaningless. In any case, no
production kernel enables this option.

> 
> But I admittedly *really* don't know this hardware very well at all.
> 
> But yes, this kind of "my fix exposed *another* bug" was why I was
> worried about backporting it without further testing.

That was my concern too, but our audit showed that the only issue was a
bogus assertion that fell out. It isn't a blocker for getting your fix
into stable.

Matt

> 
>               Linus

Re: [PATCH 5/5] drm/xe/vram: add early VRAM health check

[Summers, Stuart]

On Fri, 2026-08-28 at 16:14 +0100, Matthew Auld wrote:
> During early probe, use the last page as a canary for BAR sizing, CCS
> sizing, identity map setup etc. If something is wrong the last page
> is
> where we will likely find it. Hit it with everything we have. For now

Sorry coming in a little late here... but why only the last page and
not implementing a full per byte/bit memory test to trigger any
potential memory scanning on bit errors? Or is this not the intent
here?

If this is a production scenario, the last page makes sense, but if
we're already wrapping this in a debug config...

Thanks,
Stuart

> this is gated behind a debug config option, so shouldn't trigger on
> production.
> 
> Main motivation is around CCS sizing where on some BMG cards the CCS
> offset is programmed misaligned, for whatever reason, and our
> handling
> of that was busted, as found by Linus, leading to some amount of CCS
> storage getting pulled into the allocator as normal VRAM.
> 
> Nothing in our CI farm has such a misaligned offset it would seem,
> however I did get this to pop on my b570, which does also have the
> misaligned CCS offset:
> 
>   Tile 0: Running VRAM memtest...
>   Tile 0: VRAM bounds overlap CCS region! VRAM sizing is incorrect.
> 
> With the fix from Linus, this goes away:
> 
>   Tile 0: Running VRAM memtest...
>   Tile 0: VRAM memtest completed.
> 
> Assisted-by: Gemini:gemini-3.1-pro-preview
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Linus Torvalds <torvalds@linux-foundation.org>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device.c     |   8 +
>  drivers/gpu/drm/xe/xe_migrate.c    |  64 ++++++++
>  drivers/gpu/drm/xe/xe_migrate.h    |   6 +
>  drivers/gpu/drm/xe/xe_tile_types.h |   4 +
>  drivers/gpu/drm/xe/xe_vram.c       | 241
> +++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_vram.h       |  10 ++
>  6 files changed, 333 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c
> index 82e0a555fa69..80008bf5776c 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -1051,6 +1051,10 @@ int xe_device_probe(struct xe_device *xe)
>         if (err)
>                 return err;
>  
> +       err = xe_vram_reserve_memtest_bo(xe);
> +       if (err)
> +               return err;
> +
>         for_each_tile(tile, xe, id) {
>                 err = xe_tile_init(tile);
>                 if (err)
> @@ -1067,6 +1071,10 @@ int xe_device_probe(struct xe_device *xe)
>                         return err;
>         }
>  
> +       err = xe_vram_memtest(xe);
> +       if (err)
> +               return err;
> +
>         err = xe_pagefault_init(xe);
>         if (err)
>                 return err;
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c
> b/drivers/gpu/drm/xe/xe_migrate.c
> index 0bf000d7c901..ff45c24d8889 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -2650,3 +2650,67 @@ void xe_migrate_job_lock_assert(struct
> xe_exec_queue *q)
>  #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
>  #include "tests/xe_migrate.c"
>  #endif
> +
> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
> +                                struct xe_bo *scratch_bo,
> +                                bool write_to_ccs)
> +{
> +       struct xe_device *xe = tile_to_xe(m->tile);
> +       struct xe_gt *gt = m->tile->primary_gt;
> +       struct dma_fence *fence;
> +       struct xe_bb *bb;
> +       struct xe_sched_job *job;
> +       u64 first_page_dpa, clear_L0_ofs, scratch_dpa,
> scratch_L0_ofs;
> +
> +       if (!xe_device_has_flat_ccs(xe))
> +               return -EINVAL;
> +
> +       first_page_dpa = xe_vram_region_dpa_base(m->tile->mem.vram);
> +       clear_L0_ofs = xe_migrate_vram_ofs(xe, first_page_dpa, true);
> +
> +       scratch_dpa = xe_bo_addr(scratch_bo, 0, XE_PAGE_SIZE);
> +       scratch_L0_ofs = xe_migrate_vram_ofs(xe, scratch_dpa, false);
> +
> +       bb = xe_bb_new(gt, EMIT_COPY_CCS_DW + 1, xe->info.has_usm);
> +       if (IS_ERR(bb)) {
> +               drm_warn(&xe->drm, "Failed to create bb for VRAM
> overlap check\n");
> +               return PTR_ERR(bb);
> +       }
> +
> +       /* 4MB payload = 8KB CCS metadata */
> +       if (write_to_ccs) {
> +               emit_copy_ccs(gt, bb, clear_L0_ofs, true,
> +                             scratch_L0_ofs, false, SZ_4M);
> +       } else {
> +               emit_copy_ccs(gt, bb, scratch_L0_ofs, false,
> +                             clear_L0_ofs, true, SZ_4M);
> +       }
> +
> +       bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
> +
> +       job = xe_bb_create_migration_job(m->q, bb,
> +                                        xe_migrate_batch_base(m, xe-
> >info.has_usm),
> +                                        0);
> +       if (!IS_ERR(job)) {
> +               xe_sched_job_add_migrate_flush(job, MI_FLUSH_DW_CCS);
> +
> +               mutex_lock(&m->job_mutex);
> +               xe_sched_job_arm(job);
> +
> +               fence = dma_fence_get(&job->drm.s_fence->finished);
> +               xe_sched_job_push(job);
> +               mutex_unlock(&m->job_mutex);
> +
> +               dma_fence_wait(fence, false);
> +               dma_fence_put(fence);
> +       } else {
> +               drm_warn(&xe->drm, "Failed to create job for VRAM
> overlap check\n");
> +               xe_bb_free(bb, NULL);
> +               return PTR_ERR(job);
> +       }
> +
> +       xe_bb_free(bb, NULL);
> +       return 0;
> +}
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_migrate.h
> b/drivers/gpu/drm/xe/xe_migrate.h
> index c3a268b01768..a9acc62f78f0 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.h
> +++ b/drivers/gpu/drm/xe/xe_migrate.h
> @@ -182,4 +182,10 @@ static inline void
> xe_migrate_job_lock_assert(struct xe_exec_queue *q)
>  void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue
> *q);
>  void xe_migrate_job_unlock(struct xe_migrate *m, struct
> xe_exec_queue *q);
>  
> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
> +                                struct xe_bo *scratch_bo,
> +                                bool write_to_ccs);
> +#endif
> +
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_tile_types.h
> b/drivers/gpu/drm/xe/xe_tile_types.h
> index 0048100ccb72..e1368c04846a 100644
> --- a/drivers/gpu/drm/xe/xe_tile_types.h
> +++ b/drivers/gpu/drm/xe/xe_tile_types.h
> @@ -97,6 +97,10 @@ struct xe_tile {
>                  * Only main GT has page reclaim list allocations.
>                  */
>                 struct xe_sa_manager *reclaim_pool;
> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> +               /** @mem.memtest_bo: VRAM overlap check BO */
> +               struct xe_bo *memtest_bo;
> +#endif
>         } mem;
>  
>         /** @sriov: tile level virtualization data */
> diff --git a/drivers/gpu/drm/xe/xe_vram.c
> b/drivers/gpu/drm/xe/xe_vram.c
> index 0a2f1ab8416e..4a79580c5315 100644
> --- a/drivers/gpu/drm/xe/xe_vram.c
> +++ b/drivers/gpu/drm/xe/xe_vram.c
> @@ -17,8 +17,11 @@
>  #include "xe_device.h"
>  #include "xe_force_wake.h"
>  #include "xe_gt_mcr.h"
> +#include "xe_map.h"
> +#include "xe_migrate.h"
>  #include "xe_mmio.h"
>  #include "xe_sriov.h"
> +#include "xe_tile.h"
>  #include "xe_tile_sriov_vf.h"
>  #include "xe_ttm_vram_mgr.h"
>  #include "xe_vram.h"
> @@ -403,3 +406,241 @@ resource_size_t
> xe_vram_region_actual_physical_size(const struct xe_vram_region
>         return vram ? vram->actual_physical_size : 0;
>  }
>  EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size);
> +
> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> +static void memtest_bo_cleanup(void *arg)
> +{
> +       struct xe_device *xe = arg;
> +
> +       xe_vram_free_memtest_bos(xe);
> +}
> +
> +int xe_vram_reserve_memtest_bo(struct xe_device *xe)
> +{
> +       struct xe_tile *tile;
> +       u8 id;
> +
> +       if (IS_SRIOV_VF(xe))
> +               return 0;
> +
> +       for_each_tile(tile, xe, id) {
> +               u64 vram_size;
> +
> +               if (!tile->mem.vram)
> +                       continue;
> +
> +               if (tile->mem.vram->io_size < tile->mem.vram-
> >usable_size) {
> +                       drm_info(&xe->drm,
> +                                "Tile %d: Small-BAR system detected,
> skipping VRAM memtest\n",
> +                                id);
> +                       continue;
> +               }
> +
> +               vram_size = tile->mem.vram->usable_size;
> +
> +               tile->mem.memtest_bo =
> xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
> +                                                                  
> vram_size - SZ_64K,
> +                                                                  
> ttm_bo_type_kernel,
> +                                                                  
> XE_BO_FLAG_VRAM_IF_DGFX(tile),
> +                                                                  
> 0, false);
> +               if (IS_ERR(tile->mem.memtest_bo)) {
> +                       drm_warn(&xe->drm, "Tile %d: Failed to
> reserve memtest BO\n", id);
> +                       tile->mem.memtest_bo = NULL;
> +                       continue;
> +               }
> +
> +               drm_info(&xe->drm, "Tile %d: Reserved memtest BO at
> offset 0x%llx\n",
> +                        id, vram_size - SZ_64K);
> +       }
> +
> +       return devm_add_action_or_reset(xe->drm.dev,
> memtest_bo_cleanup, xe);
> +}
> +
> +void xe_vram_free_memtest_bos(struct xe_device *xe)
> +{
> +       struct xe_tile *tile;
> +       u8 id;
> +
> +       for_each_tile(tile, xe, id) {
> +               if (tile->mem.memtest_bo) {
> +                       xe_bo_unpin_map_no_vm(tile->mem.memtest_bo);
> +                       tile->mem.memtest_bo = NULL;
> +               }
> +       }
> +}
> +
> +int xe_vram_memtest(struct xe_device *xe)
> +{
> +       struct xe_tile *tile;
> +       u8 id;
> +       int err = 0;
> +
> +       if (IS_SRIOV_VF(xe))
> +               return 0;
> +
> +       for_each_tile(tile, xe, id) {
> +               struct xe_bo *last_page_bo = tile->mem.memtest_bo;
> +               struct dma_fence *fence;
> +               bool overlap = false;
> +               int i;
> +               u8 val;
> +
> +               if (!last_page_bo || !tile->migrate)
> +                       continue;
> +
> +               drm_info(&xe->drm, "Tile %d: Running VRAM
> memtest...\n", id);
> +
> +               /* CPU write and readback first and last byte of the
> last page */
> +               xe_map_wr(xe, &last_page_bo->vmap, 0, u8, 0xA5);
> +               xe_map_wr(xe, &last_page_bo->vmap, SZ_64K - 1, u8,
> 0x5A);
> +
> +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
> +               if (drm_WARN(&xe->drm, val != 0xA5,
> +                            "Tile %d: CPU memtest failed at offset 0
> (expected 0xA5, got 0x%02x)\n",
> +                            id, val)) {
> +                       err = -EIO;
> +                       goto unpin;
> +               }
> +
> +               val = xe_map_rd(xe, &last_page_bo->vmap, SZ_64K - 1,
> u8);
> +               if (drm_WARN(&xe->drm, val != 0x5A,
> +                            "Tile %d: CPU memtest failed at offset
> 65535 (expected 0x5A, got 0x%02x)\n",
> +                            id, val)) {
> +                       err = -EIO;
> +                       goto unpin;
> +               }
> +
> +               /* Non-CCS access via GPU on the last page */
> +               xe_bo_lock(last_page_bo, false);
> +               fence = xe_migrate_clear(tile->migrate, last_page_bo,
> +                                        last_page_bo->ttm.resource,
> +                                       
> XE_MIGRATE_CLEAR_FLAG_BO_DATA);
> +               xe_bo_unlock(last_page_bo);
> +
> +               if (!IS_ERR(fence)) {
> +                       dma_fence_wait(fence, false);
> +                       dma_fence_put(fence);
> +               } else {
> +                       err = PTR_ERR(fence);
> +                       goto unpin;
> +               }
> +
> +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
> +               if (drm_WARN(&xe->drm, val != 0x00,
> +                            "Tile %d: GPU memtest clear failed at
> offset 0 (expected 0x00, got 0x%02x)\n",
> +                            id, val)) {
> +                       err = -EIO;
> +                       goto unpin;
> +               }
> +
> +               /*
> +                * Check for CCS overlap on the root tile.
> +                *
> +                * TODO: maybe extend if we ever get multi-tile +
> CCS. Pay
> +                * special attention to the l2 flush below. Currently
> that is
> +                * hard coded to the root tile.
> +                */
> +               if (!id && xe_device_has_flat_ccs(xe) &&
> +                   GRAPHICS_VERx100(xe) >= 2000) {
> +                       struct xe_bo *scratch_bo_before;
> +                       struct xe_bo *scratch_bo_after;
> +
> +                       scratch_bo_before =
> xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
> +                                                                    
> ttm_bo_type_kernel,
> +                                                                    
> XE_BO_FLAG_VRAM_IF_DGFX(tile),
> +                                                                    
> false);
> +                       if (IS_ERR(scratch_bo_before)) {
> +                               err = PTR_ERR(scratch_bo_before);
> +                               goto unpin;
> +                       }
> +
> +                       scratch_bo_after =
> xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
> +                                                                   
> ttm_bo_type_kernel,
> +                                                                   
> XE_BO_FLAG_VRAM_IF_DGFX(tile),
> +                                                                   
> false);
> +                       if (IS_ERR(scratch_bo_after)) {
> +                               xe_bo_unpin_map_no_vm(scratch_bo_befo
> re);
> +                               err = PTR_ERR(scratch_bo_after);
> +                               goto unpin;
> +                       }
> +
> +                       /* Save original CCS metadata for PA 0 + */
> +                       err = xe_migrate_debug_ccs_overlap(tile-
> >migrate, scratch_bo_before, false);
> +                       if (err) {
> +                               xe_bo_unpin_map_no_vm(scratch_bo_befo
> re);
> +                               xe_bo_unpin_map_no_vm(scratch_bo_afte
> r);
> +                               goto unpin;
> +                       }
> +
> +                       /*
> +                        * Fill last page. If there is CCS overlap in
> the last
> +                        * page this will snag the raw CCS storage.
> +                        */
> +                       xe_map_memset(xe, &last_page_bo->vmap, 0,
> 0x5A, SZ_64K);
> +                       xe_device_wmb(xe);
> +
> +                       /*
> +                        * Global invalidation. Some BMG SKUs will
> cache the BAR
> +                        * writes in the GPU side VRAM cache. Make
> sure above
> +                        * writes are fully flushed out to VRAM, so
> this is
> +                        * hopefully more well behaved with the CCS
> unit, if
> +                        * there is indeed CCS overlap with normal
> VRAM. Since
> +                        * there is a separate CCS cache, the CCS
> unit might not
> +                        * respect the GPU VRAM cache for CCS
> accesses, so opt
> +                        * for being super careful here.
> +                        */
> +                       xe_device_l2_flush(xe, true);
> +
> +                       /* Use GPU to clear CCS state for PA 0 */
> +                       xe_map_memset(xe, &scratch_bo_after->vmap, 0,
> 0x00, SZ_64K);
> +                       err = xe_migrate_debug_ccs_overlap(tile-
> >migrate, scratch_bo_after, true);
> +                       if (err) {
> +                               xe_bo_unpin_map_no_vm(scratch_bo_befo
> re);
> +                               xe_bo_unpin_map_no_vm(scratch_bo_afte
> r);
> +                               goto unpin;
> +                       }
> +                       /*
> +                        * Global invalidation. Ensure CCS caches
> really are
> +                        * nuked and the raw CCS data is visible in
> VRAM, for
> +                        * the below access.
> +                        */
> +                       xe_device_l2_flush(xe, true);
> +
> +                       /* Check if last_page_bo was corrupted by the
> GPU CCS clear */
> +                       for (i = 0; i < SZ_64K; i += 8) {
> +                               u64 payload = xe_map_rd(xe,
> &last_page_bo->vmap, i, u64);
> +
> +                               if (payload != 0x5A5A5A5A5A5A5A5AULL)
> {
> +                                       overlap = true;
> +                                       break;
> +                               }
> +                       }
> +
> +                       /* Restore original CCS metadata for PA 0 +
> */
> +                       err = xe_migrate_debug_ccs_overlap(tile-
> >migrate, scratch_bo_before, true);
> +                       if (err)
> +                               drm_warn(&xe->drm, "Failed to restore
> CCS metadata\n");
> +
> +                       xe_bo_unpin_map_no_vm(scratch_bo_before);
> +                       xe_bo_unpin_map_no_vm(scratch_bo_after);
> +               }
> +
> +               if (drm_WARN(&xe->drm, overlap,
> +                            "Tile %d: VRAM bounds overlap CCS
> region! VRAM sizing is incorrect.\n",
> +                            id)) {
> +                       err = -EINVAL;
> +                       goto unpin;
> +               }
> +
> +               drm_info(&xe->drm, "Tile %d: VRAM memtest
> completed.\n", id);
> +
> +unpin:
> +               if (err)
> +                       break;
> +       }
> +
> +       xe_vram_free_memtest_bos(xe);
> +
> +       return err;
> +}
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_vram.h
> b/drivers/gpu/drm/xe/xe_vram.h
> index dd1c8bf17922..38425d81f777 100644
> --- a/drivers/gpu/drm/xe/xe_vram.h
> +++ b/drivers/gpu/drm/xe/xe_vram.h
> @@ -23,4 +23,14 @@ resource_size_t xe_vram_region_dpa_base(const
> struct xe_vram_region *vram);
>  resource_size_t xe_vram_region_usable_size(const struct
> xe_vram_region *vram);
>  resource_size_t xe_vram_region_actual_physical_size(const struct
> xe_vram_region *vram);
>  
> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> +int xe_vram_reserve_memtest_bo(struct xe_device *xe);
> +void xe_vram_free_memtest_bos(struct xe_device *xe);
> +int xe_vram_memtest(struct xe_device *xe);
> +#else
> +static inline int xe_vram_reserve_memtest_bo(struct xe_device *xe) {
> return 0; }
> +static inline void xe_vram_free_memtest_bos(struct xe_device *xe) {}
> +static inline int xe_vram_memtest(struct xe_device *xe) { return 0;
> }
> +#endif
> +
>  #endif

Re: [PATCH 5/5] drm/xe/vram: add early VRAM health check

[Matthew Auld]

On 28/08/2026 17:37, Summers, Stuart wrote:
> On Fri, 2026-08-28 at 16:14 +0100, Matthew Auld wrote:
>> During early probe, use the last page as a canary for BAR sizing, CCS
>> sizing, identity map setup etc. If something is wrong the last page
>> is
>> where we will likely find it. Hit it with everything we have. For now
> 
> Sorry coming in a little late here... but why only the last page and
> not implementing a full per byte/bit memory test to trigger any
> potential memory scanning on bit errors? Or is this not the intent
> here?

Current scope was just to catch obvious sizing errors, which will likely 
show up in the last page (BAR, CCS, identity map). In particular this 
was meant as a regression test for the bug Linus hit, where we had 
incorrect VRAM/CCS sizing.

Also, this is hopefully non-destructive, since it gets triggered in CI 
on probe. Also means it needs to be fast. We could extend this in the 
future as needed.

> 
> If this is a production scenario, the last page makes sense, but if
> we're already wrapping this in a debug config...
> 
> Thanks,
> Stuart
> 
>> this is gated behind a debug config option, so shouldn't trigger on
>> production.
>>
>> Main motivation is around CCS sizing where on some BMG cards the CCS
>> offset is programmed misaligned, for whatever reason, and our
>> handling
>> of that was busted, as found by Linus, leading to some amount of CCS
>> storage getting pulled into the allocator as normal VRAM.
>>
>> Nothing in our CI farm has such a misaligned offset it would seem,
>> however I did get this to pop on my b570, which does also have the
>> misaligned CCS offset:
>>
>>    Tile 0: Running VRAM memtest...
>>    Tile 0: VRAM bounds overlap CCS region! VRAM sizing is incorrect.
>>
>> With the fix from Linus, this goes away:
>>
>>    Tile 0: Running VRAM memtest...
>>    Tile 0: VRAM memtest completed.
>>
>> Assisted-by: Gemini:gemini-3.1-pro-preview
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Cc: Linus Torvalds <torvalds@linux-foundation.org>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_device.c     |   8 +
>>   drivers/gpu/drm/xe/xe_migrate.c    |  64 ++++++++
>>   drivers/gpu/drm/xe/xe_migrate.h    |   6 +
>>   drivers/gpu/drm/xe/xe_tile_types.h |   4 +
>>   drivers/gpu/drm/xe/xe_vram.c       | 241
>> +++++++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_vram.h       |  10 ++
>>   6 files changed, 333 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_device.c
>> b/drivers/gpu/drm/xe/xe_device.c
>> index 82e0a555fa69..80008bf5776c 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -1051,6 +1051,10 @@ int xe_device_probe(struct xe_device *xe)
>>          if (err)
>>                  return err;
>>   
>> +       err = xe_vram_reserve_memtest_bo(xe);
>> +       if (err)
>> +               return err;
>> +
>>          for_each_tile(tile, xe, id) {
>>                  err = xe_tile_init(tile);
>>                  if (err)
>> @@ -1067,6 +1071,10 @@ int xe_device_probe(struct xe_device *xe)
>>                          return err;
>>          }
>>   
>> +       err = xe_vram_memtest(xe);
>> +       if (err)
>> +               return err;
>> +
>>          err = xe_pagefault_init(xe);
>>          if (err)
>>                  return err;
>> diff --git a/drivers/gpu/drm/xe/xe_migrate.c
>> b/drivers/gpu/drm/xe/xe_migrate.c
>> index 0bf000d7c901..ff45c24d8889 100644
>> --- a/drivers/gpu/drm/xe/xe_migrate.c
>> +++ b/drivers/gpu/drm/xe/xe_migrate.c
>> @@ -2650,3 +2650,67 @@ void xe_migrate_job_lock_assert(struct
>> xe_exec_queue *q)
>>   #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
>>   #include "tests/xe_migrate.c"
>>   #endif
>> +
>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>> +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
>> +                                struct xe_bo *scratch_bo,
>> +                                bool write_to_ccs)
>> +{
>> +       struct xe_device *xe = tile_to_xe(m->tile);
>> +       struct xe_gt *gt = m->tile->primary_gt;
>> +       struct dma_fence *fence;
>> +       struct xe_bb *bb;
>> +       struct xe_sched_job *job;
>> +       u64 first_page_dpa, clear_L0_ofs, scratch_dpa,
>> scratch_L0_ofs;
>> +
>> +       if (!xe_device_has_flat_ccs(xe))
>> +               return -EINVAL;
>> +
>> +       first_page_dpa = xe_vram_region_dpa_base(m->tile->mem.vram);
>> +       clear_L0_ofs = xe_migrate_vram_ofs(xe, first_page_dpa, true);
>> +
>> +       scratch_dpa = xe_bo_addr(scratch_bo, 0, XE_PAGE_SIZE);
>> +       scratch_L0_ofs = xe_migrate_vram_ofs(xe, scratch_dpa, false);
>> +
>> +       bb = xe_bb_new(gt, EMIT_COPY_CCS_DW + 1, xe->info.has_usm);
>> +       if (IS_ERR(bb)) {
>> +               drm_warn(&xe->drm, "Failed to create bb for VRAM
>> overlap check\n");
>> +               return PTR_ERR(bb);
>> +       }
>> +
>> +       /* 4MB payload = 8KB CCS metadata */
>> +       if (write_to_ccs) {
>> +               emit_copy_ccs(gt, bb, clear_L0_ofs, true,
>> +                             scratch_L0_ofs, false, SZ_4M);
>> +       } else {
>> +               emit_copy_ccs(gt, bb, scratch_L0_ofs, false,
>> +                             clear_L0_ofs, true, SZ_4M);
>> +       }
>> +
>> +       bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
>> +
>> +       job = xe_bb_create_migration_job(m->q, bb,
>> +                                        xe_migrate_batch_base(m, xe-
>>> info.has_usm),
>> +                                        0);
>> +       if (!IS_ERR(job)) {
>> +               xe_sched_job_add_migrate_flush(job, MI_FLUSH_DW_CCS);
>> +
>> +               mutex_lock(&m->job_mutex);
>> +               xe_sched_job_arm(job);
>> +
>> +               fence = dma_fence_get(&job->drm.s_fence->finished);
>> +               xe_sched_job_push(job);
>> +               mutex_unlock(&m->job_mutex);
>> +
>> +               dma_fence_wait(fence, false);
>> +               dma_fence_put(fence);
>> +       } else {
>> +               drm_warn(&xe->drm, "Failed to create job for VRAM
>> overlap check\n");
>> +               xe_bb_free(bb, NULL);
>> +               return PTR_ERR(job);
>> +       }
>> +
>> +       xe_bb_free(bb, NULL);
>> +       return 0;
>> +}
>> +#endif
>> diff --git a/drivers/gpu/drm/xe/xe_migrate.h
>> b/drivers/gpu/drm/xe/xe_migrate.h
>> index c3a268b01768..a9acc62f78f0 100644
>> --- a/drivers/gpu/drm/xe/xe_migrate.h
>> +++ b/drivers/gpu/drm/xe/xe_migrate.h
>> @@ -182,4 +182,10 @@ static inline void
>> xe_migrate_job_lock_assert(struct xe_exec_queue *q)
>>   void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue
>> *q);
>>   void xe_migrate_job_unlock(struct xe_migrate *m, struct
>> xe_exec_queue *q);
>>   
>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>> +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
>> +                                struct xe_bo *scratch_bo,
>> +                                bool write_to_ccs);
>> +#endif
>> +
>>   #endif
>> diff --git a/drivers/gpu/drm/xe/xe_tile_types.h
>> b/drivers/gpu/drm/xe/xe_tile_types.h
>> index 0048100ccb72..e1368c04846a 100644
>> --- a/drivers/gpu/drm/xe/xe_tile_types.h
>> +++ b/drivers/gpu/drm/xe/xe_tile_types.h
>> @@ -97,6 +97,10 @@ struct xe_tile {
>>                   * Only main GT has page reclaim list allocations.
>>                   */
>>                  struct xe_sa_manager *reclaim_pool;
>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>> +               /** @mem.memtest_bo: VRAM overlap check BO */
>> +               struct xe_bo *memtest_bo;
>> +#endif
>>          } mem;
>>   
>>          /** @sriov: tile level virtualization data */
>> diff --git a/drivers/gpu/drm/xe/xe_vram.c
>> b/drivers/gpu/drm/xe/xe_vram.c
>> index 0a2f1ab8416e..4a79580c5315 100644
>> --- a/drivers/gpu/drm/xe/xe_vram.c
>> +++ b/drivers/gpu/drm/xe/xe_vram.c
>> @@ -17,8 +17,11 @@
>>   #include "xe_device.h"
>>   #include "xe_force_wake.h"
>>   #include "xe_gt_mcr.h"
>> +#include "xe_map.h"
>> +#include "xe_migrate.h"
>>   #include "xe_mmio.h"
>>   #include "xe_sriov.h"
>> +#include "xe_tile.h"
>>   #include "xe_tile_sriov_vf.h"
>>   #include "xe_ttm_vram_mgr.h"
>>   #include "xe_vram.h"
>> @@ -403,3 +406,241 @@ resource_size_t
>> xe_vram_region_actual_physical_size(const struct xe_vram_region
>>          return vram ? vram->actual_physical_size : 0;
>>   }
>>   EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size);
>> +
>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>> +static void memtest_bo_cleanup(void *arg)
>> +{
>> +       struct xe_device *xe = arg;
>> +
>> +       xe_vram_free_memtest_bos(xe);
>> +}
>> +
>> +int xe_vram_reserve_memtest_bo(struct xe_device *xe)
>> +{
>> +       struct xe_tile *tile;
>> +       u8 id;
>> +
>> +       if (IS_SRIOV_VF(xe))
>> +               return 0;
>> +
>> +       for_each_tile(tile, xe, id) {
>> +               u64 vram_size;
>> +
>> +               if (!tile->mem.vram)
>> +                       continue;
>> +
>> +               if (tile->mem.vram->io_size < tile->mem.vram-
>>> usable_size) {
>> +                       drm_info(&xe->drm,
>> +                                "Tile %d: Small-BAR system detected,
>> skipping VRAM memtest\n",
>> +                                id);
>> +                       continue;
>> +               }
>> +
>> +               vram_size = tile->mem.vram->usable_size;
>> +
>> +               tile->mem.memtest_bo =
>> xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
>> +
>> vram_size - SZ_64K,
>> +
>> ttm_bo_type_kernel,
>> +
>> XE_BO_FLAG_VRAM_IF_DGFX(tile),
>> +
>> 0, false);
>> +               if (IS_ERR(tile->mem.memtest_bo)) {
>> +                       drm_warn(&xe->drm, "Tile %d: Failed to
>> reserve memtest BO\n", id);
>> +                       tile->mem.memtest_bo = NULL;
>> +                       continue;
>> +               }
>> +
>> +               drm_info(&xe->drm, "Tile %d: Reserved memtest BO at
>> offset 0x%llx\n",
>> +                        id, vram_size - SZ_64K);
>> +       }
>> +
>> +       return devm_add_action_or_reset(xe->drm.dev,
>> memtest_bo_cleanup, xe);
>> +}
>> +
>> +void xe_vram_free_memtest_bos(struct xe_device *xe)
>> +{
>> +       struct xe_tile *tile;
>> +       u8 id;
>> +
>> +       for_each_tile(tile, xe, id) {
>> +               if (tile->mem.memtest_bo) {
>> +                       xe_bo_unpin_map_no_vm(tile->mem.memtest_bo);
>> +                       tile->mem.memtest_bo = NULL;
>> +               }
>> +       }
>> +}
>> +
>> +int xe_vram_memtest(struct xe_device *xe)
>> +{
>> +       struct xe_tile *tile;
>> +       u8 id;
>> +       int err = 0;
>> +
>> +       if (IS_SRIOV_VF(xe))
>> +               return 0;
>> +
>> +       for_each_tile(tile, xe, id) {
>> +               struct xe_bo *last_page_bo = tile->mem.memtest_bo;
>> +               struct dma_fence *fence;
>> +               bool overlap = false;
>> +               int i;
>> +               u8 val;
>> +
>> +               if (!last_page_bo || !tile->migrate)
>> +                       continue;
>> +
>> +               drm_info(&xe->drm, "Tile %d: Running VRAM
>> memtest...\n", id);
>> +
>> +               /* CPU write and readback first and last byte of the
>> last page */
>> +               xe_map_wr(xe, &last_page_bo->vmap, 0, u8, 0xA5);
>> +               xe_map_wr(xe, &last_page_bo->vmap, SZ_64K - 1, u8,
>> 0x5A);
>> +
>> +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
>> +               if (drm_WARN(&xe->drm, val != 0xA5,
>> +                            "Tile %d: CPU memtest failed at offset 0
>> (expected 0xA5, got 0x%02x)\n",
>> +                            id, val)) {
>> +                       err = -EIO;
>> +                       goto unpin;
>> +               }
>> +
>> +               val = xe_map_rd(xe, &last_page_bo->vmap, SZ_64K - 1,
>> u8);
>> +               if (drm_WARN(&xe->drm, val != 0x5A,
>> +                            "Tile %d: CPU memtest failed at offset
>> 65535 (expected 0x5A, got 0x%02x)\n",
>> +                            id, val)) {
>> +                       err = -EIO;
>> +                       goto unpin;
>> +               }
>> +
>> +               /* Non-CCS access via GPU on the last page */
>> +               xe_bo_lock(last_page_bo, false);
>> +               fence = xe_migrate_clear(tile->migrate, last_page_bo,
>> +                                        last_page_bo->ttm.resource,
>> +
>> XE_MIGRATE_CLEAR_FLAG_BO_DATA);
>> +               xe_bo_unlock(last_page_bo);
>> +
>> +               if (!IS_ERR(fence)) {
>> +                       dma_fence_wait(fence, false);
>> +                       dma_fence_put(fence);
>> +               } else {
>> +                       err = PTR_ERR(fence);
>> +                       goto unpin;
>> +               }
>> +
>> +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
>> +               if (drm_WARN(&xe->drm, val != 0x00,
>> +                            "Tile %d: GPU memtest clear failed at
>> offset 0 (expected 0x00, got 0x%02x)\n",
>> +                            id, val)) {
>> +                       err = -EIO;
>> +                       goto unpin;
>> +               }
>> +
>> +               /*
>> +                * Check for CCS overlap on the root tile.
>> +                *
>> +                * TODO: maybe extend if we ever get multi-tile +
>> CCS. Pay
>> +                * special attention to the l2 flush below. Currently
>> that is
>> +                * hard coded to the root tile.
>> +                */
>> +               if (!id && xe_device_has_flat_ccs(xe) &&
>> +                   GRAPHICS_VERx100(xe) >= 2000) {
>> +                       struct xe_bo *scratch_bo_before;
>> +                       struct xe_bo *scratch_bo_after;
>> +
>> +                       scratch_bo_before =
>> xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
>> +
>> ttm_bo_type_kernel,
>> +
>> XE_BO_FLAG_VRAM_IF_DGFX(tile),
>> +
>> false);
>> +                       if (IS_ERR(scratch_bo_before)) {
>> +                               err = PTR_ERR(scratch_bo_before);
>> +                               goto unpin;
>> +                       }
>> +
>> +                       scratch_bo_after =
>> xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
>> +
>> ttm_bo_type_kernel,
>> +
>> XE_BO_FLAG_VRAM_IF_DGFX(tile),
>> +
>> false);
>> +                       if (IS_ERR(scratch_bo_after)) {
>> +                               xe_bo_unpin_map_no_vm(scratch_bo_befo
>> re);
>> +                               err = PTR_ERR(scratch_bo_after);
>> +                               goto unpin;
>> +                       }
>> +
>> +                       /* Save original CCS metadata for PA 0 + */
>> +                       err = xe_migrate_debug_ccs_overlap(tile-
>>> migrate, scratch_bo_before, false);
>> +                       if (err) {
>> +                               xe_bo_unpin_map_no_vm(scratch_bo_befo
>> re);
>> +                               xe_bo_unpin_map_no_vm(scratch_bo_afte
>> r);
>> +                               goto unpin;
>> +                       }
>> +
>> +                       /*
>> +                        * Fill last page. If there is CCS overlap in
>> the last
>> +                        * page this will snag the raw CCS storage.
>> +                        */
>> +                       xe_map_memset(xe, &last_page_bo->vmap, 0,
>> 0x5A, SZ_64K);
>> +                       xe_device_wmb(xe);
>> +
>> +                       /*
>> +                        * Global invalidation. Some BMG SKUs will
>> cache the BAR
>> +                        * writes in the GPU side VRAM cache. Make
>> sure above
>> +                        * writes are fully flushed out to VRAM, so
>> this is
>> +                        * hopefully more well behaved with the CCS
>> unit, if
>> +                        * there is indeed CCS overlap with normal
>> VRAM. Since
>> +                        * there is a separate CCS cache, the CCS
>> unit might not
>> +                        * respect the GPU VRAM cache for CCS
>> accesses, so opt
>> +                        * for being super careful here.
>> +                        */
>> +                       xe_device_l2_flush(xe, true);
>> +
>> +                       /* Use GPU to clear CCS state for PA 0 */
>> +                       xe_map_memset(xe, &scratch_bo_after->vmap, 0,
>> 0x00, SZ_64K);
>> +                       err = xe_migrate_debug_ccs_overlap(tile-
>>> migrate, scratch_bo_after, true);
>> +                       if (err) {
>> +                               xe_bo_unpin_map_no_vm(scratch_bo_befo
>> re);
>> +                               xe_bo_unpin_map_no_vm(scratch_bo_afte
>> r);
>> +                               goto unpin;
>> +                       }
>> +                       /*
>> +                        * Global invalidation. Ensure CCS caches
>> really are
>> +                        * nuked and the raw CCS data is visible in
>> VRAM, for
>> +                        * the below access.
>> +                        */
>> +                       xe_device_l2_flush(xe, true);
>> +
>> +                       /* Check if last_page_bo was corrupted by the
>> GPU CCS clear */
>> +                       for (i = 0; i < SZ_64K; i += 8) {
>> +                               u64 payload = xe_map_rd(xe,
>> &last_page_bo->vmap, i, u64);
>> +
>> +                               if (payload != 0x5A5A5A5A5A5A5A5AULL)
>> {
>> +                                       overlap = true;
>> +                                       break;
>> +                               }
>> +                       }
>> +
>> +                       /* Restore original CCS metadata for PA 0 +
>> */
>> +                       err = xe_migrate_debug_ccs_overlap(tile-
>>> migrate, scratch_bo_before, true);
>> +                       if (err)
>> +                               drm_warn(&xe->drm, "Failed to restore
>> CCS metadata\n");
>> +
>> +                       xe_bo_unpin_map_no_vm(scratch_bo_before);
>> +                       xe_bo_unpin_map_no_vm(scratch_bo_after);
>> +               }
>> +
>> +               if (drm_WARN(&xe->drm, overlap,
>> +                            "Tile %d: VRAM bounds overlap CCS
>> region! VRAM sizing is incorrect.\n",
>> +                            id)) {
>> +                       err = -EINVAL;
>> +                       goto unpin;
>> +               }
>> +
>> +               drm_info(&xe->drm, "Tile %d: VRAM memtest
>> completed.\n", id);
>> +
>> +unpin:
>> +               if (err)
>> +                       break;
>> +       }
>> +
>> +       xe_vram_free_memtest_bos(xe);
>> +
>> +       return err;
>> +}
>> +#endif
>> diff --git a/drivers/gpu/drm/xe/xe_vram.h
>> b/drivers/gpu/drm/xe/xe_vram.h
>> index dd1c8bf17922..38425d81f777 100644
>> --- a/drivers/gpu/drm/xe/xe_vram.h
>> +++ b/drivers/gpu/drm/xe/xe_vram.h
>> @@ -23,4 +23,14 @@ resource_size_t xe_vram_region_dpa_base(const
>> struct xe_vram_region *vram);
>>   resource_size_t xe_vram_region_usable_size(const struct
>> xe_vram_region *vram);
>>   resource_size_t xe_vram_region_actual_physical_size(const struct
>> xe_vram_region *vram);
>>   
>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>> +int xe_vram_reserve_memtest_bo(struct xe_device *xe);
>> +void xe_vram_free_memtest_bos(struct xe_device *xe);
>> +int xe_vram_memtest(struct xe_device *xe);
>> +#else
>> +static inline int xe_vram_reserve_memtest_bo(struct xe_device *xe) {
>> return 0; }
>> +static inline void xe_vram_free_memtest_bos(struct xe_device *xe) {}
>> +static inline int xe_vram_memtest(struct xe_device *xe) { return 0;
>> }
>> +#endif
>> +
>>   #endif
> 

Re: [PATCH 5/5] drm/xe/vram: add early VRAM health check

[Matthew Brost]

On Tue, Sep 01, 2026 at 09:33:21AM +0100, Matthew Auld wrote:
> On 28/08/2026 17:37, Summers, Stuart wrote:
> > On Fri, 2026-08-28 at 16:14 +0100, Matthew Auld wrote:
> > > During early probe, use the last page as a canary for BAR sizing, CCS
> > > sizing, identity map setup etc. If something is wrong the last page
> > > is
> > > where we will likely find it. Hit it with everything we have. For now
> > 
> > Sorry coming in a little late here... but why only the last page and
> > not implementing a full per byte/bit memory test to trigger any
> > potential memory scanning on bit errors? Or is this not the intent
> > here?
> 
> Current scope was just to catch obvious sizing errors, which will likely
> show up in the last page (BAR, CCS, identity map). In particular this was
> meant as a regression test for the bug Linus hit, where we had incorrect
> VRAM/CCS sizing.
> 
> Also, this is hopefully non-destructive, since it gets triggered in CI on
> probe. Also means it needs to be fast. We could extend this in the future as
> needed.

+1 on the approach.

One nit with this patch: the commit message doesn't explain how the test
catches this bug, or even what the test is actually doing. I reverse
engineered the test and the code makes sense, but I'd suggest updating
the commit message to describe the test case and how it exercises the
bug.

Matt

> 
> > 
> > If this is a production scenario, the last page makes sense, but if
> > we're already wrapping this in a debug config...
> > 
> > Thanks,
> > Stuart
> > 
> > > this is gated behind a debug config option, so shouldn't trigger on
> > > production.
> > > 
> > > Main motivation is around CCS sizing where on some BMG cards the CCS
> > > offset is programmed misaligned, for whatever reason, and our
> > > handling
> > > of that was busted, as found by Linus, leading to some amount of CCS
> > > storage getting pulled into the allocator as normal VRAM.
> > > 
> > > Nothing in our CI farm has such a misaligned offset it would seem,
> > > however I did get this to pop on my b570, which does also have the
> > > misaligned CCS offset:
> > > 
> > >    Tile 0: Running VRAM memtest...
> > >    Tile 0: VRAM bounds overlap CCS region! VRAM sizing is incorrect.
> > > 
> > > With the fix from Linus, this goes away:
> > > 
> > >    Tile 0: Running VRAM memtest...
> > >    Tile 0: VRAM memtest completed.
> > > 
> > > Assisted-by: Gemini:gemini-3.1-pro-preview
> > > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > > Cc: Linus Torvalds <torvalds@linux-foundation.org>
> > > Cc: Matthew Brost <matthew.brost@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >   drivers/gpu/drm/xe/xe_device.c     |   8 +
> > >   drivers/gpu/drm/xe/xe_migrate.c    |  64 ++++++++
> > >   drivers/gpu/drm/xe/xe_migrate.h    |   6 +
> > >   drivers/gpu/drm/xe/xe_tile_types.h |   4 +
> > >   drivers/gpu/drm/xe/xe_vram.c       | 241
> > > +++++++++++++++++++++++++++++
> > >   drivers/gpu/drm/xe/xe_vram.h       |  10 ++
> > >   6 files changed, 333 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_device.c
> > > b/drivers/gpu/drm/xe/xe_device.c
> > > index 82e0a555fa69..80008bf5776c 100644
> > > --- a/drivers/gpu/drm/xe/xe_device.c
> > > +++ b/drivers/gpu/drm/xe/xe_device.c
> > > @@ -1051,6 +1051,10 @@ int xe_device_probe(struct xe_device *xe)
> > >          if (err)
> > >                  return err;
> > > +       err = xe_vram_reserve_memtest_bo(xe);
> > > +       if (err)
> > > +               return err;
> > > +
> > >          for_each_tile(tile, xe, id) {
> > >                  err = xe_tile_init(tile);
> > >                  if (err)
> > > @@ -1067,6 +1071,10 @@ int xe_device_probe(struct xe_device *xe)
> > >                          return err;
> > >          }
> > > +       err = xe_vram_memtest(xe);
> > > +       if (err)
> > > +               return err;
> > > +
> > >          err = xe_pagefault_init(xe);
> > >          if (err)
> > >                  return err;
> > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c
> > > b/drivers/gpu/drm/xe/xe_migrate.c
> > > index 0bf000d7c901..ff45c24d8889 100644
> > > --- a/drivers/gpu/drm/xe/xe_migrate.c
> > > +++ b/drivers/gpu/drm/xe/xe_migrate.c
> > > @@ -2650,3 +2650,67 @@ void xe_migrate_job_lock_assert(struct
> > > xe_exec_queue *q)
> > >   #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> > >   #include "tests/xe_migrate.c"
> > >   #endif
> > > +
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
> > > +                                struct xe_bo *scratch_bo,
> > > +                                bool write_to_ccs)
> > > +{
> > > +       struct xe_device *xe = tile_to_xe(m->tile);
> > > +       struct xe_gt *gt = m->tile->primary_gt;
> > > +       struct dma_fence *fence;
> > > +       struct xe_bb *bb;
> > > +       struct xe_sched_job *job;
> > > +       u64 first_page_dpa, clear_L0_ofs, scratch_dpa,
> > > scratch_L0_ofs;
> > > +
> > > +       if (!xe_device_has_flat_ccs(xe))
> > > +               return -EINVAL;
> > > +
> > > +       first_page_dpa = xe_vram_region_dpa_base(m->tile->mem.vram);
> > > +       clear_L0_ofs = xe_migrate_vram_ofs(xe, first_page_dpa, true);
> > > +
> > > +       scratch_dpa = xe_bo_addr(scratch_bo, 0, XE_PAGE_SIZE);
> > > +       scratch_L0_ofs = xe_migrate_vram_ofs(xe, scratch_dpa, false);
> > > +
> > > +       bb = xe_bb_new(gt, EMIT_COPY_CCS_DW + 1, xe->info.has_usm);
> > > +       if (IS_ERR(bb)) {
> > > +               drm_warn(&xe->drm, "Failed to create bb for VRAM
> > > overlap check\n");
> > > +               return PTR_ERR(bb);
> > > +       }
> > > +
> > > +       /* 4MB payload = 8KB CCS metadata */
> > > +       if (write_to_ccs) {
> > > +               emit_copy_ccs(gt, bb, clear_L0_ofs, true,
> > > +                             scratch_L0_ofs, false, SZ_4M);
> > > +       } else {
> > > +               emit_copy_ccs(gt, bb, scratch_L0_ofs, false,
> > > +                             clear_L0_ofs, true, SZ_4M);
> > > +       }
> > > +
> > > +       bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
> > > +
> > > +       job = xe_bb_create_migration_job(m->q, bb,
> > > +                                        xe_migrate_batch_base(m, xe-
> > > > info.has_usm),
> > > +                                        0);
> > > +       if (!IS_ERR(job)) {
> > > +               xe_sched_job_add_migrate_flush(job, MI_FLUSH_DW_CCS);
> > > +
> > > +               mutex_lock(&m->job_mutex);
> > > +               xe_sched_job_arm(job);
> > > +
> > > +               fence = dma_fence_get(&job->drm.s_fence->finished);
> > > +               xe_sched_job_push(job);
> > > +               mutex_unlock(&m->job_mutex);
> > > +
> > > +               dma_fence_wait(fence, false);
> > > +               dma_fence_put(fence);
> > > +       } else {
> > > +               drm_warn(&xe->drm, "Failed to create job for VRAM
> > > overlap check\n");
> > > +               xe_bb_free(bb, NULL);
> > > +               return PTR_ERR(job);
> > > +       }
> > > +
> > > +       xe_bb_free(bb, NULL);
> > > +       return 0;
> > > +}
> > > +#endif
> > > diff --git a/drivers/gpu/drm/xe/xe_migrate.h
> > > b/drivers/gpu/drm/xe/xe_migrate.h
> > > index c3a268b01768..a9acc62f78f0 100644
> > > --- a/drivers/gpu/drm/xe/xe_migrate.h
> > > +++ b/drivers/gpu/drm/xe/xe_migrate.h
> > > @@ -182,4 +182,10 @@ static inline void
> > > xe_migrate_job_lock_assert(struct xe_exec_queue *q)
> > >   void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue
> > > *q);
> > >   void xe_migrate_job_unlock(struct xe_migrate *m, struct
> > > xe_exec_queue *q);
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
> > > +                                struct xe_bo *scratch_bo,
> > > +                                bool write_to_ccs);
> > > +#endif
> > > +
> > >   #endif
> > > diff --git a/drivers/gpu/drm/xe/xe_tile_types.h
> > > b/drivers/gpu/drm/xe/xe_tile_types.h
> > > index 0048100ccb72..e1368c04846a 100644
> > > --- a/drivers/gpu/drm/xe/xe_tile_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_tile_types.h
> > > @@ -97,6 +97,10 @@ struct xe_tile {
> > >                   * Only main GT has page reclaim list allocations.
> > >                   */
> > >                  struct xe_sa_manager *reclaim_pool;
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +               /** @mem.memtest_bo: VRAM overlap check BO */
> > > +               struct xe_bo *memtest_bo;
> > > +#endif
> > >          } mem;
> > >          /** @sriov: tile level virtualization data */
> > > diff --git a/drivers/gpu/drm/xe/xe_vram.c
> > > b/drivers/gpu/drm/xe/xe_vram.c
> > > index 0a2f1ab8416e..4a79580c5315 100644
> > > --- a/drivers/gpu/drm/xe/xe_vram.c
> > > +++ b/drivers/gpu/drm/xe/xe_vram.c
> > > @@ -17,8 +17,11 @@
> > >   #include "xe_device.h"
> > >   #include "xe_force_wake.h"
> > >   #include "xe_gt_mcr.h"
> > > +#include "xe_map.h"
> > > +#include "xe_migrate.h"
> > >   #include "xe_mmio.h"
> > >   #include "xe_sriov.h"
> > > +#include "xe_tile.h"
> > >   #include "xe_tile_sriov_vf.h"
> > >   #include "xe_ttm_vram_mgr.h"
> > >   #include "xe_vram.h"
> > > @@ -403,3 +406,241 @@ resource_size_t
> > > xe_vram_region_actual_physical_size(const struct xe_vram_region
> > >          return vram ? vram->actual_physical_size : 0;
> > >   }
> > >   EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size);
> > > +
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +static void memtest_bo_cleanup(void *arg)
> > > +{
> > > +       struct xe_device *xe = arg;
> > > +
> > > +       xe_vram_free_memtest_bos(xe);
> > > +}
> > > +
> > > +int xe_vram_reserve_memtest_bo(struct xe_device *xe)
> > > +{
> > > +       struct xe_tile *tile;
> > > +       u8 id;
> > > +
> > > +       if (IS_SRIOV_VF(xe))
> > > +               return 0;
> > > +
> > > +       for_each_tile(tile, xe, id) {
> > > +               u64 vram_size;
> > > +
> > > +               if (!tile->mem.vram)
> > > +                       continue;
> > > +
> > > +               if (tile->mem.vram->io_size < tile->mem.vram-
> > > > usable_size) {
> > > +                       drm_info(&xe->drm,
> > > +                                "Tile %d: Small-BAR system detected,
> > > skipping VRAM memtest\n",
> > > +                                id);
> > > +                       continue;
> > > +               }
> > > +
> > > +               vram_size = tile->mem.vram->usable_size;
> > > +
> > > +               tile->mem.memtest_bo =
> > > xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
> > > +
> > > vram_size - SZ_64K,
> > > +
> > > ttm_bo_type_kernel,
> > > +
> > > XE_BO_FLAG_VRAM_IF_DGFX(tile),
> > > +
> > > 0, false);
> > > +               if (IS_ERR(tile->mem.memtest_bo)) {
> > > +                       drm_warn(&xe->drm, "Tile %d: Failed to
> > > reserve memtest BO\n", id);
> > > +                       tile->mem.memtest_bo = NULL;
> > > +                       continue;
> > > +               }
> > > +
> > > +               drm_info(&xe->drm, "Tile %d: Reserved memtest BO at
> > > offset 0x%llx\n",
> > > +                        id, vram_size - SZ_64K);
> > > +       }
> > > +
> > > +       return devm_add_action_or_reset(xe->drm.dev,
> > > memtest_bo_cleanup, xe);
> > > +}
> > > +
> > > +void xe_vram_free_memtest_bos(struct xe_device *xe)
> > > +{
> > > +       struct xe_tile *tile;
> > > +       u8 id;
> > > +
> > > +       for_each_tile(tile, xe, id) {
> > > +               if (tile->mem.memtest_bo) {
> > > +                       xe_bo_unpin_map_no_vm(tile->mem.memtest_bo);
> > > +                       tile->mem.memtest_bo = NULL;
> > > +               }
> > > +       }
> > > +}
> > > +
> > > +int xe_vram_memtest(struct xe_device *xe)
> > > +{
> > > +       struct xe_tile *tile;
> > > +       u8 id;
> > > +       int err = 0;
> > > +
> > > +       if (IS_SRIOV_VF(xe))
> > > +               return 0;
> > > +
> > > +       for_each_tile(tile, xe, id) {
> > > +               struct xe_bo *last_page_bo = tile->mem.memtest_bo;
> > > +               struct dma_fence *fence;
> > > +               bool overlap = false;
> > > +               int i;
> > > +               u8 val;
> > > +
> > > +               if (!last_page_bo || !tile->migrate)
> > > +                       continue;
> > > +
> > > +               drm_info(&xe->drm, "Tile %d: Running VRAM
> > > memtest...\n", id);
> > > +
> > > +               /* CPU write and readback first and last byte of the
> > > last page */
> > > +               xe_map_wr(xe, &last_page_bo->vmap, 0, u8, 0xA5);
> > > +               xe_map_wr(xe, &last_page_bo->vmap, SZ_64K - 1, u8,
> > > 0x5A);
> > > +
> > > +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
> > > +               if (drm_WARN(&xe->drm, val != 0xA5,
> > > +                            "Tile %d: CPU memtest failed at offset 0
> > > (expected 0xA5, got 0x%02x)\n",
> > > +                            id, val)) {
> > > +                       err = -EIO;
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               val = xe_map_rd(xe, &last_page_bo->vmap, SZ_64K - 1,
> > > u8);
> > > +               if (drm_WARN(&xe->drm, val != 0x5A,
> > > +                            "Tile %d: CPU memtest failed at offset
> > > 65535 (expected 0x5A, got 0x%02x)\n",
> > > +                            id, val)) {
> > > +                       err = -EIO;
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               /* Non-CCS access via GPU on the last page */
> > > +               xe_bo_lock(last_page_bo, false);
> > > +               fence = xe_migrate_clear(tile->migrate, last_page_bo,
> > > +                                        last_page_bo->ttm.resource,
> > > +
> > > XE_MIGRATE_CLEAR_FLAG_BO_DATA);
> > > +               xe_bo_unlock(last_page_bo);
> > > +
> > > +               if (!IS_ERR(fence)) {
> > > +                       dma_fence_wait(fence, false);
> > > +                       dma_fence_put(fence);
> > > +               } else {
> > > +                       err = PTR_ERR(fence);
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
> > > +               if (drm_WARN(&xe->drm, val != 0x00,
> > > +                            "Tile %d: GPU memtest clear failed at
> > > offset 0 (expected 0x00, got 0x%02x)\n",
> > > +                            id, val)) {
> > > +                       err = -EIO;
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               /*
> > > +                * Check for CCS overlap on the root tile.
> > > +                *
> > > +                * TODO: maybe extend if we ever get multi-tile +
> > > CCS. Pay
> > > +                * special attention to the l2 flush below. Currently
> > > that is
> > > +                * hard coded to the root tile.
> > > +                */
> > > +               if (!id && xe_device_has_flat_ccs(xe) &&
> > > +                   GRAPHICS_VERx100(xe) >= 2000) {
> > > +                       struct xe_bo *scratch_bo_before;
> > > +                       struct xe_bo *scratch_bo_after;
> > > +
> > > +                       scratch_bo_before =
> > > xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
> > > +
> > > ttm_bo_type_kernel,
> > > +
> > > XE_BO_FLAG_VRAM_IF_DGFX(tile),
> > > +
> > > false);
> > > +                       if (IS_ERR(scratch_bo_before)) {
> > > +                               err = PTR_ERR(scratch_bo_before);
> > > +                               goto unpin;
> > > +                       }
> > > +
> > > +                       scratch_bo_after =
> > > xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
> > > +
> > > ttm_bo_type_kernel,
> > > +
> > > XE_BO_FLAG_VRAM_IF_DGFX(tile),
> > > +
> > > false);
> > > +                       if (IS_ERR(scratch_bo_after)) {
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_befo
> > > re);
> > > +                               err = PTR_ERR(scratch_bo_after);
> > > +                               goto unpin;
> > > +                       }
> > > +
> > > +                       /* Save original CCS metadata for PA 0 + */
> > > +                       err = xe_migrate_debug_ccs_overlap(tile-
> > > > migrate, scratch_bo_before, false);
> > > +                       if (err) {
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_befo
> > > re);
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_afte
> > > r);
> > > +                               goto unpin;
> > > +                       }
> > > +
> > > +                       /*
> > > +                        * Fill last page. If there is CCS overlap in
> > > the last
> > > +                        * page this will snag the raw CCS storage.
> > > +                        */
> > > +                       xe_map_memset(xe, &last_page_bo->vmap, 0,
> > > 0x5A, SZ_64K);
> > > +                       xe_device_wmb(xe);
> > > +
> > > +                       /*
> > > +                        * Global invalidation. Some BMG SKUs will
> > > cache the BAR
> > > +                        * writes in the GPU side VRAM cache. Make
> > > sure above
> > > +                        * writes are fully flushed out to VRAM, so
> > > this is
> > > +                        * hopefully more well behaved with the CCS
> > > unit, if
> > > +                        * there is indeed CCS overlap with normal
> > > VRAM. Since
> > > +                        * there is a separate CCS cache, the CCS
> > > unit might not
> > > +                        * respect the GPU VRAM cache for CCS
> > > accesses, so opt
> > > +                        * for being super careful here.
> > > +                        */
> > > +                       xe_device_l2_flush(xe, true);
> > > +
> > > +                       /* Use GPU to clear CCS state for PA 0 */
> > > +                       xe_map_memset(xe, &scratch_bo_after->vmap, 0,
> > > 0x00, SZ_64K);
> > > +                       err = xe_migrate_debug_ccs_overlap(tile-
> > > > migrate, scratch_bo_after, true);
> > > +                       if (err) {
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_befo
> > > re);
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_afte
> > > r);
> > > +                               goto unpin;
> > > +                       }
> > > +                       /*
> > > +                        * Global invalidation. Ensure CCS caches
> > > really are
> > > +                        * nuked and the raw CCS data is visible in
> > > VRAM, for
> > > +                        * the below access.
> > > +                        */
> > > +                       xe_device_l2_flush(xe, true);
> > > +
> > > +                       /* Check if last_page_bo was corrupted by the
> > > GPU CCS clear */
> > > +                       for (i = 0; i < SZ_64K; i += 8) {
> > > +                               u64 payload = xe_map_rd(xe,
> > > &last_page_bo->vmap, i, u64);
> > > +
> > > +                               if (payload != 0x5A5A5A5A5A5A5A5AULL)
> > > {
> > > +                                       overlap = true;
> > > +                                       break;
> > > +                               }
> > > +                       }
> > > +
> > > +                       /* Restore original CCS metadata for PA 0 +
> > > */
> > > +                       err = xe_migrate_debug_ccs_overlap(tile-
> > > > migrate, scratch_bo_before, true);
> > > +                       if (err)
> > > +                               drm_warn(&xe->drm, "Failed to restore
> > > CCS metadata\n");
> > > +
> > > +                       xe_bo_unpin_map_no_vm(scratch_bo_before);
> > > +                       xe_bo_unpin_map_no_vm(scratch_bo_after);
> > > +               }
> > > +
> > > +               if (drm_WARN(&xe->drm, overlap,
> > > +                            "Tile %d: VRAM bounds overlap CCS
> > > region! VRAM sizing is incorrect.\n",
> > > +                            id)) {
> > > +                       err = -EINVAL;
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               drm_info(&xe->drm, "Tile %d: VRAM memtest
> > > completed.\n", id);
> > > +
> > > +unpin:
> > > +               if (err)
> > > +                       break;
> > > +       }
> > > +
> > > +       xe_vram_free_memtest_bos(xe);
> > > +
> > > +       return err;
> > > +}
> > > +#endif
> > > diff --git a/drivers/gpu/drm/xe/xe_vram.h
> > > b/drivers/gpu/drm/xe/xe_vram.h
> > > index dd1c8bf17922..38425d81f777 100644
> > > --- a/drivers/gpu/drm/xe/xe_vram.h
> > > +++ b/drivers/gpu/drm/xe/xe_vram.h
> > > @@ -23,4 +23,14 @@ resource_size_t xe_vram_region_dpa_base(const
> > > struct xe_vram_region *vram);
> > >   resource_size_t xe_vram_region_usable_size(const struct
> > > xe_vram_region *vram);
> > >   resource_size_t xe_vram_region_actual_physical_size(const struct
> > > xe_vram_region *vram);
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +int xe_vram_reserve_memtest_bo(struct xe_device *xe);
> > > +void xe_vram_free_memtest_bos(struct xe_device *xe);
> > > +int xe_vram_memtest(struct xe_device *xe);
> > > +#else
> > > +static inline int xe_vram_reserve_memtest_bo(struct xe_device *xe) {
> > > return 0; }
> > > +static inline void xe_vram_free_memtest_bos(struct xe_device *xe) {}
> > > +static inline int xe_vram_memtest(struct xe_device *xe) { return 0;
> > > }
> > > +#endif
> > > +
> > >   #endif
> > 
> 

Re: [PATCH 5/5] drm/xe/vram: add early VRAM health check

[Summers, Stuart]

On Tue, 2026-09-01 at 09:33 +0100, Matthew Auld wrote:
> On 28/08/2026 17:37, Summers, Stuart wrote:
> > On Fri, 2026-08-28 at 16:14 +0100, Matthew Auld wrote:
> > > During early probe, use the last page as a canary for BAR sizing,
> > > CCS
> > > sizing, identity map setup etc. If something is wrong the last
> > > page
> > > is
> > > where we will likely find it. Hit it with everything we have. For
> > > now
> > 
> > Sorry coming in a little late here... but why only the last page
> > and
> > not implementing a full per byte/bit memory test to trigger any
> > potential memory scanning on bit errors? Or is this not the intent
> > here?
> 
> Current scope was just to catch obvious sizing errors, which will
> likely 
> show up in the last page (BAR, CCS, identity map). In particular this
> was meant as a regression test for the bug Linus hit, where we had 
> incorrect VRAM/CCS sizing.
> 
> Also, this is hopefully non-destructive, since it gets triggered in
> CI 
> on probe. Also means it needs to be fast. We could extend this in the
> future as needed.

Ok yeah makes sense. Basically we're just trying to make sure the
driver does the right thing here - this isn't about hardware
validation.

I'm thinking it would be interesting to have something like what we're
doing in i915 in intel_memory_region_memtest(). This is more about
hardware validation though so I agree maybe out of scope here.

Is there a reason we didn't do this in kunit or part of the mm/memtest?

Anyway not a blocker for what you have here. For the flat ccs and BAR
pieces I agree this will work.

Thanks,
Stuart

> 
> > 
> > If this is a production scenario, the last page makes sense, but if
> > we're already wrapping this in a debug config...
> > 
> > Thanks,
> > Stuart
> > 
> > > this is gated behind a debug config option, so shouldn't trigger
> > > on
> > > production.
> > > 
> > > Main motivation is around CCS sizing where on some BMG cards the
> > > CCS
> > > offset is programmed misaligned, for whatever reason, and our
> > > handling
> > > of that was busted, as found by Linus, leading to some amount of
> > > CCS
> > > storage getting pulled into the allocator as normal VRAM.
> > > 
> > > Nothing in our CI farm has such a misaligned offset it would
> > > seem,
> > > however I did get this to pop on my b570, which does also have
> > > the
> > > misaligned CCS offset:
> > > 
> > >    Tile 0: Running VRAM memtest...
> > >    Tile 0: VRAM bounds overlap CCS region! VRAM sizing is
> > > incorrect.
> > > 
> > > With the fix from Linus, this goes away:
> > > 
> > >    Tile 0: Running VRAM memtest...
> > >    Tile 0: VRAM memtest completed.
> > > 
> > > Assisted-by: Gemini:gemini-3.1-pro-preview
> > > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > > Cc: Linus Torvalds <torvalds@linux-foundation.org>
> > > Cc: Matthew Brost <matthew.brost@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >   drivers/gpu/drm/xe/xe_device.c     |   8 +
> > >   drivers/gpu/drm/xe/xe_migrate.c    |  64 ++++++++
> > >   drivers/gpu/drm/xe/xe_migrate.h    |   6 +
> > >   drivers/gpu/drm/xe/xe_tile_types.h |   4 +
> > >   drivers/gpu/drm/xe/xe_vram.c       | 241
> > > +++++++++++++++++++++++++++++
> > >   drivers/gpu/drm/xe/xe_vram.h       |  10 ++
> > >   6 files changed, 333 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_device.c
> > > b/drivers/gpu/drm/xe/xe_device.c
> > > index 82e0a555fa69..80008bf5776c 100644
> > > --- a/drivers/gpu/drm/xe/xe_device.c
> > > +++ b/drivers/gpu/drm/xe/xe_device.c
> > > @@ -1051,6 +1051,10 @@ int xe_device_probe(struct xe_device *xe)
> > >          if (err)
> > >                  return err;
> > >   
> > > +       err = xe_vram_reserve_memtest_bo(xe);
> > > +       if (err)
> > > +               return err;
> > > +
> > >          for_each_tile(tile, xe, id) {
> > >                  err = xe_tile_init(tile);
> > >                  if (err)
> > > @@ -1067,6 +1071,10 @@ int xe_device_probe(struct xe_device *xe)
> > >                          return err;
> > >          }
> > >   
> > > +       err = xe_vram_memtest(xe);
> > > +       if (err)
> > > +               return err;
> > > +
> > >          err = xe_pagefault_init(xe);
> > >          if (err)
> > >                  return err;
> > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c
> > > b/drivers/gpu/drm/xe/xe_migrate.c
> > > index 0bf000d7c901..ff45c24d8889 100644
> > > --- a/drivers/gpu/drm/xe/xe_migrate.c
> > > +++ b/drivers/gpu/drm/xe/xe_migrate.c
> > > @@ -2650,3 +2650,67 @@ void xe_migrate_job_lock_assert(struct
> > > xe_exec_queue *q)
> > >   #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
> > >   #include "tests/xe_migrate.c"
> > >   #endif
> > > +
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
> > > +                                struct xe_bo *scratch_bo,
> > > +                                bool write_to_ccs)
> > > +{
> > > +       struct xe_device *xe = tile_to_xe(m->tile);
> > > +       struct xe_gt *gt = m->tile->primary_gt;
> > > +       struct dma_fence *fence;
> > > +       struct xe_bb *bb;
> > > +       struct xe_sched_job *job;
> > > +       u64 first_page_dpa, clear_L0_ofs, scratch_dpa,
> > > scratch_L0_ofs;
> > > +
> > > +       if (!xe_device_has_flat_ccs(xe))
> > > +               return -EINVAL;
> > > +
> > > +       first_page_dpa = xe_vram_region_dpa_base(m->tile-
> > > >mem.vram);
> > > +       clear_L0_ofs = xe_migrate_vram_ofs(xe, first_page_dpa,
> > > true);
> > > +
> > > +       scratch_dpa = xe_bo_addr(scratch_bo, 0, XE_PAGE_SIZE);
> > > +       scratch_L0_ofs = xe_migrate_vram_ofs(xe, scratch_dpa,
> > > false);
> > > +
> > > +       bb = xe_bb_new(gt, EMIT_COPY_CCS_DW + 1, xe-
> > > >info.has_usm);
> > > +       if (IS_ERR(bb)) {
> > > +               drm_warn(&xe->drm, "Failed to create bb for VRAM
> > > overlap check\n");
> > > +               return PTR_ERR(bb);
> > > +       }
> > > +
> > > +       /* 4MB payload = 8KB CCS metadata */
> > > +       if (write_to_ccs) {
> > > +               emit_copy_ccs(gt, bb, clear_L0_ofs, true,
> > > +                             scratch_L0_ofs, false, SZ_4M);
> > > +       } else {
> > > +               emit_copy_ccs(gt, bb, scratch_L0_ofs, false,
> > > +                             clear_L0_ofs, true, SZ_4M);
> > > +       }
> > > +
> > > +       bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
> > > +
> > > +       job = xe_bb_create_migration_job(m->q, bb,
> > > +                                        xe_migrate_batch_base(m,
> > > xe-
> > > > info.has_usm),
> > > +                                        0);
> > > +       if (!IS_ERR(job)) {
> > > +               xe_sched_job_add_migrate_flush(job,
> > > MI_FLUSH_DW_CCS);
> > > +
> > > +               mutex_lock(&m->job_mutex);
> > > +               xe_sched_job_arm(job);
> > > +
> > > +               fence = dma_fence_get(&job->drm.s_fence-
> > > >finished);
> > > +               xe_sched_job_push(job);
> > > +               mutex_unlock(&m->job_mutex);
> > > +
> > > +               dma_fence_wait(fence, false);
> > > +               dma_fence_put(fence);
> > > +       } else {
> > > +               drm_warn(&xe->drm, "Failed to create job for VRAM
> > > overlap check\n");
> > > +               xe_bb_free(bb, NULL);
> > > +               return PTR_ERR(job);
> > > +       }
> > > +
> > > +       xe_bb_free(bb, NULL);
> > > +       return 0;
> > > +}
> > > +#endif
> > > diff --git a/drivers/gpu/drm/xe/xe_migrate.h
> > > b/drivers/gpu/drm/xe/xe_migrate.h
> > > index c3a268b01768..a9acc62f78f0 100644
> > > --- a/drivers/gpu/drm/xe/xe_migrate.h
> > > +++ b/drivers/gpu/drm/xe/xe_migrate.h
> > > @@ -182,4 +182,10 @@ static inline void
> > > xe_migrate_job_lock_assert(struct xe_exec_queue *q)
> > >   void xe_migrate_job_lock(struct xe_migrate *m, struct
> > > xe_exec_queue
> > > *q);
> > >   void xe_migrate_job_unlock(struct xe_migrate *m, struct
> > > xe_exec_queue *q);
> > >   
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
> > > +                                struct xe_bo *scratch_bo,
> > > +                                bool write_to_ccs);
> > > +#endif
> > > +
> > >   #endif
> > > diff --git a/drivers/gpu/drm/xe/xe_tile_types.h
> > > b/drivers/gpu/drm/xe/xe_tile_types.h
> > > index 0048100ccb72..e1368c04846a 100644
> > > --- a/drivers/gpu/drm/xe/xe_tile_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_tile_types.h
> > > @@ -97,6 +97,10 @@ struct xe_tile {
> > >                   * Only main GT has page reclaim list
> > > allocations.
> > >                   */
> > >                  struct xe_sa_manager *reclaim_pool;
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +               /** @mem.memtest_bo: VRAM overlap check BO */
> > > +               struct xe_bo *memtest_bo;
> > > +#endif
> > >          } mem;
> > >   
> > >          /** @sriov: tile level virtualization data */
> > > diff --git a/drivers/gpu/drm/xe/xe_vram.c
> > > b/drivers/gpu/drm/xe/xe_vram.c
> > > index 0a2f1ab8416e..4a79580c5315 100644
> > > --- a/drivers/gpu/drm/xe/xe_vram.c
> > > +++ b/drivers/gpu/drm/xe/xe_vram.c
> > > @@ -17,8 +17,11 @@
> > >   #include "xe_device.h"
> > >   #include "xe_force_wake.h"
> > >   #include "xe_gt_mcr.h"
> > > +#include "xe_map.h"
> > > +#include "xe_migrate.h"
> > >   #include "xe_mmio.h"
> > >   #include "xe_sriov.h"
> > > +#include "xe_tile.h"
> > >   #include "xe_tile_sriov_vf.h"
> > >   #include "xe_ttm_vram_mgr.h"
> > >   #include "xe_vram.h"
> > > @@ -403,3 +406,241 @@ resource_size_t
> > > xe_vram_region_actual_physical_size(const struct xe_vram_region
> > >          return vram ? vram->actual_physical_size : 0;
> > >   }
> > >   EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size);
> > > +
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +static void memtest_bo_cleanup(void *arg)
> > > +{
> > > +       struct xe_device *xe = arg;
> > > +
> > > +       xe_vram_free_memtest_bos(xe);
> > > +}
> > > +
> > > +int xe_vram_reserve_memtest_bo(struct xe_device *xe)
> > > +{
> > > +       struct xe_tile *tile;
> > > +       u8 id;
> > > +
> > > +       if (IS_SRIOV_VF(xe))
> > > +               return 0;
> > > +
> > > +       for_each_tile(tile, xe, id) {
> > > +               u64 vram_size;
> > > +
> > > +               if (!tile->mem.vram)
> > > +                       continue;
> > > +
> > > +               if (tile->mem.vram->io_size < tile->mem.vram-
> > > > usable_size) {
> > > +                       drm_info(&xe->drm,
> > > +                                "Tile %d: Small-BAR system
> > > detected,
> > > skipping VRAM memtest\n",
> > > +                                id);
> > > +                       continue;
> > > +               }
> > > +
> > > +               vram_size = tile->mem.vram->usable_size;
> > > +
> > > +               tile->mem.memtest_bo =
> > > xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
> > > +
> > > vram_size - SZ_64K,
> > > +
> > > ttm_bo_type_kernel,
> > > +
> > > XE_BO_FLAG_VRAM_IF_DGFX(tile),
> > > +
> > > 0, false);
> > > +               if (IS_ERR(tile->mem.memtest_bo)) {
> > > +                       drm_warn(&xe->drm, "Tile %d: Failed to
> > > reserve memtest BO\n", id);
> > > +                       tile->mem.memtest_bo = NULL;
> > > +                       continue;
> > > +               }
> > > +
> > > +               drm_info(&xe->drm, "Tile %d: Reserved memtest BO
> > > at
> > > offset 0x%llx\n",
> > > +                        id, vram_size - SZ_64K);
> > > +       }
> > > +
> > > +       return devm_add_action_or_reset(xe->drm.dev,
> > > memtest_bo_cleanup, xe);
> > > +}
> > > +
> > > +void xe_vram_free_memtest_bos(struct xe_device *xe)
> > > +{
> > > +       struct xe_tile *tile;
> > > +       u8 id;
> > > +
> > > +       for_each_tile(tile, xe, id) {
> > > +               if (tile->mem.memtest_bo) {
> > > +                       xe_bo_unpin_map_no_vm(tile-
> > > >mem.memtest_bo);
> > > +                       tile->mem.memtest_bo = NULL;
> > > +               }
> > > +       }
> > > +}
> > > +
> > > +int xe_vram_memtest(struct xe_device *xe)
> > > +{
> > > +       struct xe_tile *tile;
> > > +       u8 id;
> > > +       int err = 0;
> > > +
> > > +       if (IS_SRIOV_VF(xe))
> > > +               return 0;
> > > +
> > > +       for_each_tile(tile, xe, id) {
> > > +               struct xe_bo *last_page_bo = tile-
> > > >mem.memtest_bo;
> > > +               struct dma_fence *fence;
> > > +               bool overlap = false;
> > > +               int i;
> > > +               u8 val;
> > > +
> > > +               if (!last_page_bo || !tile->migrate)
> > > +                       continue;
> > > +
> > > +               drm_info(&xe->drm, "Tile %d: Running VRAM
> > > memtest...\n", id);
> > > +
> > > +               /* CPU write and readback first and last byte of
> > > the
> > > last page */
> > > +               xe_map_wr(xe, &last_page_bo->vmap, 0, u8, 0xA5);
> > > +               xe_map_wr(xe, &last_page_bo->vmap, SZ_64K - 1,
> > > u8,
> > > 0x5A);
> > > +
> > > +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
> > > +               if (drm_WARN(&xe->drm, val != 0xA5,
> > > +                            "Tile %d: CPU memtest failed at
> > > offset 0
> > > (expected 0xA5, got 0x%02x)\n",
> > > +                            id, val)) {
> > > +                       err = -EIO;
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               val = xe_map_rd(xe, &last_page_bo->vmap, SZ_64K -
> > > 1,
> > > u8);
> > > +               if (drm_WARN(&xe->drm, val != 0x5A,
> > > +                            "Tile %d: CPU memtest failed at
> > > offset
> > > 65535 (expected 0x5A, got 0x%02x)\n",
> > > +                            id, val)) {
> > > +                       err = -EIO;
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               /* Non-CCS access via GPU on the last page */
> > > +               xe_bo_lock(last_page_bo, false);
> > > +               fence = xe_migrate_clear(tile->migrate,
> > > last_page_bo,
> > > +                                        last_page_bo-
> > > >ttm.resource,
> > > +
> > > XE_MIGRATE_CLEAR_FLAG_BO_DATA);
> > > +               xe_bo_unlock(last_page_bo);
> > > +
> > > +               if (!IS_ERR(fence)) {
> > > +                       dma_fence_wait(fence, false);
> > > +                       dma_fence_put(fence);
> > > +               } else {
> > > +                       err = PTR_ERR(fence);
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
> > > +               if (drm_WARN(&xe->drm, val != 0x00,
> > > +                            "Tile %d: GPU memtest clear failed
> > > at
> > > offset 0 (expected 0x00, got 0x%02x)\n",
> > > +                            id, val)) {
> > > +                       err = -EIO;
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               /*
> > > +                * Check for CCS overlap on the root tile.
> > > +                *
> > > +                * TODO: maybe extend if we ever get multi-tile +
> > > CCS. Pay
> > > +                * special attention to the l2 flush below.
> > > Currently
> > > that is
> > > +                * hard coded to the root tile.
> > > +                */
> > > +               if (!id && xe_device_has_flat_ccs(xe) &&
> > > +                   GRAPHICS_VERx100(xe) >= 2000) {
> > > +                       struct xe_bo *scratch_bo_before;
> > > +                       struct xe_bo *scratch_bo_after;
> > > +
> > > +                       scratch_bo_before =
> > > xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
> > > +
> > > ttm_bo_type_kernel,
> > > +
> > > XE_BO_FLAG_VRAM_IF_DGFX(tile),
> > > +
> > > false);
> > > +                       if (IS_ERR(scratch_bo_before)) {
> > > +                               err = PTR_ERR(scratch_bo_before);
> > > +                               goto unpin;
> > > +                       }
> > > +
> > > +                       scratch_bo_after =
> > > xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
> > > +
> > > ttm_bo_type_kernel,
> > > +
> > > XE_BO_FLAG_VRAM_IF_DGFX(tile),
> > > +
> > > false);
> > > +                       if (IS_ERR(scratch_bo_after)) {
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_
> > > befo
> > > re);
> > > +                               err = PTR_ERR(scratch_bo_after);
> > > +                               goto unpin;
> > > +                       }
> > > +
> > > +                       /* Save original CCS metadata for PA 0 +
> > > */
> > > +                       err = xe_migrate_debug_ccs_overlap(tile-
> > > > migrate, scratch_bo_before, false);
> > > +                       if (err) {
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_
> > > befo
> > > re);
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_
> > > afte
> > > r);
> > > +                               goto unpin;
> > > +                       }
> > > +
> > > +                       /*
> > > +                        * Fill last page. If there is CCS
> > > overlap in
> > > the last
> > > +                        * page this will snag the raw CCS
> > > storage.
> > > +                        */
> > > +                       xe_map_memset(xe, &last_page_bo->vmap, 0,
> > > 0x5A, SZ_64K);
> > > +                       xe_device_wmb(xe);
> > > +
> > > +                       /*
> > > +                        * Global invalidation. Some BMG SKUs
> > > will
> > > cache the BAR
> > > +                        * writes in the GPU side VRAM cache.
> > > Make
> > > sure above
> > > +                        * writes are fully flushed out to VRAM,
> > > so
> > > this is
> > > +                        * hopefully more well behaved with the
> > > CCS
> > > unit, if
> > > +                        * there is indeed CCS overlap with
> > > normal
> > > VRAM. Since
> > > +                        * there is a separate CCS cache, the CCS
> > > unit might not
> > > +                        * respect the GPU VRAM cache for CCS
> > > accesses, so opt
> > > +                        * for being super careful here.
> > > +                        */
> > > +                       xe_device_l2_flush(xe, true);
> > > +
> > > +                       /* Use GPU to clear CCS state for PA 0 */
> > > +                       xe_map_memset(xe, &scratch_bo_after-
> > > >vmap, 0,
> > > 0x00, SZ_64K);
> > > +                       err = xe_migrate_debug_ccs_overlap(tile-
> > > > migrate, scratch_bo_after, true);
> > > +                       if (err) {
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_
> > > befo
> > > re);
> > > +                               xe_bo_unpin_map_no_vm(scratch_bo_
> > > afte
> > > r);
> > > +                               goto unpin;
> > > +                       }
> > > +                       /*
> > > +                        * Global invalidation. Ensure CCS caches
> > > really are
> > > +                        * nuked and the raw CCS data is visible
> > > in
> > > VRAM, for
> > > +                        * the below access.
> > > +                        */
> > > +                       xe_device_l2_flush(xe, true);
> > > +
> > > +                       /* Check if last_page_bo was corrupted by
> > > the
> > > GPU CCS clear */
> > > +                       for (i = 0; i < SZ_64K; i += 8) {
> > > +                               u64 payload = xe_map_rd(xe,
> > > &last_page_bo->vmap, i, u64);
> > > +
> > > +                               if (payload !=
> > > 0x5A5A5A5A5A5A5A5AULL)
> > > {
> > > +                                       overlap = true;
> > > +                                       break;
> > > +                               }
> > > +                       }
> > > +
> > > +                       /* Restore original CCS metadata for PA 0
> > > +
> > > */
> > > +                       err = xe_migrate_debug_ccs_overlap(tile-
> > > > migrate, scratch_bo_before, true);
> > > +                       if (err)
> > > +                               drm_warn(&xe->drm, "Failed to
> > > restore
> > > CCS metadata\n");
> > > +
> > > +                       xe_bo_unpin_map_no_vm(scratch_bo_before);
> > > +                       xe_bo_unpin_map_no_vm(scratch_bo_after);
> > > +               }
> > > +
> > > +               if (drm_WARN(&xe->drm, overlap,
> > > +                            "Tile %d: VRAM bounds overlap CCS
> > > region! VRAM sizing is incorrect.\n",
> > > +                            id)) {
> > > +                       err = -EINVAL;
> > > +                       goto unpin;
> > > +               }
> > > +
> > > +               drm_info(&xe->drm, "Tile %d: VRAM memtest
> > > completed.\n", id);
> > > +
> > > +unpin:
> > > +               if (err)
> > > +                       break;
> > > +       }
> > > +
> > > +       xe_vram_free_memtest_bos(xe);
> > > +
> > > +       return err;
> > > +}
> > > +#endif
> > > diff --git a/drivers/gpu/drm/xe/xe_vram.h
> > > b/drivers/gpu/drm/xe/xe_vram.h
> > > index dd1c8bf17922..38425d81f777 100644
> > > --- a/drivers/gpu/drm/xe/xe_vram.h
> > > +++ b/drivers/gpu/drm/xe/xe_vram.h
> > > @@ -23,4 +23,14 @@ resource_size_t xe_vram_region_dpa_base(const
> > > struct xe_vram_region *vram);
> > >   resource_size_t xe_vram_region_usable_size(const struct
> > > xe_vram_region *vram);
> > >   resource_size_t xe_vram_region_actual_physical_size(const
> > > struct
> > > xe_vram_region *vram);
> > >   
> > > +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
> > > +int xe_vram_reserve_memtest_bo(struct xe_device *xe);
> > > +void xe_vram_free_memtest_bos(struct xe_device *xe);
> > > +int xe_vram_memtest(struct xe_device *xe);
> > > +#else
> > > +static inline int xe_vram_reserve_memtest_bo(struct xe_device
> > > *xe) {
> > > return 0; }
> > > +static inline void xe_vram_free_memtest_bos(struct xe_device
> > > *xe) {}
> > > +static inline int xe_vram_memtest(struct xe_device *xe) { return
> > > 0;
> > > }
> > > +#endif
> > > +
> > >   #endif
> > 
> 

Re: [PATCH 5/5] drm/xe/vram: add early VRAM health check

[Matthew Auld]

On 02/09/2026 21:34, Summers, Stuart wrote:
> On Tue, 2026-09-01 at 09:33 +0100, Matthew Auld wrote:
>> On 28/08/2026 17:37, Summers, Stuart wrote:
>>> On Fri, 2026-08-28 at 16:14 +0100, Matthew Auld wrote:
>>>> During early probe, use the last page as a canary for BAR sizing,
>>>> CCS
>>>> sizing, identity map setup etc. If something is wrong the last
>>>> page
>>>> is
>>>> where we will likely find it. Hit it with everything we have. For
>>>> now
>>>
>>> Sorry coming in a little late here... but why only the last page
>>> and
>>> not implementing a full per byte/bit memory test to trigger any
>>> potential memory scanning on bit errors? Or is this not the intent
>>> here?
>>
>> Current scope was just to catch obvious sizing errors, which will
>> likely
>> show up in the last page (BAR, CCS, identity map). In particular this
>> was meant as a regression test for the bug Linus hit, where we had
>> incorrect VRAM/CCS sizing.
>>
>> Also, this is hopefully non-destructive, since it gets triggered in
>> CI
>> on probe. Also means it needs to be fast. We could extend this in the
>> future as needed.
> 
> Ok yeah makes sense. Basically we're just trying to make sure the
> driver does the right thing here - this isn't about hardware
> validation.
> 
> I'm thinking it would be interesting to have something like what we're
> doing in i915 in intel_memory_region_memtest(). This is more about
> hardware validation though so I agree maybe out of scope here.

Yeah, that is something we could explore.

> 
> Is there a reason we didn't do this in kunit or part of the mm/memtest?

Not sure how we could do this in mm/memtest? AFAICT that is more for low 
level CPU access to some memory range. For something like the CCS bug, 
you would not find it with that. Writing to the CCS portion using the 
CPU looks normal, so not sure how you would detect it with that alone.

We need working GPU submission so we can trigger something like 
XY_CTRL_SURF_COPY_BLT. I think the only way to detect the CCS issue is 
to have the GPU interact with the CCS in some way. But at this point we 
also can't just globber everything in VRAM without killing the machine.

For kunit, if there is way to inject that into the probe sequence (post 
migration layer) then that might work. But also we need to reserve the 
last page as a separate step much earlier in the probe sequence, to stop 
something stealing it, and then release it after the test part. Probe 
should also fail if we detect an issue. Would that be a good fit for kunit?

> 
> Anyway not a blocker for what you have here. For the flat ccs and BAR
> pieces I agree this will work.
> 
> Thanks,
> Stuart
> 
>>
>>>
>>> If this is a production scenario, the last page makes sense, but if
>>> we're already wrapping this in a debug config...
>>>
>>> Thanks,
>>> Stuart
>>>
>>>> this is gated behind a debug config option, so shouldn't trigger
>>>> on
>>>> production.
>>>>
>>>> Main motivation is around CCS sizing where on some BMG cards the
>>>> CCS
>>>> offset is programmed misaligned, for whatever reason, and our
>>>> handling
>>>> of that was busted, as found by Linus, leading to some amount of
>>>> CCS
>>>> storage getting pulled into the allocator as normal VRAM.
>>>>
>>>> Nothing in our CI farm has such a misaligned offset it would
>>>> seem,
>>>> however I did get this to pop on my b570, which does also have
>>>> the
>>>> misaligned CCS offset:
>>>>
>>>>     Tile 0: Running VRAM memtest...
>>>>     Tile 0: VRAM bounds overlap CCS region! VRAM sizing is
>>>> incorrect.
>>>>
>>>> With the fix from Linus, this goes away:
>>>>
>>>>     Tile 0: Running VRAM memtest...
>>>>     Tile 0: VRAM memtest completed.
>>>>
>>>> Assisted-by: Gemini:gemini-3.1-pro-preview
>>>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>>>> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>>>> Cc: Linus Torvalds <torvalds@linux-foundation.org>
>>>> Cc: Matthew Brost <matthew.brost@intel.com>
>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/xe/xe_device.c     |   8 +
>>>>    drivers/gpu/drm/xe/xe_migrate.c    |  64 ++++++++
>>>>    drivers/gpu/drm/xe/xe_migrate.h    |   6 +
>>>>    drivers/gpu/drm/xe/xe_tile_types.h |   4 +
>>>>    drivers/gpu/drm/xe/xe_vram.c       | 241
>>>> +++++++++++++++++++++++++++++
>>>>    drivers/gpu/drm/xe/xe_vram.h       |  10 ++
>>>>    6 files changed, 333 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_device.c
>>>> b/drivers/gpu/drm/xe/xe_device.c
>>>> index 82e0a555fa69..80008bf5776c 100644
>>>> --- a/drivers/gpu/drm/xe/xe_device.c
>>>> +++ b/drivers/gpu/drm/xe/xe_device.c
>>>> @@ -1051,6 +1051,10 @@ int xe_device_probe(struct xe_device *xe)
>>>>           if (err)
>>>>                   return err;
>>>>    
>>>> +       err = xe_vram_reserve_memtest_bo(xe);
>>>> +       if (err)
>>>> +               return err;
>>>> +
>>>>           for_each_tile(tile, xe, id) {
>>>>                   err = xe_tile_init(tile);
>>>>                   if (err)
>>>> @@ -1067,6 +1071,10 @@ int xe_device_probe(struct xe_device *xe)
>>>>                           return err;
>>>>           }
>>>>    
>>>> +       err = xe_vram_memtest(xe);
>>>> +       if (err)
>>>> +               return err;
>>>> +
>>>>           err = xe_pagefault_init(xe);
>>>>           if (err)
>>>>                   return err;
>>>> diff --git a/drivers/gpu/drm/xe/xe_migrate.c
>>>> b/drivers/gpu/drm/xe/xe_migrate.c
>>>> index 0bf000d7c901..ff45c24d8889 100644
>>>> --- a/drivers/gpu/drm/xe/xe_migrate.c
>>>> +++ b/drivers/gpu/drm/xe/xe_migrate.c
>>>> @@ -2650,3 +2650,67 @@ void xe_migrate_job_lock_assert(struct
>>>> xe_exec_queue *q)
>>>>    #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
>>>>    #include "tests/xe_migrate.c"
>>>>    #endif
>>>> +
>>>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>>>> +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
>>>> +                                struct xe_bo *scratch_bo,
>>>> +                                bool write_to_ccs)
>>>> +{
>>>> +       struct xe_device *xe = tile_to_xe(m->tile);
>>>> +       struct xe_gt *gt = m->tile->primary_gt;
>>>> +       struct dma_fence *fence;
>>>> +       struct xe_bb *bb;
>>>> +       struct xe_sched_job *job;
>>>> +       u64 first_page_dpa, clear_L0_ofs, scratch_dpa,
>>>> scratch_L0_ofs;
>>>> +
>>>> +       if (!xe_device_has_flat_ccs(xe))
>>>> +               return -EINVAL;
>>>> +
>>>> +       first_page_dpa = xe_vram_region_dpa_base(m->tile-
>>>>> mem.vram);
>>>> +       clear_L0_ofs = xe_migrate_vram_ofs(xe, first_page_dpa,
>>>> true);
>>>> +
>>>> +       scratch_dpa = xe_bo_addr(scratch_bo, 0, XE_PAGE_SIZE);
>>>> +       scratch_L0_ofs = xe_migrate_vram_ofs(xe, scratch_dpa,
>>>> false);
>>>> +
>>>> +       bb = xe_bb_new(gt, EMIT_COPY_CCS_DW + 1, xe-
>>>>> info.has_usm);
>>>> +       if (IS_ERR(bb)) {
>>>> +               drm_warn(&xe->drm, "Failed to create bb for VRAM
>>>> overlap check\n");
>>>> +               return PTR_ERR(bb);
>>>> +       }
>>>> +
>>>> +       /* 4MB payload = 8KB CCS metadata */
>>>> +       if (write_to_ccs) {
>>>> +               emit_copy_ccs(gt, bb, clear_L0_ofs, true,
>>>> +                             scratch_L0_ofs, false, SZ_4M);
>>>> +       } else {
>>>> +               emit_copy_ccs(gt, bb, scratch_L0_ofs, false,
>>>> +                             clear_L0_ofs, true, SZ_4M);
>>>> +       }
>>>> +
>>>> +       bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
>>>> +
>>>> +       job = xe_bb_create_migration_job(m->q, bb,
>>>> +                                        xe_migrate_batch_base(m,
>>>> xe-
>>>>> info.has_usm),
>>>> +                                        0);
>>>> +       if (!IS_ERR(job)) {
>>>> +               xe_sched_job_add_migrate_flush(job,
>>>> MI_FLUSH_DW_CCS);
>>>> +
>>>> +               mutex_lock(&m->job_mutex);
>>>> +               xe_sched_job_arm(job);
>>>> +
>>>> +               fence = dma_fence_get(&job->drm.s_fence-
>>>>> finished);
>>>> +               xe_sched_job_push(job);
>>>> +               mutex_unlock(&m->job_mutex);
>>>> +
>>>> +               dma_fence_wait(fence, false);
>>>> +               dma_fence_put(fence);
>>>> +       } else {
>>>> +               drm_warn(&xe->drm, "Failed to create job for VRAM
>>>> overlap check\n");
>>>> +               xe_bb_free(bb, NULL);
>>>> +               return PTR_ERR(job);
>>>> +       }
>>>> +
>>>> +       xe_bb_free(bb, NULL);
>>>> +       return 0;
>>>> +}
>>>> +#endif
>>>> diff --git a/drivers/gpu/drm/xe/xe_migrate.h
>>>> b/drivers/gpu/drm/xe/xe_migrate.h
>>>> index c3a268b01768..a9acc62f78f0 100644
>>>> --- a/drivers/gpu/drm/xe/xe_migrate.h
>>>> +++ b/drivers/gpu/drm/xe/xe_migrate.h
>>>> @@ -182,4 +182,10 @@ static inline void
>>>> xe_migrate_job_lock_assert(struct xe_exec_queue *q)
>>>>    void xe_migrate_job_lock(struct xe_migrate *m, struct
>>>> xe_exec_queue
>>>> *q);
>>>>    void xe_migrate_job_unlock(struct xe_migrate *m, struct
>>>> xe_exec_queue *q);
>>>>    
>>>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>>>> +int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
>>>> +                                struct xe_bo *scratch_bo,
>>>> +                                bool write_to_ccs);
>>>> +#endif
>>>> +
>>>>    #endif
>>>> diff --git a/drivers/gpu/drm/xe/xe_tile_types.h
>>>> b/drivers/gpu/drm/xe/xe_tile_types.h
>>>> index 0048100ccb72..e1368c04846a 100644
>>>> --- a/drivers/gpu/drm/xe/xe_tile_types.h
>>>> +++ b/drivers/gpu/drm/xe/xe_tile_types.h
>>>> @@ -97,6 +97,10 @@ struct xe_tile {
>>>>                    * Only main GT has page reclaim list
>>>> allocations.
>>>>                    */
>>>>                   struct xe_sa_manager *reclaim_pool;
>>>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>>>> +               /** @mem.memtest_bo: VRAM overlap check BO */
>>>> +               struct xe_bo *memtest_bo;
>>>> +#endif
>>>>           } mem;
>>>>    
>>>>           /** @sriov: tile level virtualization data */
>>>> diff --git a/drivers/gpu/drm/xe/xe_vram.c
>>>> b/drivers/gpu/drm/xe/xe_vram.c
>>>> index 0a2f1ab8416e..4a79580c5315 100644
>>>> --- a/drivers/gpu/drm/xe/xe_vram.c
>>>> +++ b/drivers/gpu/drm/xe/xe_vram.c
>>>> @@ -17,8 +17,11 @@
>>>>    #include "xe_device.h"
>>>>    #include "xe_force_wake.h"
>>>>    #include "xe_gt_mcr.h"
>>>> +#include "xe_map.h"
>>>> +#include "xe_migrate.h"
>>>>    #include "xe_mmio.h"
>>>>    #include "xe_sriov.h"
>>>> +#include "xe_tile.h"
>>>>    #include "xe_tile_sriov_vf.h"
>>>>    #include "xe_ttm_vram_mgr.h"
>>>>    #include "xe_vram.h"
>>>> @@ -403,3 +406,241 @@ resource_size_t
>>>> xe_vram_region_actual_physical_size(const struct xe_vram_region
>>>>           return vram ? vram->actual_physical_size : 0;
>>>>    }
>>>>    EXPORT_SYMBOL_IF_KUNIT(xe_vram_region_actual_physical_size);
>>>> +
>>>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>>>> +static void memtest_bo_cleanup(void *arg)
>>>> +{
>>>> +       struct xe_device *xe = arg;
>>>> +
>>>> +       xe_vram_free_memtest_bos(xe);
>>>> +}
>>>> +
>>>> +int xe_vram_reserve_memtest_bo(struct xe_device *xe)
>>>> +{
>>>> +       struct xe_tile *tile;
>>>> +       u8 id;
>>>> +
>>>> +       if (IS_SRIOV_VF(xe))
>>>> +               return 0;
>>>> +
>>>> +       for_each_tile(tile, xe, id) {
>>>> +               u64 vram_size;
>>>> +
>>>> +               if (!tile->mem.vram)
>>>> +                       continue;
>>>> +
>>>> +               if (tile->mem.vram->io_size < tile->mem.vram-
>>>>> usable_size) {
>>>> +                       drm_info(&xe->drm,
>>>> +                                "Tile %d: Small-BAR system
>>>> detected,
>>>> skipping VRAM memtest\n",
>>>> +                                id);
>>>> +                       continue;
>>>> +               }
>>>> +
>>>> +               vram_size = tile->mem.vram->usable_size;
>>>> +
>>>> +               tile->mem.memtest_bo =
>>>> xe_bo_create_pin_map_at_novm(xe, tile, SZ_64K,
>>>> +
>>>> vram_size - SZ_64K,
>>>> +
>>>> ttm_bo_type_kernel,
>>>> +
>>>> XE_BO_FLAG_VRAM_IF_DGFX(tile),
>>>> +
>>>> 0, false);
>>>> +               if (IS_ERR(tile->mem.memtest_bo)) {
>>>> +                       drm_warn(&xe->drm, "Tile %d: Failed to
>>>> reserve memtest BO\n", id);
>>>> +                       tile->mem.memtest_bo = NULL;
>>>> +                       continue;
>>>> +               }
>>>> +
>>>> +               drm_info(&xe->drm, "Tile %d: Reserved memtest BO
>>>> at
>>>> offset 0x%llx\n",
>>>> +                        id, vram_size - SZ_64K);
>>>> +       }
>>>> +
>>>> +       return devm_add_action_or_reset(xe->drm.dev,
>>>> memtest_bo_cleanup, xe);
>>>> +}
>>>> +
>>>> +void xe_vram_free_memtest_bos(struct xe_device *xe)
>>>> +{
>>>> +       struct xe_tile *tile;
>>>> +       u8 id;
>>>> +
>>>> +       for_each_tile(tile, xe, id) {
>>>> +               if (tile->mem.memtest_bo) {
>>>> +                       xe_bo_unpin_map_no_vm(tile-
>>>>> mem.memtest_bo);
>>>> +                       tile->mem.memtest_bo = NULL;
>>>> +               }
>>>> +       }
>>>> +}
>>>> +
>>>> +int xe_vram_memtest(struct xe_device *xe)
>>>> +{
>>>> +       struct xe_tile *tile;
>>>> +       u8 id;
>>>> +       int err = 0;
>>>> +
>>>> +       if (IS_SRIOV_VF(xe))
>>>> +               return 0;
>>>> +
>>>> +       for_each_tile(tile, xe, id) {
>>>> +               struct xe_bo *last_page_bo = tile-
>>>>> mem.memtest_bo;
>>>> +               struct dma_fence *fence;
>>>> +               bool overlap = false;
>>>> +               int i;
>>>> +               u8 val;
>>>> +
>>>> +               if (!last_page_bo || !tile->migrate)
>>>> +                       continue;
>>>> +
>>>> +               drm_info(&xe->drm, "Tile %d: Running VRAM
>>>> memtest...\n", id);
>>>> +
>>>> +               /* CPU write and readback first and last byte of
>>>> the
>>>> last page */
>>>> +               xe_map_wr(xe, &last_page_bo->vmap, 0, u8, 0xA5);
>>>> +               xe_map_wr(xe, &last_page_bo->vmap, SZ_64K - 1,
>>>> u8,
>>>> 0x5A);
>>>> +
>>>> +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
>>>> +               if (drm_WARN(&xe->drm, val != 0xA5,
>>>> +                            "Tile %d: CPU memtest failed at
>>>> offset 0
>>>> (expected 0xA5, got 0x%02x)\n",
>>>> +                            id, val)) {
>>>> +                       err = -EIO;
>>>> +                       goto unpin;
>>>> +               }
>>>> +
>>>> +               val = xe_map_rd(xe, &last_page_bo->vmap, SZ_64K -
>>>> 1,
>>>> u8);
>>>> +               if (drm_WARN(&xe->drm, val != 0x5A,
>>>> +                            "Tile %d: CPU memtest failed at
>>>> offset
>>>> 65535 (expected 0x5A, got 0x%02x)\n",
>>>> +                            id, val)) {
>>>> +                       err = -EIO;
>>>> +                       goto unpin;
>>>> +               }
>>>> +
>>>> +               /* Non-CCS access via GPU on the last page */
>>>> +               xe_bo_lock(last_page_bo, false);
>>>> +               fence = xe_migrate_clear(tile->migrate,
>>>> last_page_bo,
>>>> +                                        last_page_bo-
>>>>> ttm.resource,
>>>> +
>>>> XE_MIGRATE_CLEAR_FLAG_BO_DATA);
>>>> +               xe_bo_unlock(last_page_bo);
>>>> +
>>>> +               if (!IS_ERR(fence)) {
>>>> +                       dma_fence_wait(fence, false);
>>>> +                       dma_fence_put(fence);
>>>> +               } else {
>>>> +                       err = PTR_ERR(fence);
>>>> +                       goto unpin;
>>>> +               }
>>>> +
>>>> +               val = xe_map_rd(xe, &last_page_bo->vmap, 0, u8);
>>>> +               if (drm_WARN(&xe->drm, val != 0x00,
>>>> +                            "Tile %d: GPU memtest clear failed
>>>> at
>>>> offset 0 (expected 0x00, got 0x%02x)\n",
>>>> +                            id, val)) {
>>>> +                       err = -EIO;
>>>> +                       goto unpin;
>>>> +               }
>>>> +
>>>> +               /*
>>>> +                * Check for CCS overlap on the root tile.
>>>> +                *
>>>> +                * TODO: maybe extend if we ever get multi-tile +
>>>> CCS. Pay
>>>> +                * special attention to the l2 flush below.
>>>> Currently
>>>> that is
>>>> +                * hard coded to the root tile.
>>>> +                */
>>>> +               if (!id && xe_device_has_flat_ccs(xe) &&
>>>> +                   GRAPHICS_VERx100(xe) >= 2000) {
>>>> +                       struct xe_bo *scratch_bo_before;
>>>> +                       struct xe_bo *scratch_bo_after;
>>>> +
>>>> +                       scratch_bo_before =
>>>> xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
>>>> +
>>>> ttm_bo_type_kernel,
>>>> +
>>>> XE_BO_FLAG_VRAM_IF_DGFX(tile),
>>>> +
>>>> false);
>>>> +                       if (IS_ERR(scratch_bo_before)) {
>>>> +                               err = PTR_ERR(scratch_bo_before);
>>>> +                               goto unpin;
>>>> +                       }
>>>> +
>>>> +                       scratch_bo_after =
>>>> xe_bo_create_pin_map_novm(xe, tile, SZ_64K,
>>>> +
>>>> ttm_bo_type_kernel,
>>>> +
>>>> XE_BO_FLAG_VRAM_IF_DGFX(tile),
>>>> +
>>>> false);
>>>> +                       if (IS_ERR(scratch_bo_after)) {
>>>> +                               xe_bo_unpin_map_no_vm(scratch_bo_
>>>> befo
>>>> re);
>>>> +                               err = PTR_ERR(scratch_bo_after);
>>>> +                               goto unpin;
>>>> +                       }
>>>> +
>>>> +                       /* Save original CCS metadata for PA 0 +
>>>> */
>>>> +                       err = xe_migrate_debug_ccs_overlap(tile-
>>>>> migrate, scratch_bo_before, false);
>>>> +                       if (err) {
>>>> +                               xe_bo_unpin_map_no_vm(scratch_bo_
>>>> befo
>>>> re);
>>>> +                               xe_bo_unpin_map_no_vm(scratch_bo_
>>>> afte
>>>> r);
>>>> +                               goto unpin;
>>>> +                       }
>>>> +
>>>> +                       /*
>>>> +                        * Fill last page. If there is CCS
>>>> overlap in
>>>> the last
>>>> +                        * page this will snag the raw CCS
>>>> storage.
>>>> +                        */
>>>> +                       xe_map_memset(xe, &last_page_bo->vmap, 0,
>>>> 0x5A, SZ_64K);
>>>> +                       xe_device_wmb(xe);
>>>> +
>>>> +                       /*
>>>> +                        * Global invalidation. Some BMG SKUs
>>>> will
>>>> cache the BAR
>>>> +                        * writes in the GPU side VRAM cache.
>>>> Make
>>>> sure above
>>>> +                        * writes are fully flushed out to VRAM,
>>>> so
>>>> this is
>>>> +                        * hopefully more well behaved with the
>>>> CCS
>>>> unit, if
>>>> +                        * there is indeed CCS overlap with
>>>> normal
>>>> VRAM. Since
>>>> +                        * there is a separate CCS cache, the CCS
>>>> unit might not
>>>> +                        * respect the GPU VRAM cache for CCS
>>>> accesses, so opt
>>>> +                        * for being super careful here.
>>>> +                        */
>>>> +                       xe_device_l2_flush(xe, true);
>>>> +
>>>> +                       /* Use GPU to clear CCS state for PA 0 */
>>>> +                       xe_map_memset(xe, &scratch_bo_after-
>>>>> vmap, 0,
>>>> 0x00, SZ_64K);
>>>> +                       err = xe_migrate_debug_ccs_overlap(tile-
>>>>> migrate, scratch_bo_after, true);
>>>> +                       if (err) {
>>>> +                               xe_bo_unpin_map_no_vm(scratch_bo_
>>>> befo
>>>> re);
>>>> +                               xe_bo_unpin_map_no_vm(scratch_bo_
>>>> afte
>>>> r);
>>>> +                               goto unpin;
>>>> +                       }
>>>> +                       /*
>>>> +                        * Global invalidation. Ensure CCS caches
>>>> really are
>>>> +                        * nuked and the raw CCS data is visible
>>>> in
>>>> VRAM, for
>>>> +                        * the below access.
>>>> +                        */
>>>> +                       xe_device_l2_flush(xe, true);
>>>> +
>>>> +                       /* Check if last_page_bo was corrupted by
>>>> the
>>>> GPU CCS clear */
>>>> +                       for (i = 0; i < SZ_64K; i += 8) {
>>>> +                               u64 payload = xe_map_rd(xe,
>>>> &last_page_bo->vmap, i, u64);
>>>> +
>>>> +                               if (payload !=
>>>> 0x5A5A5A5A5A5A5A5AULL)
>>>> {
>>>> +                                       overlap = true;
>>>> +                                       break;
>>>> +                               }
>>>> +                       }
>>>> +
>>>> +                       /* Restore original CCS metadata for PA 0
>>>> +
>>>> */
>>>> +                       err = xe_migrate_debug_ccs_overlap(tile-
>>>>> migrate, scratch_bo_before, true);
>>>> +                       if (err)
>>>> +                               drm_warn(&xe->drm, "Failed to
>>>> restore
>>>> CCS metadata\n");
>>>> +
>>>> +                       xe_bo_unpin_map_no_vm(scratch_bo_before);
>>>> +                       xe_bo_unpin_map_no_vm(scratch_bo_after);
>>>> +               }
>>>> +
>>>> +               if (drm_WARN(&xe->drm, overlap,
>>>> +                            "Tile %d: VRAM bounds overlap CCS
>>>> region! VRAM sizing is incorrect.\n",
>>>> +                            id)) {
>>>> +                       err = -EINVAL;
>>>> +                       goto unpin;
>>>> +               }
>>>> +
>>>> +               drm_info(&xe->drm, "Tile %d: VRAM memtest
>>>> completed.\n", id);
>>>> +
>>>> +unpin:
>>>> +               if (err)
>>>> +                       break;
>>>> +       }
>>>> +
>>>> +       xe_vram_free_memtest_bos(xe);
>>>> +
>>>> +       return err;
>>>> +}
>>>> +#endif
>>>> diff --git a/drivers/gpu/drm/xe/xe_vram.h
>>>> b/drivers/gpu/drm/xe/xe_vram.h
>>>> index dd1c8bf17922..38425d81f777 100644
>>>> --- a/drivers/gpu/drm/xe/xe_vram.h
>>>> +++ b/drivers/gpu/drm/xe/xe_vram.h
>>>> @@ -23,4 +23,14 @@ resource_size_t xe_vram_region_dpa_base(const
>>>> struct xe_vram_region *vram);
>>>>    resource_size_t xe_vram_region_usable_size(const struct
>>>> xe_vram_region *vram);
>>>>    resource_size_t xe_vram_region_actual_physical_size(const
>>>> struct
>>>> xe_vram_region *vram);
>>>>    
>>>> +#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
>>>> +int xe_vram_reserve_memtest_bo(struct xe_device *xe);
>>>> +void xe_vram_free_memtest_bos(struct xe_device *xe);
>>>> +int xe_vram_memtest(struct xe_device *xe);
>>>> +#else
>>>> +static inline int xe_vram_reserve_memtest_bo(struct xe_device
>>>> *xe) {
>>>> return 0; }
>>>> +static inline void xe_vram_free_memtest_bos(struct xe_device
>>>> *xe) {}
>>>> +static inline int xe_vram_memtest(struct xe_device *xe) { return
>>>> 0;
>>>> }
>>>> +#endif
>>>> +
>>>>    #endif
>>>
>>
> 

✓ CI.KUnit: success for VRAM health check + CCS fix

[Patchwork]

== Series Details ==

Series: VRAM health check + CCS fix
URL   : https://patchwork.freedesktop.org/series/172984/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[15:20:16] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:20:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:20:52] Starting KUnit Kernel (1/1)...
[15:20:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:20:53] ================== guc_buf (11 subtests) ===================
[15:20:53] [PASSED] test_smallest
[15:20:53] [PASSED] test_largest
[15:20:53] [PASSED] test_granular
[15:20:53] [PASSED] test_unique
[15:20:53] [PASSED] test_overlap
[15:20:53] [PASSED] test_reusable
[15:20:53] [PASSED] test_too_big
[15:20:53] [PASSED] test_flush
[15:20:53] [PASSED] test_lookup
[15:20:53] [PASSED] test_data
[15:20:53] [PASSED] test_class
[15:20:53] ===================== [PASSED] guc_buf =====================
[15:20:53] =================== guc_dbm (7 subtests) ===================
[15:20:53] [PASSED] test_empty
[15:20:53] [PASSED] test_default
[15:20:53] ======================== test_size  ========================
[15:20:53] [PASSED] 4
[15:20:53] [PASSED] 8
[15:20:53] [PASSED] 32
[15:20:53] [PASSED] 256
[15:20:53] ==================== [PASSED] test_size ====================
[15:20:53] ======================= test_reuse  ========================
[15:20:53] [PASSED] 4
[15:20:53] [PASSED] 8
[15:20:53] [PASSED] 32
[15:20:53] [PASSED] 256
[15:20:53] =================== [PASSED] test_reuse ====================
[15:20:53] =================== test_range_overlap  ====================
[15:20:53] [PASSED] 4
[15:20:53] [PASSED] 8
[15:20:53] [PASSED] 32
[15:20:53] [PASSED] 256
[15:20:53] =============== [PASSED] test_range_overlap ================
[15:20:53] =================== test_range_compact  ====================
[15:20:53] [PASSED] 4
[15:20:53] [PASSED] 8
[15:20:53] [PASSED] 32
[15:20:53] [PASSED] 256
[15:20:53] =============== [PASSED] test_range_compact ================
[15:20:53] ==================== test_range_spare  =====================
[15:20:53] [PASSED] 4
[15:20:53] [PASSED] 8
[15:20:53] [PASSED] 32
[15:20:53] [PASSED] 256
[15:20:53] ================ [PASSED] test_range_spare =================
[15:20:53] ===================== [PASSED] guc_dbm =====================
[15:20:53] =================== guc_idm (6 subtests) ===================
[15:20:53] [PASSED] bad_init
[15:20:53] [PASSED] no_init
[15:20:53] [PASSED] init_fini
[15:20:53] [PASSED] check_used
[15:20:53] [PASSED] check_quota
[15:20:53] [PASSED] check_all
[15:20:53] ===================== [PASSED] guc_idm =====================
[15:20:53] =============== guc_klv_helpers (9 subtests) ===============
[15:20:53] [PASSED] test_count
[15:20:53] [PASSED] test_encode_u32
[15:20:53] [PASSED] test_encode_u64
[15:20:53] [PASSED] test_encode_string
[15:20:53] [PASSED] test_encode_object_raw
[15:20:53] [PASSED] test_encode_object_klv
[15:20:53] [PASSED] test_encode_object_nested
[15:20:53] [PASSED] test_encode_object_basic
[15:20:53] [PASSED] test_print
[15:20:53] ================= [PASSED] guc_klv_helpers =================
[15:20:53] =================== xe_log (4 subtests) ====================
[15:20:53] [PASSED] demo_cper
[15:20:53] [PASSED] demo_dmesg
[15:20:53] ======================= test_dmesg  ========================
[15:20:53] [PASSED] test_fatal
[15:20:53] [PASSED] test_fatal_tile
[15:20:53] [PASSED] test_fatal_gt
[15:20:53] [PASSED] test_fatal_comp
[15:20:53] [PASSED] test_fatal_comp_tile
[15:20:53] [PASSED] test_fatal_comp_gt
[15:20:53] [PASSED] test_fatal_all
[15:20:53] [PASSED] test_recoverable
[15:20:53] [PASSED] test_recoverable_tile
[15:20:53] [PASSED] test_recoverable_gt
[15:20:53] [PASSED] test_recoverable_comp
[15:20:53] [PASSED] test_recoverable_comp_tile
[15:20:53] [PASSED] test_recoverable_comp_gt
[15:20:53] [PASSED] test_recoverable_all
[15:20:53] [PASSED] test_info
[15:20:53] [PASSED] test_info_tile
[15:20:53] [PASSED] test_info_gt
[15:20:53] [PASSED] test_info_err
[15:20:53] [PASSED] test_info_comp
[15:20:53] [PASSED] test_info_comp_tile
[15:20:53] [PASSED] test_info_comp_gt
[15:20:53] [PASSED] test_info_all
[15:20:53] [PASSED] test_hw_fatal
[15:20:53] [PASSED] test_hw_recoverable
[15:20:53] [PASSED] test_hw_corrected
[15:20:53] [PASSED] test_hw_informational
[15:20:53] =================== [PASSED] test_dmesg ====================
[15:20:53] ====================== test_invalid  =======================
[15:20:53] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[15:20:53] ================== [SKIPPED] test_invalid ==================
[15:20:53] ===================== [PASSED] xe_log ======================
[15:20:53] ================== no_relay (3 subtests) ===================
[15:20:53] [PASSED] xe_drops_guc2pf_if_not_ready
[15:20:53] [PASSED] xe_drops_guc2vf_if_not_ready
[15:20:53] [PASSED] xe_rejects_send_if_not_ready
[15:20:53] ==================== [PASSED] no_relay =====================
[15:20:53] ================== pf_relay (14 subtests) ==================
[15:20:53] [PASSED] pf_rejects_guc2pf_too_short
[15:20:53] [PASSED] pf_rejects_guc2pf_too_long
[15:20:53] [PASSED] pf_rejects_guc2pf_no_payload
[15:20:53] [PASSED] pf_fails_no_payload
[15:20:53] [PASSED] pf_fails_bad_origin
[15:20:53] [PASSED] pf_fails_bad_type
[15:20:53] [PASSED] pf_txn_reports_error
[15:20:53] [PASSED] pf_txn_sends_pf2guc
[15:20:53] [PASSED] pf_sends_pf2guc
[15:20:53] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:20:53] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:20:53] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:20:53] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:20:53] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:20:53] ==================== [PASSED] pf_relay =====================
[15:20:53] ================== vf_relay (3 subtests) ===================
[15:20:53] [PASSED] vf_rejects_guc2vf_too_short
[15:20:53] [PASSED] vf_rejects_guc2vf_too_long
[15:20:53] [PASSED] vf_rejects_guc2vf_no_payload
[15:20:53] ==================== [PASSED] vf_relay =====================
[15:20:53] ================ pf_gt_config (9 subtests) =================
[15:20:53] [PASSED] fair_contexts_1vf
[15:20:53] [PASSED] fair_doorbells_1vf
[15:20:53] [PASSED] fair_ggtt_1vf
[15:20:53] ====================== fair_vram_1vf  ======================
[15:20:53] [PASSED] 3.50 GiB
[15:20:53] [PASSED] 11.5 GiB
[15:20:53] [PASSED] 15.5 GiB
[15:20:53] [PASSED] 31.5 GiB
[15:20:53] [PASSED] 63.5 GiB
[15:20:53] [PASSED] 1.91 GiB
[15:20:53] ================== [PASSED] fair_vram_1vf ==================
[15:20:53] ================ fair_vram_1vf_admin_only  =================
[15:20:53] [PASSED] 3.50 GiB
[15:20:53] [PASSED] 11.5 GiB
[15:20:53] [PASSED] 15.5 GiB
[15:20:53] [PASSED] 31.5 GiB
[15:20:53] [PASSED] 63.5 GiB
[15:20:53] [PASSED] 1.91 GiB
[15:20:53] ============ [PASSED] fair_vram_1vf_admin_only =============
[15:20:53] ====================== fair_contexts  ======================
[15:20:53] [PASSED] 1 VF
[15:20:53] [PASSED] 2 VFs
[15:20:53] [PASSED] 3 VFs
[15:20:53] [PASSED] 4 VFs
[15:20:53] [PASSED] 5 VFs
[15:20:53] [PASSED] 6 VFs
[15:20:53] [PASSED] 7 VFs
[15:20:53] [PASSED] 8 VFs
[15:20:53] [PASSED] 9 VFs
[15:20:53] [PASSED] 10 VFs
[15:20:53] [PASSED] 11 VFs
[15:20:53] [PASSED] 12 VFs
[15:20:53] [PASSED] 13 VFs
[15:20:53] [PASSED] 14 VFs
[15:20:53] [PASSED] 15 VFs
[15:20:53] [PASSED] 16 VFs
[15:20:53] [PASSED] 17 VFs
[15:20:53] [PASSED] 18 VFs
[15:20:53] [PASSED] 19 VFs
[15:20:53] [PASSED] 20 VFs
[15:20:53] [PASSED] 21 VFs
[15:20:53] [PASSED] 22 VFs
[15:20:53] [PASSED] 23 VFs
[15:20:53] [PASSED] 24 VFs
[15:20:53] [PASSED] 25 VFs
[15:20:53] [PASSED] 26 VFs
[15:20:53] [PASSED] 27 VFs
[15:20:53] [PASSED] 28 VFs
[15:20:53] [PASSED] 29 VFs
[15:20:53] [PASSED] 30 VFs
[15:20:53] [PASSED] 31 VFs
[15:20:53] [PASSED] 32 VFs
[15:20:53] [PASSED] 33 VFs
[15:20:53] [PASSED] 34 VFs
[15:20:53] [PASSED] 35 VFs
[15:20:53] [PASSED] 36 VFs
[15:20:53] [PASSED] 37 VFs
[15:20:53] [PASSED] 38 VFs
[15:20:53] [PASSED] 39 VFs
[15:20:53] [PASSED] 40 VFs
[15:20:53] [PASSED] 41 VFs
[15:20:53] [PASSED] 42 VFs
[15:20:53] [PASSED] 43 VFs
[15:20:53] [PASSED] 44 VFs
[15:20:53] [PASSED] 45 VFs
[15:20:53] [PASSED] 46 VFs
[15:20:53] [PASSED] 47 VFs
[15:20:53] [PASSED] 48 VFs
[15:20:53] [PASSED] 49 VFs
[15:20:53] [PASSED] 50 VFs
[15:20:53] [PASSED] 51 VFs
[15:20:53] [PASSED] 52 VFs
[15:20:53] [PASSED] 53 VFs
[15:20:53] [PASSED] 54 VFs
[15:20:53] [PASSED] 55 VFs
[15:20:53] [PASSED] 56 VFs
[15:20:53] [PASSED] 57 VFs
[15:20:53] [PASSED] 58 VFs
[15:20:53] [PASSED] 59 VFs
[15:20:53] [PASSED] 60 VFs
[15:20:53] [PASSED] 61 VFs
[15:20:53] [PASSED] 62 VFs
[15:20:53] [PASSED] 63 VFs
[15:20:53] ================== [PASSED] fair_contexts ==================
[15:20:53] ===================== fair_doorbells  ======================
[15:20:53] [PASSED] 1 VF
[15:20:53] [PASSED] 2 VFs
[15:20:53] [PASSED] 3 VFs
[15:20:53] [PASSED] 4 VFs
[15:20:53] [PASSED] 5 VFs
[15:20:53] [PASSED] 6 VFs
[15:20:53] [PASSED] 7 VFs
[15:20:53] [PASSED] 8 VFs
[15:20:53] [PASSED] 9 VFs
[15:20:53] [PASSED] 10 VFs
[15:20:53] [PASSED] 11 VFs
[15:20:53] [PASSED] 12 VFs
[15:20:53] [PASSED] 13 VFs
[15:20:53] [PASSED] 14 VFs
[15:20:53] [PASSED] 15 VFs
[15:20:53] [PASSED] 16 VFs
[15:20:53] [PASSED] 17 VFs
[15:20:53] [PASSED] 18 VFs
[15:20:53] [PASSED] 19 VFs
[15:20:53] [PASSED] 20 VFs
[15:20:53] [PASSED] 21 VFs
[15:20:53] [PASSED] 22 VFs
[15:20:53] [PASSED] 23 VFs
[15:20:53] [PASSED] 24 VFs
[15:20:53] [PASSED] 25 VFs
[15:20:53] [PASSED] 26 VFs
[15:20:53] [PASSED] 27 VFs
[15:20:53] [PASSED] 28 VFs
[15:20:53] [PASSED] 29 VFs
[15:20:53] [PASSED] 30 VFs
[15:20:53] [PASSED] 31 VFs
[15:20:53] [PASSED] 32 VFs
[15:20:53] [PASSED] 33 VFs
[15:20:53] [PASSED] 34 VFs
[15:20:53] [PASSED] 35 VFs
[15:20:53] [PASSED] 36 VFs
[15:20:53] [PASSED] 37 VFs
[15:20:53] [PASSED] 38 VFs
[15:20:53] [PASSED] 39 VFs
[15:20:53] [PASSED] 40 VFs
[15:20:53] [PASSED] 41 VFs
[15:20:53] [PASSED] 42 VFs
[15:20:53] [PASSED] 43 VFs
[15:20:53] [PASSED] 44 VFs
[15:20:53] [PASSED] 45 VFs
[15:20:53] [PASSED] 46 VFs
[15:20:53] [PASSED] 47 VFs
[15:20:53] [PASSED] 48 VFs
[15:20:53] [PASSED] 49 VFs
[15:20:53] [PASSED] 50 VFs
[15:20:53] [PASSED] 51 VFs
[15:20:53] [PASSED] 52 VFs
[15:20:53] [PASSED] 53 VFs
[15:20:53] [PASSED] 54 VFs
[15:20:53] [PASSED] 55 VFs
[15:20:53] [PASSED] 56 VFs
[15:20:53] [PASSED] 57 VFs
[15:20:53] [PASSED] 58 VFs
[15:20:53] [PASSED] 59 VFs
[15:20:53] [PASSED] 60 VFs
[15:20:53] [PASSED] 61 VFs
[15:20:53] [PASSED] 62 VFs
[15:20:53] [PASSED] 63 VFs
[15:20:53] ================= [PASSED] fair_doorbells ==================
[15:20:53] ======================== fair_ggtt  ========================
[15:20:53] [PASSED] 1 VF
[15:20:53] [PASSED] 2 VFs
[15:20:53] [PASSED] 3 VFs
[15:20:53] [PASSED] 4 VFs
[15:20:53] [PASSED] 5 VFs
[15:20:53] [PASSED] 6 VFs
[15:20:53] [PASSED] 7 VFs
[15:20:53] [PASSED] 8 VFs
[15:20:53] [PASSED] 9 VFs
[15:20:53] [PASSED] 10 VFs
[15:20:53] [PASSED] 11 VFs
[15:20:53] [PASSED] 12 VFs
[15:20:53] [PASSED] 13 VFs
[15:20:53] [PASSED] 14 VFs
[15:20:53] [PASSED] 15 VFs
[15:20:53] [PASSED] 16 VFs
[15:20:53] [PASSED] 17 VFs
[15:20:53] [PASSED] 18 VFs
[15:20:53] [PASSED] 19 VFs
[15:20:53] [PASSED] 20 VFs
[15:20:53] [PASSED] 21 VFs
[15:20:53] [PASSED] 22 VFs
[15:20:53] [PASSED] 23 VFs
[15:20:53] [PASSED] 24 VFs
[15:20:53] [PASSED] 25 VFs
[15:20:53] [PASSED] 26 VFs
[15:20:53] [PASSED] 27 VFs
[15:20:53] [PASSED] 28 VFs
[15:20:53] [PASSED] 29 VFs
[15:20:53] [PASSED] 30 VFs
[15:20:53] [PASSED] 31 VFs
[15:20:53] [PASSED] 32 VFs
[15:20:53] [PASSED] 33 VFs
[15:20:53] [PASSED] 34 VFs
[15:20:53] [PASSED] 35 VFs
[15:20:53] [PASSED] 36 VFs
[15:20:53] [PASSED] 37 VFs
[15:20:53] [PASSED] 38 VFs
[15:20:53] [PASSED] 39 VFs
[15:20:53] [PASSED] 40 VFs
[15:20:53] [PASSED] 41 VFs
[15:20:53] [PASSED] 42 VFs
[15:20:53] [PASSED] 43 VFs
[15:20:53] [PASSED] 44 VFs
[15:20:53] [PASSED] 45 VFs
[15:20:53] [PASSED] 46 VFs
[15:20:53] [PASSED] 47 VFs
[15:20:53] [PASSED] 48 VFs
[15:20:53] [PASSED] 49 VFs
[15:20:53] [PASSED] 50 VFs
[15:20:53] [PASSED] 51 VFs
[15:20:53] [PASSED] 52 VFs
[15:20:53] [PASSED] 53 VFs
[15:20:53] [PASSED] 54 VFs
[15:20:53] [PASSED] 55 VFs
[15:20:53] [PASSED] 56 VFs
[15:20:53] [PASSED] 57 VFs
[15:20:53] [PASSED] 58 VFs
[15:20:53] [PASSED] 59 VFs
[15:20:53] [PASSED] 60 VFs
[15:20:53] [PASSED] 61 VFs
[15:20:53] [PASSED] 62 VFs
[15:20:53] [PASSED] 63 VFs
[15:20:53] ==================== [PASSED] fair_ggtt ====================
[15:20:53] ======================== fair_vram  ========================
[15:20:53] [PASSED] 1 VF
[15:20:53] [PASSED] 2 VFs
[15:20:53] [PASSED] 3 VFs
[15:20:53] [PASSED] 4 VFs
[15:20:53] [PASSED] 5 VFs
[15:20:53] [PASSED] 6 VFs
[15:20:53] [PASSED] 7 VFs
[15:20:53] [PASSED] 8 VFs
[15:20:53] [PASSED] 9 VFs
[15:20:53] [PASSED] 10 VFs
[15:20:53] [PASSED] 11 VFs
[15:20:53] [PASSED] 12 VFs
[15:20:53] [PASSED] 13 VFs
[15:20:53] [PASSED] 14 VFs
[15:20:53] [PASSED] 15 VFs
[15:20:53] [PASSED] 16 VFs
[15:20:53] [PASSED] 17 VFs
[15:20:53] [PASSED] 18 VFs
[15:20:53] [PASSED] 19 VFs
[15:20:53] [PASSED] 20 VFs
[15:20:53] [PASSED] 21 VFs
[15:20:53] [PASSED] 22 VFs
[15:20:53] [PASSED] 23 VFs
[15:20:53] [PASSED] 24 VFs
[15:20:53] [PASSED] 25 VFs
[15:20:53] [PASSED] 26 VFs
[15:20:53] [PASSED] 27 VFs
[15:20:53] [PASSED] 28 VFs
[15:20:53] [PASSED] 29 VFs
[15:20:53] [PASSED] 30 VFs
[15:20:53] [PASSED] 31 VFs
[15:20:53] [PASSED] 32 VFs
[15:20:53] [PASSED] 33 VFs
[15:20:53] [PASSED] 34 VFs
[15:20:53] [PASSED] 35 VFs
[15:20:53] [PASSED] 36 VFs
[15:20:53] [PASSED] 37 VFs
[15:20:53] [PASSED] 38 VFs
[15:20:53] [PASSED] 39 VFs
[15:20:53] [PASSED] 40 VFs
[15:20:53] [PASSED] 41 VFs
[15:20:53] [PASSED] 42 VFs
[15:20:53] [PASSED] 43 VFs
[15:20:53] [PASSED] 44 VFs
[15:20:53] [PASSED] 45 VFs
[15:20:53] [PASSED] 46 VFs
[15:20:53] [PASSED] 47 VFs
[15:20:53] [PASSED] 48 VFs
[15:20:53] [PASSED] 49 VFs
[15:20:53] [PASSED] 50 VFs
[15:20:53] [PASSED] 51 VFs
[15:20:53] [PASSED] 52 VFs
[15:20:53] [PASSED] 53 VFs
[15:20:53] [PASSED] 54 VFs
[15:20:53] [PASSED] 55 VFs
[15:20:53] [PASSED] 56 VFs
[15:20:53] [PASSED] 57 VFs
[15:20:53] [PASSED] 58 VFs
[15:20:53] [PASSED] 59 VFs
[15:20:53] [PASSED] 60 VFs
[15:20:53] [PASSED] 61 VFs
[15:20:53] [PASSED] 62 VFs
[15:20:53] [PASSED] 63 VFs
[15:20:53] ==================== [PASSED] fair_vram ====================
[15:20:53] ================== [PASSED] pf_gt_config ===================
[15:20:53] ===================== lmtt (1 subtest) =====================
[15:20:53] ======================== test_ops  =========================
[15:20:53] [PASSED] 2-level
[15:20:53] [PASSED] multi-level
[15:20:53] ==================== [PASSED] test_ops =====================
[15:20:53] ====================== [PASSED] lmtt =======================
[15:20:53] ================= sriov_packet (1 subtest) =================
[15:20:53] [PASSED] test_descriptor_init
[15:20:53] ================== [PASSED] sriov_packet ===================
[15:20:53] ================= pf_service (11 subtests) =================
[15:20:53] [PASSED] pf_negotiate_any
[15:20:53] [PASSED] pf_negotiate_base_match
[15:20:53] [PASSED] pf_negotiate_base_newer
[15:20:53] [PASSED] pf_negotiate_base_next
[15:20:53] [SKIPPED] pf_negotiate_base_older (no older minor)
[15:20:53] [PASSED] pf_negotiate_base_prev
[15:20:53] [PASSED] pf_negotiate_latest_match
[15:20:53] [PASSED] pf_negotiate_latest_newer
[15:20:53] [PASSED] pf_negotiate_latest_next
[15:20:53] [SKIPPED] pf_negotiate_latest_older (no older minor)
[15:20:53] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[15:20:53] =================== [PASSED] pf_service ====================
[15:20:53] ================= xe_guc_g2g (2 subtests) ==================
[15:20:53] ============== xe_live_guc_g2g_kunit_default  ==============
[15:20:53] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[15:20:53] ============== xe_live_guc_g2g_kunit_allmem  ===============
[15:20:53] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[15:20:53] =================== [SKIPPED] xe_guc_g2g ===================
[15:20:53] =================== xe_mocs (2 subtests) ===================
[15:20:53] ================ xe_live_mocs_kernel_kunit  ================
[15:20:53] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[15:20:53] ================ xe_live_mocs_reset_kunit  =================
[15:20:53] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[15:20:53] ==================== [SKIPPED] xe_mocs =====================
[15:20:53] ================= xe_migrate (2 subtests) ==================
[15:20:53] ================= xe_migrate_sanity_kunit  =================
[15:20:53] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[15:20:53] ================== xe_validate_ccs_kunit  ==================
[15:20:53] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[15:20:53] =================== [SKIPPED] xe_migrate ===================
[15:20:53] ================== xe_dma_buf (1 subtest) ==================
[15:20:53] ==================== xe_dma_buf_kunit  =====================
[15:20:53] ================ [SKIPPED] xe_dma_buf_kunit ================
[15:20:53] =================== [SKIPPED] xe_dma_buf ===================
[15:20:53] ================= xe_bo_shrink (1 subtest) =================
[15:20:53] =================== xe_bo_shrink_kunit  ====================
[15:20:53] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[15:20:53] ================== [SKIPPED] xe_bo_shrink ==================
[15:20:53] ==================== xe_bo (2 subtests) ====================
[15:20:53] ================== xe_ccs_migrate_kunit  ===================
[15:20:53] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[15:20:53] ==================== xe_bo_evict_kunit  ====================
[15:20:53] =============== [SKIPPED] xe_bo_evict_kunit ================
[15:20:53] ===================== [SKIPPED] xe_bo ======================
[15:20:53] =================== xe_any (9 subtests) ====================
[15:20:53] [PASSED] test_to_xe
[15:20:53] [PASSED] test_to_dev
[15:20:53] [PASSED] test_to_pdev
[15:20:53] [PASSED] test_to_drm
[15:20:53] [PASSED] test_if_pdev
[15:20:53] [PASSED] test_if_xe
[15:20:53] [PASSED] test_if_tile
[15:20:53] [PASSED] test_if_gt
[15:20:53] [PASSED] test_to_id
[15:20:53] ===================== [PASSED] xe_any ======================
[15:20:53] ==================== args (13 subtests) ====================
[15:20:53] [PASSED] count_args_test
[15:20:53] [PASSED] call_args_example
[15:20:53] [PASSED] call_args_test
[15:20:53] [PASSED] drop_first_arg_example
[15:20:53] [PASSED] drop_first_arg_test
[15:20:53] [PASSED] first_arg_example
[15:20:53] [PASSED] first_arg_test
[15:20:53] [PASSED] last_arg_example
[15:20:53] [PASSED] last_arg_test
[15:20:53] [PASSED] pick_arg_example
[15:20:53] [PASSED] if_args_example
[15:20:53] [PASSED] if_args_test
[15:20:53] [PASSED] sep_comma_example
[15:20:53] ====================== [PASSED] args =======================
[15:20:53] =================== xe_pci (3 subtests) ====================
[15:20:53] ==================== check_graphics_ip  ====================
[15:20:53] [PASSED] 12.00 Xe_LP
[15:20:53] [PASSED] 12.10 Xe_LP+
[15:20:53] [PASSED] 12.55 Xe_HPG
[15:20:53] [PASSED] 12.60 Xe_HPC
[15:20:53] [PASSED] 12.70 Xe_LPG
[15:20:53] [PASSED] 12.71 Xe_LPG
[15:20:53] [PASSED] 12.74 Xe_LPG+
[15:20:53] [PASSED] 20.01 Xe2_HPG
[15:20:53] [PASSED] 20.02 Xe2_HPG
[15:20:53] [PASSED] 20.04 Xe2_LPG
[15:20:53] [PASSED] 30.00 Xe3_LPG
[15:20:53] [PASSED] 30.01 Xe3_LPG
[15:20:53] [PASSED] 30.03 Xe3_LPG
[15:20:53] [PASSED] 30.04 Xe3_LPG
[15:20:53] [PASSED] 30.05 Xe3_LPG
[15:20:53] [PASSED] 35.10 Xe3p_LPG
[15:20:53] [PASSED] 35.11 Xe3p_XPC
[15:20:53] ================ [PASSED] check_graphics_ip ================
[15:20:53] ===================== check_media_ip  ======================
[15:20:53] [PASSED] 12.00 Xe_M
[15:20:53] [PASSED] 12.55 Xe_HPM
[15:20:53] [PASSED] 13.00 Xe_LPM+
[15:20:53] [PASSED] 13.01 Xe2_HPM
[15:20:53] [PASSED] 20.00 Xe2_LPM
[15:20:53] [PASSED] 30.00 Xe3_LPM
[15:20:53] [PASSED] 30.02 Xe3_LPM
[15:20:53] [PASSED] 35.00 Xe3p_LPM
[15:20:53] [PASSED] 35.03 Xe3p_HPM
[15:20:53] ================= [PASSED] check_media_ip ==================
[15:20:53] =================== check_platform_desc  ===================
[15:20:53] [PASSED] 0x9A60 (TIGERLAKE)
[15:20:53] [PASSED] 0x9A68 (TIGERLAKE)
[15:20:53] [PASSED] 0x9A70 (TIGERLAKE)
[15:20:53] [PASSED] 0x9A40 (TIGERLAKE)
[15:20:53] [PASSED] 0x9A49 (TIGERLAKE)
[15:20:53] [PASSED] 0x9A59 (TIGERLAKE)
[15:20:53] [PASSED] 0x9A78 (TIGERLAKE)
[15:20:53] [PASSED] 0x9AC0 (TIGERLAKE)
[15:20:53] [PASSED] 0x9AC9 (TIGERLAKE)
[15:20:53] [PASSED] 0x9AD9 (TIGERLAKE)
[15:20:53] [PASSED] 0x9AF8 (TIGERLAKE)
[15:20:53] [PASSED] 0x4C80 (ROCKETLAKE)
[15:20:53] [PASSED] 0x4C8A (ROCKETLAKE)
[15:20:53] [PASSED] 0x4C8B (ROCKETLAKE)
[15:20:53] [PASSED] 0x4C8C (ROCKETLAKE)
[15:20:53] [PASSED] 0x4C90 (ROCKETLAKE)
[15:20:53] [PASSED] 0x4C9A (ROCKETLAKE)
[15:20:53] [PASSED] 0x4680 (ALDERLAKE_S)
[15:20:53] [PASSED] 0x4682 (ALDERLAKE_S)
[15:20:53] [PASSED] 0x4688 (ALDERLAKE_S)
[15:20:53] [PASSED] 0x468A (ALDERLAKE_S)
[15:20:53] [PASSED] 0x468B (ALDERLAKE_S)
[15:20:53] [PASSED] 0x4690 (ALDERLAKE_S)
[15:20:53] [PASSED] 0x4692 (ALDERLAKE_S)
[15:20:53] [PASSED] 0x4693 (ALDERLAKE_S)
[15:20:53] [PASSED] 0x46A0 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46A1 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46A2 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46A3 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46A6 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46A8 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46AA (ALDERLAKE_P)
[15:20:53] [PASSED] 0x462A (ALDERLAKE_P)
[15:20:53] [PASSED] 0x4626 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x4628 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46B0 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46B1 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46B2 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46B3 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46C0 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46C1 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46C2 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46C3 (ALDERLAKE_P)
[15:20:53] [PASSED] 0x46D0 (ALDERLAKE_N)
[15:20:53] [PASSED] 0x46D1 (ALDERLAKE_N)
[15:20:53] [PASSED] 0x46D2 (ALDERLAKE_N)
[15:20:53] [PASSED] 0x46D3 (ALDERLAKE_N)
[15:20:53] [PASSED] 0x46D4 (ALDERLAKE_N)
[15:20:53] [PASSED] 0xA721 (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA7A1 (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA7A9 (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA7AC (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA7AD (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA720 (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA7A0 (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA7A8 (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA7AA (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA7AB (ALDERLAKE_P)
[15:20:53] [PASSED] 0xA780 (ALDERLAKE_S)
[15:20:53] [PASSED] 0xA781 (ALDERLAKE_S)
[15:20:53] [PASSED] 0xA782 (ALDERLAKE_S)
[15:20:53] [PASSED] 0xA783 (ALDERLAKE_S)
[15:20:53] [PASSED] 0xA788 (ALDERLAKE_S)
[15:20:53] [PASSED] 0xA789 (ALDERLAKE_S)
[15:20:53] [PASSED] 0xA78A (ALDERLAKE_S)
[15:20:53] [PASSED] 0xA78B (ALDERLAKE_S)
[15:20:53] [PASSED] 0x4905 (DG1)
[15:20:53] [PASSED] 0x4906 (DG1)
[15:20:53] [PASSED] 0x4907 (DG1)
[15:20:53] [PASSED] 0x4908 (DG1)
[15:20:53] [PASSED] 0x4909 (DG1)
[15:20:53] [PASSED] 0x56C0 (DG2)
[15:20:53] [PASSED] 0x56C2 (DG2)
[15:20:53] [PASSED] 0x56C1 (DG2)
[15:20:53] [PASSED] 0x7D51 (METEORLAKE)
[15:20:53] [PASSED] 0x7DD1 (METEORLAKE)
[15:20:53] [PASSED] 0x7D41 (METEORLAKE)
[15:20:53] [PASSED] 0x7D67 (METEORLAKE)
[15:20:53] [PASSED] 0xB640 (METEORLAKE)
[15:20:53] [PASSED] 0x56A0 (DG2)
[15:20:53] [PASSED] 0x56A1 (DG2)
[15:20:53] [PASSED] 0x56A2 (DG2)
[15:20:53] [PASSED] 0x56BE (DG2)
[15:20:53] [PASSED] 0x56BF (DG2)
[15:20:53] [PASSED] 0x5690 (DG2)
[15:20:53] [PASSED] 0x5691 (DG2)
[15:20:53] [PASSED] 0x5692 (DG2)
[15:20:53] [PASSED] 0x56A5 (DG2)
[15:20:53] [PASSED] 0x56A6 (DG2)
[15:20:53] [PASSED] 0x56B0 (DG2)
[15:20:53] [PASSED] 0x56B1 (DG2)
[15:20:53] [PASSED] 0x56BA (DG2)
[15:20:53] [PASSED] 0x56BB (DG2)
[15:20:53] [PASSED] 0x56BC (DG2)
[15:20:53] [PASSED] 0x56BD (DG2)
[15:20:53] [PASSED] 0x5693 (DG2)
[15:20:53] [PASSED] 0x5694 (DG2)
[15:20:53] [PASSED] 0x5695 (DG2)
[15:20:53] [PASSED] 0x56A3 (DG2)
[15:20:53] [PASSED] 0x56A4 (DG2)
[15:20:53] [PASSED] 0x56B2 (DG2)
[15:20:53] [PASSED] 0x56B3 (DG2)
[15:20:53] [PASSED] 0x5696 (DG2)
[15:20:53] [PASSED] 0x5697 (DG2)
[15:20:53] [PASSED] 0xB69 (PVC)
[15:20:53] [PASSED] 0xB6E (PVC)
[15:20:53] [PASSED] 0xBD4 (PVC)
[15:20:53] [PASSED] 0xBD5 (PVC)
[15:20:53] [PASSED] 0xBD6 (PVC)
[15:20:53] [PASSED] 0xBD7 (PVC)
[15:20:53] [PASSED] 0xBD8 (PVC)
[15:20:53] [PASSED] 0xBD9 (PVC)
[15:20:53] [PASSED] 0xBDA (PVC)
[15:20:53] [PASSED] 0xBDB (PVC)
[15:20:53] [PASSED] 0xBE0 (PVC)
[15:20:53] [PASSED] 0xBE1 (PVC)
[15:20:53] [PASSED] 0xBE5 (PVC)
[15:20:53] [PASSED] 0x7D40 (METEORLAKE)
[15:20:53] [PASSED] 0x7D45 (METEORLAKE)
[15:20:53] [PASSED] 0x7D55 (METEORLAKE)
[15:20:53] [PASSED] 0x7D60 (METEORLAKE)
[15:20:53] [PASSED] 0x7DD5 (METEORLAKE)
[15:20:53] [PASSED] 0x6420 (LUNARLAKE)
[15:20:53] [PASSED] 0x64A0 (LUNARLAKE)
[15:20:53] [PASSED] 0x64B0 (LUNARLAKE)
[15:20:53] [PASSED] 0xE202 (BATTLEMAGE)
[15:20:53] [PASSED] 0xE209 (BATTLEMAGE)
[15:20:53] [PASSED] 0xE20B (BATTLEMAGE)
[15:20:53] [PASSED] 0xE20C (BATTLEMAGE)
[15:20:53] [PASSED] 0xE20D (BATTLEMAGE)
[15:20:53] [PASSED] 0xE210 (BATTLEMAGE)
[15:20:53] [PASSED] 0xE211 (BATTLEMAGE)
[15:20:53] [PASSED] 0xE212 (BATTLEMAGE)
[15:20:53] [PASSED] 0xE216 (BATTLEMAGE)
[15:20:53] [PASSED] 0xE220 (BATTLEMAGE)
[15:20:53] [PASSED] 0xE221 (BATTLEMAGE)
[15:20:53] [PASSED] 0xE222 (BATTLEMAGE)
[15:20:53] [PASSED] 0xE223 (BATTLEMAGE)
[15:20:53] [PASSED] 0xB080 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB081 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB082 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB083 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB084 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB085 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB086 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB087 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB08F (PANTHERLAKE)
[15:20:53] [PASSED] 0xB090 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB0A0 (PANTHERLAKE)
[15:20:53] [PASSED] 0xB0B0 (PANTHERLAKE)
[15:20:53] [PASSED] 0xFD80 (PANTHERLAKE)
[15:20:53] [PASSED] 0xFD81 (PANTHERLAKE)
[15:20:53] [PASSED] 0xD740 (NOVALAKE_S)
[15:20:53] [PASSED] 0xD741 (NOVALAKE_S)
[15:20:53] [PASSED] 0xD742 (NOVALAKE_S)
[15:20:53] [PASSED] 0xD743 (NOVALAKE_S)
[15:20:53] [PASSED] 0xD745 (NOVALAKE_S)
[15:20:53] [PASSED] 0xD74A (NOVALAKE_S)
[15:20:53] [PASSED] 0xD74B (NOVALAKE_S)
[15:20:53] [PASSED] 0x674C (CRESCENTISLAND)
[15:20:53] [PASSED] 0x674D (CRESCENTISLAND)
[15:20:53] [PASSED] 0x674E (CRESCENTISLAND)
[15:20:53] [PASSED] 0x674F (CRESCENTISLAND)
[15:20:53] [PASSED] 0x6750 (CRESCENTISLAND)
[15:20:53] [PASSED] 0xD750 (NOVALAKE_P)
[15:20:53] [PASSED] 0xD751 (NOVALAKE_P)
[15:20:53] [PASSED] 0xD752 (NOVALAKE_P)
[15:20:53] [PASSED] 0xD753 (NOVALAKE_P)
[15:20:53] [PASSED] 0xD754 (NOVALAKE_P)
[15:20:53] [PASSED] 0xD755 (NOVALAKE_P)
[15:20:53] [PASSED] 0xD756 (NOVALAKE_P)
[15:20:53] [PASSED] 0xD757 (NOVALAKE_P)
[15:20:53] [PASSED] 0xD75F (NOVALAKE_P)
[15:20:53] =============== [PASSED] check_platform_desc ===============
[15:20:53] ===================== [PASSED] xe_pci ======================
[15:20:53] ============= xe_rtp_tables_test (5 subtests) ==============
[15:20:53] ================== xe_rtp_table_gt_test  ===================
[15:20:53] [PASSED] gt_was/14011060649
[15:20:53] [PASSED] gt_was/14011059788
[15:20:53] [PASSED] gt_was/14015795083
[15:20:53] [PASSED] gt_was/16021867713
[15:20:53] [PASSED] gt_was/14019449301
[15:20:53] [PASSED] gt_was/16028005424
[15:20:53] [PASSED] gt_was/14026578760
[15:20:53] [PASSED] gt_was/1409420604
[15:20:53] [PASSED] gt_was/1408615072
[15:20:53] [PASSED] gt_was/22010523718
[15:20:53] [PASSED] gt_was/14011006942
[15:20:53] [PASSED] gt_was/14014830051
[15:20:53] [PASSED] gt_was/18018781329
[15:20:53] [PASSED] gt_was/1509235366
[15:20:53] [PASSED] gt_was/18018781329
[15:20:53] [PASSED] gt_was/16016694945
[15:20:53] [PASSED] gt_was/14018575942
[15:20:53] [PASSED] gt_was/22016670082
[15:20:53] [PASSED] gt_was/22016670082
[15:20:53] [PASSED] gt_was/14017421178
[15:20:53] [PASSED] gt_was/16025250150
[15:20:53] [PASSED] gt_was/14021871409
[15:20:53] [PASSED] gt_was/16021865536
[15:20:53] [PASSED] gt_was/14021486841
[15:20:53] [PASSED] gt_was/14025160223
[15:20:53] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[15:20:53] [PASSED] gt_was/14025635424
[15:20:53] [PASSED] gt_was/16028005424
[15:20:53] ============== [PASSED] xe_rtp_table_gt_test ===============
[15:20:53] ================== xe_rtp_table_gt_test  ===================
[15:20:53] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[15:20:53] [PASSED] gt_tunings/Tuning: 32B Access Enable
[15:20:53] [PASSED] gt_tunings/Tuning: L3 cache
[15:20:53] [PASSED] gt_tunings/Tuning: L3 cache - media
[15:20:53] [PASSED] gt_tunings/Tuning: Compression Overfetch
[15:20:53] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[15:20:53] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[15:20:53] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[15:20:53] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[15:20:53] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[15:20:53] [PASSED] gt_tunings/Tuning: Stateless compression control
[15:20:53] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[15:20:53] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[15:20:53] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[15:20:53] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[15:20:53] ============== [PASSED] xe_rtp_table_gt_test ===============
[15:20:53] ================== xe_rtp_table_oob_test  ==================
[15:20:53] [PASSED] oob_was/1607983814
[15:20:53] [PASSED] oob_was/16010904313
[15:20:53] [PASSED] oob_was/18022495364
[15:20:53] [PASSED] oob_was/22012773006
[15:20:53] [PASSED] oob_was/14014475959
[15:20:53] [PASSED] oob_was/22011391025
[15:20:53] [PASSED] oob_was/22012727170
[15:20:53] [PASSED] oob_was/22012727685
[15:20:53] [PASSED] oob_was/22016596838
[15:20:53] [PASSED] oob_was/18020744125
[15:20:53] [PASSED] oob_was/1409600907
[15:20:53] [PASSED] oob_was/22014953428
[15:20:53] [PASSED] oob_was/16017236439
[15:20:53] [PASSED] oob_was/14019821291
[15:20:53] [PASSED] oob_was/14015076503
[15:20:53] [PASSED] oob_was/14018913170
[15:20:53] [PASSED] oob_was/14018094691
[15:20:53] [PASSED] oob_was/18024947630
[15:20:53] [PASSED] oob_was/16022287689
[15:20:53] [PASSED] oob_was/13011645652
[15:20:53] [PASSED] oob_was/14022293748
[15:20:53] [PASSED] oob_was/22019794406
[15:20:53] [PASSED] oob_was/22019338487
[15:20:53] [PASSED] oob_was/16023588340
[15:20:53] [PASSED] oob_was/14019789679
[15:20:53] [PASSED] oob_was/14022866841
[15:20:53] [PASSED] oob_was/16021333562
[15:20:53] [PASSED] oob_was/14016712196
[15:20:53] [PASSED] oob_was/14015568240
[15:20:53] [PASSED] oob_was/18013179988
[15:20:53] [PASSED] oob_was/1508761755
[15:20:53] [PASSED] oob_was/16023105232
[15:20:53] [PASSED] oob_was/16026508708
[15:20:53] [PASSED] oob_was/14020001231
[15:20:53] [PASSED] oob_was/16023683509
[15:20:53] [PASSED] oob_was/14025515070
[15:20:53] [PASSED] oob_was/15015404425_disable
[15:20:53] [PASSED] oob_was/16026007364
[15:20:53] [PASSED] oob_was/14020316580
[15:20:53] [PASSED] oob_was/14025883347
[15:20:53] [PASSED] oob_was/16029380221
[15:20:53] [PASSED] oob_was/22022079272
[15:20:53] [PASSED] oob_was/16029897822
[15:20:53] [PASSED] oob_was/14027054324
[15:20:53] ============== [PASSED] xe_rtp_table_oob_test ==============
[15:20:53] ================ xe_rtp_table_dev_oob_test  ================
[15:20:53] [PASSED] device_oob_was/22010954014
[15:20:53] [PASSED] device_oob_was/15015404425
[15:20:53] [PASSED] device_oob_was/22019338487_display
[15:20:53] [PASSED] device_oob_was/14022085890
[15:20:53] [PASSED] device_oob_was/14026539277
[15:20:53] [PASSED] device_oob_was/14026633728
[15:20:53] [PASSED] device_oob_was/14026746987
[15:20:53] [PASSED] device_oob_was/14026779378
[15:20:53] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[15:20:53] ========== xe_rtp_table_missing_upper_bound_test  ==========
[15:20:53] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[15:20:53] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[15:20:53] [PASSED] register_whitelist/1806527549
[15:20:53] [PASSED] register_whitelist/allow_read_ctx_timestamp
[15:20:53] [PASSED] register_whitelist/allow_read_queue_timestamp
[15:20:53] [PASSED] register_whitelist/16014440446
[15:20:53] [PASSED] register_whitelist/16017236439
[15:20:53] [PASSED] register_whitelist/16020183090
[15:20:53] [PASSED] register_whitelist/14024997852
[15:20:53] [PASSED] register_whitelist/14024997852
[15:20:53] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[15:20:53] =============== [PASSED] xe_rtp_tables_test ================
[15:20:53] =================== xe_rtp (3 subtests) ====================
[15:20:53] =================== xe_rtp_rules_tests  ====================
[15:20:53] [PASSED] no
[15:20:53] [PASSED] yes
[15:20:53] [PASSED] no-and-no
[15:20:53] [PASSED] no-and-yes
[15:20:53] [PASSED] yes-and-no
[15:20:53] [PASSED] yes-and-yes
[15:20:53] [PASSED] no-or-no
[15:20:53] [PASSED] no-or-yes
[15:20:53] [PASSED] yes-or-no
[15:20:53] [PASSED] yes-or-yes
[15:20:53] [PASSED] no-yes-or-yes-no
[15:20:53] [PASSED] no-yes-or-yes-yes
[15:20:53] [PASSED] yes-yes-or-no-yes
[15:20:53] [PASSED] yes-yes-or-yes-yes
[15:20:53] [PASSED] no-no-or-yes-or-no
[15:20:53] [PASSED] or
[15:20:53] [PASSED] or-yes
[15:20:53] [PASSED] or-no
[15:20:53] [PASSED] yes-or
[15:20:53] [PASSED] no-or
[15:20:53] [PASSED] no-or-or-yes
[15:20:53] [PASSED] yes-or-or-no
[15:20:53] [PASSED] no-or-or-no
[15:20:53] [PASSED] missing-context-engine-class
[15:20:53] [PASSED] missing-context-engine-class-or-yes
[15:20:53] [PASSED] missing-context-engine-class-or-or-yes
[15:20:53] =============== [PASSED] xe_rtp_rules_tests ================
[15:20:53] =============== xe_rtp_process_to_sr_tests  ================
[15:20:53] [PASSED] coalesce-same-reg
[15:20:53] [PASSED] coalesce-same-reg-literal-and-func
[15:20:53] [PASSED] no-match-no-add
[15:20:53] [PASSED] two-regs-two-entries
[15:20:53] [PASSED] clr-one-set-other
[15:20:53] [PASSED] set-field
[15:20:53] [PASSED] conflict-duplicate
[15:20:53] [PASSED] conflict-not-disjoint
[15:20:53] [PASSED] conflict-not-disjoint-literal-and-func
[15:20:53] [PASSED] conflict-reg-type
[15:20:53] [PASSED] bad-mcr-reg-forced-to-regular
[15:20:53] [PASSED] bad-regular-reg-forced-to-mcr
[15:20:53] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[15:20:53] ================== xe_rtp_process_tests  ===================
[15:20:53] [PASSED] active1
[15:20:53] [PASSED] active2
[15:20:53] [PASSED] active-inactive
[15:20:53] [PASSED] inactive-active
[15:20:53] [PASSED] inactive-active-inactive
[15:20:53] [PASSED] inactive-inactive-inactive
[15:20:53] ============== [PASSED] xe_rtp_process_tests ===============
[15:20:53] ===================== [PASSED] xe_rtp ======================
[15:20:53] ==================== xe_wa (1 subtest) =====================
[15:20:53] ======================== xe_wa_gt  =========================
[15:20:53] [PASSED] TIGERLAKE B0
[15:20:53] [PASSED] DG1 A0
[15:20:53] [PASSED] DG1 B0
[15:20:53] [PASSED] ALDERLAKE_S A0
[15:20:53] [PASSED] ALDERLAKE_S B0
[15:20:53] [PASSED] ALDERLAKE_S C0
[15:20:53] [PASSED] ALDERLAKE_S D0
[15:20:53] [PASSED] ALDERLAKE_P A0
[15:20:53] [PASSED] ALDERLAKE_P B0
[15:20:53] [PASSED] ALDERLAKE_P C0
[15:20:53] [PASSED] ALDERLAKE_S RPLS D0
[15:20:53] [PASSED] ALDERLAKE_P RPLU E0
[15:20:53] [PASSED] DG2 G10 C0
[15:20:53] [PASSED] DG2 G11 B1
[15:20:53] [PASSED] DG2 G12 A1
[15:20:53] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:20:53] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:20:53] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[15:20:53] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[15:20:53] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[15:20:53] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[15:20:53] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[15:20:53] ==================== [PASSED] xe_wa_gt =====================
[15:20:53] ====================== [PASSED] xe_wa ======================
[15:20:53] ============================================================
[15:20:53] Testing complete. Ran 789 tests: passed: 761, skipped: 28
[15:20:53] Elapsed time: 36.850s total, 4.310s configuring, 31.824s building, 0.674s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[15:20:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:20:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:21:20] Starting KUnit Kernel (1/1)...
[15:21:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:21:20] ============ drm_test_pick_cmdline (2 subtests) ============
[15:21:20] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[15:21:20] =============== drm_test_pick_cmdline_named  ===============
[15:21:20] [PASSED] NTSC
[15:21:20] [PASSED] NTSC-J
[15:21:20] [PASSED] PAL
[15:21:20] [PASSED] PAL-M
[15:21:20] =========== [PASSED] drm_test_pick_cmdline_named ===========
[15:21:20] ============== [PASSED] drm_test_pick_cmdline ==============
[15:21:20] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:21:20] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:21:20] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:21:20] =========== drm_validate_clone_mode (2 subtests) ===========
[15:21:20] ============== drm_test_check_in_clone_mode  ===============
[15:21:20] [PASSED] in_clone_mode
[15:21:20] [PASSED] not_in_clone_mode
[15:21:20] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:21:20] =============== drm_test_check_valid_clones  ===============
[15:21:20] [PASSED] not_in_clone_mode
[15:21:20] [PASSED] valid_clone
[15:21:20] [PASSED] invalid_clone
[15:21:20] =========== [PASSED] drm_test_check_valid_clones ===========
[15:21:20] ============= [PASSED] drm_validate_clone_mode =============
[15:21:20] ============= drm_validate_modeset (1 subtest) =============
[15:21:20] [PASSED] drm_test_check_connector_changed_modeset
[15:21:20] ============== [PASSED] drm_validate_modeset ===============
[15:21:20] ====== drm_test_bridge_get_current_state (1 subtest) =======
[15:21:20] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:21:20] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:21:20] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[15:21:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:21:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:21:20] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[15:21:20] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:21:20] ============== drm_bridge_alloc (2 subtests) ===============
[15:21:20] [PASSED] drm_test_drm_bridge_alloc_basic
[15:21:20] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:21:20] ================ [PASSED] drm_bridge_alloc =================
[15:21:20] ============= drm_bridge_bus_fmt (5 subtests) ==============
[15:21:20] [PASSED] drm_test_bridge_rgb_yuv_rgb
[15:21:20] [PASSED] drm_test_bridge_must_convert_to_yuv444
[15:21:20] [PASSED] drm_test_bridge_hdmi_auto_rgb
[15:21:20] [PASSED] drm_test_bridge_auto_first
[15:21:20] [PASSED] drm_test_bridge_rgb_yuv_no_path
[15:21:20] =============== [PASSED] drm_bridge_bus_fmt ================
[15:21:20] ============= drm_cmdline_parser (40 subtests) =============
[15:21:20] [PASSED] drm_test_cmdline_force_d_only
[15:21:20] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:21:20] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:21:20] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:21:20] [PASSED] drm_test_cmdline_force_e_only
[15:21:20] [PASSED] drm_test_cmdline_res
[15:21:20] [PASSED] drm_test_cmdline_res_vesa
[15:21:20] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:21:20] [PASSED] drm_test_cmdline_res_rblank
[15:21:20] [PASSED] drm_test_cmdline_res_bpp
[15:21:20] [PASSED] drm_test_cmdline_res_refresh
[15:21:20] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:21:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:21:20] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:21:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:21:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:21:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:21:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:21:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:21:20] [PASSED] drm_test_cmdline_res_margins_force_on
[15:21:20] [PASSED] drm_test_cmdline_res_vesa_margins
[15:21:20] [PASSED] drm_test_cmdline_name
[15:21:20] [PASSED] drm_test_cmdline_name_bpp
[15:21:20] [PASSED] drm_test_cmdline_name_option
[15:21:20] [PASSED] drm_test_cmdline_name_bpp_option
[15:21:20] [PASSED] drm_test_cmdline_rotate_0
[15:21:20] [PASSED] drm_test_cmdline_rotate_90
[15:21:20] [PASSED] drm_test_cmdline_rotate_180
[15:21:20] [PASSED] drm_test_cmdline_rotate_270
[15:21:20] [PASSED] drm_test_cmdline_hmirror
[15:21:20] [PASSED] drm_test_cmdline_vmirror
[15:21:20] [PASSED] drm_test_cmdline_margin_options
[15:21:20] [PASSED] drm_test_cmdline_multiple_options
[15:21:20] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:21:20] [PASSED] drm_test_cmdline_extra_and_option
[15:21:20] [PASSED] drm_test_cmdline_freestanding_options
[15:21:20] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:21:20] [PASSED] drm_test_cmdline_panel_orientation
[15:21:20] ================ drm_test_cmdline_invalid  =================
[15:21:20] [PASSED] margin_only
[15:21:20] [PASSED] interlace_only
[15:21:20] [PASSED] res_missing_x
[15:21:20] [PASSED] res_missing_y
[15:21:20] [PASSED] res_bad_y
[15:21:20] [PASSED] res_missing_y_bpp
[15:21:20] [PASSED] res_bad_bpp
[15:21:20] [PASSED] res_bad_refresh
[15:21:20] [PASSED] res_bpp_refresh_force_on_off
[15:21:20] [PASSED] res_invalid_mode
[15:21:20] [PASSED] res_bpp_wrong_place_mode
[15:21:20] [PASSED] name_bpp_refresh
[15:21:20] [PASSED] name_refresh
[15:21:20] [PASSED] name_refresh_wrong_mode
[15:21:20] [PASSED] name_refresh_invalid_mode
[15:21:20] [PASSED] rotate_multiple
[15:21:20] [PASSED] rotate_invalid_val
[15:21:20] [PASSED] rotate_truncated
[15:21:20] [PASSED] invalid_option
[15:21:20] [PASSED] invalid_tv_option
[15:21:20] [PASSED] truncated_tv_option
[15:21:20] ============ [PASSED] drm_test_cmdline_invalid =============
[15:21:20] =============== drm_test_cmdline_tv_options  ===============
[15:21:20] [PASSED] NTSC
[15:21:20] [PASSED] NTSC_443
[15:21:20] [PASSED] NTSC_J
[15:21:20] [PASSED] PAL
[15:21:20] [PASSED] PAL_M
[15:21:20] [PASSED] PAL_N
[15:21:20] [PASSED] SECAM
[15:21:20] [PASSED] MONO_525
[15:21:20] [PASSED] MONO_625
[15:21:20] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:21:20] =============== [PASSED] drm_cmdline_parser ================
[15:21:20] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:21:20] [PASSED] drm_test_connector_hdmi_init_valid
[15:21:20] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:21:20] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:21:20] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:21:20] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:21:20] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:21:20] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:21:20] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:21:20] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[15:21:20] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:21:20] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:21:20] [PASSED] supported_formats=0x5 yuv420_allowed=1
[15:21:20] [PASSED] supported_formats=0x5 yuv420_allowed=0
[15:21:20] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:21:20] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:21:20] [PASSED] drm_test_connector_hdmi_init_null_product
[15:21:20] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:21:20] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:21:20] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:21:20] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:21:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:21:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:21:20] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:21:20] ========= drm_test_connector_hdmi_init_type_valid  =========
[15:21:20] [PASSED] HDMI-A
[15:21:20] [PASSED] HDMI-B
[15:21:20] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:21:20] ======== drm_test_connector_hdmi_init_type_invalid  ========
[15:21:20] [PASSED] Unknown
[15:21:20] [PASSED] VGA
[15:21:20] [PASSED] DVI-I
[15:21:20] [PASSED] DVI-D
[15:21:20] [PASSED] DVI-A
[15:21:20] [PASSED] Composite
[15:21:20] [PASSED] SVIDEO
[15:21:20] [PASSED] LVDS
[15:21:20] [PASSED] Component
[15:21:20] [PASSED] DIN
[15:21:20] [PASSED] DP
[15:21:20] [PASSED] TV
[15:21:20] [PASSED] eDP
[15:21:20] [PASSED] Virtual
[15:21:20] [PASSED] DSI
[15:21:20] [PASSED] DPI
[15:21:20] [PASSED] Writeback
[15:21:20] [PASSED] SPI
[15:21:20] [PASSED] USB
[15:21:20] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:21:20] ============ [PASSED] drmm_connector_hdmi_init =============
[15:21:20] ============= drmm_connector_init (3 subtests) =============
[15:21:20] [PASSED] drm_test_drmm_connector_init
[15:21:20] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:21:20] ========= drm_test_drmm_connector_init_type_valid  =========
[15:21:20] [PASSED] Unknown
[15:21:20] [PASSED] VGA
[15:21:20] [PASSED] DVI-I
[15:21:20] [PASSED] DVI-D
[15:21:20] [PASSED] DVI-A
[15:21:20] [PASSED] Composite
[15:21:20] [PASSED] SVIDEO
[15:21:20] [PASSED] LVDS
[15:21:20] [PASSED] Component
[15:21:20] [PASSED] DIN
[15:21:20] [PASSED] DP
[15:21:20] [PASSED] HDMI-A
[15:21:20] [PASSED] HDMI-B
[15:21:20] [PASSED] TV
[15:21:20] [PASSED] eDP
[15:21:20] [PASSED] Virtual
[15:21:20] [PASSED] DSI
[15:21:20] [PASSED] DPI
[15:21:20] [PASSED] Writeback
[15:21:20] [PASSED] SPI
[15:21:20] [PASSED] USB
[15:21:20] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:21:20] =============== [PASSED] drmm_connector_init ===============
[15:21:20] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_init
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:21:20] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[15:21:20] [PASSED] Unknown
[15:21:20] [PASSED] VGA
[15:21:20] [PASSED] DVI-I
[15:21:20] [PASSED] DVI-D
[15:21:20] [PASSED] DVI-A
[15:21:20] [PASSED] Composite
[15:21:20] [PASSED] SVIDEO
[15:21:20] [PASSED] LVDS
[15:21:20] [PASSED] Component
[15:21:20] [PASSED] DIN
[15:21:20] [PASSED] DP
[15:21:20] [PASSED] HDMI-A
[15:21:20] [PASSED] HDMI-B
[15:21:20] [PASSED] TV
[15:21:20] [PASSED] eDP
[15:21:20] [PASSED] Virtual
[15:21:20] [PASSED] DSI
[15:21:20] [PASSED] DPI
[15:21:20] [PASSED] Writeback
[15:21:20] [PASSED] SPI
[15:21:20] [PASSED] USB
[15:21:20] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:21:20] ======== drm_test_drm_connector_dynamic_init_name  =========
[15:21:20] [PASSED] Unknown
[15:21:20] [PASSED] VGA
[15:21:20] [PASSED] DVI-I
[15:21:20] [PASSED] DVI-D
[15:21:20] [PASSED] DVI-A
[15:21:20] [PASSED] Composite
[15:21:20] [PASSED] SVIDEO
[15:21:20] [PASSED] LVDS
[15:21:20] [PASSED] Component
[15:21:20] [PASSED] DIN
[15:21:20] [PASSED] DP
[15:21:20] [PASSED] HDMI-A
[15:21:20] [PASSED] HDMI-B
[15:21:20] [PASSED] TV
[15:21:20] [PASSED] eDP
[15:21:20] [PASSED] Virtual
[15:21:20] [PASSED] DSI
[15:21:20] [PASSED] DPI
[15:21:20] [PASSED] Writeback
[15:21:20] [PASSED] SPI
[15:21:20] [PASSED] USB
[15:21:20] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:21:20] =========== [PASSED] drm_connector_dynamic_init ============
[15:21:20] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:21:20] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:21:20] ======= drm_connector_dynamic_register (7 subtests) ========
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:21:20] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:21:20] ========= [PASSED] drm_connector_dynamic_register ==========
[15:21:20] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:21:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:21:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:21:20] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:21:20] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:21:20] ========== drm_test_get_tv_mode_from_name_valid  ===========
[15:21:20] [PASSED] NTSC
[15:21:20] [PASSED] NTSC-443
[15:21:20] [PASSED] NTSC-J
[15:21:20] [PASSED] PAL
[15:21:20] [PASSED] PAL-M
[15:21:20] [PASSED] PAL-N
[15:21:20] [PASSED] SECAM
[15:21:20] [PASSED] Mono
[15:21:20] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:21:20] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:21:20] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:21:20] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:21:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:21:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:21:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:21:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:21:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:21:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:21:20] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[15:21:20] [PASSED] VIC 96
[15:21:20] [PASSED] VIC 97
[15:21:20] [PASSED] VIC 101
[15:21:20] [PASSED] VIC 102
[15:21:20] [PASSED] VIC 106
[15:21:20] [PASSED] VIC 107
[15:21:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:21:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:21:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:21:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:21:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:21:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:21:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:21:20] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:21:20] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[15:21:20] [PASSED] Automatic
[15:21:20] [PASSED] Full
[15:21:20] [PASSED] Limited 16:235
[15:21:20] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:21:20] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:21:20] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:21:20] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:21:20] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[15:21:20] [PASSED] RGB
[15:21:20] [PASSED] YUV 4:2:0
[15:21:20] [PASSED] YUV 4:2:2
[15:21:20] [PASSED] YUV 4:4:4
[15:21:20] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:21:20] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:21:20] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:21:20] ============= drm_damage_helper (21 subtests) ==============
[15:21:20] [PASSED] drm_test_damage_iter_no_damage
[15:21:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:21:20] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:21:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:21:20] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:21:20] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:21:20] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:21:20] [PASSED] drm_test_damage_iter_simple_damage
[15:21:20] [PASSED] drm_test_damage_iter_single_damage
[15:21:20] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:21:20] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:21:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:21:20] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:21:20] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:21:20] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:21:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:21:20] [PASSED] drm_test_damage_iter_damage
[15:21:20] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:21:20] [PASSED] drm_test_damage_iter_damage_one_outside
[15:21:20] [PASSED] drm_test_damage_iter_damage_src_moved
[15:21:20] [PASSED] drm_test_damage_iter_damage_not_visible
[15:21:20] ================ [PASSED] drm_damage_helper ================
[15:21:20] ============== drm_dp_mst_helper (3 subtests) ==============
[15:21:20] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[15:21:20] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:21:20] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:21:20] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:21:20] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:21:20] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:21:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:21:20] ============== drm_test_dp_mst_calc_pbn_div  ===============
[15:21:20] [PASSED] Link rate 2000000 lane count 4
[15:21:20] [PASSED] Link rate 2000000 lane count 2
[15:21:20] [PASSED] Link rate 2000000 lane count 1
[15:21:20] [PASSED] Link rate 1350000 lane count 4
[15:21:20] [PASSED] Link rate 1350000 lane count 2
[15:21:20] [PASSED] Link rate 1350000 lane count 1
[15:21:20] [PASSED] Link rate 1000000 lane count 4
[15:21:20] [PASSED] Link rate 1000000 lane count 2
[15:21:20] [PASSED] Link rate 1000000 lane count 1
[15:21:20] [PASSED] Link rate 810000 lane count 4
[15:21:20] [PASSED] Link rate 810000 lane count 2
[15:21:20] [PASSED] Link rate 810000 lane count 1
[15:21:20] [PASSED] Link rate 540000 lane count 4
[15:21:20] [PASSED] Link rate 540000 lane count 2
[15:21:20] [PASSED] Link rate 540000 lane count 1
[15:21:20] [PASSED] Link rate 270000 lane count 4
[15:21:20] [PASSED] Link rate 270000 lane count 2
[15:21:20] [PASSED] Link rate 270000 lane count 1
[15:21:20] [PASSED] Link rate 162000 lane count 4
[15:21:20] [PASSED] Link rate 162000 lane count 2
[15:21:20] [PASSED] Link rate 162000 lane count 1
[15:21:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:21:20] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[15:21:20] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:21:20] [PASSED] DP_POWER_UP_PHY with port number
[15:21:20] [PASSED] DP_POWER_DOWN_PHY with port number
[15:21:20] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:21:20] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:21:20] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:21:20] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:21:20] [PASSED] DP_QUERY_PAYLOAD with port number
[15:21:20] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:21:20] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:21:20] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:21:20] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:21:20] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:21:20] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:21:20] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:21:20] [PASSED] DP_REMOTE_I2C_READ with port number
[15:21:20] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:21:20] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:21:20] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:21:20] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:21:20] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:21:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:21:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:21:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:21:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:21:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:21:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:21:20] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:21:20] ================ [PASSED] drm_dp_mst_helper ================
[15:21:20] ================== drm_exec (7 subtests) ===================
[15:21:20] [PASSED] sanitycheck
[15:21:20] [PASSED] test_lock
[15:21:20] [PASSED] test_lock_unlock
[15:21:20] [PASSED] test_duplicates
[15:21:20] [PASSED] test_prepare
[15:21:20] [PASSED] test_prepare_array
[15:21:20] [PASSED] test_multiple_loops
[15:21:20] ==================== [PASSED] drm_exec =====================
[15:21:20] =========== drm_format_helper_test (17 subtests) ===========
[15:21:20] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:21:20] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:21:20] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:21:20] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:21:20] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:21:20] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:21:20] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:21:20] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:21:20] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:21:20] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:21:20] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:21:20] ============== drm_test_fb_xrgb8888_to_mono  ===============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:21:20] ==================== drm_test_fb_swab  =====================
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ================ [PASSED] drm_test_fb_swab =================
[15:21:20] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:21:20] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[15:21:20] [PASSED] single_pixel_source_buffer
[15:21:20] [PASSED] single_pixel_clip_rectangle
[15:21:20] [PASSED] well_known_colors
[15:21:20] [PASSED] destination_pitch
[15:21:20] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:21:20] ================= drm_test_fb_clip_offset  =================
[15:21:20] [PASSED] pass through
[15:21:20] [PASSED] horizontal offset
[15:21:20] [PASSED] vertical offset
[15:21:20] [PASSED] horizontal and vertical offset
[15:21:20] [PASSED] horizontal offset (custom pitch)
[15:21:20] [PASSED] vertical offset (custom pitch)
[15:21:20] [PASSED] horizontal and vertical offset (custom pitch)
[15:21:20] ============= [PASSED] drm_test_fb_clip_offset =============
[15:21:20] =================== drm_test_fb_memcpy  ====================
[15:21:20] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:21:20] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:21:20] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:21:20] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:21:20] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:21:20] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:21:20] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:21:20] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:21:20] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:21:20] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:21:20] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:21:20] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:21:20] =============== [PASSED] drm_test_fb_memcpy ================
[15:21:20] ============= [PASSED] drm_format_helper_test ==============
[15:21:20] ================= drm_format (18 subtests) =================
[15:21:20] [PASSED] drm_test_format_block_width_invalid
[15:21:20] [PASSED] drm_test_format_block_width_one_plane
[15:21:20] [PASSED] drm_test_format_block_width_two_plane
[15:21:20] [PASSED] drm_test_format_block_width_three_plane
[15:21:20] [PASSED] drm_test_format_block_width_tiled
[15:21:20] [PASSED] drm_test_format_block_height_invalid
[15:21:20] [PASSED] drm_test_format_block_height_one_plane
[15:21:20] [PASSED] drm_test_format_block_height_two_plane
[15:21:20] [PASSED] drm_test_format_block_height_three_plane
[15:21:20] [PASSED] drm_test_format_block_height_tiled
[15:21:20] [PASSED] drm_test_format_min_pitch_invalid
[15:21:20] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:21:20] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:21:20] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:21:20] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:21:20] [PASSED] drm_test_format_min_pitch_two_plane
[15:21:20] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:21:20] [PASSED] drm_test_format_min_pitch_tiled
[15:21:20] =================== [PASSED] drm_format ====================
[15:21:20] ============== drm_framebuffer (10 subtests) ===============
[15:21:20] ========== drm_test_framebuffer_check_src_coords  ==========
[15:21:20] [PASSED] Success: source fits into fb
[15:21:20] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:21:20] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:21:20] [PASSED] Fail: overflowing fb with source width
[15:21:20] [PASSED] Fail: overflowing fb with source height
[15:21:20] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:21:20] [PASSED] drm_test_framebuffer_cleanup
[15:21:20] =============== drm_test_framebuffer_create  ===============
[15:21:20] [PASSED] ABGR8888 normal sizes
[15:21:20] [PASSED] ABGR8888 max sizes
[15:21:20] [PASSED] ABGR8888 pitch greater than min required
[15:21:20] [PASSED] ABGR8888 pitch less than min required
[15:21:20] [PASSED] ABGR8888 Invalid width
[15:21:20] [PASSED] ABGR8888 Invalid buffer handle
[15:21:20] [PASSED] No pixel format
[15:21:20] [PASSED] ABGR8888 Width 0
[15:21:20] [PASSED] ABGR8888 Height 0
[15:21:20] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:21:20] [PASSED] ABGR8888 Large buffer offset
[15:21:20] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:21:20] [PASSED] ABGR8888 Invalid flag
[15:21:20] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:21:20] [PASSED] ABGR8888 Valid buffer modifier
[15:21:20] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:21:20] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:21:20] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:21:20] [PASSED] NV12 Normal sizes
[15:21:20] [PASSED] NV12 Max sizes
[15:21:20] [PASSED] NV12 Invalid pitch
[15:21:20] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:21:20] [PASSED] NV12 different  modifier per-plane
[15:21:20] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:21:20] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:21:20] [PASSED] NV12 Modifier for inexistent plane
[15:21:20] [PASSED] NV12 Handle for inexistent plane
[15:21:20] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:21:20] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:21:20] [PASSED] YVU420 Normal sizes
[15:21:20] [PASSED] YVU420 Max sizes
[15:21:20] [PASSED] YVU420 Invalid pitch
[15:21:20] [PASSED] YVU420 Different pitches
[15:21:20] [PASSED] YVU420 Different buffer offsets/pitches
[15:21:20] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:21:20] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:21:20] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:21:20] [PASSED] YVU420 Valid modifier
[15:21:20] [PASSED] YVU420 Different modifiers per plane
[15:21:20] [PASSED] YVU420 Modifier for inexistent plane
[15:21:20] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:21:20] [PASSED] X0L2 Normal sizes
[15:21:20] [PASSED] X0L2 Max sizes
[15:21:20] [PASSED] X0L2 Invalid pitch
[15:21:20] [PASSED] X0L2 Pitch greater than minimum required
[15:21:20] [PASSED] X0L2 Handle for inexistent plane
[15:21:20] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:21:20] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:21:20] [PASSED] X0L2 Valid modifier
[15:21:20] [PASSED] X0L2 Modifier for inexistent plane
[15:21:20] =========== [PASSED] drm_test_framebuffer_create ===========
[15:21:20] [PASSED] drm_test_framebuffer_free
[15:21:20] [PASSED] drm_test_framebuffer_init
[15:21:20] [PASSED] drm_test_framebuffer_init_bad_format
[15:21:20] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:21:20] [PASSED] drm_test_framebuffer_lookup
[15:21:20] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:21:20] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:21:20] ================= [PASSED] drm_framebuffer =================
[15:21:20] ================ drm_gem_shmem (8 subtests) ================
[15:21:20] [PASSED] drm_gem_shmem_test_obj_create
[15:21:20] [PASSED] drm_gem_shmem_test_obj_create_private
[15:21:20] [PASSED] drm_gem_shmem_test_pin_pages
[15:21:20] [PASSED] drm_gem_shmem_test_vmap
[15:21:20] [PASSED] drm_gem_shmem_test_get_sg_table
[15:21:20] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:21:20] [PASSED] drm_gem_shmem_test_madvise
[15:21:20] [PASSED] drm_gem_shmem_test_purge
[15:21:20] ================== [PASSED] drm_gem_shmem ==================
[15:21:20] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[15:21:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:21:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:21:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:21:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:21:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:21:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:21:20] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[15:21:20] [PASSED] Automatic
[15:21:20] [PASSED] Full
[15:21:20] [PASSED] Limited 16:235
[15:21:20] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:21:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:21:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:21:20] [PASSED] drm_test_check_disable_connector
[15:21:20] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:21:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:21:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:21:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:21:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:21:20] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:21:20] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:21:20] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:21:20] [PASSED] drm_test_check_output_bpc_dvi
[15:21:20] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:21:20] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:21:20] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:21:20] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:21:20] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:21:20] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:21:20] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:21:20] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:21:20] ============ drm_test_check_hdmi_color_format  =============
[15:21:20] [PASSED] AUTO -> RGB
[15:21:20] [PASSED] YCBCR422 -> YUV422
[15:21:20] [PASSED] YCBCR420 -> YUV420
[15:21:20] [PASSED] YCBCR444 -> YUV444
[15:21:20] [PASSED] RGB -> RGB
[15:21:20] ======== [PASSED] drm_test_check_hdmi_color_format =========
[15:21:20] ======== drm_test_check_hdmi_color_format_420_only  ========
[15:21:20] [PASSED] RGB should fail
[15:21:20] [PASSED] YUV444 should fail
[15:21:20] [PASSED] YUV422 should fail
[15:21:20] [PASSED] YUV420 should work
[15:21:20] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[15:21:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:21:20] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:21:20] [PASSED] drm_test_check_broadcast_rgb_value
[15:21:20] [PASSED] drm_test_check_bpc_8_value
[15:21:20] [PASSED] drm_test_check_bpc_10_value
[15:21:20] [PASSED] drm_test_check_bpc_12_value
[15:21:20] [PASSED] drm_test_check_format_value
[15:21:20] [PASSED] drm_test_check_tmds_char_value
[15:21:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:21:20] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[15:21:20] [PASSED] drm_test_check_mode_valid
[15:21:20] [PASSED] drm_test_check_mode_valid_reject
[15:21:20] [PASSED] drm_test_check_mode_valid_reject_rate
[15:21:20] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:21:20] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[15:21:20] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[15:21:20] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[15:21:20] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:21:20] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[15:21:20] [PASSED] drm_test_check_infoframes
[15:21:20] [PASSED] drm_test_check_reject_avi_infoframe
[15:21:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[15:21:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[15:21:20] [PASSED] drm_test_check_reject_audio_infoframe
[15:21:20] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[15:21:20] ================= drm_managed (2 subtests) =================
[15:21:20] [PASSED] drm_test_managed_release_action
[15:21:20] [PASSED] drm_test_managed_run_action
[15:21:20] =================== [PASSED] drm_managed ===================
[15:21:20] =================== drm_mm (6 subtests) ====================
[15:21:20] [PASSED] drm_test_mm_init
[15:21:20] [PASSED] drm_test_mm_debug
[15:21:20] [PASSED] drm_test_mm_align32
[15:21:20] [PASSED] drm_test_mm_align64
[15:21:20] [PASSED] drm_test_mm_lowest
[15:21:20] [PASSED] drm_test_mm_highest
[15:21:20] ===================== [PASSED] drm_mm ======================
[15:21:20] ============= drm_modes_analog_tv (5 subtests) =============
[15:21:20] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:21:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:21:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:21:20] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:21:20] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:21:20] =============== [PASSED] drm_modes_analog_tv ===============
[15:21:20] ============== drm_plane_helper (2 subtests) ===============
[15:21:20] =============== drm_test_check_plane_state  ================
[15:21:20] [PASSED] clipping_simple
[15:21:20] [PASSED] clipping_rotate_reflect
[15:21:20] [PASSED] positioning_simple
[15:21:20] [PASSED] upscaling
[15:21:20] [PASSED] downscaling
[15:21:20] [PASSED] rounding1
[15:21:20] [PASSED] rounding2
[15:21:20] [PASSED] rounding3
[15:21:20] [PASSED] rounding4
[15:21:20] =========== [PASSED] drm_test_check_plane_state ============
[15:21:20] =========== drm_test_check_invalid_plane_state  ============
[15:21:20] [PASSED] positioning_invalid
[15:21:20] [PASSED] upscaling_invalid
[15:21:20] [PASSED] downscaling_invalid
[15:21:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:21:20] ================ [PASSED] drm_plane_helper =================
[15:21:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:21:20] ====== drm_test_connector_helper_tv_get_modes_check  =======
[15:21:20] [PASSED] None
[15:21:20] [PASSED] PAL
[15:21:20] [PASSED] NTSC
[15:21:20] [PASSED] Both, NTSC Default
[15:21:20] [PASSED] Both, PAL Default
[15:21:20] [PASSED] Both, NTSC Default, with PAL on command-line
[15:21:20] [PASSED] Both, PAL Default, with NTSC on command-line
[15:21:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:21:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:21:20] ================== drm_rect (9 subtests) ===================
[15:21:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:21:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:21:20] [PASSED] drm_test_rect_clip_scaled_clipped
[15:21:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:21:20] ================= drm_test_rect_intersect  =================
[15:21:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:21:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:21:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:21:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:21:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:21:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:21:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:21:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:21:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:21:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:21:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:21:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:21:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:21:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:21:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:21:20] ============= [PASSED] drm_test_rect_intersect =============
[15:21:20] ================ drm_test_rect_calc_hscale  ================
[15:21:20] [PASSED] normal use
[15:21:20] [PASSED] out of max range
[15:21:20] [PASSED] out of min range
[15:21:20] [PASSED] zero dst
[15:21:20] [PASSED] negative src
[15:21:20] [PASSED] negative dst
[15:21:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:21:20] ================ drm_test_rect_calc_vscale  ================
[15:21:20] [PASSED] normal use
[15:21:20] [PASSED] out of max range
[15:21:20] [PASSED] out of min range
[15:21:20] [PASSED] zero dst
[15:21:20] [PASSED] negative src
[15:21:20] [PASSED] negative dst
[15:21:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:21:20] ================== drm_test_rect_rotate  ===================
[15:21:20] [PASSED] reflect-x
[15:21:20] [PASSED] reflect-y
[15:21:20] [PASSED] rotate-0
[15:21:20] [PASSED] rotate-90
[15:21:20] [PASSED] rotate-180
[15:21:20] [PASSED] rotate-270
[15:21:20] ============== [PASSED] drm_test_rect_rotate ===============
[15:21:20] ================ drm_test_rect_rotate_inv  =================
[15:21:20] [PASSED] reflect-x
[15:21:20] [PASSED] reflect-y
[15:21:20] [PASSED] rotate-0
[15:21:20] [PASSED] rotate-90
[15:21:20] [PASSED] rotate-180
[15:21:20] [PASSED] rotate-270
[15:21:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:21:20] ==================== [PASSED] drm_rect =====================
[15:21:20] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:21:20] ============ drm_test_sysfb_build_fourcc_list  =============
[15:21:20] [PASSED] no native formats
[15:21:20] [PASSED] XRGB8888 as native format
[15:21:20] [PASSED] remove duplicates
[15:21:20] [PASSED] convert alpha formats
[15:21:20] [PASSED] random formats
[15:21:20] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:21:20] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:21:20] ================== drm_fixp (2 subtests) ===================
[15:21:20] [PASSED] drm_test_int2fixp
[15:21:20] [PASSED] drm_test_sm2fixp
[15:21:20] ==================== [PASSED] drm_fixp =====================
[15:21:20] ============================================================
[15:21:20] Testing complete. Ran 637 tests: passed: 637
[15:21:20] Elapsed time: 26.966s total, 1.807s configuring, 24.943s building, 0.199s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:21:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:21:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:21:32] Starting KUnit Kernel (1/1)...
[15:21:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:21:32] ================= ttm_device (5 subtests) ==================
[15:21:32] [PASSED] ttm_device_init_basic
[15:21:32] [PASSED] ttm_device_init_multiple
[15:21:32] [PASSED] ttm_device_fini_basic
[15:21:32] [PASSED] ttm_device_init_no_vma_man
[15:21:32] ================== ttm_device_init_pools  ==================
[15:21:32] [PASSED] No DMA allocations, no DMA32 required
[15:21:32] [PASSED] DMA allocations, DMA32 required
[15:21:32] [PASSED] No DMA allocations, DMA32 required
[15:21:32] [PASSED] DMA allocations, no DMA32 required
[15:21:32] ============== [PASSED] ttm_device_init_pools ==============
[15:21:32] =================== [PASSED] ttm_device ====================
[15:21:32] ================== ttm_pool (8 subtests) ===================
[15:21:32] ================== ttm_pool_alloc_basic  ===================
[15:21:32] [PASSED] One page
[15:21:32] [PASSED] More than one page
[15:21:32] [PASSED] Above the allocation limit
[15:21:32] [PASSED] One page, with coherent DMA mappings enabled
[15:21:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:21:32] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:21:32] ============== ttm_pool_alloc_basic_dma_addr  ==============
[15:21:32] [PASSED] One page
[15:21:32] [PASSED] More than one page
[15:21:32] [PASSED] Above the allocation limit
[15:21:32] [PASSED] One page, with coherent DMA mappings enabled
[15:21:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:21:32] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:21:32] [PASSED] ttm_pool_alloc_order_caching_match
[15:21:32] [PASSED] ttm_pool_alloc_caching_mismatch
[15:21:32] [PASSED] ttm_pool_alloc_order_mismatch
[15:21:32] [PASSED] ttm_pool_free_dma_alloc
[15:21:32] [PASSED] ttm_pool_free_no_dma_alloc
[15:21:32] [PASSED] ttm_pool_fini_basic
[15:21:32] ==================== [PASSED] ttm_pool =====================
[15:21:32] ================ ttm_resource (8 subtests) =================
[15:21:32] ================= ttm_resource_init_basic  =================
[15:21:32] [PASSED] Init resource in TTM_PL_SYSTEM
[15:21:32] [PASSED] Init resource in TTM_PL_VRAM
[15:21:32] [PASSED] Init resource in a private placement
[15:21:32] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:21:32] ============= [PASSED] ttm_resource_init_basic =============
[15:21:32] [PASSED] ttm_resource_init_pinned
[15:21:32] [PASSED] ttm_resource_fini_basic
[15:21:32] [PASSED] ttm_resource_manager_init_basic
[15:21:32] [PASSED] ttm_resource_manager_usage_basic
[15:21:32] [PASSED] ttm_resource_manager_set_used_basic
[15:21:32] [PASSED] ttm_sys_man_alloc_basic
[15:21:32] [PASSED] ttm_sys_man_free_basic
[15:21:32] ================== [PASSED] ttm_resource ===================
[15:21:32] =================== ttm_tt (15 subtests) ===================
[15:21:32] ==================== ttm_tt_init_basic  ====================
[15:21:32] [PASSED] Page-aligned size
[15:21:32] [PASSED] Extra pages requested
[15:21:32] ================ [PASSED] ttm_tt_init_basic ================
[15:21:32] [PASSED] ttm_tt_init_misaligned
[15:21:32] [PASSED] ttm_tt_fini_basic
[15:21:32] [PASSED] ttm_tt_fini_sg
[15:21:32] [PASSED] ttm_tt_fini_shmem
[15:21:32] [PASSED] ttm_tt_create_basic
[15:21:32] [PASSED] ttm_tt_create_invalid_bo_type
[15:21:32] [PASSED] ttm_tt_create_ttm_exists
[15:21:32] [PASSED] ttm_tt_create_failed
[15:21:32] [PASSED] ttm_tt_destroy_basic
[15:21:32] [PASSED] ttm_tt_populate_null_ttm
[15:21:32] [PASSED] ttm_tt_populate_populated_ttm
[15:21:32] [PASSED] ttm_tt_unpopulate_basic
[15:21:32] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:21:32] [PASSED] ttm_tt_swapin_basic
[15:21:32] ===================== [PASSED] ttm_tt ======================
[15:21:32] =================== ttm_bo (14 subtests) ===================
[15:21:32] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[15:21:32] [PASSED] Cannot be interrupted and sleeps
[15:21:32] [PASSED] Cannot be interrupted, locks straight away
[15:21:32] [PASSED] Can be interrupted, sleeps
[15:21:32] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:21:32] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:21:32] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:21:32] [PASSED] ttm_bo_reserve_double_resv
[15:21:32] [PASSED] ttm_bo_reserve_interrupted
[15:21:32] [PASSED] ttm_bo_reserve_deadlock
[15:21:32] [PASSED] ttm_bo_unreserve_basic
[15:21:32] [PASSED] ttm_bo_unreserve_pinned
[15:21:32] [PASSED] ttm_bo_unreserve_bulk
[15:21:32] [PASSED] ttm_bo_fini_basic
[15:21:32] [PASSED] ttm_bo_fini_shared_resv
[15:21:32] [PASSED] ttm_bo_pin_basic
[15:21:32] [PASSED] ttm_bo_pin_unpin_resource
[15:21:32] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:21:32] ===================== [PASSED] ttm_bo ======================
[15:21:32] ============== ttm_bo_validate (22 subtests) ===============
[15:21:32] ============== ttm_bo_init_reserved_sys_man  ===============
[15:21:32] [PASSED] Buffer object for userspace
[15:21:32] [PASSED] Kernel buffer object
[15:21:32] [PASSED] Shared buffer object
[15:21:32] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:21:32] ============== ttm_bo_init_reserved_mock_man  ==============
[15:21:32] [PASSED] Buffer object for userspace
[15:21:32] [PASSED] Kernel buffer object
[15:21:32] [PASSED] Shared buffer object
[15:21:32] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:21:32] [PASSED] ttm_bo_init_reserved_resv
[15:21:32] ================== ttm_bo_validate_basic  ==================
[15:21:32] [PASSED] Buffer object for userspace
[15:21:32] [PASSED] Kernel buffer object
[15:21:32] [PASSED] Shared buffer object
[15:21:32] ============== [PASSED] ttm_bo_validate_basic ==============
[15:21:32] [PASSED] ttm_bo_validate_invalid_placement
[15:21:32] ============= ttm_bo_validate_same_placement  ==============
[15:21:32] [PASSED] System manager
[15:21:32] [PASSED] VRAM manager
[15:21:32] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:21:32] [PASSED] ttm_bo_validate_failed_alloc
[15:21:32] [PASSED] ttm_bo_validate_pinned
[15:21:32] [PASSED] ttm_bo_validate_busy_placement
[15:21:32] ================ ttm_bo_validate_multihop  =================
[15:21:32] [PASSED] Buffer object for userspace
[15:21:32] [PASSED] Kernel buffer object
[15:21:32] [PASSED] Shared buffer object
[15:21:32] ============ [PASSED] ttm_bo_validate_multihop =============
[15:21:32] ========== ttm_bo_validate_no_placement_signaled  ==========
[15:21:32] [PASSED] Buffer object in system domain, no page vector
[15:21:32] [PASSED] Buffer object in system domain with an existing page vector
[15:21:32] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:21:32] ======== ttm_bo_validate_no_placement_not_signaled  ========
[15:21:32] [PASSED] Buffer object for userspace
[15:21:32] [PASSED] Kernel buffer object
[15:21:32] [PASSED] Shared buffer object
[15:21:32] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:21:32] [PASSED] ttm_bo_validate_move_fence_signaled
[15:21:32] ========= ttm_bo_validate_move_fence_not_signaled  =========
[15:21:32] [PASSED] Waits for GPU
[15:21:32] [PASSED] Tries to lock straight away
[15:21:32] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:21:32] [PASSED] ttm_bo_validate_swapout
[15:21:32] [PASSED] ttm_bo_validate_happy_evict
[15:21:32] [PASSED] ttm_bo_validate_all_pinned_evict
[15:21:32] [PASSED] ttm_bo_validate_allowed_only_evict
[15:21:32] [PASSED] ttm_bo_validate_deleted_evict
[15:21:32] [PASSED] ttm_bo_validate_busy_domain_evict
[15:21:32] [PASSED] ttm_bo_validate_evict_gutting
[15:21:32] [PASSED] ttm_bo_validate_recrusive_evict
[15:21:32] ================= [PASSED] ttm_bo_validate =================
[15:21:32] ============================================================
[15:21:32] Testing complete. Ran 102 tests: passed: 102
[15:21:32] Elapsed time: 11.914s total, 1.756s configuring, 9.893s building, 0.227s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[15:21:32] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:21:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:21:43] Starting KUnit Kernel (1/1)...
[15:21:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:21:43] =============== dma-buf-fence (12 subtests) ================
[15:21:43] [PASSED] test_sanitycheck
[15:21:43] [PASSED] test_signaling
[15:21:43] [PASSED] test_add_callback
[15:21:43] [PASSED] test_late_add_callback
[15:21:43] [PASSED] test_rm_callback
[15:21:43] [PASSED] test_late_rm_callback
[15:21:43] [PASSED] test_status
[15:21:43] [PASSED] test_error
[15:21:43] [PASSED] test_wait
[15:21:43] [PASSED] test_wait_timeout
[15:21:43] [PASSED] test_stub
[15:21:43] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[15:21:43] ================== [PASSED] dma-buf-fence ==================
[15:21:43] ============ dma-buf-fence-chain (11 subtests) =============
[15:21:43] [PASSED] test_sanitycheck
[15:21:43] [PASSED] test_find_seqno
[15:21:43] [PASSED] test_find_signaled
[15:21:43] [PASSED] test_find_out_of_order
[15:21:48] [PASSED] test_find_gap
[15:21:48] [PASSED] test_find_race
[15:21:48] [PASSED] test_signal_forward
[15:21:48] [PASSED] test_signal_backward
[15:21:48] [PASSED] test_wait_forward
[15:21:48] [PASSED] test_wait_backward
[15:21:48] [PASSED] test_wait_random
[15:21:48] =============== [PASSED] dma-buf-fence-chain ===============
[15:21:48] ============ dma-buf-fence-unwrap (10 subtests) ============
[15:21:48] [PASSED] test_sanitycheck
[15:21:48] [PASSED] test_unwrap_array
[15:21:48] [PASSED] test_unwrap_chain
[15:21:48] [PASSED] test_unwrap_chain_array
[15:21:48] [PASSED] test_unwrap_merge
[15:21:48] [PASSED] test_unwrap_merge_duplicate
[15:21:48] [PASSED] test_unwrap_merge_seqno
[15:21:48] [PASSED] test_unwrap_merge_order
[15:21:48] [PASSED] test_unwrap_merge_complex
[15:21:48] [PASSED] test_unwrap_merge_complex_seqno
[15:21:48] ============== [PASSED] dma-buf-fence-unwrap ===============
[15:21:48] ================ dma-buf-resv (5 subtests) =================
[15:21:48] [PASSED] test_sanitycheck
[15:21:48] ===================== test_signaling  ======================
[15:21:48] [PASSED] kernel
[15:21:48] [PASSED] write
[15:21:48] [PASSED] read
[15:21:48] [PASSED] bookkeep
[15:21:48] ================= [PASSED] test_signaling ==================
[15:21:48] ====================== test_for_each  ======================
[15:21:48] [PASSED] kernel
[15:21:48] [PASSED] write
[15:21:48] [PASSED] read
[15:21:48] [PASSED] bookkeep
[15:21:48] ================== [PASSED] test_for_each ==================
[15:21:48] ================= test_for_each_unlocked  ==================
[15:21:48] [PASSED] kernel
[15:21:48] [PASSED] write
[15:21:48] [PASSED] read
[15:21:48] [PASSED] bookkeep
[15:21:48] ============= [PASSED] test_for_each_unlocked ==============
[15:21:48] ===================== test_get_fences  =====================
[15:21:48] [PASSED] kernel
[15:21:48] [PASSED] write
[15:21:48] [PASSED] read
[15:21:48] [PASSED] bookkeep
[15:21:48] ================= [PASSED] test_get_fences =================
[15:21:48] ================== [PASSED] dma-buf-resv ===================
[15:21:48] ============================================================
[15:21:48] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[15:21:48] Elapsed time: 15.544s total, 1.690s configuring, 8.532s building, 5.283s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for VRAM health check + CCS fix

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 844 bytes --]

== Series Details ==

Series: VRAM health check + CCS fix
URL   : https://patchwork.freedesktop.org/series/172984/
State : success

== Summary ==

CI Bug Log - changes from xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832_BAT -> xe-pw-172984v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 12)
------------------------------

  Missing    (1): bat-nvls-1 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832 -> xe-pw-172984v1

  IGT_9078: 9078
  xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832: 5901f93eb5a007e8b7c21ca2b5bfae5958467832
  xe-pw-172984v1: 172984v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/index.html

[-- Attachment #2: Type: text/html, Size: 1392 bytes --]

✓ Xe.CI.FULL: success for VRAM health check + CCS fix

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 34945 bytes --]

== Series Details ==

Series: VRAM health check + CCS fix
URL   : https://patchwork.freedesktop.org/series/172984/
State : success

== Summary ==

CI Bug Log - changes from xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832_FULL -> xe-pw-172984v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-172984v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@device_reset@unbind-reset-rebind:
    - shard-bmg:          [PASS][1] -> [ABORT][2] ([Intel XE#8007]) +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-2/igt@device_reset@unbind-reset-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-2/igt@device_reset@unbind-reset-rebind.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-bmg:          [PASS][3] -> [FAIL][4] ([Intel XE#3718] / [Intel XE#6078])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-7/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-3:
    - shard-bmg:          [PASS][5] -> [FAIL][6] ([Intel XE#6078])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-7/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-3.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2327])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-7/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1407])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1124])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#1124]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-1920x1080p:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#7679])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_bw@connected-linear-tiling-2-displays-target-1920x1080p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2887]) +3 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-6/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#2887])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#3432])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-lut1d:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#7358])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_chamelium_color_pipeline@plane-lut1d-lut1d.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#373])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2252])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-0:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#6969]) +10 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-0.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-plane-2:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#6969] / [Intel XE#7006]) +1 other test skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-plane-2.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          NOTRUN -> [FAIL][20] ([Intel XE#6707] / [Intel XE#7439]) +1 other test fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-6/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-onscreen-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2320])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-6/igt@kms_cursor_crc@cursor-onscreen-32x10.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2321] / [Intel XE#7355])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#4354] / [Intel XE#7386])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#8265])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#8265]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#1138] / [Intel XE#7344])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#1421])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][28] -> [FAIL][29] ([Intel XE#301])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][30] -> [FAIL][31] ([Intel XE#301] / [Intel XE#3149]) +2 other tests fail
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@wf_vblank-ts-check:
    - shard-bmg:          [PASS][32] -> [FAIL][33] ([Intel XE#5408] / [Intel XE#6266])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-10/igt@kms_flip@wf_vblank-ts-check.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-5/igt@kms_flip@wf_vblank-ts-check.html

  * igt@kms_flip@wf_vblank-ts-check@d-dp2:
    - shard-bmg:          [PASS][34] -> [FAIL][35] ([Intel XE#6266])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-10/igt@kms_flip@wf_vblank-ts-check@d-dp2.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-5/igt@kms_flip@wf_vblank-ts-check@d-dp2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#7178] / [Intel XE#7349])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#7178] / [Intel XE#7349])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#7178] / [Intel XE#7351])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7178] / [Intel XE#7351]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#656] / [Intel XE#7905]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#7061] / [Intel XE#7356])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2311]) +15 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-shrfb-scaledprimary:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#6312] / [Intel XE#651]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#4141]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-spr-indfb-move:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#6312]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7399])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrshdr-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2313]) +16 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#7061])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-indfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#7905]) +6 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2350] / [Intel XE#7503])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psrhdr-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#7865]) +5 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_frontbuffer_tracking@psrhdr-suspend.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4298] / [Intel XE#5873])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#6911] / [Intel XE#7378])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#7283])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier.html

  * igt@kms_plane@planar-pixel-format-settings@nv12-tile4-src-y:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#8076])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_plane@planar-pixel-format-settings@nv12-tile4-src-y.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#599])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#4596] / [Intel XE#5854])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc3co-vpb-simulation@psr2-yuv420:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#8396]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_pm_dc@dc3co-vpb-simulation@psr2-yuv420.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#1489]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-7/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#1127] / [Intel XE#5813])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#3904] / [Intel XE#7342])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaler:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#6503])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@kms_sharpness_filter@invalid-filter-with-scaler.html

  * igt@sriov_basic@pf-unbind-with-vf-probed:
    - shard-bmg:          NOTRUN -> [ABORT][66] ([Intel XE#8868])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@sriov_basic@pf-unbind-with-vf-probed.html

  * igt@xe_evict@evict-beng-mixed-threads-large:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#6540] / [Intel XE#688])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_evict@evict-beng-mixed-threads-large.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][68] -> [INCOMPLETE][69] ([Intel XE#6321] / [Intel XE#8355])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-1/igt@xe_evict@evict-mixed-many-threads-small.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_balancer@once-cm-parallel-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#7482]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_exec_balancer@once-cm-parallel-userptr.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-imm:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#8374]) +2 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@xe_exec_fault_mode@many-execqueues-multi-queue-imm.html

  * igt@xe_exec_fault_mode@twice-multi-queue-rebind-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#8374]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_exec_fault_mode@twice-multi-queue-rebind-prefetch.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-basic-smem:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#8364]) +4 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_exec_multi_queue@few-execs-preempt-mode-basic-smem.html

  * igt@xe_exec_multi_queue@two-queues-priority:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#8364]) +7 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@xe_exec_multi_queue@two-queues-priority.html

  * igt@xe_exec_reset@gt-stress-reset-mixed-engine-usage:
    - shard-bmg:          [PASS][76] -> [INCOMPLETE][77] ([Intel XE#9041])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-7/igt@xe_exec_reset@gt-stress-reset-mixed-engine-usage.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-9/igt@xe_exec_reset@gt-stress-reset-mixed-engine-usage.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#8378]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-6/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#8378]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_exec_threads@threads-multi-queue-userptr-rebind.html

  * igt@xe_gt_freq@freq_suspend:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#584] / [Intel XE#7369])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_gt_freq@freq_suspend.html

  * igt@xe_multigpu_svm@mgpu-pagefault-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#6964])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_multigpu_svm@mgpu-pagefault-prefetch.html

  * igt@xe_pat@l2-flush-opt-svm-pat-restrict:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#7590] / [Intel XE#7772])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_pat@l2-flush-opt-svm-pat-restrict.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#7599])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-6/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#4733] / [Intel XE#7417])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-6/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#944])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  * igt@xe_sriov_admin@default-sched-attributes-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#7174])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_sriov_admin@default-sched-attributes-vfs-disabled.html

  * igt@xe_sriov_scheduling@equal-throughput-normal-priority:
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#8339])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-3/igt@xe_sriov_scheduling@equal-throughput-normal-priority.html

  
#### Possible fixes ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][88] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][89] +1 other test pass
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][90] ([Intel XE#301]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][92] ([Intel XE#1503]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-5/igt@kms_hdr@invalid-hdr.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-7/igt@kms_hdr@invalid-hdr.html

  * igt@xe_configfs@gt-types-allowed:
    - shard-bmg:          [ABORT][94] ([Intel XE#8007]) -> [PASS][95] +1 other test pass
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-8/igt@xe_configfs@gt-types-allowed.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-1/igt@xe_configfs@gt-types-allowed.html

  * igt@xe_exec_system_allocator@many-stride-mmap-remap-ro-eocheck:
    - shard-bmg:          [ABORT][96] ([Intel XE#9066]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-5/igt@xe_exec_system_allocator@many-stride-mmap-remap-ro-eocheck.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-6/igt@xe_exec_system_allocator@many-stride-mmap-remap-ro-eocheck.html

  
#### Warnings ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][98] ([Intel XE#301]) -> [FAIL][99] ([Intel XE#301] / [Intel XE#3149])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][100] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][101] ([Intel XE#3544])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][102] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][103] ([Intel XE#2426] / [Intel XE#5848])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][104] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][105] ([Intel XE#2426] / [Intel XE#5848])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2350
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5873
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
  [Intel XE#7386]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7386
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7503
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7772]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7772
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8076]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8076
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8339
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8868
  [Intel XE#9041]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9041
  [Intel XE#9066]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9066
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832 -> xe-pw-172984v1

  IGT_9078: 9078
  xe-5659-5901f93eb5a007e8b7c21ca2b5bfae5958467832: 5901f93eb5a007e8b7c21ca2b5bfae5958467832
  xe-pw-172984v1: 172984v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-172984v1/index.html

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