From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Imre Deak <imre.deak@gmail.com>
Subject: [PATCH 04/17] drm/i915/ddi: Set missing TC DP PHY lane stagger delay in DDI_BUF_CTL
Date: Wed, 29 Jan 2025 22:02:08 +0200 [thread overview]
Message-ID: <20250129200221.2508101-5-imre.deak@intel.com> (raw)
In-Reply-To: <20250129200221.2508101-1-imre.deak@intel.com>
From: Imre Deak <imre.deak@gmail.com>
Add the missing PHY lane stagger delay programming for ICL-ADL
platforms on TypeC DP outputs.
Bspec: 7534, 49533
Signed-off-by: Imre Deak <imre.deak@gmail.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 76e8296cb134b..6192c0d3c87a5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -328,9 +328,21 @@ static u32 ddi_buf_phy_link_rate(int port_clock)
}
}
+static int dp_phy_lane_stagger_delay(int port_clock)
+{
+ /*
+ * Return the number of link symbols per 100 ns:
+ * port_clock (10 kHz) -> bits / 100 us
+ * / symbol_size -> symbols / 100 us
+ * / 1000 -> symbols / 100 ns
+ */
+ return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000);
+}
+
static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
@@ -356,6 +368,12 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
if (!intel_tc_port_in_tbt_alt_mode(dig_port))
intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
+
+ if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {
+ int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock);
+
+ intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay);
+ }
}
static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04e47d0a8ab92..7fe4e71fc08ec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3632,6 +3632,9 @@ enum skl_power_gate {
#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
#define DDI_BUF_PORT_REVERSAL (1 << 16)
+#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8)
+#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \
+ symbols)
#define DDI_BUF_IS_IDLE (1 << 7)
#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
#define DDI_A_4_LANES (1 << 4)
--
2.44.2
next prev parent reply other threads:[~2025-01-29 20:01 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-29 20:02 [PATCH 00/17] drm/i915/ddi: Fix/simplify port enabling/disabling Imre Deak
2025-01-29 20:02 ` [PATCH 01/17] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro Imre Deak
2025-01-30 11:47 ` Jani Nikula
2025-01-29 20:02 ` [PATCH 02/17] drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL Imre Deak
2025-01-30 11:51 ` Jani Nikula
2025-01-30 13:33 ` Imre Deak
2025-01-29 20:02 ` [PATCH 03/17] drm/i915/ddi: Make all the PORT_WIDTH macros work the same way Imre Deak
2025-01-30 11:52 ` Jani Nikula
2025-01-29 20:02 ` Imre Deak [this message]
2025-02-05 12:22 ` [PATCH 04/17] drm/i915/ddi: Set missing TC DP PHY lane stagger delay in DDI_BUF_CTL Jani Nikula
2025-02-05 13:20 ` Imre Deak
2025-01-29 20:02 ` [PATCH 05/17] drm/i915/ddi: Simplify the port enabling via DDI_BUF_CTL Imre Deak
2025-01-30 11:55 ` Jani Nikula
2025-01-30 13:34 ` Imre Deak
2025-01-29 20:02 ` [PATCH 06/17] drm/i915/ddi: Simplify the port disabling " Imre Deak
2025-02-05 12:24 ` Jani Nikula
2025-01-29 20:02 ` [PATCH 07/17] drm/i915/ddi: Simplify waiting for a port to idle " Imre Deak
2025-02-05 12:35 ` Jani Nikula
2025-02-05 12:47 ` Imre Deak
2025-02-05 13:02 ` Jani Nikula
2025-02-12 11:48 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 08/17] drm/i915/ddi: Move platform checks within mtl_ddi_enable/disable_d2d_link() Imre Deak
2025-02-05 12:42 ` Jani Nikula
2025-02-05 13:46 ` Imre Deak
2025-01-29 20:02 ` [PATCH 09/17] drm/i915/ddi: Unify the platform specific functions disabling a port Imre Deak
2025-02-05 12:45 ` Jani Nikula
2025-01-29 20:02 ` [PATCH 10/17] drm/i915/ddi: Add a helper to enable " Imre Deak
2025-02-05 12:49 ` Jani Nikula
2025-02-05 14:43 ` Imre Deak
2025-01-29 20:02 ` [PATCH 11/17] drm/i915/ddi: Sanitize DDI_BUF_CTL register definitions Imre Deak
2025-02-05 12:52 ` Jani Nikula
2025-02-05 14:52 ` Imre Deak
2025-01-29 20:02 ` [PATCH 12/17] drm/i915/ddi: Configure/enable a port in DDI_BUF_CTL via read-modify-write Imre Deak
2025-02-10 18:13 ` Jani Nikula
2025-02-10 18:25 ` Imre Deak
2025-02-12 11:51 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 13/17] drm/i915/ddi: Factor out a helper to get DDI_BUF_CTL's config value Imre Deak
2025-02-10 18:06 ` Jani Nikula
2025-01-29 20:02 ` [PATCH 14/17] drm/i915/ddi: Reuse helper to compute the HDMI DDI_BUF_CTL config Imre Deak
2025-02-11 14:06 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 15/17] drm/i915/ddi: Reuse helper to compute the HDMI PORT_BUF_CTL1 config Imre Deak
2025-02-12 9:51 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 16/17] drm/i915/ddi: Move platform/encoder checks within adlp_tbt_to_dp_alt_switch_wa() Imre Deak
2025-02-12 11:06 ` Kahola, Mika
2025-01-29 20:02 ` [PATCH 17/17] drm/i915/ddi: Unify the platform specific functions enabling a port Imre Deak
2025-02-12 11:26 ` Kahola, Mika
2025-01-29 22:16 ` ✓ CI.Patch_applied: success for drm/i915/ddi: Fix/simplify port enabling/disabling Patchwork
2025-01-29 22:17 ` ✗ CI.checkpatch: warning " Patchwork
2025-01-29 22:18 ` ✓ CI.KUnit: success " Patchwork
2025-01-29 22:34 ` ✓ CI.Build: " Patchwork
2025-01-29 22:37 ` ✓ CI.Hooks: " Patchwork
2025-01-29 22:38 ` ✗ CI.checksparse: warning " Patchwork
2025-01-30 6:22 ` ✓ Xe.CI.BAT: success " Patchwork
2025-01-30 8:27 ` ✗ Xe.CI.Full: failure " Patchwork
2025-01-31 7:42 ` Patchwork
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