Re: [PATCH 03/17] drm/i915/ddi: Make all the PORT_WIDTH macros work the same way

[Jani Nikula <jani.nikula@linux.intel.com>]

On Wed, 29 Jan 2025, Imre Deak <imre.deak@intel.com> wrote:
> Make the PORT_WIDTH macro of the XELPDP_PORT_CTL1 register work the same
> way as those used for the DDI_BUF_CTL and the TRANS_DDI_FUNC_CTL
> registers: accept a width parameter and convert it to the given
> register's encoding.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  3 ++-
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 22 ++-----------------
>  2 files changed, 4 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 4a3cf08007e31..a24531656aa89 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -110,7 +110,8 @@
>  #define   XELPDP_TCSS_POWER_REQUEST			REG_BIT(5)
>  #define   XELPDP_TCSS_POWER_STATE			REG_BIT(4)
>  #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
> -#define   XELPDP_PORT_WIDTH(val)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
> +#define   XELPDP_PORT_WIDTH(width)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \
> +								       (width) == 3 ? 4 : (width) - 1)
>  
>  #define _XELPDP_PORT_BUF_CTL2(idx)			_MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
>  										 _XELPDP_PORT_BUF_CTL1_LN0_A, \
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 36e7dde422d37..76e8296cb134b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2525,23 +2525,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
>  		     OVERLAP_PIXELS_MASK, dss1);
>  }
>  
> -static u8 mtl_get_port_width(u8 lane_count)
> -{
> -	switch (lane_count) {
> -	case 1:
> -		return 0;
> -	case 2:
> -		return 1;
> -	case 3:
> -		return 4;
> -	case 4:
> -		return 3;
> -	default:
> -		MISSING_CASE(lane_count);
> -		return 4;
> -	}
> -}
> -
>  static void
>  mtl_ddi_enable_d2d(struct intel_encoder *encoder)
>  {
> @@ -2575,7 +2558,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
>  	enum port port = encoder->port;
>  	u32 val = 0;
>  
> -	val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
> +	val |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
>  
>  	if (intel_dp_is_uhbr(crtc_state))
>  		val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
> @@ -3490,10 +3473,9 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
>  		buf_ctl |= DDI_A_4_LANES;
>  
>  	if (DISPLAY_VER(dev_priv) >= 14) {
> -		u8  lane_count = mtl_get_port_width(crtc_state->lane_count);
>  		u32 port_buf = 0;
>  
> -		port_buf |= XELPDP_PORT_WIDTH(lane_count);
> +		port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
>  
>  		if (dig_port->lane_reversal)
>  			port_buf |= XELPDP_PORT_REVERSAL;

-- 
Jani Nikula, Intel