[PATCH 00/22] drm/i915/vrr: A few fixes and a bunch of cleanup

[PATCH 00/22] drm/i915/vrr: A few fixes and a bunch of cleanup

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With all the recent work on the VRR code we've accumulated quite
a few slightly rough corners. Try to clean things up a bit.

While testing the cleanups I noticed a few real issues, fixes
for which are included at the start of the series.

Ville Syrjälä (22):
  drm/i915/vrr: Fix intel_vrr_always_use_vrr_tg()==true on TGL
  drm/i915/lrr: Include SCL in lrr_params_changed()
  drm/i915: Remove the "vblank delay" state dump
  drm/i915/vrr: Compute fixed refresh rate timings the sam way as CMRR
    timings
  drm/i915/vrr: Reorganize intel_vrr_compute_cmrr_timings() a bit
  drm/i195/vrr: Move crtc_state->vrr.{vmin,vmax} update into
    intel_vrr_compute_vrr_timings()
  drm/i915/vrr: Move compute_fixed_rr_timings()
  drm/i915/vrr: Extract intel_vrr_set_vrr_timings()
  drm/i915/vrr: Avoid redundant TRANS_PUSH write in intel_vrr_enable()
  drm/i915/vrr: Move EMP_AS_SDP_TL write into
    intel_vrr_set_transcoder_timings()
  drm/i915/vrr: Use trans_vrr_ctl() in intel_vrr_transcoder_disable()
  drm/i915/vrr: Extract intel_vrr_tg_disable()
  drm/i915/vrr: Extract intel_vrr_tg_enable()
  drm/i915/vrr: Disable VRR TG in intel_vrr_transcoder_disable() only on
    always use_vrr_tg() platforms
  drm/i915/vrr: Always write TRANS_VRR_CTL in
    intel_vrr_set_transcoder_timings() on !always_use_vrr_tg()
  drm/i915/vrr: Remove redundant HAS_VRR() checks
  drm/i915/vrr: Move HAS_VRR() check into
    intel_vrr_set_transcoder_timings()
  drm/i915/vrr: s/crtc_state/old_crtc_state/ in
    intel_vrr_transcoder_disable()
  drm/i915/vrr: Nuke intel_vrr_vblank_exit_length()
  drm/i915/vrr: Nuke intel_vrr_vmin_flipline()
  drm/i915/vrr: Update the intel_vrr_extra_vblank_delay() comment
  drm/i915/vrr: Check HAS_VRR() first in intel_vrr_is_capable()

 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  22 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 212 ++++++++----------
 3 files changed, 113 insertions(+), 125 deletions(-)

-- 
2.49.1

[PATCH 01/22] drm/i915/vrr: Fix intel_vrr_always_use_vrr_tg()==true on TGL

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On TGL the hardware always needs TRANS_VBLANK.VBLANK_START
to be programemd with VACTIVE+SCL. Make it so.

The current way of programming it with crtc_vblank_start only
works for the legacy timing generator, as there the delayed
vblank does happen exactly at VACTIVE+SCL.

But if one tries to change intel_vrr_always_use_vrr_tg() to
always use the VRR timing generator on TGL, crtc_vblank_start
will point to the VRR timing generator's delayed vblank,
which may not match VACTIVE+SCL.

Fortunately the state checker caught the issue right away
when I tried intel_vrr_always_use_vrr_tg()==true on TGL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a8b4619de347..09d3eb422ad4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2631,6 +2631,9 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		 * to make it stand out in register dumps.
 		 */
 		crtc_vblank_start = 1;
+	} else if (DISPLAY_VER(display) == 12) {
+		/* VBLANK_START - VACTIVE defines SCL on TGL */
+		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
 	}
 
 	if (DISPLAY_VER(display) >= 4)
@@ -2721,6 +2724,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 		 * to make it stand out in register dumps.
 		 */
 		crtc_vblank_start = 1;
+	} else if (DISPLAY_VER(display) == 12) {
+		/* VBLANK_START - VACTIVE defines SCL on TGL */
+		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
 	}
 
 	/*
-- 
2.49.1

[PATCH 02/22] drm/i915/lrr: Include SCL in lrr_params_changed()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

If SCL is changing we need to take the LRR codepath to update
it during a fastset. Account for that in lrr_params_changed().

The current code will only notice the SCL change if the position
of the delayed vblank also changes. But that might not happen
when using the VRR timing generator because the delayed vblank
is then defined by the guardband instead of the SCL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 09d3eb422ad4..490b4f2907e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5711,12 +5711,16 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
 	return 0;
 }
 
-static bool lrr_params_changed(const struct drm_display_mode *old_adjusted_mode,
-			       const struct drm_display_mode *new_adjusted_mode)
+static bool lrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+			       const struct intel_crtc_state *new_crtc_state)
 {
+	const struct drm_display_mode *old_adjusted_mode = &old_crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *new_adjusted_mode = &new_crtc_state->hw.adjusted_mode;
+
 	return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start ||
 		old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||
-		old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal;
+		old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal ||
+		old_crtc_state->set_context_latency != new_crtc_state->set_context_latency;
 }
 
 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
@@ -5742,8 +5746,7 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
 				   &new_crtc_state->dp_m_n))
 		new_crtc_state->update_m_n = false;
 
-	if (!lrr_params_changed(&old_crtc_state->hw.adjusted_mode,
-				&new_crtc_state->hw.adjusted_mode))
+	if (!lrr_params_changed(old_crtc_state, new_crtc_state))
 		new_crtc_state->update_lrr = false;
 
 	if (intel_crtc_needs_modeset(new_crtc_state))
-- 
2.49.1

[PATCH 03/22] drm/i915: Remove the "vblank delay" state dump

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The "vblank delay" we are including in the crtc state dump is
meaningful only when running with fixed refresh rate timings.
With VRR timings one has to look at the VRR state to figure out
the same thing.

Since we already dump the position of the delayed vblank for
both fixed refresh rate and VRR timings, this "vblank delay"
thing seems pretty much pointless now. Get rid of it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 23e25e97d060..e6f300dbb5ee 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -289,9 +289,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 	drm_printf(&p, "scanline offset: %d\n",
 		   intel_crtc_scanline_offset(pipe_config));
 
-	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d set context latency: %d\n",
-		   pipe_config->hw.adjusted_mode.crtc_vblank_start -
-		   pipe_config->hw.adjusted_mode.crtc_vdisplay,
+	drm_printf(&p, "framestart delay: %d, MSA timing delay: %d, set context latency: %d\n",
 		   pipe_config->framestart_delay, pipe_config->msa_timing_delay,
 		   pipe_config->set_context_latency);
 
-- 
2.49.1

[PATCH 04/22] drm/i915/vrr: Compute fixed refresh rate timings the sam way as CMRR timings

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Unify the VRR timing computation stuff a bit having both the
fixed refrehs rate and CMRR cases assign the crtc_state->vrr
stuff in exactly the same way.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 92fb72b56f16..510dc199376f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -305,12 +305,10 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 static
 void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
 {
-	/*
-	 * For fixed rr,  vmin = vmax = flipline.
-	 * vmin is already set to crtc_vtotal set vmax and flipline the same.
-	 */
+	/* For fixed rr,  vmin = vmax = flipline */
 	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
-	crtc_state->vrr.flipline = crtc_state->hw.adjusted_mode.crtc_vtotal;
+	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
+	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
 }
 
 static
-- 
2.49.1

[PATCH 05/22] drm/i915/vrr: Reorganize intel_vrr_compute_cmrr_timings() a bit

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move the cmrr.enable assignment next to the mode_flags assignment
to keep things in a bit more logical order in
intel_vrr_compute_cmrr_timings().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 510dc199376f..01cb9cfe08e1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -220,7 +220,6 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
 static
 void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 {
-	crtc_state->cmrr.enable = true;
 	/*
 	 * TODO: Compute precise target refresh rate to determine
 	 * if video_mode_required should be true. Currently set to
@@ -230,6 +229,8 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
 	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
 	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
+
+	crtc_state->cmrr.enable = true;
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
-- 
2.49.1

[PATCH 06/22] drm/i195/vrr: Move crtc_state->vrr.{vmin, vmax} update into intel_vrr_compute_vrr_timings()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The way intel_vrr_compute_*_timings() works is rather confusing.
First intel_vrr_compute_config() assigns the computed vmin/vmax
into crtc_state->vrr.{vmin,vmax}, and then either
intel_vrr_compute_vrr_timings() leaves them untouched or
intel_vrr_compute_{cmrr,fixed_rr}_timings() overwrite them with
something else.

Clean this up by moving all crtc_state->vrr.{vmin,vmax} assignments
into intel_vrr_compute_*_timings().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 01cb9cfe08e1..9179ad53a2e7 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -235,8 +235,13 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 }
 
 static
-void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
+void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state,
+				   int vmin, int vmax)
 {
+	crtc_state->vrr.vmax = vmax;
+	crtc_state->vrr.vmin = vmin;
+	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
+
 	crtc_state->vrr.enable = true;
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
@@ -381,13 +386,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		vmax = vmin;
 	}
 
-	crtc_state->vrr.vmin = vmin;
-	crtc_state->vrr.vmax = vmax;
-
-	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
-
 	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
-		intel_vrr_compute_vrr_timings(crtc_state);
+		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
 	else if (is_cmrr_frac_required(crtc_state) && is_edp)
 		intel_vrr_compute_cmrr_timings(crtc_state);
 	else
-- 
2.49.1

[PATCH 07/22] drm/i915/vrr: Move compute_fixed_rr_timings()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Relocate intel_vrr_compute_fixed_rr_timings() next to its
VRR and CMRR counterparts.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 9179ad53a2e7..99e10943368d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -246,6 +246,15 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state,
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
+static
+void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
+{
+	/* For fixed rr,  vmin = vmax = flipline */
+	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
+	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
+	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
+}
+
 static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
 			      int value)
 {
@@ -308,15 +317,6 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
 }
 
-static
-void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
-{
-	/* For fixed rr,  vmin = vmax = flipline */
-	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
-	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
-	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
-}
-
 static
 int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state)
 {
-- 
2.49.1

[PATCH 08/22] drm/i915/vrr: Extract intel_vrr_set_vrr_timings()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract intel_vrr_set_vrr_timings() as the counterpart to
intel_vrr_set_fixed_rr_timings().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 99e10943368d..b2f139addc8b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -686,20 +686,28 @@ static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline);
 }
 
-void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
+static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (!crtc_state->vrr.enable)
-		return;
-
 	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
 		       intel_vrr_hw_vmin(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
 		       intel_vrr_hw_vmax(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
 		       intel_vrr_hw_flipline(crtc_state) - 1);
+}
+
+void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!crtc_state->vrr.enable)
+		return;
+
+	intel_vrr_set_vrr_timings(crtc_state);
 
 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
 		       TRANS_PUSH_EN);
-- 
2.49.1

[PATCH 09/22] drm/i915/vrr: Avoid redundant TRANS_PUSH write in intel_vrr_enable()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We keep TRANS_PUSH_EN always set for always_use_vrr_tg() platfforms,
so there is no need to write it again in  intel_vrr_enable().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b2f139addc8b..6e8f8e673312 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -709,12 +709,12 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 
 	intel_vrr_set_vrr_timings(crtc_state);
 
-	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
-		       TRANS_PUSH_EN);
-
 	if (!intel_vrr_always_use_vrr_tg(display)) {
 		intel_vrr_set_db_point_and_transmission_line(crtc_state);
 
+		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
+			       TRANS_PUSH_EN);
+
 		if (crtc_state->cmrr.enable) {
 			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 				       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
-- 
2.49.1

[PATCH 10/22] drm/i915/vrr: Move EMP_AS_SDP_TL write into intel_vrr_set_transcoder_timings()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

EMP_AS_SDL_TL replaces the TRANS_VRR_VSUNC for the purposes of
setting the AS SDP transmission line. Move the EMP_AS_SDL_TL into
intel_vrr_set_transcoder_timings() since that's where we write
TRANS_VRR_VSYNC as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 35 ++++++++----------------
 1 file changed, 12 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 6e8f8e673312..562a5feadaab 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -571,6 +571,18 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       TRANS_VRR_VSYNC(display, cpu_transcoder),
 			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
 			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
+
+	/*
+	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
+	 * double buffering point and transmission line for VRR packets for
+	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
+	 * Since currently we support VRR only for DP/eDP, so this is programmed
+	 * to for Adaptive Sync SDP to Vsync start.
+	 */
+	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
+		intel_de_write(display,
+			       EMP_AS_SDP_TL(display, cpu_transcoder),
+			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
 }
 
 void intel_vrr_send_push(struct intel_dsb *dsb,
@@ -649,25 +661,6 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
 	return false;
 }
 
-static
-void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(crtc_state);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-
-	/*
-	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
-	 * double buffering point and transmission line for VRR packets for
-	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
-	 * Since currently we support VRR only for DP/eDP, so this is programmed
-	 * to for Adaptive Sync SDP to Vsync start.
-	 */
-	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
-		intel_de_write(display,
-			       EMP_AS_SDP_TL(display, cpu_transcoder),
-			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
-}
-
 static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -710,8 +703,6 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	intel_vrr_set_vrr_timings(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display)) {
-		intel_vrr_set_db_point_and_transmission_line(crtc_state);
-
 		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
 			       TRANS_PUSH_EN);
 
@@ -773,8 +764,6 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
 		       TRANS_PUSH_EN);
 
-	intel_vrr_set_db_point_and_transmission_line(crtc_state);
-
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 		       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
 }
-- 
2.49.1

[PATCH 11/22] drm/i915/vrr: Use trans_vrr_ctl() in intel_vrr_transcoder_disable()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently intel_vrr_disable() writes TRANS_VRR_CTL() with
trans_vrr_ctl(), whereas intel_vrr_transcoder_disable() always
writes just a plain 0. Write trans_vrr_ctl() in both places to
unify the code, allowing for more shared code in the future.

Since the VRR timing generator will be disabled by the
TRANS_VRR_CTL write it doesn't really matter what we write to
the register (other than VRR_CTL_VRR_ENABLE that is).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 562a5feadaab..19b38ad77189 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -779,7 +779,8 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0);
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
+		       trans_vrr_ctl(crtc_state));
 
 	intel_vrr_wait_for_live_status_clear(display, cpu_transcoder);
 
-- 
2.49.1

[PATCH 12/22] drm/i915/vrr: Extract intel_vrr_tg_disable()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we always disable the VRR timing generator the same way
we can extract the duplicated code into a helper.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 42 +++++++++++-------------
 1 file changed, 19 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 19b38ad77189..3ed6a56fb779 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -692,6 +692,22 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_hw_flipline(crtc_state) - 1);
 }
 
+static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_display *display = to_intel_display(old_crtc_state);
+	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
+		       trans_vrr_ctl(old_crtc_state));
+
+	if (intel_de_wait_for_clear(display,
+				    TRANS_VRR_STATUS(display, cpu_transcoder),
+				    VRR_STATUS_VRR_EN_LIVE, 1000))
+		drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
+
+	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
+}
+
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -717,29 +733,15 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	}
 }
 
-static void intel_vrr_wait_for_live_status_clear(struct intel_display *display,
-						 enum transcoder cpu_transcoder)
-{
-	if (intel_de_wait_for_clear(display,
-				    TRANS_VRR_STATUS(display, cpu_transcoder),
-				    VRR_STATUS_VRR_EN_LIVE, 1000))
-		drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
-}
-
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
-	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 
 	if (!old_crtc_state->vrr.enable)
 		return;
 
-	if (!intel_vrr_always_use_vrr_tg(display)) {
-		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-			       trans_vrr_ctl(old_crtc_state));
-		intel_vrr_wait_for_live_status_clear(display, cpu_transcoder);
-		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
-	}
+	if (!intel_vrr_always_use_vrr_tg(display))
+		intel_vrr_tg_disable(old_crtc_state);
 
 	intel_vrr_set_fixed_rr_timings(old_crtc_state);
 }
@@ -771,7 +773,6 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (!HAS_VRR(display))
 		return;
@@ -779,12 +780,7 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-		       trans_vrr_ctl(crtc_state));
-
-	intel_vrr_wait_for_live_status_clear(display, cpu_transcoder);
-
-	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
+	intel_vrr_tg_disable(crtc_state);
 }
 
 bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
-- 
2.49.1

[PATCH 13/22] drm/i915/vrr: Extract intel_vrr_tg_enable()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the VRR timing generator enable into intel_vrr_tg_enable(),
as a counterpart to intel_vrr_tg_disable().

Note that the CMRR part is probably broken, but so are other
things in the CMRR implementation, and thus it is currently
disabled.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 44 ++++++++++++++----------
 1 file changed, 25 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 3ed6a56fb779..b49121b2676c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -692,6 +692,28 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_hw_flipline(crtc_state) - 1);
 }
 
+static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
+				bool cmrr_enable)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 vrr_ctl;
+
+	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
+
+	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
+
+	/*
+	 * FIXME this might be broken as bspec seems to imply that
+	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
+	 * when enabling CMRR (but not when disabling CMRR?).
+	 */
+	if (cmrr_enable)
+		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
+}
+
 static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
@@ -711,26 +733,14 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (!crtc_state->vrr.enable)
 		return;
 
 	intel_vrr_set_vrr_timings(crtc_state);
 
-	if (!intel_vrr_always_use_vrr_tg(display)) {
-		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
-			       TRANS_PUSH_EN);
-
-		if (crtc_state->cmrr.enable) {
-			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-				       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
-				       trans_vrr_ctl(crtc_state));
-		} else {
-			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-				       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
-		}
-	}
+	if (!intel_vrr_always_use_vrr_tg(display))
+		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -763,11 +773,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
-	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
-		       TRANS_PUSH_EN);
-
-	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-		       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+	intel_vrr_tg_enable(crtc_state, false);
 }
 
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
-- 
2.49.1

[PATCH 14/22] drm/i915/vrr: Disable VRR TG in intel_vrr_transcoder_disable() only on always use_vrr_tg() platforms

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we always disable the VRR timing generator in
intel_vrr_transcoder_disable(). But doing so on !always_use_vrr_tg()
platforms is redundant since we've alreayd disabled the VRR timing
generator earlier in intel_vrr_disable(). Do the disable in
intel_vrr_transcoder_disable() only on always_on_vrr_tg() platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b49121b2676c..d8fbbef1ae23 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -786,7 +786,8 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	intel_vrr_tg_disable(crtc_state);
+	if (intel_vrr_always_use_vrr_tg(display))
+		intel_vrr_tg_disable(crtc_state);
 }
 
 bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
-- 
2.49.1

[PATCH 15/22] drm/i915/vrr: Always write TRANS_VRR_CTL in intel_vrr_set_transcoder_timings() on !always_use_vrr_tg()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently, dependign on vrr.enable, we may write TRANS_VRR_CTL from
both intel_vrr_set_transcoder_timings() and intel_vrr_transcoder_enable()
on !always_use_vrr_tg() platforms. Streamline this so that we just
always write it from intel_vrr_set_transcoder_timings(), and
never from intel_vrr_transcoder_enable().

The main benefit is that intel_vrr_transcoder_enable() becomes symmetric
to intel_vrr_transcoder_disable().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d8fbbef1ae23..67b1ed606d8f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -562,7 +562,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 
 	intel_vrr_set_fixed_rr_timings(crtc_state);
 
-	if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable)
+	if (!intel_vrr_always_use_vrr_tg(display))
 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 			       trans_vrr_ctl(crtc_state));
 
@@ -759,7 +759,6 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (!HAS_VRR(display))
 		return;
@@ -767,13 +766,8 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	if (!intel_vrr_always_use_vrr_tg(display)) {
-		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-			       trans_vrr_ctl(crtc_state));
-		return;
-	}
-
-	intel_vrr_tg_enable(crtc_state, false);
+	if (intel_vrr_always_use_vrr_tg(display))
+		intel_vrr_tg_enable(crtc_state, false);
 }
 
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
-- 
2.49.1

[PATCH 16/22] drm/i915/vrr: Remove redundant HAS_VRR() checks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_vrr_transcoder_{enable,disable}() already check
for intel_vrr_possible(), so the extra HAS_VRR() checks are
redundant. Remove them.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 67b1ed606d8f..b64a54d22991 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -760,9 +760,6 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	if (!HAS_VRR(display))
-		return;
-
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
@@ -774,9 +771,6 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	if (!HAS_VRR(display))
-		return;
-
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-- 
2.49.1

[PATCH 17/22] drm/i915/vrr: Move HAS_VRR() check into intel_vrr_set_transcoder_timings()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reduce the clutter in hsw_configure_cpu_transcoder() a bit by moving
the HAS_VRR() check into intel_vrr_set_transcoder_timings().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +--
 drivers/gpu/drm/i915/display/intel_vrr.c     | 3 +++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 490b4f2907e1..2744f83bda2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1581,8 +1581,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 	}
 
 	intel_set_transcoder_timings(crtc_state);
-	if (HAS_VRR(display))
-		intel_vrr_set_transcoder_timings(crtc_state);
+	intel_vrr_set_transcoder_timings(crtc_state);
 
 	if (cpu_transcoder != TRANSCODER_EDP)
 		intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b64a54d22991..29143dd092a8 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -534,6 +534,9 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
+	if (!HAS_VRR(display))
+		return;
+
 	/*
 	 * This bit seems to have two meanings depending on the platform:
 	 * TGL: generate VRR "safe window" for DSB vblank waits
-- 
2.49.1

[PATCH 18/22] drm/i915/vrr: s/crtc_state/old_crtc_state/ in intel_vrr_transcoder_disable()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We generally use the 'old_crtc_state' in the disable functiosn to
make it clear these generally get called when the hardware is
still using the old crtc state rather than the new crtc state.
Rename the intel_vrr_transcoder_disable() 'crtc_state' parameter
to 'old_crtc_state' for consistency.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 29143dd092a8..71c5d8bf7557 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -770,15 +770,15 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 		intel_vrr_tg_enable(crtc_state, false);
 }
 
-void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
+void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_display *display = to_intel_display(old_crtc_state);
 
-	if (!intel_vrr_possible(crtc_state))
+	if (!intel_vrr_possible(old_crtc_state))
 		return;
 
 	if (intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_disable(crtc_state);
+		intel_vrr_tg_disable(old_crtc_state);
 }
 
 bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
-- 
2.49.1

[PATCH 19/22] drm/i915/vrr: Nuke intel_vrr_vblank_exit_length()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we always populate crtc_state->vrr.guardband even on
ICL/TGL intel_vrr_vblank_exit_length() has become rather pointless.
Get rid of it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 71c5d8bf7557..ba92e0a76855 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -143,10 +143,6 @@ static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *c
  *
  * framestart_delay is programmable 1-4.
  */
-static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
-{
-	return crtc_state->vrr.guardband;
-}
 
 int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
 {
@@ -161,12 +157,12 @@ int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
 
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+	return intel_vrr_vmin_vtotal(crtc_state) - crtc_state->vrr.guardband;
 }
 
 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
 }
 
 static bool
-- 
2.49.1

[PATCH 20/22] drm/i915/vrr: Nuke intel_vrr_vmin_flipline()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that intel_vrr_flipline_offset() is completely hidden from the
higher level VRR code, intel_vrr_vmin_flipline() has become rather
pointless. Remove it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index ba92e0a76855..8875e5fe86aa 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -108,11 +108,6 @@ static int intel_vrr_vmin_flipline_offset(struct intel_display *display)
 	return DISPLAY_VER(display) < 13 ? 1 : 0;
 }
 
-static int intel_vrr_vmin_flipline(const struct intel_crtc_state *crtc_state)
-{
-	return crtc_state->vrr.vmin;
-}
-
 static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state,
 						int guardband)
 {
@@ -147,7 +142,7 @@ static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *c
 int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
 {
 	/* Min vblank actually determined by flipline */
-	return intel_vrr_vmin_flipline(crtc_state);
+	return crtc_state->vrr.vmin;
 }
 
 int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
@@ -781,7 +776,7 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
 {
 	return crtc_state->vrr.flipline &&
 	       crtc_state->vrr.flipline == crtc_state->vrr.vmax &&
-	       crtc_state->vrr.flipline == intel_vrr_vmin_flipline(crtc_state);
+	       crtc_state->vrr.flipline == crtc_state->vrr.vmin;
 }
 
 void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
-- 
2.49.1

[PATCH 21/22] drm/i915/vrr: Update the intel_vrr_extra_vblank_delay() comment

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The coment in intel_vrr_extra_vblank_delay() is a bit outdated now
that we generally got rid of the "vblank delay" stuff. Update the
comment to better describe the current state of things.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8875e5fe86aa..c28491b9002a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -87,10 +87,8 @@ static int intel_vrr_extra_vblank_delay(struct intel_display *display)
 	/*
 	 * On ICL/TGL VRR hardware inserts one extra scanline
 	 * just after vactive, which pushes the vmin decision
-	 * boundary ahead accordingly. We'll include the extra
-	 * scanline in our vblank delay estimates to make sure
-	 * that we never underestimate how long we have until
-	 * the delayed vblank has passed.
+	 * boundary ahead accordingly, and thus reduces the
+	 * max guardband length by one scanline.
 	 */
 	return DISPLAY_VER(display) < 13 ? 1 : 0;
 }
-- 
2.49.1

[PATCH 22/22] drm/i915/vrr: Check HAS_VRR() first in intel_vrr_is_capable()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

There's no point in doing all the other checks in
intel_vrr_is_capable() is the platform doesn't support VRR at all
Check HAS_VRR() before wasting time on the other checks.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c28491b9002a..00cbc126fb36 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -25,6 +25,9 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 	const struct drm_display_info *info = &connector->base.display_info;
 	struct intel_dp *intel_dp;
 
+	if (!HAS_VRR(display))
+		return false;
+
 	/*
 	 * DP Sink is capable of VRR video timings if
 	 * Ignore MSA bit is set in DPCD.
@@ -49,8 +52,7 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 		return false;
 	}
 
-	return HAS_VRR(display) &&
-		info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
+	return info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
 }
 
 bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh)
-- 
2.49.1

✓ CI.KUnit: success for drm/i915/vrr: A few fixes and a bunch of cleanup

[Patchwork]

== Series Details ==

Series: drm/i915/vrr: A few fixes and a bunch of cleanup
URL   : https://patchwork.freedesktop.org/series/156222/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[07:47:12] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:47:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[07:47:54] Starting KUnit Kernel (1/1)...
[07:47:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:47:54] ================== guc_buf (11 subtests) ===================
[07:47:54] [PASSED] test_smallest
[07:47:54] [PASSED] test_largest
[07:47:54] [PASSED] test_granular
[07:47:54] [PASSED] test_unique
[07:47:54] [PASSED] test_overlap
[07:47:54] [PASSED] test_reusable
[07:47:54] [PASSED] test_too_big
[07:47:54] [PASSED] test_flush
[07:47:54] [PASSED] test_lookup
[07:47:54] [PASSED] test_data
[07:47:54] [PASSED] test_class
[07:47:54] ===================== [PASSED] guc_buf =====================
[07:47:54] =================== guc_dbm (7 subtests) ===================
[07:47:54] [PASSED] test_empty
[07:47:54] [PASSED] test_default
[07:47:54] ======================== test_size  ========================
[07:47:54] [PASSED] 4
[07:47:54] [PASSED] 8
[07:47:54] [PASSED] 32
[07:47:54] [PASSED] 256
[07:47:54] ==================== [PASSED] test_size ====================
[07:47:54] ======================= test_reuse  ========================
[07:47:54] [PASSED] 4
[07:47:54] [PASSED] 8
[07:47:54] [PASSED] 32
[07:47:54] [PASSED] 256
[07:47:54] =================== [PASSED] test_reuse ====================
[07:47:54] =================== test_range_overlap  ====================
[07:47:54] [PASSED] 4
[07:47:54] [PASSED] 8
[07:47:54] [PASSED] 32
[07:47:54] [PASSED] 256
[07:47:54] =============== [PASSED] test_range_overlap ================
[07:47:54] =================== test_range_compact  ====================
[07:47:54] [PASSED] 4
[07:47:54] [PASSED] 8
[07:47:54] [PASSED] 32
[07:47:54] [PASSED] 256
[07:47:54] =============== [PASSED] test_range_compact ================
[07:47:54] ==================== test_range_spare  =====================
[07:47:54] [PASSED] 4
[07:47:54] [PASSED] 8
[07:47:54] [PASSED] 32
[07:47:54] [PASSED] 256
[07:47:54] ================ [PASSED] test_range_spare =================
[07:47:54] ===================== [PASSED] guc_dbm =====================
[07:47:54] =================== guc_idm (6 subtests) ===================
[07:47:54] [PASSED] bad_init
[07:47:54] [PASSED] no_init
[07:47:54] [PASSED] init_fini
[07:47:54] [PASSED] check_used
[07:47:54] [PASSED] check_quota
[07:47:54] [PASSED] check_all
[07:47:54] ===================== [PASSED] guc_idm =====================
[07:47:54] ================== no_relay (3 subtests) ===================
[07:47:54] [PASSED] xe_drops_guc2pf_if_not_ready
[07:47:54] [PASSED] xe_drops_guc2vf_if_not_ready
[07:47:54] [PASSED] xe_rejects_send_if_not_ready
[07:47:54] ==================== [PASSED] no_relay =====================
[07:47:54] ================== pf_relay (14 subtests) ==================
[07:47:54] [PASSED] pf_rejects_guc2pf_too_short
[07:47:54] [PASSED] pf_rejects_guc2pf_too_long
[07:47:54] [PASSED] pf_rejects_guc2pf_no_payload
[07:47:54] [PASSED] pf_fails_no_payload
[07:47:54] [PASSED] pf_fails_bad_origin
[07:47:54] [PASSED] pf_fails_bad_type
[07:47:54] [PASSED] pf_txn_reports_error
[07:47:54] [PASSED] pf_txn_sends_pf2guc
[07:47:54] [PASSED] pf_sends_pf2guc
[07:47:54] [SKIPPED] pf_loopback_nop
[07:47:54] [SKIPPED] pf_loopback_echo
[07:47:54] [SKIPPED] pf_loopback_fail
[07:47:54] [SKIPPED] pf_loopback_busy
[07:47:54] [SKIPPED] pf_loopback_retry
[07:47:54] ==================== [PASSED] pf_relay =====================
[07:47:54] ================== vf_relay (3 subtests) ===================
[07:47:54] [PASSED] vf_rejects_guc2vf_too_short
[07:47:54] [PASSED] vf_rejects_guc2vf_too_long
[07:47:54] [PASSED] vf_rejects_guc2vf_no_payload
[07:47:54] ==================== [PASSED] vf_relay =====================
[07:47:54] ===================== lmtt (1 subtest) =====================
[07:47:54] ======================== test_ops  =========================
[07:47:54] [PASSED] 2-level
[07:47:54] [PASSED] multi-level
[07:47:54] ==================== [PASSED] test_ops =====================
[07:47:54] ====================== [PASSED] lmtt =======================
[07:47:54] ================= pf_service (11 subtests) =================
[07:47:54] [PASSED] pf_negotiate_any
[07:47:54] [PASSED] pf_negotiate_base_match
[07:47:54] [PASSED] pf_negotiate_base_newer
[07:47:54] [PASSED] pf_negotiate_base_next
[07:47:54] [SKIPPED] pf_negotiate_base_older
[07:47:54] [PASSED] pf_negotiate_base_prev
[07:47:54] [PASSED] pf_negotiate_latest_match
[07:47:54] [PASSED] pf_negotiate_latest_newer
[07:47:54] [PASSED] pf_negotiate_latest_next
[07:47:54] [SKIPPED] pf_negotiate_latest_older
[07:47:54] [SKIPPED] pf_negotiate_latest_prev
[07:47:54] =================== [PASSED] pf_service ====================
[07:47:54] ================= xe_guc_g2g (2 subtests) ==================
[07:47:54] ============== xe_live_guc_g2g_kunit_default  ==============
[07:47:54] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[07:47:54] ============== xe_live_guc_g2g_kunit_allmem  ===============
[07:47:54] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[07:47:54] =================== [SKIPPED] xe_guc_g2g ===================
[07:47:54] =================== xe_mocs (2 subtests) ===================
[07:47:54] ================ xe_live_mocs_kernel_kunit  ================
[07:47:54] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[07:47:54] ================ xe_live_mocs_reset_kunit  =================
[07:47:54] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[07:47:54] ==================== [SKIPPED] xe_mocs =====================
[07:47:54] ================= xe_migrate (2 subtests) ==================
[07:47:54] ================= xe_migrate_sanity_kunit  =================
[07:47:54] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[07:47:54] ================== xe_validate_ccs_kunit  ==================
[07:47:54] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[07:47:54] =================== [SKIPPED] xe_migrate ===================
[07:47:54] ================== xe_dma_buf (1 subtest) ==================
[07:47:54] ==================== xe_dma_buf_kunit  =====================
[07:47:54] ================ [SKIPPED] xe_dma_buf_kunit ================
[07:47:54] =================== [SKIPPED] xe_dma_buf ===================
[07:47:54] ================= xe_bo_shrink (1 subtest) =================
[07:47:54] =================== xe_bo_shrink_kunit  ====================
[07:47:54] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[07:47:54] ================== [SKIPPED] xe_bo_shrink ==================
[07:47:54] ==================== xe_bo (2 subtests) ====================
[07:47:54] ================== xe_ccs_migrate_kunit  ===================
[07:47:54] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[07:47:54] ==================== xe_bo_evict_kunit  ====================
[07:47:54] =============== [SKIPPED] xe_bo_evict_kunit ================
[07:47:54] ===================== [SKIPPED] xe_bo ======================
[07:47:54] ==================== args (11 subtests) ====================
[07:47:54] [PASSED] count_args_test
[07:47:54] [PASSED] call_args_example
[07:47:54] [PASSED] call_args_test
[07:47:54] [PASSED] drop_first_arg_example
[07:47:54] [PASSED] drop_first_arg_test
[07:47:54] [PASSED] first_arg_example
[07:47:54] [PASSED] first_arg_test
[07:47:54] [PASSED] last_arg_example
[07:47:54] [PASSED] last_arg_test
[07:47:54] [PASSED] pick_arg_example
[07:47:54] [PASSED] sep_comma_example
[07:47:54] ====================== [PASSED] args =======================
[07:47:54] =================== xe_pci (3 subtests) ====================
[07:47:54] ==================== check_graphics_ip  ====================
[07:47:54] [PASSED] 12.00 Xe_LP
[07:47:54] [PASSED] 12.10 Xe_LP+
[07:47:54] [PASSED] 12.55 Xe_HPG
[07:47:54] [PASSED] 12.60 Xe_HPC
[07:47:54] [PASSED] 12.70 Xe_LPG
[07:47:54] [PASSED] 12.71 Xe_LPG
[07:47:54] [PASSED] 12.74 Xe_LPG+
[07:47:54] [PASSED] 20.01 Xe2_HPG
[07:47:54] [PASSED] 20.02 Xe2_HPG
[07:47:54] [PASSED] 20.04 Xe2_LPG
[07:47:54] [PASSED] 30.00 Xe3_LPG
[07:47:54] [PASSED] 30.01 Xe3_LPG
[07:47:54] [PASSED] 30.03 Xe3_LPG
[07:47:54] [PASSED] 30.04 Xe3_LPG
[07:47:54] [PASSED] 30.05 Xe3_LPG
[07:47:54] [PASSED] 35.11 Xe3p_XPC
[07:47:54] ================ [PASSED] check_graphics_ip ================
[07:47:54] ===================== check_media_ip  ======================
[07:47:54] [PASSED] 12.00 Xe_M
[07:47:54] [PASSED] 12.55 Xe_HPM
[07:47:54] [PASSED] 13.00 Xe_LPM+
[07:47:54] [PASSED] 13.01 Xe2_HPM
[07:47:54] [PASSED] 20.00 Xe2_LPM
[07:47:54] [PASSED] 30.00 Xe3_LPM
[07:47:54] [PASSED] 30.02 Xe3_LPM
[07:47:54] [PASSED] 35.00 Xe3p_LPM
[07:47:54] [PASSED] 35.03 Xe3p_HPM
[07:47:54] ================= [PASSED] check_media_ip ==================
[07:47:54] ================= check_platform_gt_count  =================
[07:47:54] [PASSED] 0x9A60 (TIGERLAKE)
[07:47:54] [PASSED] 0x9A68 (TIGERLAKE)
[07:47:54] [PASSED] 0x9A70 (TIGERLAKE)
[07:47:54] [PASSED] 0x9A40 (TIGERLAKE)
[07:47:54] [PASSED] 0x9A49 (TIGERLAKE)
[07:47:54] [PASSED] 0x9A59 (TIGERLAKE)
[07:47:54] [PASSED] 0x9A78 (TIGERLAKE)
[07:47:54] [PASSED] 0x9AC0 (TIGERLAKE)
[07:47:54] [PASSED] 0x9AC9 (TIGERLAKE)
[07:47:54] [PASSED] 0x9AD9 (TIGERLAKE)
[07:47:54] [PASSED] 0x9AF8 (TIGERLAKE)
[07:47:54] [PASSED] 0x4C80 (ROCKETLAKE)
[07:47:54] [PASSED] 0x4C8A (ROCKETLAKE)
[07:47:54] [PASSED] 0x4C8B (ROCKETLAKE)
[07:47:54] [PASSED] 0x4C8C (ROCKETLAKE)
[07:47:54] [PASSED] 0x4C90 (ROCKETLAKE)
[07:47:54] [PASSED] 0x4C9A (ROCKETLAKE)
[07:47:54] [PASSED] 0x4680 (ALDERLAKE_S)
[07:47:54] [PASSED] 0x4682 (ALDERLAKE_S)
[07:47:54] [PASSED] 0x4688 (ALDERLAKE_S)
[07:47:54] [PASSED] 0x468A (ALDERLAKE_S)
[07:47:54] [PASSED] 0x468B (ALDERLAKE_S)
[07:47:54] [PASSED] 0x4690 (ALDERLAKE_S)
[07:47:54] [PASSED] 0x4692 (ALDERLAKE_S)
[07:47:54] [PASSED] 0x4693 (ALDERLAKE_S)
[07:47:54] [PASSED] 0x46A0 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46A1 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46A2 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46A3 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46A6 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46A8 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46AA (ALDERLAKE_P)
[07:47:54] [PASSED] 0x462A (ALDERLAKE_P)
[07:47:54] [PASSED] 0x4626 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x4628 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46B0 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46B1 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46B2 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46B3 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46C0 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46C1 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46C2 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46C3 (ALDERLAKE_P)
[07:47:54] [PASSED] 0x46D0 (ALDERLAKE_N)
[07:47:54] [PASSED] 0x46D1 (ALDERLAKE_N)
[07:47:54] [PASSED] 0x46D2 (ALDERLAKE_N)
[07:47:54] [PASSED] 0x46D3 (ALDERLAKE_N)
[07:47:54] [PASSED] 0x46D4 (ALDERLAKE_N)
[07:47:54] [PASSED] 0xA721 (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA7A1 (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA7A9 (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA7AC (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA7AD (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA720 (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA7A0 (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA7A8 (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA7AA (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA7AB (ALDERLAKE_P)
[07:47:54] [PASSED] 0xA780 (ALDERLAKE_S)
[07:47:54] [PASSED] 0xA781 (ALDERLAKE_S)
[07:47:54] [PASSED] 0xA782 (ALDERLAKE_S)
[07:47:54] [PASSED] 0xA783 (ALDERLAKE_S)
[07:47:54] [PASSED] 0xA788 (ALDERLAKE_S)
[07:47:54] [PASSED] 0xA789 (ALDERLAKE_S)
[07:47:54] [PASSED] 0xA78A (ALDERLAKE_S)
[07:47:54] [PASSED] 0xA78B (ALDERLAKE_S)
[07:47:54] [PASSED] 0x4905 (DG1)
[07:47:54] [PASSED] 0x4906 (DG1)
[07:47:54] [PASSED] 0x4907 (DG1)
[07:47:54] [PASSED] 0x4908 (DG1)
[07:47:54] [PASSED] 0x4909 (DG1)
[07:47:54] [PASSED] 0x56C0 (DG2)
[07:47:54] [PASSED] 0x56C2 (DG2)
[07:47:54] [PASSED] 0x56C1 (DG2)
[07:47:54] [PASSED] 0x7D51 (METEORLAKE)
[07:47:54] [PASSED] 0x7DD1 (METEORLAKE)
[07:47:54] [PASSED] 0x7D41 (METEORLAKE)
[07:47:54] [PASSED] 0x7D67 (METEORLAKE)
[07:47:54] [PASSED] 0xB640 (METEORLAKE)
[07:47:54] [PASSED] 0x56A0 (DG2)
[07:47:54] [PASSED] 0x56A1 (DG2)
[07:47:54] [PASSED] 0x56A2 (DG2)
[07:47:54] [PASSED] 0x56BE (DG2)
[07:47:54] [PASSED] 0x56BF (DG2)
[07:47:54] [PASSED] 0x5690 (DG2)
[07:47:54] [PASSED] 0x5691 (DG2)
[07:47:54] [PASSED] 0x5692 (DG2)
[07:47:54] [PASSED] 0x56A5 (DG2)
[07:47:54] [PASSED] 0x56A6 (DG2)
[07:47:54] [PASSED] 0x56B0 (DG2)
[07:47:54] [PASSED] 0x56B1 (DG2)
[07:47:54] [PASSED] 0x56BA (DG2)
[07:47:54] [PASSED] 0x56BB (DG2)
[07:47:54] [PASSED] 0x56BC (DG2)
[07:47:54] [PASSED] 0x56BD (DG2)
[07:47:54] [PASSED] 0x5693 (DG2)
[07:47:54] [PASSED] 0x5694 (DG2)
[07:47:54] [PASSED] 0x5695 (DG2)
[07:47:54] [PASSED] 0x56A3 (DG2)
[07:47:54] [PASSED] 0x56A4 (DG2)
[07:47:54] [PASSED] 0x56B2 (DG2)
[07:47:54] [PASSED] 0x56B3 (DG2)
[07:47:54] [PASSED] 0x5696 (DG2)
[07:47:54] [PASSED] 0x5697 (DG2)
[07:47:54] [PASSED] 0xB69 (PVC)
[07:47:54] [PASSED] 0xB6E (PVC)
[07:47:54] [PASSED] 0xBD4 (PVC)
[07:47:54] [PASSED] 0xBD5 (PVC)
[07:47:54] [PASSED] 0xBD6 (PVC)
[07:47:54] [PASSED] 0xBD7 (PVC)
[07:47:54] [PASSED] 0xBD8 (PVC)
[07:47:54] [PASSED] 0xBD9 (PVC)
[07:47:54] [PASSED] 0xBDA (PVC)
[07:47:54] [PASSED] 0xBDB (PVC)
[07:47:54] [PASSED] 0xBE0 (PVC)
[07:47:54] [PASSED] 0xBE1 (PVC)
[07:47:54] [PASSED] 0xBE5 (PVC)
[07:47:54] [PASSED] 0x7D40 (METEORLAKE)
[07:47:54] [PASSED] 0x7D45 (METEORLAKE)
[07:47:54] [PASSED] 0x7D55 (METEORLAKE)
[07:47:54] [PASSED] 0x7D60 (METEORLAKE)
[07:47:54] [PASSED] 0x7DD5 (METEORLAKE)
[07:47:54] [PASSED] 0x6420 (LUNARLAKE)
[07:47:54] [PASSED] 0x64A0 (LUNARLAKE)
[07:47:54] [PASSED] 0x64B0 (LUNARLAKE)
[07:47:54] [PASSED] 0xE202 (BATTLEMAGE)
[07:47:54] [PASSED] 0xE209 (BATTLEMAGE)
[07:47:54] [PASSED] 0xE20B (BATTLEMAGE)
[07:47:54] [PASSED] 0xE20C (BATTLEMAGE)
[07:47:54] [PASSED] 0xE20D (BATTLEMAGE)
[07:47:54] [PASSED] 0xE210 (BATTLEMAGE)
[07:47:54] [PASSED] 0xE211 (BATTLEMAGE)
[07:47:54] [PASSED] 0xE212 (BATTLEMAGE)
[07:47:54] [PASSED] 0xE216 (BATTLEMAGE)
[07:47:54] [PASSED] 0xE220 (BATTLEMAGE)
[07:47:54] [PASSED] 0xE221 (BATTLEMAGE)
[07:47:54] [PASSED] 0xE222 (BATTLEMAGE)
[07:47:54] [PASSED] 0xE223 (BATTLEMAGE)
[07:47:54] [PASSED] 0xB080 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB081 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB082 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB083 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB084 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB085 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB086 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB087 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB08F (PANTHERLAKE)
[07:47:54] [PASSED] 0xB090 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB0A0 (PANTHERLAKE)
[07:47:54] [PASSED] 0xB0B0 (PANTHERLAKE)
[07:47:54] [PASSED] 0xFD80 (PANTHERLAKE)
[07:47:54] [PASSED] 0xFD81 (PANTHERLAKE)
[07:47:54] [PASSED] 0xD740 (NOVALAKE_S)
[07:47:54] [PASSED] 0xD741 (NOVALAKE_S)
[07:47:54] [PASSED] 0xD742 (NOVALAKE_S)
[07:47:54] [PASSED] 0xD743 (NOVALAKE_S)
[07:47:54] [PASSED] 0xD744 (NOVALAKE_S)
[07:47:54] [PASSED] 0xD745 (NOVALAKE_S)
[07:47:54] ============= [PASSED] check_platform_gt_count =============
[07:47:54] ===================== [PASSED] xe_pci ======================
[07:47:54] =================== xe_rtp (2 subtests) ====================
[07:47:54] =============== xe_rtp_process_to_sr_tests  ================
[07:47:54] [PASSED] coalesce-same-reg
[07:47:54] [PASSED] no-match-no-add
[07:47:54] [PASSED] match-or
[07:47:54] [PASSED] match-or-xfail
[07:47:54] [PASSED] no-match-no-add-multiple-rules
[07:47:54] [PASSED] two-regs-two-entries
[07:47:54] [PASSED] clr-one-set-other
[07:47:54] [PASSED] set-field
[07:47:54] [PASSED] conflict-duplicate
[07:47:54] [PASSED] conflict-not-disjoint
[07:47:54] [PASSED] conflict-reg-type
[07:47:54] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[07:47:54] ================== xe_rtp_process_tests  ===================
[07:47:54] [PASSED] active1
[07:47:54] [PASSED] active2
[07:47:54] [PASSED] active-inactive
[07:47:54] [PASSED] inactive-active
[07:47:54] [PASSED] inactive-1st_or_active-inactive
[07:47:54] [PASSED] inactive-2nd_or_active-inactive
[07:47:54] [PASSED] inactive-last_or_active-inactive
[07:47:54] [PASSED] inactive-no_or_active-inactive
stty: 'standard input': Inappropriate ioctl for device
[07:47:54] ============== [PASSED] xe_rtp_process_tests ===============
[07:47:54] ===================== [PASSED] xe_rtp ======================
[07:47:54] ==================== xe_wa (1 subtest) =====================
[07:47:54] ======================== xe_wa_gt  =========================
[07:47:54] [PASSED] TIGERLAKE B0
[07:47:54] [PASSED] DG1 A0
[07:47:54] [PASSED] DG1 B0
[07:47:54] [PASSED] ALDERLAKE_S A0
[07:47:54] [PASSED] ALDERLAKE_S B0
[07:47:54] [PASSED] ALDERLAKE_S C0
[07:47:54] [PASSED] ALDERLAKE_S D0
[07:47:54] [PASSED] ALDERLAKE_P A0
[07:47:54] [PASSED] ALDERLAKE_P B0
[07:47:54] [PASSED] ALDERLAKE_P C0
[07:47:54] [PASSED] ALDERLAKE_S RPLS D0
[07:47:54] [PASSED] ALDERLAKE_P RPLU E0
[07:47:54] [PASSED] DG2 G10 C0
[07:47:54] [PASSED] DG2 G11 B1
[07:47:54] [PASSED] DG2 G12 A1
[07:47:54] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:47:54] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[07:47:54] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[07:47:54] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[07:47:54] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[07:47:54] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[07:47:54] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[07:47:54] ==================== [PASSED] xe_wa_gt =====================
[07:47:54] ====================== [PASSED] xe_wa ======================
[07:47:54] ============================================================
[07:47:54] Testing complete. Ran 317 tests: passed: 299, skipped: 18
[07:47:54] Elapsed time: 41.603s total, 4.298s configuring, 36.939s building, 0.316s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[07:47:54] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:47:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[07:48:25] Starting KUnit Kernel (1/1)...
[07:48:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:48:25] ============ drm_test_pick_cmdline (2 subtests) ============
[07:48:25] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[07:48:25] =============== drm_test_pick_cmdline_named  ===============
[07:48:25] [PASSED] NTSC
[07:48:25] [PASSED] NTSC-J
[07:48:25] [PASSED] PAL
[07:48:25] [PASSED] PAL-M
[07:48:25] =========== [PASSED] drm_test_pick_cmdline_named ===========
[07:48:25] ============== [PASSED] drm_test_pick_cmdline ==============
[07:48:25] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[07:48:25] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[07:48:25] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[07:48:25] =========== drm_validate_clone_mode (2 subtests) ===========
[07:48:25] ============== drm_test_check_in_clone_mode  ===============
[07:48:25] [PASSED] in_clone_mode
[07:48:25] [PASSED] not_in_clone_mode
[07:48:25] ========== [PASSED] drm_test_check_in_clone_mode ===========
[07:48:25] =============== drm_test_check_valid_clones  ===============
[07:48:25] [PASSED] not_in_clone_mode
[07:48:25] [PASSED] valid_clone
[07:48:25] [PASSED] invalid_clone
[07:48:25] =========== [PASSED] drm_test_check_valid_clones ===========
[07:48:25] ============= [PASSED] drm_validate_clone_mode =============
[07:48:25] ============= drm_validate_modeset (1 subtest) =============
[07:48:25] [PASSED] drm_test_check_connector_changed_modeset
[07:48:25] ============== [PASSED] drm_validate_modeset ===============
[07:48:25] ====== drm_test_bridge_get_current_state (2 subtests) ======
[07:48:25] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[07:48:25] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[07:48:25] ======== [PASSED] drm_test_bridge_get_current_state ========
[07:48:25] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[07:48:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[07:48:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[07:48:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[07:48:25] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[07:48:25] ============== drm_bridge_alloc (2 subtests) ===============
[07:48:25] [PASSED] drm_test_drm_bridge_alloc_basic
[07:48:25] [PASSED] drm_test_drm_bridge_alloc_get_put
[07:48:25] ================ [PASSED] drm_bridge_alloc =================
[07:48:25] ================== drm_buddy (8 subtests) ==================
[07:48:25] [PASSED] drm_test_buddy_alloc_limit
[07:48:25] [PASSED] drm_test_buddy_alloc_optimistic
[07:48:25] [PASSED] drm_test_buddy_alloc_pessimistic
[07:48:25] [PASSED] drm_test_buddy_alloc_pathological
[07:48:25] [PASSED] drm_test_buddy_alloc_contiguous
[07:48:25] [PASSED] drm_test_buddy_alloc_clear
[07:48:25] [PASSED] drm_test_buddy_alloc_range_bias
[07:48:26] [PASSED] drm_test_buddy_fragmentation_performance
[07:48:26] ==================== [PASSED] drm_buddy ====================
[07:48:26] ============= drm_cmdline_parser (40 subtests) =============
[07:48:26] [PASSED] drm_test_cmdline_force_d_only
[07:48:26] [PASSED] drm_test_cmdline_force_D_only_dvi
[07:48:26] [PASSED] drm_test_cmdline_force_D_only_hdmi
[07:48:26] [PASSED] drm_test_cmdline_force_D_only_not_digital
[07:48:26] [PASSED] drm_test_cmdline_force_e_only
[07:48:26] [PASSED] drm_test_cmdline_res
[07:48:26] [PASSED] drm_test_cmdline_res_vesa
[07:48:26] [PASSED] drm_test_cmdline_res_vesa_rblank
[07:48:26] [PASSED] drm_test_cmdline_res_rblank
[07:48:26] [PASSED] drm_test_cmdline_res_bpp
[07:48:26] [PASSED] drm_test_cmdline_res_refresh
[07:48:26] [PASSED] drm_test_cmdline_res_bpp_refresh
[07:48:26] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[07:48:26] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[07:48:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[07:48:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[07:48:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[07:48:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[07:48:26] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[07:48:26] [PASSED] drm_test_cmdline_res_margins_force_on
[07:48:26] [PASSED] drm_test_cmdline_res_vesa_margins
[07:48:26] [PASSED] drm_test_cmdline_name
[07:48:26] [PASSED] drm_test_cmdline_name_bpp
[07:48:26] [PASSED] drm_test_cmdline_name_option
[07:48:26] [PASSED] drm_test_cmdline_name_bpp_option
[07:48:26] [PASSED] drm_test_cmdline_rotate_0
[07:48:26] [PASSED] drm_test_cmdline_rotate_90
[07:48:26] [PASSED] drm_test_cmdline_rotate_180
[07:48:26] [PASSED] drm_test_cmdline_rotate_270
[07:48:26] [PASSED] drm_test_cmdline_hmirror
[07:48:26] [PASSED] drm_test_cmdline_vmirror
[07:48:26] [PASSED] drm_test_cmdline_margin_options
[07:48:26] [PASSED] drm_test_cmdline_multiple_options
[07:48:26] [PASSED] drm_test_cmdline_bpp_extra_and_option
[07:48:26] [PASSED] drm_test_cmdline_extra_and_option
[07:48:26] [PASSED] drm_test_cmdline_freestanding_options
[07:48:26] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[07:48:26] [PASSED] drm_test_cmdline_panel_orientation
[07:48:26] ================ drm_test_cmdline_invalid  =================
[07:48:26] [PASSED] margin_only
[07:48:26] [PASSED] interlace_only
[07:48:26] [PASSED] res_missing_x
[07:48:26] [PASSED] res_missing_y
[07:48:26] [PASSED] res_bad_y
[07:48:26] [PASSED] res_missing_y_bpp
[07:48:26] [PASSED] res_bad_bpp
[07:48:26] [PASSED] res_bad_refresh
[07:48:26] [PASSED] res_bpp_refresh_force_on_off
[07:48:26] [PASSED] res_invalid_mode
[07:48:26] [PASSED] res_bpp_wrong_place_mode
[07:48:26] [PASSED] name_bpp_refresh
[07:48:26] [PASSED] name_refresh
[07:48:26] [PASSED] name_refresh_wrong_mode
[07:48:26] [PASSED] name_refresh_invalid_mode
[07:48:26] [PASSED] rotate_multiple
[07:48:26] [PASSED] rotate_invalid_val
[07:48:26] [PASSED] rotate_truncated
[07:48:26] [PASSED] invalid_option
[07:48:26] [PASSED] invalid_tv_option
[07:48:26] [PASSED] truncated_tv_option
[07:48:26] ============ [PASSED] drm_test_cmdline_invalid =============
[07:48:26] =============== drm_test_cmdline_tv_options  ===============
[07:48:26] [PASSED] NTSC
[07:48:26] [PASSED] NTSC_443
[07:48:26] [PASSED] NTSC_J
[07:48:26] [PASSED] PAL
[07:48:26] [PASSED] PAL_M
[07:48:26] [PASSED] PAL_N
[07:48:26] [PASSED] SECAM
[07:48:26] [PASSED] MONO_525
[07:48:26] [PASSED] MONO_625
[07:48:26] =========== [PASSED] drm_test_cmdline_tv_options ===========
[07:48:26] =============== [PASSED] drm_cmdline_parser ================
[07:48:26] ========== drmm_connector_hdmi_init (20 subtests) ==========
[07:48:26] [PASSED] drm_test_connector_hdmi_init_valid
[07:48:26] [PASSED] drm_test_connector_hdmi_init_bpc_8
[07:48:26] [PASSED] drm_test_connector_hdmi_init_bpc_10
[07:48:26] [PASSED] drm_test_connector_hdmi_init_bpc_12
[07:48:26] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[07:48:26] [PASSED] drm_test_connector_hdmi_init_bpc_null
[07:48:26] [PASSED] drm_test_connector_hdmi_init_formats_empty
[07:48:26] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[07:48:26] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[07:48:26] [PASSED] supported_formats=0x9 yuv420_allowed=1
[07:48:26] [PASSED] supported_formats=0x9 yuv420_allowed=0
[07:48:26] [PASSED] supported_formats=0x3 yuv420_allowed=1
[07:48:26] [PASSED] supported_formats=0x3 yuv420_allowed=0
[07:48:26] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[07:48:26] [PASSED] drm_test_connector_hdmi_init_null_ddc
[07:48:26] [PASSED] drm_test_connector_hdmi_init_null_product
[07:48:26] [PASSED] drm_test_connector_hdmi_init_null_vendor
[07:48:26] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[07:48:26] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[07:48:26] [PASSED] drm_test_connector_hdmi_init_product_valid
[07:48:26] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[07:48:26] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[07:48:26] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[07:48:26] ========= drm_test_connector_hdmi_init_type_valid  =========
[07:48:26] [PASSED] HDMI-A
[07:48:26] [PASSED] HDMI-B
[07:48:26] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[07:48:26] ======== drm_test_connector_hdmi_init_type_invalid  ========
[07:48:26] [PASSED] Unknown
[07:48:26] [PASSED] VGA
[07:48:26] [PASSED] DVI-I
[07:48:26] [PASSED] DVI-D
[07:48:26] [PASSED] DVI-A
[07:48:26] [PASSED] Composite
[07:48:26] [PASSED] SVIDEO
[07:48:26] [PASSED] LVDS
[07:48:26] [PASSED] Component
[07:48:26] [PASSED] DIN
[07:48:26] [PASSED] DP
[07:48:26] [PASSED] TV
[07:48:26] [PASSED] eDP
[07:48:26] [PASSED] Virtual
[07:48:26] [PASSED] DSI
[07:48:26] [PASSED] DPI
[07:48:26] [PASSED] Writeback
[07:48:26] [PASSED] SPI
[07:48:26] [PASSED] USB
[07:48:26] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[07:48:26] ============ [PASSED] drmm_connector_hdmi_init =============
[07:48:26] ============= drmm_connector_init (3 subtests) =============
[07:48:26] [PASSED] drm_test_drmm_connector_init
[07:48:26] [PASSED] drm_test_drmm_connector_init_null_ddc
[07:48:26] ========= drm_test_drmm_connector_init_type_valid  =========
[07:48:26] [PASSED] Unknown
[07:48:26] [PASSED] VGA
[07:48:26] [PASSED] DVI-I
[07:48:26] [PASSED] DVI-D
[07:48:26] [PASSED] DVI-A
[07:48:26] [PASSED] Composite
[07:48:26] [PASSED] SVIDEO
[07:48:26] [PASSED] LVDS
[07:48:26] [PASSED] Component
[07:48:26] [PASSED] DIN
[07:48:26] [PASSED] DP
[07:48:26] [PASSED] HDMI-A
[07:48:26] [PASSED] HDMI-B
[07:48:26] [PASSED] TV
[07:48:26] [PASSED] eDP
[07:48:26] [PASSED] Virtual
[07:48:26] [PASSED] DSI
[07:48:26] [PASSED] DPI
[07:48:26] [PASSED] Writeback
[07:48:26] [PASSED] SPI
[07:48:26] [PASSED] USB
[07:48:26] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[07:48:26] =============== [PASSED] drmm_connector_init ===============
[07:48:26] ========= drm_connector_dynamic_init (6 subtests) ==========
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_init
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_init_properties
[07:48:26] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[07:48:26] [PASSED] Unknown
[07:48:26] [PASSED] VGA
[07:48:26] [PASSED] DVI-I
[07:48:26] [PASSED] DVI-D
[07:48:26] [PASSED] DVI-A
[07:48:26] [PASSED] Composite
[07:48:26] [PASSED] SVIDEO
[07:48:26] [PASSED] LVDS
[07:48:26] [PASSED] Component
[07:48:26] [PASSED] DIN
[07:48:26] [PASSED] DP
[07:48:26] [PASSED] HDMI-A
[07:48:26] [PASSED] HDMI-B
[07:48:26] [PASSED] TV
[07:48:26] [PASSED] eDP
[07:48:26] [PASSED] Virtual
[07:48:26] [PASSED] DSI
[07:48:26] [PASSED] DPI
[07:48:26] [PASSED] Writeback
[07:48:26] [PASSED] SPI
[07:48:26] [PASSED] USB
[07:48:26] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[07:48:26] ======== drm_test_drm_connector_dynamic_init_name  =========
[07:48:26] [PASSED] Unknown
[07:48:26] [PASSED] VGA
[07:48:26] [PASSED] DVI-I
[07:48:26] [PASSED] DVI-D
[07:48:26] [PASSED] DVI-A
[07:48:26] [PASSED] Composite
[07:48:26] [PASSED] SVIDEO
[07:48:26] [PASSED] LVDS
[07:48:26] [PASSED] Component
[07:48:26] [PASSED] DIN
[07:48:26] [PASSED] DP
[07:48:26] [PASSED] HDMI-A
[07:48:26] [PASSED] HDMI-B
[07:48:26] [PASSED] TV
[07:48:26] [PASSED] eDP
[07:48:26] [PASSED] Virtual
[07:48:26] [PASSED] DSI
[07:48:26] [PASSED] DPI
[07:48:26] [PASSED] Writeback
[07:48:26] [PASSED] SPI
[07:48:26] [PASSED] USB
[07:48:26] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[07:48:26] =========== [PASSED] drm_connector_dynamic_init ============
[07:48:26] ==== drm_connector_dynamic_register_early (4 subtests) =====
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[07:48:26] ====== [PASSED] drm_connector_dynamic_register_early =======
[07:48:26] ======= drm_connector_dynamic_register (7 subtests) ========
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[07:48:26] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[07:48:26] ========= [PASSED] drm_connector_dynamic_register ==========
[07:48:26] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[07:48:26] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[07:48:26] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[07:48:26] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[07:48:26] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[07:48:26] ========== drm_test_get_tv_mode_from_name_valid  ===========
[07:48:26] [PASSED] NTSC
[07:48:26] [PASSED] NTSC-443
[07:48:26] [PASSED] NTSC-J
[07:48:26] [PASSED] PAL
[07:48:26] [PASSED] PAL-M
[07:48:26] [PASSED] PAL-N
[07:48:26] [PASSED] SECAM
[07:48:26] [PASSED] Mono
[07:48:26] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[07:48:26] [PASSED] drm_test_get_tv_mode_from_name_truncated
[07:48:26] ============ [PASSED] drm_get_tv_mode_from_name ============
[07:48:26] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[07:48:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[07:48:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[07:48:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[07:48:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[07:48:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[07:48:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[07:48:26] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[07:48:26] [PASSED] VIC 96
[07:48:26] [PASSED] VIC 97
[07:48:26] [PASSED] VIC 101
[07:48:26] [PASSED] VIC 102
[07:48:26] [PASSED] VIC 106
[07:48:26] [PASSED] VIC 107
[07:48:26] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[07:48:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[07:48:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[07:48:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[07:48:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[07:48:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[07:48:26] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[07:48:26] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[07:48:26] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[07:48:26] [PASSED] Automatic
[07:48:26] [PASSED] Full
[07:48:26] [PASSED] Limited 16:235
[07:48:26] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[07:48:26] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[07:48:26] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[07:48:26] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[07:48:26] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[07:48:26] [PASSED] RGB
[07:48:26] [PASSED] YUV 4:2:0
[07:48:26] [PASSED] YUV 4:2:2
[07:48:26] [PASSED] YUV 4:4:4
[07:48:26] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[07:48:26] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[07:48:26] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[07:48:26] ============= drm_damage_helper (21 subtests) ==============
[07:48:26] [PASSED] drm_test_damage_iter_no_damage
[07:48:26] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[07:48:26] [PASSED] drm_test_damage_iter_no_damage_src_moved
[07:48:26] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[07:48:26] [PASSED] drm_test_damage_iter_no_damage_not_visible
[07:48:26] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[07:48:26] [PASSED] drm_test_damage_iter_no_damage_no_fb
[07:48:26] [PASSED] drm_test_damage_iter_simple_damage
[07:48:26] [PASSED] drm_test_damage_iter_single_damage
[07:48:26] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[07:48:26] [PASSED] drm_test_damage_iter_single_damage_outside_src
[07:48:26] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[07:48:26] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[07:48:26] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[07:48:26] [PASSED] drm_test_damage_iter_single_damage_src_moved
[07:48:26] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[07:48:26] [PASSED] drm_test_damage_iter_damage
[07:48:26] [PASSED] drm_test_damage_iter_damage_one_intersect
[07:48:26] [PASSED] drm_test_damage_iter_damage_one_outside
[07:48:26] [PASSED] drm_test_damage_iter_damage_src_moved
[07:48:26] [PASSED] drm_test_damage_iter_damage_not_visible
[07:48:26] ================ [PASSED] drm_damage_helper ================
[07:48:26] ============== drm_dp_mst_helper (3 subtests) ==============
[07:48:26] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[07:48:26] [PASSED] Clock 154000 BPP 30 DSC disabled
[07:48:26] [PASSED] Clock 234000 BPP 30 DSC disabled
[07:48:26] [PASSED] Clock 297000 BPP 24 DSC disabled
[07:48:26] [PASSED] Clock 332880 BPP 24 DSC enabled
[07:48:26] [PASSED] Clock 324540 BPP 24 DSC enabled
[07:48:26] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[07:48:26] ============== drm_test_dp_mst_calc_pbn_div  ===============
[07:48:26] [PASSED] Link rate 2000000 lane count 4
[07:48:26] [PASSED] Link rate 2000000 lane count 2
[07:48:26] [PASSED] Link rate 2000000 lane count 1
[07:48:26] [PASSED] Link rate 1350000 lane count 4
[07:48:26] [PASSED] Link rate 1350000 lane count 2
[07:48:26] [PASSED] Link rate 1350000 lane count 1
[07:48:26] [PASSED] Link rate 1000000 lane count 4
[07:48:26] [PASSED] Link rate 1000000 lane count 2
[07:48:26] [PASSED] Link rate 1000000 lane count 1
[07:48:26] [PASSED] Link rate 810000 lane count 4
[07:48:26] [PASSED] Link rate 810000 lane count 2
[07:48:26] [PASSED] Link rate 810000 lane count 1
[07:48:26] [PASSED] Link rate 540000 lane count 4
[07:48:26] [PASSED] Link rate 540000 lane count 2
[07:48:26] [PASSED] Link rate 540000 lane count 1
[07:48:26] [PASSED] Link rate 270000 lane count 4
[07:48:26] [PASSED] Link rate 270000 lane count 2
[07:48:26] [PASSED] Link rate 270000 lane count 1
[07:48:26] [PASSED] Link rate 162000 lane count 4
[07:48:26] [PASSED] Link rate 162000 lane count 2
[07:48:26] [PASSED] Link rate 162000 lane count 1
[07:48:26] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[07:48:26] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[07:48:26] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[07:48:26] [PASSED] DP_POWER_UP_PHY with port number
[07:48:26] [PASSED] DP_POWER_DOWN_PHY with port number
[07:48:26] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[07:48:26] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[07:48:26] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[07:48:26] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[07:48:26] [PASSED] DP_QUERY_PAYLOAD with port number
[07:48:26] [PASSED] DP_QUERY_PAYLOAD with VCPI
[07:48:26] [PASSED] DP_REMOTE_DPCD_READ with port number
[07:48:26] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[07:48:26] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[07:48:26] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[07:48:26] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[07:48:26] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[07:48:26] [PASSED] DP_REMOTE_I2C_READ with port number
[07:48:26] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[07:48:26] [PASSED] DP_REMOTE_I2C_READ with transactions array
[07:48:26] [PASSED] DP_REMOTE_I2C_WRITE with port number
[07:48:26] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[07:48:26] [PASSED] DP_REMOTE_I2C_WRITE with data array
[07:48:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[07:48:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[07:48:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[07:48:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[07:48:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[07:48:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[07:48:26] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[07:48:26] ================ [PASSED] drm_dp_mst_helper ================
[07:48:26] ================== drm_exec (7 subtests) ===================
[07:48:26] [PASSED] sanitycheck
[07:48:26] [PASSED] test_lock
[07:48:26] [PASSED] test_lock_unlock
[07:48:26] [PASSED] test_duplicates
[07:48:26] [PASSED] test_prepare
[07:48:26] [PASSED] test_prepare_array
[07:48:26] [PASSED] test_multiple_loops
[07:48:26] ==================== [PASSED] drm_exec =====================
[07:48:26] =========== drm_format_helper_test (17 subtests) ===========
[07:48:26] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[07:48:26] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[07:48:26] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[07:48:26] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[07:48:26] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[07:48:26] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[07:48:26] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[07:48:26] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[07:48:26] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[07:48:26] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[07:48:26] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[07:48:26] ============== drm_test_fb_xrgb8888_to_mono  ===============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[07:48:26] ==================== drm_test_fb_swab  =====================
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ================ [PASSED] drm_test_fb_swab =================
[07:48:26] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[07:48:26] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[07:48:26] [PASSED] single_pixel_source_buffer
[07:48:26] [PASSED] single_pixel_clip_rectangle
[07:48:26] [PASSED] well_known_colors
[07:48:26] [PASSED] destination_pitch
[07:48:26] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[07:48:26] ================= drm_test_fb_clip_offset  =================
[07:48:26] [PASSED] pass through
[07:48:26] [PASSED] horizontal offset
[07:48:26] [PASSED] vertical offset
[07:48:26] [PASSED] horizontal and vertical offset
[07:48:26] [PASSED] horizontal offset (custom pitch)
[07:48:26] [PASSED] vertical offset (custom pitch)
[07:48:26] [PASSED] horizontal and vertical offset (custom pitch)
[07:48:26] ============= [PASSED] drm_test_fb_clip_offset =============
[07:48:26] =================== drm_test_fb_memcpy  ====================
[07:48:26] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[07:48:26] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[07:48:26] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[07:48:26] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[07:48:26] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[07:48:26] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[07:48:26] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[07:48:26] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[07:48:26] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[07:48:26] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[07:48:26] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[07:48:26] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[07:48:26] =============== [PASSED] drm_test_fb_memcpy ================
[07:48:26] ============= [PASSED] drm_format_helper_test ==============
[07:48:26] ================= drm_format (18 subtests) =================
[07:48:26] [PASSED] drm_test_format_block_width_invalid
[07:48:26] [PASSED] drm_test_format_block_width_one_plane
[07:48:26] [PASSED] drm_test_format_block_width_two_plane
[07:48:26] [PASSED] drm_test_format_block_width_three_plane
[07:48:26] [PASSED] drm_test_format_block_width_tiled
[07:48:26] [PASSED] drm_test_format_block_height_invalid
[07:48:26] [PASSED] drm_test_format_block_height_one_plane
[07:48:26] [PASSED] drm_test_format_block_height_two_plane
[07:48:26] [PASSED] drm_test_format_block_height_three_plane
[07:48:26] [PASSED] drm_test_format_block_height_tiled
[07:48:26] [PASSED] drm_test_format_min_pitch_invalid
[07:48:26] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[07:48:26] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[07:48:26] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[07:48:26] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[07:48:26] [PASSED] drm_test_format_min_pitch_two_plane
[07:48:26] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[07:48:26] [PASSED] drm_test_format_min_pitch_tiled
[07:48:26] =================== [PASSED] drm_format ====================
[07:48:26] ============== drm_framebuffer (10 subtests) ===============
[07:48:26] ========== drm_test_framebuffer_check_src_coords  ==========
[07:48:26] [PASSED] Success: source fits into fb
[07:48:26] [PASSED] Fail: overflowing fb with x-axis coordinate
[07:48:26] [PASSED] Fail: overflowing fb with y-axis coordinate
[07:48:26] [PASSED] Fail: overflowing fb with source width
[07:48:26] [PASSED] Fail: overflowing fb with source height
[07:48:26] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[07:48:26] [PASSED] drm_test_framebuffer_cleanup
[07:48:26] =============== drm_test_framebuffer_create  ===============
[07:48:26] [PASSED] ABGR8888 normal sizes
[07:48:26] [PASSED] ABGR8888 max sizes
[07:48:26] [PASSED] ABGR8888 pitch greater than min required
[07:48:26] [PASSED] ABGR8888 pitch less than min required
[07:48:26] [PASSED] ABGR8888 Invalid width
[07:48:26] [PASSED] ABGR8888 Invalid buffer handle
[07:48:26] [PASSED] No pixel format
[07:48:26] [PASSED] ABGR8888 Width 0
[07:48:26] [PASSED] ABGR8888 Height 0
[07:48:26] [PASSED] ABGR8888 Out of bound height * pitch combination
[07:48:26] [PASSED] ABGR8888 Large buffer offset
[07:48:26] [PASSED] ABGR8888 Buffer offset for inexistent plane
[07:48:26] [PASSED] ABGR8888 Invalid flag
[07:48:26] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[07:48:26] [PASSED] ABGR8888 Valid buffer modifier
[07:48:26] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[07:48:26] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[07:48:26] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[07:48:26] [PASSED] NV12 Normal sizes
[07:48:26] [PASSED] NV12 Max sizes
[07:48:26] [PASSED] NV12 Invalid pitch
[07:48:26] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[07:48:26] [PASSED] NV12 different  modifier per-plane
[07:48:26] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[07:48:26] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[07:48:26] [PASSED] NV12 Modifier for inexistent plane
[07:48:26] [PASSED] NV12 Handle for inexistent plane
[07:48:26] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[07:48:26] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[07:48:26] [PASSED] YVU420 Normal sizes
[07:48:26] [PASSED] YVU420 Max sizes
[07:48:26] [PASSED] YVU420 Invalid pitch
[07:48:26] [PASSED] YVU420 Different pitches
[07:48:26] [PASSED] YVU420 Different buffer offsets/pitches
[07:48:26] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[07:48:26] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[07:48:26] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[07:48:26] [PASSED] YVU420 Valid modifier
[07:48:26] [PASSED] YVU420 Different modifiers per plane
[07:48:26] [PASSED] YVU420 Modifier for inexistent plane
[07:48:26] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[07:48:26] [PASSED] X0L2 Normal sizes
[07:48:26] [PASSED] X0L2 Max sizes
[07:48:26] [PASSED] X0L2 Invalid pitch
[07:48:26] [PASSED] X0L2 Pitch greater than minimum required
[07:48:26] [PASSED] X0L2 Handle for inexistent plane
[07:48:26] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[07:48:26] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[07:48:26] [PASSED] X0L2 Valid modifier
[07:48:26] [PASSED] X0L2 Modifier for inexistent plane
[07:48:26] =========== [PASSED] drm_test_framebuffer_create ===========
[07:48:26] [PASSED] drm_test_framebuffer_free
[07:48:26] [PASSED] drm_test_framebuffer_init
[07:48:26] [PASSED] drm_test_framebuffer_init_bad_format
[07:48:26] [PASSED] drm_test_framebuffer_init_dev_mismatch
[07:48:26] [PASSED] drm_test_framebuffer_lookup
[07:48:26] [PASSED] drm_test_framebuffer_lookup_inexistent
[07:48:26] [PASSED] drm_test_framebuffer_modifiers_not_supported
[07:48:26] ================= [PASSED] drm_framebuffer =================
[07:48:26] ================ drm_gem_shmem (8 subtests) ================
[07:48:26] [PASSED] drm_gem_shmem_test_obj_create
[07:48:26] [PASSED] drm_gem_shmem_test_obj_create_private
[07:48:26] [PASSED] drm_gem_shmem_test_pin_pages
[07:48:26] [PASSED] drm_gem_shmem_test_vmap
[07:48:26] [PASSED] drm_gem_shmem_test_get_pages_sgt
[07:48:26] [PASSED] drm_gem_shmem_test_get_sg_table
[07:48:26] [PASSED] drm_gem_shmem_test_madvise
[07:48:26] [PASSED] drm_gem_shmem_test_purge
[07:48:26] ================== [PASSED] drm_gem_shmem ==================
[07:48:26] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[07:48:26] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[07:48:26] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[07:48:26] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[07:48:26] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[07:48:26] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[07:48:26] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[07:48:26] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[07:48:26] [PASSED] Automatic
[07:48:26] [PASSED] Full
[07:48:26] [PASSED] Limited 16:235
[07:48:26] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[07:48:26] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[07:48:26] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[07:48:26] [PASSED] drm_test_check_disable_connector
[07:48:26] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[07:48:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[07:48:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[07:48:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[07:48:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[07:48:26] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[07:48:26] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[07:48:26] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[07:48:26] [PASSED] drm_test_check_output_bpc_dvi
[07:48:26] [PASSED] drm_test_check_output_bpc_format_vic_1
[07:48:26] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[07:48:26] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[07:48:26] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[07:48:26] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[07:48:26] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[07:48:26] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[07:48:26] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[07:48:26] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[07:48:26] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[07:48:26] [PASSED] drm_test_check_broadcast_rgb_value
[07:48:26] [PASSED] drm_test_check_bpc_8_value
[07:48:26] [PASSED] drm_test_check_bpc_10_value
[07:48:26] [PASSED] drm_test_check_bpc_12_value
[07:48:26] [PASSED] drm_test_check_format_value
[07:48:26] [PASSED] drm_test_check_tmds_char_value
[07:48:26] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[07:48:26] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[07:48:26] [PASSED] drm_test_check_mode_valid
[07:48:26] [PASSED] drm_test_check_mode_valid_reject
[07:48:26] [PASSED] drm_test_check_mode_valid_reject_rate
[07:48:26] [PASSED] drm_test_check_mode_valid_reject_max_clock
[07:48:26] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[07:48:26] ================= drm_managed (2 subtests) =================
[07:48:26] [PASSED] drm_test_managed_release_action
[07:48:26] [PASSED] drm_test_managed_run_action
[07:48:26] =================== [PASSED] drm_managed ===================
[07:48:26] =================== drm_mm (6 subtests) ====================
[07:48:26] [PASSED] drm_test_mm_init
[07:48:26] [PASSED] drm_test_mm_debug
[07:48:26] [PASSED] drm_test_mm_align32
[07:48:26] [PASSED] drm_test_mm_align64
[07:48:26] [PASSED] drm_test_mm_lowest
[07:48:26] [PASSED] drm_test_mm_highest
[07:48:26] ===================== [PASSED] drm_mm ======================
[07:48:26] ============= drm_modes_analog_tv (5 subtests) =============
[07:48:26] [PASSED] drm_test_modes_analog_tv_mono_576i
[07:48:26] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[07:48:26] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[07:48:26] [PASSED] drm_test_modes_analog_tv_pal_576i
[07:48:26] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[07:48:26] =============== [PASSED] drm_modes_analog_tv ===============
[07:48:26] ============== drm_plane_helper (2 subtests) ===============
[07:48:26] =============== drm_test_check_plane_state  ================
[07:48:26] [PASSED] clipping_simple
[07:48:26] [PASSED] clipping_rotate_reflect
[07:48:26] [PASSED] positioning_simple
[07:48:26] [PASSED] upscaling
[07:48:26] [PASSED] downscaling
[07:48:26] [PASSED] rounding1
[07:48:26] [PASSED] rounding2
[07:48:26] [PASSED] rounding3
[07:48:26] [PASSED] rounding4
[07:48:26] =========== [PASSED] drm_test_check_plane_state ============
[07:48:26] =========== drm_test_check_invalid_plane_state  ============
[07:48:26] [PASSED] positioning_invalid
[07:48:26] [PASSED] upscaling_invalid
[07:48:26] [PASSED] downscaling_invalid
[07:48:26] ======= [PASSED] drm_test_check_invalid_plane_state ========
[07:48:26] ================ [PASSED] drm_plane_helper =================
[07:48:26] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[07:48:26] ====== drm_test_connector_helper_tv_get_modes_check  =======
[07:48:26] [PASSED] None
[07:48:26] [PASSED] PAL
[07:48:26] [PASSED] NTSC
[07:48:26] [PASSED] Both, NTSC Default
[07:48:26] [PASSED] Both, PAL Default
[07:48:26] [PASSED] Both, NTSC Default, with PAL on command-line
[07:48:26] [PASSED] Both, PAL Default, with NTSC on command-line
[07:48:26] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[07:48:26] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[07:48:26] ================== drm_rect (9 subtests) ===================
[07:48:26] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[07:48:26] [PASSED] drm_test_rect_clip_scaled_not_clipped
[07:48:26] [PASSED] drm_test_rect_clip_scaled_clipped
[07:48:26] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[07:48:26] ================= drm_test_rect_intersect  =================
[07:48:26] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[07:48:26] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[07:48:26] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[07:48:26] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[07:48:26] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[07:48:26] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[07:48:26] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[07:48:26] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[07:48:26] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[07:48:26] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[07:48:26] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[07:48:26] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[07:48:26] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[07:48:26] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[07:48:26] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[07:48:26] ============= [PASSED] drm_test_rect_intersect =============
[07:48:26] ================ drm_test_rect_calc_hscale  ================
[07:48:26] [PASSED] normal use
[07:48:26] [PASSED] out of max range
[07:48:26] [PASSED] out of min range
[07:48:26] [PASSED] zero dst
[07:48:26] [PASSED] negative src
[07:48:26] [PASSED] negative dst
[07:48:26] ============ [PASSED] drm_test_rect_calc_hscale ============
[07:48:26] ================ drm_test_rect_calc_vscale  ================
[07:48:26] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[07:48:26] [PASSED] out of max range
[07:48:26] [PASSED] out of min range
[07:48:26] [PASSED] zero dst
[07:48:26] [PASSED] negative src
[07:48:26] [PASSED] negative dst
[07:48:26] ============ [PASSED] drm_test_rect_calc_vscale ============
[07:48:26] ================== drm_test_rect_rotate  ===================
[07:48:26] [PASSED] reflect-x
[07:48:26] [PASSED] reflect-y
[07:48:26] [PASSED] rotate-0
[07:48:26] [PASSED] rotate-90
[07:48:26] [PASSED] rotate-180
[07:48:26] [PASSED] rotate-270
[07:48:26] ============== [PASSED] drm_test_rect_rotate ===============
[07:48:26] ================ drm_test_rect_rotate_inv  =================
[07:48:26] [PASSED] reflect-x
[07:48:26] [PASSED] reflect-y
[07:48:26] [PASSED] rotate-0
[07:48:26] [PASSED] rotate-90
[07:48:26] [PASSED] rotate-180
[07:48:26] [PASSED] rotate-270
[07:48:26] ============ [PASSED] drm_test_rect_rotate_inv =============
[07:48:26] ==================== [PASSED] drm_rect =====================
[07:48:26] ============ drm_sysfb_modeset_test (1 subtest) ============
[07:48:26] ============ drm_test_sysfb_build_fourcc_list  =============
[07:48:26] [PASSED] no native formats
[07:48:26] [PASSED] XRGB8888 as native format
[07:48:26] [PASSED] remove duplicates
[07:48:26] [PASSED] convert alpha formats
[07:48:26] [PASSED] random formats
[07:48:26] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[07:48:26] ============= [PASSED] drm_sysfb_modeset_test ==============
[07:48:26] ============================================================
[07:48:26] Testing complete. Ran 622 tests: passed: 622
[07:48:26] Elapsed time: 31.563s total, 1.615s configuring, 29.431s building, 0.469s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[07:48:26] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[07:48:27] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[07:48:37] Starting KUnit Kernel (1/1)...
[07:48:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[07:48:37] ================= ttm_device (5 subtests) ==================
[07:48:37] [PASSED] ttm_device_init_basic
[07:48:37] [PASSED] ttm_device_init_multiple
[07:48:37] [PASSED] ttm_device_fini_basic
[07:48:37] [PASSED] ttm_device_init_no_vma_man
[07:48:37] ================== ttm_device_init_pools  ==================
[07:48:37] [PASSED] No DMA allocations, no DMA32 required
[07:48:37] [PASSED] DMA allocations, DMA32 required
[07:48:37] [PASSED] No DMA allocations, DMA32 required
[07:48:37] [PASSED] DMA allocations, no DMA32 required
[07:48:37] ============== [PASSED] ttm_device_init_pools ==============
[07:48:37] =================== [PASSED] ttm_device ====================
[07:48:37] ================== ttm_pool (8 subtests) ===================
[07:48:37] ================== ttm_pool_alloc_basic  ===================
[07:48:37] [PASSED] One page
[07:48:37] [PASSED] More than one page
[07:48:37] [PASSED] Above the allocation limit
[07:48:37] [PASSED] One page, with coherent DMA mappings enabled
[07:48:37] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:48:37] ============== [PASSED] ttm_pool_alloc_basic ===============
[07:48:37] ============== ttm_pool_alloc_basic_dma_addr  ==============
[07:48:37] [PASSED] One page
[07:48:37] [PASSED] More than one page
[07:48:37] [PASSED] Above the allocation limit
[07:48:37] [PASSED] One page, with coherent DMA mappings enabled
[07:48:37] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[07:48:37] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[07:48:37] [PASSED] ttm_pool_alloc_order_caching_match
[07:48:37] [PASSED] ttm_pool_alloc_caching_mismatch
[07:48:37] [PASSED] ttm_pool_alloc_order_mismatch
[07:48:37] [PASSED] ttm_pool_free_dma_alloc
[07:48:37] [PASSED] ttm_pool_free_no_dma_alloc
[07:48:37] [PASSED] ttm_pool_fini_basic
[07:48:37] ==================== [PASSED] ttm_pool =====================
[07:48:37] ================ ttm_resource (8 subtests) =================
[07:48:37] ================= ttm_resource_init_basic  =================
[07:48:37] [PASSED] Init resource in TTM_PL_SYSTEM
[07:48:37] [PASSED] Init resource in TTM_PL_VRAM
[07:48:37] [PASSED] Init resource in a private placement
[07:48:37] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[07:48:37] ============= [PASSED] ttm_resource_init_basic =============
[07:48:37] [PASSED] ttm_resource_init_pinned
[07:48:37] [PASSED] ttm_resource_fini_basic
[07:48:37] [PASSED] ttm_resource_manager_init_basic
[07:48:37] [PASSED] ttm_resource_manager_usage_basic
[07:48:37] [PASSED] ttm_resource_manager_set_used_basic
[07:48:37] [PASSED] ttm_sys_man_alloc_basic
[07:48:37] [PASSED] ttm_sys_man_free_basic
[07:48:37] ================== [PASSED] ttm_resource ===================
[07:48:37] =================== ttm_tt (15 subtests) ===================
[07:48:37] ==================== ttm_tt_init_basic  ====================
[07:48:37] [PASSED] Page-aligned size
[07:48:37] [PASSED] Extra pages requested
[07:48:37] ================ [PASSED] ttm_tt_init_basic ================
[07:48:37] [PASSED] ttm_tt_init_misaligned
[07:48:37] [PASSED] ttm_tt_fini_basic
[07:48:37] [PASSED] ttm_tt_fini_sg
[07:48:37] [PASSED] ttm_tt_fini_shmem
[07:48:37] [PASSED] ttm_tt_create_basic
[07:48:37] [PASSED] ttm_tt_create_invalid_bo_type
[07:48:37] [PASSED] ttm_tt_create_ttm_exists
[07:48:37] [PASSED] ttm_tt_create_failed
[07:48:37] [PASSED] ttm_tt_destroy_basic
[07:48:37] [PASSED] ttm_tt_populate_null_ttm
[07:48:37] [PASSED] ttm_tt_populate_populated_ttm
[07:48:37] [PASSED] ttm_tt_unpopulate_basic
[07:48:37] [PASSED] ttm_tt_unpopulate_empty_ttm
[07:48:37] [PASSED] ttm_tt_swapin_basic
[07:48:37] ===================== [PASSED] ttm_tt ======================
[07:48:37] =================== ttm_bo (14 subtests) ===================
[07:48:37] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[07:48:37] [PASSED] Cannot be interrupted and sleeps
[07:48:37] [PASSED] Cannot be interrupted, locks straight away
[07:48:37] [PASSED] Can be interrupted, sleeps
[07:48:37] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[07:48:37] [PASSED] ttm_bo_reserve_locked_no_sleep
[07:48:37] [PASSED] ttm_bo_reserve_no_wait_ticket
[07:48:37] [PASSED] ttm_bo_reserve_double_resv
[07:48:37] [PASSED] ttm_bo_reserve_interrupted
[07:48:37] [PASSED] ttm_bo_reserve_deadlock
[07:48:37] [PASSED] ttm_bo_unreserve_basic
[07:48:37] [PASSED] ttm_bo_unreserve_pinned
[07:48:37] [PASSED] ttm_bo_unreserve_bulk
[07:48:37] [PASSED] ttm_bo_fini_basic
[07:48:37] [PASSED] ttm_bo_fini_shared_resv
[07:48:37] [PASSED] ttm_bo_pin_basic
[07:48:37] [PASSED] ttm_bo_pin_unpin_resource
[07:48:37] [PASSED] ttm_bo_multiple_pin_one_unpin
[07:48:37] ===================== [PASSED] ttm_bo ======================
[07:48:37] ============== ttm_bo_validate (21 subtests) ===============
[07:48:37] ============== ttm_bo_init_reserved_sys_man  ===============
[07:48:37] [PASSED] Buffer object for userspace
[07:48:37] [PASSED] Kernel buffer object
[07:48:37] [PASSED] Shared buffer object
[07:48:37] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[07:48:37] ============== ttm_bo_init_reserved_mock_man  ==============
[07:48:37] [PASSED] Buffer object for userspace
[07:48:37] [PASSED] Kernel buffer object
[07:48:37] [PASSED] Shared buffer object
[07:48:37] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[07:48:37] [PASSED] ttm_bo_init_reserved_resv
[07:48:37] ================== ttm_bo_validate_basic  ==================
[07:48:37] [PASSED] Buffer object for userspace
[07:48:37] [PASSED] Kernel buffer object
[07:48:37] [PASSED] Shared buffer object
[07:48:37] ============== [PASSED] ttm_bo_validate_basic ==============
[07:48:37] [PASSED] ttm_bo_validate_invalid_placement
[07:48:37] ============= ttm_bo_validate_same_placement  ==============
[07:48:37] [PASSED] System manager
[07:48:37] [PASSED] VRAM manager
[07:48:37] ========= [PASSED] ttm_bo_validate_same_placement ==========
[07:48:37] [PASSED] ttm_bo_validate_failed_alloc
[07:48:37] [PASSED] ttm_bo_validate_pinned
[07:48:37] [PASSED] ttm_bo_validate_busy_placement
[07:48:37] ================ ttm_bo_validate_multihop  =================
[07:48:37] [PASSED] Buffer object for userspace
[07:48:37] [PASSED] Kernel buffer object
[07:48:37] [PASSED] Shared buffer object
[07:48:37] ============ [PASSED] ttm_bo_validate_multihop =============
[07:48:37] ========== ttm_bo_validate_no_placement_signaled  ==========
[07:48:37] [PASSED] Buffer object in system domain, no page vector
[07:48:37] [PASSED] Buffer object in system domain with an existing page vector
[07:48:37] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[07:48:37] ======== ttm_bo_validate_no_placement_not_signaled  ========
[07:48:37] [PASSED] Buffer object for userspace
[07:48:37] [PASSED] Kernel buffer object
[07:48:37] [PASSED] Shared buffer object
[07:48:37] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[07:48:37] [PASSED] ttm_bo_validate_move_fence_signaled
[07:48:37] ========= ttm_bo_validate_move_fence_not_signaled  =========
[07:48:37] [PASSED] Waits for GPU
[07:48:37] [PASSED] Tries to lock straight away
[07:48:37] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[07:48:37] [PASSED] ttm_bo_validate_happy_evict
[07:48:37] [PASSED] ttm_bo_validate_all_pinned_evict
[07:48:37] [PASSED] ttm_bo_validate_allowed_only_evict
[07:48:37] [PASSED] ttm_bo_validate_deleted_evict
[07:48:37] [PASSED] ttm_bo_validate_busy_domain_evict
[07:48:37] [PASSED] ttm_bo_validate_evict_gutting
[07:48:37] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[07:48:37] ================= [PASSED] ttm_bo_validate =================
[07:48:37] ============================================================
[07:48:37] Testing complete. Ran 101 tests: passed: 101
[07:48:37] Elapsed time: 11.231s total, 1.630s configuring, 9.334s building, 0.220s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH 00/22] drm/i915/vrr: A few fixes and a bunch of cleanup

[Jani Nikula]

On Mon, 20 Oct 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> With all the recent work on the VRR code we've accumulated quite
> a few slightly rough corners. Try to clean things up a bit.
>
> While testing the cleanups I noticed a few real issues, fixes
> for which are included at the start of the series.

I quickly eyeballed through this, looks good, but would Ankit be up for
detailed review considering the recent contributions in the area?

BR,
Jani.


>
> Ville Syrjälä (22):
>   drm/i915/vrr: Fix intel_vrr_always_use_vrr_tg()==true on TGL
>   drm/i915/lrr: Include SCL in lrr_params_changed()
>   drm/i915: Remove the "vblank delay" state dump
>   drm/i915/vrr: Compute fixed refresh rate timings the sam way as CMRR
>     timings
>   drm/i915/vrr: Reorganize intel_vrr_compute_cmrr_timings() a bit
>   drm/i195/vrr: Move crtc_state->vrr.{vmin,vmax} update into
>     intel_vrr_compute_vrr_timings()
>   drm/i915/vrr: Move compute_fixed_rr_timings()
>   drm/i915/vrr: Extract intel_vrr_set_vrr_timings()
>   drm/i915/vrr: Avoid redundant TRANS_PUSH write in intel_vrr_enable()
>   drm/i915/vrr: Move EMP_AS_SDP_TL write into
>     intel_vrr_set_transcoder_timings()
>   drm/i915/vrr: Use trans_vrr_ctl() in intel_vrr_transcoder_disable()
>   drm/i915/vrr: Extract intel_vrr_tg_disable()
>   drm/i915/vrr: Extract intel_vrr_tg_enable()
>   drm/i915/vrr: Disable VRR TG in intel_vrr_transcoder_disable() only on
>     always use_vrr_tg() platforms
>   drm/i915/vrr: Always write TRANS_VRR_CTL in
>     intel_vrr_set_transcoder_timings() on !always_use_vrr_tg()
>   drm/i915/vrr: Remove redundant HAS_VRR() checks
>   drm/i915/vrr: Move HAS_VRR() check into
>     intel_vrr_set_transcoder_timings()
>   drm/i915/vrr: s/crtc_state/old_crtc_state/ in
>     intel_vrr_transcoder_disable()
>   drm/i915/vrr: Nuke intel_vrr_vblank_exit_length()
>   drm/i915/vrr: Nuke intel_vrr_vmin_flipline()
>   drm/i915/vrr: Update the intel_vrr_extra_vblank_delay() comment
>   drm/i915/vrr: Check HAS_VRR() first in intel_vrr_is_capable()
>
>  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |  22 +-
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 212 ++++++++----------
>  3 files changed, 113 insertions(+), 125 deletions(-)

-- 
Jani Nikula, Intel

✓ Xe.CI.BAT: success for drm/i915/vrr: A few fixes and a bunch of cleanup

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1475 bytes --]

== Series Details ==

Series: drm/i915/vrr: A few fixes and a bunch of cleanup
URL   : https://patchwork.freedesktop.org/series/156222/
State : success

== Summary ==

CI Bug Log - changes from xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a_BAT -> xe-pw-156222v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-156222v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-plain-flip@c-edp1:
    - bat-adlp-7:         [PASS][1] -> [DMESG-WARN][2] ([Intel XE#4543]) +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/bat-adlp-7/igt@kms_flip@basic-plain-flip@c-edp1.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543


Build changes
-------------

  * Linux: xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a -> xe-pw-156222v1

  IGT_8594: 8594
  xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a: aae2e4df375e567f00c8d494004cf6a34a73d75a
  xe-pw-156222v1: 156222v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/index.html

[-- Attachment #2: Type: text/html, Size: 2040 bytes --]

✗ Xe.CI.Full: failure for drm/i915/vrr: A few fixes and a bunch of cleanup

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 45057 bytes --]

== Series Details ==

Series: drm/i915/vrr: A few fixes and a bunch of cleanup
URL   : https://patchwork.freedesktop.org/series/156222/
State : failure

== Summary ==

CI Bug Log - changes from xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a_FULL -> xe-pw-156222v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-156222v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-156222v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-156222v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-432/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-6.html

  
#### Warnings ####

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-dg2-set2:     [INCOMPLETE][2] ([Intel XE#4842]) -> [INCOMPLETE][3]
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-dg2-432/igt@kms_hdr@bpc-switch-suspend.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-432/igt@kms_hdr@bpc-switch-suspend.html

  
Known issues
------------

  Here are the changes found in xe-pw-156222v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
    - shard-lnl:          [PASS][4] -> [FAIL][5] ([Intel XE#6054]) +1 other test fail
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-adlp:         NOTRUN -> [SKIP][6] ([Intel XE#1124])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2327])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_big_fb@linear-8bpp-rotate-90.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#316])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][9] ([Intel XE#4543])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#1124]) +1 other test skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-adlp:         NOTRUN -> [SKIP][11] ([Intel XE#367])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][12] ([Intel XE#2907])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][13] ([Intel XE#787]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][14] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#787]) +13 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [PASS][17] -> [INCOMPLETE][18] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) +1 other test incomplete
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2325])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2252]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#373])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-adlp:         NOTRUN -> [SKIP][23] ([Intel XE#373]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_content_protection@atomic:
    - shard-adlp:         NOTRUN -> [SKIP][24] ([Intel XE#455]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][25] ([Intel XE#1178])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2321])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-adlp:         [PASS][27] -> [DMESG-WARN][28] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#4422])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#4422])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-adlp:         NOTRUN -> [SKIP][31] ([Intel XE#310])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_flip@2x-flip-vs-dpms.html
    - shard-bmg:          [PASS][32] -> [SKIP][33] ([Intel XE#2316]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-4/igt@kms_flip@2x-flip-vs-dpms.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [PASS][34] -> [DMESG-WARN][35] ([Intel XE#4543] / [Intel XE#5208])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-3/igt@kms_flip@flip-vs-rmfb.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-2/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_flip@flip-vs-suspend@c-dp4:
    - shard-dg2-set2:     [PASS][36] -> [INCOMPLETE][37] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-dg2-463/igt@kms_flip@flip-vs-suspend@c-dp4.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-463/igt@kms_flip@flip-vs-suspend@c-dp4.html

  * igt@kms_flip@plain-flip-interruptible@b-hdmi-a1:
    - shard-adlp:         [PASS][38] -> [DMESG-WARN][39] ([Intel XE#4543]) +4 other tests dmesg-warn
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-4/igt@kms_flip@plain-flip-interruptible@b-hdmi-a1.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-3/igt@kms_flip@plain-flip-interruptible@b-hdmi-a1.html

  * igt@kms_flip_tiling@flip-change-tiling:
    - shard-adlp:         [PASS][40] -> [DMESG-FAIL][41] ([Intel XE#4543]) +1 other test dmesg-fail
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y:
    - shard-adlp:         [PASS][42] -> [FAIL][43] ([Intel XE#1874])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#651]) +4 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-adlp:         NOTRUN -> [SKIP][45] ([Intel XE#656]) +4 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#6313])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#5390]) +4 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#2311]) +4 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-adlp:         NOTRUN -> [SKIP][49] ([Intel XE#1151])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
    - shard-adlp:         NOTRUN -> [SKIP][50] ([Intel XE#653]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2313]) +4 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#653]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][53] ([Intel XE#2927])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-adlp:         NOTRUN -> [SKIP][54] ([Intel XE#1122])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#3309])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#1406] / [Intel XE#1489])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][58] ([Intel XE#1406] / [Intel XE#1489])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr@fbc-pr-basic:
    - shard-adlp:         NOTRUN -> [SKIP][59] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_psr@fbc-pr-basic.html

  * igt@kms_psr@fbc-psr2-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_psr@fbc-psr2-suspend.html

  * igt@kms_psr@psr2-sprite-plane-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][61] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@kms_psr@psr2-sprite-plane-move.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#3414] / [Intel XE#3904])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_rotation_crc@primary-rotation-90.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][63] ([Intel XE#3414])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-adlp:         NOTRUN -> [SKIP][64] ([Intel XE#3414])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][65] -> [FAIL][66] ([Intel XE#4459]) +1 other test fail
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-lnl-2/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_copy_basic@mem-page-copy-1:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#5300])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@xe_copy_basic@mem-page-copy-1.html

  * igt@xe_eudebug@basic-exec-queues:
    - shard-adlp:         NOTRUN -> [SKIP][68] ([Intel XE#4837] / [Intel XE#5565]) +2 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_eudebug@basic-exec-queues.html

  * igt@xe_eudebug@basic-vm-bind-ufence:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#4837]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@xe_eudebug@basic-vm-bind-ufence.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#4837]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@xe_eudebug@basic-vm-bind-ufence.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][71] -> [INCOMPLETE][72] ([Intel XE#6321])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-8/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-1/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-beng-mixed-threads-large:
    - shard-adlp:         NOTRUN -> [SKIP][73] ([Intel XE#261]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_evict@evict-beng-mixed-threads-large.html

  * igt@xe_exec_basic@multigpu-no-exec-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#2322])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@xe_exec_basic@multigpu-no-exec-null-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-rebind:
    - shard-adlp:         NOTRUN -> [SKIP][75] ([Intel XE#1392] / [Intel XE#5575]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_exec_basic@multigpu-no-exec-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#288]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-prefetch.html

  * igt@xe_exec_fault_mode@many-execqueues-userptr-prefetch:
    - shard-adlp:         NOTRUN -> [SKIP][77] ([Intel XE#288] / [Intel XE#5561]) +2 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_exec_fault_mode@many-execqueues-userptr-prefetch.html

  * igt@xe_exec_system_allocator@many-64k-mmap-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#5007])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@xe_exec_system_allocator@many-64k-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          [PASS][79] -> [FAIL][80] ([Intel XE#5625])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_exec_system_allocator@process-many-execqueues-free-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][81] ([Intel XE#4915]) +41 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@xe_exec_system_allocator@process-many-execqueues-free-race.html

  * igt@xe_exec_system_allocator@processes-evict-malloc:
    - shard-adlp:         NOTRUN -> [SKIP][82] ([Intel XE#4915]) +38 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_exec_system_allocator@processes-evict-malloc.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#4943]) +3 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-new-huge.html

  * igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit:
    - shard-dg2-set2:     NOTRUN -> [FAIL][84] ([Intel XE#3099]) +2 other tests fail
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html

  * igt@xe_module_load@force-load:
    - shard-adlp:         NOTRUN -> [SKIP][85] ([Intel XE#378] / [Intel XE#5612])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_module_load@force-load.html

  * igt@xe_oa@invalid-oa-exponent:
    - shard-adlp:         NOTRUN -> [SKIP][86] ([Intel XE#3573]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_oa@invalid-oa-exponent.html

  * igt@xe_oa@unprivileged-single-ctx-counters:
    - shard-dg2-set2:     NOTRUN -> [SKIP][87] ([Intel XE#3573])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@xe_oa@unprivileged-single-ctx-counters.html

  * igt@xe_pm@d3hot-i2c:
    - shard-dg2-set2:     NOTRUN -> [SKIP][88] ([Intel XE#5742])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@xe_pm@d3hot-i2c.html
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#5742])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@xe_pm@d3hot-i2c.html

  * igt@xe_query@multigpu-query-cs-cycles:
    - shard-adlp:         NOTRUN -> [SKIP][90] ([Intel XE#944])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_query@multigpu-query-cs-cycles.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#944])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@xe_query@multigpu-query-hwconfig.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][92] ([Intel XE#944])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_sriov_auto_provisioning@selfconfig-basic:
    - shard-bmg:          NOTRUN -> [FAIL][93] ([Intel XE#5937]) +1 other test fail
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@xe_sriov_auto_provisioning@selfconfig-basic.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][94] ([Intel XE#4130])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-466/igt@xe_sriov_auto_provisioning@selfconfig-basic.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-d-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][95] ([Intel XE#4912]) -> [PASS][96] +1 other test pass
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-dg2-466/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-dp-4.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-432/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-dp-4.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-bmg:          [SKIP][97] ([Intel XE#2291]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-adlp:         [DMESG-WARN][99] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-bmg:          [SKIP][101] ([Intel XE#2316]) -> [PASS][102] +1 other test pass
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-6/igt@kms_flip@2x-absolute-wf_vblank.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][103] ([Intel XE#4543]) -> [PASS][104] +9 other tests pass
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-6/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-2/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [INCOMPLETE][105] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][106] +1 other test pass
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [SKIP][107] ([Intel XE#4596]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@xe_exec_balancer@once-parallel-userptr-invalidate:
    - shard-adlp:         [DMESG-FAIL][109] ([Intel XE#3876]) -> [PASS][110] +2 other tests pass
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-1/igt@xe_exec_balancer@once-parallel-userptr-invalidate.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_exec_balancer@once-parallel-userptr-invalidate.html

  * igt@xe_exec_basic@many-null-defer-bind:
    - shard-adlp:         [DMESG-WARN][111] ([Intel XE#3876]) -> [PASS][112]
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-1/igt@xe_exec_basic@many-null-defer-bind.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_exec_basic@many-null-defer-bind.html

  * igt@xe_exec_reset@cm-gt-reset:
    - shard-adlp:         [FAIL][113] ([Intel XE#6325]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-1/igt@xe_exec_reset@cm-gt-reset.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_exec_reset@cm-gt-reset.html

  * igt@xe_exec_threads@threads-cm-rebind:
    - shard-adlp:         [FAIL][115] ([Intel XE#5625]) -> [PASS][116] +2 other tests pass
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-1/igt@xe_exec_threads@threads-cm-rebind.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_exec_threads@threads-cm-rebind.html

  * igt@xe_gt_freq@freq_fixed_idle:
    - shard-dg2-set2:     [FAIL][117] ([Intel XE#6407]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-dg2-436/igt@xe_gt_freq@freq_fixed_idle.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-434/igt@xe_gt_freq@freq_fixed_idle.html

  * igt@xe_pm@s2idle-exec-after:
    - shard-adlp:         [TIMEOUT][119] ([Intel XE#3876]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-1/igt@xe_pm@s2idle-exec-after.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_pm@s2idle-exec-after.html

  * igt@xe_pm_residency@gt-c6-freeze@gt0:
    - shard-adlp:         [DMESG-FAIL][121] ([Intel XE#5545]) -> [PASS][122] +1 other test pass
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-1/igt@xe_pm_residency@gt-c6-freeze@gt0.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_pm_residency@gt-c6-freeze@gt0.html

  * igt@xe_vm@munmap-style-unbind-userptr-inval-front:
    - shard-adlp:         [INCOMPLETE][123] -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-1/igt@xe_vm@munmap-style-unbind-userptr-inval-front.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@xe_vm@munmap-style-unbind-userptr-inval-front.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-adlp:         [DMESG-WARN][125] ([Intel XE#4543]) -> [DMESG-WARN][126] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-2/igt@kms_async_flips@async-flip-suspend-resume.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-4/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1:
    - shard-adlp:         [DMESG-WARN][127] ([Intel XE#4543]) -> [DMESG-WARN][128] ([Intel XE#2953] / [Intel XE#4173])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-2/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-4/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-hdmi-a-1.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-adlp:         [DMESG-FAIL][129] ([Intel XE#4543]) -> [DMESG-FAIL][130] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [FAIL][131] ([Intel XE#1178]) -> [SKIP][132] ([Intel XE#2341])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-4/igt@kms_content_protection@atomic.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-6/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [SKIP][133] ([Intel XE#2341]) -> [FAIL][134] ([Intel XE#1178])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-6/igt@kms_content_protection@srm.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_content_protection@srm.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][135] ([Intel XE#2311]) -> [SKIP][136] ([Intel XE#2312]) +2 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][137] ([Intel XE#2312]) -> [SKIP][138] ([Intel XE#5390])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][139] ([Intel XE#5390]) -> [SKIP][140] ([Intel XE#2312]) +1 other test skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][141] ([Intel XE#2312]) -> [SKIP][142] ([Intel XE#2311]) +3 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][143] ([Intel XE#2312]) -> [SKIP][144] ([Intel XE#2313]) +2 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][145] ([Intel XE#2313]) -> [SKIP][146] ([Intel XE#2312]) +3 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][147] ([Intel XE#1500]) -> [SKIP][148] ([Intel XE#362])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_eudebug_sriov@deny-sriov:
    - shard-adlp:         [SKIP][149] ([Intel XE#4519]) -> [SKIP][150] ([Intel XE#6386])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-4/igt@xe_eudebug_sriov@deny-sriov.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-3/igt@xe_eudebug_sriov@deny-sriov.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-bmg:          [ABORT][151] ([Intel XE#5466] / [Intel XE#5530]) -> [ABORT][152] ([Intel XE#4917] / [Intel XE#5466] / [Intel XE#5530])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-bmg-6/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-bmg-6/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_sriov_scheduling@equal-throughput:
    - shard-adlp:         [DMESG-FAIL][153] ([Intel XE#3868] / [Intel XE#5213]) -> [DMESG-FAIL][154] ([Intel XE#3868] / [Intel XE#5213] / [Intel XE#5545]) +1 other test dmesg-fail
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a/shard-adlp-4/igt@xe_sriov_scheduling@equal-throughput.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/shard-adlp-3/igt@xe_sriov_scheduling@equal-throughput.html

  
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1151
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3099]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3099
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4519
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842
  [Intel XE#4912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4912
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6313
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6325
  [Intel XE#6386]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6386
  [Intel XE#6407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6407
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a -> xe-pw-156222v1

  IGT_8594: 8594
  xe-3951-aae2e4df375e567f00c8d494004cf6a34a73d75a: aae2e4df375e567f00c8d494004cf6a34a73d75a
  xe-pw-156222v1: 156222v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-156222v1/index.html

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Re: [PATCH 01/22] drm/i915/vrr: Fix intel_vrr_always_use_vrr_tg()==true on TGL

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On TGL the hardware always needs TRANS_VBLANK.VBLANK_START
> to be programemd with VACTIVE+SCL. Make it so.
>
> The current way of programming it with crtc_vblank_start only
> works for the legacy timing generator, as there the delayed
> vblank does happen exactly at VACTIVE+SCL.
>
> But if one tries to change intel_vrr_always_use_vrr_tg() to
> always use the VRR timing generator on TGL, crtc_vblank_start
> will point to the VRR timing generator's delayed vblank,
> which may not match VACTIVE+SCL.
>
> Fortunately the state checker caught the issue right away
> when I tried intel_vrr_always_use_vrr_tg()==true on TGL.

Hmm. TGL doesn't have SCL register, and still needs Vblank.start.
So irrespective of VRR TG or Legacy TG it needs this value.
Readout for vblank.start temporarily sets 
adjusted_mode->crtc_vblank_start to  vactive + SCL,
we use it for deriving crtc_state->set_context_latency and then 
adjusted_mode->crtc_vblank_start gets overwritten to point to delayed 
vblank, and everything falls in place.

LGTM

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a8b4619de347..09d3eb422ad4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2631,6 +2631,9 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>   		 * to make it stand out in register dumps.
>   		 */
>   		crtc_vblank_start = 1;
> +	} else if (DISPLAY_VER(display) == 12) {
> +		/* VBLANK_START - VACTIVE defines SCL on TGL */
> +		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
>   	}
>   
>   	if (DISPLAY_VER(display) >= 4)
> @@ -2721,6 +2724,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>   		 * to make it stand out in register dumps.
>   		 */
>   		crtc_vblank_start = 1;
> +	} else if (DISPLAY_VER(display) == 12) {
> +		/* VBLANK_START - VACTIVE defines SCL on TGL */
> +		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
>   	}
>   
>   	/*

Re: [PATCH 02/22] drm/i915/lrr: Include SCL in lrr_params_changed()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> If SCL is changing we need to take the LRR codepath to update
> it during a fastset. Account for that in lrr_params_changed().
>
> The current code will only notice the SCL change if the position
> of the delayed vblank also changes. But that might not happen
> when using the VRR timing generator because the delayed vblank
> is then defined by the guardband instead of the SCL.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++++-----
>   1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 09d3eb422ad4..490b4f2907e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5711,12 +5711,16 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
>   	return 0;
>   }
>   
> -static bool lrr_params_changed(const struct drm_display_mode *old_adjusted_mode,
> -			       const struct drm_display_mode *new_adjusted_mode)
> +static bool lrr_params_changed(const struct intel_crtc_state *old_crtc_state,
> +			       const struct intel_crtc_state *new_crtc_state)
>   {
> +	const struct drm_display_mode *old_adjusted_mode = &old_crtc_state->hw.adjusted_mode;
> +	const struct drm_display_mode *new_adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> +
>   	return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start ||
>   		old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||
> -		old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal;
> +		old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal ||
> +		old_crtc_state->set_context_latency != new_crtc_state->set_context_latency;
>   }
>   
>   static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
> @@ -5742,8 +5746,7 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
>   				   &new_crtc_state->dp_m_n))
>   		new_crtc_state->update_m_n = false;
>   
> -	if (!lrr_params_changed(&old_crtc_state->hw.adjusted_mode,
> -				&new_crtc_state->hw.adjusted_mode))
> +	if (!lrr_params_changed(old_crtc_state, new_crtc_state))
>   		new_crtc_state->update_lrr = false;
>   
>   	if (intel_crtc_needs_modeset(new_crtc_state))

Re: [PATCH 03/22] drm/i915: Remove the "vblank delay" state dump

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The "vblank delay" we are including in the crtc state dump is
> meaningful only when running with fixed refresh rate timings.
> With VRR timings one has to look at the VRR state to figure out
> the same thing.
>
> Since we already dump the position of the delayed vblank for
> both fixed refresh rate and VRR timings, this "vblank delay"
> thing seems pretty much pointless now. Get rid of it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 23e25e97d060..e6f300dbb5ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -289,9 +289,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>   	drm_printf(&p, "scanline offset: %d\n",
>   		   intel_crtc_scanline_offset(pipe_config));
>   
> -	drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d set context latency: %d\n",
> -		   pipe_config->hw.adjusted_mode.crtc_vblank_start -
> -		   pipe_config->hw.adjusted_mode.crtc_vdisplay,
> +	drm_printf(&p, "framestart delay: %d, MSA timing delay: %d, set context latency: %d\n",
>   		   pipe_config->framestart_delay, pipe_config->msa_timing_delay,
>   		   pipe_config->set_context_latency);
>   

Re: [PATCH 04/22] drm/i915/vrr: Compute fixed refresh rate timings the sam way as CMRR timings

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Unify the VRR timing computation stuff a bit having both the
> fixed refrehs rate and CMRR cases assign the crtc_state->vrr

Nitpick: typo refresh.

Otherwise LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> stuff in exactly the same way.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 8 +++-----
>   1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 92fb72b56f16..510dc199376f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -305,12 +305,10 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
>   static
>   void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
>   {
> -	/*
> -	 * For fixed rr,  vmin = vmax = flipline.
> -	 * vmin is already set to crtc_vtotal set vmax and flipline the same.
> -	 */
> +	/* For fixed rr,  vmin = vmax = flipline */
>   	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
> -	crtc_state->vrr.flipline = crtc_state->hw.adjusted_mode.crtc_vtotal;
> +	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> +	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
>   }
>   
>   static

Re: [PATCH 05/22] drm/i915/vrr: Reorganize intel_vrr_compute_cmrr_timings() a bit

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the cmrr.enable assignment next to the mode_flags assignment
> to keep things in a bit more logical order in
> intel_vrr_compute_cmrr_timings().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 510dc199376f..01cb9cfe08e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -220,7 +220,6 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
>   static
>   void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
>   {
> -	crtc_state->cmrr.enable = true;
>   	/*
>   	 * TODO: Compute precise target refresh rate to determine
>   	 * if video_mode_required should be true. Currently set to
> @@ -230,6 +229,8 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
>   	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
>   	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
>   	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> +
> +	crtc_state->cmrr.enable = true;
>   	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   }
>   

Re: [PATCH 06/22] drm/i195/vrr: Move crtc_state->vrr.{vmin, vmax} update into intel_vrr_compute_vrr_timings()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The way intel_vrr_compute_*_timings() works is rather confusing.
> First intel_vrr_compute_config() assigns the computed vmin/vmax
> into crtc_state->vrr.{vmin,vmax}, and then either
> intel_vrr_compute_vrr_timings() leaves them untouched or
> intel_vrr_compute_{cmrr,fixed_rr}_timings() overwrite them with
> something else.
>
> Clean this up by moving all crtc_state->vrr.{vmin,vmax} assignments
> into intel_vrr_compute_*_timings().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 01cb9cfe08e1..9179ad53a2e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -235,8 +235,13 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
>   }
>   
>   static
> -void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
> +void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state,
> +				   int vmin, int vmax)
>   {
> +	crtc_state->vrr.vmax = vmax;
> +	crtc_state->vrr.vmin = vmin;
> +	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> +
>   	crtc_state->vrr.enable = true;
>   	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   }
> @@ -381,13 +386,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   		vmax = vmin;
>   	}
>   
> -	crtc_state->vrr.vmin = vmin;
> -	crtc_state->vrr.vmax = vmax;
> -
> -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> -
>   	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
> -		intel_vrr_compute_vrr_timings(crtc_state);
> +		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
>   	else if (is_cmrr_frac_required(crtc_state) && is_edp)
>   		intel_vrr_compute_cmrr_timings(crtc_state);
>   	else

Re: [PATCH 07/22] drm/i915/vrr: Move compute_fixed_rr_timings()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Relocate intel_vrr_compute_fixed_rr_timings() next to its
> VRR and CMRR counterparts.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 9179ad53a2e7..99e10943368d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -246,6 +246,15 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state,
>   	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   }
>   
> +static
> +void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
> +{
> +	/* For fixed rr,  vmin = vmax = flipline */
> +	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
> +	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> +	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> +}
> +
>   static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
>   			      int value)
>   {
> @@ -308,15 +317,6 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
>   		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
>   }
>   
> -static
> -void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
> -{
> -	/* For fixed rr,  vmin = vmax = flipline */
> -	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
> -	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
> -	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
> -}
> -
>   static
>   int intel_vrr_compute_vmin(struct intel_crtc_state *crtc_state)
>   {

Re: [PATCH 08/22] drm/i915/vrr: Extract intel_vrr_set_vrr_timings()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract intel_vrr_set_vrr_timings() as the counterpart to
> intel_vrr_set_fixed_rr_timings().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 16 ++++++++++++----
>   1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 99e10943368d..b2f139addc8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -686,20 +686,28 @@ static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state)
>   	return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline);
>   }
>   
> -void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> +static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>   
> -	if (!crtc_state->vrr.enable)
> -		return;
> -
>   	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
>   		       intel_vrr_hw_vmin(crtc_state) - 1);
>   	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
>   		       intel_vrr_hw_vmax(crtc_state) - 1);
>   	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
>   		       intel_vrr_hw_flipline(crtc_state) - 1);
> +}
> +
> +void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if (!crtc_state->vrr.enable)
> +		return;
> +
> +	intel_vrr_set_vrr_timings(crtc_state);
>   
>   	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
>   		       TRANS_PUSH_EN);

Re: [PATCH 09/22] drm/i915/vrr: Avoid redundant TRANS_PUSH write in intel_vrr_enable()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We keep TRANS_PUSH_EN always set for always_use_vrr_tg() platfforms,
> so there is no need to write it again in  intel_vrr_enable().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b2f139addc8b..6e8f8e673312 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -709,12 +709,12 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   
>   	intel_vrr_set_vrr_timings(crtc_state);
>   
> -	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> -		       TRANS_PUSH_EN);
> -
>   	if (!intel_vrr_always_use_vrr_tg(display)) {
>   		intel_vrr_set_db_point_and_transmission_line(crtc_state);
>   
> +		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> +			       TRANS_PUSH_EN);
> +
>   		if (crtc_state->cmrr.enable) {
>   			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
>   				       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |

Re: [PATCH 10/22] drm/i915/vrr: Move EMP_AS_SDP_TL write into intel_vrr_set_transcoder_timings()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> EMP_AS_SDL_TL replaces the TRANS_VRR_VSUNC for the purposes of

Nitpick: typo TRANS_VRR_VSYNC.


> setting the AS SDP transmission line. Move the EMP_AS_SDL_TL into
> intel_vrr_set_transcoder_timings() since that's where we write
> TRANS_VRR_VSYNC as well.


Not related to this change, but perhaps at some point we might need to 
come with a policy if there are more SDPs that have configurable 
Transmission lines and DB point.

We have VS_SDP_TL for PTL (we do not use VS_SDP currently), and some 
more for NVL.

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 35 ++++++++----------------
>   1 file changed, 12 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 6e8f8e673312..562a5feadaab 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -571,6 +571,18 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   			       TRANS_VRR_VSYNC(display, cpu_transcoder),
>   			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
>   			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
> +
> +	/*
> +	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> +	 * double buffering point and transmission line for VRR packets for
> +	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> +	 * Since currently we support VRR only for DP/eDP, so this is programmed
> +	 * to for Adaptive Sync SDP to Vsync start.
> +	 */
> +	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> +		intel_de_write(display,
> +			       EMP_AS_SDP_TL(display, cpu_transcoder),
> +			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>   }
>   
>   void intel_vrr_send_push(struct intel_dsb *dsb,
> @@ -649,25 +661,6 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
>   	return false;
>   }
>   
> -static
> -void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_display *display = to_intel_display(crtc_state);
> -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -
> -	/*
> -	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> -	 * double buffering point and transmission line for VRR packets for
> -	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> -	 * Since currently we support VRR only for DP/eDP, so this is programmed
> -	 * to for Adaptive Sync SDP to Vsync start.
> -	 */
> -	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> -		intel_de_write(display,
> -			       EMP_AS_SDP_TL(display, cpu_transcoder),
> -			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> -}
> -
>   static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> @@ -710,8 +703,6 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   	intel_vrr_set_vrr_timings(crtc_state);
>   
>   	if (!intel_vrr_always_use_vrr_tg(display)) {
> -		intel_vrr_set_db_point_and_transmission_line(crtc_state);
> -
>   		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
>   			       TRANS_PUSH_EN);
>   
> @@ -773,8 +764,6 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
>   	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
>   		       TRANS_PUSH_EN);
>   
> -	intel_vrr_set_db_point_and_transmission_line(crtc_state);
> -
>   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
>   		       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
>   }

Re: [PATCH 11/22] drm/i915/vrr: Use trans_vrr_ctl() in intel_vrr_transcoder_disable()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently intel_vrr_disable() writes TRANS_VRR_CTL() with
> trans_vrr_ctl(), whereas intel_vrr_transcoder_disable() always
> writes just a plain 0. Write trans_vrr_ctl() in both places to
> unify the code, allowing for more shared code in the future.
>
> Since the VRR timing generator will be disabled by the
> TRANS_VRR_CTL write it doesn't really matter what we write to
> the register (other than VRR_CTL_VRR_ENABLE that is).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 562a5feadaab..19b38ad77189 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -779,7 +779,8 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
>   	if (!intel_vrr_possible(crtc_state))
>   		return;
>   
> -	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 0);
> +	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> +		       trans_vrr_ctl(crtc_state));
>   
>   	intel_vrr_wait_for_live_status_clear(display, cpu_transcoder);
>   

Re: [PATCH 12/22] drm/i915/vrr: Extract intel_vrr_tg_disable()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we always disable the VRR timing generator the same way
> we can extract the duplicated code into a helper.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 42 +++++++++++-------------
>   1 file changed, 19 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 19b38ad77189..3ed6a56fb779 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -692,6 +692,22 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
>   		       intel_vrr_hw_flipline(crtc_state) - 1);
>   }
>   
> +static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(old_crtc_state);
> +	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> +
> +	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> +		       trans_vrr_ctl(old_crtc_state));
> +
> +	if (intel_de_wait_for_clear(display,
> +				    TRANS_VRR_STATUS(display, cpu_transcoder),
> +				    VRR_STATUS_VRR_EN_LIVE, 1000))
> +		drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
> +
> +	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
> +}
> +
>   void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> @@ -717,29 +733,15 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   	}
>   }
>   
> -static void intel_vrr_wait_for_live_status_clear(struct intel_display *display,
> -						 enum transcoder cpu_transcoder)
> -{
> -	if (intel_de_wait_for_clear(display,
> -				    TRANS_VRR_STATUS(display, cpu_transcoder),
> -				    VRR_STATUS_VRR_EN_LIVE, 1000))
> -		drm_err(display->drm, "Timed out waiting for VRR live status to clear\n");
> -}
> -
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(old_crtc_state);
> -	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>   
>   	if (!old_crtc_state->vrr.enable)
>   		return;
>   
> -	if (!intel_vrr_always_use_vrr_tg(display)) {
> -		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> -			       trans_vrr_ctl(old_crtc_state));
> -		intel_vrr_wait_for_live_status_clear(display, cpu_transcoder);
> -		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
> -	}
> +	if (!intel_vrr_always_use_vrr_tg(display))
> +		intel_vrr_tg_disable(old_crtc_state);
>   
>   	intel_vrr_set_fixed_rr_timings(old_crtc_state);
>   }
> @@ -771,7 +773,6 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
>   void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>   
>   	if (!HAS_VRR(display))
>   		return;
> @@ -779,12 +780,7 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
>   	if (!intel_vrr_possible(crtc_state))
>   		return;
>   
> -	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> -		       trans_vrr_ctl(crtc_state));
> -
> -	intel_vrr_wait_for_live_status_clear(display, cpu_transcoder);
> -
> -	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
> +	intel_vrr_tg_disable(crtc_state);
>   }
>   
>   bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)

Re: [PATCH 10/22] drm/i915/vrr: Move EMP_AS_SDP_TL write into intel_vrr_set_transcoder_timings()

[Ville Syrjälä]

On Fri, Oct 24, 2025 at 07:09:19PM +0530, Nautiyal, Ankit K wrote:
> 
> On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > EMP_AS_SDL_TL replaces the TRANS_VRR_VSUNC for the purposes of
> 
> Nitpick: typo TRANS_VRR_VSYNC.
> 
> 
> > setting the AS SDP transmission line. Move the EMP_AS_SDL_TL into
> > intel_vrr_set_transcoder_timings() since that's where we write
> > TRANS_VRR_VSYNC as well.
> 
> 
> Not related to this change, but perhaps at some point we might need to 
> come with a policy if there are more SDPs that have configurable 
> Transmission lines and DB point.
> 
> We have VS_SDP_TL for PTL (we do not use VS_SDP currently), and some 
> more for NVL.

Yeah, I think this actually the wrong place to program this as
it also affects infoframes on HDMI. Probably all these should
be in the infoframe code somewhere.

> 
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> 
> > ---
> >   drivers/gpu/drm/i915/display/intel_vrr.c | 35 ++++++++----------------
> >   1 file changed, 12 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 6e8f8e673312..562a5feadaab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -571,6 +571,18 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> >   			       TRANS_VRR_VSYNC(display, cpu_transcoder),
> >   			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
> >   			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
> > +
> > +	/*
> > +	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> > +	 * double buffering point and transmission line for VRR packets for
> > +	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> > +	 * Since currently we support VRR only for DP/eDP, so this is programmed
> > +	 * to for Adaptive Sync SDP to Vsync start.
> > +	 */
> > +	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> > +		intel_de_write(display,
> > +			       EMP_AS_SDP_TL(display, cpu_transcoder),
> > +			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> >   }
> >   
> >   void intel_vrr_send_push(struct intel_dsb *dsb,
> > @@ -649,25 +661,6 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
> >   	return false;
> >   }
> >   
> > -static
> > -void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state *crtc_state)
> > -{
> > -	struct intel_display *display = to_intel_display(crtc_state);
> > -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > -
> > -	/*
> > -	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
> > -	 * double buffering point and transmission line for VRR packets for
> > -	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> > -	 * Since currently we support VRR only for DP/eDP, so this is programmed
> > -	 * to for Adaptive Sync SDP to Vsync start.
> > -	 */
> > -	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> > -		intel_de_write(display,
> > -			       EMP_AS_SDP_TL(display, cpu_transcoder),
> > -			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> > -}
> > -
> >   static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
> >   {
> >   	struct intel_display *display = to_intel_display(crtc_state);
> > @@ -710,8 +703,6 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> >   	intel_vrr_set_vrr_timings(crtc_state);
> >   
> >   	if (!intel_vrr_always_use_vrr_tg(display)) {
> > -		intel_vrr_set_db_point_and_transmission_line(crtc_state);
> > -
> >   		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> >   			       TRANS_PUSH_EN);
> >   
> > @@ -773,8 +764,6 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
> >   	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> >   		       TRANS_PUSH_EN);
> >   
> > -	intel_vrr_set_db_point_and_transmission_line(crtc_state);
> > -
> >   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> >   		       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> >   }

-- 
Ville Syrjälä
Intel

Re: [PATCH 13/22] drm/i915/vrr: Extract intel_vrr_tg_enable()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the VRR timing generator enable into intel_vrr_tg_enable(),
> as a counterpart to intel_vrr_tg_disable().
>
> Note that the CMRR part is probably broken, but so are other
> things in the CMRR implementation, and thus it is currently
> disabled.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 44 ++++++++++++++----------
>   1 file changed, 25 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 3ed6a56fb779..b49121b2676c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -692,6 +692,28 @@ static void intel_vrr_set_vrr_timings(const struct intel_crtc_state *crtc_state)
>   		       intel_vrr_hw_flipline(crtc_state) - 1);
>   }
>   
> +static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
> +				bool cmrr_enable)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 vrr_ctl;
> +
> +	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
> +
> +	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
> +
> +	/*
> +	 * FIXME this might be broken as bspec seems to imply that
> +	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
> +	 * when enabling CMRR (but not when disabling CMRR?).
> +	 */
> +	if (cmrr_enable)
> +		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> +
> +	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
> +}
> +
>   static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(old_crtc_state);
> @@ -711,26 +733,14 @@ static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
>   void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>   
>   	if (!crtc_state->vrr.enable)
>   		return;
>   
>   	intel_vrr_set_vrr_timings(crtc_state);
>   
> -	if (!intel_vrr_always_use_vrr_tg(display)) {
> -		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> -			       TRANS_PUSH_EN);
> -
> -		if (crtc_state->cmrr.enable) {
> -			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> -				       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
> -				       trans_vrr_ctl(crtc_state));
> -		} else {
> -			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> -				       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> -		}
> -	}
> +	if (!intel_vrr_always_use_vrr_tg(display))
> +		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
>   }
>   
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -763,11 +773,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
>   		return;
>   	}
>   
> -	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> -		       TRANS_PUSH_EN);
> -
> -	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> -		       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> +	intel_vrr_tg_enable(crtc_state, false);
>   }
>   
>   void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)

Re: [PATCH 14/22] drm/i915/vrr: Disable VRR TG in intel_vrr_transcoder_disable() only on always use_vrr_tg() platforms

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we always disable the VRR timing generator in
> intel_vrr_transcoder_disable(). But doing so on !always_use_vrr_tg()
> platforms is redundant since we've alreayd disabled the VRR timing
> generator earlier in intel_vrr_disable(). Do the disable in
> intel_vrr_transcoder_disable() only on always_on_vrr_tg() platforms.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b49121b2676c..d8fbbef1ae23 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -786,7 +786,8 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
>   	if (!intel_vrr_possible(crtc_state))
>   		return;
>   
> -	intel_vrr_tg_disable(crtc_state);
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		intel_vrr_tg_disable(crtc_state);
>   }
>   
>   bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)

Re: [PATCH 15/22] drm/i915/vrr: Always write TRANS_VRR_CTL in intel_vrr_set_transcoder_timings() on !always_use_vrr_tg()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently, dependign on vrr.enable, we may write TRANS_VRR_CTL from

Typo : depending

Otherwise LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> both intel_vrr_set_transcoder_timings() and intel_vrr_transcoder_enable()
> on !always_use_vrr_tg() platforms. Streamline this so that we just
> always write it from intel_vrr_set_transcoder_timings(), and
> never from intel_vrr_transcoder_enable().
>
> The main benefit is that intel_vrr_transcoder_enable() becomes symmetric
> to intel_vrr_transcoder_disable().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++---------
>   1 file changed, 3 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index d8fbbef1ae23..67b1ed606d8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -562,7 +562,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   
>   	intel_vrr_set_fixed_rr_timings(crtc_state);
>   
> -	if (!intel_vrr_always_use_vrr_tg(display) && !crtc_state->vrr.enable)
> +	if (!intel_vrr_always_use_vrr_tg(display))
>   		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
>   			       trans_vrr_ctl(crtc_state));
>   
> @@ -759,7 +759,6 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>   
>   	if (!HAS_VRR(display))
>   		return;
> @@ -767,13 +766,8 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
>   	if (!intel_vrr_possible(crtc_state))
>   		return;
>   
> -	if (!intel_vrr_always_use_vrr_tg(display)) {
> -		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> -			       trans_vrr_ctl(crtc_state));
> -		return;
> -	}
> -
> -	intel_vrr_tg_enable(crtc_state, false);
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		intel_vrr_tg_enable(crtc_state, false);
>   }
>   
>   void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)

Re: [PATCH 16/22] drm/i915/vrr: Remove redundant HAS_VRR() checks

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_vrr_transcoder_{enable,disable}() already check
> for intel_vrr_possible(), so the extra HAS_VRR() checks are
> redundant. Remove them.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 6 ------
>   1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 67b1ed606d8f..b64a54d22991 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -760,9 +760,6 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   
> -	if (!HAS_VRR(display))
> -		return;
> -
>   	if (!intel_vrr_possible(crtc_state))
>   		return;
>   
> @@ -774,9 +771,6 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   
> -	if (!HAS_VRR(display))
> -		return;
> -
>   	if (!intel_vrr_possible(crtc_state))
>   		return;
>   

Re: [PATCH 17/22] drm/i915/vrr: Move HAS_VRR() check into intel_vrr_set_transcoder_timings()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reduce the clutter in hsw_configure_cpu_transcoder() a bit by moving
> the HAS_VRR() check into intel_vrr_set_transcoder_timings().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 3 +--
>   drivers/gpu/drm/i915/display/intel_vrr.c     | 3 +++
>   2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 490b4f2907e1..2744f83bda2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1581,8 +1581,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
>   	}
>   
>   	intel_set_transcoder_timings(crtc_state);
> -	if (HAS_VRR(display))
> -		intel_vrr_set_transcoder_timings(crtc_state);
> +	intel_vrr_set_transcoder_timings(crtc_state);
>   
>   	if (cpu_transcoder != TRANSCODER_EDP)
>   		intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index b64a54d22991..29143dd092a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -534,6 +534,9 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>   
> +	if (!HAS_VRR(display))
> +		return;
> +
>   	/*
>   	 * This bit seems to have two meanings depending on the platform:
>   	 * TGL: generate VRR "safe window" for DSB vblank waits

Re: [PATCH 18/22] drm/i915/vrr: s/crtc_state/old_crtc_state/ in intel_vrr_transcoder_disable()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We generally use the 'old_crtc_state' in the disable functiosn to
Typo: function
> make it clear these generally get called when the hardware is
> still using the old crtc state rather than the new crtc state.
> Rename the intel_vrr_transcoder_disable() 'crtc_state' parameter
> to 'old_crtc_state' for consistency.

Makes sense, will keep this in mind going forward.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 29143dd092a8..71c5d8bf7557 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -770,15 +770,15 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
>   		intel_vrr_tg_enable(crtc_state, false);
>   }
>   
> -void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state)
> +void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state)
>   {
> -	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_display *display = to_intel_display(old_crtc_state);
>   
> -	if (!intel_vrr_possible(crtc_state))
> +	if (!intel_vrr_possible(old_crtc_state))
>   		return;
>   
>   	if (intel_vrr_always_use_vrr_tg(display))
> -		intel_vrr_tg_disable(crtc_state);
> +		intel_vrr_tg_disable(old_crtc_state);
>   }
>   
>   bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)

Re: [PATCH 19/22] drm/i915/vrr: Nuke intel_vrr_vblank_exit_length()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we always populate crtc_state->vrr.guardband even on
> ICL/TGL intel_vrr_vblank_exit_length() has become rather pointless.
> Get rid of it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++------
>   1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 71c5d8bf7557..ba92e0a76855 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -143,10 +143,6 @@ static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *c
>    *
>    * framestart_delay is programmable 1-4.
>    */
> -static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
> -{
> -	return crtc_state->vrr.guardband;
> -}
>   
>   int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
>   {
> @@ -161,12 +157,12 @@ int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
>   
>   int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
>   {
> -	return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
> +	return intel_vrr_vmin_vtotal(crtc_state) - crtc_state->vrr.guardband;
>   }
>   
>   int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
>   {
> -	return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
> +	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
>   }
>   
>   static bool

Re: [PATCH 20/22] drm/i915/vrr: Nuke intel_vrr_vmin_flipline()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that intel_vrr_flipline_offset() is completely hidden from the
> higher level VRR code, intel_vrr_vmin_flipline() has become rather
> pointless. Remove it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 9 ++-------
>   1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index ba92e0a76855..8875e5fe86aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -108,11 +108,6 @@ static int intel_vrr_vmin_flipline_offset(struct intel_display *display)
>   	return DISPLAY_VER(display) < 13 ? 1 : 0;
>   }
>   
> -static int intel_vrr_vmin_flipline(const struct intel_crtc_state *crtc_state)
> -{
> -	return crtc_state->vrr.vmin;
> -}
> -
>   static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state,
>   						int guardband)
>   {
> @@ -147,7 +142,7 @@ static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *c
>   int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
>   {
>   	/* Min vblank actually determined by flipline */
> -	return intel_vrr_vmin_flipline(crtc_state);
> +	return crtc_state->vrr.vmin;
>   }
>   
>   int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
> @@ -781,7 +776,7 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state)
>   {
>   	return crtc_state->vrr.flipline &&
>   	       crtc_state->vrr.flipline == crtc_state->vrr.vmax &&
> -	       crtc_state->vrr.flipline == intel_vrr_vmin_flipline(crtc_state);
> +	       crtc_state->vrr.flipline == crtc_state->vrr.vmin;
>   }
>   
>   void intel_vrr_get_config(struct intel_crtc_state *crtc_state)

Re: [PATCH 21/22] drm/i915/vrr: Update the intel_vrr_extra_vblank_delay() comment

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The coment in intel_vrr_extra_vblank_delay() is a bit outdated now
> that we generally got rid of the "vblank delay" stuff. Update the
> comment to better describe the current state of things.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++----
>   1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 8875e5fe86aa..c28491b9002a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -87,10 +87,8 @@ static int intel_vrr_extra_vblank_delay(struct intel_display *display)
>   	/*
>   	 * On ICL/TGL VRR hardware inserts one extra scanline
>   	 * just after vactive, which pushes the vmin decision
> -	 * boundary ahead accordingly. We'll include the extra
> -	 * scanline in our vblank delay estimates to make sure
> -	 * that we never underestimate how long we have until
> -	 * the delayed vblank has passed.
> +	 * boundary ahead accordingly, and thus reduces the
> +	 * max guardband length by one scanline.
>   	 */
>   	return DISPLAY_VER(display) < 13 ? 1 : 0;
>   }

Re: [PATCH 22/22] drm/i915/vrr: Check HAS_VRR() first in intel_vrr_is_capable()

[Nautiyal, Ankit K]

On 10/21/2025 12:20 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There's no point in doing all the other checks in
> intel_vrr_is_capable() is the platform doesn't support VRR at all

s/is/if


> Check HAS_VRR() before wasting time on the other checks.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index c28491b9002a..00cbc126fb36 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -25,6 +25,9 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
>   	const struct drm_display_info *info = &connector->base.display_info;
>   	struct intel_dp *intel_dp;
>   
> +	if (!HAS_VRR(display))
> +		return false;
> +
>   	/*
>   	 * DP Sink is capable of VRR video timings if
>   	 * Ignore MSA bit is set in DPCD.
> @@ -49,8 +52,7 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
>   		return false;
>   	}
>   
> -	return HAS_VRR(display) &&
> -		info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
> +	return info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
>   }
>   
>   bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh)