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From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Subject: [CI 08/14] drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds
Date: Wed, 22 Oct 2025 08:32:33 +0100	[thread overview]
Message-ID: <20251022073241.71401-9-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20251022073241.71401-1-tvrtko.ursulin@igalia.com>

Following from the i915 reference implementation, we add the AuxCCS
invalidation to the indirect context workarounds page.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
---
 drivers/gpu/drm/xe/xe_lrc.c | 42 +++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index b5083c99dd50..7543df0160dd 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -27,6 +27,7 @@
 #include "xe_map.h"
 #include "xe_memirq.h"
 #include "xe_mmio.h"
+#include "xe_ring_ops.h"
 #include "xe_sriov.h"
 #include "xe_trace_lrc.h"
 #include "xe_vm.h"
@@ -74,6 +75,21 @@ lrc_to_xe(struct xe_lrc *lrc)
 	return gt_to_xe(lrc->fence_ctx.gt);
 }
 
+static bool
+xe_engine_supports_auxccs(struct xe_device *xe, enum xe_engine_class class)
+{
+	if (GRAPHICS_VERx100(xe) >= 1200 &&
+	    GRAPHICS_VERx100(xe) <= 1210 &&
+	    (class == XE_ENGINE_CLASS_RENDER ||
+	     class == XE_ENGINE_CLASS_COMPUTE ||
+	     class == XE_ENGINE_CLASS_COPY ||
+	     class == XE_ENGINE_CLASS_VIDEO_DECODE ||
+	     class == XE_ENGINE_CLASS_VIDEO_ENHANCE))
+		return true;
+
+	return false;
+}
+
 static bool
 gt_engine_needs_indirect_ctx(struct xe_gt *gt, enum xe_engine_class class)
 {
@@ -88,6 +104,10 @@ gt_engine_needs_indirect_ctx(struct xe_gt *gt, enum xe_engine_class class)
 					       class, NULL))
 		return true;
 
+	/* For AuxCCS invalidation */
+	if (xe_engine_supports_auxccs(xe, class))
+		return true;
+
 	return false;
 }
 
@@ -1188,6 +1208,26 @@ static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
 	return cmd - batch;
 }
 
+static ssize_t setup_invalidate_auxccs_wa(struct xe_lrc *lrc,
+					  struct xe_hw_engine *hwe,
+					  u32 *batch, size_t max_len)
+{
+	struct xe_gt *gt = lrc->gt;
+	struct xe_device *xe = gt_to_xe(gt);
+	const unsigned int class = hwe->class;
+	u32 *cmd;
+
+	if (!xe_engine_supports_auxccs(xe, class))
+		return 0;
+
+	if (xe_gt_WARN_ON(gt, max_len < 8))
+		return -ENOSPC;
+
+	cmd = xe_emit_aux_table_inv(hwe, batch);
+
+	return cmd - batch;
+}
+
 struct bo_setup {
 	ssize_t (*setup)(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
 			 u32 *batch, size_t max_size);
@@ -1320,9 +1360,11 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
 {
 	static const struct bo_setup rcs_funcs[] = {
 		{ .setup = setup_timestamp_wa },
+		{ .setup = setup_invalidate_auxccs_wa },
 		{ .setup = setup_configfs_mid_ctx_restore_bb },
 	};
 	static const struct bo_setup xcs_funcs[] = {
+		{ .setup = setup_invalidate_auxccs_wa },
 		{ .setup = setup_configfs_mid_ctx_restore_bb },
 	};
 	struct bo_setup_state state = {
-- 
2.48.0


  parent reply	other threads:[~2025-10-22  7:32 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-22  7:32 [CI 00/14] auxccs ci run no stolen with flush Tvrtko Ursulin
2025-10-22  7:32 ` [CI 01/14] drm/xe: Fix ggtt fb alignment Tvrtko Ursulin
2025-10-22  7:32 ` [CI 02/14] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-10-22  7:32 ` [CI 03/14] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS Tvrtko Ursulin
2025-10-22  7:32 ` [CI 04/14] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-10-22  7:32 ` [CI 05/14] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-10-22  7:32 ` [CI 06/14] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2025-10-22  7:32 ` [CI 07/14] drm/xe: Export xe_emit_aux_table_inv Tvrtko Ursulin
2025-10-22  7:32 ` Tvrtko Ursulin [this message]
2025-10-22  7:32 ` [CI 09/14] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-10-22  7:32 ` [CI 10/14] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-10-22  7:32 ` [CI 11/14] drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS Tvrtko Ursulin
2025-10-22  7:32 ` [CI 12/14] drm/xe: Force flush system memory AuxCCS framebuffers before scan out Tvrtko Ursulin
2025-10-22  7:32 ` [CI 13/14] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-10-22  7:32 ` [CI 14/14] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-10-22  8:53 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen with flush Patchwork
2025-10-22  8:54 ` ✓ CI.KUnit: success " Patchwork
2025-10-22  9:36 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 11:39 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-22 17:16 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen with flush (rev2) Patchwork
2025-10-22 17:17 ` ✓ CI.KUnit: success " Patchwork
2025-10-22 17:55 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 20:47 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-23  9:31 ` ✗ CI.checkpatch: warning for auxccs ci run no stolen with flush (rev3) Patchwork
2025-10-23  9:32 ` ✓ CI.KUnit: success " Patchwork
2025-10-23 10:42 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-23 16:11 ` ✗ Xe.CI.Full: failure " Patchwork

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