From: Suraj Kandpal <suraj.kandpal@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, arun.r.murthy@intel.com,
uma.shankar@intel.com, gustavo.sousa@intel.com,
lucas.demarchi@intel.com, Suraj Kandpal <suraj.kandpal@intel.com>
Subject: [PATCH v2 10/26] drm/i915/ltphy: Update the ltpll config table value for eDP
Date: Fri, 24 Oct 2025 15:36:56 +0530 [thread overview]
Message-ID: <20251024100712.3776261-11-suraj.kandpal@intel.com> (raw)
In-Reply-To: <20251024100712.3776261-1-suraj.kandpal@intel.com>
When we get the eDP tables we reuse dp tables for some data rates.
We need to modify the 3rd config value of this table to 1 instead
of 0 since that is the only difference in the dp and edp table for
that particular data rate.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index b506bda8a751..c790fe652aa0 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1227,6 +1227,10 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
for (i = 0; tables[i]; i++) {
if (crtc_state->port_clock == tables[i]->clock) {
crtc_state->dpll_hw_state.ltpll = *tables[i];
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ crtc_state->dpll_hw_state.ltpll.config[2] = 1;
+ }
return 0;
}
}
--
2.34.1
next prev parent reply other threads:[~2025-10-24 10:07 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-24 10:06 [PATCH v2 00/26] Enable LT PHY Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 01/26] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 02/26] drm/i915/cx0: Change register bit naming for powerdown values Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 03/26] drm/i915/ltphy: Phy lane reset for LT Phy Suraj Kandpal
2025-10-28 7:47 ` Murthy, Arun R
2025-10-24 10:06 ` [PATCH v2 04/26] drm/i915/cx0: Move the HDMI FRL function to intel_hdmi Suraj Kandpal
2025-10-28 7:48 ` Murthy, Arun R
2025-10-24 10:06 ` [PATCH v2 05/26] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy Suraj Kandpal
2025-10-28 7:51 ` Murthy, Arun R
2025-10-24 10:06 ` [PATCH v2 06/26] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 07/26] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register Suraj Kandpal
2025-10-28 9:17 ` Jani Nikula
2025-10-24 10:06 ` [PATCH v2 08/26] drm/i915/ltphy: Add LT Phy Programming recipe tables Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 09/26] drm/i915/ltphy: Program the VDR PLL registers for LT PHY Suraj Kandpal
2025-10-24 10:06 ` Suraj Kandpal [this message]
2025-10-24 10:06 ` [PATCH v2 11/26] drm/i915/ltphy: Enable SSC during port clock programming Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 12/26] drm/i915/ltphy: Add function to calculate LT PHY port clock Suraj Kandpal
2025-10-31 5:15 ` Nautiyal, Ankit K
2025-10-24 10:06 ` [PATCH v2 13/26] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy Suraj Kandpal
2025-10-28 7:55 ` Murthy, Arun R
2025-10-24 10:07 ` [PATCH v2 14/26] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 15/26] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 16/26] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 17/26] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 18/26] drm/i915/ddi: Define LT Phy Swing tables Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 19/26] drm/i915/ltphy: Program LT Phy Voltage Swing Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 20/26] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 21/26] drm/i915/ltphy: Define the LT Phy state compare function Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 22/26] drm/i915/ltphy: Define function to readout LT Phy PLL state Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 23/26] drm/i915/ltphy: Define LT PHY PLL state verify function Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 24/26] drm/i915/display: Aux Enable and Display powerwell timeouts Suraj Kandpal
2025-10-28 7:58 ` Murthy, Arun R
2025-10-24 10:07 ` [PATCH v2 25/26] drm/i915/ltphy: Modify the step that need to be skipped Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 26/26] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-10-31 6:24 ` Nautiyal, Ankit K
2025-10-24 10:27 ` ✗ CI.checkpatch: warning for Enable LT PHY (rev2) Patchwork
2025-10-24 10:28 ` ✓ CI.KUnit: success " Patchwork
2025-10-24 10:43 ` ✗ CI.checksparse: warning " Patchwork
2025-10-24 11:20 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-24 21:07 ` ✗ Xe.CI.Full: failure " Patchwork
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