Re: [PATCH v2 04/26] drm/i915/cx0: Move the HDMI FRL function to intel_hdmi

["Murthy, Arun R" <arun.r.murthy@intel.com>]

On 24-10-2025 15:36, Suraj Kandpal wrote:
> Move the is_hdmi_frl to intel_hdmi.c. Rename it appropriately and
> make it non static.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c | 21 +++-----------------
>   drivers/gpu/drm/i915/display/intel_hdmi.c    | 14 +++++++++++++
>   drivers/gpu/drm/i915/display/intel_hdmi.h    |  1 +
>   3 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index c99e0885e737..6991707abdc7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2590,20 +2590,6 @@ static bool is_dp2(u32 clock)
>   	return false;
>   }
>   
> -static bool is_hdmi_frl(u32 clock)
> -{
> -	switch (clock) {
> -	case 300000: /* 3 Gbps */
> -	case 600000: /* 6 Gbps */
> -	case 800000: /* 8 Gbps */
> -	case 1000000: /* 10 Gbps */
> -	case 1200000: /* 12 Gbps */
> -		return true;
> -	default:
> -		return false;
> -	}
> -}
> -
>   static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
>   {
>   	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> @@ -2617,7 +2603,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
>   {
>   	if (dp && is_dp2(clock))
>   		return 2;
> -	else if (is_hdmi_frl(clock))
> +	else if (intel_hdmi_is_frl(clock))
>   		return 1;
>   	else
>   		return 0;
> @@ -2706,11 +2692,10 @@ static void intel_c20_pll_program(struct intel_display *display,
>   
>   	/* 5. For DP or 6. For HDMI */
>   	serdes = 0;
> -
>   	if (is_dp)
>   		serdes = PHY_C20_IS_DP |
>   			 PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
> -	else if (is_hdmi_frl(port_clock))
> +	else if (intel_hdmi_is_frl(port_clock))
>   		serdes = PHY_C20_IS_HDMI_FRL;
>   
>   	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
> @@ -2777,7 +2762,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>   
>   	val |= XELPDP_FORWARD_CLOCK_UNGATE;
>   
> -	if (!is_dp && is_hdmi_frl(port_clock))
> +	if (!is_dp && intel_hdmi_is_frl(port_clock))
>   		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
>   	else
>   		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 4ab7e2e3bfd4..e81c3e5aa250 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -68,6 +68,20 @@
>   #include "intel_snps_phy.h"
>   #include "intel_vrr.h"
>   
> +bool intel_hdmi_is_frl(u32 clock)
> +{
> +	switch (clock) {
> +	case 300000: /* 3 Gbps */
> +	case 600000: /* 6 Gbps */
> +	case 800000: /* 8 Gbps */
> +	case 1000000: /* 10 Gbps */
> +	case 1200000: /* 12 Gbps */
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
>   static void
>   assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
>   {
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
> index dec2ad7dd8a2..be2fad57e4ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
> @@ -60,6 +60,7 @@ int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
>   				  int src_max_slices, int src_max_slice_width,
>   				  int hdmi_max_slices, int hdmi_throughput);
>   int intel_hdmi_dsc_get_slice_height(int vactive);
> +bool intel_hdmi_is_frl(u32 clock);
>   
>   void hsw_write_infoframe(struct intel_encoder *encoder,
>   			 const struct intel_crtc_state *crtc_state,