Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Suraj Kandpal <suraj.kandpal@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, arun.r.murthy@intel.com,
	uma.shankar@intel.com, gustavo.sousa@intel.com,
	lucas.demarchi@intel.com, Suraj Kandpal <suraj.kandpal@intel.com>
Subject: [PATCH v2 21/26] drm/i915/ltphy: Define the LT Phy state compare function
Date: Fri, 24 Oct 2025 15:37:07 +0530	[thread overview]
Message-ID: <20251024100712.3776261-22-suraj.kandpal@intel.com> (raw)
In-Reply-To: <20251024100712.3776261-1-suraj.kandpal@intel.com>

Define function to compare the state and if mismatch is detected
dump both the states.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 33 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c  | 30 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h  |  6 ++++
 3 files changed, 68 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a8b4619de347..c4452ed4a42d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -99,6 +99,7 @@
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
 #include "intel_link_bw.h"
+#include "intel_lt_phy.h"
 #include "intel_lvds.h"
 #include "intel_lvds_regs.h"
 #include "intel_modeset_setup.h"
@@ -4969,6 +4970,24 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
 	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
 }
 
+static void
+pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
+				const struct intel_crtc *crtc,
+				const char *name,
+				const struct intel_lt_phy_pll_state *a,
+				const struct intel_lt_phy_pll_state *b)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	char *chipname = "LTPHY";
+
+	pipe_config_mismatch(p, fastset, crtc, name, chipname);
+
+	drm_printf(p, "expected:\n");
+	intel_lt_phy_dump_hw_state(display, a);
+	drm_printf(p, "found:\n");
+	intel_lt_phy_dump_hw_state(display, b);
+}
+
 bool
 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 			  const struct intel_crtc_state *pipe_config,
@@ -5093,6 +5112,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_PLL_LT(name) do { \
+	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
+					       &pipe_config->name)) { \
+		pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
+						&current_config->name, \
+						&pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)
+
 #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
 	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
 	PIPE_CONF_CHECK_I(name.crtc_htotal); \
@@ -5317,7 +5346,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_PLL(dpll_hw_state);
 
 	/* FIXME convert MTL+ platforms over to dpll_mgr */
-	if (DISPLAY_VER(display) >= 14)
+	if (HAS_LT_PHY(display))
+		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
+	else if (DISPLAY_VER(display) >= 14)
 		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
 
 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 9ee862f95209..45130fdc6273 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1839,6 +1839,36 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
 	intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
+void intel_lt_phy_dump_hw_state(struct intel_display *display,
+				const struct intel_lt_phy_pll_state *hw_state)
+{
+	int i, j;
+
+	drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n");
+	for (i = 0; i < 3; i++) {
+		drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n",
+			    i, hw_state->config[i]);
+	}
+
+	for (i = 0; i <= 12; i++)
+		for (j = 3; j >= 0; j--)
+			drm_dbg_kms(display->drm, "vdr_data[%d][%d] = 0x%.4x,\n",
+				    i, j, hw_state->data[i][j]);
+}
+
+bool
+intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
+				  const struct intel_lt_phy_pll_state *b)
+{
+	if (memcmp(&a->config, &b->config, sizeof(a->config)) != 0)
+		return false;
+
+	if (memcmp(&a->data, &b->data, sizeof(a->data)) != 0)
+		return false;
+
+	return true;
+}
+
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 6e67ae78801c..e93e5becc316 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+struct intel_display;
 struct intel_encoder;
 struct intel_crtc_state;
 struct intel_lt_phy_pll_state;
@@ -22,6 +23,11 @@ int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state);
 void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
 				    const struct intel_crtc_state *crtc_state);
+void intel_lt_phy_dump_hw_state(struct intel_display *display,
+				const struct intel_lt_phy_pll_state *hw_state);
+bool
+intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a,
+				  const struct intel_lt_phy_pll_state *b);
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
-- 
2.34.1


  parent reply	other threads:[~2025-10-24 10:08 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-24 10:06 [PATCH v2 00/26] Enable LT PHY Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 01/26] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 02/26] drm/i915/cx0: Change register bit naming for powerdown values Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 03/26] drm/i915/ltphy: Phy lane reset for LT Phy Suraj Kandpal
2025-10-28  7:47   ` Murthy, Arun R
2025-10-24 10:06 ` [PATCH v2 04/26] drm/i915/cx0: Move the HDMI FRL function to intel_hdmi Suraj Kandpal
2025-10-28  7:48   ` Murthy, Arun R
2025-10-24 10:06 ` [PATCH v2 05/26] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy Suraj Kandpal
2025-10-28  7:51   ` Murthy, Arun R
2025-10-24 10:06 ` [PATCH v2 06/26] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 07/26] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register Suraj Kandpal
2025-10-28  9:17   ` Jani Nikula
2025-10-24 10:06 ` [PATCH v2 08/26] drm/i915/ltphy: Add LT Phy Programming recipe tables Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 09/26] drm/i915/ltphy: Program the VDR PLL registers for LT PHY Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 10/26] drm/i915/ltphy: Update the ltpll config table value for eDP Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 11/26] drm/i915/ltphy: Enable SSC during port clock programming Suraj Kandpal
2025-10-24 10:06 ` [PATCH v2 12/26] drm/i915/ltphy: Add function to calculate LT PHY port clock Suraj Kandpal
2025-10-31  5:15   ` Nautiyal, Ankit K
2025-10-24 10:06 ` [PATCH v2 13/26] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy Suraj Kandpal
2025-10-28  7:55   ` Murthy, Arun R
2025-10-24 10:07 ` [PATCH v2 14/26] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 15/26] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 16/26] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 17/26] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 18/26] drm/i915/ddi: Define LT Phy Swing tables Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 19/26] drm/i915/ltphy: Program LT Phy Voltage Swing Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 20/26] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence Suraj Kandpal
2025-10-24 10:07 ` Suraj Kandpal [this message]
2025-10-24 10:07 ` [PATCH v2 22/26] drm/i915/ltphy: Define function to readout LT Phy PLL state Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 23/26] drm/i915/ltphy: Define LT PHY PLL state verify function Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 24/26] drm/i915/display: Aux Enable and Display powerwell timeouts Suraj Kandpal
2025-10-28  7:58   ` Murthy, Arun R
2025-10-24 10:07 ` [PATCH v2 25/26] drm/i915/ltphy: Modify the step that need to be skipped Suraj Kandpal
2025-10-24 10:07 ` [PATCH v2 26/26] drm/i915/ltphy: Implement HDMI Algo for Pll state Suraj Kandpal
2025-10-31  6:24   ` Nautiyal, Ankit K
2025-10-24 10:27 ` ✗ CI.checkpatch: warning for Enable LT PHY (rev2) Patchwork
2025-10-24 10:28 ` ✓ CI.KUnit: success " Patchwork
2025-10-24 10:43 ` ✗ CI.checksparse: warning " Patchwork
2025-10-24 11:20 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-24 21:07 ` ✗ Xe.CI.Full: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251024100712.3776261-22-suraj.kandpal@intel.com \
    --to=suraj.kandpal@intel.com \
    --cc=ankit.k.nautiyal@intel.com \
    --cc=arun.r.murthy@intel.com \
    --cc=gustavo.sousa@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=uma.shankar@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox