[PATCH 00/19] Make Display free from i915_reg.h

[PATCH 00/19] Make Display free from i915_reg.h

[Uma Shankar]

Move the common register definition to a header to free up
display files from including i915_reg.h. This will help
avoid dupicate definitions and includes and can serve as
a common file for xe, i915 and display module.

Uma Shankar (19):
  drm/{i915, xe}: Extract common registers into a separate file
  drm/{i915, xe}: Extract South chicken registers
  drm/{i915, xe}: Extract display interrupt definitions
  drm/{i915, xe}: Extract DSPCLK_GATE_D
  drm/{i915, xe}: Extract pcode definitions
  drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c
  drm/{i915, xe}: Remove i915_reg.h from intel_dram.c
  drm/{i915, xe}: Removed i915_reg.h from intel_display.c
  drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c
  drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c
  drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c
  drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
  drm/{i915, xe}: Remove i915_reg.h from intel_rom.c
  drm/{i915, xe}: Remove i915_reg.h from intel_psr.c
  drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c
  drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c
  drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c
  drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c
  drm/{i915, xe}: Removed i915_reg.h from display

 drivers/gpu/drm/i915/display/g4x_dp.c         |   2 +-
 drivers/gpu/drm/i915/display/g4x_hdmi.c       |   2 +-
 drivers/gpu/drm/i915/display/hsw_ips.c        |   2 +-
 drivers/gpu/drm/i915/display/i9xx_plane.c     |   2 +-
 drivers/gpu/drm/i915/display/i9xx_wm.c        |   2 +-
 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 +-
 .../gpu/drm/i915/display/intel_backlight.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_bw.c       |   2 +-
 drivers/gpu/drm/i915/display/intel_casf.c     |   1 -
 drivers/gpu/drm/i915/display/intel_cdclk.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
 .../drm/i915/display/intel_display_debugfs.c  |   2 +-
 .../drm/i915/display/intel_display_device.c   |   2 +-
 .../gpu/drm/i915/display/intel_display_irq.c  |   2 +-
 .../drm/i915/display/intel_display_power.c    |   2 +-
 .../i915/display/intel_display_power_well.c   |   2 +-
 .../gpu/drm/i915/display/intel_display_regs.h |  90 +++-
 .../gpu/drm/i915/display/intel_display_rps.c  |   2 +-
 .../gpu/drm/i915/display/intel_display_wa.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_dram.c     |   3 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |   2 +-
 .../drm/i915/display/intel_fifo_underrun.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_gmbus.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c     |   2 +-
 .../gpu/drm/i915/display/intel_hotplug_irq.c  |   2 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |   2 +-
 .../drm/i915/display/intel_modeset_setup.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_overlay.c  |   2 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   2 +-
 .../gpu/drm/i915/display/intel_pch_refclk.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_pps.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_rom.c      |   4 +-
 drivers/gpu/drm/i915/display/intel_tc.c       |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |   2 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |   2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 463 +-----------------
 include/drm/intel/intel_gmd_common_regs.h     | 419 ++++++++++++++++
 40 files changed, 534 insertions(+), 514 deletions(-)
 create mode 100644 include/drm/intel/intel_gmd_common_regs.h

-- 
2.50.1

[PATCH 01/19] drm/{i915, xe}: Extract common registers into a separate file

[Uma Shankar]

There are certain register definitions which are commonly shared
by i915, xe and display. Extract the same to a common header to
avoid duplication.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_pch_display.c    |  2 +-
 drivers/gpu/drm/i915/i915_reg.h                 | 11 +----------
 include/drm/intel/intel_gmd_common_regs.h       | 17 +++++++++++++++++
 3 files changed, 19 insertions(+), 11 deletions(-)
 create mode 100644 include/drm/intel/intel_gmd_common_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 16619f7be5f8..2f39ff32c6d5 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -4,9 +4,9 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_crt.h"
 #include "intel_crt_regs.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5bf3b4ab2baa..f60259c41c56 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,6 +25,7 @@
 #ifndef _I915_REG_H_
 #define _I915_REG_H_
 
+#include <drm/intel/intel_gmd_common_regs.h>
 #include "i915_reg_defs.h"
 #include "display/intel_display_reg_defs.h"
 
@@ -1022,16 +1023,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define _TRANSA_CHICKEN2	 0xf0064
-#define _TRANSB_CHICKEN2	 0xf1064
-#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
-#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
-#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
-#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
-#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
-#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
-
 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
new file mode 100644
index 000000000000..4d91bc2dbb27
--- /dev/null
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2025 Intel Corporation */
+
+#ifndef _INTEL_GMD_COMMON_REG_H_
+#define _INTEL_GMD_COMMON_REG_H_
+
+#define _TRANSA_CHICKEN2	 0xf0064
+#define _TRANSB_CHICKEN2	 0xf1064
+#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
+#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
+#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
+#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
+#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
+#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
+
+#endif
-- 
2.50.1

[PATCH 02/19] drm/{i915, xe}: Extract South chicken registers

[Uma Shankar]

Extract South Chicken registers to common header.
This allows intel_pch_refclk.c not to include i915_reg.h

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_pch_refclk.c   |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 27 -------------------
 include/drm/intel/intel_gmd_common_regs.h     | 27 +++++++++++++++++++
 3 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 9a89bb6dcf65..55abb97c6562 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -4,8 +4,8 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f60259c41c56..c1f33c11ac1b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1023,33 +1023,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define SOUTH_CHICKEN1		_MMIO(0xc2000)
-#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
-#define  FDIA_PHASE_SYNC_SHIFT_EN	18
-#define  INVERT_DDIE_HPD			REG_BIT(28)
-#define  INVERT_DDID_HPD_MTP			REG_BIT(27)
-#define  INVERT_TC4_HPD				REG_BIT(26)
-#define  INVERT_TC3_HPD				REG_BIT(25)
-#define  INVERT_TC2_HPD				REG_BIT(24)
-#define  INVERT_TC1_HPD				REG_BIT(23)
-#define  INVERT_DDID_HPD			(1 << 18)
-#define  INVERT_DDIC_HPD			(1 << 17)
-#define  INVERT_DDIB_HPD			(1 << 16)
-#define  INVERT_DDIA_HPD			(1 << 15)
-#define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
-#define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
-#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
-#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
-#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
-#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
-#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
-#define  SPT_PWM_GRANULARITY		(1 << 0)
-#define SOUTH_CHICKEN2		_MMIO(0xc2004)
-#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
-#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
-#define  LPT_PWM_GRANULARITY		(1 << 5)
-#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
-
 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
 #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 4d91bc2dbb27..b4cfd186d5c0 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -4,6 +4,33 @@
 #ifndef _INTEL_GMD_COMMON_REG_H_
 #define _INTEL_GMD_COMMON_REG_H_
 
+#define SOUTH_CHICKEN1		_MMIO(0xc2000)
+#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
+#define  FDIA_PHASE_SYNC_SHIFT_EN	18
+#define  INVERT_DDIE_HPD			REG_BIT(28)
+#define  INVERT_DDID_HPD_MTP			REG_BIT(27)
+#define  INVERT_TC4_HPD				REG_BIT(26)
+#define  INVERT_TC3_HPD				REG_BIT(25)
+#define  INVERT_TC2_HPD				REG_BIT(24)
+#define  INVERT_TC1_HPD				REG_BIT(23)
+#define  INVERT_DDID_HPD			(1 << 18)
+#define  INVERT_DDIC_HPD			(1 << 17)
+#define  INVERT_DDIB_HPD			(1 << 16)
+#define  INVERT_DDIA_HPD			(1 << 15)
+#define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
+#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
+#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
+#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
+#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
+#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
+#define  SPT_PWM_GRANULARITY		(1 << 0)
+#define SOUTH_CHICKEN2		_MMIO(0xc2004)
+#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
+#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
+#define  LPT_PWM_GRANULARITY		(1 << 5)
+#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
+
 #define _TRANSA_CHICKEN2	 0xf0064
 #define _TRANSB_CHICKEN2	 0xf1064
 #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-- 
2.50.1

[PATCH 03/19] drm/{i915, xe}: Extract display interrupt definitions

[Uma Shankar]

Move common registers to display to allow intel_display_rps.c
free of i915_reg.h dependency.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 34 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_display_rps.c  |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 33 ------------------
 3 files changed, 35 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9e0d853f4b61..566de308e482 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1333,6 +1333,40 @@
 						      GEN8_DE_PORT_IER, \
 						      GEN8_DE_PORT_IIR)
 
+/* interrupts */
+#define DE_MASTER_IRQ_CONTROL   (1 << 31)
+#define DE_SPRITEB_FLIP_DONE    (1 << 29)
+#define DE_SPRITEA_FLIP_DONE    (1 << 28)
+#define DE_PLANEB_FLIP_DONE     (1 << 27)
+#define DE_PLANEA_FLIP_DONE     (1 << 26)
+#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
+#define DE_PCU_EVENT            (1 << 25)
+#define DE_GTT_FAULT            (1 << 24)
+#define DE_POISON               (1 << 23)
+#define DE_PERFORM_COUNTER      (1 << 22)
+#define DE_PCH_EVENT            (1 << 21)
+#define DE_AUX_CHANNEL_A        (1 << 20)
+#define DE_DP_A_HOTPLUG         (1 << 19)
+#define DE_GSE                  (1 << 18)
+#define DE_PIPEB_VBLANK         (1 << 15)
+#define DE_PIPEB_EVEN_FIELD     (1 << 14)
+#define DE_PIPEB_ODD_FIELD      (1 << 13)
+#define DE_PIPEB_LINE_COMPARE   (1 << 12)
+#define DE_PIPEB_VSYNC          (1 << 11)
+#define DE_PIPEB_CRC_DONE	(1 << 10)
+#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
+#define DE_PIPEA_VBLANK         (1 << 7)
+#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
+#define DE_PIPEA_EVEN_FIELD     (1 << 6)
+#define DE_PIPEA_ODD_FIELD      (1 << 5)
+#define DE_PIPEA_LINE_COMPARE   (1 << 4)
+#define DE_PIPEA_VSYNC          (1 << 3)
+#define DE_PIPEA_CRC_DONE	(1 << 2)
+#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
+#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
+#define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
+
+
 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c b/drivers/gpu/drm/i915/display/intel_display_rps.c
index e77811396474..bf00266dae4b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_rps.c
+++ b/drivers/gpu/drm/i915/display/intel_display_rps.c
@@ -8,8 +8,8 @@
 #include <drm/drm_crtc.h>
 #include <drm/drm_vblank.h>
 
-#include "i915_reg.h"
 #include "intel_display_core.h"
+#include "intel_display_regs.h"
 #include "intel_display_irq.h"
 #include "intel_display_rps.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1f33c11ac1b..a338f01a539b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -805,39 +805,6 @@
 #define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
 
-/* interrupts */
-#define DE_MASTER_IRQ_CONTROL   (1 << 31)
-#define DE_SPRITEB_FLIP_DONE    (1 << 29)
-#define DE_SPRITEA_FLIP_DONE    (1 << 28)
-#define DE_PLANEB_FLIP_DONE     (1 << 27)
-#define DE_PLANEA_FLIP_DONE     (1 << 26)
-#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
-#define DE_PCU_EVENT            (1 << 25)
-#define DE_GTT_FAULT            (1 << 24)
-#define DE_POISON               (1 << 23)
-#define DE_PERFORM_COUNTER      (1 << 22)
-#define DE_PCH_EVENT            (1 << 21)
-#define DE_AUX_CHANNEL_A        (1 << 20)
-#define DE_DP_A_HOTPLUG         (1 << 19)
-#define DE_GSE                  (1 << 18)
-#define DE_PIPEB_VBLANK         (1 << 15)
-#define DE_PIPEB_EVEN_FIELD     (1 << 14)
-#define DE_PIPEB_ODD_FIELD      (1 << 13)
-#define DE_PIPEB_LINE_COMPARE   (1 << 12)
-#define DE_PIPEB_VSYNC          (1 << 11)
-#define DE_PIPEB_CRC_DONE	(1 << 10)
-#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
-#define DE_PIPEA_VBLANK         (1 << 7)
-#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
-#define DE_PIPEA_EVEN_FIELD     (1 << 6)
-#define DE_PIPEA_ODD_FIELD      (1 << 5)
-#define DE_PIPEA_LINE_COMPARE   (1 << 4)
-#define DE_PIPEA_VSYNC          (1 << 3)
-#define DE_PIPEA_CRC_DONE	(1 << 2)
-#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
-#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
-#define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
-
 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
 
-- 
2.50.1

[PATCH 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D

[Uma Shankar]

Move DSPCLK_GATE_D register definition to common header.
This allows intel_gmbus.c free of i915_reg.h include.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_gmbus.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h            | 50 ----------------------
 include/drm/intel/intel_gmd_common_regs.h  | 49 +++++++++++++++++++++
 3 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 2caff677600c..b77860c5d649 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -34,8 +34,8 @@
 
 #include <drm/drm_print.h>
 #include <drm/display/drm_hdcp_helper.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a338f01a539b..30f504a47593 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -614,47 +614,6 @@
 #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
 
-#define DSPCLK_GATE_D			_MMIO(0x6200)
-#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
-# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
-# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
-# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
-# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
-# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
-# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
-# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
-# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
-# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
-# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
-# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
-# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
-# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
-# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
-# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
-# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
-# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
-# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
-# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
-# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
-# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
-# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
-# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
-# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
-# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
-# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
-# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
-# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
-# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
-/*
- * This bit must be set on the 830 to prevent hangs when turning off the
- * overlay scaler.
- */
-# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
-# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
-# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
-# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
-# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
-
 #define RENCLK_GATE_D1		_MMIO(0x6204)
 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
@@ -990,15 +949,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
-#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
-#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
-#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
-#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
-#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
-#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
-#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index b4cfd186d5c0..fb2a327befd8 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -4,6 +4,46 @@
 #ifndef _INTEL_GMD_COMMON_REG_H_
 #define _INTEL_GMD_COMMON_REG_H_
 
+#define DSPCLK_GATE_D			_MMIO(0x6200)
+#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
+# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
+# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
+# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
+# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
+# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
+# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
+# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
+# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
+# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
+# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
+# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
+# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
+# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
+# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
+# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
+# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
+# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
+# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
+# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
+# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
+# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
+# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
+# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
+/*
+ * This bit must be set on the 830 to prevent hangs when turning off the
+ * overlay scaler.
+ */
+# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
+# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
+# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
+# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
+# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
@@ -31,6 +71,15 @@
 #define  LPT_PWM_GRANULARITY		(1 << 5)
 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
 
+#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
+#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
+#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
+#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
+#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
+#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
+#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
+#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
+
 #define _TRANSA_CHICKEN2	 0xf0064
 #define _TRANSB_CHICKEN2	 0xf1064
 #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-- 
2.50.1

[PATCH 05/19] drm/{i915, xe}: Extract pcode definitions

[Uma Shankar]

Move GEN6_PCODE_MAILBOX to common header to make
intel_cdclk.c free from including i915_reg.h

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c |   2 +-
 drivers/gpu/drm/i915/i915_reg.h            | 100 --------------------
 include/drm/intel/intel_gmd_common_regs.h  | 101 +++++++++++++++++++++
 3 files changed, 102 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0aa59d624095..56e5ef0f3bc9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -27,9 +27,9 @@
 
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_audio.h"
 #include "intel_cdclk.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 30f504a47593..35122c997b8a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -957,106 +957,6 @@
 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
 
-#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
-#define   GEN6_PCODE_READY			(1 << 31)
-#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
-#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
-#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
-#define   GEN6_PCODE_ERROR_MASK			0xFF
-#define     GEN6_PCODE_SUCCESS			0x0
-#define     GEN6_PCODE_ILLEGAL_CMD		0x1
-#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
-#define     GEN6_PCODE_TIMEOUT			0x3
-#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
-#define     GEN7_PCODE_TIMEOUT			0x2
-#define     GEN7_PCODE_ILLEGAL_DATA		0x3
-#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
-#define     GEN11_PCODE_LOCKED			0x6
-#define     GEN11_PCODE_REJECTED		0x11
-#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
-#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
-#define   GEN6_PCODE_READ_RC6VIDS		0x5
-#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
-#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
-#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
-#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
-#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK	REG_GENMASK(31, 24)
-#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK	REG_GENMASK(23, 16)
-#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK	REG_GENMASK(15, 8)
-#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
-#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
-#define   SKL_PCODE_CDCLK_CONTROL		0x7
-#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
-#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
-#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
-#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
-#define   GEN6_READ_OC_PARAMS			0xc
-#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
-#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
-#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
-#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
-#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
-#define   DISPLAY_TO_PCODE_VOLTAGE_MASK		REG_GENMASK(1, 0)
-#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX		DISPLAY_TO_PCODE_VOLTAGE_MASK
-#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
-#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
-#define   DISPLAY_TO_PCODE_CDCLK_MASK		REG_GENMASK(25, 16)
-#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK	REG_GENMASK(30, 28)
-#define   DISPLAY_TO_PCODE_CDCLK(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
-#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
-#define   DISPLAY_TO_PCODE_VOLTAGE(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
-#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
-		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
-		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
-		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
-#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
-#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
-#define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
-#define     ICL_PCODE_REP_QGV_POLL		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
-#define     ICL_PCODE_REP_QGV_REJECTED		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
-#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
-#define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
-#define     ADLS_PCODE_REP_PSF_POLL		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
-#define     ADLS_PCODE_REP_PSF_REJECTED		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
-#define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
-#define     ICL_PCODE_REQ_QGV_PT(x)		REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
-#define     ADLS_PCODE_REQ_PSF_PT_MASK		REG_GENMASK(10, 8)
-#define     ADLS_PCODE_REQ_PSF_PT(x)		REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
-#define   GEN6_PCODE_READ_D_COMP		0x10
-#define   GEN6_PCODE_WRITE_D_COMP		0x11
-#define   ICL_PCODE_EXIT_TCCOLD			0x12
-#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
-#define   DISPLAY_IPS_CONTROL			0x19
-#define   TGL_PCODE_TCCOLD			0x26
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
-            /* See also IPS_CTL */
-#define     IPS_PCODE_CONTROL			(1 << 30)
-#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
-#define   GEN9_PCODE_SAGV_CONTROL		0x21
-#define     GEN9_SAGV_DISABLE			0x0
-#define     GEN9_SAGV_IS_DISABLED		0x1
-#define     GEN9_SAGV_ENABLE			0x3
-#define   DG1_PCODE_STATUS			0x7E
-#define     DG1_UNCORE_GET_INIT_STATUS		0x0
-#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
-#define   PCODE_POWER_SETUP			0x7C
-#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
-#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
-#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
-#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */
-#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
-#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
-#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
-#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
-/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
-#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
-#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
-/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
-/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
-#define     PCODE_MBOX_DOMAIN_NONE		0x0
-#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index fb2a327befd8..5d156d7cfdbe 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -90,4 +90,105 @@
 #define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
 #define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
 
+#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
+#define   GEN6_PCODE_READY			(1 << 31)
+#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
+#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
+#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
+#define   GEN6_PCODE_ERROR_MASK			0xFF
+#define     GEN6_PCODE_SUCCESS			0x0
+#define     GEN6_PCODE_ILLEGAL_CMD		0x1
+#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
+#define     GEN6_PCODE_TIMEOUT			0x3
+#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
+#define     GEN7_PCODE_TIMEOUT			0x2
+#define     GEN7_PCODE_ILLEGAL_DATA		0x3
+#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
+#define     GEN11_PCODE_LOCKED			0x6
+#define     GEN11_PCODE_REJECTED		0x11
+#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
+#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
+#define   GEN6_PCODE_READ_RC6VIDS		0x5
+#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
+#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
+#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
+#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
+#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK	REG_GENMASK(31, 24)
+#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK	REG_GENMASK(23, 16)
+#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK	REG_GENMASK(15, 8)
+#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
+#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
+#define   SKL_PCODE_CDCLK_CONTROL		0x7
+#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
+#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
+#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
+#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
+#define   GEN6_READ_OC_PARAMS			0xc
+#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
+#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
+#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
+#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
+#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
+#define   DISPLAY_TO_PCODE_VOLTAGE_MASK		REG_GENMASK(1, 0)
+#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX		DISPLAY_TO_PCODE_VOLTAGE_MASK
+#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
+#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
+#define   DISPLAY_TO_PCODE_CDCLK_MASK		REG_GENMASK(25, 16)
+#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK	REG_GENMASK(30, 28)
+#define   DISPLAY_TO_PCODE_CDCLK(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
+#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
+#define   DISPLAY_TO_PCODE_VOLTAGE(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
+#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
+		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
+		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
+		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
+#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
+#define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
+#define     ICL_PCODE_REP_QGV_POLL		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
+#define     ICL_PCODE_REP_QGV_REJECTED		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
+#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
+#define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
+#define     ADLS_PCODE_REP_PSF_POLL		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
+#define     ADLS_PCODE_REP_PSF_REJECTED		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
+#define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
+#define     ICL_PCODE_REQ_QGV_PT(x)		REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
+#define     ADLS_PCODE_REQ_PSF_PT_MASK		REG_GENMASK(10, 8)
+#define     ADLS_PCODE_REQ_PSF_PT(x)		REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
+#define   GEN6_PCODE_READ_D_COMP		0x10
+#define   GEN6_PCODE_WRITE_D_COMP		0x11
+#define   ICL_PCODE_EXIT_TCCOLD			0x12
+#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
+#define   DISPLAY_IPS_CONTROL			0x19
+#define   TGL_PCODE_TCCOLD			0x26
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
+            /* See also IPS_CTL */
+#define     IPS_PCODE_CONTROL			(1 << 30)
+#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
+#define   GEN9_PCODE_SAGV_CONTROL		0x21
+#define     GEN9_SAGV_DISABLE			0x0
+#define     GEN9_SAGV_IS_DISABLED		0x1
+#define     GEN9_SAGV_ENABLE			0x3
+#define   DG1_PCODE_STATUS			0x7E
+#define     DG1_UNCORE_GET_INIT_STATUS		0x0
+#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
+#define   PCODE_POWER_SETUP			0x7C
+#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
+#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
+#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
+#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */
+#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
+#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
+#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
+#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
+#define     PCODE_MBOX_DOMAIN_NONE		0x0
+#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
+
 #endif
-- 
2.50.1

[PATCH 06/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c

[Uma Shankar]

Move GU_CNTL_PROTECTED to common header, this helps
intel_display_device.c free from i915_reg.h dependency.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display_regs.h   | 3 +++
 drivers/gpu/drm/i915/i915_reg.h                     | 8 --------
 include/drm/intel/intel_gmd_common_regs.h           | 5 +++++
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 471f236c9ddf..f7cc4198a870 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -9,8 +9,8 @@
 #include <drm/drm_drv.h>
 #include <drm/drm_print.h>
 #include <drm/intel/pciids.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_de.h"
 #include "intel_display.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 566de308e482..8d0badea5cad 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -6,6 +6,9 @@
 
 #include "intel_display_reg_defs.h"
 
+#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
+#define   DEPRESENT			REG_BIT(9)
+
 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 35122c997b8a..fac24a649d61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -117,9 +117,6 @@
  *  #define GEN8_BAR                    _MMIO(0xb888)
  */
 
-#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
-#define   DEPRESENT			REG_BIT(9)
-
 #define GU_CNTL				_MMIO(0x101010)
 #define   LMEM_INIT			REG_BIT(7)
 #define   DRIVERFLR			REG_BIT(31)
@@ -925,11 +922,6 @@
 #define   MASK_WAKEMEM				REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
-#define GMD_ID_DISPLAY				_MMIO(0x510a0)
-#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
-#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
-#define   GMD_ID_STEP				REG_GENMASK(5, 0)
-
 /* PCH */
 
 #define SDEISR  _MMIO(0xc4000)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 5d156d7cfdbe..d4f91703e8a0 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -191,4 +191,9 @@
 #define     PCODE_MBOX_DOMAIN_NONE		0x0
 #define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
 
+#define GMD_ID_DISPLAY				_MMIO(0x510a0)
+#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
+#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
+#define   GMD_ID_STEP				REG_GENMASK(5, 0)
+
 #endif
-- 
2.50.1

[PATCH 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c

[Uma Shankar]

Make intel_dram.c free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 6 +++++-
 drivers/gpu/drm/i915/display/intel_dram.c         | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h                   | 6 ------
 3 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 8d0badea5cad..11952ce980ac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2987,6 +2987,10 @@ enum skl_power_gate {
 #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
 #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
 
-
+#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
+#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
+#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
+#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
+#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
 
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
index 019a722a38bf..f0e75fa5feb2 100644
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -7,11 +7,12 @@
 
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "i915_drv.h"
-#include "i915_reg.h"
 #include "intel_display_core.h"
 #include "intel_display_utils.h"
+#include "intel_display_regs.h"
 #include "intel_dram.h"
 #include "intel_mchbar_regs.h"
 #include "intel_pcode.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fac24a649d61..c9fb9af1a35c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1005,12 +1005,6 @@
 #define OROM_OFFSET				_MMIO(0x1020c0)
 #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
 
-#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
-#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
-#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
-#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
-#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
-
 #define MTL_MEDIA_GSI_BASE		0x380000
 
 #endif /* _I915_REG_H_ */
-- 
2.50.1

[PATCH 08/19] drm/{i915, xe}: Removed i915_reg.h from intel_display.c

[Uma Shankar]

Move CHICKEN_PIPESL_1 to common header to free intel_display.c
from including i915_reg.h

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h              | 23 --------------------
 include/drm/intel/intel_gmd_common_regs.h    | 23 ++++++++++++++++++++
 3 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9c6d3ecdb589..ad2782d85074 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -45,13 +45,13 @@
 #include <drm/drm_probe_helper.h>
 #include <drm/drm_rect.h>
 #include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "g4x_dp.h"
 #include "g4x_hdmi.h"
 #include "hsw_ips.h"
 #include "i915_config.h"
 #include "i915_drv.h"
-#include "i915_reg.h"
 #include "i9xx_plane.h"
 #include "i9xx_plane_regs.h"
 #include "i9xx_wm.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9fb9af1a35c..e807be4a9962 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -878,29 +878,6 @@
 #define CHICKEN_PAR2_1		_MMIO(0x42090)
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
 
-#define _CHICKEN_PIPESL_1_A	0x420b0
-#define _CHICKEN_PIPESL_1_B	0x420b4
-#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
-#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
-#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
-#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
-#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
-#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
-#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
-#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
-#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
-#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
-#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
-#define   HSW_FBCQ_DIS			REG_BIT(22)
-#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
-#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
-#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
-#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
-#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
-#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
-#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
-#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
-
 #define DISP_ARB_CTL	_MMIO(0x45000)
 #define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
 #define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index d4f91703e8a0..1908c203d54c 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -80,6 +80,29 @@
 #define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
 #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
 
+#define _CHICKEN_PIPESL_1_A	0x420b0
+#define _CHICKEN_PIPESL_1_B	0x420b4
+#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
+#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
+#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
+#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
+#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
+#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
+#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
+#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
+#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
+#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
+#define   HSW_FBCQ_DIS			REG_BIT(22)
+#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
+#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
+#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
+#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
+#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
+#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
+#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
+#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
+
 #define _TRANSA_CHICKEN2	 0xf0064
 #define _TRANSB_CHICKEN2	 0xf1064
 #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-- 
2.50.1

[PATCH 09/19] drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c

[Uma Shankar]

Move GEN2_ISR and some interrupt definitions to common header.
This removes dependency of i915_reg.h from intel_overlay.c.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_overlay.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h              | 36 -------------------
 include/drm/intel/intel_gmd_common_regs.h    | 38 ++++++++++++++++++++
 3 files changed, 39 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 88eb7ae5765c..62026f7f71d3 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -28,6 +28,7 @@
 
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_object_frontbuffer.h"
@@ -37,7 +38,6 @@
 #include "gt/intel_ring.h"
 
 #include "i915_drv.h"
-#include "i915_reg.h"
 #include "intel_color_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e807be4a9962..ec80c21f88b8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -522,42 +522,6 @@
 /* These are all the "old" interrupts */
 #define ILK_BSD_USER_INTERRUPT				(1 << 5)
 
-#define I915_PM_INTERRUPT				(1 << 31)
-#define I915_ISP_INTERRUPT				(1 << 22)
-#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
-#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
-#define I915_MIPIC_INTERRUPT				(1 << 19)
-#define I915_MIPIA_INTERRUPT				(1 << 18)
-#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
-#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
-#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
-#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
-#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
-#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
-#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
-#define I915_HWB_OOM_INTERRUPT				(1 << 13)
-#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
-#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
-#define I915_MISC_INTERRUPT				(1 << 11)
-#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
-#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
-#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
-#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
-#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
-#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
-#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
-#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
-#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
-#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
-#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
-#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
-#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
-#define I915_DEBUG_INTERRUPT				(1 << 2)
-#define I915_WINVALID_INTERRUPT				(1 << 1)
-#define I915_USER_INTERRUPT				(1 << 1)
-#define I915_ASLE_INTERRUPT				(1 << 0)
-#define I915_BSD_USER_INTERRUPT				(1 << 25)
-
 #define GEN6_BSD_RNCID			_MMIO(0x12198)
 
 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 1908c203d54c..6d302fb8aa94 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -219,4 +219,42 @@
 #define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
 #define   GMD_ID_STEP				REG_GENMASK(5, 0)
 
+#define GEN2_ISR	_MMIO(0x20ac)
+
+#define I915_PM_INTERRUPT				(1 << 31)
+#define I915_ISP_INTERRUPT				(1 << 22)
+#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
+#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
+#define I915_MIPIC_INTERRUPT				(1 << 19)
+#define I915_MIPIA_INTERRUPT				(1 << 18)
+#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
+#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
+#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
+#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
+#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
+#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
+#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
+#define I915_HWB_OOM_INTERRUPT				(1 << 13)
+#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
+#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
+#define I915_MISC_INTERRUPT				(1 << 11)
+#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
+#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
+#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
+#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
+#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
+#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
+#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
+#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
+#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
+#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
+#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
+#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
+#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
+#define I915_DEBUG_INTERRUPT				(1 << 2)
+#define I915_WINVALID_INTERRUPT				(1 << 1)
+#define I915_USER_INTERRUPT				(1 << 1)
+#define I915_ASLE_INTERRUPT				(1 << 0)
+#define I915_BSD_USER_INTERRUPT				(1 << 25)
+
 #endif
-- 
2.50.1

[PATCH 10/19] drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c

[Uma Shankar]

Move DE_IRQ_REGS to common header to make g4x_dp.c
free from i915_reg.h dependency.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c            |  2 +-
 .../gpu/drm/i915/display/intel_display_regs.h    |  9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h                  | 16 ----------------
 include/drm/intel/intel_gmd_common_regs.h        |  7 +++++++
 4 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 4cb753177fd8..b2b63e811776 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -8,9 +8,9 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_audio.h"
 #include "intel_backlight.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 11952ce980ac..14fa089d4f5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2993,4 +2993,13 @@ enum skl_power_gate {
 #define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
 #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
 
+#define DEISR   _MMIO(0x44000)
+#define DEIMR   _MMIO(0x44004)
+#define DEIIR   _MMIO(0x44008)
+#define DEIER   _MMIO(0x4400c)
+
+#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
+					      DEIER, \
+					      DEIIR)
+
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ec80c21f88b8..a75853cf58ab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -728,15 +728,6 @@
 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
 
-#define DEISR   _MMIO(0x44000)
-#define DEIMR   _MMIO(0x44004)
-#define DEIIR   _MMIO(0x44008)
-#define DEIER   _MMIO(0x4400c)
-
-#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
-					      DEIER, \
-					      DEIIR)
-
 #define GTISR   _MMIO(0x44010)
 #define GTIMR   _MMIO(0x44014)
 #define GTIIR   _MMIO(0x44018)
@@ -863,13 +854,6 @@
 #define   MASK_WAKEMEM				REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
-/* PCH */
-
-#define SDEISR  _MMIO(0xc4000)
-#define SDEIMR  _MMIO(0xc4004)
-#define SDEIIR  _MMIO(0xc4008)
-#define SDEIER  _MMIO(0xc400c)
-
 /* Icelake PPS_DATA and _ECC DIP Registers.
  * These are available for transcoders B,C and eDP.
  * Adding the _A so as to reuse the _MMIO_TRANS2
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 6d302fb8aa94..cf91c4786e7b 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -257,4 +257,11 @@
 #define I915_ASLE_INTERRUPT				(1 << 0)
 #define I915_BSD_USER_INTERRUPT				(1 << 25)
 
+/* PCH */
+
+#define SDEISR  _MMIO(0xc4000)
+#define SDEIMR  _MMIO(0xc4004)
+#define SDEIIR  _MMIO(0xc4008)
+#define SDEIER  _MMIO(0xc400c)
+
 #endif
-- 
2.50.1

[PATCH 11/19] drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c

[Uma Shankar]

Move FW_BLC_SELF to common header to make i9xx_wm.c
free from i915_reg.h include.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c        |  2 +-
 .../gpu/drm/i915/display/intel_display_regs.h |  7 +++++++
 drivers/gpu/drm/i915/i915_reg.h               | 19 -------------------
 include/drm/intel/intel_gmd_common_regs.h     | 14 ++++++++++++++
 4 files changed, 22 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 167277cd8877..2d5c71ce39a2 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -6,9 +6,9 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "i915_drv.h"
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "i9xx_wm_regs.h"
 #include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 14fa089d4f5b..ecae358c5b0e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3002,4 +3002,11 @@ enum skl_power_gate {
 					      DEIER, \
 					      DEIIR)
 
+#define FW_BLC		_MMIO(0x20d8)
+#define FW_BLC2		_MMIO(0x20dc)
+#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
+#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
+#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
+#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
+
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a75853cf58ab..1ae12cd1911b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -395,24 +395,10 @@
 
 #define GEN2_ERROR_REGS		I915_ERROR_REGS(EMR, EIR)
 
-#define INSTPM	        _MMIO(0x20c0)
-#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
-#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
-					will not assert AGPBUSY# and will only
-					be delivered when out of C3. */
-#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
-#define   INSTPM_TLB_INVALIDATE	(1 << 9)
-#define   INSTPM_SYNC_FLUSH	(1 << 5)
 #define MEM_MODE	_MMIO(0x20cc)
 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
-#define FW_BLC		_MMIO(0x20d8)
-#define FW_BLC2		_MMIO(0x20dc)
-#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
-#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
-#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
-#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
 #define MM_BURST_LENGTH     0x00700000
 #define MM_FIFO_WATERMARK   0x0001F000
 #define LM_BURST_LENGTH     0x00000700
@@ -833,11 +819,6 @@
 #define CHICKEN_PAR2_1		_MMIO(0x42090)
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
 
-#define DISP_ARB_CTL	_MMIO(0x45000)
-#define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
-#define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
-#define   DISP_FBC_WM_DIS		REG_BIT(15)
-
 #define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
 #define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
 #define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index cf91c4786e7b..9cd7f50c5de3 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -264,4 +264,18 @@
 #define SDEIIR  _MMIO(0xc4008)
 #define SDEIER  _MMIO(0xc400c)
 
+#define DISP_ARB_CTL	_MMIO(0x45000)
+#define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
+#define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
+#define   DISP_FBC_WM_DIS		REG_BIT(15)
+
+#define INSTPM	        _MMIO(0x20c0)
+#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
+#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+					will not assert AGPBUSY# and will only
+					be delivered when out of C3. */
+#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
+#define   INSTPM_TLB_INVALIDATE	(1 << 9)
+#define   INSTPM_SYNC_FLUSH	(1 << 5)
+
 #endif
-- 
2.50.1

[PATCH 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c

[Uma Shankar]

Move TRANS_CHICKEN1 reg to common header to make g4x_hdmi.c
free from i915_reg.h dependency.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_hdmi.c   |  2 +-
 drivers/gpu/drm/i915/i915_reg.h           | 12 ------------
 include/drm/intel/intel_gmd_common_regs.h | 13 +++++++++++++
 3 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 8b22447e8e23..c5bff08c7cee 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -6,9 +6,9 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "g4x_hdmi.h"
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_audio.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1ae12cd1911b..77ae9a9ba27a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -835,18 +835,6 @@
 #define   MASK_WAKEMEM				REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
-/* Icelake PPS_DATA and _ECC DIP Registers.
- * These are available for transcoders B,C and eDP.
- * Adding the _A so as to reuse the _MMIO_TRANS2
- * definition, with which it offsets to the right location.
- */
-
-#define _TRANSA_CHICKEN1	 0xf0060
-#define _TRANSB_CHICKEN1	 0xf1060
-#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
-#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
-#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 9cd7f50c5de3..01fffc983e47 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -103,6 +103,19 @@
 #define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
 #define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
 
+/*
+ * Icelake PPS_DATA and _ECC DIP Registers.
+ * These are available for transcoders B,C and eDP.
+ * Adding the _A so as to reuse the _MMIO_TRANS2
+ * definition, with which it offsets to the right location.
+ */
+
+#define _TRANSA_CHICKEN1	 0xf0060
+#define _TRANSB_CHICKEN1	 0xf1060
+#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
+#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
+#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
+
 #define _TRANSA_CHICKEN2	 0xf0064
 #define _TRANSB_CHICKEN2	 0xf1064
 #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-- 
2.50.1

[PATCH 13/19] drm/{i915, xe}: Remove i915_reg.h from intel_rom.c

[Uma Shankar]

Make intel_rom.c free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_rom.c  | 4 ++--
 drivers/gpu/drm/i915/i915_reg.h           | 8 --------
 include/drm/intel/intel_gmd_common_regs.h | 8 ++++++++
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c
index 2f17dc856e7f..2b9801d370a3 100644
--- a/drivers/gpu/drm/i915/display/intel_rom.c
+++ b/drivers/gpu/drm/i915/display/intel_rom.c
@@ -3,9 +3,9 @@
  * Copyright © 2024 Intel Corporation
  */
 
-#include "i915_drv.h"
-#include "i915_reg.h"
+#include <drm/intel/intel_gmd_common_regs.h>
 
+#include "i915_drv.h"
 #include "intel_rom.h"
 #include "intel_uncore.h"
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77ae9a9ba27a..fd3f87f0bcd9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -891,14 +891,6 @@
 #define   SGGI_DIS			REG_BIT(15)
 #define   SGR_DIS			REG_BIT(13)
 
-#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
-#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
-#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
-#define SPI_STATIC_REGIONS			_MMIO(0x102090)
-#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
-#define OROM_OFFSET				_MMIO(0x1020c0)
-#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
-
 #define MTL_MEDIA_GSI_BASE		0x380000
 
 #endif /* _I915_REG_H_ */
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 01fffc983e47..59ea27228935 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -291,4 +291,12 @@
 #define   INSTPM_TLB_INVALIDATE	(1 << 9)
 #define   INSTPM_SYNC_FLUSH	(1 << 5)
 
+#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
+#define SPI_STATIC_REGIONS			_MMIO(0x102090)
+#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
+#define OROM_OFFSET				_MMIO(0x1020c0)
+#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
+
 #endif
-- 
2.50.1

[PATCH 14/19] drm/{i915, xe}: Remove i915_reg.h from intel_psr.c

[Uma Shankar]

Move some chicken registers to common header to make
intel_psr.c free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c  |  2 +-
 drivers/gpu/drm/i915/i915_reg.h           | 26 -----------------------
 include/drm/intel/intel_gmd_common_regs.h | 26 +++++++++++++++++++++++
 3 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 91f4ac86c7ad..79bb2a73ee2f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -28,8 +28,8 @@
 #include <drm/drm_debugfs.h>
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_alpm.h"
 #include "intel_atomic.h"
 #include "intel_crtc.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fd3f87f0bcd9..409c450a208a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -806,35 +806,9 @@
 #define   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	REG_BIT(5)
 #define   CHICKEN3_DGMG_DONE_FIX_DISABLE	REG_BIT(2)
 
-#define CHICKEN_PAR1_1		_MMIO(0x42080)
-#define   IGNORE_KVMR_PIPE_A		REG_BIT(23)
-#define   KBL_ARB_FILL_SPARE_22		REG_BIT(22)
-#define   DIS_RAM_BYPASS_PSR2_MAN_TRACK	REG_BIT(16)
-#define   SKL_DE_COMPRESSED_HASH_MODE	REG_BIT(15)
-#define   HSW_MASK_VBL_TO_PIPE_IN_SRD	REG_BIT(15) /* hsw/bdw */
-#define   FORCE_ARB_IDLE_PLANES		REG_BIT(14)
-#define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
-#define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
-
 #define CHICKEN_PAR2_1		_MMIO(0x42090)
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
 
-#define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
-#define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_A	REG_BIT(23)
-#define   LATENCY_REPORTING_REMOVED(pipe)	_PICK((pipe), \
-						      _LATENCY_REPORTING_REMOVED_PIPE_A, \
-						      _LATENCY_REPORTING_REMOVED_PIPE_B, \
-						      _LATENCY_REPORTING_REMOVED_PIPE_C, \
-						      _LATENCY_REPORTING_REMOVED_PIPE_D)
-#define   ICL_DELAY_PMRSP			REG_BIT(22)
-#define   DISABLE_FLR_SRC			REG_BIT(15)
-#define   MASK_WAKEMEM				REG_BIT(13)
-#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 59ea27228935..13b3e4ad27f4 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -299,4 +299,30 @@
 #define OROM_OFFSET				_MMIO(0x1020c0)
 #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
 
+#define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
+#define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_A	REG_BIT(23)
+#define   LATENCY_REPORTING_REMOVED(pipe)	_PICK((pipe), \
+						      _LATENCY_REPORTING_REMOVED_PIPE_A, \
+						      _LATENCY_REPORTING_REMOVED_PIPE_B, \
+						      _LATENCY_REPORTING_REMOVED_PIPE_C, \
+						      _LATENCY_REPORTING_REMOVED_PIPE_D)
+#define   ICL_DELAY_PMRSP			REG_BIT(22)
+#define   DISABLE_FLR_SRC			REG_BIT(15)
+#define   MASK_WAKEMEM				REG_BIT(13)
+#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
+
+#define CHICKEN_PAR1_1		_MMIO(0x42080)
+#define   IGNORE_KVMR_PIPE_A		REG_BIT(23)
+#define   KBL_ARB_FILL_SPARE_22		REG_BIT(22)
+#define   DIS_RAM_BYPASS_PSR2_MAN_TRACK	REG_BIT(16)
+#define   SKL_DE_COMPRESSED_HASH_MODE	REG_BIT(15)
+#define   HSW_MASK_VBL_TO_PIPE_IN_SRD	REG_BIT(15) /* hsw/bdw */
+#define   FORCE_ARB_IDLE_PLANES		REG_BIT(14)
+#define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
+#define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
+
 #endif
-- 
2.50.1

[PATCH 15/19] drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c

[Uma Shankar]

Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../drm/i915/display/intel_fifo_underrun.c    |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 23 -------------------
 include/drm/intel/intel_gmd_common_regs.h     | 23 +++++++++++++++++++
 3 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index b413b3e871d8..c834be759e40 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -28,8 +28,8 @@
 #include <linux/seq_buf.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_irq.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 409c450a208a..ef2b33bbebee 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -326,29 +326,6 @@
 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
 
-#define GEN7_ERR_INT	_MMIO(0x44040)
-#define   ERR_INT_POISON		(1 << 31)
-#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
-#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
-#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
-#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
-#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
-#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
-#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
-#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
-#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
-#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
-#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
-#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
-#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
-#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
-#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
-#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
-#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
-#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
-#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
-#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
-
 #define FPGA_DBG		_MMIO(0x42300)
 #define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
 
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 13b3e4ad27f4..db7a03699bcb 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -325,4 +325,27 @@
 #define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
 #define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
 
+#define GEN7_ERR_INT	_MMIO(0x44040)
+#define   ERR_INT_POISON		(1 << 31)
+#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
+#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
+#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
+#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
+#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
+#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
+#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
+#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
+#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
+#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
+#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
+#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
+#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
+#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
+#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
+#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
+#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
+#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
+#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
+#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
+
 #endif
-- 
2.50.1

[PATCH 16/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c

[Uma Shankar]

Move VLV_IRQ_REGS to common header to make intel_display_irq.c
free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  |  2 +-
 .../gpu/drm/i915/display/intel_display_regs.h | 28 +++++-----
 drivers/gpu/drm/i915/i915_reg.h               | 52 ------------------
 include/drm/intel/intel_gmd_common_regs.h     | 55 +++++++++++++++++++
 4 files changed, 70 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 9adeebb376b1..206c0d004646 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -5,8 +5,8 @@
 
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "icl_dsi_regs.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index ecae358c5b0e..b433982cee56 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -82,20 +82,6 @@
 #define   DERRMR_PIPEC_VBLANK		(1 << 21)
 #define   DERRMR_PIPEC_HBLANK		(1 << 22)
 
-#define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
-					      VLV_IER, \
-					      VLV_IIR)
-
-#define VLV_EIR		_MMIO(VLV_DISPLAY_BASE + 0x20b0)
-#define VLV_EMR		_MMIO(VLV_DISPLAY_BASE + 0x20b4)
-#define VLV_ESR		_MMIO(VLV_DISPLAY_BASE + 0x20b8)
-#define   VLV_ERROR_GUNIT_TLB_DATA			(1 << 6)
-#define   VLV_ERROR_GUNIT_TLB_PTE			(1 << 5)
-#define   VLV_ERROR_PAGE_TABLE				(1 << 4)
-#define   VLV_ERROR_CLAIM				(1 << 0)
-
-#define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR, VLV_EIR)
-
 #define _MBUS_ABOX0_CTL			0x45038
 #define _MBUS_ABOX1_CTL			0x45048
 #define _MBUS_ABOX2_CTL			0x4504C
@@ -3009,4 +2995,18 @@ enum skl_power_gate {
 #define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
 #define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
 
+#define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
+					      VLV_IER, \
+					      VLV_IIR)
+
+#define VLV_EIR		_MMIO(VLV_DISPLAY_BASE + 0x20b0)
+#define VLV_EMR		_MMIO(VLV_DISPLAY_BASE + 0x20b4)
+#define VLV_ESR		_MMIO(VLV_DISPLAY_BASE + 0x20b8)
+#define   VLV_ERROR_GUNIT_TLB_DATA			(1 << 6)
+#define   VLV_ERROR_GUNIT_TLB_PTE			(1 << 5)
+#define   VLV_ERROR_PAGE_TABLE				(1 << 4)
+#define   VLV_ERROR_CLAIM				(1 << 0)
+
+#define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR, VLV_EIR)
+
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef2b33bbebee..44df40e25e37 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -336,9 +336,6 @@
 
 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
-#define SCPD0		_MMIO(0x209c) /* 915+ only */
-#define  SCPD_FBC_IGNORE_3D			(1 << 6)
-#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
 #define GEN2_IER	_MMIO(0x20a0)
 #define GEN2_IIR	_MMIO(0x20a4)
 #define GEN2_IMR	_MMIO(0x20a8)
@@ -352,13 +349,6 @@
 #define   GINT_DIS		(1 << 22)
 #define   GCFG_DIS		(1 << 8)
 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
-#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
-#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
-#define VLV_PCBR_ADDR_SHIFT	12
 
 #define EIR		_MMIO(0x20b0)
 #define EMR		_MMIO(0x20b4)
@@ -683,11 +673,6 @@
 #define PCH_3DCGDIS1		_MMIO(0x46024)
 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 
-/* Display Internal Timeout Register */
-#define RM_TIMEOUT		_MMIO(0x42060)
-#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
-#define  MMIO_TIMEOUT_US(us)	((us) << 0)
-
 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
 
@@ -700,24 +685,6 @@
 					      GTIER, \
 					      GTIIR)
 
-#define GEN8_MASTER_IRQ			_MMIO(0x44200)
-#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
-#define  GEN8_PCU_IRQ			(1 << 30)
-#define  GEN8_DE_PCH_IRQ		(1 << 23)
-#define  GEN8_DE_MISC_IRQ		(1 << 22)
-#define  GEN8_DE_PORT_IRQ		(1 << 20)
-#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
-#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
-#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
-#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
-#define  GEN8_GT_VECS_IRQ		(1 << 6)
-#define  GEN8_GT_GUC_IRQ		(1 << 5)
-#define  GEN8_GT_PM_IRQ			(1 << 4)
-#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
-#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
-#define  GEN8_GT_BCS_IRQ		(1 << 1)
-#define  GEN8_GT_RCS_IRQ		(1 << 0)
-
 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
@@ -743,25 +710,6 @@
 						      GEN8_PCU_IER, \
 						      GEN8_PCU_IIR)
 
-#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
-#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
-#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
-#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
-#define  GEN11_GU_MISC_GSE	(1 << 27)
-
-#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
-						      GEN11_GU_MISC_IER, \
-						      GEN11_GU_MISC_IIR)
-
-#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
-#define  GEN11_MASTER_IRQ		(1 << 31)
-#define  GEN11_PCU_IRQ			(1 << 30)
-#define  GEN11_GU_MISC_IRQ		(1 << 29)
-#define  GEN11_DISPLAY_IRQ		(1 << 16)
-#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
-#define  GEN11_GT_DW1_IRQ		(1 << 1)
-#define  GEN11_GT_DW0_IRQ		(1 << 0)
-
 #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
 #define   DG1_MSTR_IRQ			REG_BIT(31)
 #define   DG1_MSTR_TILE(t)		REG_BIT(t)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index db7a03699bcb..5a42b473de8a 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -233,6 +233,10 @@
 #define   GMD_ID_STEP				REG_GENMASK(5, 0)
 
 #define GEN2_ISR	_MMIO(0x20ac)
+#define SCPD0		_MMIO(0x209c) /* 915+ only */
+#define  SCPD_FBC_IGNORE_3D			(1 << 6)
+#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
+
 
 #define I915_PM_INTERRUPT				(1 << 31)
 #define I915_ISP_INTERRUPT				(1 << 22)
@@ -348,4 +352,55 @@
 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
 #define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
 
+#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
+#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
+#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
+#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
+#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT	12
+
+#define GEN8_MASTER_IRQ			_MMIO(0x44200)
+#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
+#define  GEN8_PCU_IRQ			(1 << 30)
+#define  GEN8_DE_PCH_IRQ		(1 << 23)
+#define  GEN8_DE_MISC_IRQ		(1 << 22)
+#define  GEN8_DE_PORT_IRQ		(1 << 20)
+#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
+#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
+#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
+#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
+#define  GEN8_GT_VECS_IRQ		(1 << 6)
+#define  GEN8_GT_GUC_IRQ		(1 << 5)
+#define  GEN8_GT_PM_IRQ			(1 << 4)
+#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
+#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
+#define  GEN8_GT_BCS_IRQ		(1 << 1)
+#define  GEN8_GT_RCS_IRQ		(1 << 0)
+
+
+#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
+#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
+#define  GEN11_GU_MISC_GSE	(1 << 27)
+
+#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
+						      GEN11_GU_MISC_IER, \
+						      GEN11_GU_MISC_IIR)
+
+/* Display Internal Timeout Register */
+#define RM_TIMEOUT		_MMIO(0x42060)
+#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
+#define  MMIO_TIMEOUT_US(us)	((us) << 0)
+
+#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
+#define  GEN11_MASTER_IRQ		(1 << 31)
+#define  GEN11_PCU_IRQ			(1 << 30)
+#define  GEN11_GU_MISC_IRQ		(1 << 29)
+#define  GEN11_DISPLAY_IRQ		(1 << 16)
+#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
+#define  GEN11_GT_DW1_IRQ		(1 << 1)
+#define  GEN11_GT_DW0_IRQ		(1 << 0)
+
 #endif
-- 
2.50.1

[PATCH 17/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c

[Uma Shankar]

Make intel_display_power_well.c free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display_regs.h       | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index db185a859133..8a1f1c61c6da 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -6,8 +6,8 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_backlight_regs.h"
 #include "intel_combo_phy.h"
 #include "intel_combo_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index b433982cee56..fce36b34c796 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -916,6 +916,11 @@
 #define   SPRITEA_INVALID_GTT_STATUS			REG_BIT(1)
 #define   PLANEA_INVALID_GTT_STATUS			REG_BIT(0)
 
+#define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
+
+/* Disable display A/B trickle feed */
+#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
+
 #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
 #define  CBR_PND_DEADLINE_DISABLE	(1 << 31)
 #define  CBR_PWM_CLOCK_MUX_SELECT	(1 << 30)
-- 
2.50.1

[PATCH 18/19] drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c

[Uma Shankar]

Move GEN9_CLKGATE_DIS_0 reg to common header to make
intel_modeset_setup.c free from i915_reg.h include.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_modeset_setup.c |  2 +-
 drivers/gpu/drm/i915/i915_reg.h                    | 13 -------------
 include/drm/intel/intel_gmd_common_regs.h          | 13 +++++++++++++
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index d10cbf69a5f8..2502f0076e64 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -10,8 +10,8 @@
 #include <drm/drm_atomic_uapi.h>
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "intel_atomic.h"
 #include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44df40e25e37..e41b80cae1d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -632,19 +632,6 @@
 #define VLV_CLK_CTL2			_MMIO(0x101104)
 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
 
-/*
- * GEN9 clock gating regs
- */
-#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
-#define   DARBF_GATING_DIS		REG_BIT(27)
-#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))
-#define   PWM2_GATING_DIS		REG_BIT(14)
-#define   PWM1_GATING_DIS		REG_BIT(13)
-
-#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
-#define   TGL_VRH_GATING_DIS		REG_BIT(31)
-#define   DPT_GATING_DIS		REG_BIT(22)
-
 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
 #define   PIPEB_LINE_COMPARE_INT_EN			REG_BIT(29)
 #define   PIPEB_HLINE_INT_EN			REG_BIT(28)
diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
index 5a42b473de8a..6faccce3de2a 100644
--- a/include/drm/intel/intel_gmd_common_regs.h
+++ b/include/drm/intel/intel_gmd_common_regs.h
@@ -403,4 +403,17 @@
 #define  GEN11_GT_DW1_IRQ		(1 << 1)
 #define  GEN11_GT_DW0_IRQ		(1 << 0)
 
+/*
+ * GEN9 clock gating regs
+ */
+#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
+#define   DARBF_GATING_DIS		REG_BIT(27)
+#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))
+#define   PWM2_GATING_DIS		REG_BIT(14)
+#define   PWM1_GATING_DIS		REG_BIT(13)
+
+#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
+#define   TGL_VRH_GATING_DIS		REG_BIT(31)
+#define   DPT_GATING_DIS		REG_BIT(22)
+
 #endif
-- 
2.50.1

[PATCH 19/19] drm/{i915, xe}: Removed i915_reg.h from display

[Uma Shankar]

Make display files free from including i915_reg.h.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c               | 2 +-
 drivers/gpu/drm/i915/display/i9xx_plane.c            | 2 +-
 drivers/gpu/drm/i915/display/icl_dsi.c               | 2 +-
 drivers/gpu/drm/i915/display/intel_backlight.c       | 2 +-
 drivers/gpu/drm/i915/display/intel_bw.c              | 2 +-
 drivers/gpu/drm/i915/display/intel_casf.c            | 1 -
 drivers/gpu/drm/i915/display/intel_ddi.c             | 2 +-
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display_power.c   | 2 +-
 drivers/gpu/drm/i915/display/intel_display_wa.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_dmc.c             | 2 +-
 drivers/gpu/drm/i915/display/intel_fdi.c             | 2 +-
 drivers/gpu/drm/i915/display/intel_hdcp.c            | 2 +-
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_lt_phy.c          | 2 +-
 drivers/gpu/drm/i915/display/intel_pps.c             | 2 +-
 drivers/gpu/drm/i915/display/intel_tc.c              | 2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c         | 2 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c               | 2 +-
 19 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 008d339d5c21..290d54fe87e4 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -6,9 +6,9 @@
 #include <linux/debugfs.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "intel_color_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1fecf178906..7042e15489ed 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -9,8 +9,8 @@
 #include <drm/drm_blend.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "i9xx_plane.h"
 #include "i9xx_plane_regs.h"
 #include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index dac781f54661..0052a4bb7ec9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -33,8 +33,8 @@
 #include <drm/drm_mipi_dsi.h>
 #include <drm/drm_print.h>
 #include <drm/drm_probe_helper.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "icl_dsi.h"
 #include "icl_dsi_regs.h"
 #include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index a68fdbd2acb9..812bfad3905c 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -11,8 +11,8 @@
 
 #include <drm/drm_file.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_backlight.h"
 #include "intel_backlight_regs.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index d27835ed49c2..71984795dfcb 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -5,9 +5,9 @@
 
 #include <drm/drm_atomic_state_helper.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "i915_drv.h"
-#include "i915_reg.h"
 #include "intel_bw.h"
 #include "intel_crtc.h"
 #include "intel_display_core.h"
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index 95339b496f24..d18a1ecbb101 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -3,7 +3,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_casf.h"
 #include "intel_casf_regs.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index cb91d07cdaa6..745eb83dfa03 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -33,8 +33,8 @@
 #include <drm/display/drm_scdc_helper.h>
 #include <drm/drm_print.h>
 #include <drm/drm_privacy_screen_consumer.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "icl_dsi.h"
 #include "intel_alpm.h"
 #include "intel_audio.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index aba13e8a9051..07cb56f80e88 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -13,9 +13,9 @@
 #include <drm/drm_file.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "i9xx_wm_regs.h"
 #include "intel_alpm.h"
 #include "intel_bo.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9f323c39d798..7bb187448e19 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -7,9 +7,9 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "i915_drv.h"
-#include "i915_reg.h"
 #include "intel_backlight_regs.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index a00af39f7538..76983ca5bed7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -4,8 +4,8 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_core.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 2fb6fec6dc99..171baad41d55 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -25,11 +25,11 @@
 #include <linux/debugfs.h>
 #include <linux/firmware.h>
 #include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include <drm/drm_file.h>
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 5bb0090dd5ed..5eb880747955 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -7,8 +7,8 @@
 
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_crtc.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 7114fc405c29..db15bf1980c0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -17,8 +17,8 @@
 #include <drm/display/drm_hdcp_helper.h>
 #include <drm/drm_print.h>
 #include <drm/intel/i915_component.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_connector.h"
 #include "intel_de.h"
 #include "intel_display_jiffies.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 82c39e4ffa37..334f27c3dccb 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -4,8 +4,8 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_irq.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 939c8975fd4c..af1e02184619 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -4,8 +4,8 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b217ec7aa758..6ae5600fc4d1 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -7,9 +7,9 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 064f572bbc85..5784d5d5132d 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -6,8 +6,8 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index a6aab79812e5..410289b3fadd 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -7,8 +7,8 @@
 
 #include <drm/drm_blend.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "intel_atomic.h"
 #include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index d705af3bf8ba..c2501d0268dc 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -32,8 +32,8 @@
 #include <drm/drm_mipi_dsi.h>
 #include <drm/drm_print.h>
 #include <drm/drm_probe_helper.h>
+#include <drm/intel/intel_gmd_common_regs.h>
 
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_backlight.h"
 #include "intel_connector.h"
-- 
2.50.1

✗ CI.checkpatch: warning for Make Display free from i915_reg.h

[Patchwork]

== Series Details ==

Series: Make Display free from i915_reg.h
URL   : https://patchwork.freedesktop.org/series/159130/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
8f50e69d0ce3656564bbdf8b3e213d61470d463f
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit f183716025ad09ab677d08b46ac3f748049b691c
Author: Uma Shankar <uma.shankar@intel.com>
Date:   Wed Dec 17 11:52:09 2025 +0530

    drm/{i915, xe}: Removed i915_reg.h from display
    
    Make display files free from including i915_reg.h.
    
    Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch 2eb2f8746a879f1c0e4c56b715c179424dafd8e0 drm-intel
9ad12c7fa9d3 drm/{i915, xe}: Extract common registers into a separate file
-:57: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#57: 
new file mode 100644

-:74: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#74: FILE: include/drm/intel/intel_gmd_common_regs.h:13:
+#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */

total: 0 errors, 2 warnings, 0 checks, 50 lines checked
753edd94e038 drm/{i915, xe}: Extract South chicken registers
cbd55bb40782 drm/{i915, xe}: Extract display interrupt definitions
-:52: CHECK:LINE_SPACING: Please don't use multiple blank lines
#52: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:1369:
+
+

total: 0 errors, 0 warnings, 1 checks, 88 lines checked
7b1300b97fe1 drm/{i915, xe}: Extract DSPCLK_GATE_D
c36489116648 drm/{i915, xe}: Extract pcode definitions
-:191: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#191: FILE: include/drm/intel/intel_gmd_common_regs.h:139:
+#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))

-:219: ERROR:CODE_INDENT: code indent should use tabs where possible
#219: FILE: include/drm/intel/intel_gmd_common_regs.h:167:
+            /* See also IPS_CTL */$

total: 1 errors, 1 warnings, 0 checks, 221 lines checked
b0c38f023894 drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c
84db1ed76918 drm/{i915, xe}: Remove i915_reg.h from intel_dram.c
66fdc87f7e27 drm/{i915, xe}: Removed i915_reg.h from intel_display.c
3ad63a27f4fe drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c
5868b3e36460 drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c
00187d159475 drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c
-:99: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#99: FILE: include/drm/intel/intel_gmd_common_regs.h:275:
+#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+					will not assert AGPBUSY# and will only

-:100: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#100: FILE: include/drm/intel/intel_gmd_common_regs.h:276:
+					be delivered when out of C3. */

total: 0 errors, 2 warnings, 0 checks, 74 lines checked
cdf3d85164be drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
ac94949407c3 drm/{i915, xe}: Remove i915_reg.h from intel_rom.c
1bf5225d739c drm/{i915, xe}: Remove i915_reg.h from intel_psr.c
76cf1faf87ba drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c
e3727aaae98d drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c
-:205: CHECK:LINE_SPACING: Please don't use multiple blank lines
#205: FILE: include/drm/intel/intel_gmd_common_regs.h:381:
+
+

total: 0 errors, 0 warnings, 1 checks, 194 lines checked
04349bae6aa4 drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c
fd6451b235b7 drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c
f183716025ad drm/{i915, xe}: Removed i915_reg.h from display

✓ CI.KUnit: success for Make Display free from i915_reg.h

[Patchwork]

== Series Details ==

Series: Make Display free from i915_reg.h
URL   : https://patchwork.freedesktop.org/series/159130/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:26:20] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:26:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[06:27:03] Starting KUnit Kernel (1/1)...
[06:27:03] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:27:04] ================== guc_buf (11 subtests) ===================
[06:27:04] [PASSED] test_smallest
[06:27:04] [PASSED] test_largest
[06:27:04] [PASSED] test_granular
[06:27:04] [PASSED] test_unique
[06:27:04] [PASSED] test_overlap
[06:27:04] [PASSED] test_reusable
[06:27:04] [PASSED] test_too_big
[06:27:04] [PASSED] test_flush
[06:27:04] [PASSED] test_lookup
[06:27:04] [PASSED] test_data
[06:27:04] [PASSED] test_class
[06:27:04] ===================== [PASSED] guc_buf =====================
[06:27:04] =================== guc_dbm (7 subtests) ===================
[06:27:04] [PASSED] test_empty
[06:27:04] [PASSED] test_default
[06:27:04] ======================== test_size  ========================
[06:27:04] [PASSED] 4
[06:27:04] [PASSED] 8
[06:27:04] [PASSED] 32
[06:27:04] [PASSED] 256
[06:27:04] ==================== [PASSED] test_size ====================
[06:27:04] ======================= test_reuse  ========================
[06:27:04] [PASSED] 4
[06:27:04] [PASSED] 8
[06:27:04] [PASSED] 32
[06:27:04] [PASSED] 256
[06:27:04] =================== [PASSED] test_reuse ====================
[06:27:04] =================== test_range_overlap  ====================
[06:27:04] [PASSED] 4
[06:27:04] [PASSED] 8
[06:27:04] [PASSED] 32
[06:27:04] [PASSED] 256
[06:27:04] =============== [PASSED] test_range_overlap ================
[06:27:04] =================== test_range_compact  ====================
[06:27:04] [PASSED] 4
[06:27:04] [PASSED] 8
[06:27:04] [PASSED] 32
[06:27:04] [PASSED] 256
[06:27:04] =============== [PASSED] test_range_compact ================
[06:27:04] ==================== test_range_spare  =====================
[06:27:04] [PASSED] 4
[06:27:04] [PASSED] 8
[06:27:04] [PASSED] 32
[06:27:04] [PASSED] 256
[06:27:04] ================ [PASSED] test_range_spare =================
[06:27:04] ===================== [PASSED] guc_dbm =====================
[06:27:04] =================== guc_idm (6 subtests) ===================
[06:27:04] [PASSED] bad_init
[06:27:04] [PASSED] no_init
[06:27:04] [PASSED] init_fini
[06:27:04] [PASSED] check_used
[06:27:04] [PASSED] check_quota
[06:27:04] [PASSED] check_all
[06:27:04] ===================== [PASSED] guc_idm =====================
[06:27:04] ================== no_relay (3 subtests) ===================
[06:27:04] [PASSED] xe_drops_guc2pf_if_not_ready
[06:27:04] [PASSED] xe_drops_guc2vf_if_not_ready
[06:27:04] [PASSED] xe_rejects_send_if_not_ready
[06:27:04] ==================== [PASSED] no_relay =====================
[06:27:04] ================== pf_relay (14 subtests) ==================
[06:27:04] [PASSED] pf_rejects_guc2pf_too_short
[06:27:04] [PASSED] pf_rejects_guc2pf_too_long
[06:27:04] [PASSED] pf_rejects_guc2pf_no_payload
[06:27:04] [PASSED] pf_fails_no_payload
[06:27:04] [PASSED] pf_fails_bad_origin
[06:27:04] [PASSED] pf_fails_bad_type
[06:27:04] [PASSED] pf_txn_reports_error
[06:27:04] [PASSED] pf_txn_sends_pf2guc
[06:27:04] [PASSED] pf_sends_pf2guc
[06:27:04] [SKIPPED] pf_loopback_nop
[06:27:04] [SKIPPED] pf_loopback_echo
[06:27:04] [SKIPPED] pf_loopback_fail
[06:27:04] [SKIPPED] pf_loopback_busy
[06:27:04] [SKIPPED] pf_loopback_retry
[06:27:04] ==================== [PASSED] pf_relay =====================
[06:27:04] ================== vf_relay (3 subtests) ===================
[06:27:04] [PASSED] vf_rejects_guc2vf_too_short
[06:27:04] [PASSED] vf_rejects_guc2vf_too_long
[06:27:04] [PASSED] vf_rejects_guc2vf_no_payload
[06:27:04] ==================== [PASSED] vf_relay =====================
[06:27:04] ================ pf_gt_config (6 subtests) =================
[06:27:04] [PASSED] fair_contexts_1vf
[06:27:04] [PASSED] fair_doorbells_1vf
[06:27:04] [PASSED] fair_ggtt_1vf
[06:27:04] ====================== fair_contexts  ======================
[06:27:04] [PASSED] 1 VF
[06:27:04] [PASSED] 2 VFs
[06:27:04] [PASSED] 3 VFs
[06:27:04] [PASSED] 4 VFs
[06:27:04] [PASSED] 5 VFs
[06:27:04] [PASSED] 6 VFs
[06:27:04] [PASSED] 7 VFs
[06:27:04] [PASSED] 8 VFs
[06:27:04] [PASSED] 9 VFs
[06:27:04] [PASSED] 10 VFs
[06:27:04] [PASSED] 11 VFs
[06:27:04] [PASSED] 12 VFs
[06:27:04] [PASSED] 13 VFs
[06:27:04] [PASSED] 14 VFs
[06:27:04] [PASSED] 15 VFs
[06:27:04] [PASSED] 16 VFs
[06:27:04] [PASSED] 17 VFs
[06:27:04] [PASSED] 18 VFs
[06:27:04] [PASSED] 19 VFs
[06:27:04] [PASSED] 20 VFs
[06:27:04] [PASSED] 21 VFs
[06:27:04] [PASSED] 22 VFs
[06:27:04] [PASSED] 23 VFs
[06:27:04] [PASSED] 24 VFs
[06:27:04] [PASSED] 25 VFs
[06:27:04] [PASSED] 26 VFs
[06:27:04] [PASSED] 27 VFs
[06:27:04] [PASSED] 28 VFs
[06:27:04] [PASSED] 29 VFs
[06:27:04] [PASSED] 30 VFs
[06:27:04] [PASSED] 31 VFs
[06:27:04] [PASSED] 32 VFs
[06:27:04] [PASSED] 33 VFs
[06:27:04] [PASSED] 34 VFs
[06:27:04] [PASSED] 35 VFs
[06:27:04] [PASSED] 36 VFs
[06:27:04] [PASSED] 37 VFs
[06:27:04] [PASSED] 38 VFs
[06:27:04] [PASSED] 39 VFs
[06:27:04] [PASSED] 40 VFs
[06:27:04] [PASSED] 41 VFs
[06:27:04] [PASSED] 42 VFs
[06:27:04] [PASSED] 43 VFs
[06:27:04] [PASSED] 44 VFs
[06:27:04] [PASSED] 45 VFs
[06:27:04] [PASSED] 46 VFs
[06:27:04] [PASSED] 47 VFs
[06:27:04] [PASSED] 48 VFs
[06:27:04] [PASSED] 49 VFs
[06:27:04] [PASSED] 50 VFs
[06:27:04] [PASSED] 51 VFs
[06:27:04] [PASSED] 52 VFs
[06:27:04] [PASSED] 53 VFs
[06:27:04] [PASSED] 54 VFs
[06:27:04] [PASSED] 55 VFs
[06:27:04] [PASSED] 56 VFs
[06:27:04] [PASSED] 57 VFs
[06:27:04] [PASSED] 58 VFs
[06:27:04] [PASSED] 59 VFs
[06:27:04] [PASSED] 60 VFs
[06:27:04] [PASSED] 61 VFs
[06:27:04] [PASSED] 62 VFs
[06:27:04] [PASSED] 63 VFs
[06:27:04] ================== [PASSED] fair_contexts ==================
[06:27:04] ===================== fair_doorbells  ======================
[06:27:04] [PASSED] 1 VF
[06:27:04] [PASSED] 2 VFs
[06:27:04] [PASSED] 3 VFs
[06:27:04] [PASSED] 4 VFs
[06:27:04] [PASSED] 5 VFs
[06:27:04] [PASSED] 6 VFs
[06:27:04] [PASSED] 7 VFs
[06:27:04] [PASSED] 8 VFs
[06:27:04] [PASSED] 9 VFs
[06:27:04] [PASSED] 10 VFs
[06:27:04] [PASSED] 11 VFs
[06:27:04] [PASSED] 12 VFs
[06:27:04] [PASSED] 13 VFs
[06:27:04] [PASSED] 14 VFs
[06:27:04] [PASSED] 15 VFs
[06:27:04] [PASSED] 16 VFs
[06:27:04] [PASSED] 17 VFs
[06:27:04] [PASSED] 18 VFs
[06:27:04] [PASSED] 19 VFs
[06:27:04] [PASSED] 20 VFs
[06:27:04] [PASSED] 21 VFs
[06:27:04] [PASSED] 22 VFs
[06:27:04] [PASSED] 23 VFs
[06:27:04] [PASSED] 24 VFs
[06:27:04] [PASSED] 25 VFs
[06:27:04] [PASSED] 26 VFs
[06:27:04] [PASSED] 27 VFs
[06:27:04] [PASSED] 28 VFs
[06:27:04] [PASSED] 29 VFs
[06:27:04] [PASSED] 30 VFs
[06:27:04] [PASSED] 31 VFs
[06:27:04] [PASSED] 32 VFs
[06:27:04] [PASSED] 33 VFs
[06:27:04] [PASSED] 34 VFs
[06:27:04] [PASSED] 35 VFs
[06:27:04] [PASSED] 36 VFs
[06:27:04] [PASSED] 37 VFs
[06:27:04] [PASSED] 38 VFs
[06:27:04] [PASSED] 39 VFs
[06:27:04] [PASSED] 40 VFs
[06:27:04] [PASSED] 41 VFs
[06:27:04] [PASSED] 42 VFs
[06:27:04] [PASSED] 43 VFs
[06:27:04] [PASSED] 44 VFs
[06:27:04] [PASSED] 45 VFs
[06:27:04] [PASSED] 46 VFs
[06:27:04] [PASSED] 47 VFs
[06:27:04] [PASSED] 48 VFs
[06:27:04] [PASSED] 49 VFs
[06:27:04] [PASSED] 50 VFs
[06:27:04] [PASSED] 51 VFs
[06:27:04] [PASSED] 52 VFs
[06:27:04] [PASSED] 53 VFs
[06:27:04] [PASSED] 54 VFs
[06:27:04] [PASSED] 55 VFs
[06:27:04] [PASSED] 56 VFs
[06:27:04] [PASSED] 57 VFs
[06:27:04] [PASSED] 58 VFs
[06:27:04] [PASSED] 59 VFs
[06:27:04] [PASSED] 60 VFs
[06:27:04] [PASSED] 61 VFs
[06:27:04] [PASSED] 62 VFs
[06:27:04] [PASSED] 63 VFs
[06:27:04] ================= [PASSED] fair_doorbells ==================
[06:27:04] ======================== fair_ggtt  ========================
[06:27:04] [PASSED] 1 VF
[06:27:04] [PASSED] 2 VFs
[06:27:04] [PASSED] 3 VFs
[06:27:04] [PASSED] 4 VFs
[06:27:04] [PASSED] 5 VFs
[06:27:04] [PASSED] 6 VFs
[06:27:04] [PASSED] 7 VFs
[06:27:04] [PASSED] 8 VFs
[06:27:04] [PASSED] 9 VFs
[06:27:04] [PASSED] 10 VFs
[06:27:04] [PASSED] 11 VFs
[06:27:04] [PASSED] 12 VFs
[06:27:04] [PASSED] 13 VFs
[06:27:04] [PASSED] 14 VFs
[06:27:04] [PASSED] 15 VFs
[06:27:04] [PASSED] 16 VFs
[06:27:04] [PASSED] 17 VFs
[06:27:04] [PASSED] 18 VFs
[06:27:04] [PASSED] 19 VFs
[06:27:04] [PASSED] 20 VFs
[06:27:04] [PASSED] 21 VFs
[06:27:04] [PASSED] 22 VFs
[06:27:04] [PASSED] 23 VFs
[06:27:04] [PASSED] 24 VFs
[06:27:04] [PASSED] 25 VFs
[06:27:04] [PASSED] 26 VFs
[06:27:04] [PASSED] 27 VFs
[06:27:04] [PASSED] 28 VFs
[06:27:04] [PASSED] 29 VFs
[06:27:04] [PASSED] 30 VFs
[06:27:04] [PASSED] 31 VFs
[06:27:04] [PASSED] 32 VFs
[06:27:04] [PASSED] 33 VFs
[06:27:04] [PASSED] 34 VFs
[06:27:04] [PASSED] 35 VFs
[06:27:04] [PASSED] 36 VFs
[06:27:04] [PASSED] 37 VFs
[06:27:04] [PASSED] 38 VFs
[06:27:04] [PASSED] 39 VFs
[06:27:04] [PASSED] 40 VFs
[06:27:04] [PASSED] 41 VFs
[06:27:04] [PASSED] 42 VFs
[06:27:04] [PASSED] 43 VFs
[06:27:04] [PASSED] 44 VFs
[06:27:04] [PASSED] 45 VFs
[06:27:04] [PASSED] 46 VFs
[06:27:04] [PASSED] 47 VFs
[06:27:04] [PASSED] 48 VFs
[06:27:04] [PASSED] 49 VFs
[06:27:04] [PASSED] 50 VFs
[06:27:04] [PASSED] 51 VFs
[06:27:04] [PASSED] 52 VFs
[06:27:04] [PASSED] 53 VFs
[06:27:04] [PASSED] 54 VFs
[06:27:04] [PASSED] 55 VFs
[06:27:04] [PASSED] 56 VFs
[06:27:04] [PASSED] 57 VFs
[06:27:04] [PASSED] 58 VFs
[06:27:04] [PASSED] 59 VFs
[06:27:04] [PASSED] 60 VFs
[06:27:04] [PASSED] 61 VFs
[06:27:04] [PASSED] 62 VFs
[06:27:04] [PASSED] 63 VFs
[06:27:04] ==================== [PASSED] fair_ggtt ====================
[06:27:04] ================== [PASSED] pf_gt_config ===================
[06:27:04] ===================== lmtt (1 subtest) =====================
[06:27:04] ======================== test_ops  =========================
[06:27:04] [PASSED] 2-level
[06:27:04] [PASSED] multi-level
[06:27:04] ==================== [PASSED] test_ops =====================
[06:27:04] ====================== [PASSED] lmtt =======================
[06:27:04] ================= pf_service (11 subtests) =================
[06:27:04] [PASSED] pf_negotiate_any
[06:27:04] [PASSED] pf_negotiate_base_match
[06:27:04] [PASSED] pf_negotiate_base_newer
[06:27:04] [PASSED] pf_negotiate_base_next
[06:27:04] [SKIPPED] pf_negotiate_base_older
[06:27:04] [PASSED] pf_negotiate_base_prev
[06:27:04] [PASSED] pf_negotiate_latest_match
[06:27:04] [PASSED] pf_negotiate_latest_newer
[06:27:04] [PASSED] pf_negotiate_latest_next
[06:27:04] [SKIPPED] pf_negotiate_latest_older
[06:27:04] [SKIPPED] pf_negotiate_latest_prev
[06:27:04] =================== [PASSED] pf_service ====================
[06:27:04] ================= xe_guc_g2g (2 subtests) ==================
[06:27:04] ============== xe_live_guc_g2g_kunit_default  ==============
[06:27:04] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[06:27:04] ============== xe_live_guc_g2g_kunit_allmem  ===============
[06:27:04] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[06:27:04] =================== [SKIPPED] xe_guc_g2g ===================
[06:27:04] =================== xe_mocs (2 subtests) ===================
[06:27:04] ================ xe_live_mocs_kernel_kunit  ================
[06:27:04] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:27:04] ================ xe_live_mocs_reset_kunit  =================
[06:27:04] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:27:04] ==================== [SKIPPED] xe_mocs =====================
[06:27:04] ================= xe_migrate (2 subtests) ==================
[06:27:04] ================= xe_migrate_sanity_kunit  =================
[06:27:04] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:27:04] ================== xe_validate_ccs_kunit  ==================
[06:27:04] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:27:04] =================== [SKIPPED] xe_migrate ===================
[06:27:04] ================== xe_dma_buf (1 subtest) ==================
[06:27:04] ==================== xe_dma_buf_kunit  =====================
[06:27:04] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:27:04] =================== [SKIPPED] xe_dma_buf ===================
[06:27:04] ================= xe_bo_shrink (1 subtest) =================
[06:27:04] =================== xe_bo_shrink_kunit  ====================
[06:27:04] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:27:04] ================== [SKIPPED] xe_bo_shrink ==================
[06:27:04] ==================== xe_bo (2 subtests) ====================
[06:27:04] ================== xe_ccs_migrate_kunit  ===================
[06:27:04] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:27:04] ==================== xe_bo_evict_kunit  ====================
[06:27:04] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:27:04] ===================== [SKIPPED] xe_bo ======================
[06:27:04] ==================== args (11 subtests) ====================
[06:27:04] [PASSED] count_args_test
[06:27:04] [PASSED] call_args_example
[06:27:04] [PASSED] call_args_test
[06:27:04] [PASSED] drop_first_arg_example
[06:27:04] [PASSED] drop_first_arg_test
[06:27:04] [PASSED] first_arg_example
[06:27:04] [PASSED] first_arg_test
[06:27:04] [PASSED] last_arg_example
[06:27:04] [PASSED] last_arg_test
[06:27:04] [PASSED] pick_arg_example
[06:27:04] [PASSED] sep_comma_example
[06:27:04] ====================== [PASSED] args =======================
[06:27:04] =================== xe_pci (3 subtests) ====================
[06:27:04] ==================== check_graphics_ip  ====================
[06:27:04] [PASSED] 12.00 Xe_LP
[06:27:04] [PASSED] 12.10 Xe_LP+
[06:27:04] [PASSED] 12.55 Xe_HPG
[06:27:04] [PASSED] 12.60 Xe_HPC
[06:27:04] [PASSED] 12.70 Xe_LPG
[06:27:04] [PASSED] 12.71 Xe_LPG
[06:27:04] [PASSED] 12.74 Xe_LPG+
[06:27:04] [PASSED] 20.01 Xe2_HPG
[06:27:04] [PASSED] 20.02 Xe2_HPG
[06:27:04] [PASSED] 20.04 Xe2_LPG
[06:27:04] [PASSED] 30.00 Xe3_LPG
[06:27:04] [PASSED] 30.01 Xe3_LPG
[06:27:04] [PASSED] 30.03 Xe3_LPG
[06:27:04] [PASSED] 30.04 Xe3_LPG
[06:27:04] [PASSED] 30.05 Xe3_LPG
[06:27:04] [PASSED] 35.11 Xe3p_XPC
[06:27:04] ================ [PASSED] check_graphics_ip ================
[06:27:04] ===================== check_media_ip  ======================
[06:27:04] [PASSED] 12.00 Xe_M
[06:27:04] [PASSED] 12.55 Xe_HPM
[06:27:04] [PASSED] 13.00 Xe_LPM+
[06:27:04] [PASSED] 13.01 Xe2_HPM
[06:27:04] [PASSED] 20.00 Xe2_LPM
[06:27:04] [PASSED] 30.00 Xe3_LPM
[06:27:04] [PASSED] 30.02 Xe3_LPM
[06:27:04] [PASSED] 35.00 Xe3p_LPM
[06:27:04] [PASSED] 35.03 Xe3p_HPM
[06:27:04] ================= [PASSED] check_media_ip ==================
[06:27:04] =================== check_platform_desc  ===================
[06:27:04] [PASSED] 0x9A60 (TIGERLAKE)
[06:27:04] [PASSED] 0x9A68 (TIGERLAKE)
[06:27:04] [PASSED] 0x9A70 (TIGERLAKE)
[06:27:04] [PASSED] 0x9A40 (TIGERLAKE)
[06:27:04] [PASSED] 0x9A49 (TIGERLAKE)
[06:27:04] [PASSED] 0x9A59 (TIGERLAKE)
[06:27:04] [PASSED] 0x9A78 (TIGERLAKE)
[06:27:04] [PASSED] 0x9AC0 (TIGERLAKE)
[06:27:04] [PASSED] 0x9AC9 (TIGERLAKE)
[06:27:04] [PASSED] 0x9AD9 (TIGERLAKE)
[06:27:04] [PASSED] 0x9AF8 (TIGERLAKE)
[06:27:04] [PASSED] 0x4C80 (ROCKETLAKE)
[06:27:04] [PASSED] 0x4C8A (ROCKETLAKE)
[06:27:04] [PASSED] 0x4C8B (ROCKETLAKE)
[06:27:04] [PASSED] 0x4C8C (ROCKETLAKE)
[06:27:04] [PASSED] 0x4C90 (ROCKETLAKE)
[06:27:04] [PASSED] 0x4C9A (ROCKETLAKE)
[06:27:04] [PASSED] 0x4680 (ALDERLAKE_S)
[06:27:04] [PASSED] 0x4682 (ALDERLAKE_S)
[06:27:04] [PASSED] 0x4688 (ALDERLAKE_S)
[06:27:04] [PASSED] 0x468A (ALDERLAKE_S)
[06:27:04] [PASSED] 0x468B (ALDERLAKE_S)
[06:27:04] [PASSED] 0x4690 (ALDERLAKE_S)
[06:27:04] [PASSED] 0x4692 (ALDERLAKE_S)
[06:27:04] [PASSED] 0x4693 (ALDERLAKE_S)
[06:27:04] [PASSED] 0x46A0 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46A1 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46A2 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46A3 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46A6 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46A8 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46AA (ALDERLAKE_P)
[06:27:04] [PASSED] 0x462A (ALDERLAKE_P)
[06:27:04] [PASSED] 0x4626 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x4628 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[06:27:04] [PASSED] 0x46B1 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46B2 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46B3 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46C0 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46C1 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46C2 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46C3 (ALDERLAKE_P)
[06:27:04] [PASSED] 0x46D0 (ALDERLAKE_N)
[06:27:04] [PASSED] 0x46D1 (ALDERLAKE_N)
[06:27:04] [PASSED] 0x46D2 (ALDERLAKE_N)
[06:27:04] [PASSED] 0x46D3 (ALDERLAKE_N)
[06:27:04] [PASSED] 0x46D4 (ALDERLAKE_N)
[06:27:04] [PASSED] 0xA721 (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA7A1 (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA7A9 (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA7AC (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA7AD (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA720 (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA7A0 (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA7A8 (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA7AA (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA7AB (ALDERLAKE_P)
[06:27:04] [PASSED] 0xA780 (ALDERLAKE_S)
[06:27:04] [PASSED] 0xA781 (ALDERLAKE_S)
[06:27:04] [PASSED] 0xA782 (ALDERLAKE_S)
[06:27:04] [PASSED] 0xA783 (ALDERLAKE_S)
[06:27:04] [PASSED] 0xA788 (ALDERLAKE_S)
[06:27:04] [PASSED] 0xA789 (ALDERLAKE_S)
[06:27:04] [PASSED] 0xA78A (ALDERLAKE_S)
[06:27:04] [PASSED] 0xA78B (ALDERLAKE_S)
[06:27:04] [PASSED] 0x4905 (DG1)
[06:27:04] [PASSED] 0x4906 (DG1)
[06:27:04] [PASSED] 0x4907 (DG1)
[06:27:04] [PASSED] 0x4908 (DG1)
[06:27:04] [PASSED] 0x4909 (DG1)
[06:27:04] [PASSED] 0x56C0 (DG2)
[06:27:04] [PASSED] 0x56C2 (DG2)
[06:27:04] [PASSED] 0x56C1 (DG2)
[06:27:04] [PASSED] 0x7D51 (METEORLAKE)
[06:27:04] [PASSED] 0x7DD1 (METEORLAKE)
[06:27:04] [PASSED] 0x7D41 (METEORLAKE)
[06:27:04] [PASSED] 0x7D67 (METEORLAKE)
[06:27:04] [PASSED] 0xB640 (METEORLAKE)
[06:27:04] [PASSED] 0x56A0 (DG2)
[06:27:04] [PASSED] 0x56A1 (DG2)
[06:27:04] [PASSED] 0x56A2 (DG2)
[06:27:04] [PASSED] 0x56BE (DG2)
[06:27:04] [PASSED] 0x56BF (DG2)
[06:27:04] [PASSED] 0x5690 (DG2)
[06:27:04] [PASSED] 0x5691 (DG2)
[06:27:04] [PASSED] 0x5692 (DG2)
[06:27:04] [PASSED] 0x56A5 (DG2)
[06:27:04] [PASSED] 0x56A6 (DG2)
[06:27:04] [PASSED] 0x56B0 (DG2)
[06:27:04] [PASSED] 0x56B1 (DG2)
[06:27:04] [PASSED] 0x56BA (DG2)
[06:27:04] [PASSED] 0x56BB (DG2)
[06:27:04] [PASSED] 0x56BC (DG2)
[06:27:04] [PASSED] 0x56BD (DG2)
[06:27:04] [PASSED] 0x5693 (DG2)
[06:27:04] [PASSED] 0x5694 (DG2)
[06:27:04] [PASSED] 0x5695 (DG2)
[06:27:04] [PASSED] 0x56A3 (DG2)
[06:27:04] [PASSED] 0x56A4 (DG2)
[06:27:04] [PASSED] 0x56B2 (DG2)
[06:27:04] [PASSED] 0x56B3 (DG2)
[06:27:04] [PASSED] 0x5696 (DG2)
[06:27:04] [PASSED] 0x5697 (DG2)
[06:27:04] [PASSED] 0xB69 (PVC)
[06:27:04] [PASSED] 0xB6E (PVC)
[06:27:04] [PASSED] 0xBD4 (PVC)
[06:27:04] [PASSED] 0xBD5 (PVC)
[06:27:04] [PASSED] 0xBD6 (PVC)
[06:27:04] [PASSED] 0xBD7 (PVC)
[06:27:04] [PASSED] 0xBD8 (PVC)
[06:27:04] [PASSED] 0xBD9 (PVC)
[06:27:04] [PASSED] 0xBDA (PVC)
[06:27:04] [PASSED] 0xBDB (PVC)
[06:27:04] [PASSED] 0xBE0 (PVC)
[06:27:04] [PASSED] 0xBE1 (PVC)
[06:27:04] [PASSED] 0xBE5 (PVC)
[06:27:04] [PASSED] 0x7D40 (METEORLAKE)
[06:27:04] [PASSED] 0x7D45 (METEORLAKE)
[06:27:04] [PASSED] 0x7D55 (METEORLAKE)
[06:27:04] [PASSED] 0x7D60 (METEORLAKE)
[06:27:04] [PASSED] 0x7DD5 (METEORLAKE)
[06:27:04] [PASSED] 0x6420 (LUNARLAKE)
[06:27:04] [PASSED] 0x64A0 (LUNARLAKE)
[06:27:04] [PASSED] 0x64B0 (LUNARLAKE)
[06:27:04] [PASSED] 0xE202 (BATTLEMAGE)
[06:27:04] [PASSED] 0xE209 (BATTLEMAGE)
[06:27:04] [PASSED] 0xE20B (BATTLEMAGE)
[06:27:04] [PASSED] 0xE20C (BATTLEMAGE)
[06:27:04] [PASSED] 0xE20D (BATTLEMAGE)
[06:27:04] [PASSED] 0xE210 (BATTLEMAGE)
[06:27:04] [PASSED] 0xE211 (BATTLEMAGE)
[06:27:04] [PASSED] 0xE212 (BATTLEMAGE)
[06:27:04] [PASSED] 0xE216 (BATTLEMAGE)
[06:27:04] [PASSED] 0xE220 (BATTLEMAGE)
[06:27:04] [PASSED] 0xE221 (BATTLEMAGE)
[06:27:04] [PASSED] 0xE222 (BATTLEMAGE)
[06:27:04] [PASSED] 0xE223 (BATTLEMAGE)
[06:27:04] [PASSED] 0xB080 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB081 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB082 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB083 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB084 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB085 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB086 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB087 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB08F (PANTHERLAKE)
[06:27:04] [PASSED] 0xB090 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB0A0 (PANTHERLAKE)
[06:27:04] [PASSED] 0xB0B0 (PANTHERLAKE)
[06:27:04] [PASSED] 0xFD80 (PANTHERLAKE)
[06:27:04] [PASSED] 0xFD81 (PANTHERLAKE)
[06:27:04] [PASSED] 0xD740 (NOVALAKE_S)
[06:27:04] [PASSED] 0xD741 (NOVALAKE_S)
[06:27:04] [PASSED] 0xD742 (NOVALAKE_S)
[06:27:04] [PASSED] 0xD743 (NOVALAKE_S)
[06:27:04] [PASSED] 0xD744 (NOVALAKE_S)
[06:27:04] [PASSED] 0xD745 (NOVALAKE_S)
[06:27:04] [PASSED] 0x674C (CRESCENTISLAND)
[06:27:04] =============== [PASSED] check_platform_desc ===============
[06:27:04] ===================== [PASSED] xe_pci ======================
[06:27:04] =================== xe_rtp (2 subtests) ====================
[06:27:04] =============== xe_rtp_process_to_sr_tests  ================
[06:27:04] [PASSED] coalesce-same-reg
[06:27:04] [PASSED] no-match-no-add
[06:27:04] [PASSED] match-or
[06:27:04] [PASSED] match-or-xfail
[06:27:04] [PASSED] no-match-no-add-multiple-rules
[06:27:04] [PASSED] two-regs-two-entries
[06:27:04] [PASSED] clr-one-set-other
[06:27:04] [PASSED] set-field
[06:27:04] [PASSED] conflict-duplicate
[06:27:04] [PASSED] conflict-not-disjoint
[06:27:04] [PASSED] conflict-reg-type
[06:27:04] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:27:04] ================== xe_rtp_process_tests  ===================
[06:27:04] [PASSED] active1
[06:27:04] [PASSED] active2
[06:27:04] [PASSED] active-inactive
[06:27:04] [PASSED] inactive-active
[06:27:04] [PASSED] inactive-1st_or_active-inactive
[06:27:04] [PASSED] inactive-2nd_or_active-inactive
[06:27:04] [PASSED] inactive-last_or_active-inactive
[06:27:04] [PASSED] inactive-no_or_active-inactive
[06:27:04] ============== [PASSED] xe_rtp_process_tests ===============
[06:27:04] ===================== [PASSED] xe_rtp ======================
[06:27:04] ==================== xe_wa (1 subtest) =====================
[06:27:04] ======================== xe_wa_gt  =========================
[06:27:04] [PASSED] TIGERLAKE B0
[06:27:04] [PASSED] DG1 A0
[06:27:04] [PASSED] DG1 B0
[06:27:04] [PASSED] ALDERLAKE_S A0
[06:27:04] [PASSED] ALDERLAKE_S B0
[06:27:04] [PASSED] ALDERLAKE_S C0
[06:27:04] [PASSED] ALDERLAKE_S D0
[06:27:04] [PASSED] ALDERLAKE_P A0
[06:27:04] [PASSED] ALDERLAKE_P B0
[06:27:04] [PASSED] ALDERLAKE_P C0
[06:27:04] [PASSED] ALDERLAKE_S RPLS D0
[06:27:04] [PASSED] ALDERLAKE_P RPLU E0
[06:27:04] [PASSED] DG2 G10 C0
[06:27:04] [PASSED] DG2 G11 B1
[06:27:04] [PASSED] DG2 G12 A1
[06:27:04] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:27:04] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:27:04] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[06:27:04] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[06:27:04] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[06:27:04] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[06:27:04] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[06:27:04] ==================== [PASSED] xe_wa_gt =====================
[06:27:04] ====================== [PASSED] xe_wa ======================
[06:27:04] ============================================================
[06:27:04] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[06:27:04] Elapsed time: 43.451s total, 4.296s configuring, 38.638s building, 0.479s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:27:04] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:27:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[06:27:36] Starting KUnit Kernel (1/1)...
[06:27:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:27:36] ============ drm_test_pick_cmdline (2 subtests) ============
[06:27:36] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:27:36] =============== drm_test_pick_cmdline_named  ===============
[06:27:36] [PASSED] NTSC
[06:27:36] [PASSED] NTSC-J
[06:27:36] [PASSED] PAL
[06:27:36] [PASSED] PAL-M
[06:27:36] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:27:36] ============== [PASSED] drm_test_pick_cmdline ==============
[06:27:36] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:27:36] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:27:36] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:27:36] =========== drm_validate_clone_mode (2 subtests) ===========
[06:27:36] ============== drm_test_check_in_clone_mode  ===============
[06:27:36] [PASSED] in_clone_mode
[06:27:36] [PASSED] not_in_clone_mode
[06:27:36] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:27:36] =============== drm_test_check_valid_clones  ===============
[06:27:36] [PASSED] not_in_clone_mode
[06:27:36] [PASSED] valid_clone
[06:27:36] [PASSED] invalid_clone
[06:27:36] =========== [PASSED] drm_test_check_valid_clones ===========
[06:27:36] ============= [PASSED] drm_validate_clone_mode =============
[06:27:36] ============= drm_validate_modeset (1 subtest) =============
[06:27:36] [PASSED] drm_test_check_connector_changed_modeset
[06:27:36] ============== [PASSED] drm_validate_modeset ===============
[06:27:36] ====== drm_test_bridge_get_current_state (2 subtests) ======
[06:27:36] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:27:36] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[06:27:36] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:27:36] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:27:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:27:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:27:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[06:27:36] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:27:36] ============== drm_bridge_alloc (2 subtests) ===============
[06:27:36] [PASSED] drm_test_drm_bridge_alloc_basic
[06:27:36] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:27:36] ================ [PASSED] drm_bridge_alloc =================
[06:27:36] ================== drm_buddy (8 subtests) ==================
[06:27:36] [PASSED] drm_test_buddy_alloc_limit
[06:27:36] [PASSED] drm_test_buddy_alloc_optimistic
[06:27:36] [PASSED] drm_test_buddy_alloc_pessimistic
[06:27:36] [PASSED] drm_test_buddy_alloc_pathological
[06:27:36] [PASSED] drm_test_buddy_alloc_contiguous
[06:27:36] [PASSED] drm_test_buddy_alloc_clear
[06:27:36] [PASSED] drm_test_buddy_alloc_range_bias
[06:27:36] [PASSED] drm_test_buddy_fragmentation_performance
[06:27:36] ==================== [PASSED] drm_buddy ====================
[06:27:36] ============= drm_cmdline_parser (40 subtests) =============
[06:27:36] [PASSED] drm_test_cmdline_force_d_only
[06:27:36] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:27:36] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:27:36] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:27:36] [PASSED] drm_test_cmdline_force_e_only
[06:27:36] [PASSED] drm_test_cmdline_res
[06:27:36] [PASSED] drm_test_cmdline_res_vesa
[06:27:36] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:27:36] [PASSED] drm_test_cmdline_res_rblank
[06:27:36] [PASSED] drm_test_cmdline_res_bpp
[06:27:36] [PASSED] drm_test_cmdline_res_refresh
[06:27:36] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:27:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:27:36] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:27:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:27:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:27:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:27:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:27:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:27:36] [PASSED] drm_test_cmdline_res_margins_force_on
[06:27:36] [PASSED] drm_test_cmdline_res_vesa_margins
[06:27:36] [PASSED] drm_test_cmdline_name
[06:27:36] [PASSED] drm_test_cmdline_name_bpp
[06:27:36] [PASSED] drm_test_cmdline_name_option
[06:27:36] [PASSED] drm_test_cmdline_name_bpp_option
[06:27:36] [PASSED] drm_test_cmdline_rotate_0
[06:27:36] [PASSED] drm_test_cmdline_rotate_90
[06:27:36] [PASSED] drm_test_cmdline_rotate_180
[06:27:36] [PASSED] drm_test_cmdline_rotate_270
[06:27:36] [PASSED] drm_test_cmdline_hmirror
[06:27:36] [PASSED] drm_test_cmdline_vmirror
[06:27:36] [PASSED] drm_test_cmdline_margin_options
[06:27:36] [PASSED] drm_test_cmdline_multiple_options
[06:27:36] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:27:36] [PASSED] drm_test_cmdline_extra_and_option
[06:27:36] [PASSED] drm_test_cmdline_freestanding_options
[06:27:36] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:27:36] [PASSED] drm_test_cmdline_panel_orientation
[06:27:36] ================ drm_test_cmdline_invalid  =================
[06:27:36] [PASSED] margin_only
[06:27:36] [PASSED] interlace_only
[06:27:36] [PASSED] res_missing_x
[06:27:36] [PASSED] res_missing_y
[06:27:36] [PASSED] res_bad_y
[06:27:36] [PASSED] res_missing_y_bpp
[06:27:36] [PASSED] res_bad_bpp
[06:27:36] [PASSED] res_bad_refresh
[06:27:36] [PASSED] res_bpp_refresh_force_on_off
[06:27:36] [PASSED] res_invalid_mode
[06:27:36] [PASSED] res_bpp_wrong_place_mode
[06:27:36] [PASSED] name_bpp_refresh
[06:27:36] [PASSED] name_refresh
[06:27:36] [PASSED] name_refresh_wrong_mode
[06:27:36] [PASSED] name_refresh_invalid_mode
[06:27:36] [PASSED] rotate_multiple
[06:27:36] [PASSED] rotate_invalid_val
[06:27:36] [PASSED] rotate_truncated
[06:27:36] [PASSED] invalid_option
[06:27:36] [PASSED] invalid_tv_option
[06:27:36] [PASSED] truncated_tv_option
[06:27:36] ============ [PASSED] drm_test_cmdline_invalid =============
[06:27:36] =============== drm_test_cmdline_tv_options  ===============
[06:27:36] [PASSED] NTSC
[06:27:36] [PASSED] NTSC_443
[06:27:36] [PASSED] NTSC_J
[06:27:36] [PASSED] PAL
[06:27:36] [PASSED] PAL_M
[06:27:36] [PASSED] PAL_N
[06:27:36] [PASSED] SECAM
[06:27:36] [PASSED] MONO_525
[06:27:36] [PASSED] MONO_625
[06:27:36] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:27:36] =============== [PASSED] drm_cmdline_parser ================
[06:27:36] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:27:36] [PASSED] drm_test_connector_hdmi_init_valid
[06:27:36] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:27:36] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:27:36] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:27:36] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:27:36] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:27:36] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:27:36] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:27:36] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[06:27:36] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:27:36] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:27:36] [PASSED] supported_formats=0x3 yuv420_allowed=1
[06:27:36] [PASSED] supported_formats=0x3 yuv420_allowed=0
[06:27:36] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:27:36] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:27:36] [PASSED] drm_test_connector_hdmi_init_null_product
[06:27:36] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:27:36] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:27:36] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:27:36] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:27:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:27:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:27:36] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:27:36] ========= drm_test_connector_hdmi_init_type_valid  =========
[06:27:36] [PASSED] HDMI-A
[06:27:36] [PASSED] HDMI-B
[06:27:36] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:27:36] ======== drm_test_connector_hdmi_init_type_invalid  ========
[06:27:36] [PASSED] Unknown
[06:27:36] [PASSED] VGA
[06:27:36] [PASSED] DVI-I
[06:27:36] [PASSED] DVI-D
[06:27:36] [PASSED] DVI-A
[06:27:36] [PASSED] Composite
[06:27:36] [PASSED] SVIDEO
[06:27:36] [PASSED] LVDS
[06:27:36] [PASSED] Component
[06:27:36] [PASSED] DIN
[06:27:36] [PASSED] DP
[06:27:36] [PASSED] TV
[06:27:36] [PASSED] eDP
[06:27:36] [PASSED] Virtual
[06:27:36] [PASSED] DSI
[06:27:36] [PASSED] DPI
[06:27:36] [PASSED] Writeback
[06:27:36] [PASSED] SPI
[06:27:36] [PASSED] USB
[06:27:36] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:27:36] ============ [PASSED] drmm_connector_hdmi_init =============
[06:27:36] ============= drmm_connector_init (3 subtests) =============
[06:27:36] [PASSED] drm_test_drmm_connector_init
[06:27:36] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:27:36] ========= drm_test_drmm_connector_init_type_valid  =========
[06:27:36] [PASSED] Unknown
[06:27:36] [PASSED] VGA
[06:27:36] [PASSED] DVI-I
[06:27:36] [PASSED] DVI-D
[06:27:36] [PASSED] DVI-A
[06:27:36] [PASSED] Composite
[06:27:36] [PASSED] SVIDEO
[06:27:36] [PASSED] LVDS
[06:27:36] [PASSED] Component
[06:27:36] [PASSED] DIN
[06:27:36] [PASSED] DP
[06:27:36] [PASSED] HDMI-A
[06:27:36] [PASSED] HDMI-B
[06:27:36] [PASSED] TV
[06:27:36] [PASSED] eDP
[06:27:36] [PASSED] Virtual
[06:27:36] [PASSED] DSI
[06:27:36] [PASSED] DPI
[06:27:36] [PASSED] Writeback
[06:27:36] [PASSED] SPI
[06:27:36] [PASSED] USB
[06:27:36] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:27:36] =============== [PASSED] drmm_connector_init ===============
[06:27:36] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_init
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:27:36] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[06:27:36] [PASSED] Unknown
[06:27:36] [PASSED] VGA
[06:27:36] [PASSED] DVI-I
[06:27:36] [PASSED] DVI-D
[06:27:36] [PASSED] DVI-A
[06:27:36] [PASSED] Composite
[06:27:36] [PASSED] SVIDEO
[06:27:36] [PASSED] LVDS
[06:27:36] [PASSED] Component
[06:27:36] [PASSED] DIN
[06:27:36] [PASSED] DP
[06:27:36] [PASSED] HDMI-A
[06:27:36] [PASSED] HDMI-B
[06:27:36] [PASSED] TV
[06:27:36] [PASSED] eDP
[06:27:36] [PASSED] Virtual
[06:27:36] [PASSED] DSI
[06:27:36] [PASSED] DPI
[06:27:36] [PASSED] Writeback
[06:27:36] [PASSED] SPI
[06:27:36] [PASSED] USB
[06:27:36] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:27:36] ======== drm_test_drm_connector_dynamic_init_name  =========
[06:27:36] [PASSED] Unknown
[06:27:36] [PASSED] VGA
[06:27:36] [PASSED] DVI-I
[06:27:36] [PASSED] DVI-D
[06:27:36] [PASSED] DVI-A
[06:27:36] [PASSED] Composite
[06:27:36] [PASSED] SVIDEO
[06:27:36] [PASSED] LVDS
[06:27:36] [PASSED] Component
[06:27:36] [PASSED] DIN
[06:27:36] [PASSED] DP
[06:27:36] [PASSED] HDMI-A
[06:27:36] [PASSED] HDMI-B
[06:27:36] [PASSED] TV
[06:27:36] [PASSED] eDP
[06:27:36] [PASSED] Virtual
[06:27:36] [PASSED] DSI
[06:27:36] [PASSED] DPI
[06:27:36] [PASSED] Writeback
[06:27:36] [PASSED] SPI
[06:27:36] [PASSED] USB
[06:27:36] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:27:36] =========== [PASSED] drm_connector_dynamic_init ============
[06:27:36] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:27:36] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:27:36] ======= drm_connector_dynamic_register (7 subtests) ========
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:27:36] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:27:36] ========= [PASSED] drm_connector_dynamic_register ==========
[06:27:36] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:27:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:27:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:27:36] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:27:36] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:27:36] ========== drm_test_get_tv_mode_from_name_valid  ===========
[06:27:36] [PASSED] NTSC
[06:27:36] [PASSED] NTSC-443
[06:27:36] [PASSED] NTSC-J
[06:27:36] [PASSED] PAL
[06:27:36] [PASSED] PAL-M
[06:27:36] [PASSED] PAL-N
[06:27:36] [PASSED] SECAM
[06:27:36] [PASSED] Mono
[06:27:36] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:27:36] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:27:36] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:27:36] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:27:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:27:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:27:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:27:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:27:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:27:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:27:36] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[06:27:36] [PASSED] VIC 96
[06:27:36] [PASSED] VIC 97
[06:27:36] [PASSED] VIC 101
[06:27:36] [PASSED] VIC 102
[06:27:36] [PASSED] VIC 106
[06:27:36] [PASSED] VIC 107
[06:27:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:27:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:27:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:27:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:27:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:27:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:27:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:27:36] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:27:36] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[06:27:36] [PASSED] Automatic
[06:27:36] [PASSED] Full
[06:27:36] [PASSED] Limited 16:235
[06:27:36] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:27:36] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:27:36] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:27:36] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:27:36] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[06:27:36] [PASSED] RGB
[06:27:36] [PASSED] YUV 4:2:0
[06:27:36] [PASSED] YUV 4:2:2
[06:27:36] [PASSED] YUV 4:4:4
[06:27:36] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:27:36] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:27:36] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:27:36] ============= drm_damage_helper (21 subtests) ==============
[06:27:36] [PASSED] drm_test_damage_iter_no_damage
[06:27:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:27:36] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:27:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:27:36] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:27:36] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:27:36] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:27:36] [PASSED] drm_test_damage_iter_simple_damage
[06:27:36] [PASSED] drm_test_damage_iter_single_damage
[06:27:36] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:27:36] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:27:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:27:36] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:27:36] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:27:36] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:27:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:27:36] [PASSED] drm_test_damage_iter_damage
[06:27:36] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:27:36] [PASSED] drm_test_damage_iter_damage_one_outside
[06:27:36] [PASSED] drm_test_damage_iter_damage_src_moved
[06:27:36] [PASSED] drm_test_damage_iter_damage_not_visible
[06:27:36] ================ [PASSED] drm_damage_helper ================
[06:27:36] ============== drm_dp_mst_helper (3 subtests) ==============
[06:27:36] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[06:27:36] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:27:36] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:27:36] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:27:36] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:27:36] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:27:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:27:36] ============== drm_test_dp_mst_calc_pbn_div  ===============
[06:27:36] [PASSED] Link rate 2000000 lane count 4
[06:27:36] [PASSED] Link rate 2000000 lane count 2
[06:27:36] [PASSED] Link rate 2000000 lane count 1
[06:27:36] [PASSED] Link rate 1350000 lane count 4
[06:27:36] [PASSED] Link rate 1350000 lane count 2
[06:27:36] [PASSED] Link rate 1350000 lane count 1
[06:27:36] [PASSED] Link rate 1000000 lane count 4
[06:27:36] [PASSED] Link rate 1000000 lane count 2
[06:27:36] [PASSED] Link rate 1000000 lane count 1
[06:27:36] [PASSED] Link rate 810000 lane count 4
[06:27:36] [PASSED] Link rate 810000 lane count 2
[06:27:36] [PASSED] Link rate 810000 lane count 1
[06:27:36] [PASSED] Link rate 540000 lane count 4
[06:27:36] [PASSED] Link rate 540000 lane count 2
[06:27:36] [PASSED] Link rate 540000 lane count 1
[06:27:36] [PASSED] Link rate 270000 lane count 4
[06:27:36] [PASSED] Link rate 270000 lane count 2
[06:27:36] [PASSED] Link rate 270000 lane count 1
[06:27:36] [PASSED] Link rate 162000 lane count 4
[06:27:36] [PASSED] Link rate 162000 lane count 2
[06:27:36] [PASSED] Link rate 162000 lane count 1
[06:27:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:27:36] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[06:27:36] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:27:36] [PASSED] DP_POWER_UP_PHY with port number
[06:27:36] [PASSED] DP_POWER_DOWN_PHY with port number
[06:27:36] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:27:36] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:27:36] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:27:36] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:27:36] [PASSED] DP_QUERY_PAYLOAD with port number
[06:27:36] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:27:36] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:27:36] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:27:36] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:27:36] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:27:36] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:27:36] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:27:36] [PASSED] DP_REMOTE_I2C_READ with port number
[06:27:36] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:27:36] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:27:36] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:27:36] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:27:36] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:27:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:27:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:27:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:27:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:27:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:27:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:27:36] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:27:36] ================ [PASSED] drm_dp_mst_helper ================
[06:27:36] ================== drm_exec (7 subtests) ===================
[06:27:36] [PASSED] sanitycheck
[06:27:36] [PASSED] test_lock
[06:27:36] [PASSED] test_lock_unlock
[06:27:36] [PASSED] test_duplicates
[06:27:36] [PASSED] test_prepare
[06:27:36] [PASSED] test_prepare_array
[06:27:36] [PASSED] test_multiple_loops
[06:27:36] ==================== [PASSED] drm_exec =====================
[06:27:36] =========== drm_format_helper_test (17 subtests) ===========
[06:27:36] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:27:36] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:27:36] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:27:36] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:27:36] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:27:36] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:27:36] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:27:36] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:27:36] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:27:36] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:27:36] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:27:36] ============== drm_test_fb_xrgb8888_to_mono  ===============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:27:36] ==================== drm_test_fb_swab  =====================
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ================ [PASSED] drm_test_fb_swab =================
[06:27:36] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:27:36] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[06:27:36] [PASSED] single_pixel_source_buffer
[06:27:36] [PASSED] single_pixel_clip_rectangle
[06:27:36] [PASSED] well_known_colors
[06:27:36] [PASSED] destination_pitch
[06:27:36] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:27:36] ================= drm_test_fb_clip_offset  =================
[06:27:36] [PASSED] pass through
[06:27:36] [PASSED] horizontal offset
[06:27:36] [PASSED] vertical offset
[06:27:36] [PASSED] horizontal and vertical offset
[06:27:36] [PASSED] horizontal offset (custom pitch)
[06:27:36] [PASSED] vertical offset (custom pitch)
[06:27:36] [PASSED] horizontal and vertical offset (custom pitch)
[06:27:36] ============= [PASSED] drm_test_fb_clip_offset =============
[06:27:36] =================== drm_test_fb_memcpy  ====================
[06:27:36] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:27:36] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:27:36] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:27:36] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:27:36] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:27:36] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:27:36] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:27:36] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:27:36] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:27:36] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:27:36] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:27:36] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:27:36] =============== [PASSED] drm_test_fb_memcpy ================
[06:27:36] ============= [PASSED] drm_format_helper_test ==============
[06:27:36] ================= drm_format (18 subtests) =================
[06:27:36] [PASSED] drm_test_format_block_width_invalid
[06:27:36] [PASSED] drm_test_format_block_width_one_plane
[06:27:36] [PASSED] drm_test_format_block_width_two_plane
[06:27:36] [PASSED] drm_test_format_block_width_three_plane
[06:27:36] [PASSED] drm_test_format_block_width_tiled
[06:27:36] [PASSED] drm_test_format_block_height_invalid
[06:27:36] [PASSED] drm_test_format_block_height_one_plane
[06:27:36] [PASSED] drm_test_format_block_height_two_plane
[06:27:36] [PASSED] drm_test_format_block_height_three_plane
[06:27:36] [PASSED] drm_test_format_block_height_tiled
[06:27:36] [PASSED] drm_test_format_min_pitch_invalid
[06:27:36] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:27:36] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:27:36] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:27:36] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:27:36] [PASSED] drm_test_format_min_pitch_two_plane
[06:27:36] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:27:36] [PASSED] drm_test_format_min_pitch_tiled
[06:27:36] =================== [PASSED] drm_format ====================
[06:27:36] ============== drm_framebuffer (10 subtests) ===============
[06:27:36] ========== drm_test_framebuffer_check_src_coords  ==========
[06:27:36] [PASSED] Success: source fits into fb
[06:27:36] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:27:36] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:27:36] [PASSED] Fail: overflowing fb with source width
[06:27:36] [PASSED] Fail: overflowing fb with source height
[06:27:36] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:27:36] [PASSED] drm_test_framebuffer_cleanup
[06:27:36] =============== drm_test_framebuffer_create  ===============
[06:27:36] [PASSED] ABGR8888 normal sizes
[06:27:36] [PASSED] ABGR8888 max sizes
[06:27:36] [PASSED] ABGR8888 pitch greater than min required
[06:27:36] [PASSED] ABGR8888 pitch less than min required
[06:27:36] [PASSED] ABGR8888 Invalid width
[06:27:36] [PASSED] ABGR8888 Invalid buffer handle
[06:27:36] [PASSED] No pixel format
[06:27:36] [PASSED] ABGR8888 Width 0
[06:27:36] [PASSED] ABGR8888 Height 0
[06:27:36] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:27:36] [PASSED] ABGR8888 Large buffer offset
[06:27:36] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:27:36] [PASSED] ABGR8888 Invalid flag
[06:27:36] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:27:36] [PASSED] ABGR8888 Valid buffer modifier
[06:27:36] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:27:36] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:27:36] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:27:36] [PASSED] NV12 Normal sizes
[06:27:36] [PASSED] NV12 Max sizes
[06:27:36] [PASSED] NV12 Invalid pitch
[06:27:36] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:27:36] [PASSED] NV12 different  modifier per-plane
[06:27:36] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:27:36] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:27:36] [PASSED] NV12 Modifier for inexistent plane
[06:27:36] [PASSED] NV12 Handle for inexistent plane
[06:27:36] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:27:36] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:27:36] [PASSED] YVU420 Normal sizes
[06:27:36] [PASSED] YVU420 Max sizes
[06:27:36] [PASSED] YVU420 Invalid pitch
[06:27:36] [PASSED] YVU420 Different pitches
[06:27:36] [PASSED] YVU420 Different buffer offsets/pitches
[06:27:36] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:27:36] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:27:36] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:27:36] [PASSED] YVU420 Valid modifier
[06:27:36] [PASSED] YVU420 Different modifiers per plane
[06:27:36] [PASSED] YVU420 Modifier for inexistent plane
[06:27:36] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:27:36] [PASSED] X0L2 Normal sizes
[06:27:36] [PASSED] X0L2 Max sizes
[06:27:36] [PASSED] X0L2 Invalid pitch
[06:27:36] [PASSED] X0L2 Pitch greater than minimum required
[06:27:36] [PASSED] X0L2 Handle for inexistent plane
[06:27:36] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:27:36] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:27:36] [PASSED] X0L2 Valid modifier
[06:27:36] [PASSED] X0L2 Modifier for inexistent plane
[06:27:36] =========== [PASSED] drm_test_framebuffer_create ===========
[06:27:36] [PASSED] drm_test_framebuffer_free
[06:27:36] [PASSED] drm_test_framebuffer_init
[06:27:36] [PASSED] drm_test_framebuffer_init_bad_format
[06:27:36] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:27:36] [PASSED] drm_test_framebuffer_lookup
[06:27:36] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:27:36] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:27:36] ================= [PASSED] drm_framebuffer =================
[06:27:36] ================ drm_gem_shmem (8 subtests) ================
[06:27:36] [PASSED] drm_gem_shmem_test_obj_create
[06:27:36] [PASSED] drm_gem_shmem_test_obj_create_private
[06:27:36] [PASSED] drm_gem_shmem_test_pin_pages
[06:27:36] [PASSED] drm_gem_shmem_test_vmap
[06:27:36] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:27:36] [PASSED] drm_gem_shmem_test_get_sg_table
[06:27:36] [PASSED] drm_gem_shmem_test_madvise
[06:27:36] [PASSED] drm_gem_shmem_test_purge
[06:27:36] ================== [PASSED] drm_gem_shmem ==================
[06:27:36] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[06:27:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:27:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:27:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:27:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:27:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:27:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:27:36] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[06:27:36] [PASSED] Automatic
[06:27:36] [PASSED] Full
[06:27:36] [PASSED] Limited 16:235
[06:27:36] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:27:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:27:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:27:36] [PASSED] drm_test_check_disable_connector
[06:27:36] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:27:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:27:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:27:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:27:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:27:36] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:27:36] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:27:36] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:27:36] [PASSED] drm_test_check_output_bpc_dvi
[06:27:36] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:27:36] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:27:36] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:27:36] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:27:36] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:27:36] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:27:36] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:27:36] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:27:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:27:36] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:27:36] [PASSED] drm_test_check_broadcast_rgb_value
[06:27:36] [PASSED] drm_test_check_bpc_8_value
[06:27:36] [PASSED] drm_test_check_bpc_10_value
[06:27:36] [PASSED] drm_test_check_bpc_12_value
[06:27:36] [PASSED] drm_test_check_format_value
[06:27:36] [PASSED] drm_test_check_tmds_char_value
[06:27:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:27:36] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[06:27:36] [PASSED] drm_test_check_mode_valid
[06:27:36] [PASSED] drm_test_check_mode_valid_reject
[06:27:36] [PASSED] drm_test_check_mode_valid_reject_rate
[06:27:36] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:27:36] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:27:36] ================= drm_managed (2 subtests) =================
[06:27:36] [PASSED] drm_test_managed_release_action
[06:27:36] [PASSED] drm_test_managed_run_action
[06:27:36] =================== [PASSED] drm_managed ===================
[06:27:36] =================== drm_mm (6 subtests) ====================
[06:27:36] [PASSED] drm_test_mm_init
[06:27:36] [PASSED] drm_test_mm_debug
[06:27:36] [PASSED] drm_test_mm_align32
[06:27:36] [PASSED] drm_test_mm_align64
[06:27:36] [PASSED] drm_test_mm_lowest
[06:27:36] [PASSED] drm_test_mm_highest
[06:27:36] ===================== [PASSED] drm_mm ======================
[06:27:36] ============= drm_modes_analog_tv (5 subtests) =============
[06:27:36] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:27:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:27:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:27:36] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:27:36] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:27:36] =============== [PASSED] drm_modes_analog_tv ===============
[06:27:36] ============== drm_plane_helper (2 subtests) ===============
[06:27:36] =============== drm_test_check_plane_state  ================
[06:27:36] [PASSED] clipping_simple
[06:27:36] [PASSED] clipping_rotate_reflect
[06:27:36] [PASSED] positioning_simple
[06:27:36] [PASSED] upscaling
[06:27:36] [PASSED] downscaling
[06:27:36] [PASSED] rounding1
[06:27:36] [PASSED] rounding2
[06:27:36] [PASSED] rounding3
[06:27:36] [PASSED] rounding4
[06:27:36] =========== [PASSED] drm_test_check_plane_state ============
[06:27:36] =========== drm_test_check_invalid_plane_state  ============
[06:27:36] [PASSED] positioning_invalid
[06:27:36] [PASSED] upscaling_invalid
[06:27:36] [PASSED] downscaling_invalid
[06:27:36] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:27:36] ================ [PASSED] drm_plane_helper =================
[06:27:36] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:27:36] ====== drm_test_connector_helper_tv_get_modes_check  =======
[06:27:36] [PASSED] None
[06:27:36] [PASSED] PAL
[06:27:36] [PASSED] NTSC
[06:27:36] [PASSED] Both, NTSC Default
[06:27:36] [PASSED] Both, PAL Default
[06:27:36] [PASSED] Both, NTSC Default, with PAL on command-line
[06:27:36] [PASSED] Both, PAL Default, with NTSC on command-line
[06:27:36] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:27:36] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:27:36] ================== drm_rect (9 subtests) ===================
[06:27:36] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:27:36] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:27:36] [PASSED] drm_test_rect_clip_scaled_clipped
[06:27:36] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:27:36] ================= drm_test_rect_intersect  =================
[06:27:36] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:27:36] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:27:36] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:27:36] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:27:36] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:27:36] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:27:36] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:27:36] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:27:36] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:27:36] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:27:36] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:27:36] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:27:36] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:27:36] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:27:36] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:27:36] ============= [PASSED] drm_test_rect_intersect =============
[06:27:36] ================ drm_test_rect_calc_hscale  ================
[06:27:36] [PASSED] normal use
[06:27:36] [PASSED] out of max range
[06:27:36] [PASSED] out of min range
[06:27:36] [PASSED] zero dst
[06:27:36] [PASSED] negative src
[06:27:36] [PASSED] negative dst
[06:27:36] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:27:36] ================ drm_test_rect_calc_vscale  ================
[06:27:36] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[06:27:36] [PASSED] out of max range
[06:27:36] [PASSED] out of min range
[06:27:36] [PASSED] zero dst
[06:27:36] [PASSED] negative src
[06:27:36] [PASSED] negative dst
[06:27:36] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:27:36] ================== drm_test_rect_rotate  ===================
[06:27:36] [PASSED] reflect-x
[06:27:36] [PASSED] reflect-y
[06:27:36] [PASSED] rotate-0
[06:27:36] [PASSED] rotate-90
[06:27:36] [PASSED] rotate-180
[06:27:36] [PASSED] rotate-270
[06:27:36] ============== [PASSED] drm_test_rect_rotate ===============
[06:27:36] ================ drm_test_rect_rotate_inv  =================
[06:27:36] [PASSED] reflect-x
[06:27:36] [PASSED] reflect-y
[06:27:36] [PASSED] rotate-0
[06:27:36] [PASSED] rotate-90
[06:27:36] [PASSED] rotate-180
[06:27:36] [PASSED] rotate-270
[06:27:36] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:27:36] ==================== [PASSED] drm_rect =====================
[06:27:36] ============ drm_sysfb_modeset_test (1 subtest) ============
[06:27:36] ============ drm_test_sysfb_build_fourcc_list  =============
[06:27:36] [PASSED] no native formats
[06:27:36] [PASSED] XRGB8888 as native format
[06:27:36] [PASSED] remove duplicates
[06:27:36] [PASSED] convert alpha formats
[06:27:36] [PASSED] random formats
[06:27:36] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[06:27:36] ============= [PASSED] drm_sysfb_modeset_test ==============
[06:27:36] ================== drm_fixp (2 subtests) ===================
[06:27:36] [PASSED] drm_test_int2fixp
[06:27:36] [PASSED] drm_test_sm2fixp
[06:27:36] ==================== [PASSED] drm_fixp =====================
[06:27:36] ============================================================
[06:27:36] Testing complete. Ran 624 tests: passed: 624
[06:27:36] Elapsed time: 32.336s total, 1.617s configuring, 30.252s building, 0.449s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:27:36] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:27:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[06:27:47] Starting KUnit Kernel (1/1)...
[06:27:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:27:47] ================= ttm_device (5 subtests) ==================
[06:27:47] [PASSED] ttm_device_init_basic
[06:27:47] [PASSED] ttm_device_init_multiple
[06:27:47] [PASSED] ttm_device_fini_basic
[06:27:47] [PASSED] ttm_device_init_no_vma_man
[06:27:47] ================== ttm_device_init_pools  ==================
[06:27:47] [PASSED] No DMA allocations, no DMA32 required
[06:27:47] [PASSED] DMA allocations, DMA32 required
[06:27:47] [PASSED] No DMA allocations, DMA32 required
[06:27:47] [PASSED] DMA allocations, no DMA32 required
[06:27:47] ============== [PASSED] ttm_device_init_pools ==============
[06:27:47] =================== [PASSED] ttm_device ====================
[06:27:47] ================== ttm_pool (8 subtests) ===================
[06:27:47] ================== ttm_pool_alloc_basic  ===================
[06:27:47] [PASSED] One page
[06:27:47] [PASSED] More than one page
[06:27:47] [PASSED] Above the allocation limit
[06:27:47] [PASSED] One page, with coherent DMA mappings enabled
[06:27:47] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:27:47] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:27:47] ============== ttm_pool_alloc_basic_dma_addr  ==============
[06:27:47] [PASSED] One page
[06:27:47] [PASSED] More than one page
[06:27:47] [PASSED] Above the allocation limit
[06:27:47] [PASSED] One page, with coherent DMA mappings enabled
[06:27:47] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:27:47] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:27:47] [PASSED] ttm_pool_alloc_order_caching_match
[06:27:47] [PASSED] ttm_pool_alloc_caching_mismatch
[06:27:47] [PASSED] ttm_pool_alloc_order_mismatch
[06:27:47] [PASSED] ttm_pool_free_dma_alloc
[06:27:47] [PASSED] ttm_pool_free_no_dma_alloc
[06:27:47] [PASSED] ttm_pool_fini_basic
[06:27:47] ==================== [PASSED] ttm_pool =====================
[06:27:47] ================ ttm_resource (8 subtests) =================
[06:27:47] ================= ttm_resource_init_basic  =================
[06:27:47] [PASSED] Init resource in TTM_PL_SYSTEM
[06:27:47] [PASSED] Init resource in TTM_PL_VRAM
[06:27:47] [PASSED] Init resource in a private placement
[06:27:47] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:27:47] ============= [PASSED] ttm_resource_init_basic =============
[06:27:47] [PASSED] ttm_resource_init_pinned
[06:27:47] [PASSED] ttm_resource_fini_basic
[06:27:47] [PASSED] ttm_resource_manager_init_basic
[06:27:47] [PASSED] ttm_resource_manager_usage_basic
[06:27:47] [PASSED] ttm_resource_manager_set_used_basic
[06:27:47] [PASSED] ttm_sys_man_alloc_basic
[06:27:47] [PASSED] ttm_sys_man_free_basic
[06:27:47] ================== [PASSED] ttm_resource ===================
[06:27:47] =================== ttm_tt (15 subtests) ===================
[06:27:47] ==================== ttm_tt_init_basic  ====================
[06:27:47] [PASSED] Page-aligned size
[06:27:47] [PASSED] Extra pages requested
[06:27:47] ================ [PASSED] ttm_tt_init_basic ================
[06:27:47] [PASSED] ttm_tt_init_misaligned
[06:27:47] [PASSED] ttm_tt_fini_basic
[06:27:47] [PASSED] ttm_tt_fini_sg
[06:27:47] [PASSED] ttm_tt_fini_shmem
[06:27:47] [PASSED] ttm_tt_create_basic
[06:27:47] [PASSED] ttm_tt_create_invalid_bo_type
[06:27:47] [PASSED] ttm_tt_create_ttm_exists
[06:27:47] [PASSED] ttm_tt_create_failed
[06:27:47] [PASSED] ttm_tt_destroy_basic
[06:27:47] [PASSED] ttm_tt_populate_null_ttm
[06:27:47] [PASSED] ttm_tt_populate_populated_ttm
[06:27:47] [PASSED] ttm_tt_unpopulate_basic
[06:27:47] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:27:47] [PASSED] ttm_tt_swapin_basic
[06:27:47] ===================== [PASSED] ttm_tt ======================
[06:27:47] =================== ttm_bo (14 subtests) ===================
[06:27:47] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[06:27:47] [PASSED] Cannot be interrupted and sleeps
[06:27:47] [PASSED] Cannot be interrupted, locks straight away
[06:27:47] [PASSED] Can be interrupted, sleeps
[06:27:47] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:27:47] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:27:47] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:27:47] [PASSED] ttm_bo_reserve_double_resv
[06:27:47] [PASSED] ttm_bo_reserve_interrupted
[06:27:47] [PASSED] ttm_bo_reserve_deadlock
[06:27:48] [PASSED] ttm_bo_unreserve_basic
[06:27:48] [PASSED] ttm_bo_unreserve_pinned
[06:27:48] [PASSED] ttm_bo_unreserve_bulk
[06:27:48] [PASSED] ttm_bo_fini_basic
[06:27:48] [PASSED] ttm_bo_fini_shared_resv
[06:27:48] [PASSED] ttm_bo_pin_basic
[06:27:48] [PASSED] ttm_bo_pin_unpin_resource
[06:27:48] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:27:48] ===================== [PASSED] ttm_bo ======================
[06:27:48] ============== ttm_bo_validate (21 subtests) ===============
[06:27:48] ============== ttm_bo_init_reserved_sys_man  ===============
[06:27:48] [PASSED] Buffer object for userspace
[06:27:48] [PASSED] Kernel buffer object
[06:27:48] [PASSED] Shared buffer object
[06:27:48] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:27:48] ============== ttm_bo_init_reserved_mock_man  ==============
[06:27:48] [PASSED] Buffer object for userspace
[06:27:48] [PASSED] Kernel buffer object
[06:27:48] [PASSED] Shared buffer object
[06:27:48] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:27:48] [PASSED] ttm_bo_init_reserved_resv
[06:27:48] ================== ttm_bo_validate_basic  ==================
[06:27:48] [PASSED] Buffer object for userspace
[06:27:48] [PASSED] Kernel buffer object
[06:27:48] [PASSED] Shared buffer object
[06:27:48] ============== [PASSED] ttm_bo_validate_basic ==============
[06:27:48] [PASSED] ttm_bo_validate_invalid_placement
[06:27:48] ============= ttm_bo_validate_same_placement  ==============
[06:27:48] [PASSED] System manager
[06:27:48] [PASSED] VRAM manager
[06:27:48] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:27:48] [PASSED] ttm_bo_validate_failed_alloc
[06:27:48] [PASSED] ttm_bo_validate_pinned
[06:27:48] [PASSED] ttm_bo_validate_busy_placement
[06:27:48] ================ ttm_bo_validate_multihop  =================
[06:27:48] [PASSED] Buffer object for userspace
[06:27:48] [PASSED] Kernel buffer object
[06:27:48] [PASSED] Shared buffer object
[06:27:48] ============ [PASSED] ttm_bo_validate_multihop =============
[06:27:48] ========== ttm_bo_validate_no_placement_signaled  ==========
[06:27:48] [PASSED] Buffer object in system domain, no page vector
[06:27:48] [PASSED] Buffer object in system domain with an existing page vector
[06:27:48] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:27:48] ======== ttm_bo_validate_no_placement_not_signaled  ========
[06:27:48] [PASSED] Buffer object for userspace
[06:27:48] [PASSED] Kernel buffer object
[06:27:48] [PASSED] Shared buffer object
[06:27:48] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:27:48] [PASSED] ttm_bo_validate_move_fence_signaled
[06:27:48] ========= ttm_bo_validate_move_fence_not_signaled  =========
[06:27:48] [PASSED] Waits for GPU
[06:27:48] [PASSED] Tries to lock straight away
[06:27:48] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:27:48] [PASSED] ttm_bo_validate_happy_evict
[06:27:48] [PASSED] ttm_bo_validate_all_pinned_evict
[06:27:48] [PASSED] ttm_bo_validate_allowed_only_evict
[06:27:48] [PASSED] ttm_bo_validate_deleted_evict
[06:27:48] [PASSED] ttm_bo_validate_busy_domain_evict
[06:27:48] [PASSED] ttm_bo_validate_evict_gutting
[06:27:48] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[06:27:48] ================= [PASSED] ttm_bo_validate =================
[06:27:48] ============================================================
[06:27:48] Testing complete. Ran 101 tests: passed: 101
[06:27:48] Elapsed time: 11.128s total, 1.619s configuring, 9.243s building, 0.233s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Make Display free from i915_reg.h

[Patchwork]

== Series Details ==

Series: Make Display free from i915_reg.h
URL   : https://patchwork.freedesktop.org/series/159130/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 2eb2f8746a879f1c0e4c56b715c179424dafd8e0
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/g4x_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_combo_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_crt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cx0_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_device.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_display_power_map.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_well.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_rps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpio_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll_mgr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_mst.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt_common.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_test.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_drrs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi_vbt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fbc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_fifo_underrun.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_gmbus.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lspcon.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_setup.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_overlay.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_refclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pfit.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pipe_crc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pmdemand.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sdvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tv.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vblank.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vrr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_scaler.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/skl_universal_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/gt/intel_reset.c:1569:12: warning: context imbalance in '_intel_gt_reset_lock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:193:1: error: bad constant expression
+drivers/gpu/drm/i915/i915_gpu_error.c:692:3: warning: symbol 'guc_hw_reg_state' was not declared. Should it be static?
+drivers/gpu/drm/i915/i915_irq.c:467:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:467:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:475:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:475:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:518:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:518:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:526:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:526:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:575:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:575:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:578:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:578:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:582:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:582:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Make Display free from i915_reg.h

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2503 bytes --]

== Series Details ==

Series: Make Display free from i915_reg.h
URL   : https://patchwork.freedesktop.org/series/159130/
State : success

== Summary ==

CI Bug Log - changes from xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0_BAT -> xe-pw-159130v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-159130v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [PASS][1] -> [TIMEOUT][2] ([Intel XE#6506])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [PASS][3] -> [FAIL][4] ([Intel XE#6520])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [FAIL][5] ([Intel XE#6519]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * IGT: IGT_8668 -> IGT_8669
  * Linux: xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0 -> xe-pw-159130v1

  IGT_8668: 906681747a312ef11ef9af8ab1fa6eff28b4cbd0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8669: 319db2ffba419f9711acc72895f065a818905efa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0: 2eb2f8746a879f1c0e4c56b715c179424dafd8e0
  xe-pw-159130v1: 159130v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/index.html

[-- Attachment #2: Type: text/html, Size: 3138 bytes --]

Re: [PATCH 01/19] drm/{i915, xe}: Extract common registers into a separate file

[Jani Nikula]

On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> There are certain register definitions which are commonly shared
> by i915, xe and display. Extract the same to a common header to
> avoid duplication.

I think TRANS_CHICKEN2 should be moved to intel_display_regs.h instead
of something under include/drm/intel. The goal is that the display
specific parts of intel_clock_gating.c should be moved there too.

BR,
Jani.


>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_pch_display.c    |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h                 | 11 +----------
>  include/drm/intel/intel_gmd_common_regs.h       | 17 +++++++++++++++++
>  3 files changed, 19 insertions(+), 11 deletions(-)
>  create mode 100644 include/drm/intel/intel_gmd_common_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 16619f7be5f8..2f39ff32c6d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -4,9 +4,9 @@
>   */
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
>  #include "g4x_dp.h"
> -#include "i915_reg.h"
>  #include "intel_crt.h"
>  #include "intel_crt_regs.h"
>  #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5bf3b4ab2baa..f60259c41c56 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,6 +25,7 @@
>  #ifndef _I915_REG_H_
>  #define _I915_REG_H_
>  
> +#include <drm/intel/intel_gmd_common_regs.h>
>  #include "i915_reg_defs.h"
>  #include "display/intel_display_reg_defs.h"
>  
> @@ -1022,16 +1023,6 @@
>  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
>  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
>  
> -#define _TRANSA_CHICKEN2	 0xf0064
> -#define _TRANSB_CHICKEN2	 0xf1064
> -#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> -#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> -#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
> -#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
> -#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
> -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
> -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
> -
>  #define SOUTH_CHICKEN1		_MMIO(0xc2000)
>  #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
>  #define  FDIA_PHASE_SYNC_SHIFT_EN	18
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> new file mode 100644
> index 000000000000..4d91bc2dbb27
> --- /dev/null
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2025 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_COMMON_REG_H_
> +#define _INTEL_GMD_COMMON_REG_H_
> +
> +#define _TRANSA_CHICKEN2	 0xf0064
> +#define _TRANSB_CHICKEN2	 0xf1064
> +#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> +#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> +#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
> +#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
> +#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
> +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
> +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
> +
> +#endif

-- 
Jani Nikula, Intel

Re: [PATCH 02/19] drm/{i915, xe}: Extract South chicken registers

[Jani Nikula]

On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> Extract South Chicken registers to common header.
> This allows intel_pch_refclk.c not to include i915_reg.h

Why not intel_display_regs.h?

>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_pch_refclk.c   |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 27 -------------------
>  include/drm/intel/intel_gmd_common_regs.h     | 27 +++++++++++++++++++
>  3 files changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 9a89bb6dcf65..55abb97c6562 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -4,8 +4,8 @@
>   */
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f60259c41c56..c1f33c11ac1b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1023,33 +1023,6 @@
>  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
>  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
>  
> -#define SOUTH_CHICKEN1		_MMIO(0xc2000)
> -#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
> -#define  FDIA_PHASE_SYNC_SHIFT_EN	18
> -#define  INVERT_DDIE_HPD			REG_BIT(28)
> -#define  INVERT_DDID_HPD_MTP			REG_BIT(27)
> -#define  INVERT_TC4_HPD				REG_BIT(26)
> -#define  INVERT_TC3_HPD				REG_BIT(25)
> -#define  INVERT_TC2_HPD				REG_BIT(24)
> -#define  INVERT_TC1_HPD				REG_BIT(23)
> -#define  INVERT_DDID_HPD			(1 << 18)
> -#define  INVERT_DDIC_HPD			(1 << 17)
> -#define  INVERT_DDIB_HPD			(1 << 16)
> -#define  INVERT_DDIA_HPD			(1 << 15)
> -#define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
> -#define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
> -#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
> -#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
> -#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
> -#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
> -#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
> -#define  SPT_PWM_GRANULARITY		(1 << 0)
> -#define SOUTH_CHICKEN2		_MMIO(0xc2004)
> -#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
> -#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
> -#define  LPT_PWM_GRANULARITY		(1 << 5)
> -#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
> -
>  #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
>  #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
>  #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index 4d91bc2dbb27..b4cfd186d5c0 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -4,6 +4,33 @@
>  #ifndef _INTEL_GMD_COMMON_REG_H_
>  #define _INTEL_GMD_COMMON_REG_H_
>  
> +#define SOUTH_CHICKEN1		_MMIO(0xc2000)
> +#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
> +#define  FDIA_PHASE_SYNC_SHIFT_EN	18
> +#define  INVERT_DDIE_HPD			REG_BIT(28)
> +#define  INVERT_DDID_HPD_MTP			REG_BIT(27)
> +#define  INVERT_TC4_HPD				REG_BIT(26)
> +#define  INVERT_TC3_HPD				REG_BIT(25)
> +#define  INVERT_TC2_HPD				REG_BIT(24)
> +#define  INVERT_TC1_HPD				REG_BIT(23)
> +#define  INVERT_DDID_HPD			(1 << 18)
> +#define  INVERT_DDIC_HPD			(1 << 17)
> +#define  INVERT_DDIB_HPD			(1 << 16)
> +#define  INVERT_DDIA_HPD			(1 << 15)
> +#define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
> +#define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
> +#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
> +#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
> +#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
> +#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
> +#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
> +#define  SPT_PWM_GRANULARITY		(1 << 0)
> +#define SOUTH_CHICKEN2		_MMIO(0xc2004)
> +#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
> +#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
> +#define  LPT_PWM_GRANULARITY		(1 << 5)
> +#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
> +
>  #define _TRANSA_CHICKEN2	 0xf0064
>  #define _TRANSB_CHICKEN2	 0xf1064
>  #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

-- 
Jani Nikula, Intel

Re: [PATCH 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D

[Jani Nikula]

On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> Move DSPCLK_GATE_D register definition to common header.
> This allows intel_gmbus.c free of i915_reg.h include.

I think these too should be moved to intel_display_regs.h (or some
suitable new file) instead of include/drm/intel.

The intel_clock_gating.c users of the registers should be moved under
display/, though not necessarily in this series. For starters,
intel_clock_gating.c and gvt can include the necessary headers from
display/.

BR,
Jani.

>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_gmbus.c |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h            | 50 ----------------------
>  include/drm/intel/intel_gmd_common_regs.h  | 49 +++++++++++++++++++++
>  3 files changed, 50 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 2caff677600c..b77860c5d649 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -34,8 +34,8 @@
>  
>  #include <drm/drm_print.h>
>  #include <drm/display/drm_hdcp_helper.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a338f01a539b..30f504a47593 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -614,47 +614,6 @@
>  #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
>  #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
>  
> -#define DSPCLK_GATE_D			_MMIO(0x6200)
> -#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
> -# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
> -# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
> -# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
> -# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
> -# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
> -# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
> -# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
> -# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
> -# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
> -# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
> -# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
> -# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
> -# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
> -# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
> -# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
> -# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
> -# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
> -# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
> -# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
> -# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
> -# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
> -# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
> -# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
> -# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
> -# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
> -# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
> -# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
> -# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
> -# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
> -/*
> - * This bit must be set on the 830 to prevent hangs when turning off the
> - * overlay scaler.
> - */
> -# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
> -# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
> -# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
> -# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
> -# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
> -
>  #define RENCLK_GATE_D1		_MMIO(0x6204)
>  # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
>  # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
> @@ -990,15 +949,6 @@
>  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
>  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
>  
> -#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
> -#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
> -#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
> -#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
> -#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
> -#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
> -#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
> -#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
> -
>  #define  VLV_PMWGICZ				_MMIO(0x1300a4)
>  
>  #define  HSW_EDRAM_CAP				_MMIO(0x120010)
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index b4cfd186d5c0..fb2a327befd8 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -4,6 +4,46 @@
>  #ifndef _INTEL_GMD_COMMON_REG_H_
>  #define _INTEL_GMD_COMMON_REG_H_
>  
> +#define DSPCLK_GATE_D			_MMIO(0x6200)
> +#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
> +# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
> +# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
> +# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
> +# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
> +# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
> +# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
> +# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
> +# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
> +# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
> +# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
> +# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
> +# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
> +# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
> +# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
> +# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
> +# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
> +# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
> +# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
> +# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
> +# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
> +# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
> +# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
> +# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
> +# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
> +# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
> +# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
> +# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
> +# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
> +# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
> +/*
> + * This bit must be set on the 830 to prevent hangs when turning off the
> + * overlay scaler.
> + */
> +# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
> +# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
> +# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
> +# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
> +# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
>  #define SOUTH_CHICKEN1		_MMIO(0xc2000)
>  #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
>  #define  FDIA_PHASE_SYNC_SHIFT_EN	18
> @@ -31,6 +71,15 @@
>  #define  LPT_PWM_GRANULARITY		(1 << 5)
>  #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
>  
> +#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
> +#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
> +#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
> +#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
> +#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
> +#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
> +#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
> +#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
> +
>  #define _TRANSA_CHICKEN2	 0xf0064
>  #define _TRANSB_CHICKEN2	 0xf1064
>  #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

-- 
Jani Nikula, Intel

Re: [PATCH 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c

[Jani Nikula]

On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_dram.c free from including i915_reg.h.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h | 6 +++++-
>  drivers/gpu/drm/i915/display/intel_dram.c         | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h                   | 6 ------
>  3 files changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 8d0badea5cad..11952ce980ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2987,6 +2987,10 @@ enum skl_power_gate {
>  #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
>  #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
>  
> -
> +#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> +#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
> +#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
> +#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
> +#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
>  
>  #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
> index 019a722a38bf..f0e75fa5feb2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dram.c
> +++ b/drivers/gpu/drm/i915/display/intel_dram.c
> @@ -7,11 +7,12 @@
>  
>  #include <drm/drm_managed.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>

This isn't actually used here, is it?

>  
>  #include "i915_drv.h"
> -#include "i915_reg.h"
>  #include "intel_display_core.h"
>  #include "intel_display_utils.h"
> +#include "intel_display_regs.h"
>  #include "intel_dram.h"
>  #include "intel_mchbar_regs.h"
>  #include "intel_pcode.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fac24a649d61..c9fb9af1a35c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1005,12 +1005,6 @@
>  #define OROM_OFFSET				_MMIO(0x1020c0)
>  #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
>  
> -#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> -#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
> -#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
> -#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
> -#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> -
>  #define MTL_MEDIA_GSI_BASE		0x380000
>  
>  #endif /* _I915_REG_H_ */

-- 
Jani Nikula, Intel

Re: [PATCH 08/19] drm/{i915, xe}: Removed i915_reg.h from intel_display.c

[Jani Nikula]

On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> Move CHICKEN_PIPESL_1 to common header to free intel_display.c
> from including i915_reg.h

Same as before, I think this is display stuff that belongs under
display, intel_clock_gating.c parts that use it belong in display/ too,
and gvt can include the header directly.

BR,
Jani.

>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h              | 23 --------------------
>  include/drm/intel/intel_gmd_common_regs.h    | 23 ++++++++++++++++++++
>  3 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9c6d3ecdb589..ad2782d85074 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -45,13 +45,13 @@
>  #include <drm/drm_probe_helper.h>
>  #include <drm/drm_rect.h>
>  #include <drm/drm_vblank.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>  
>  #include "g4x_dp.h"
>  #include "g4x_hdmi.h"
>  #include "hsw_ips.h"
>  #include "i915_config.h"
>  #include "i915_drv.h"
> -#include "i915_reg.h"
>  #include "i9xx_plane.h"
>  #include "i9xx_plane_regs.h"
>  #include "i9xx_wm.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c9fb9af1a35c..e807be4a9962 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -878,29 +878,6 @@
>  #define CHICKEN_PAR2_1		_MMIO(0x42090)
>  #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
>  
> -#define _CHICKEN_PIPESL_1_A	0x420b0
> -#define _CHICKEN_PIPESL_1_B	0x420b4
> -#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
> -#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
> -#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
> -#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
> -#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
> -#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
> -#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
> -#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
> -#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
> -#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
> -#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
> -#define   HSW_FBCQ_DIS			REG_BIT(22)
> -#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
> -#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
> -#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
> -#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
> -#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
> -#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
> -#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
> -#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
> -
>  #define DISP_ARB_CTL	_MMIO(0x45000)
>  #define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
>  #define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index d4f91703e8a0..1908c203d54c 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -80,6 +80,29 @@
>  #define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
>  #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
>  
> +#define _CHICKEN_PIPESL_1_A	0x420b0
> +#define _CHICKEN_PIPESL_1_B	0x420b4
> +#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
> +#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
> +#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
> +#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
> +#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
> +#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
> +#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
> +#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
> +#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
> +#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
> +#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
> +#define   HSW_FBCQ_DIS			REG_BIT(22)
> +#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
> +#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
> +#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
> +#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
> +#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
> +#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
> +#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
> +#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
> +
>  #define _TRANSA_CHICKEN2	 0xf0064
>  #define _TRANSB_CHICKEN2	 0xf1064
>  #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

-- 
Jani Nikula, Intel

Re: [PATCH 00/19] Make Display free from i915_reg.h

[Jani Nikula]

On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> Move the common register definition to a header to free up
> display files from including i915_reg.h. This will help
> avoid dupicate definitions and includes and can serve as
> a common file for xe, i915 and display module.

So I commented on a number of patches, but I think the overall
impression is that we should avoid moving stuff to
intel_gmd_common_regs.h if at all possible.

There *may* be cases that benefit from having a file like that, but I
don't think most of these cases here require it.

BR,
Jani.

>
> Uma Shankar (19):
>   drm/{i915, xe}: Extract common registers into a separate file
>   drm/{i915, xe}: Extract South chicken registers
>   drm/{i915, xe}: Extract display interrupt definitions
>   drm/{i915, xe}: Extract DSPCLK_GATE_D
>   drm/{i915, xe}: Extract pcode definitions
>   drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c
>   drm/{i915, xe}: Remove i915_reg.h from intel_dram.c
>   drm/{i915, xe}: Removed i915_reg.h from intel_display.c
>   drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c
>   drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c
>   drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c
>   drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
>   drm/{i915, xe}: Remove i915_reg.h from intel_rom.c
>   drm/{i915, xe}: Remove i915_reg.h from intel_psr.c
>   drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c
>   drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c
>   drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c
>   drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c
>   drm/{i915, xe}: Removed i915_reg.h from display
>
>  drivers/gpu/drm/i915/display/g4x_dp.c         |   2 +-
>  drivers/gpu/drm/i915/display/g4x_hdmi.c       |   2 +-
>  drivers/gpu/drm/i915/display/hsw_ips.c        |   2 +-
>  drivers/gpu/drm/i915/display/i9xx_plane.c     |   2 +-
>  drivers/gpu/drm/i915/display/i9xx_wm.c        |   2 +-
>  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 +-
>  .../gpu/drm/i915/display/intel_backlight.c    |   2 +-
>  drivers/gpu/drm/i915/display/intel_bw.c       |   2 +-
>  drivers/gpu/drm/i915/display/intel_casf.c     |   1 -
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |   2 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |   2 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
>  .../drm/i915/display/intel_display_debugfs.c  |   2 +-
>  .../drm/i915/display/intel_display_device.c   |   2 +-
>  .../gpu/drm/i915/display/intel_display_irq.c  |   2 +-
>  .../drm/i915/display/intel_display_power.c    |   2 +-
>  .../i915/display/intel_display_power_well.c   |   2 +-
>  .../gpu/drm/i915/display/intel_display_regs.h |  90 +++-
>  .../gpu/drm/i915/display/intel_display_rps.c  |   2 +-
>  .../gpu/drm/i915/display/intel_display_wa.c   |   2 +-
>  drivers/gpu/drm/i915/display/intel_dmc.c      |   2 +-
>  drivers/gpu/drm/i915/display/intel_dram.c     |   3 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c      |   2 +-
>  .../drm/i915/display/intel_fifo_underrun.c    |   2 +-
>  drivers/gpu/drm/i915/display/intel_gmbus.c    |   2 +-
>  drivers/gpu/drm/i915/display/intel_hdcp.c     |   2 +-
>  .../gpu/drm/i915/display/intel_hotplug_irq.c  |   2 +-
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   |   2 +-
>  .../drm/i915/display/intel_modeset_setup.c    |   2 +-
>  drivers/gpu/drm/i915/display/intel_overlay.c  |   2 +-
>  .../gpu/drm/i915/display/intel_pch_display.c  |   2 +-
>  .../gpu/drm/i915/display/intel_pch_refclk.c   |   2 +-
>  drivers/gpu/drm/i915/display/intel_pps.c      |   2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      |   2 +-
>  drivers/gpu/drm/i915/display/intel_rom.c      |   4 +-
>  drivers/gpu/drm/i915/display/intel_tc.c       |   2 +-
>  drivers/gpu/drm/i915/display/skl_watermark.c  |   2 +-
>  drivers/gpu/drm/i915/display/vlv_dsi.c        |   2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 463 +-----------------
>  include/drm/intel/intel_gmd_common_regs.h     | 419 ++++++++++++++++
>  40 files changed, 534 insertions(+), 514 deletions(-)
>  create mode 100644 include/drm/intel/intel_gmd_common_regs.h

-- 
Jani Nikula, Intel

✗ Xe.CI.Full: failure for Make Display free from i915_reg.h

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 99001 bytes --]

== Series Details ==

Series: Make Display free from i915_reg.h
URL   : https://patchwork.freedesktop.org/series/159130/
State : failure

== Summary ==

CI Bug Log - changes from xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0_FULL -> xe-pw-159130v1_FULL
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with xe-pw-159130v1_FULL need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-159130v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-159130v1_FULL:

### IGT changes ###

#### Warnings ####

  * igt@kms_joiner@basic-big-joiner:
    - shard-lnl:          [SKIP][1] ([Intel XE#2925] / [Intel XE#346]) -> [SKIP][2] +1 other test skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-4/igt@kms_joiner@basic-big-joiner.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-5/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-bmg:          [SKIP][3] ([Intel XE#2934] / [Intel XE#6590]) -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-3/igt@kms_joiner@basic-force-ultra-joiner.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-lnl:          [SKIP][5] ([Intel XE#2925] / [Intel XE#2927]) -> [SKIP][6] +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-7/igt@kms_joiner@basic-ultra-joiner.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-7/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-lnl:          [SKIP][7] ([Intel XE#2925]) -> [SKIP][8] +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-2/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-5/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          [SKIP][9] ([Intel XE#6703]) -> [SKIP][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  
Known issues
------------

  Here are the changes found in xe-pw-159130v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@hotrebind:
    - shard-bmg:          [PASS][11] -> [SKIP][12] ([Intel XE#6779])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@core_hotunplug@hotrebind.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@core_hotunplug@hotrebind.html

  * igt@fbdev@unaligned-read:
    - shard-bmg:          [PASS][13] -> [SKIP][14] ([Intel XE#2134])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@fbdev@unaligned-read.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@fbdev@unaligned-read.html

  * igt@intel_hwmon@hwmon-write:
    - shard-bmg:          [PASS][15] -> [FAIL][16] ([Intel XE#4665])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@intel_hwmon@hwmon-write.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@intel_hwmon@hwmon-write.html

  * igt@kms_3d@basic:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#6011])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-1/igt@kms_3d@basic.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#1407])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-7/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2327])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#1124]) +4 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_bw@linear-tiling-4-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#367]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#2887]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-2/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2887]) +9 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_ccs@bad-rotation-90-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2652] / [Intel XE#787]) +21 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#3432])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2325])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2252]) +4 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2341])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-2/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][29] ([Intel XE#1178]) +1 other test fail
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_content_protection@suspend-resume:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#6705])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-7/igt@kms_content_protection@suspend-resume.html

  * igt@kms_cursor_crc@cursor-dpms:
    - shard-bmg:          [PASS][31] -> [SKIP][32] ([Intel XE#2320])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@kms_cursor_crc@cursor-dpms.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_cursor_crc@cursor-dpms.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2320]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_cursor_crc@cursor-onscreen-64x21.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2321])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2291])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-bmg:          [PASS][36] -> [SKIP][37] ([Intel XE#2291])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2286])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2244])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#4422])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#776])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2373])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
    - shard-bmg:          [PASS][43] -> [SKIP][44] ([Intel XE#2316]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2316])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1421]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-7/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][47] -> [FAIL][48] ([Intel XE#301]) +1 other test fail
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#2293] / [Intel XE#2380]) +2 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2293]) +5 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2311]) +16 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#4141]) +8 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#656]) +2 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#6703]) +256 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#651]) +2 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2313]) +10 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#2312]) +4 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2393])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#4596])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#5020])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-1/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#6886]) +8 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@package-g7:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#6693])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_pm_rpm@package-g7.html

  * igt@kms_pm_rpm@universal-planes-dpms:
    - shard-bmg:          [PASS][64] -> [SKIP][65] ([Intel XE#6693]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_pm_rpm@universal-planes-dpms.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_pm_rpm@universal-planes-dpms.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#1406] / [Intel XE#6703]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#1406] / [Intel XE#2387])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +8 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@kms_psr@fbc-psr-suspend.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#2330])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-bmg:          [PASS][72] -> [SKIP][73] ([Intel XE#1435]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaling-mode:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#6503])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@kms_sharpness_filter@invalid-filter-with-scaling-mode.html

  * igt@kms_vrr@flipline:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#1499])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_vrr@flipline.html

  * igt@xe_configfs@survivability-mode:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#6010])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-1/igt@xe_configfs@survivability-mode.html

  * igt@xe_eudebug@basic-exec-queues-enable:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#4837]) +5 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_eudebug@basic-exec-queues-enable.html

  * igt@xe_eudebug@discovery-empty-clients:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#4837])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-2/igt@xe_eudebug@discovery-empty-clients.html

  * igt@xe_eudebug_online@interrupt-all:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#4837] / [Intel XE#6665])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-3/igt@xe_eudebug_online@interrupt-all.html

  * igt@xe_eudebug_online@interrupt-other:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_eudebug_online@interrupt-other.html

  * igt@xe_eudebug_online@pagefault-one-of-many:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#6665])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_eudebug_online@pagefault-one-of-many.html

  * igt@xe_eudebug_online@pagefault-write-stress:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#6665] / [Intel XE#6681])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@xe_eudebug_online@pagefault-write-stress.html

  * igt@xe_evict@evict-beng-small-external-cm:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#688])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-3/igt@xe_evict@evict-beng-small-external-cm.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2322]) +4 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-null:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#1392])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-5/igt@xe_exec_basic@multigpu-no-exec-null.html

  * igt@xe_exec_basic@once-bindexecqueue-userptr-invalidate-race:
    - shard-bmg:          [PASS][86] -> [SKIP][87] ([Intel XE#6703]) +498 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@xe_exec_basic@once-bindexecqueue-userptr-invalidate-race.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_exec_basic@once-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-basic-smem:
    - shard-lnl:          NOTRUN -> [SKIP][88] ([Intel XE#6874])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-3/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-basic-smem.html

  * igt@xe_exec_multi_queue@two-queues-priority:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#6874]) +18 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@xe_exec_multi_queue@two-queues-priority.html

  * igt@xe_exec_system_allocator@process-many-large-new-nomemset:
    - shard-bmg:          [PASS][90] -> [SKIP][91] ([Intel XE#6557] / [Intel XE#6703]) +7 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@xe_exec_system_allocator@process-many-large-new-nomemset.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_exec_system_allocator@process-many-large-new-nomemset.html

  * igt@xe_exec_system_allocator@threads-many-mmap-free-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][92] ([Intel XE#4943]) +12 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@xe_exec_system_allocator@threads-many-mmap-free-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#4943]) +3 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-8/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#6557] / [Intel XE#6703]) +5 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-prefetch.html

  * igt@xe_live_ktest@xe_bo:
    - shard-bmg:          [PASS][95] -> [SKIP][96] ([Intel XE#2229]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@xe_live_ktest@xe_bo.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_live_ktest@xe_bo.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#2245])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@xe_pat@pat-index-xelp.html

  * igt@xe_peer2peer@write:
    - shard-bmg:          NOTRUN -> [SKIP][98] ([Intel XE#2427])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@xe_peer2peer@write.html

  * igt@xe_pmu@engine-activity-accuracy-50:
    - shard-lnl:          [PASS][99] -> [FAIL][100] ([Intel XE#6251]) +2 other tests fail
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-7/igt@xe_pmu@engine-activity-accuracy-50.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-5/igt@xe_pmu@engine-activity-accuracy-50.html

  * igt@xe_query@multigpu-query-engines:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#944])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@xe_query@multigpu-query-engines.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unplug-rescan:
    - shard-bmg:          [SKIP][102] ([Intel XE#6779]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@core_hotunplug@unplug-rescan.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@core_hotunplug@unplug-rescan.html

  * igt@core_setmaster@master-drop-set-shared-fd:
    - shard-bmg:          [SKIP][104] -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@core_setmaster@master-drop-set-shared-fd.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@core_setmaster@master-drop-set-shared-fd.html

  * igt@fbdev@eof:
    - shard-bmg:          [SKIP][106] ([Intel XE#2134]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@fbdev@eof.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@fbdev@eof.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-bmg:          [SKIP][108] ([Intel XE#2291]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [FAIL][110] ([Intel XE#5299]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-bmg:          [SKIP][112] ([Intel XE#2316]) -> [PASS][113] +3 other tests pass
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][114] ([Intel XE#301]) -> [PASS][115] +2 other tests pass
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a3:
    - shard-bmg:          [INCOMPLETE][116] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][117] +1 other test pass
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-3/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-bmg:          [SKIP][118] ([Intel XE#3012] / [Intel XE#6590]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-bmg:          [SKIP][120] ([Intel XE#4596]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-none.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-bmg:          [SKIP][122] ([Intel XE#6693]) -> [PASS][123] +1 other test pass
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_pm_rpm@system-suspend-modeset.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-lnl:          [SKIP][124] ([Intel XE#1406] / [Intel XE#4692]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@testdisplay:
    - shard-bmg:          [ABORT][126] -> [PASS][127]
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@testdisplay.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@testdisplay.html

  * igt@xe_exec_system_allocator@many-large-execqueues-mmap-new:
    - shard-bmg:          [SKIP][128] ([Intel XE#6703]) -> [PASS][129] +332 other tests pass
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_exec_system_allocator@many-large-execqueues-mmap-new.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@xe_exec_system_allocator@many-large-execqueues-mmap-new.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          [FAIL][130] ([Intel XE#5625]) -> [PASS][131]
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-4/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_exec_system_allocator@threads-many-stride-mmap-new-race:
    - shard-bmg:          [SKIP][132] ([Intel XE#6557] / [Intel XE#6703]) -> [PASS][133] +5 other tests pass
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-stride-mmap-new-race.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@xe_exec_system_allocator@threads-many-stride-mmap-new-race.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0:
    - shard-lnl:          [FAIL][134] ([Intel XE#6251]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-4/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html

  
#### Warnings ####

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-bmg:          [SKIP][136] ([Intel XE#6703]) -> [SKIP][137] ([Intel XE#2233])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-bmg:          [SKIP][138] ([Intel XE#6703]) -> [SKIP][139] ([Intel XE#2327])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_big_fb@linear-64bpp-rotate-90.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-bmg:          [SKIP][140] ([Intel XE#2327]) -> [SKIP][141] ([Intel XE#6703]) +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          [SKIP][142] ([Intel XE#6703]) -> [SKIP][143] ([Intel XE#1124]) +7 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
    - shard-bmg:          [SKIP][144] ([Intel XE#1124]) -> [SKIP][145] ([Intel XE#6703]) +9 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [SKIP][146] ([Intel XE#2314] / [Intel XE#2894]) -> [SKIP][147] ([Intel XE#6703])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
    - shard-bmg:          [SKIP][148] ([Intel XE#6703]) -> [SKIP][149] ([Intel XE#2314] / [Intel XE#2894])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          [SKIP][150] ([Intel XE#367]) -> [SKIP][151] ([Intel XE#6703]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-2160x1440p:
    - shard-bmg:          [SKIP][152] ([Intel XE#6703]) -> [SKIP][153] ([Intel XE#367])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs:
    - shard-bmg:          [SKIP][154] ([Intel XE#6703]) -> [SKIP][155] ([Intel XE#2887]) +6 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs:
    - shard-bmg:          [SKIP][156] ([Intel XE#2887]) -> [SKIP][157] ([Intel XE#6703]) +9 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-3/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][158] ([Intel XE#2652] / [Intel XE#787]) -> [SKIP][159] ([Intel XE#6703])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][160] ([Intel XE#6703]) -> [SKIP][161] ([Intel XE#2652] / [Intel XE#787])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          [SKIP][162] ([Intel XE#6703]) -> [SKIP][163] ([Intel XE#3432]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs:
    - shard-bmg:          [SKIP][164] ([Intel XE#3432]) -> [SKIP][165] ([Intel XE#6703]) +1 other test skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          [SKIP][166] ([Intel XE#2724]) -> [SKIP][167] ([Intel XE#6703])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@kms_cdclk@plane-scaling.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-bmg:          [SKIP][168] ([Intel XE#6703]) -> [SKIP][169] ([Intel XE#2325]) +3 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_chamelium_color@ctm-blue-to-red.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@degamma:
    - shard-bmg:          [SKIP][170] ([Intel XE#2325]) -> [SKIP][171] ([Intel XE#6703]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_chamelium_color@degamma.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_edid@dp-edid-read:
    - shard-bmg:          [SKIP][172] ([Intel XE#2252]) -> [SKIP][173] ([Intel XE#6703]) +8 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@kms_chamelium_edid@dp-edid-read.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_chamelium_edid@dp-edid-read.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-bmg:          [SKIP][174] ([Intel XE#6703]) -> [SKIP][175] ([Intel XE#2252]) +5 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_chamelium_edid@dp-edid-resolution-list.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-bmg:          [SKIP][176] ([Intel XE#2390]) -> [SKIP][177] ([Intel XE#6703])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_content_protection@dp-mst-type-1.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-bmg:          [SKIP][178] ([Intel XE#6703]) -> [SKIP][179] ([Intel XE#2341])
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_content_protection@mei-interface.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-bmg:          [SKIP][180] ([Intel XE#2341]) -> [SKIP][181] ([Intel XE#6703])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_content_protection@type1.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-bmg:          [SKIP][182] ([Intel XE#2320]) -> [SKIP][183] ([Intel XE#6703]) +3 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_cursor_crc@cursor-offscreen-32x32.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-bmg:          [SKIP][184] ([Intel XE#6703]) -> [SKIP][185] ([Intel XE#2320]) +4 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_cursor_crc@cursor-random-32x32.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-bmg:          [SKIP][186] ([Intel XE#2321]) -> [SKIP][187] ([Intel XE#6703]) +1 other test skip
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-bmg:          [SKIP][188] ([Intel XE#2291]) -> [SKIP][189] ([Intel XE#6703]) +2 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [SKIP][190] ([Intel XE#6703]) -> [FAIL][191] ([Intel XE#6715])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [SKIP][192] ([Intel XE#6703]) -> [FAIL][193] ([Intel XE#5299])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-toggle:
    - shard-bmg:          [FAIL][194] ([Intel XE#4633]) -> [SKIP][195] ([Intel XE#6703])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-bmg:          [SKIP][196] ([Intel XE#6703]) -> [SKIP][197] ([Intel XE#1508])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-bmg:          [SKIP][198] ([Intel XE#4331]) -> [SKIP][199] ([Intel XE#6703])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-basic:
    - shard-bmg:          [SKIP][200] ([Intel XE#2244]) -> [SKIP][201] ([Intel XE#6703])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_dsc@dsc-basic.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_dsc@dsc-basic.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-bmg:          [SKIP][202] ([Intel XE#4422]) -> [SKIP][203] ([Intel XE#6703])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_fbcon_fbt@psr:
    - shard-bmg:          [SKIP][204] ([Intel XE#6703]) -> [SKIP][205] ([Intel XE#776])
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_fbcon_fbt@psr.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@chamelium:
    - shard-bmg:          [SKIP][206] ([Intel XE#2372]) -> [SKIP][207] ([Intel XE#6703])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_feature_discovery@chamelium.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-3x:
    - shard-bmg:          [SKIP][208] ([Intel XE#2373]) -> [SKIP][209] ([Intel XE#6703])
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_feature_discovery@display-3x.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
    - shard-bmg:          [SKIP][210] ([Intel XE#2316]) -> [SKIP][211] ([Intel XE#6703]) +2 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-bmg:          [SKIP][212] ([Intel XE#6703]) -> [SKIP][213] ([Intel XE#2316]) +2 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@absolute-wf_vblank-interruptible:
    - shard-bmg:          [FAIL][214] ([Intel XE#3149] / [Intel XE#5352]) -> [SKIP][215] ([Intel XE#6703])
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_flip@absolute-wf_vblank-interruptible.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_flip@absolute-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-bmg:          [SKIP][216] ([Intel XE#2293] / [Intel XE#2380]) -> [SKIP][217] ([Intel XE#6703]) +2 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          [SKIP][218] ([Intel XE#2380]) -> [SKIP][219] ([Intel XE#6703])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-bmg:          [SKIP][220] ([Intel XE#6703]) -> [SKIP][221] ([Intel XE#2293] / [Intel XE#2380]) +2 other tests skip
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][222] ([Intel XE#2312]) -> [SKIP][223] ([Intel XE#6703]) +14 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-bmg:          [SKIP][224] ([Intel XE#2311]) -> [SKIP][225] ([Intel XE#6703]) +15 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][226] ([Intel XE#6703]) -> [SKIP][227] ([Intel XE#4141]) +9 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][228] ([Intel XE#4141]) -> [SKIP][229] ([Intel XE#2312])
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][230] ([Intel XE#2312]) -> [SKIP][231] ([Intel XE#4141]) +2 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][232] ([Intel XE#4141]) -> [SKIP][233] ([Intel XE#6703]) +6 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][234] ([Intel XE#2311]) -> [SKIP][235] ([Intel XE#2312]) +3 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt:
    - shard-bmg:          [SKIP][236] ([Intel XE#6703]) -> [SKIP][237] ([Intel XE#2311]) +8 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][238] ([Intel XE#2312]) -> [SKIP][239] ([Intel XE#2311]) +4 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-suspend:
    - shard-bmg:          [SKIP][240] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][241] ([Intel XE#2311])
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][242] ([Intel XE#2313]) -> [SKIP][243] ([Intel XE#6703]) +24 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][244] ([Intel XE#6703]) -> [SKIP][245] ([Intel XE#2313]) +17 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][246] ([Intel XE#2313]) -> [SKIP][247] ([Intel XE#2312]) +3 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][248] ([Intel XE#6703]) -> [SKIP][249] ([Intel XE#2312]) +5 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][250] ([Intel XE#2312]) -> [SKIP][251] ([Intel XE#2313]) +8 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-bmg:          [ABORT][252] ([Intel XE#6740]) -> [SKIP][253] ([Intel XE#6703])
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_hdr@bpc-switch-dpms.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-lnl:          [SKIP][254] ([Intel XE#2925]) -> [SKIP][255] ([Intel XE#4298])
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-lnl-5/igt@kms_joiner@basic-max-non-joiner.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-lnl-4/igt@kms_joiner@basic-max-non-joiner.html
    - shard-bmg:          [SKIP][256] ([Intel XE#6590]) -> [SKIP][257] ([Intel XE#4298])
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_joiner@basic-max-non-joiner.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          [SKIP][258] ([Intel XE#2934] / [Intel XE#6590]) -> [SKIP][259] ([Intel XE#6703])
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-bmg:          [SKIP][260] ([Intel XE#2927] / [Intel XE#6590]) -> [SKIP][261] ([Intel XE#6703])
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_joiner@invalid-modeset-ultra-joiner.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-bmg:          [SKIP][262] ([Intel XE#2501]) -> [SKIP][263] ([Intel XE#6703])
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@legacy:
    - shard-bmg:          [SKIP][264] ([Intel XE#2486]) -> [SKIP][265] ([Intel XE#6703])
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@kms_panel_fitting@legacy.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-bmg:          [SKIP][266] ([Intel XE#2393]) -> [SKIP][267] ([Intel XE#6703])
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_plane_lowres@tiling-yf.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          [SKIP][268] ([Intel XE#4596]) -> [SKIP][269] ([Intel XE#6703])
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-y.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-bmg:          [SKIP][270] ([Intel XE#2571]) -> [SKIP][271] ([Intel XE#6703])
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75:
    - shard-bmg:          [SKIP][272] ([Intel XE#6703]) -> [SKIP][273] ([Intel XE#6886])
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_plane_scaling@planes-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-bmg:          [SKIP][274] ([Intel XE#6886]) -> [SKIP][275] ([Intel XE#6703])
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-bmg:          [SKIP][276] ([Intel XE#2499]) -> [SKIP][277] ([Intel XE#6703])
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_pm_lpsp@kms-lpsp.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-bmg:          [SKIP][278] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) -> [SKIP][279] ([Intel XE#6693])
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_pm_rpm@dpms-lpsp.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-bmg:          [SKIP][280] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][281] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area:
    - shard-bmg:          [SKIP][282] ([Intel XE#1406] / [Intel XE#1489]) -> [SKIP][283] ([Intel XE#1406] / [Intel XE#6703]) +9 other tests skip
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-bmg:          [SKIP][284] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][285] ([Intel XE#1406] / [Intel XE#2387])
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@psr-primary-page-flip:
    - shard-bmg:          [SKIP][286] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][287] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_psr@psr-primary-page-flip.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_psr@psr2-primary-page-flip:
    - shard-bmg:          [SKIP][288] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) -> [SKIP][289] ([Intel XE#1406] / [Intel XE#6703]) +10 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_psr@psr2-primary-page-flip.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_psr@psr2-primary-page-flip.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-bmg:          [SKIP][290] ([Intel XE#1406] / [Intel XE#2414]) -> [SKIP][291] ([Intel XE#1406] / [Intel XE#6703])
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-bmg:          [SKIP][292] ([Intel XE#2330]) -> [SKIP][293] ([Intel XE#6703])
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-bmg:          [SKIP][294] ([Intel XE#3414] / [Intel XE#3904]) -> [SKIP][295] ([Intel XE#6703]) +1 other test skip
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-bmg:          [SKIP][296] ([Intel XE#6703]) -> [SKIP][297] ([Intel XE#3414] / [Intel XE#3904])
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-bmg:          [SKIP][298] ([Intel XE#6703]) -> [SKIP][299] ([Intel XE#1435])
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_setmode@invalid-clone-exclusive-crtc.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@filter-formats:
    - shard-bmg:          [SKIP][300] ([Intel XE#6503]) -> [SKIP][301] ([Intel XE#6703]) +3 other tests skip
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-3/igt@kms_sharpness_filter@filter-formats.html
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_sharpness_filter@filter-formats.html

  * igt@kms_sharpness_filter@invalid-filter-with-plane:
    - shard-bmg:          [SKIP][302] ([Intel XE#6703]) -> [SKIP][303] ([Intel XE#6503])
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@kms_sharpness_filter@invalid-filter-with-plane.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@kms_sharpness_filter@invalid-filter-with-plane.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          [SKIP][304] ([Intel XE#1499]) -> [SKIP][305] ([Intel XE#6703])
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@kms_vrr@seamless-rr-switch-drrs.html
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_compute@ccs-mode-basic:
    - shard-bmg:          [SKIP][306] ([Intel XE#6599]) -> [SKIP][307] ([Intel XE#6703])
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@xe_compute@ccs-mode-basic.html
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_compute@ccs-mode-basic.html

  * igt@xe_eudebug@basic-vm-access-userptr:
    - shard-bmg:          [SKIP][308] ([Intel XE#4837]) -> [SKIP][309] ([Intel XE#6703]) +5 other tests skip
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@xe_eudebug@basic-vm-access-userptr.html
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_eudebug@basic-vm-access-userptr.html

  * igt@xe_eudebug@basic-vm-bind-ufence-sigint-client:
    - shard-bmg:          [SKIP][310] ([Intel XE#6703]) -> [SKIP][311] ([Intel XE#4837]) +1 other test skip
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_eudebug@basic-vm-bind-ufence-sigint-client.html
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@xe_eudebug@basic-vm-bind-ufence-sigint-client.html

  * igt@xe_eudebug_online@breakpoint-many-sessions-tiles:
    - shard-bmg:          [SKIP][312] ([Intel XE#4837] / [Intel XE#6665]) -> [SKIP][313] ([Intel XE#6703]) +5 other tests skip
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@xe_eudebug_online@breakpoint-many-sessions-tiles.html
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_eudebug_online@breakpoint-many-sessions-tiles.html

  * igt@xe_eudebug_online@pagefault-read-stress:
    - shard-bmg:          [SKIP][314] ([Intel XE#6703]) -> [SKIP][315] ([Intel XE#6665] / [Intel XE#6681])
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_eudebug_online@pagefault-read-stress.html
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@xe_eudebug_online@pagefault-read-stress.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram:
    - shard-bmg:          [SKIP][316] ([Intel XE#6703]) -> [SKIP][317] ([Intel XE#4837] / [Intel XE#6665]) +4 other tests skip
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram.html
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-sram.html

  * igt@xe_eudebug_sriov@deny-eudebug:
    - shard-bmg:          [SKIP][318] ([Intel XE#5793]) -> [SKIP][319] ([Intel XE#6703])
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@xe_eudebug_sriov@deny-eudebug.html
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_eudebug_sriov@deny-eudebug.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
    - shard-bmg:          [SKIP][320] ([Intel XE#2322]) -> [SKIP][321] ([Intel XE#6703]) +7 other tests skip
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
    - shard-bmg:          [SKIP][322] ([Intel XE#6703]) -> [SKIP][323] ([Intel XE#2322]) +5 other tests skip
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-priority:
    - shard-bmg:          [SKIP][324] ([Intel XE#6703]) -> [SKIP][325] ([Intel XE#6874]) +15 other tests skip
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_exec_multi_queue@few-execs-preempt-mode-priority.html
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_exec_multi_queue@few-execs-preempt-mode-priority.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate:
    - shard-bmg:          [SKIP][326] ([Intel XE#6874]) -> [SKIP][327] ([Intel XE#6703]) +24 other tests skip
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate.html
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate.html

  * igt@xe_exec_system_allocator@many-64k-mmap-free-huge-nomemset:
    - shard-bmg:          [SKIP][328] ([Intel XE#6703]) -> [SKIP][329] ([Intel XE#5007])
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_exec_system_allocator@many-64k-mmap-free-huge-nomemset.html
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_exec_system_allocator@many-64k-mmap-free-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-many-execqueues-mmap-new-huge:
    - shard-bmg:          [SKIP][330] ([Intel XE#6703]) -> [SKIP][331] ([Intel XE#4943]) +13 other tests skip
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-new-huge.html
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-new-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge:
    - shard-bmg:          [SKIP][332] ([Intel XE#4943]) -> [SKIP][333] ([Intel XE#6703]) +19 other tests skip
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge.html
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          [SKIP][334] ([Intel XE#6703]) -> [SKIP][335] ([Intel XE#6281])
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-bmg:          [SKIP][336] ([Intel XE#6703]) -> [ABORT][337] ([Intel XE#5466])
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          [SKIP][338] ([Intel XE#2459] / [Intel XE#2596]) -> [SKIP][339] ([Intel XE#6703])
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@xe_media_fill@media-fill.html
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_media_fill@media-fill.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          [SKIP][340] ([Intel XE#586]) -> [SKIP][341] ([Intel XE#6703])
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@xe_mmap@small-bar.html
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_mmap@small-bar.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][342], [PASS][343], [PASS][344], [PASS][345], [PASS][346], [PASS][347], [SKIP][348], [PASS][349], [ABORT][350], [ABORT][351], [PASS][352], [ABORT][353], [PASS][354], [PASS][355], [PASS][356], [PASS][357], [PASS][358], [PASS][359], [PASS][360], [PASS][361], [PASS][362], [PASS][363], [PASS][364], [PASS][365], [PASS][366]) ([Intel XE#2457] / [Intel XE#6887]) -> ([PASS][367], [PASS][368], [ABORT][369], [PASS][370], [PASS][371], [PASS][372], [PASS][373], [PASS][374], [PASS][375], [PASS][376], [PASS][377], [PASS][378], [PASS][379], [PASS][380], [ABORT][381], [ABORT][382], [ABORT][383], [PASS][384], [PASS][385], [PASS][386], [PASS][387], [PASS][388], [PASS][389], [PASS][390], [PASS][391], [SKIP][392]) ([Intel XE#2457] / [Intel XE#6818])
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@xe_module_load@load.html
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_module_load@load.html
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@xe_module_load@load.html
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@xe_module_load@load.html
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@xe_module_load@load.html
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@xe_module_load@load.html
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@xe_module_load@load.html
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-3/igt@xe_module_load@load.html
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-6/igt@xe_module_load@load.html
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-6/igt@xe_module_load@load.html
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-7/igt@xe_module_load@load.html
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-6/igt@xe_module_load@load.html
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-3/igt@xe_module_load@load.html
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@xe_module_load@load.html
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@xe_module_load@load.html
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_module_load@load.html
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@xe_module_load@load.html
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_module_load@load.html
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_module_load@load.html
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_module_load@load.html
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@xe_module_load@load.html
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-1/igt@xe_module_load@load.html
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@xe_module_load@load.html
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@xe_module_load@load.html
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-2/igt@xe_module_load@load.html
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@xe_module_load@load.html
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_module_load@load.html
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-6/igt@xe_module_load@load.html
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@xe_module_load@load.html
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@xe_module_load@load.html
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_module_load@load.html
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-2/igt@xe_module_load@load.html
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@xe_module_load@load.html
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@xe_module_load@load.html
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_module_load@load.html
   [377]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-8/igt@xe_module_load@load.html
   [378]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_module_load@load.html
   [379]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_module_load@load.html
   [380]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_module_load@load.html
   [381]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-6/igt@xe_module_load@load.html
   [382]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-6/igt@xe_module_load@load.html
   [383]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-6/igt@xe_module_load@load.html
   [384]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@xe_module_load@load.html
   [385]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@xe_module_load@load.html
   [386]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-3/igt@xe_module_load@load.html
   [387]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_module_load@load.html
   [388]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@xe_module_load@load.html
   [389]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-7/igt@xe_module_load@load.html
   [390]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_module_load@load.html
   [391]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_module_load@load.html
   [392]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_module_load@load.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-bmg:          [SKIP][393] ([Intel XE#1420]) -> [SKIP][394] ([Intel XE#6703])
   [393]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@xe_pat@pat-index-xehpc.html
   [394]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-bmg:          [SKIP][395] ([Intel XE#6703]) -> [SKIP][396] ([Intel XE#2236])
   [395]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_pat@pat-index-xelpg.html
   [396]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-bmg:          [SKIP][397] ([Intel XE#4733]) -> [SKIP][398] ([Intel XE#6703]) +2 other tests skip
   [397]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-8/igt@xe_pxp@display-pxp-fb.html
   [398]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_pxp@pxp-optout:
    - shard-bmg:          [SKIP][399] ([Intel XE#6703]) -> [SKIP][400] ([Intel XE#4733]) +1 other test skip
   [399]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_pxp@pxp-optout.html
   [400]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-1/igt@xe_pxp@pxp-optout.html

  * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
    - shard-bmg:          [SKIP][401] ([Intel XE#944]) -> [SKIP][402] ([Intel XE#6703]) +2 other tests skip
   [401]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-4/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html
   [402]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-5/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html

  * igt@xe_query@multigpu-query-pxp-status:
    - shard-bmg:          [SKIP][403] ([Intel XE#6703]) -> [SKIP][404] ([Intel XE#944])
   [403]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0/shard-bmg-5/igt@xe_query@multigpu-query-pxp-status.html
   [404]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/shard-bmg-4/igt@xe_query@multigpu-query-pxp-status.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2501
  [Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4665
  [Intel XE#4692]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4692
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5352
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#6010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6010
  [Intel XE#6011]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6011
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6590
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6681]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6681
  [Intel XE#6693]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6693
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6705
  [Intel XE#6715]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6715
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#6779]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6779
  [Intel XE#6818]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6818
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6887
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8668 -> IGT_8669
  * Linux: xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0 -> xe-pw-159130v1

  IGT_8668: 906681747a312ef11ef9af8ab1fa6eff28b4cbd0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8669: 319db2ffba419f9711acc72895f065a818905efa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4255-2eb2f8746a879f1c0e4c56b715c179424dafd8e0: 2eb2f8746a879f1c0e4c56b715c179424dafd8e0
  xe-pw-159130v1: 159130v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v1/index.html

[-- Attachment #2: Type: text/html, Size: 123261 bytes --]

RE: [PATCH 01/19] drm/{i915, xe}: Extract common registers into a separate file

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Wednesday, December 17, 2025 7:28 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH 01/19] drm/{i915, xe}: Extract common registers into a
> separate file
> 
> On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> > There are certain register definitions which are commonly shared by
> > i915, xe and display. Extract the same to a common header to avoid
> > duplication.
> 
> I think TRANS_CHICKEN2 should be moved to intel_display_regs.h instead of
> something under include/drm/intel. The goal is that the display specific parts of
> intel_clock_gating.c should be moved there too.

Oh ok, got it Jani.
Will update this and send out a next version.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> 
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_pch_display.c    |  2 +-
> >  drivers/gpu/drm/i915/i915_reg.h                 | 11 +----------
> >  include/drm/intel/intel_gmd_common_regs.h       | 17 +++++++++++++++++
> >  3 files changed, 19 insertions(+), 11 deletions(-)  create mode
> > 100644 include/drm/intel/intel_gmd_common_regs.h
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > index 16619f7be5f8..2f39ff32c6d5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> > @@ -4,9 +4,9 @@
> >   */
> >
> >  #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >
> >  #include "g4x_dp.h"
> > -#include "i915_reg.h"
> >  #include "intel_crt.h"
> >  #include "intel_crt_regs.h"
> >  #include "intel_de.h"
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 5bf3b4ab2baa..f60259c41c56
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -25,6 +25,7 @@
> >  #ifndef _I915_REG_H_
> >  #define _I915_REG_H_
> >
> > +#include <drm/intel/intel_gmd_common_regs.h>
> >  #include "i915_reg_defs.h"
> >  #include "display/intel_display_reg_defs.h"
> >
> > @@ -1022,16 +1023,6 @@
> >  #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
> >  #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
> >
> > -#define _TRANSA_CHICKEN2	 0xf0064
> > -#define _TRANSB_CHICKEN2	 0xf1064
> > -#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe,
> _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> > -#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> > -#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED
> 	REG_BIT(29)
> > -#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK
> 	REG_GENMASK(28, 27)
> > -#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)
> 	REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK,
> (x)) /* 0-3 */
> > -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
> 	REG_BIT(26)
> > -#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
> 	REG_BIT(25)
> > -
> >  #define SOUTH_CHICKEN1		_MMIO(0xc2000)
> >  #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
> >  #define  FDIA_PHASE_SYNC_SHIFT_EN	18
> > diff --git a/include/drm/intel/intel_gmd_common_regs.h
> > b/include/drm/intel/intel_gmd_common_regs.h
> > new file mode 100644
> > index 000000000000..4d91bc2dbb27
> > --- /dev/null
> > +++ b/include/drm/intel/intel_gmd_common_regs.h
> > @@ -0,0 +1,17 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/* Copyright © 2025 Intel Corporation */
> > +
> > +#ifndef _INTEL_GMD_COMMON_REG_H_
> > +#define _INTEL_GMD_COMMON_REG_H_
> > +
> > +#define _TRANSA_CHICKEN2	 0xf0064
> > +#define _TRANSB_CHICKEN2	 0xf1064
> > +#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe,
> _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> > +#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
> > +#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED
> 	REG_BIT(29)
> > +#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK
> 	REG_GENMASK(28, 27)
> > +#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)
> 	REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK,
> (x)) /* 0-3 */
> > +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
> 	REG_BIT(26)
> > +#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
> 	REG_BIT(25)
> > +
> > +#endif
> 
> --
> Jani Nikula, Intel

RE: [PATCH 00/19] Make Display free from i915_reg.h

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Wednesday, December 17, 2025 7:36 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH 00/19] Make Display free from i915_reg.h
> 
> On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move the common register definition to a header to free up display
> > files from including i915_reg.h. This will help avoid dupicate
> > definitions and includes and can serve as a common file for xe, i915
> > and display module.
> 
> So I commented on a number of patches, but I think the overall impression is that
> we should avoid moving stuff to intel_gmd_common_regs.h if at all possible.
> 
> There *may* be cases that benefit from having a file like that, but I don't think
> most of these cases here require it.

Thanks Jani for the feedback and review.
I will re-check and review all these again and re-send a new version.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> >
> > Uma Shankar (19):
> >   drm/{i915, xe}: Extract common registers into a separate file
> >   drm/{i915, xe}: Extract South chicken registers
> >   drm/{i915, xe}: Extract display interrupt definitions
> >   drm/{i915, xe}: Extract DSPCLK_GATE_D
> >   drm/{i915, xe}: Extract pcode definitions
> >   drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c
> >   drm/{i915, xe}: Remove i915_reg.h from intel_dram.c
> >   drm/{i915, xe}: Removed i915_reg.h from intel_display.c
> >   drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c
> >   drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c
> >   drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c
> >   drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
> >   drm/{i915, xe}: Remove i915_reg.h from intel_rom.c
> >   drm/{i915, xe}: Remove i915_reg.h from intel_psr.c
> >   drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c
> >   drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c
> >   drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c
> >   drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c
> >   drm/{i915, xe}: Removed i915_reg.h from display
> >
> >  drivers/gpu/drm/i915/display/g4x_dp.c         |   2 +-
> >  drivers/gpu/drm/i915/display/g4x_hdmi.c       |   2 +-
> >  drivers/gpu/drm/i915/display/hsw_ips.c        |   2 +-
> >  drivers/gpu/drm/i915/display/i9xx_plane.c     |   2 +-
> >  drivers/gpu/drm/i915/display/i9xx_wm.c        |   2 +-
> >  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 +-
> >  .../gpu/drm/i915/display/intel_backlight.c    |   2 +-
> >  drivers/gpu/drm/i915/display/intel_bw.c       |   2 +-
> >  drivers/gpu/drm/i915/display/intel_casf.c     |   1 -
> >  drivers/gpu/drm/i915/display/intel_cdclk.c    |   2 +-
> >  drivers/gpu/drm/i915/display/intel_ddi.c      |   2 +-
> >  drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
> >  .../drm/i915/display/intel_display_debugfs.c  |   2 +-
> >  .../drm/i915/display/intel_display_device.c   |   2 +-
> >  .../gpu/drm/i915/display/intel_display_irq.c  |   2 +-
> >  .../drm/i915/display/intel_display_power.c    |   2 +-
> >  .../i915/display/intel_display_power_well.c   |   2 +-
> >  .../gpu/drm/i915/display/intel_display_regs.h |  90 +++-
> >  .../gpu/drm/i915/display/intel_display_rps.c  |   2 +-
> >  .../gpu/drm/i915/display/intel_display_wa.c   |   2 +-
> >  drivers/gpu/drm/i915/display/intel_dmc.c      |   2 +-
> >  drivers/gpu/drm/i915/display/intel_dram.c     |   3 +-
> >  drivers/gpu/drm/i915/display/intel_fdi.c      |   2 +-
> >  .../drm/i915/display/intel_fifo_underrun.c    |   2 +-
> >  drivers/gpu/drm/i915/display/intel_gmbus.c    |   2 +-
> >  drivers/gpu/drm/i915/display/intel_hdcp.c     |   2 +-
> >  .../gpu/drm/i915/display/intel_hotplug_irq.c  |   2 +-
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c   |   2 +-
> >  .../drm/i915/display/intel_modeset_setup.c    |   2 +-
> >  drivers/gpu/drm/i915/display/intel_overlay.c  |   2 +-
> >  .../gpu/drm/i915/display/intel_pch_display.c  |   2 +-
> >  .../gpu/drm/i915/display/intel_pch_refclk.c   |   2 +-
> >  drivers/gpu/drm/i915/display/intel_pps.c      |   2 +-
> >  drivers/gpu/drm/i915/display/intel_psr.c      |   2 +-
> >  drivers/gpu/drm/i915/display/intel_rom.c      |   4 +-
> >  drivers/gpu/drm/i915/display/intel_tc.c       |   2 +-
> >  drivers/gpu/drm/i915/display/skl_watermark.c  |   2 +-
> >  drivers/gpu/drm/i915/display/vlv_dsi.c        |   2 +-
> >  drivers/gpu/drm/i915/i915_reg.h               | 463 +-----------------
> >  include/drm/intel/intel_gmd_common_regs.h     | 419 ++++++++++++++++
> >  40 files changed, 534 insertions(+), 514 deletions(-)  create mode
> > 100644 include/drm/intel/intel_gmd_common_regs.h
> 
> --
> Jani Nikula, Intel