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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Gustavo Sousa <gustavo.sousa@intel.com>,
	 Matt Roper <matthew.d.roper@intel.com>,
	 Suraj Kandpal <suraj.kandpal@intel.com>
Subject: [PATCH v2 14/15] drm/i915/nvlp: Hook up display support
Date: Thu, 05 Feb 2026 20:39:42 -0300	[thread overview]
Message-ID: <20260205-nvl-p-upstreaming-v2-14-9ec14f00cc6c@intel.com> (raw)
In-Reply-To: <20260205-nvl-p-upstreaming-v2-0-9ec14f00cc6c@intel.com>

From: Matt Roper <matthew.d.roper@intel.com>

Although NVL-S and NVL-P are quite different on the GT side, they use
identical Xe3p_LPD display IP and should take all the same codepaths.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 471f236c9ddf..1a7f3ca079e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1500,6 +1500,7 @@ static const struct {
 	INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
 	INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
+	INTEL_NVLP_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
 };
 
 static const struct {

-- 
2.52.0


  parent reply	other threads:[~2026-02-05 23:40 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
2026-02-06 15:26   ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10 Gustavo Sousa
2026-02-06 15:25   ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 03/15] drm/xe/pat: Differentiate between primary and media for PTA Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 04/15] drm/xe/xe3p_lpg: Add new PAT table Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 05/15] drm/xe/xe3p_lpg: Add MCR steering Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 06/15] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 07/15] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 08/15] drm/xe/xe3p_lpg: Drop unnecessary tuning settings Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 09/15] drm/xe/xe3p_lpg: Extend 'group ID' mask size Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 10/15] drm/xe/xe3p_lpg: Update LRC sizes Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 11/15] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 12/15] drm/xe/nvlp: Add NVL-P platform definition Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 13/15] drm/xe/nvlp: Attach MOCS table for nvlp Gustavo Sousa
2026-02-05 23:39 ` Gustavo Sousa [this message]
2026-02-05 23:39 ` [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size Gustavo Sousa
2026-02-06  8:39   ` Bhadane, Dnyaneshwar
2026-02-05 23:47 ` ✗ CI.checkpatch: warning for Basic enabling patches for Xe3p_LPG and NVL-P (rev2) Patchwork
2026-02-05 23:48 ` ✓ CI.KUnit: success " Patchwork
2026-02-06  0:04 ` ✗ CI.checksparse: warning " Patchwork
2026-02-06  0:47 ` ✓ Xe.CI.BAT: success " Patchwork

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