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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Gustavo Sousa <gustavo.sousa@intel.com>,
	 Matt Roper <matthew.d.roper@intel.com>,
	 Matt Atwood <matthew.s.atwood@intel.com>
Subject: [PATCH v2 07/15] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP
Date: Thu, 05 Feb 2026 20:39:35 -0300	[thread overview]
Message-ID: <20260205-nvl-p-upstreaming-v2-7-9ec14f00cc6c@intel.com> (raw)
In-Reply-To: <20260205-nvl-p-upstreaming-v2-0-9ec14f00cc6c@intel.com>

From: Matt Roper <matthew.d.roper@intel.com>

By default the hardware reports context switch status into the global
hardware status page.  The Xe driver doesn't use this information for
anything, and as of Xe3p, leaving this setting enabled will prevent
other hardware optimizations from being enabled.  Disable this reporting
as suggested by the tuning guide.

Bspec: 72161
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/xe/xe_tuning.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 5766fa7742d3..a97872b3214b 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -10,6 +10,7 @@
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
 
+#include "regs/xe_engine_regs.h"
 #include "regs/xe_gt_regs.h"
 #include "xe_gt_types.h"
 #include "xe_platform_types.h"
@@ -107,6 +108,12 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(RT_CTRL, DIS_NULL_QUERY))
 	},
+	{ XE_RTP_NAME("Tuning: disable HW reporting of ctx switch to GHWSP"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3500, XE_RTP_END_VERSION_UNDEFINED)),
+	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
+			     GHWSP_CSB_REPORT_DIS,
+			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+	},
 };
 
 static const struct xe_rtp_entry_sr lrc_tunings[] = {

-- 
2.52.0


  parent reply	other threads:[~2026-02-05 23:40 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
2026-02-06 15:26   ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10 Gustavo Sousa
2026-02-06 15:25   ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 03/15] drm/xe/pat: Differentiate between primary and media for PTA Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 04/15] drm/xe/xe3p_lpg: Add new PAT table Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 05/15] drm/xe/xe3p_lpg: Add MCR steering Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 06/15] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state Gustavo Sousa
2026-02-05 23:39 ` Gustavo Sousa [this message]
2026-02-05 23:39 ` [PATCH v2 08/15] drm/xe/xe3p_lpg: Drop unnecessary tuning settings Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 09/15] drm/xe/xe3p_lpg: Extend 'group ID' mask size Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 10/15] drm/xe/xe3p_lpg: Update LRC sizes Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 11/15] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 12/15] drm/xe/nvlp: Add NVL-P platform definition Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 13/15] drm/xe/nvlp: Attach MOCS table for nvlp Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 14/15] drm/i915/nvlp: Hook up display support Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size Gustavo Sousa
2026-02-06  8:39   ` Bhadane, Dnyaneshwar
2026-02-05 23:47 ` ✗ CI.checkpatch: warning for Basic enabling patches for Xe3p_LPG and NVL-P (rev2) Patchwork
2026-02-05 23:48 ` ✓ CI.KUnit: success " Patchwork
2026-02-06  0:04 ` ✗ CI.checksparse: warning " Patchwork
2026-02-06  0:47 ` ✓ Xe.CI.BAT: success " Patchwork

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