From: Matt Roper <matthew.d.roper@intel.com>
To: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: <intel-xe@lists.freedesktop.org>,
<intel-gfx@lists.freedesktop.org>,
Shekhar Chauhan <shekhar.chauhan@intel.com>,
Nitin Gote <nitin.r.gote@intel.com>,
Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>,
Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Subject: Re: [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10
Date: Fri, 6 Feb 2026 07:25:15 -0800 [thread overview]
Message-ID: <20260206152515.GL2174980@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20260205-nvl-p-upstreaming-v2-2-9ec14f00cc6c@intel.com>
On Thu, Feb 05, 2026 at 08:39:30PM -0300, Gustavo Sousa wrote:
> From: Shekhar Chauhan <shekhar.chauhan@intel.com>
>
> Add the initial set of workarounds for Xe3p_LPG graphics version 35.10.
>
> v2:
> - Fix spacing style for field LOCALITYDIS. (Matt)
> - Drop unnecessary Wa_14025780377. (Matt)
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Co-developed-by: Nitin Gote <nitin.r.gote@intel.com>
> Signed-off-by: Nitin Gote <nitin.r.gote@intel.com>
> Co-developed-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> Signed-off-by: Tangudu Tilak Tirumalesh <tilak.tirumalesh.tangudu@intel.com>
> Co-developed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 16 +++++++++++++
> drivers/gpu/drm/xe/xe_reg_whitelist.c | 8 +++++++
> drivers/gpu/drm/xe/xe_wa.c | 43 +++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 24fc64fc832e..55f5be7283db 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -100,6 +100,9 @@
> #define VE1_AUX_INV XE_REG(0x42b8)
> #define AUX_INV REG_BIT(0)
>
> +#define GAMSTLB_CTRL2 XE_REG_MCR(0x4788)
> +#define STLB_SINGLE_BANK_MODE REG_BIT(11)
> +
> #define XE2_LMEM_CFG XE_REG(0x48b0)
>
> #define XE2_GAMWALK_CTRL 0x47e4
> @@ -107,6 +110,9 @@
> #define XE2_GAMWALK_CTRL_3D XE_REG_MCR(XE2_GAMWALK_CTRL)
> #define EN_CMP_1WCOH_GW REG_BIT(14)
>
> +#define MMIOATSREQLIMIT_GAM_WALK_3D XE_REG_MCR(0x47f8)
> +#define DIS_ATS_WRONLY_PG REG_BIT(18)
> +
> #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
> #define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8)
>
> @@ -210,6 +216,9 @@
>
> #define GSCPSMI_BASE XE_REG(0x880c)
>
> +#define CCCHKNREG2 XE_REG_MCR(0x881c)
> +#define LOCALITYDIS REG_BIT(7)
> +
> #define CCCHKNREG1 XE_REG_MCR(0x8828)
> #define L3CMPCTRL REG_BIT(23)
> #define ENCOMPPERFFIX REG_BIT(18)
> @@ -420,6 +429,8 @@
> #define LSN_DIM_Z_WGT(value) REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
>
> #define L3SQCREG2 XE_REG_MCR(0xb104)
> +#define L3_SQ_DISABLE_COAMA_2WAY_COH REG_BIT(30)
> +#define L3_SQ_DISABLE_COAMA REG_BIT(22)
> #define COMPMEMRD256BOVRFETCHEN REG_BIT(20)
>
> #define L3SQCREG3 XE_REG_MCR(0xb108)
> @@ -550,11 +561,16 @@
> #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32)
> #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
> #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32)
> +#define SAMPLER_LD_LSC_DISABLE REG_BIT(45 - 32)
> #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32)
> #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
> #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
> #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
> #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
> +#define LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE REG_BIT(35 - 32)
> +
> +#define ROW_CHICKEN5 XE_REG_MCR(0xe7f0)
> +#define CPSS_AWARE_DIS REG_BIT(3)
>
> #define SARB_CHICKEN1 XE_REG_MCR(0xe90c)
> #define COMP_CKN_IN REG_GENMASK(30, 29)
> diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> index 1d36c09681aa..9c513778d370 100644
> --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
> +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
> @@ -81,6 +81,14 @@ static const struct xe_rtp_entry_sr register_whitelist[] = {
> WHITELIST(VFLSKPD,
> RING_FORCE_TO_NONPRIV_ACCESS_RW))
> },
> + { XE_RTP_NAME("14024997852"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> + ENGINE_CLASS(RENDER)),
> + XE_RTP_ACTIONS(WHITELIST(FF_MODE,
> + RING_FORCE_TO_NONPRIV_ACCESS_RW),
> + WHITELIST(VFLSKPD,
> + RING_FORCE_TO_NONPRIV_ACCESS_RW))
> + },
>
> #define WHITELIST_OA_MMIO_TRG(trg, status, head) \
> WHITELIST(trg, RING_FORCE_TO_NONPRIV_ACCESS_RW), \
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 1e8d61ac581b..682865f1fc16 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -325,6 +325,31 @@ static const struct xe_rtp_entry_sr gt_was[] = {
> XE_RTP_RULES(MEDIA_VERSION(3500)),
> XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> },
> +
> + /* Xe3P_LPG */
> +
> + { XE_RTP_NAME("14025160223"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(MMIOATSREQLIMIT_GAM_WALK_3D,
> + DIS_ATS_WRONLY_PG))
> + },
> + { XE_RTP_NAME("16028780921"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(CCCHKNREG2, LOCALITYDIS))
> + },
> + { XE_RTP_NAME("14026144927"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(L3SQCREG2, L3_SQ_DISABLE_COAMA_2WAY_COH |
> + L3_SQ_DISABLE_COAMA))
> + },
> + { XE_RTP_NAME("14025635424"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(GAMSTLB_CTRL2, STLB_SINGLE_BANK_MODE))
> + },
> + { XE_RTP_NAME("16028005424"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)),
> + XE_RTP_ACTIONS(SET(GUC_INTR_CHICKEN, DISABLE_SIGNALING_ENGINES))
> + },
> };
>
> static const struct xe_rtp_entry_sr engine_was[] = {
> @@ -699,6 +724,24 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
> },
> +
> + /* Xe3p_LPG*/
> +
> + { XE_RTP_NAME("22021149932"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> + FUNC(xe_rtp_match_first_render_or_compute)),
> + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, SAMPLER_LD_LSC_DISABLE))
> + },
> + { XE_RTP_NAME("14025676848"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> + FUNC(xe_rtp_match_first_render_or_compute)),
> + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE))
> + },
> + { XE_RTP_NAME("16028951944"),
> + XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
> + FUNC(xe_rtp_match_first_render_or_compute)),
> + XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
> + },
> };
>
> static const struct xe_rtp_entry_sr lrc_was[] = {
>
> --
> 2.52.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
next prev parent reply other threads:[~2026-02-06 15:25 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
2026-02-06 15:26 ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10 Gustavo Sousa
2026-02-06 15:25 ` Matt Roper [this message]
2026-02-05 23:39 ` [PATCH v2 03/15] drm/xe/pat: Differentiate between primary and media for PTA Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 04/15] drm/xe/xe3p_lpg: Add new PAT table Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 05/15] drm/xe/xe3p_lpg: Add MCR steering Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 06/15] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 07/15] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 08/15] drm/xe/xe3p_lpg: Drop unnecessary tuning settings Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 09/15] drm/xe/xe3p_lpg: Extend 'group ID' mask size Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 10/15] drm/xe/xe3p_lpg: Update LRC sizes Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 11/15] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 12/15] drm/xe/nvlp: Add NVL-P platform definition Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 13/15] drm/xe/nvlp: Attach MOCS table for nvlp Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 14/15] drm/i915/nvlp: Hook up display support Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size Gustavo Sousa
2026-02-06 8:39 ` Bhadane, Dnyaneshwar
2026-02-05 23:47 ` ✗ CI.checkpatch: warning for Basic enabling patches for Xe3p_LPG and NVL-P (rev2) Patchwork
2026-02-05 23:48 ` ✓ CI.KUnit: success " Patchwork
2026-02-06 0:04 ` ✗ CI.checksparse: warning " Patchwork
2026-02-06 0:47 ` ✓ Xe.CI.BAT: success " Patchwork
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