From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Gustavo Sousa <gustavo.sousa@intel.com>,
Matt Roper <matthew.d.roper@intel.com>,
Tejas Upadhyay <tejas.upadhyay@intel.com>
Subject: [PATCH v2 03/15] drm/xe/pat: Differentiate between primary and media for PTA
Date: Thu, 05 Feb 2026 20:39:31 -0300 [thread overview]
Message-ID: <20260205-nvl-p-upstreaming-v2-3-9ec14f00cc6c@intel.com> (raw)
In-Reply-To: <20260205-nvl-p-upstreaming-v2-0-9ec14f00cc6c@intel.com>
Differently from currently supported platforms, in upcoming changes we
will need to have different PAT entries for PTA based on the GT type. As
such, let's prepare the code to support that by having two separate
PTA-specific members in the pat struct, one for each type of GT.
While at it, also fix the kerneldoc for pat_ats.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Co-developed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 8 +++++---
drivers/gpu/drm/xe/xe_pat.c | 27 ++++++++++++++++++---------
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 14bf2c027f89..059f026e80d5 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -400,10 +400,12 @@ struct xe_device {
const struct xe_pat_table_entry *table;
/** @pat.n_entries: Number of PAT entries */
int n_entries;
- /** @pat.ats_entry: PAT entry for PCIe ATS responses */
+ /** @pat.pat_ats: PAT entry for PCIe ATS responses */
const struct xe_pat_table_entry *pat_ats;
- /** @pat.pta_entry: PAT entry for page table accesses */
- const struct xe_pat_table_entry *pat_pta;
+ /** @pat.pat_primary_pta: primary GT PAT entry for page table accesses */
+ const struct xe_pat_table_entry *pat_primary_pta;
+ /** @pat.pat_media_pta: media GT PAT entry for page table accesses */
+ const struct xe_pat_table_entry *pat_media_pta;
u32 idx[__XE_CACHE_LEVEL_COUNT];
} pat;
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 2cd3fd1c3953..5ba650948a4a 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -285,8 +285,10 @@ static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[
if (xe->pat.pat_ats)
xe_mmio_write32(>->mmio, XE_REG(_PAT_ATS), xe->pat.pat_ats->value);
- if (xe->pat.pat_pta)
- xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe->pat.pat_pta->value);
+ if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
+ xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe->pat.pat_primary_pta->value);
+ if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
+ xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe->pat.pat_media_pta->value);
}
static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[],
@@ -302,8 +304,10 @@ static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry ta
if (xe->pat.pat_ats)
xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_ATS), xe->pat.pat_ats->value);
- if (xe->pat.pat_pta)
- xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_pta->value);
+ if (xe->pat.pat_primary_pta && xe_gt_is_main_type(gt))
+ xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_primary_pta->value);
+ if (xe->pat.pat_media_pta && xe_gt_is_media_type(gt))
+ xe_gt_mcr_multicast_write(gt, XE_REG_MCR(_PAT_PTA), xe->pat.pat_media_pta->value);
}
static int xelp_dump(struct xe_gt *gt, struct drm_printer *p)
@@ -498,7 +502,8 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.ops = &xe3p_xpc_pat_ops;
xe->pat.table = xe3p_xpc_pat_table;
xe->pat.pat_ats = &xe3p_xpc_pat_ats;
- xe->pat.pat_pta = &xe3p_xpc_pat_pta;
+ xe->pat.pat_primary_pta = &xe3p_xpc_pat_pta;
+ xe->pat.pat_media_pta = &xe3p_xpc_pat_pta;
xe->pat.n_entries = ARRAY_SIZE(xe3p_xpc_pat_table);
xe->pat.idx[XE_CACHE_NONE] = 3;
xe->pat.idx[XE_CACHE_WT] = 3; /* N/A (no display); use UC */
@@ -512,8 +517,10 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.table = xe2_pat_table;
}
xe->pat.pat_ats = &xe2_pat_ats;
- if (IS_DGFX(xe))
- xe->pat.pat_pta = &xe2_pat_pta;
+ if (IS_DGFX(xe)) {
+ xe->pat.pat_primary_pta = &xe2_pat_pta;
+ xe->pat.pat_media_pta = &xe2_pat_pta;
+ }
/* Wa_16023588340. XXX: Should use XE_WA */
if (GRAPHICS_VERx100(xe) == 2001)
@@ -617,6 +624,8 @@ int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p)
int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
{
struct xe_device *xe = gt_to_xe(gt);
+ const struct xe_pat_table_entry *pta_entry = xe_gt_is_main_type(gt) ?
+ xe->pat.pat_primary_pta : xe->pat.pat_media_pta;
char label[PAT_LABEL_LEN];
if (!xe->pat.table || !xe->pat.n_entries)
@@ -640,8 +649,8 @@ int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p)
}
}
- if (xe->pat.pat_pta) {
- u32 pat = xe->pat.pat_pta->value;
+ if (pta_entry) {
+ u32 pat = pta_entry->value;
drm_printf(p, "Page Table Access:\n");
xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false);
--
2.52.0
next prev parent reply other threads:[~2026-02-05 23:40 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-05 23:39 [PATCH v2 00/15] Basic enabling patches for Xe3p_LPG and NVL-P Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 01/15] drm/xe/xe3p_lpg: Add support for graphics IP 35.10 Gustavo Sousa
2026-02-06 15:26 ` Matt Roper
2026-02-05 23:39 ` [PATCH v2 02/15] drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10 Gustavo Sousa
2026-02-06 15:25 ` Matt Roper
2026-02-05 23:39 ` Gustavo Sousa [this message]
2026-02-05 23:39 ` [PATCH v2 04/15] drm/xe/xe3p_lpg: Add new PAT table Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 05/15] drm/xe/xe3p_lpg: Add MCR steering Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 06/15] drm/xe/xe3p_lpg: Add LRC parsing for additional RCS engine state Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 07/15] drm/xe/xe3p_lpg: Disable reporting of context switch status to GHWSP Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 08/15] drm/xe/xe3p_lpg: Drop unnecessary tuning settings Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 09/15] drm/xe/xe3p_lpg: Extend 'group ID' mask size Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 10/15] drm/xe/xe3p_lpg: Update LRC sizes Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 11/15] drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 12/15] drm/xe/nvlp: Add NVL-P platform definition Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 13/15] drm/xe/nvlp: Attach MOCS table for nvlp Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 14/15] drm/i915/nvlp: Hook up display support Gustavo Sousa
2026-02-05 23:39 ` [PATCH v2 15/15] drm/xe/nvlp: Bump maximum WOPCM size Gustavo Sousa
2026-02-06 8:39 ` Bhadane, Dnyaneshwar
2026-02-05 23:47 ` ✗ CI.checkpatch: warning for Basic enabling patches for Xe3p_LPG and NVL-P (rev2) Patchwork
2026-02-05 23:48 ` ✓ CI.KUnit: success " Patchwork
2026-02-06 0:04 ` ✗ CI.checksparse: warning " Patchwork
2026-02-06 0:47 ` ✓ Xe.CI.BAT: success " Patchwork
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