[PATCH v2 00/10] GuC paging engine support

[PATCH v2 00/10] GuC paging engine support

[Matthew Auld]

On NVL-S+, the GuC will be moving towards a dedicated GuC engine class for
the driver reserved copy engine(s), which we need for USM flows. With this
the GuC will now be able to internally differentiate KMD paging operations,
like clearing/migrating/binding, from other copy engine submissions.

Note that this is purely a software view within the GuC. There is no new
physical engine, or anything like that. With that in mind the design here
keeps this contained on the GuC side, with upper layers not needing to know
about this distinction.

The final GuC versioning is still being finalised (marked as TODO in the
relevant commits) and we are still missing the proper GuC release, so
merging is still gated by that, but in the meantime we can get this
reviewed in upstream and ready to go. This has already seen some internal
smoke testing, both on VF and PF flows with the new GUC_PAGING class.

v2 (Sashiko):
 - In VF query patch, we shouldn't call guc_has_paging_engine(), since this
   is too early in the VF sequence, and GUC_SUBMIT_VER() is still unset.

-- 
2.54.0

[PATCH v2 01/10] drm/xe/guc: refactor ads to use guc_class

[Matthew Auld]

Currently in the lrc init flow on the ads side, we loop through each
generic engine class and convert that to the respective guc engine
class. However, with some upcoming changes, it will be better to go the
opposite way and loop through every guc engine class, and convert that
to the generic engine class.

This also reworks engine_enable_mask to operate on the guc_class, that
way we can easily filter out the PAGING vs normal BSC, when applicable.

This will be needed in an upcoming patch where we have a new guc engine
class that just matches up to the existing blitter/copy class, but needs
to be treated as separate entity from the normal copy lrc, when setting
up the ADS.

As a bonus this also gets rid of two xe_engine_class_to_guc_class()
users which will be helpful for the next patch.

No functional changes.

Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c | 67 ++++++++++++++++++++++-----------
 1 file changed, 45 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index b9bca6084a4f..ffe60d77b713 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -251,15 +251,37 @@ static size_t calculate_regset_size(struct xe_gt *gt)
 	return count * sizeof(struct guc_mmio_reg);
 }
 
-static u32 engine_enable_mask(struct xe_gt *gt, enum xe_engine_class class)
+static inline enum xe_engine_class guc_class_to_engine_class(u16 guc_class)
+{
+	switch (guc_class) {
+	case GUC_RENDER_CLASS:
+		return XE_ENGINE_CLASS_RENDER;
+	case GUC_VIDEO_CLASS:
+		return XE_ENGINE_CLASS_VIDEO_DECODE;
+	case GUC_VIDEOENHANCE_CLASS:
+		return XE_ENGINE_CLASS_VIDEO_ENHANCE;
+	case GUC_BLITTER_CLASS:
+		return XE_ENGINE_CLASS_COPY;
+	case GUC_COMPUTE_CLASS:
+		return XE_ENGINE_CLASS_COMPUTE;
+	case GUC_GSC_OTHER_CLASS:
+		return XE_ENGINE_CLASS_OTHER;
+	default:
+		XE_WARN_ON(guc_class);
+		return -1;
+	}
+}
+
+static u32 engine_enable_mask(struct xe_gt *gt, u16 guc_class)
 {
 	struct xe_hw_engine *hwe;
 	enum xe_hw_engine_id id;
 	u32 mask = 0;
 
-	for_each_hw_engine(hwe, gt, id)
-		if (hwe->class == class)
+	for_each_hw_engine(hwe, gt, id) {
+		if (xe_engine_class_to_guc_class(hwe->class) == guc_class)
 			mask |= BIT(hwe->instance);
+	}
 
 	return mask;
 }
@@ -268,10 +290,13 @@ static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads)
 {
 	struct xe_gt *gt = ads_to_gt(ads);
 	size_t total_size = 0, alloc_size, real_size;
-	int class;
+	u16 guc_class;
 
-	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
-		if (!engine_enable_mask(gt, class))
+	for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) {
+		enum xe_engine_class class =
+			guc_class_to_engine_class(guc_class);
+
+		if (!engine_enable_mask(gt, guc_class))
 			continue;
 
 		real_size = xe_gt_lrc_size(gt, class);
@@ -465,18 +490,18 @@ static void fill_engine_enable_masks(struct xe_gt *gt,
 	struct xe_device *xe = gt_to_xe(gt);
 
 	info_map_write(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS],
-		       engine_enable_mask(gt, XE_ENGINE_CLASS_RENDER));
+		       engine_enable_mask(gt, GUC_RENDER_CLASS));
 	info_map_write(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS],
-		       engine_enable_mask(gt, XE_ENGINE_CLASS_COPY));
+		       engine_enable_mask(gt, GUC_BLITTER_CLASS));
 	info_map_write(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS],
-		       engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_DECODE));
+		       engine_enable_mask(gt, GUC_VIDEO_CLASS));
 	info_map_write(xe, info_map,
 		       engine_enabled_masks[GUC_VIDEOENHANCE_CLASS],
-		       engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE));
+		       engine_enable_mask(gt, GUC_VIDEOENHANCE_CLASS));
 	info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS],
-		       engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE));
+		       engine_enable_mask(gt, GUC_COMPUTE_CLASS));
 	info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
-		       engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER));
+		       engine_enable_mask(gt, GUC_GSC_OTHER_CLASS));
 }
 
 /*
@@ -491,15 +516,14 @@ static void guc_golden_lrc_init(struct xe_guc_ads *ads)
 			offsetof(struct __guc_ads_blob, system_info));
 	size_t alloc_size, real_size;
 	u32 addr_ggtt, offset;
-	int class;
+	u16 guc_class;
 
 	offset = guc_ads_golden_lrc_offset(ads);
 	addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset;
 
-	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
-		u8 guc_class;
-
-		guc_class = xe_engine_class_to_guc_class(class);
+	for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) {
+		enum xe_engine_class class =
+			guc_class_to_engine_class(guc_class);
 
 		if (!info_map_read(xe, &info_map,
 				   engine_enabled_masks[guc_class]))
@@ -943,14 +967,13 @@ static void guc_golden_lrc_populate(struct xe_guc_ads *ads)
 			offsetof(struct __guc_ads_blob, system_info));
 	size_t total_size = 0, alloc_size, real_size;
 	u32 offset;
-	int class;
+	u16 guc_class;
 
 	offset = guc_ads_golden_lrc_offset(ads);
 
-	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
-		u8 guc_class;
-
-		guc_class = xe_engine_class_to_guc_class(class);
+	for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) {
+		enum xe_engine_class class =
+			guc_class_to_engine_class(guc_class);
 
 		if (!info_map_read(xe, &info_map,
 				   engine_enabled_masks[guc_class]))
-- 
2.54.0

[PATCH v2 02/10] drm/xe/guc: refactor to_guc_class() to accept hwe

[Matthew Auld]

Rather then inferring the GuC engine class from the generic hw engine
class, pass in the hwe itself, which gives the complete view, like
instance etc.  On future GuC version, there is dedicated PAGING class to
identify the KMD reserved BCS engine, so we need more info here in order
to return the correct GuC specific engine class.

With this everything should now be using the new hwe based interface. No
functional changes.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c |  2 +-
 drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c  |  2 +-
 drivers/gpu/drm/xe/xe_guc.h                 | 21 +---------------
 drivers/gpu/drm/xe/xe_guc_ads.c             | 27 ++++++++++++++++++---
 drivers/gpu/drm/xe/xe_guc_capture.c         | 12 ++++-----
 drivers/gpu/drm/xe/xe_guc_capture.h         |  4 +--
 drivers/gpu/drm/xe/xe_guc_engine_activity.c |  4 +--
 drivers/gpu/drm/xe/xe_guc_submit.c          |  2 +-
 8 files changed, 38 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
index ffa27f66bba7..f28c7ae0e8c2 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
@@ -381,7 +381,7 @@ static ssize_t sched_group_engines_read(struct file *file, char __user *buf,
 
 	if (group < num_groups) {
 		for_each_hw_engine(hwe, gt, id) {
-			u8 guc_class = xe_engine_class_to_guc_class(hwe->class);
+			u8 guc_class = xe_hwe_to_guc_class(hwe);
 			u32 mask = groups[group].engines[guc_class];
 
 			if (mask & BIT(hwe->logical_instance)) {
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
index e8458d63742d..cf117bf52d41 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
@@ -471,7 +471,7 @@ static void pf_sched_group_media_slices(struct xe_gt *gt, struct guc_sched_group
 		return;
 
 	for_each_hw_engine(hwe, gt, id) {
-		u8 guc_class = xe_engine_class_to_guc_class(hwe->class);
+		u8 guc_class = xe_hwe_to_guc_class(hwe);
 
 		switch (hwe->class) {
 		case XE_ENGINE_CLASS_VIDEO_DECODE:
diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 02514914f404..12faf0ba7229 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -67,26 +67,7 @@ bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
 int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
 #endif
 
-static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class)
-{
-	switch (class) {
-	case XE_ENGINE_CLASS_RENDER:
-		return GUC_RENDER_CLASS;
-	case XE_ENGINE_CLASS_VIDEO_DECODE:
-		return GUC_VIDEO_CLASS;
-	case XE_ENGINE_CLASS_VIDEO_ENHANCE:
-		return GUC_VIDEOENHANCE_CLASS;
-	case XE_ENGINE_CLASS_COPY:
-		return GUC_BLITTER_CLASS;
-	case XE_ENGINE_CLASS_COMPUTE:
-		return GUC_COMPUTE_CLASS;
-	case XE_ENGINE_CLASS_OTHER:
-		return GUC_GSC_OTHER_CLASS;
-	default:
-		XE_WARN_ON(class);
-		return -1;
-	}
-}
+u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe);
 
 static inline struct xe_gt *guc_to_gt(struct xe_guc *guc)
 {
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index ffe60d77b713..6626803d75b5 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -279,7 +279,7 @@ static u32 engine_enable_mask(struct xe_gt *gt, u16 guc_class)
 	u32 mask = 0;
 
 	for_each_hw_engine(hwe, gt, id) {
-		if (xe_engine_class_to_guc_class(hwe->class) == guc_class)
+		if (xe_hwe_to_guc_class(hwe) == guc_class)
 			mask |= BIT(hwe->instance);
 	}
 
@@ -504,6 +504,27 @@ static void fill_engine_enable_masks(struct xe_gt *gt,
 		       engine_enable_mask(gt, GUC_GSC_OTHER_CLASS));
 }
 
+u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe)
+{
+	switch (hwe->class) {
+	case XE_ENGINE_CLASS_RENDER:
+		return GUC_RENDER_CLASS;
+	case XE_ENGINE_CLASS_VIDEO_DECODE:
+		return GUC_VIDEO_CLASS;
+	case XE_ENGINE_CLASS_VIDEO_ENHANCE:
+		return GUC_VIDEOENHANCE_CLASS;
+	case XE_ENGINE_CLASS_COPY:
+		return GUC_BLITTER_CLASS;
+	case XE_ENGINE_CLASS_COMPUTE:
+		return GUC_COMPUTE_CLASS;
+	case XE_ENGINE_CLASS_OTHER:
+		return GUC_GSC_OTHER_CLASS;
+	default:
+		XE_WARN_ON(hwe->class);
+		return -1;
+	}
+}
+
 /*
  * Write the offsets corresponding to the golden LRCs. The actual data is
  * populated later by guc_golden_lrc_populate()
@@ -574,7 +595,7 @@ static void guc_mapping_table_init(struct xe_gt *gt,
 	for_each_hw_engine(hwe, gt, id) {
 		u8 guc_class;
 
-		guc_class = xe_engine_class_to_guc_class(hwe->class);
+		guc_class = xe_hwe_to_guc_class(hwe);
 		info_map_write(xe, info_map,
 			       mapping_table[guc_class][hwe->logical_instance],
 			       hwe->instance);
@@ -824,7 +845,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
 		 * 2. Record in the header (ads.reg_state_list) the address
 		 * location and number of entries
 		 */
-		gc = xe_engine_class_to_guc_class(hwe->class);
+		gc = xe_hwe_to_guc_class(hwe);
 		ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].address, addr);
 		ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].count, count);
 
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 21f7caf9ea08..50c6b9466c14 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -440,7 +440,7 @@ static void guc_capture_alloc_steered_lists(struct xe_guc *guc)
 	 * to be extended
 	 */
 	for_each_hw_engine(hwe, gt, id) {
-		if (xe_engine_class_to_guc_capture_class(hwe->class) ==
+		if (xe_hwe_to_guc_capture_class(hwe) ==
 		    GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE) {
 			has_rcs_ccs = true;
 			break;
@@ -812,7 +812,7 @@ static int guc_capture_output_size_est(struct xe_guc *guc)
 	for_each_hw_engine(hwe, gt, id) {
 		enum guc_capture_list_class_type capture_class;
 
-		capture_class = xe_engine_class_to_guc_capture_class(hwe->class);
+		capture_class = xe_hwe_to_guc_capture_class(hwe);
 		capture_size += sizeof(struct guc_state_capture_group_header_t) +
 					 (3 * sizeof(struct guc_state_capture_header_t));
 
@@ -1620,7 +1620,7 @@ xe_engine_manual_capture(struct xe_hw_engine *hwe, struct xe_hw_engine_snapshot
 	if (!new)
 		return;
 
-	capture_class = xe_engine_class_to_guc_capture_class(hwe->class);
+	capture_class = xe_hwe_to_guc_capture_class(hwe);
 	for (type = GUC_STATE_CAPTURE_TYPE_GLOBAL; type < GUC_STATE_CAPTURE_TYPE_MAX; type++) {
 		struct gcap_reg_list_info *reginfo = &new->reginfo[type];
 		/*
@@ -1662,7 +1662,7 @@ xe_engine_manual_capture(struct xe_hw_engine *hwe, struct xe_hw_engine_snapshot
 		}
 	}
 
-	new->eng_class = xe_engine_class_to_guc_class(hwe->class);
+	new->eng_class = xe_hwe_to_guc_class(hwe);
 	new->eng_inst = hwe->instance;
 	new->guc_id = guc_id;
 	new->lrca = lrca;
@@ -1826,7 +1826,7 @@ void xe_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot, struct drm
 
 	xe_gt_assert(gt, snapshot->hwe);
 
-	capture_class = xe_engine_class_to_guc_capture_class(snapshot->hwe->class);
+	capture_class = xe_hwe_to_guc_capture_class(snapshot->hwe);
 
 	drm_printf(p, "%s (physical), logical instance=%d\n",
 		   snapshot->name ? snapshot->name : "",
@@ -1898,7 +1898,7 @@ xe_guc_capture_get_matching_and_lock(struct xe_exec_queue *q)
 	for_each_hw_engine(hwe, q->gt, id) {
 		if (hwe != q->hwe)
 			continue;
-		guc_class = xe_engine_class_to_guc_class(hwe->class);
+		guc_class = xe_hwe_to_guc_class(hwe);
 		break;
 	}
 
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h
index dca97d52b192..eb954f4d1ffd 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.h
+++ b/drivers/gpu/drm/xe/xe_guc_capture.h
@@ -35,9 +35,9 @@ static inline enum guc_capture_list_class_type xe_guc_class_to_capture_class(u16
 }
 
 static inline enum guc_capture_list_class_type
-xe_engine_class_to_guc_capture_class(enum xe_engine_class class)
+xe_hwe_to_guc_capture_class(struct xe_hw_engine *hwe)
 {
-	return xe_guc_class_to_capture_class(xe_engine_class_to_guc_class(class));
+	return xe_guc_class_to_capture_class(xe_hwe_to_guc_class(hwe));
 }
 
 void xe_guc_capture_process(struct xe_guc *guc);
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
index 2b99c1ebdd58..150d891d5a09 100644
--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
@@ -27,7 +27,7 @@ static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_eng
 {
 	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
 	struct engine_activity_buffer *buffer;
-	u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
+	u16 guc_class = xe_hwe_to_guc_class(hwe);
 	size_t offset;
 
 	if (engine_activity->num_functions) {
@@ -150,7 +150,7 @@ static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine
 {
 	struct xe_guc *guc = &hwe->gt->uc.guc;
 	struct engine_activity_group *eag = &guc->engine_activity.eag[index];
-	u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
+	u16 guc_class = xe_hwe_to_guc_class(hwe);
 
 	return &eag->engine[guc_class][hwe->logical_instance];
 }
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index afd8cc7bd231..1ee4f2434876 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -985,7 +985,7 @@ static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
 
 	memset(&info, 0, sizeof(info));
 	info.context_idx = q->guc->id;
-	info.engine_class = xe_engine_class_to_guc_class(q->class);
+	info.engine_class = xe_hwe_to_guc_class(q->hwe);
 	info.engine_submit_mask = q->logical_mask;
 	info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc));
 	info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));
-- 
2.54.0

[PATCH v2 03/10] drm/xe/guc: add the plumbing for GUC_PAGING_CLASS

[Matthew Auld]

On newer platforms, the GuC has a new engine class which we need to use
to refer to the dedicated/reserved KMD BCS engine. With that add the
plumbing in the GuC backend to support GUC_PAGING_CLASS and
GUC_CAPTURE_LIST_CLASS_PAGING.

Currently this is still turned off.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/xe/abi/guc_capture_abi.h   |  3 ++-
 drivers/gpu/drm/xe/abi/guc_scheduler_abi.h |  3 ++-
 drivers/gpu/drm/xe/xe_guc.c                | 15 +++++++++++++++
 drivers/gpu/drm/xe/xe_guc.h                |  1 +
 drivers/gpu/drm/xe/xe_guc_ads.c            | 13 +++++++++++++
 drivers/gpu/drm/xe/xe_guc_capture.c        |  7 +++++++
 drivers/gpu/drm/xe/xe_guc_capture.h        |  2 ++
 7 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/abi/guc_capture_abi.h b/drivers/gpu/drm/xe/abi/guc_capture_abi.h
index dd4117553739..ff9c0ae34a28 100644
--- a/drivers/gpu/drm/xe/abi/guc_capture_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_capture_abi.h
@@ -32,9 +32,10 @@ enum guc_capture_list_class_type {
 	GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2,
 	GUC_CAPTURE_LIST_CLASS_BLITTER = 3,
 	GUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4,
+	GUC_CAPTURE_LIST_CLASS_PAGING = 5,
 };
 
-#define GUC_CAPTURE_LIST_CLASS_MAX	(GUC_CAPTURE_LIST_CLASS_GSC_OTHER + 1)
+#define GUC_CAPTURE_LIST_CLASS_MAX	(GUC_CAPTURE_LIST_CLASS_PAGING + 1)
 
 /**
  * struct guc_mmio_reg - GuC MMIO reg state struct
diff --git a/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h b/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h
index 19ec89bf39c5..85bba34277ed 100644
--- a/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_scheduler_abi.h
@@ -21,7 +21,8 @@
 #define GUC_BLITTER_CLASS		3
 #define GUC_COMPUTE_CLASS		4
 #define GUC_GSC_OTHER_CLASS		5
-#define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS
+#define GUC_PAGING_CLASS		6
+#define GUC_LAST_ENGINE_CLASS		GUC_PAGING_CLASS
 #define GUC_MAX_ENGINE_CLASSES		16
 #define GUC_MAX_INSTANCES_PER_CLASS	32
 
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 4023700ff2a9..cdbcad79b060 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -1846,6 +1846,21 @@ bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
 	return GT_VER(gt) >= 35;
 }
 
+bool xe_guc_has_paging_engine(struct xe_guc *guc)
+{
+	/*
+	 * On newer platforms the GuC now has a dedicated engine class for the
+	 * special PAGING engine, which is the driver reserved BCS engine used
+	 * for KMD paging/binding operations. GuC requires KMD to refer to this
+	 * using the special PAGING engine class. Note that there is no new hw
+	 * engine here, this purely a sw view in the GuC itself, which we need
+	 * to respect.
+	 */
+
+	/* TODO: Have some way to query this from the GuC? */
+	return false;
+}
+
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 #include "tests/xe_guc_g2g_test.c"
 #endif
diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 12faf0ba7229..0934927e8254 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -62,6 +62,7 @@ void xe_guc_stop(struct xe_guc *guc);
 int xe_guc_start(struct xe_guc *guc);
 void xe_guc_declare_wedged(struct xe_guc *guc);
 bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
+bool xe_guc_has_paging_engine(struct xe_guc *guc);
 
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 6626803d75b5..996eb58f5484 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -261,6 +261,7 @@ static inline enum xe_engine_class guc_class_to_engine_class(u16 guc_class)
 	case GUC_VIDEOENHANCE_CLASS:
 		return XE_ENGINE_CLASS_VIDEO_ENHANCE;
 	case GUC_BLITTER_CLASS:
+	case GUC_PAGING_CLASS:
 		return XE_ENGINE_CLASS_COPY;
 	case GUC_COMPUTE_CLASS:
 		return XE_ENGINE_CLASS_COMPUTE;
@@ -488,6 +489,7 @@ static void fill_engine_enable_masks(struct xe_gt *gt,
 				     struct iosys_map *info_map)
 {
 	struct xe_device *xe = gt_to_xe(gt);
+	u32 paging_mask = engine_enable_mask(gt, GUC_PAGING_CLASS);
 
 	info_map_write(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS],
 		       engine_enable_mask(gt, GUC_RENDER_CLASS));
@@ -502,10 +504,18 @@ static void fill_engine_enable_masks(struct xe_gt *gt,
 		       engine_enable_mask(gt, GUC_COMPUTE_CLASS));
 	info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
 		       engine_enable_mask(gt, GUC_GSC_OTHER_CLASS));
+	info_map_write(xe, info_map, engine_enabled_masks[GUC_PAGING_CLASS],
+		       paging_mask);
+	/* We assume at most one paging engine per GuC instance, for now */
+	xe_gt_assert(gt, !paging_mask || is_power_of_2(paging_mask));
 }
 
 u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe)
 {
+	if (xe_guc_has_paging_engine(&hwe->gt->uc.guc) &&
+	    xe_gt_is_usm_hwe(hwe->gt, hwe))
+		return GUC_PAGING_CLASS;
+
 	switch (hwe->class) {
 	case XE_ENGINE_CLASS_RENDER:
 		return GUC_RENDER_CLASS;
@@ -625,6 +635,9 @@ static u32 guc_get_capture_engine_mask(struct xe_gt *gt, struct iosys_map *info_
 	case GUC_CAPTURE_LIST_CLASS_GSC_OTHER:
 		mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]);
 		break;
+	case GUC_CAPTURE_LIST_CLASS_PAGING:
+		mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_PAGING_CLASS]);
+		break;
 	default:
 		mask = 0;
 	}
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 50c6b9466c14..c13b23c45aac 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -265,6 +265,8 @@ static const struct __guc_mmio_reg_descr_group xe3p_lists[] = {
 	MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_BLITTER),
 	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
 	MAKE_REGLIST(xe_lp_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_GSC_OTHER),
+	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_CAPTURE_LIST_CLASS_PAGING),
+	MAKE_REGLIST(xe_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_CAPTURE_LIST_CLASS_PAGING),
 	{}
 };
 static const char * const capture_list_type_names[] = {
@@ -279,6 +281,7 @@ static const char * const capture_engine_class_names[] = {
 	"VideoEnhance",
 	"Blitter",
 	"GSC-Other",
+	"Paging",
 };
 
 struct __guc_capture_ads_cache {
@@ -766,6 +769,10 @@ size_t xe_guc_capture_ads_input_worst_size(struct xe_guc *guc)
 	total_size = PAGE_SIZE;	/* Pad a page in front for empty lists */
 	for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
 		for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) {
+			if (!xe_guc_has_paging_engine(guc) &&
+			    j == GUC_CAPTURE_LIST_CLASS_PAGING)
+				continue;
+
 			if (xe_guc_capture_getlistsize(guc, i,
 						       GUC_STATE_CAPTURE_TYPE_ENGINE_CLASS,
 						       j, &class_size) < 0)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h
index eb954f4d1ffd..fcd4f1298536 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.h
+++ b/drivers/gpu/drm/xe/xe_guc_capture.h
@@ -28,6 +28,8 @@ static inline enum guc_capture_list_class_type xe_guc_class_to_capture_class(u16
 	case GUC_VIDEOENHANCE_CLASS:
 	case GUC_BLITTER_CLASS:
 		return class;
+	case GUC_PAGING_CLASS:
+		return GUC_CAPTURE_LIST_CLASS_PAGING;
 	default:
 		XE_WARN_ON(class);
 		return GUC_CAPTURE_LIST_CLASS_MAX;
-- 
2.54.0

[PATCH v2 04/10] drm/xe/hw_engine: don't open code is_usm_hwe()

[Matthew Auld]

Prefer is_usm_hwe() here.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 8c66ff6f3d3c..768b0cd4c16a 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -1037,8 +1037,7 @@ bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe)
 	    hwe->logical_instance >= gt->ccs_mode)
 		return true;
 
-	return xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY &&
-		hwe->instance == gt->usm.reserved_bcs_instance;
+	return xe_gt_is_usm_hwe(gt, hwe);
 }
 
 const char *xe_hw_engine_class_to_str(enum xe_engine_class class)
-- 
2.54.0

[PATCH v2 05/10] drm/xe: refactor the paging engine setup

[Matthew Auld]

On newer platforms, the paging configuration is now configured by the PF
via the ADS object, where VF side should ensure that everything
configured as GUC_PAGING_CLASS is correctly mirrored on VF side. For
example PF could in theory reserve two BCS instances, and we expect VF
to mirror that.

With that move towards having a logical mask of all the paging engines,
and also generalise selecting those engines, based on the number of
paging engines. Also cache the first designated paging engine, which
will makes things a little cleaner here, and in later patches.

No functional changes for existing platforms.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/xe/xe_exec_queue.c |  5 +---
 drivers/gpu/drm/xe/xe_gt.h         |  6 ++---
 drivers/gpu/drm/xe/xe_gt_types.h   | 12 ++++++---
 drivers/gpu/drm/xe/xe_hw_engine.c  | 39 +++++++++++++++++++++++-------
 drivers/gpu/drm/xe/xe_migrate.c    | 32 +++---------------------
 5 files changed, 46 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 1b5ca3ce578a..cfd2a4e6d4c7 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -530,10 +530,7 @@ struct xe_exec_queue *xe_exec_queue_create_bind(struct xe_device *xe,
 
 	migrate_vm = xe_migrate_get_vm(tile->migrate);
 	if (xe->info.has_usm) {
-		struct xe_hw_engine *hwe = xe_gt_hw_engine(gt,
-							   XE_ENGINE_CLASS_COPY,
-							   gt->usm.reserved_bcs_instance,
-							   false);
+		struct xe_hw_engine *hwe = gt->usm.paging_hwe0;
 
 		if (!hwe) {
 			xe_vm_put(migrate_vm);
diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h
index 4150aa594f05..a6cfaa1af23f 100644
--- a/drivers/gpu/drm/xe/xe_gt.h
+++ b/drivers/gpu/drm/xe/xe_gt.h
@@ -137,10 +137,8 @@ static inline bool xe_gt_is_media_type(struct xe_gt *gt)
 
 static inline bool xe_gt_is_usm_hwe(struct xe_gt *gt, struct xe_hw_engine *hwe)
 {
-	struct xe_device *xe = gt_to_xe(gt);
-
-	return xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY &&
-		hwe->instance == gt->usm.reserved_bcs_instance;
+	return hwe->class == XE_ENGINE_CLASS_COPY &&
+	       (gt->usm.paging_logical_mask & BIT(hwe->logical_instance));
 }
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index e5588c88800a..10c32ea3ccdf 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -230,10 +230,16 @@ struct xe_gt {
 		 */
 		struct xe_sa_manager *bb_pool;
 		/**
-		 * @usm.reserved_bcs_instance: reserved BCS instance used for USM
-		 * operations (e.g. migrations, fixing page tables)
+		 * @usm.paging_hwe0: The first designated paging engine.
+		 * This is some reserved BCS instance used for USM operations
+		 * (e.g. migrations, fixing page tables)
 		 */
-		u16 reserved_bcs_instance;
+		struct xe_hw_engine *paging_hwe0;
+		/**
+		 * @usm.paging_logical_mask: logical mask of paging engines.
+		 * Should be densely populated.
+		 */
+		u32 paging_logical_mask;
 	} usm;
 
 	/** @ordered_wq: used to serialize GT resets and TDRs */
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 768b0cd4c16a..77f882cd8ff8 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -639,10 +639,6 @@ static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,
 			xe_hw_engine_enable_ring(hwe);
 	}
 
-	/* We reserve the highest BCS instance for USM */
-	if (xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY)
-		gt->usm.reserved_bcs_instance = hwe->instance;
-
 	/* Ensure IDLEDLY is lower than MAXCNT */
 	adjust_idledly(hwe);
 
@@ -656,19 +652,44 @@ static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,
 	return err;
 }
 
-static void hw_engine_setup_logical_mapping(struct xe_gt *gt)
+static void hw_engine_setup_logical_and_paging_mapping(struct xe_gt *gt)
 {
+	struct xe_device *xe = gt_to_xe(gt);
+	unsigned int num_copy_engines = 0, num_paging_engines = 0;
+	unsigned int reserved_logical_bcs_start;
+	struct xe_hw_engine *hwe;
+	enum xe_hw_engine_id id;
 	int class;
 
+	for_each_hw_engine(hwe, gt, id)
+		if (hwe->class == XE_ENGINE_CLASS_COPY)
+			num_copy_engines++;
+
+	/* We just reserve the highest BCS instance for USM */
+	if (num_copy_engines && xe->info.has_usm)
+		num_paging_engines = 1;
+
+	xe_gt_assert(gt, !(num_copy_engines || num_paging_engines) ||
+		     (num_paging_engines < num_copy_engines));
+
+	reserved_logical_bcs_start = num_copy_engines - num_paging_engines;
+
 	/* FIXME: Doing a simple logical mapping that works for most hardware */
 	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
-		struct xe_hw_engine *hwe;
-		enum xe_hw_engine_id id;
 		int logical_instance = 0;
 
-		for_each_hw_engine(hwe, gt, id)
+		for_each_hw_engine(hwe, gt, id) {
 			if (hwe->class == class)
 				hwe->logical_instance = logical_instance++;
+
+			if (hwe->class == XE_ENGINE_CLASS_COPY &&
+			    hwe->logical_instance >= reserved_logical_bcs_start) {
+				if (!gt->usm.paging_hwe0)
+					gt->usm.paging_hwe0 = hwe;
+				gt->usm.paging_logical_mask |=
+					BIT(hwe->logical_instance);
+			}
+		}
 	}
 }
 
@@ -888,7 +909,7 @@ int xe_hw_engines_init(struct xe_gt *gt)
 			return err;
 	}
 
-	hw_engine_setup_logical_mapping(gt);
+	hw_engine_setup_logical_and_paging_mapping(gt);
 	err = xe_hw_engine_setup_groups(gt);
 	if (err)
 		return err;
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 9428dd5e7760..92d5e81ceac2 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -383,27 +383,6 @@ static void xe_migrate_suballoc_manager_init(struct xe_migrate *m, u32 map_ofs)
 				  NUM_VMUSA_UNIT_PER_PAGE, 0);
 }
 
-/*
- * Including the reserved copy engine is required to avoid deadlocks due to
- * migrate jobs servicing the faults gets stuck behind the job that faulted.
- */
-static u32 xe_migrate_usm_logical_mask(struct xe_gt *gt)
-{
-	u32 logical_mask = 0;
-	struct xe_hw_engine *hwe;
-	enum xe_hw_engine_id id;
-
-	for_each_hw_engine(hwe, gt, id) {
-		if (hwe->class != XE_ENGINE_CLASS_COPY)
-			continue;
-
-		if (xe_gt_is_usm_hwe(gt, hwe))
-			logical_mask |= BIT(hwe->logical_instance);
-	}
-
-	return logical_mask;
-}
-
 static bool xe_migrate_needs_ccs_emit(struct xe_device *xe)
 {
 	return xe_device_has_flat_ccs(xe) && !(GRAPHICS_VER(xe) >= 20 && IS_DGFX(xe));
@@ -479,13 +458,10 @@ int xe_migrate_init(struct xe_migrate *m)
 		goto err_out;
 
 	if (xe->info.has_usm) {
-		struct xe_hw_engine *hwe = xe_gt_hw_engine(primary_gt,
-							   XE_ENGINE_CLASS_COPY,
-							   primary_gt->usm.reserved_bcs_instance,
-							   false);
-		u32 logical_mask = xe_migrate_usm_logical_mask(primary_gt);
+		struct xe_hw_engine *hwe0 = primary_gt->usm.paging_hwe0;
+		u32 logical_mask = primary_gt->usm.paging_logical_mask;
 
-		if (!hwe || !logical_mask) {
+		if (!hwe0 || !logical_mask) {
 			err = -EINVAL;
 			goto err_out;
 		}
@@ -494,7 +470,7 @@ int xe_migrate_init(struct xe_migrate *m)
 		 * XXX: Currently only reserving 1 (likely slow) BCS instance on
 		 * PVC, may want to revisit if performance is needed.
 		 */
-		m->q = xe_exec_queue_create(xe, vm, logical_mask, 1, hwe,
+		m->q = xe_exec_queue_create(xe, vm, logical_mask, 1, hwe0,
 					    EXEC_QUEUE_FLAG_KERNEL |
 					    EXEC_QUEUE_FLAG_PERMANENT |
 					    EXEC_QUEUE_FLAG_HIGH_PRIORITY |
-- 
2.54.0

[PATCH v2 06/10] drm/xe/guc: handle guc logical instance for paging engine

[Matthew Auld]

In the GuC backend, we need a special logical instance when referring to
the reserved paging engine. Under the hood this is still just the same
physical BSC engine, however from the POV of the GuC this is actually
re-mapped as a separate GUC_PAGING_CLASS, with the logical index
starting from zero.

We don't want to leak this into the upper layers, since this is GuC
version specific,  so this really should be hidden on the GuC side, with
upper layers still being able to reference this as a normal BCS engine.

No functional change.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c |  3 ++-
 drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c  |  3 ++-
 drivers/gpu/drm/xe/xe_guc.h                 |  1 +
 drivers/gpu/drm/xe/xe_guc_ads.c             | 22 ++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_guc_engine_activity.c |  6 ++++--
 5 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
index f28c7ae0e8c2..0f242db775e1 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
@@ -382,9 +382,10 @@ static ssize_t sched_group_engines_read(struct file *file, char __user *buf,
 	if (group < num_groups) {
 		for_each_hw_engine(hwe, gt, id) {
 			u8 guc_class = xe_hwe_to_guc_class(hwe);
+			u16 guc_logical_instance = xe_hwe_guc_logical_instance(hwe);
 			u32 mask = groups[group].engines[guc_class];
 
-			if (mask & BIT(hwe->logical_instance)) {
+			if (mask & BIT(guc_logical_instance)) {
 				strlcat(engines, hwe->name, sizeof(engines));
 				strlcat(engines, " ", sizeof(engines));
 			}
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
index cf117bf52d41..cdfe194926d3 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
@@ -472,6 +472,7 @@ static void pf_sched_group_media_slices(struct xe_gt *gt, struct guc_sched_group
 
 	for_each_hw_engine(hwe, gt, id) {
 		u8 guc_class = xe_hwe_to_guc_class(hwe);
+		u16 guc_logical_instance = xe_hwe_guc_logical_instance(hwe);
 
 		switch (hwe->class) {
 		case XE_ENGINE_CLASS_VIDEO_DECODE:
@@ -490,7 +491,7 @@ static void pf_sched_group_media_slices(struct xe_gt *gt, struct guc_sched_group
 			slice = 0;
 		}
 
-		values[slice_to_group[slice]].engines[guc_class] |= BIT(hwe->logical_instance);
+		values[slice_to_group[slice]].engines[guc_class] |= BIT(guc_logical_instance);
 	}
 
 	*groups = values;
diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 0934927e8254..61e3ee19a59b 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -69,6 +69,7 @@ int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
 #endif
 
 u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe);
+u16 xe_hwe_guc_logical_instance(struct xe_hw_engine *hwe);
 
 static inline struct xe_gt *guc_to_gt(struct xe_guc *guc)
 {
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 996eb58f5484..8dd6400827be 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -535,6 +535,23 @@ u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe)
 	}
 }
 
+u16 xe_hwe_guc_logical_instance(struct xe_hw_engine *hwe)
+{
+	struct xe_gt *gt = hwe->gt;
+
+	if (xe_guc_has_paging_engine(&hwe->gt->uc.guc) &&
+	    xe_gt_is_usm_hwe(gt, hwe)) {
+		int shift = gt->usm.paging_hwe0->logical_instance;
+
+		xe_gt_assert(gt, shift <= hwe->logical_instance);
+
+		/* GUC_PAGING_CLASS:guc_logical_instance */
+		return hwe->logical_instance - shift;
+	}
+
+	return hwe->logical_instance;
+}
+
 /*
  * Write the offsets corresponding to the golden LRCs. The actual data is
  * populated later by guc_golden_lrc_populate()
@@ -603,11 +620,14 @@ static void guc_mapping_table_init(struct xe_gt *gt,
 	guc_mapping_table_init_invalid(gt, info_map);
 
 	for_each_hw_engine(hwe, gt, id) {
+		u16 guc_logical_instance;
 		u8 guc_class;
 
 		guc_class = xe_hwe_to_guc_class(hwe);
+		guc_logical_instance = xe_hwe_guc_logical_instance(hwe);
+
 		info_map_write(xe, info_map,
-			       mapping_table[guc_class][hwe->logical_instance],
+			       mapping_table[guc_class][guc_logical_instance],
 			       hwe->instance);
 	}
 }
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
index 150d891d5a09..2feb87492312 100644
--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
@@ -28,6 +28,7 @@ static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_eng
 	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
 	struct engine_activity_buffer *buffer;
 	u16 guc_class = xe_hwe_to_guc_class(hwe);
+	u16 guc_logical_instance = xe_hwe_guc_logical_instance(hwe);
 	size_t offset;
 
 	if (engine_activity->num_functions) {
@@ -39,7 +40,7 @@ static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_eng
 	}
 
 	offset += offsetof(struct guc_engine_activity_data,
-			  engine_activity[guc_class][hwe->logical_instance]);
+			  engine_activity[guc_class][guc_logical_instance]);
 
 	return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
 }
@@ -151,8 +152,9 @@ static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine
 	struct xe_guc *guc = &hwe->gt->uc.guc;
 	struct engine_activity_group *eag = &guc->engine_activity.eag[index];
 	u16 guc_class = xe_hwe_to_guc_class(hwe);
+	u16 guc_logical_instance = xe_hwe_guc_logical_instance(hwe);
 
-	return &eag->engine[guc_class][hwe->logical_instance];
+	return &eag->engine[guc_class][guc_logical_instance];
 }
 
 static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
-- 
2.54.0

[PATCH v2 07/10] drm/xe/guc: handle submit mask with paging engine

[Matthew Auld]

We need to also re-map the submit mask so that we correctly account for
the remapped logical mask of, if the GUC_PAGING_CLASS is in play.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.h        |  1 +
 drivers/gpu/drm/xe/xe_guc_ads.c    | 21 +++++++++++++++++++++
 drivers/gpu/drm/xe/xe_guc_submit.c |  3 ++-
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index 61e3ee19a59b..dd98ceb81026 100644
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -70,6 +70,7 @@ int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
 
 u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe);
 u16 xe_hwe_guc_logical_instance(struct xe_hw_engine *hwe);
+u32 xe_hwe_guc_logical_to_submit_mask(struct xe_hw_engine *hwe, u32 logical_mask);
 
 static inline struct xe_gt *guc_to_gt(struct xe_guc *guc)
 {
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 8dd6400827be..7437d443343e 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -552,6 +552,27 @@ u16 xe_hwe_guc_logical_instance(struct xe_hw_engine *hwe)
 	return hwe->logical_instance;
 }
 
+u32 xe_hwe_guc_logical_to_submit_mask(struct xe_hw_engine *hwe, u32 logical_mask)
+{
+	struct xe_gt *gt = hwe->gt;
+
+	if (xe_gt_is_usm_hwe(gt, hwe)) {
+		int shift = gt->usm.paging_hwe0->logical_instance;
+		u32 paging_logical_mask = gt->usm.paging_logical_mask;
+
+		xe_gt_assert(gt, (logical_mask & paging_logical_mask) == logical_mask);
+
+		/*
+		 * Remap to GUC_PAGING_CLASS logical instance mask, if
+		 * applicable.
+		 */
+		if (xe_guc_has_paging_engine(&hwe->gt->uc.guc))
+			return logical_mask >> shift;
+	}
+
+	return logical_mask;
+}
+
 /*
  * Write the offsets corresponding to the golden LRCs. The actual data is
  * populated later by guc_golden_lrc_populate()
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 1ee4f2434876..53df499df968 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -986,7 +986,8 @@ static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
 	memset(&info, 0, sizeof(info));
 	info.context_idx = q->guc->id;
 	info.engine_class = xe_hwe_to_guc_class(q->hwe);
-	info.engine_submit_mask = q->logical_mask;
+	info.engine_submit_mask =
+		xe_hwe_guc_logical_to_submit_mask(q->hwe, q->logical_mask);
 	info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc));
 	info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));
 	info.flags = CONTEXT_REGISTRATION_FLAG_KMD |
-- 
2.54.0

[PATCH v2 08/10] drm/xe/vf: wire up NUM_PAGING_ENGINE_INSTANCES

[Matthew Auld]

When host PF writes the logical configuration for the GUC PAGING engine,
the VF is meant to query it, and mirror it. Size of N, means we have
paging logical index range [0, N-1], with N fewer normal copy engines.

Agreement is that PF will only spawn PAGING engines on NVL-S+, so this
should be zero on older platforms, where we should simply fallback to
the old behaviour.

TODO: Check the final GuC ABI version before merging

v2 (Sashiko):
  - We can't call use the guc_has_paging_engine() this early in the VF
    code. With that just unconditionally do the query, if the GuC is new
    enough and take the value as-is. With that drop the -1 special case and
    just let the upper layers figure out the rest.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>
---
 drivers/gpu/drm/xe/abi/guc_klvs_abi.h     |  9 ++++++
 drivers/gpu/drm/xe/xe_gt_sriov_vf.c       | 39 +++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_gt_sriov_vf.h       |  1 +
 drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h |  4 +++
 drivers/gpu/drm/xe/xe_hw_engine.c         | 18 +++++++++++
 5 files changed, 71 insertions(+)

diff --git a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
index 644f5a4226d7..608678f8b18c 100644
--- a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
@@ -52,6 +52,12 @@
  * _`GUC_KLV_GLOBAL_CFG_GROUP_SCHEDULING_AVAILABLE` : 0x3001
  *      Tells the driver whether scheduler groups are enabled or not.
  *      Requires GuC ABI 1.26+
+ *
+ * _`GUC_KLV_GLOBAL_CFG_NUM_PAGING_ENGINE_INSTANCES` : 0x3003
+ *      Tells the driver the paging engine configuration.
+ *      Paging engine logical instances are guaranteed to be dense starting at
+ *      index 0.
+ *      Requires GuC ABI 1.35.1+
  */
 
 #define GUC_KLV_GLOBAL_CFG_GMD_ID_KEY			0x3000u
@@ -60,6 +66,9 @@
 #define GUC_KLV_GLOBAL_CFG_GROUP_SCHEDULING_AVAILABLE_KEY	0x3001u
 #define GUC_KLV_GLOBAL_CFG_GROUP_SCHEDULING_AVAILABLE_LEN	1u
 
+#define GUC_KLV_GLOBAL_CFG_NUM_PAGING_ENGINE_INSTANCES_KEY	0x3003u
+#define GUC_KLV_GLOBAL_CFG_NUM_PAGING_ENGINE_INSTANCES_LEN	1u
+
 /**
  * DOC: GuC Self Config KLVs
  *
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
index 0cd9d77f3351..5c1581c9e432 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
@@ -658,6 +658,41 @@ static int vf_cache_sched_groups_status(struct xe_gt *gt)
 	return 0;
 }
 
+static int vf_cache_num_paging_engines(struct xe_gt *gt)
+{
+	struct xe_guc *guc = &gt->uc.guc;
+	struct xe_uc_fw_version guc_version;
+	u32 value = 0;
+	int err;
+
+	xe_gt_sriov_vf_guc_versions(gt, NULL, &guc_version);
+
+	if (MAKE_GUC_VER_STRUCT(guc_version) < MAKE_GUC_VER(1, 35, 1))
+		return 0;
+
+	err = guc_action_query_single_klv32(guc, GUC_KLV_GLOBAL_CFG_NUM_PAGING_ENGINE_INSTANCES_KEY,
+					    &value);
+	if (unlikely(err)) {
+		xe_gt_sriov_err(gt,
+				"Failed to obtain the number of paging instances (%pe)\n",
+				ERR_PTR(err));
+		return err;
+	}
+
+	gt->sriov.vf.runtime.num_paging_engine_instances = value;
+
+	xe_gt_sriov_dbg(gt, "num_paging_engines %u\n", value);
+	return err;
+}
+
+u32 xe_gt_sriov_vf_paging_engines(struct xe_gt *gt)
+{
+	xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
+	xe_gt_assert(gt, gt->sriov.vf.guc_version.major);
+
+	return gt->sriov.vf.runtime.num_paging_engine_instances;
+}
+
 /**
  * xe_gt_sriov_vf_query_config - Query SR-IOV config data over MMIO.
  * @gt: the &xe_gt
@@ -694,6 +729,10 @@ int xe_gt_sriov_vf_query_config(struct xe_gt *gt)
 	if (has_gmdid(xe))
 		vf_cache_gmdid(gt);
 
+	err = vf_cache_num_paging_engines(gt);
+	if (unlikely(err))
+		return err;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
index 79878f21b1da..d171a8242a34 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
@@ -31,6 +31,7 @@ u32 xe_gt_sriov_vf_gmdid(struct xe_gt *gt);
 u16 xe_gt_sriov_vf_guc_ids(struct xe_gt *gt);
 u64 xe_gt_sriov_vf_lmem(struct xe_gt *gt);
 bool xe_gt_sriov_vf_sched_groups_enabled(struct xe_gt *gt);
+u32 xe_gt_sriov_vf_paging_engines(struct xe_gt *gt);
 
 u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg);
 void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val);
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h b/drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h
index 80562ffadb16..21cb9bc1a341 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h
@@ -40,6 +40,10 @@ struct xe_gt_sriov_vf_runtime {
 		/** @regs.value: register value. */
 		u32 value;
 	} *regs;
+	/**
+	 * @num_paging_engine_instances: number of configured paging engines.
+	 */
+	u32 num_paging_engine_instances;
 };
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 77f882cd8ff8..c279a7dc62e2 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -669,6 +669,24 @@ static void hw_engine_setup_logical_and_paging_mapping(struct xe_gt *gt)
 	if (num_copy_engines && xe->info.has_usm)
 		num_paging_engines = 1;
 
+	if (IS_SRIOV_VF(xe)) {
+		u32 vf_num_paging_engines;
+
+		/*
+		 * PF could in theory reserve multiple paging engines, which
+		 * internally the submission/scheduling backend can load balance
+		 * from. Not something we currently expect, but we are at the
+		 * mercy of the PF, so we just need try our best to mirror the
+		 * paging configuration.
+		 */
+		vf_num_paging_engines = xe_gt_sriov_vf_paging_engines(gt);
+		if (xe->info.platform >= XE_NOVALAKE_S)
+			num_paging_engines = vf_num_paging_engines;
+		else
+			/* This should only be non-zero on NVL-S+ */
+			xe_gt_assert(gt, !vf_num_paging_engines);
+	}
+
 	xe_gt_assert(gt, !(num_copy_engines || num_paging_engines) ||
 		     (num_paging_engines < num_copy_engines));
 
-- 
2.54.0

[PATCH v2 09/10] drm/xe/hw_engine: document top-down paging requirement

[Matthew Auld]

We were doing this anyway, but going forward for paging engines,
agreement is to always reserve BCS instances in top down fashion. This
hopefully future proofs things for VFs, where in some low-level places
it might only have the physical BCS instance from hw pov. If we stick to
a consistent mapping scheme, it should make it possible to determine if
this a special paging engine, or not.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index c279a7dc62e2..5583fd98b08d 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -665,7 +665,6 @@ static void hw_engine_setup_logical_and_paging_mapping(struct xe_gt *gt)
 		if (hwe->class == XE_ENGINE_CLASS_COPY)
 			num_copy_engines++;
 
-	/* We just reserve the highest BCS instance for USM */
 	if (num_copy_engines && xe->info.has_usm)
 		num_paging_engines = 1;
 
@@ -690,6 +689,16 @@ static void hw_engine_setup_logical_and_paging_mapping(struct xe_gt *gt)
 	xe_gt_assert(gt, !(num_copy_engines || num_paging_engines) ||
 		     (num_paging_engines < num_copy_engines));
 
+	/*
+	 * On PF, we just reserve the highest BCS instance for USM.
+	 *
+	 * Note: This is now a requirement going forward. The PF must ALWAYS
+	 * reserve BCS instances in top down order, that way the VF has a chance
+	 * of discovering the physical BCS instance mappings for paging engines,
+	 * in conjunction with vf_num_paging_engines. In some places we might
+	 * only have the physical instance, and from hw pov there is no such
+	 * thing as a paging engine.
+	 */
 	reserved_logical_bcs_start = num_copy_engines - num_paging_engines;
 
 	/* FIXME: Doing a simple logical mapping that works for most hardware */
-- 
2.54.0

[PATCH v2 10/10] drm/xe/guc: toggle paging engine support for NVL-S+

[Matthew Auld]

NVL-S with newest GuC should be the first platform combo to
support the special GUC_PAGING_CLASS feature.

TODO: Check the final GuC ABI version before merging

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index cdbcad79b060..16a9ea8deeb3 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -1848,6 +1848,9 @@ bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
 
 bool xe_guc_has_paging_engine(struct xe_guc *guc)
 {
+	struct xe_gt *gt = guc_to_gt(guc);
+	struct xe_device *xe = gt_to_xe(gt);
+
 	/*
 	 * On newer platforms the GuC now has a dedicated engine class for the
 	 * special PAGING engine, which is the driver reserved BCS engine used
@@ -1856,9 +1859,8 @@ bool xe_guc_has_paging_engine(struct xe_guc *guc)
 	 * engine here, this purely a sw view in the GuC itself, which we need
 	 * to respect.
 	 */
-
-	/* TODO: Have some way to query this from the GuC? */
-	return false;
+	return GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 35, 1) &&
+	       xe->info.platform >= XE_NOVALAKE_S;
 }
 
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
-- 
2.54.0

✓ CI.KUnit: success for GuC paging engine support (rev2)

[Patchwork]

== Series Details ==

Series: GuC paging engine support (rev2)
URL   : https://patchwork.freedesktop.org/series/166960/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[13:56:24] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:56:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:57:00] Starting KUnit Kernel (1/1)...
[13:57:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:57:00] ================== guc_buf (11 subtests) ===================
[13:57:00] [PASSED] test_smallest
[13:57:00] [PASSED] test_largest
[13:57:00] [PASSED] test_granular
[13:57:00] [PASSED] test_unique
[13:57:00] [PASSED] test_overlap
[13:57:00] [PASSED] test_reusable
[13:57:00] [PASSED] test_too_big
[13:57:00] [PASSED] test_flush
[13:57:00] [PASSED] test_lookup
[13:57:00] [PASSED] test_data
[13:57:00] [PASSED] test_class
[13:57:00] ===================== [PASSED] guc_buf =====================
[13:57:00] =================== guc_dbm (7 subtests) ===================
[13:57:00] [PASSED] test_empty
[13:57:00] [PASSED] test_default
[13:57:00] ======================== test_size  ========================
[13:57:00] [PASSED] 4
[13:57:00] [PASSED] 8
[13:57:00] [PASSED] 32
[13:57:00] [PASSED] 256
[13:57:00] ==================== [PASSED] test_size ====================
[13:57:00] ======================= test_reuse  ========================
[13:57:00] [PASSED] 4
[13:57:00] [PASSED] 8
[13:57:00] [PASSED] 32
[13:57:00] [PASSED] 256
[13:57:00] =================== [PASSED] test_reuse ====================
[13:57:00] =================== test_range_overlap  ====================
[13:57:00] [PASSED] 4
[13:57:00] [PASSED] 8
[13:57:00] [PASSED] 32
[13:57:00] [PASSED] 256
[13:57:00] =============== [PASSED] test_range_overlap ================
[13:57:00] =================== test_range_compact  ====================
[13:57:00] [PASSED] 4
[13:57:00] [PASSED] 8
[13:57:00] [PASSED] 32
[13:57:00] [PASSED] 256
[13:57:00] =============== [PASSED] test_range_compact ================
[13:57:00] ==================== test_range_spare  =====================
[13:57:00] [PASSED] 4
[13:57:00] [PASSED] 8
[13:57:00] [PASSED] 32
[13:57:00] [PASSED] 256
[13:57:00] ================ [PASSED] test_range_spare =================
[13:57:00] ===================== [PASSED] guc_dbm =====================
[13:57:00] =================== guc_idm (6 subtests) ===================
[13:57:00] [PASSED] bad_init
[13:57:00] [PASSED] no_init
[13:57:00] [PASSED] init_fini
[13:57:00] [PASSED] check_used
[13:57:00] [PASSED] check_quota
[13:57:00] [PASSED] check_all
[13:57:00] ===================== [PASSED] guc_idm =====================
[13:57:00] ================== no_relay (3 subtests) ===================
[13:57:00] [PASSED] xe_drops_guc2pf_if_not_ready
[13:57:00] [PASSED] xe_drops_guc2vf_if_not_ready
[13:57:00] [PASSED] xe_rejects_send_if_not_ready
[13:57:00] ==================== [PASSED] no_relay =====================
[13:57:00] ================== pf_relay (14 subtests) ==================
[13:57:00] [PASSED] pf_rejects_guc2pf_too_short
[13:57:00] [PASSED] pf_rejects_guc2pf_too_long
[13:57:00] [PASSED] pf_rejects_guc2pf_no_payload
[13:57:00] [PASSED] pf_fails_no_payload
[13:57:00] [PASSED] pf_fails_bad_origin
[13:57:00] [PASSED] pf_fails_bad_type
[13:57:00] [PASSED] pf_txn_reports_error
[13:57:00] [PASSED] pf_txn_sends_pf2guc
[13:57:00] [PASSED] pf_sends_pf2guc
[13:57:00] [SKIPPED] pf_loopback_nop
[13:57:00] [SKIPPED] pf_loopback_echo
[13:57:00] [SKIPPED] pf_loopback_fail
[13:57:00] [SKIPPED] pf_loopback_busy
[13:57:00] [SKIPPED] pf_loopback_retry
[13:57:00] ==================== [PASSED] pf_relay =====================
[13:57:00] ================== vf_relay (3 subtests) ===================
[13:57:00] [PASSED] vf_rejects_guc2vf_too_short
[13:57:00] [PASSED] vf_rejects_guc2vf_too_long
[13:57:00] [PASSED] vf_rejects_guc2vf_no_payload
[13:57:00] ==================== [PASSED] vf_relay =====================
[13:57:00] ================ pf_gt_config (9 subtests) =================
[13:57:00] [PASSED] fair_contexts_1vf
[13:57:00] [PASSED] fair_doorbells_1vf
[13:57:00] [PASSED] fair_ggtt_1vf
[13:57:00] ====================== fair_vram_1vf  ======================
[13:57:00] [PASSED] 3.50 GiB
[13:57:00] [PASSED] 11.5 GiB
[13:57:00] [PASSED] 15.5 GiB
[13:57:00] [PASSED] 31.5 GiB
[13:57:00] [PASSED] 63.5 GiB
[13:57:00] [PASSED] 1.91 GiB
[13:57:00] ================== [PASSED] fair_vram_1vf ==================
[13:57:00] ================ fair_vram_1vf_admin_only  =================
[13:57:00] [PASSED] 3.50 GiB
[13:57:00] [PASSED] 11.5 GiB
[13:57:00] [PASSED] 15.5 GiB
[13:57:00] [PASSED] 31.5 GiB
[13:57:00] [PASSED] 63.5 GiB
[13:57:00] [PASSED] 1.91 GiB
[13:57:00] ============ [PASSED] fair_vram_1vf_admin_only =============
[13:57:00] ====================== fair_contexts  ======================
[13:57:00] [PASSED] 1 VF
[13:57:00] [PASSED] 2 VFs
[13:57:00] [PASSED] 3 VFs
[13:57:00] [PASSED] 4 VFs
[13:57:00] [PASSED] 5 VFs
[13:57:00] [PASSED] 6 VFs
[13:57:00] [PASSED] 7 VFs
[13:57:00] [PASSED] 8 VFs
[13:57:00] [PASSED] 9 VFs
[13:57:00] [PASSED] 10 VFs
[13:57:00] [PASSED] 11 VFs
[13:57:00] [PASSED] 12 VFs
[13:57:00] [PASSED] 13 VFs
[13:57:00] [PASSED] 14 VFs
[13:57:00] [PASSED] 15 VFs
[13:57:00] [PASSED] 16 VFs
[13:57:00] [PASSED] 17 VFs
[13:57:00] [PASSED] 18 VFs
[13:57:00] [PASSED] 19 VFs
[13:57:00] [PASSED] 20 VFs
[13:57:00] [PASSED] 21 VFs
[13:57:00] [PASSED] 22 VFs
[13:57:00] [PASSED] 23 VFs
[13:57:00] [PASSED] 24 VFs
[13:57:00] [PASSED] 25 VFs
[13:57:00] [PASSED] 26 VFs
[13:57:00] [PASSED] 27 VFs
[13:57:00] [PASSED] 28 VFs
[13:57:00] [PASSED] 29 VFs
[13:57:00] [PASSED] 30 VFs
[13:57:00] [PASSED] 31 VFs
[13:57:00] [PASSED] 32 VFs
[13:57:00] [PASSED] 33 VFs
[13:57:00] [PASSED] 34 VFs
[13:57:00] [PASSED] 35 VFs
[13:57:00] [PASSED] 36 VFs
[13:57:00] [PASSED] 37 VFs
[13:57:00] [PASSED] 38 VFs
[13:57:00] [PASSED] 39 VFs
[13:57:00] [PASSED] 40 VFs
[13:57:00] [PASSED] 41 VFs
[13:57:00] [PASSED] 42 VFs
[13:57:00] [PASSED] 43 VFs
[13:57:00] [PASSED] 44 VFs
[13:57:00] [PASSED] 45 VFs
[13:57:00] [PASSED] 46 VFs
[13:57:00] [PASSED] 47 VFs
[13:57:00] [PASSED] 48 VFs
[13:57:00] [PASSED] 49 VFs
[13:57:00] [PASSED] 50 VFs
[13:57:00] [PASSED] 51 VFs
[13:57:00] [PASSED] 52 VFs
[13:57:00] [PASSED] 53 VFs
[13:57:00] [PASSED] 54 VFs
[13:57:00] [PASSED] 55 VFs
[13:57:00] [PASSED] 56 VFs
[13:57:00] [PASSED] 57 VFs
[13:57:00] [PASSED] 58 VFs
[13:57:00] [PASSED] 59 VFs
[13:57:00] [PASSED] 60 VFs
[13:57:00] [PASSED] 61 VFs
[13:57:00] [PASSED] 62 VFs
[13:57:00] [PASSED] 63 VFs
[13:57:00] ================== [PASSED] fair_contexts ==================
[13:57:00] ===================== fair_doorbells  ======================
[13:57:00] [PASSED] 1 VF
[13:57:00] [PASSED] 2 VFs
[13:57:00] [PASSED] 3 VFs
[13:57:00] [PASSED] 4 VFs
[13:57:00] [PASSED] 5 VFs
[13:57:00] [PASSED] 6 VFs
[13:57:00] [PASSED] 7 VFs
[13:57:00] [PASSED] 8 VFs
[13:57:00] [PASSED] 9 VFs
[13:57:00] [PASSED] 10 VFs
[13:57:00] [PASSED] 11 VFs
[13:57:00] [PASSED] 12 VFs
[13:57:00] [PASSED] 13 VFs
[13:57:00] [PASSED] 14 VFs
[13:57:00] [PASSED] 15 VFs
[13:57:00] [PASSED] 16 VFs
[13:57:00] [PASSED] 17 VFs
[13:57:00] [PASSED] 18 VFs
[13:57:00] [PASSED] 19 VFs
[13:57:00] [PASSED] 20 VFs
[13:57:00] [PASSED] 21 VFs
[13:57:00] [PASSED] 22 VFs
[13:57:00] [PASSED] 23 VFs
[13:57:00] [PASSED] 24 VFs
[13:57:00] [PASSED] 25 VFs
[13:57:00] [PASSED] 26 VFs
[13:57:00] [PASSED] 27 VFs
[13:57:00] [PASSED] 28 VFs
[13:57:00] [PASSED] 29 VFs
[13:57:00] [PASSED] 30 VFs
[13:57:00] [PASSED] 31 VFs
[13:57:00] [PASSED] 32 VFs
[13:57:00] [PASSED] 33 VFs
[13:57:00] [PASSED] 34 VFs
[13:57:00] [PASSED] 35 VFs
[13:57:00] [PASSED] 36 VFs
[13:57:00] [PASSED] 37 VFs
[13:57:00] [PASSED] 38 VFs
[13:57:00] [PASSED] 39 VFs
[13:57:00] [PASSED] 40 VFs
[13:57:00] [PASSED] 41 VFs
[13:57:00] [PASSED] 42 VFs
[13:57:00] [PASSED] 43 VFs
[13:57:00] [PASSED] 44 VFs
[13:57:00] [PASSED] 45 VFs
[13:57:00] [PASSED] 46 VFs
[13:57:00] [PASSED] 47 VFs
[13:57:00] [PASSED] 48 VFs
[13:57:00] [PASSED] 49 VFs
[13:57:00] [PASSED] 50 VFs
[13:57:00] [PASSED] 51 VFs
[13:57:00] [PASSED] 52 VFs
[13:57:00] [PASSED] 53 VFs
[13:57:00] [PASSED] 54 VFs
[13:57:00] [PASSED] 55 VFs
[13:57:00] [PASSED] 56 VFs
[13:57:00] [PASSED] 57 VFs
[13:57:00] [PASSED] 58 VFs
[13:57:00] [PASSED] 59 VFs
[13:57:00] [PASSED] 60 VFs
[13:57:00] [PASSED] 61 VFs
[13:57:00] [PASSED] 62 VFs
[13:57:00] [PASSED] 63 VFs
[13:57:00] ================= [PASSED] fair_doorbells ==================
[13:57:00] ======================== fair_ggtt  ========================
[13:57:00] [PASSED] 1 VF
[13:57:00] [PASSED] 2 VFs
[13:57:00] [PASSED] 3 VFs
[13:57:00] [PASSED] 4 VFs
[13:57:00] [PASSED] 5 VFs
[13:57:00] [PASSED] 6 VFs
[13:57:00] [PASSED] 7 VFs
[13:57:00] [PASSED] 8 VFs
[13:57:00] [PASSED] 9 VFs
[13:57:00] [PASSED] 10 VFs
[13:57:00] [PASSED] 11 VFs
[13:57:00] [PASSED] 12 VFs
[13:57:00] [PASSED] 13 VFs
[13:57:00] [PASSED] 14 VFs
[13:57:00] [PASSED] 15 VFs
[13:57:00] [PASSED] 16 VFs
[13:57:00] [PASSED] 17 VFs
[13:57:00] [PASSED] 18 VFs
[13:57:00] [PASSED] 19 VFs
[13:57:00] [PASSED] 20 VFs
[13:57:00] [PASSED] 21 VFs
[13:57:00] [PASSED] 22 VFs
[13:57:00] [PASSED] 23 VFs
[13:57:00] [PASSED] 24 VFs
[13:57:00] [PASSED] 25 VFs
[13:57:00] [PASSED] 26 VFs
[13:57:00] [PASSED] 27 VFs
[13:57:00] [PASSED] 28 VFs
[13:57:00] [PASSED] 29 VFs
[13:57:00] [PASSED] 30 VFs
[13:57:00] [PASSED] 31 VFs
[13:57:00] [PASSED] 32 VFs
[13:57:00] [PASSED] 33 VFs
[13:57:00] [PASSED] 34 VFs
[13:57:00] [PASSED] 35 VFs
[13:57:00] [PASSED] 36 VFs
[13:57:00] [PASSED] 37 VFs
[13:57:00] [PASSED] 38 VFs
[13:57:00] [PASSED] 39 VFs
[13:57:00] [PASSED] 40 VFs
[13:57:00] [PASSED] 41 VFs
[13:57:00] [PASSED] 42 VFs
[13:57:00] [PASSED] 43 VFs
[13:57:00] [PASSED] 44 VFs
[13:57:00] [PASSED] 45 VFs
[13:57:00] [PASSED] 46 VFs
[13:57:00] [PASSED] 47 VFs
[13:57:00] [PASSED] 48 VFs
[13:57:00] [PASSED] 49 VFs
[13:57:00] [PASSED] 50 VFs
[13:57:00] [PASSED] 51 VFs
[13:57:00] [PASSED] 52 VFs
[13:57:00] [PASSED] 53 VFs
[13:57:00] [PASSED] 54 VFs
[13:57:00] [PASSED] 55 VFs
[13:57:00] [PASSED] 56 VFs
[13:57:00] [PASSED] 57 VFs
[13:57:00] [PASSED] 58 VFs
[13:57:00] [PASSED] 59 VFs
[13:57:00] [PASSED] 60 VFs
[13:57:00] [PASSED] 61 VFs
[13:57:00] [PASSED] 62 VFs
[13:57:00] [PASSED] 63 VFs
[13:57:00] ==================== [PASSED] fair_ggtt ====================
[13:57:00] ======================== fair_vram  ========================
[13:57:00] [PASSED] 1 VF
[13:57:00] [PASSED] 2 VFs
[13:57:00] [PASSED] 3 VFs
[13:57:00] [PASSED] 4 VFs
[13:57:00] [PASSED] 5 VFs
[13:57:00] [PASSED] 6 VFs
[13:57:00] [PASSED] 7 VFs
[13:57:00] [PASSED] 8 VFs
[13:57:00] [PASSED] 9 VFs
[13:57:00] [PASSED] 10 VFs
[13:57:00] [PASSED] 11 VFs
[13:57:00] [PASSED] 12 VFs
[13:57:00] [PASSED] 13 VFs
[13:57:00] [PASSED] 14 VFs
[13:57:00] [PASSED] 15 VFs
[13:57:00] [PASSED] 16 VFs
[13:57:00] [PASSED] 17 VFs
[13:57:00] [PASSED] 18 VFs
[13:57:00] [PASSED] 19 VFs
[13:57:00] [PASSED] 20 VFs
[13:57:00] [PASSED] 21 VFs
[13:57:00] [PASSED] 22 VFs
[13:57:00] [PASSED] 23 VFs
[13:57:00] [PASSED] 24 VFs
[13:57:00] [PASSED] 25 VFs
[13:57:00] [PASSED] 26 VFs
[13:57:00] [PASSED] 27 VFs
[13:57:00] [PASSED] 28 VFs
[13:57:00] [PASSED] 29 VFs
[13:57:00] [PASSED] 30 VFs
[13:57:00] [PASSED] 31 VFs
[13:57:00] [PASSED] 32 VFs
[13:57:00] [PASSED] 33 VFs
[13:57:00] [PASSED] 34 VFs
[13:57:00] [PASSED] 35 VFs
[13:57:00] [PASSED] 36 VFs
[13:57:00] [PASSED] 37 VFs
[13:57:00] [PASSED] 38 VFs
[13:57:00] [PASSED] 39 VFs
[13:57:00] [PASSED] 40 VFs
[13:57:00] [PASSED] 41 VFs
[13:57:00] [PASSED] 42 VFs
[13:57:00] [PASSED] 43 VFs
[13:57:00] [PASSED] 44 VFs
[13:57:00] [PASSED] 45 VFs
[13:57:00] [PASSED] 46 VFs
[13:57:00] [PASSED] 47 VFs
[13:57:00] [PASSED] 48 VFs
[13:57:00] [PASSED] 49 VFs
[13:57:00] [PASSED] 50 VFs
[13:57:00] [PASSED] 51 VFs
[13:57:00] [PASSED] 52 VFs
[13:57:00] [PASSED] 53 VFs
[13:57:00] [PASSED] 54 VFs
[13:57:00] [PASSED] 55 VFs
[13:57:00] [PASSED] 56 VFs
[13:57:00] [PASSED] 57 VFs
[13:57:00] [PASSED] 58 VFs
[13:57:00] [PASSED] 59 VFs
[13:57:00] [PASSED] 60 VFs
[13:57:00] [PASSED] 61 VFs
[13:57:00] [PASSED] 62 VFs
[13:57:00] [PASSED] 63 VFs
[13:57:00] ==================== [PASSED] fair_vram ====================
[13:57:00] ================== [PASSED] pf_gt_config ===================
[13:57:00] ===================== lmtt (1 subtest) =====================
[13:57:00] ======================== test_ops  =========================
[13:57:00] [PASSED] 2-level
[13:57:00] [PASSED] multi-level
[13:57:00] ==================== [PASSED] test_ops =====================
[13:57:00] ====================== [PASSED] lmtt =======================
[13:57:00] ================= pf_service (11 subtests) =================
[13:57:00] [PASSED] pf_negotiate_any
[13:57:00] [PASSED] pf_negotiate_base_match
[13:57:00] [PASSED] pf_negotiate_base_newer
[13:57:00] [PASSED] pf_negotiate_base_next
[13:57:00] [SKIPPED] pf_negotiate_base_older
[13:57:00] [PASSED] pf_negotiate_base_prev
[13:57:00] [PASSED] pf_negotiate_latest_match
[13:57:00] [PASSED] pf_negotiate_latest_newer
[13:57:00] [PASSED] pf_negotiate_latest_next
[13:57:00] [SKIPPED] pf_negotiate_latest_older
[13:57:00] [SKIPPED] pf_negotiate_latest_prev
[13:57:00] =================== [PASSED] pf_service ====================
[13:57:00] ================= xe_guc_g2g (2 subtests) ==================
[13:57:00] ============== xe_live_guc_g2g_kunit_default  ==============
[13:57:00] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[13:57:00] ============== xe_live_guc_g2g_kunit_allmem  ===============
[13:57:00] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[13:57:00] =================== [SKIPPED] xe_guc_g2g ===================
[13:57:00] =================== xe_mocs (2 subtests) ===================
[13:57:00] ================ xe_live_mocs_kernel_kunit  ================
[13:57:00] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[13:57:00] ================ xe_live_mocs_reset_kunit  =================
[13:57:00] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[13:57:00] ==================== [SKIPPED] xe_mocs =====================
[13:57:00] ================= xe_migrate (2 subtests) ==================
[13:57:00] ================= xe_migrate_sanity_kunit  =================
[13:57:00] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[13:57:00] ================== xe_validate_ccs_kunit  ==================
[13:57:00] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[13:57:00] =================== [SKIPPED] xe_migrate ===================
[13:57:00] ================== xe_dma_buf (1 subtest) ==================
[13:57:00] ==================== xe_dma_buf_kunit  =====================
[13:57:00] ================ [SKIPPED] xe_dma_buf_kunit ================
[13:57:00] =================== [SKIPPED] xe_dma_buf ===================
[13:57:00] ================= xe_bo_shrink (1 subtest) =================
[13:57:00] =================== xe_bo_shrink_kunit  ====================
[13:57:00] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[13:57:00] ================== [SKIPPED] xe_bo_shrink ==================
[13:57:00] ==================== xe_bo (2 subtests) ====================
[13:57:00] ================== xe_ccs_migrate_kunit  ===================
[13:57:00] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[13:57:00] ==================== xe_bo_evict_kunit  ====================
[13:57:00] =============== [SKIPPED] xe_bo_evict_kunit ================
[13:57:00] ===================== [SKIPPED] xe_bo ======================
[13:57:00] ==================== args (13 subtests) ====================
[13:57:00] [PASSED] count_args_test
[13:57:00] [PASSED] call_args_example
[13:57:00] [PASSED] call_args_test
[13:57:00] [PASSED] drop_first_arg_example
[13:57:00] [PASSED] drop_first_arg_test
[13:57:00] [PASSED] first_arg_example
[13:57:00] [PASSED] first_arg_test
[13:57:00] [PASSED] last_arg_example
[13:57:00] [PASSED] last_arg_test
[13:57:00] [PASSED] pick_arg_example
[13:57:00] [PASSED] if_args_example
[13:57:00] [PASSED] if_args_test
[13:57:00] [PASSED] sep_comma_example
[13:57:00] ====================== [PASSED] args =======================
[13:57:00] =================== xe_pci (3 subtests) ====================
[13:57:00] ==================== check_graphics_ip  ====================
[13:57:00] [PASSED] 12.00 Xe_LP
[13:57:00] [PASSED] 12.10 Xe_LP+
[13:57:00] [PASSED] 12.55 Xe_HPG
[13:57:00] [PASSED] 12.60 Xe_HPC
[13:57:00] [PASSED] 12.70 Xe_LPG
[13:57:00] [PASSED] 12.71 Xe_LPG
[13:57:00] [PASSED] 12.74 Xe_LPG+
[13:57:00] [PASSED] 20.01 Xe2_HPG
[13:57:00] [PASSED] 20.02 Xe2_HPG
[13:57:00] [PASSED] 20.04 Xe2_LPG
[13:57:00] [PASSED] 30.00 Xe3_LPG
[13:57:00] [PASSED] 30.01 Xe3_LPG
[13:57:00] [PASSED] 30.03 Xe3_LPG
[13:57:00] [PASSED] 30.04 Xe3_LPG
[13:57:00] [PASSED] 30.05 Xe3_LPG
[13:57:00] [PASSED] 35.10 Xe3p_LPG
[13:57:00] [PASSED] 35.11 Xe3p_XPC
[13:57:00] ================ [PASSED] check_graphics_ip ================
[13:57:00] ===================== check_media_ip  ======================
[13:57:00] [PASSED] 12.00 Xe_M
[13:57:00] [PASSED] 12.55 Xe_HPM
[13:57:00] [PASSED] 13.00 Xe_LPM+
[13:57:00] [PASSED] 13.01 Xe2_HPM
[13:57:00] [PASSED] 20.00 Xe2_LPM
[13:57:00] [PASSED] 30.00 Xe3_LPM
[13:57:00] [PASSED] 30.02 Xe3_LPM
[13:57:00] [PASSED] 35.00 Xe3p_LPM
[13:57:00] [PASSED] 35.03 Xe3p_HPM
[13:57:00] ================= [PASSED] check_media_ip ==================
[13:57:00] =================== check_platform_desc  ===================
[13:57:00] [PASSED] 0x9A60 (TIGERLAKE)
[13:57:00] [PASSED] 0x9A68 (TIGERLAKE)
[13:57:00] [PASSED] 0x9A70 (TIGERLAKE)
[13:57:00] [PASSED] 0x9A40 (TIGERLAKE)
[13:57:00] [PASSED] 0x9A49 (TIGERLAKE)
[13:57:00] [PASSED] 0x9A59 (TIGERLAKE)
[13:57:00] [PASSED] 0x9A78 (TIGERLAKE)
[13:57:00] [PASSED] 0x9AC0 (TIGERLAKE)
[13:57:00] [PASSED] 0x9AC9 (TIGERLAKE)
[13:57:00] [PASSED] 0x9AD9 (TIGERLAKE)
[13:57:00] [PASSED] 0x9AF8 (TIGERLAKE)
[13:57:00] [PASSED] 0x4C80 (ROCKETLAKE)
[13:57:00] [PASSED] 0x4C8A (ROCKETLAKE)
[13:57:00] [PASSED] 0x4C8B (ROCKETLAKE)
[13:57:00] [PASSED] 0x4C8C (ROCKETLAKE)
[13:57:00] [PASSED] 0x4C90 (ROCKETLAKE)
[13:57:00] [PASSED] 0x4C9A (ROCKETLAKE)
[13:57:00] [PASSED] 0x4680 (ALDERLAKE_S)
[13:57:00] [PASSED] 0x4682 (ALDERLAKE_S)
[13:57:00] [PASSED] 0x4688 (ALDERLAKE_S)
[13:57:00] [PASSED] 0x468A (ALDERLAKE_S)
[13:57:00] [PASSED] 0x468B (ALDERLAKE_S)
[13:57:00] [PASSED] 0x4690 (ALDERLAKE_S)
[13:57:00] [PASSED] 0x4692 (ALDERLAKE_S)
[13:57:00] [PASSED] 0x4693 (ALDERLAKE_S)
[13:57:00] [PASSED] 0x46A0 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46A1 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46A2 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46A3 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46A6 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46A8 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46AA (ALDERLAKE_P)
[13:57:00] [PASSED] 0x462A (ALDERLAKE_P)
[13:57:00] [PASSED] 0x4626 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x4628 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46B0 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46B1 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46B2 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46B3 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46C0 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46C1 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46C2 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46C3 (ALDERLAKE_P)
[13:57:00] [PASSED] 0x46D0 (ALDERLAKE_N)
[13:57:00] [PASSED] 0x46D1 (ALDERLAKE_N)
[13:57:00] [PASSED] 0x46D2 (ALDERLAKE_N)
[13:57:00] [PASSED] 0x46D3 (ALDERLAKE_N)
[13:57:00] [PASSED] 0x46D4 (ALDERLAKE_N)
[13:57:00] [PASSED] 0xA721 (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA7A1 (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA7A9 (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA7AC (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA7AD (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA720 (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA7A0 (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA7A8 (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA7AA (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA7AB (ALDERLAKE_P)
[13:57:00] [PASSED] 0xA780 (ALDERLAKE_S)
[13:57:00] [PASSED] 0xA781 (ALDERLAKE_S)
[13:57:00] [PASSED] 0xA782 (ALDERLAKE_S)
[13:57:00] [PASSED] 0xA783 (ALDERLAKE_S)
[13:57:00] [PASSED] 0xA788 (ALDERLAKE_S)
[13:57:00] [PASSED] 0xA789 (ALDERLAKE_S)
[13:57:00] [PASSED] 0xA78A (ALDERLAKE_S)
[13:57:00] [PASSED] 0xA78B (ALDERLAKE_S)
[13:57:00] [PASSED] 0x4905 (DG1)
[13:57:00] [PASSED] 0x4906 (DG1)
[13:57:00] [PASSED] 0x4907 (DG1)
[13:57:00] [PASSED] 0x4908 (DG1)
[13:57:00] [PASSED] 0x4909 (DG1)
[13:57:00] [PASSED] 0x56C0 (DG2)
[13:57:00] [PASSED] 0x56C2 (DG2)
[13:57:00] [PASSED] 0x56C1 (DG2)
[13:57:00] [PASSED] 0x7D51 (METEORLAKE)
[13:57:00] [PASSED] 0x7DD1 (METEORLAKE)
[13:57:00] [PASSED] 0x7D41 (METEORLAKE)
[13:57:00] [PASSED] 0x7D67 (METEORLAKE)
[13:57:00] [PASSED] 0xB640 (METEORLAKE)
[13:57:00] [PASSED] 0x56A0 (DG2)
[13:57:00] [PASSED] 0x56A1 (DG2)
[13:57:00] [PASSED] 0x56A2 (DG2)
[13:57:00] [PASSED] 0x56BE (DG2)
[13:57:00] [PASSED] 0x56BF (DG2)
[13:57:00] [PASSED] 0x5690 (DG2)
[13:57:00] [PASSED] 0x5691 (DG2)
[13:57:00] [PASSED] 0x5692 (DG2)
[13:57:00] [PASSED] 0x56A5 (DG2)
[13:57:00] [PASSED] 0x56A6 (DG2)
[13:57:00] [PASSED] 0x56B0 (DG2)
[13:57:00] [PASSED] 0x56B1 (DG2)
[13:57:00] [PASSED] 0x56BA (DG2)
[13:57:00] [PASSED] 0x56BB (DG2)
[13:57:00] [PASSED] 0x56BC (DG2)
[13:57:00] [PASSED] 0x56BD (DG2)
[13:57:00] [PASSED] 0x5693 (DG2)
[13:57:00] [PASSED] 0x5694 (DG2)
[13:57:00] [PASSED] 0x5695 (DG2)
[13:57:00] [PASSED] 0x56A3 (DG2)
[13:57:00] [PASSED] 0x56A4 (DG2)
[13:57:00] [PASSED] 0x56B2 (DG2)
[13:57:00] [PASSED] 0x56B3 (DG2)
[13:57:00] [PASSED] 0x5696 (DG2)
[13:57:00] [PASSED] 0x5697 (DG2)
[13:57:00] [PASSED] 0xB69 (PVC)
[13:57:00] [PASSED] 0xB6E (PVC)
[13:57:00] [PASSED] 0xBD4 (PVC)
[13:57:00] [PASSED] 0xBD5 (PVC)
[13:57:00] [PASSED] 0xBD6 (PVC)
[13:57:00] [PASSED] 0xBD7 (PVC)
[13:57:00] [PASSED] 0xBD8 (PVC)
[13:57:00] [PASSED] 0xBD9 (PVC)
[13:57:00] [PASSED] 0xBDA (PVC)
[13:57:00] [PASSED] 0xBDB (PVC)
[13:57:00] [PASSED] 0xBE0 (PVC)
[13:57:00] [PASSED] 0xBE1 (PVC)
[13:57:00] [PASSED] 0xBE5 (PVC)
[13:57:00] [PASSED] 0x7D40 (METEORLAKE)
[13:57:00] [PASSED] 0x7D45 (METEORLAKE)
[13:57:00] [PASSED] 0x7D55 (METEORLAKE)
[13:57:00] [PASSED] 0x7D60 (METEORLAKE)
[13:57:00] [PASSED] 0x7DD5 (METEORLAKE)
[13:57:00] [PASSED] 0x6420 (LUNARLAKE)
[13:57:00] [PASSED] 0x64A0 (LUNARLAKE)
[13:57:00] [PASSED] 0x64B0 (LUNARLAKE)
[13:57:00] [PASSED] 0xE202 (BATTLEMAGE)
[13:57:00] [PASSED] 0xE209 (BATTLEMAGE)
[13:57:00] [PASSED] 0xE20B (BATTLEMAGE)
[13:57:00] [PASSED] 0xE20C (BATTLEMAGE)
[13:57:00] [PASSED] 0xE20D (BATTLEMAGE)
[13:57:00] [PASSED] 0xE210 (BATTLEMAGE)
[13:57:00] [PASSED] 0xE211 (BATTLEMAGE)
[13:57:00] [PASSED] 0xE212 (BATTLEMAGE)
[13:57:00] [PASSED] 0xE216 (BATTLEMAGE)
[13:57:00] [PASSED] 0xE220 (BATTLEMAGE)
[13:57:00] [PASSED] 0xE221 (BATTLEMAGE)
[13:57:00] [PASSED] 0xE222 (BATTLEMAGE)
[13:57:00] [PASSED] 0xE223 (BATTLEMAGE)
[13:57:00] [PASSED] 0xB080 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB081 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB082 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB083 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB084 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB085 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB086 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB087 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB08F (PANTHERLAKE)
[13:57:00] [PASSED] 0xB090 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB0A0 (PANTHERLAKE)
[13:57:00] [PASSED] 0xB0B0 (PANTHERLAKE)
[13:57:00] [PASSED] 0xFD80 (PANTHERLAKE)
[13:57:00] [PASSED] 0xFD81 (PANTHERLAKE)
[13:57:00] [PASSED] 0xD740 (NOVALAKE_S)
[13:57:00] [PASSED] 0xD741 (NOVALAKE_S)
[13:57:00] [PASSED] 0xD742 (NOVALAKE_S)
[13:57:00] [PASSED] 0xD743 (NOVALAKE_S)
[13:57:00] [PASSED] 0xD744 (NOVALAKE_S)
[13:57:00] [PASSED] 0xD745 (NOVALAKE_S)
[13:57:00] [PASSED] 0x674C (CRESCENTISLAND)
[13:57:00] [PASSED] 0x674D (CRESCENTISLAND)
[13:57:00] [PASSED] 0x674E (CRESCENTISLAND)
[13:57:00] [PASSED] 0x674F (CRESCENTISLAND)
[13:57:00] [PASSED] 0x6750 (CRESCENTISLAND)
[13:57:00] [PASSED] 0xD750 (NOVALAKE_P)
[13:57:00] [PASSED] 0xD751 (NOVALAKE_P)
[13:57:00] [PASSED] 0xD752 (NOVALAKE_P)
[13:57:00] [PASSED] 0xD753 (NOVALAKE_P)
[13:57:00] [PASSED] 0xD754 (NOVALAKE_P)
[13:57:00] [PASSED] 0xD755 (NOVALAKE_P)
[13:57:00] [PASSED] 0xD756 (NOVALAKE_P)
[13:57:00] [PASSED] 0xD757 (NOVALAKE_P)
[13:57:00] [PASSED] 0xD75F (NOVALAKE_P)
[13:57:00] =============== [PASSED] check_platform_desc ===============
[13:57:00] ===================== [PASSED] xe_pci ======================
[13:57:00] =================== xe_rtp (2 subtests) ====================
[13:57:00] =============== xe_rtp_process_to_sr_tests  ================
[13:57:00] [PASSED] coalesce-same-reg
[13:57:00] [PASSED] no-match-no-add
[13:57:00] [PASSED] match-or
[13:57:00] [PASSED] match-or-xfail
[13:57:00] [PASSED] no-match-no-add-multiple-rules
[13:57:00] [PASSED] two-regs-two-entries
[13:57:00] [PASSED] clr-one-set-other
[13:57:00] [PASSED] set-field
[13:57:00] [PASSED] conflict-duplicate
[13:57:00] [PASSED] conflict-not-disjoint
[13:57:00] [PASSED] conflict-reg-type
[13:57:00] [PASSED] bad-mcr-reg-forced-to-regular
[13:57:00] [PASSED] bad-regular-reg-forced-to-mcr
[13:57:00] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[13:57:00] ================== xe_rtp_process_tests  ===================
[13:57:00] [PASSED] active1
[13:57:00] [PASSED] active2
[13:57:00] [PASSED] active-inactive
[13:57:00] [PASSED] inactive-active
[13:57:00] [PASSED] inactive-1st_or_active-inactive
[13:57:00] [PASSED] inactive-2nd_or_active-inactive
[13:57:00] [PASSED] inactive-last_or_active-inactive
[13:57:00] [PASSED] inactive-no_or_active-inactive
[13:57:00] ============== [PASSED] xe_rtp_process_tests ===============
[13:57:00] ===================== [PASSED] xe_rtp ======================
[13:57:00] ==================== xe_wa (1 subtest) =====================
[13:57:01] ======================== xe_wa_gt  =========================
[13:57:01] [PASSED] TIGERLAKE B0
[13:57:01] [PASSED] DG1 A0
[13:57:01] [PASSED] DG1 B0
[13:57:01] [PASSED] ALDERLAKE_S A0
[13:57:01] [PASSED] ALDERLAKE_S B0
[13:57:01] [PASSED] ALDERLAKE_S C0
[13:57:01] [PASSED] ALDERLAKE_S D0
[13:57:01] [PASSED] ALDERLAKE_P A0
[13:57:01] [PASSED] ALDERLAKE_P B0
[13:57:01] [PASSED] ALDERLAKE_P C0
[13:57:01] [PASSED] ALDERLAKE_S RPLS D0
[13:57:01] [PASSED] ALDERLAKE_P RPLU E0
[13:57:01] [PASSED] DG2 G10 C0
[13:57:01] [PASSED] DG2 G11 B1
[13:57:01] [PASSED] DG2 G12 A1
[13:57:01] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:57:01] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[13:57:01] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[13:57:01] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[13:57:01] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[13:57:01] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[13:57:01] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[13:57:01] ==================== [PASSED] xe_wa_gt =====================
[13:57:01] ====================== [PASSED] xe_wa ======================
[13:57:01] ============================================================
[13:57:01] Testing complete. Ran 603 tests: passed: 585, skipped: 18
[13:57:01] Elapsed time: 36.285s total, 4.290s configuring, 31.379s building, 0.610s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[13:57:01] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:57:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:57:26] Starting KUnit Kernel (1/1)...
[13:57:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:57:26] ============ drm_test_pick_cmdline (2 subtests) ============
[13:57:26] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[13:57:26] =============== drm_test_pick_cmdline_named  ===============
[13:57:26] [PASSED] NTSC
[13:57:26] [PASSED] NTSC-J
[13:57:26] [PASSED] PAL
[13:57:26] [PASSED] PAL-M
[13:57:26] =========== [PASSED] drm_test_pick_cmdline_named ===========
[13:57:26] ============== [PASSED] drm_test_pick_cmdline ==============
[13:57:26] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[13:57:26] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[13:57:26] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[13:57:26] =========== drm_validate_clone_mode (2 subtests) ===========
[13:57:26] ============== drm_test_check_in_clone_mode  ===============
[13:57:26] [PASSED] in_clone_mode
[13:57:26] [PASSED] not_in_clone_mode
[13:57:26] ========== [PASSED] drm_test_check_in_clone_mode ===========
[13:57:26] =============== drm_test_check_valid_clones  ===============
[13:57:26] [PASSED] not_in_clone_mode
[13:57:26] [PASSED] valid_clone
[13:57:26] [PASSED] invalid_clone
[13:57:26] =========== [PASSED] drm_test_check_valid_clones ===========
[13:57:26] ============= [PASSED] drm_validate_clone_mode =============
[13:57:26] ============= drm_validate_modeset (1 subtest) =============
[13:57:26] [PASSED] drm_test_check_connector_changed_modeset
[13:57:26] ============== [PASSED] drm_validate_modeset ===============
[13:57:26] ====== drm_test_bridge_get_current_state (2 subtests) ======
[13:57:26] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[13:57:26] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[13:57:26] ======== [PASSED] drm_test_bridge_get_current_state ========
[13:57:26] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[13:57:26] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[13:57:26] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[13:57:26] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[13:57:26] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[13:57:26] ============== drm_bridge_alloc (2 subtests) ===============
[13:57:26] [PASSED] drm_test_drm_bridge_alloc_basic
[13:57:26] [PASSED] drm_test_drm_bridge_alloc_get_put
[13:57:26] ================ [PASSED] drm_bridge_alloc =================
[13:57:26] ============= drm_cmdline_parser (40 subtests) =============
[13:57:26] [PASSED] drm_test_cmdline_force_d_only
[13:57:26] [PASSED] drm_test_cmdline_force_D_only_dvi
[13:57:26] [PASSED] drm_test_cmdline_force_D_only_hdmi
[13:57:26] [PASSED] drm_test_cmdline_force_D_only_not_digital
[13:57:26] [PASSED] drm_test_cmdline_force_e_only
[13:57:26] [PASSED] drm_test_cmdline_res
[13:57:26] [PASSED] drm_test_cmdline_res_vesa
[13:57:26] [PASSED] drm_test_cmdline_res_vesa_rblank
[13:57:26] [PASSED] drm_test_cmdline_res_rblank
[13:57:26] [PASSED] drm_test_cmdline_res_bpp
[13:57:26] [PASSED] drm_test_cmdline_res_refresh
[13:57:26] [PASSED] drm_test_cmdline_res_bpp_refresh
[13:57:26] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[13:57:26] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[13:57:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[13:57:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[13:57:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[13:57:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[13:57:26] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[13:57:26] [PASSED] drm_test_cmdline_res_margins_force_on
[13:57:26] [PASSED] drm_test_cmdline_res_vesa_margins
[13:57:26] [PASSED] drm_test_cmdline_name
[13:57:26] [PASSED] drm_test_cmdline_name_bpp
[13:57:26] [PASSED] drm_test_cmdline_name_option
[13:57:26] [PASSED] drm_test_cmdline_name_bpp_option
[13:57:26] [PASSED] drm_test_cmdline_rotate_0
[13:57:26] [PASSED] drm_test_cmdline_rotate_90
[13:57:26] [PASSED] drm_test_cmdline_rotate_180
[13:57:26] [PASSED] drm_test_cmdline_rotate_270
[13:57:26] [PASSED] drm_test_cmdline_hmirror
[13:57:26] [PASSED] drm_test_cmdline_vmirror
[13:57:26] [PASSED] drm_test_cmdline_margin_options
[13:57:26] [PASSED] drm_test_cmdline_multiple_options
[13:57:26] [PASSED] drm_test_cmdline_bpp_extra_and_option
[13:57:26] [PASSED] drm_test_cmdline_extra_and_option
[13:57:26] [PASSED] drm_test_cmdline_freestanding_options
[13:57:26] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[13:57:26] [PASSED] drm_test_cmdline_panel_orientation
[13:57:26] ================ drm_test_cmdline_invalid  =================
[13:57:26] [PASSED] margin_only
[13:57:26] [PASSED] interlace_only
[13:57:26] [PASSED] res_missing_x
[13:57:26] [PASSED] res_missing_y
[13:57:26] [PASSED] res_bad_y
[13:57:26] [PASSED] res_missing_y_bpp
[13:57:26] [PASSED] res_bad_bpp
[13:57:26] [PASSED] res_bad_refresh
[13:57:26] [PASSED] res_bpp_refresh_force_on_off
[13:57:26] [PASSED] res_invalid_mode
[13:57:26] [PASSED] res_bpp_wrong_place_mode
[13:57:26] [PASSED] name_bpp_refresh
[13:57:26] [PASSED] name_refresh
[13:57:26] [PASSED] name_refresh_wrong_mode
[13:57:26] [PASSED] name_refresh_invalid_mode
[13:57:26] [PASSED] rotate_multiple
[13:57:26] [PASSED] rotate_invalid_val
[13:57:26] [PASSED] rotate_truncated
[13:57:26] [PASSED] invalid_option
[13:57:26] [PASSED] invalid_tv_option
[13:57:26] [PASSED] truncated_tv_option
[13:57:26] ============ [PASSED] drm_test_cmdline_invalid =============
[13:57:26] =============== drm_test_cmdline_tv_options  ===============
[13:57:26] [PASSED] NTSC
[13:57:26] [PASSED] NTSC_443
[13:57:26] [PASSED] NTSC_J
[13:57:26] [PASSED] PAL
[13:57:26] [PASSED] PAL_M
[13:57:26] [PASSED] PAL_N
[13:57:26] [PASSED] SECAM
[13:57:26] [PASSED] MONO_525
[13:57:26] [PASSED] MONO_625
[13:57:26] =========== [PASSED] drm_test_cmdline_tv_options ===========
[13:57:26] =============== [PASSED] drm_cmdline_parser ================
[13:57:26] ========== drmm_connector_hdmi_init (20 subtests) ==========
[13:57:26] [PASSED] drm_test_connector_hdmi_init_valid
[13:57:26] [PASSED] drm_test_connector_hdmi_init_bpc_8
[13:57:26] [PASSED] drm_test_connector_hdmi_init_bpc_10
[13:57:26] [PASSED] drm_test_connector_hdmi_init_bpc_12
[13:57:26] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[13:57:26] [PASSED] drm_test_connector_hdmi_init_bpc_null
[13:57:26] [PASSED] drm_test_connector_hdmi_init_formats_empty
[13:57:26] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[13:57:26] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[13:57:26] [PASSED] supported_formats=0x9 yuv420_allowed=1
[13:57:26] [PASSED] supported_formats=0x9 yuv420_allowed=0
[13:57:26] [PASSED] supported_formats=0x5 yuv420_allowed=1
[13:57:26] [PASSED] supported_formats=0x5 yuv420_allowed=0
[13:57:26] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:57:26] [PASSED] drm_test_connector_hdmi_init_null_ddc
[13:57:26] [PASSED] drm_test_connector_hdmi_init_null_product
[13:57:26] [PASSED] drm_test_connector_hdmi_init_null_vendor
[13:57:26] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[13:57:26] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[13:57:26] [PASSED] drm_test_connector_hdmi_init_product_valid
[13:57:26] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[13:57:26] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[13:57:26] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[13:57:26] ========= drm_test_connector_hdmi_init_type_valid  =========
[13:57:26] [PASSED] HDMI-A
[13:57:26] [PASSED] HDMI-B
[13:57:26] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[13:57:26] ======== drm_test_connector_hdmi_init_type_invalid  ========
[13:57:26] [PASSED] Unknown
[13:57:26] [PASSED] VGA
[13:57:26] [PASSED] DVI-I
[13:57:26] [PASSED] DVI-D
[13:57:26] [PASSED] DVI-A
[13:57:26] [PASSED] Composite
[13:57:26] [PASSED] SVIDEO
[13:57:26] [PASSED] LVDS
[13:57:26] [PASSED] Component
[13:57:26] [PASSED] DIN
[13:57:26] [PASSED] DP
[13:57:26] [PASSED] TV
[13:57:26] [PASSED] eDP
[13:57:26] [PASSED] Virtual
[13:57:26] [PASSED] DSI
[13:57:26] [PASSED] DPI
[13:57:26] [PASSED] Writeback
[13:57:26] [PASSED] SPI
[13:57:26] [PASSED] USB
[13:57:26] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[13:57:26] ============ [PASSED] drmm_connector_hdmi_init =============
[13:57:26] ============= drmm_connector_init (3 subtests) =============
[13:57:26] [PASSED] drm_test_drmm_connector_init
[13:57:26] [PASSED] drm_test_drmm_connector_init_null_ddc
[13:57:26] ========= drm_test_drmm_connector_init_type_valid  =========
[13:57:26] [PASSED] Unknown
[13:57:26] [PASSED] VGA
[13:57:26] [PASSED] DVI-I
[13:57:26] [PASSED] DVI-D
[13:57:26] [PASSED] DVI-A
[13:57:26] [PASSED] Composite
[13:57:26] [PASSED] SVIDEO
[13:57:26] [PASSED] LVDS
[13:57:26] [PASSED] Component
[13:57:26] [PASSED] DIN
[13:57:26] [PASSED] DP
[13:57:26] [PASSED] HDMI-A
[13:57:26] [PASSED] HDMI-B
[13:57:26] [PASSED] TV
[13:57:26] [PASSED] eDP
[13:57:26] [PASSED] Virtual
[13:57:26] [PASSED] DSI
[13:57:26] [PASSED] DPI
[13:57:26] [PASSED] Writeback
[13:57:26] [PASSED] SPI
[13:57:26] [PASSED] USB
[13:57:26] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[13:57:26] =============== [PASSED] drmm_connector_init ===============
[13:57:26] ========= drm_connector_dynamic_init (6 subtests) ==========
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_init
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_init_properties
[13:57:26] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[13:57:26] [PASSED] Unknown
[13:57:26] [PASSED] VGA
[13:57:26] [PASSED] DVI-I
[13:57:26] [PASSED] DVI-D
[13:57:26] [PASSED] DVI-A
[13:57:26] [PASSED] Composite
[13:57:26] [PASSED] SVIDEO
[13:57:26] [PASSED] LVDS
[13:57:26] [PASSED] Component
[13:57:26] [PASSED] DIN
[13:57:26] [PASSED] DP
[13:57:26] [PASSED] HDMI-A
[13:57:26] [PASSED] HDMI-B
[13:57:26] [PASSED] TV
[13:57:26] [PASSED] eDP
[13:57:26] [PASSED] Virtual
[13:57:26] [PASSED] DSI
[13:57:26] [PASSED] DPI
[13:57:26] [PASSED] Writeback
[13:57:26] [PASSED] SPI
[13:57:26] [PASSED] USB
[13:57:26] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[13:57:26] ======== drm_test_drm_connector_dynamic_init_name  =========
[13:57:26] [PASSED] Unknown
[13:57:26] [PASSED] VGA
[13:57:26] [PASSED] DVI-I
[13:57:26] [PASSED] DVI-D
[13:57:26] [PASSED] DVI-A
[13:57:26] [PASSED] Composite
[13:57:26] [PASSED] SVIDEO
[13:57:26] [PASSED] LVDS
[13:57:26] [PASSED] Component
[13:57:26] [PASSED] DIN
[13:57:26] [PASSED] DP
[13:57:26] [PASSED] HDMI-A
[13:57:26] [PASSED] HDMI-B
[13:57:26] [PASSED] TV
[13:57:26] [PASSED] eDP
[13:57:26] [PASSED] Virtual
[13:57:26] [PASSED] DSI
[13:57:26] [PASSED] DPI
[13:57:26] [PASSED] Writeback
[13:57:26] [PASSED] SPI
[13:57:26] [PASSED] USB
[13:57:26] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[13:57:26] =========== [PASSED] drm_connector_dynamic_init ============
[13:57:26] ==== drm_connector_dynamic_register_early (4 subtests) =====
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[13:57:26] ====== [PASSED] drm_connector_dynamic_register_early =======
[13:57:26] ======= drm_connector_dynamic_register (7 subtests) ========
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[13:57:26] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[13:57:26] ========= [PASSED] drm_connector_dynamic_register ==========
[13:57:26] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[13:57:26] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[13:57:26] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[13:57:26] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[13:57:26] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[13:57:26] ========== drm_test_get_tv_mode_from_name_valid  ===========
[13:57:26] [PASSED] NTSC
[13:57:26] [PASSED] NTSC-443
[13:57:26] [PASSED] NTSC-J
[13:57:26] [PASSED] PAL
[13:57:26] [PASSED] PAL-M
[13:57:26] [PASSED] PAL-N
[13:57:26] [PASSED] SECAM
[13:57:26] [PASSED] Mono
[13:57:26] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[13:57:26] [PASSED] drm_test_get_tv_mode_from_name_truncated
[13:57:26] ============ [PASSED] drm_get_tv_mode_from_name ============
[13:57:26] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[13:57:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[13:57:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[13:57:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[13:57:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[13:57:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[13:57:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[13:57:26] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[13:57:26] [PASSED] VIC 96
[13:57:26] [PASSED] VIC 97
[13:57:26] [PASSED] VIC 101
[13:57:26] [PASSED] VIC 102
[13:57:26] [PASSED] VIC 106
[13:57:26] [PASSED] VIC 107
[13:57:26] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[13:57:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[13:57:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[13:57:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[13:57:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[13:57:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[13:57:26] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[13:57:26] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[13:57:26] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[13:57:26] [PASSED] Automatic
[13:57:26] [PASSED] Full
[13:57:26] [PASSED] Limited 16:235
[13:57:26] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[13:57:26] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[13:57:26] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[13:57:26] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[13:57:26] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[13:57:26] [PASSED] RGB
[13:57:26] [PASSED] YUV 4:2:0
[13:57:26] [PASSED] YUV 4:2:2
[13:57:26] [PASSED] YUV 4:4:4
[13:57:26] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[13:57:26] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[13:57:26] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[13:57:26] ============= drm_damage_helper (21 subtests) ==============
[13:57:26] [PASSED] drm_test_damage_iter_no_damage
[13:57:26] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[13:57:26] [PASSED] drm_test_damage_iter_no_damage_src_moved
[13:57:26] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[13:57:26] [PASSED] drm_test_damage_iter_no_damage_not_visible
[13:57:26] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[13:57:26] [PASSED] drm_test_damage_iter_no_damage_no_fb
[13:57:26] [PASSED] drm_test_damage_iter_simple_damage
[13:57:26] [PASSED] drm_test_damage_iter_single_damage
[13:57:26] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[13:57:26] [PASSED] drm_test_damage_iter_single_damage_outside_src
[13:57:26] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[13:57:26] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[13:57:26] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[13:57:26] [PASSED] drm_test_damage_iter_single_damage_src_moved
[13:57:26] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[13:57:26] [PASSED] drm_test_damage_iter_damage
[13:57:26] [PASSED] drm_test_damage_iter_damage_one_intersect
[13:57:26] [PASSED] drm_test_damage_iter_damage_one_outside
[13:57:26] [PASSED] drm_test_damage_iter_damage_src_moved
[13:57:26] [PASSED] drm_test_damage_iter_damage_not_visible
[13:57:26] ================ [PASSED] drm_damage_helper ================
[13:57:26] ============== drm_dp_mst_helper (3 subtests) ==============
[13:57:26] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[13:57:26] [PASSED] Clock 154000 BPP 30 DSC disabled
[13:57:26] [PASSED] Clock 234000 BPP 30 DSC disabled
[13:57:26] [PASSED] Clock 297000 BPP 24 DSC disabled
[13:57:26] [PASSED] Clock 332880 BPP 24 DSC enabled
[13:57:26] [PASSED] Clock 324540 BPP 24 DSC enabled
[13:57:26] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[13:57:26] ============== drm_test_dp_mst_calc_pbn_div  ===============
[13:57:26] [PASSED] Link rate 2000000 lane count 4
[13:57:26] [PASSED] Link rate 2000000 lane count 2
[13:57:26] [PASSED] Link rate 2000000 lane count 1
[13:57:26] [PASSED] Link rate 1350000 lane count 4
[13:57:26] [PASSED] Link rate 1350000 lane count 2
[13:57:26] [PASSED] Link rate 1350000 lane count 1
[13:57:26] [PASSED] Link rate 1000000 lane count 4
[13:57:26] [PASSED] Link rate 1000000 lane count 2
[13:57:26] [PASSED] Link rate 1000000 lane count 1
[13:57:26] [PASSED] Link rate 810000 lane count 4
[13:57:26] [PASSED] Link rate 810000 lane count 2
[13:57:26] [PASSED] Link rate 810000 lane count 1
[13:57:26] [PASSED] Link rate 540000 lane count 4
[13:57:26] [PASSED] Link rate 540000 lane count 2
[13:57:26] [PASSED] Link rate 540000 lane count 1
[13:57:26] [PASSED] Link rate 270000 lane count 4
[13:57:26] [PASSED] Link rate 270000 lane count 2
[13:57:26] [PASSED] Link rate 270000 lane count 1
[13:57:26] [PASSED] Link rate 162000 lane count 4
[13:57:26] [PASSED] Link rate 162000 lane count 2
[13:57:26] [PASSED] Link rate 162000 lane count 1
[13:57:26] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[13:57:26] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[13:57:26] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[13:57:26] [PASSED] DP_POWER_UP_PHY with port number
[13:57:26] [PASSED] DP_POWER_DOWN_PHY with port number
[13:57:26] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[13:57:26] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[13:57:26] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[13:57:26] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[13:57:26] [PASSED] DP_QUERY_PAYLOAD with port number
[13:57:26] [PASSED] DP_QUERY_PAYLOAD with VCPI
[13:57:26] [PASSED] DP_REMOTE_DPCD_READ with port number
[13:57:26] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[13:57:26] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[13:57:26] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[13:57:26] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[13:57:26] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[13:57:26] [PASSED] DP_REMOTE_I2C_READ with port number
[13:57:26] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[13:57:26] [PASSED] DP_REMOTE_I2C_READ with transactions array
[13:57:26] [PASSED] DP_REMOTE_I2C_WRITE with port number
[13:57:26] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[13:57:26] [PASSED] DP_REMOTE_I2C_WRITE with data array
[13:57:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[13:57:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[13:57:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[13:57:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[13:57:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[13:57:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[13:57:26] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[13:57:26] ================ [PASSED] drm_dp_mst_helper ================
[13:57:26] ================== drm_exec (7 subtests) ===================
[13:57:26] [PASSED] sanitycheck
[13:57:26] [PASSED] test_lock
[13:57:26] [PASSED] test_lock_unlock
[13:57:26] [PASSED] test_duplicates
[13:57:26] [PASSED] test_prepare
[13:57:26] [PASSED] test_prepare_array
[13:57:26] [PASSED] test_multiple_loops
[13:57:26] ==================== [PASSED] drm_exec =====================
[13:57:26] =========== drm_format_helper_test (17 subtests) ===========
[13:57:26] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[13:57:26] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[13:57:26] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[13:57:26] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[13:57:26] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[13:57:26] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[13:57:26] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[13:57:26] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[13:57:26] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[13:57:26] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[13:57:26] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[13:57:26] ============== drm_test_fb_xrgb8888_to_mono  ===============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[13:57:26] ==================== drm_test_fb_swab  =====================
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ================ [PASSED] drm_test_fb_swab =================
[13:57:26] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[13:57:26] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[13:57:26] [PASSED] single_pixel_source_buffer
[13:57:26] [PASSED] single_pixel_clip_rectangle
[13:57:26] [PASSED] well_known_colors
[13:57:26] [PASSED] destination_pitch
[13:57:26] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[13:57:26] ================= drm_test_fb_clip_offset  =================
[13:57:26] [PASSED] pass through
[13:57:26] [PASSED] horizontal offset
[13:57:26] [PASSED] vertical offset
[13:57:26] [PASSED] horizontal and vertical offset
[13:57:26] [PASSED] horizontal offset (custom pitch)
[13:57:26] [PASSED] vertical offset (custom pitch)
[13:57:26] [PASSED] horizontal and vertical offset (custom pitch)
[13:57:26] ============= [PASSED] drm_test_fb_clip_offset =============
[13:57:26] =================== drm_test_fb_memcpy  ====================
[13:57:26] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[13:57:26] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[13:57:26] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[13:57:26] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[13:57:26] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[13:57:26] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[13:57:26] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[13:57:26] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[13:57:26] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[13:57:26] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[13:57:26] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[13:57:26] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[13:57:26] =============== [PASSED] drm_test_fb_memcpy ================
[13:57:26] ============= [PASSED] drm_format_helper_test ==============
[13:57:26] ================= drm_format (18 subtests) =================
[13:57:26] [PASSED] drm_test_format_block_width_invalid
[13:57:26] [PASSED] drm_test_format_block_width_one_plane
[13:57:26] [PASSED] drm_test_format_block_width_two_plane
[13:57:26] [PASSED] drm_test_format_block_width_three_plane
[13:57:26] [PASSED] drm_test_format_block_width_tiled
[13:57:26] [PASSED] drm_test_format_block_height_invalid
[13:57:26] [PASSED] drm_test_format_block_height_one_plane
[13:57:26] [PASSED] drm_test_format_block_height_two_plane
[13:57:26] [PASSED] drm_test_format_block_height_three_plane
[13:57:26] [PASSED] drm_test_format_block_height_tiled
[13:57:26] [PASSED] drm_test_format_min_pitch_invalid
[13:57:26] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[13:57:26] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[13:57:26] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[13:57:26] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[13:57:26] [PASSED] drm_test_format_min_pitch_two_plane
[13:57:26] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[13:57:26] [PASSED] drm_test_format_min_pitch_tiled
[13:57:26] =================== [PASSED] drm_format ====================
[13:57:26] ============== drm_framebuffer (10 subtests) ===============
[13:57:26] ========== drm_test_framebuffer_check_src_coords  ==========
[13:57:26] [PASSED] Success: source fits into fb
[13:57:26] [PASSED] Fail: overflowing fb with x-axis coordinate
[13:57:26] [PASSED] Fail: overflowing fb with y-axis coordinate
[13:57:26] [PASSED] Fail: overflowing fb with source width
[13:57:26] [PASSED] Fail: overflowing fb with source height
[13:57:26] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[13:57:26] [PASSED] drm_test_framebuffer_cleanup
[13:57:26] =============== drm_test_framebuffer_create  ===============
[13:57:26] [PASSED] ABGR8888 normal sizes
[13:57:26] [PASSED] ABGR8888 max sizes
[13:57:26] [PASSED] ABGR8888 pitch greater than min required
[13:57:26] [PASSED] ABGR8888 pitch less than min required
[13:57:26] [PASSED] ABGR8888 Invalid width
[13:57:26] [PASSED] ABGR8888 Invalid buffer handle
[13:57:26] [PASSED] No pixel format
[13:57:26] [PASSED] ABGR8888 Width 0
[13:57:26] [PASSED] ABGR8888 Height 0
[13:57:26] [PASSED] ABGR8888 Out of bound height * pitch combination
[13:57:26] [PASSED] ABGR8888 Large buffer offset
[13:57:26] [PASSED] ABGR8888 Buffer offset for inexistent plane
[13:57:26] [PASSED] ABGR8888 Invalid flag
[13:57:26] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[13:57:26] [PASSED] ABGR8888 Valid buffer modifier
[13:57:26] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[13:57:26] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[13:57:26] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[13:57:26] [PASSED] NV12 Normal sizes
[13:57:26] [PASSED] NV12 Max sizes
[13:57:26] [PASSED] NV12 Invalid pitch
[13:57:26] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[13:57:26] [PASSED] NV12 different  modifier per-plane
[13:57:26] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[13:57:26] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[13:57:26] [PASSED] NV12 Modifier for inexistent plane
[13:57:26] [PASSED] NV12 Handle for inexistent plane
[13:57:26] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[13:57:26] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[13:57:26] [PASSED] YVU420 Normal sizes
[13:57:26] [PASSED] YVU420 Max sizes
[13:57:26] [PASSED] YVU420 Invalid pitch
[13:57:26] [PASSED] YVU420 Different pitches
[13:57:26] [PASSED] YVU420 Different buffer offsets/pitches
[13:57:26] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[13:57:26] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[13:57:26] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[13:57:26] [PASSED] YVU420 Valid modifier
[13:57:26] [PASSED] YVU420 Different modifiers per plane
[13:57:26] [PASSED] YVU420 Modifier for inexistent plane
[13:57:26] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[13:57:26] [PASSED] X0L2 Normal sizes
[13:57:26] [PASSED] X0L2 Max sizes
[13:57:26] [PASSED] X0L2 Invalid pitch
[13:57:26] [PASSED] X0L2 Pitch greater than minimum required
[13:57:26] [PASSED] X0L2 Handle for inexistent plane
[13:57:26] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[13:57:26] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[13:57:26] [PASSED] X0L2 Valid modifier
[13:57:26] [PASSED] X0L2 Modifier for inexistent plane
[13:57:26] =========== [PASSED] drm_test_framebuffer_create ===========
[13:57:26] [PASSED] drm_test_framebuffer_free
[13:57:26] [PASSED] drm_test_framebuffer_init
[13:57:26] [PASSED] drm_test_framebuffer_init_bad_format
[13:57:26] [PASSED] drm_test_framebuffer_init_dev_mismatch
[13:57:26] [PASSED] drm_test_framebuffer_lookup
[13:57:26] [PASSED] drm_test_framebuffer_lookup_inexistent
[13:57:26] [PASSED] drm_test_framebuffer_modifiers_not_supported
[13:57:26] ================= [PASSED] drm_framebuffer =================
[13:57:26] ================ drm_gem_shmem (8 subtests) ================
[13:57:26] [PASSED] drm_gem_shmem_test_obj_create
[13:57:26] [PASSED] drm_gem_shmem_test_obj_create_private
[13:57:26] [PASSED] drm_gem_shmem_test_pin_pages
[13:57:26] [PASSED] drm_gem_shmem_test_vmap
[13:57:26] [PASSED] drm_gem_shmem_test_get_sg_table
[13:57:26] [PASSED] drm_gem_shmem_test_get_pages_sgt
[13:57:26] [PASSED] drm_gem_shmem_test_madvise
[13:57:26] [PASSED] drm_gem_shmem_test_purge
[13:57:26] ================== [PASSED] drm_gem_shmem ==================
[13:57:26] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[13:57:26] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[13:57:26] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[13:57:26] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[13:57:26] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[13:57:26] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[13:57:26] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[13:57:26] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[13:57:26] [PASSED] Automatic
[13:57:26] [PASSED] Full
[13:57:26] [PASSED] Limited 16:235
[13:57:26] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[13:57:26] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[13:57:26] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[13:57:26] [PASSED] drm_test_check_disable_connector
[13:57:26] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[13:57:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[13:57:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[13:57:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[13:57:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[13:57:26] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[13:57:26] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[13:57:26] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[13:57:26] [PASSED] drm_test_check_output_bpc_dvi
[13:57:26] [PASSED] drm_test_check_output_bpc_format_vic_1
[13:57:26] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[13:57:26] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[13:57:26] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[13:57:26] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[13:57:26] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[13:57:26] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[13:57:26] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[13:57:26] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[13:57:26] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[13:57:26] [PASSED] drm_test_check_broadcast_rgb_value
[13:57:26] [PASSED] drm_test_check_bpc_8_value
[13:57:26] [PASSED] drm_test_check_bpc_10_value
[13:57:26] [PASSED] drm_test_check_bpc_12_value
[13:57:26] [PASSED] drm_test_check_format_value
[13:57:26] [PASSED] drm_test_check_tmds_char_value
[13:57:26] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[13:57:26] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[13:57:26] [PASSED] drm_test_check_mode_valid
[13:57:26] [PASSED] drm_test_check_mode_valid_reject
[13:57:26] [PASSED] drm_test_check_mode_valid_reject_rate
[13:57:26] [PASSED] drm_test_check_mode_valid_reject_max_clock
[13:57:26] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[13:57:26] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[13:57:26] [PASSED] drm_test_check_infoframes
[13:57:26] [PASSED] drm_test_check_reject_avi_infoframe
[13:57:26] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[13:57:26] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[13:57:26] [PASSED] drm_test_check_reject_audio_infoframe
[13:57:26] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[13:57:26] ================= drm_managed (2 subtests) =================
[13:57:26] [PASSED] drm_test_managed_release_action
[13:57:26] [PASSED] drm_test_managed_run_action
[13:57:26] =================== [PASSED] drm_managed ===================
[13:57:26] =================== drm_mm (6 subtests) ====================
[13:57:26] [PASSED] drm_test_mm_init
[13:57:26] [PASSED] drm_test_mm_debug
[13:57:26] [PASSED] drm_test_mm_align32
[13:57:26] [PASSED] drm_test_mm_align64
[13:57:26] [PASSED] drm_test_mm_lowest
[13:57:26] [PASSED] drm_test_mm_highest
[13:57:26] ===================== [PASSED] drm_mm ======================
[13:57:26] ============= drm_modes_analog_tv (5 subtests) =============
[13:57:26] [PASSED] drm_test_modes_analog_tv_mono_576i
[13:57:26] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[13:57:26] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[13:57:26] [PASSED] drm_test_modes_analog_tv_pal_576i
[13:57:26] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[13:57:26] =============== [PASSED] drm_modes_analog_tv ===============
[13:57:26] ============== drm_plane_helper (2 subtests) ===============
[13:57:26] =============== drm_test_check_plane_state  ================
[13:57:26] [PASSED] clipping_simple
[13:57:26] [PASSED] clipping_rotate_reflect
[13:57:26] [PASSED] positioning_simple
[13:57:26] [PASSED] upscaling
[13:57:26] [PASSED] downscaling
[13:57:26] [PASSED] rounding1
[13:57:26] [PASSED] rounding2
[13:57:26] [PASSED] rounding3
[13:57:26] [PASSED] rounding4
[13:57:26] =========== [PASSED] drm_test_check_plane_state ============
[13:57:26] =========== drm_test_check_invalid_plane_state  ============
[13:57:26] [PASSED] positioning_invalid
[13:57:26] [PASSED] upscaling_invalid
[13:57:26] [PASSED] downscaling_invalid
[13:57:26] ======= [PASSED] drm_test_check_invalid_plane_state ========
[13:57:26] ================ [PASSED] drm_plane_helper =================
[13:57:26] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[13:57:26] ====== drm_test_connector_helper_tv_get_modes_check  =======
[13:57:26] [PASSED] None
[13:57:26] [PASSED] PAL
[13:57:26] [PASSED] NTSC
[13:57:26] [PASSED] Both, NTSC Default
[13:57:26] [PASSED] Both, PAL Default
[13:57:26] [PASSED] Both, NTSC Default, with PAL on command-line
[13:57:26] [PASSED] Both, PAL Default, with NTSC on command-line
[13:57:26] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[13:57:26] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[13:57:26] ================== drm_rect (9 subtests) ===================
[13:57:26] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[13:57:26] [PASSED] drm_test_rect_clip_scaled_not_clipped
[13:57:26] [PASSED] drm_test_rect_clip_scaled_clipped
[13:57:26] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[13:57:26] ================= drm_test_rect_intersect  =================
[13:57:26] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[13:57:26] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[13:57:26] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[13:57:26] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[13:57:26] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[13:57:26] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[13:57:26] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[13:57:26] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[13:57:26] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[13:57:26] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[13:57:26] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[13:57:26] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[13:57:26] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[13:57:26] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[13:57:26] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[13:57:26] ============= [PASSED] drm_test_rect_intersect =============
[13:57:26] ================ drm_test_rect_calc_hscale  ================
[13:57:26] [PASSED] normal use
[13:57:26] [PASSED] out of max range
[13:57:26] [PASSED] out of min range
[13:57:26] [PASSED] zero dst
[13:57:26] [PASSED] negative src
[13:57:26] [PASSED] negative dst
[13:57:26] ============ [PASSED] drm_test_rect_calc_hscale ============
[13:57:26] ================ drm_test_rect_calc_vscale  ================
[13:57:26] [PASSED] normal use
[13:57:26] [PASSED] out of max range
[13:57:26] [PASSED] out of min range
[13:57:26] [PASSED] zero dst
[13:57:26] [PASSED] negative src
[13:57:26] [PASSED] negative dst
[13:57:26] ============ [PASSED] drm_test_rect_calc_vscale ============
[13:57:26] ================== drm_test_rect_rotate  ===================
[13:57:26] [PASSED] reflect-x
[13:57:26] [PASSED] reflect-y
[13:57:26] [PASSED] rotate-0
[13:57:26] [PASSED] rotate-90
[13:57:26] [PASSED] rotate-180
[13:57:26] [PASSED] rotate-270
[13:57:26] ============== [PASSED] drm_test_rect_rotate ===============
[13:57:26] ================ drm_test_rect_rotate_inv  =================
[13:57:26] [PASSED] reflect-x
[13:57:26] [PASSED] reflect-y
[13:57:26] [PASSED] rotate-0
[13:57:26] [PASSED] rotate-90
[13:57:26] [PASSED] rotate-180
[13:57:26] [PASSED] rotate-270
[13:57:26] ============ [PASSED] drm_test_rect_rotate_inv =============
[13:57:26] ==================== [PASSED] drm_rect =====================
[13:57:26] ============ drm_sysfb_modeset_test (1 subtest) ============
[13:57:26] ============ drm_test_sysfb_build_fourcc_list  =============
[13:57:26] [PASSED] no native formats
[13:57:26] [PASSED] XRGB8888 as native format
[13:57:26] [PASSED] remove duplicates
[13:57:26] [PASSED] convert alpha formats
[13:57:26] [PASSED] random formats
[13:57:26] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[13:57:26] ============= [PASSED] drm_sysfb_modeset_test ==============
[13:57:26] ================== drm_fixp (2 subtests) ===================
[13:57:26] [PASSED] drm_test_int2fixp
[13:57:26] [PASSED] drm_test_sm2fixp
[13:57:26] ==================== [PASSED] drm_fixp =====================
[13:57:26] ============================================================
[13:57:26] Testing complete. Ran 621 tests: passed: 621
[13:57:26] Elapsed time: 25.746s total, 1.713s configuring, 23.868s building, 0.119s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[13:57:26] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:57:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:57:38] Starting KUnit Kernel (1/1)...
[13:57:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:57:38] ================= ttm_device (5 subtests) ==================
[13:57:38] [PASSED] ttm_device_init_basic
[13:57:38] [PASSED] ttm_device_init_multiple
[13:57:38] [PASSED] ttm_device_fini_basic
[13:57:38] [PASSED] ttm_device_init_no_vma_man
[13:57:38] ================== ttm_device_init_pools  ==================
[13:57:38] [PASSED] No DMA allocations, no DMA32 required
[13:57:38] [PASSED] DMA allocations, DMA32 required
[13:57:38] [PASSED] No DMA allocations, DMA32 required
[13:57:38] [PASSED] DMA allocations, no DMA32 required
[13:57:38] ============== [PASSED] ttm_device_init_pools ==============
[13:57:38] =================== [PASSED] ttm_device ====================
[13:57:38] ================== ttm_pool (8 subtests) ===================
[13:57:38] ================== ttm_pool_alloc_basic  ===================
[13:57:38] [PASSED] One page
[13:57:38] [PASSED] More than one page
[13:57:38] [PASSED] Above the allocation limit
[13:57:38] [PASSED] One page, with coherent DMA mappings enabled
[13:57:38] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:57:38] ============== [PASSED] ttm_pool_alloc_basic ===============
[13:57:38] ============== ttm_pool_alloc_basic_dma_addr  ==============
[13:57:38] [PASSED] One page
[13:57:38] [PASSED] More than one page
[13:57:38] [PASSED] Above the allocation limit
[13:57:38] [PASSED] One page, with coherent DMA mappings enabled
[13:57:38] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:57:38] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[13:57:38] [PASSED] ttm_pool_alloc_order_caching_match
[13:57:38] [PASSED] ttm_pool_alloc_caching_mismatch
[13:57:38] [PASSED] ttm_pool_alloc_order_mismatch
[13:57:38] [PASSED] ttm_pool_free_dma_alloc
[13:57:38] [PASSED] ttm_pool_free_no_dma_alloc
[13:57:38] [PASSED] ttm_pool_fini_basic
[13:57:38] ==================== [PASSED] ttm_pool =====================
[13:57:38] ================ ttm_resource (8 subtests) =================
[13:57:38] ================= ttm_resource_init_basic  =================
[13:57:38] [PASSED] Init resource in TTM_PL_SYSTEM
[13:57:38] [PASSED] Init resource in TTM_PL_VRAM
[13:57:38] [PASSED] Init resource in a private placement
[13:57:38] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[13:57:38] ============= [PASSED] ttm_resource_init_basic =============
[13:57:38] [PASSED] ttm_resource_init_pinned
[13:57:38] [PASSED] ttm_resource_fini_basic
[13:57:38] [PASSED] ttm_resource_manager_init_basic
[13:57:38] [PASSED] ttm_resource_manager_usage_basic
[13:57:38] [PASSED] ttm_resource_manager_set_used_basic
[13:57:38] [PASSED] ttm_sys_man_alloc_basic
[13:57:38] [PASSED] ttm_sys_man_free_basic
[13:57:38] ================== [PASSED] ttm_resource ===================
[13:57:38] =================== ttm_tt (15 subtests) ===================
[13:57:38] ==================== ttm_tt_init_basic  ====================
[13:57:38] [PASSED] Page-aligned size
[13:57:38] [PASSED] Extra pages requested
[13:57:38] ================ [PASSED] ttm_tt_init_basic ================
[13:57:38] [PASSED] ttm_tt_init_misaligned
[13:57:38] [PASSED] ttm_tt_fini_basic
[13:57:38] [PASSED] ttm_tt_fini_sg
[13:57:38] [PASSED] ttm_tt_fini_shmem
[13:57:38] [PASSED] ttm_tt_create_basic
[13:57:38] [PASSED] ttm_tt_create_invalid_bo_type
[13:57:38] [PASSED] ttm_tt_create_ttm_exists
[13:57:38] [PASSED] ttm_tt_create_failed
[13:57:38] [PASSED] ttm_tt_destroy_basic
[13:57:38] [PASSED] ttm_tt_populate_null_ttm
[13:57:38] [PASSED] ttm_tt_populate_populated_ttm
[13:57:38] [PASSED] ttm_tt_unpopulate_basic
[13:57:38] [PASSED] ttm_tt_unpopulate_empty_ttm
[13:57:38] [PASSED] ttm_tt_swapin_basic
[13:57:38] ===================== [PASSED] ttm_tt ======================
[13:57:38] =================== ttm_bo (14 subtests) ===================
[13:57:38] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[13:57:38] [PASSED] Cannot be interrupted and sleeps
[13:57:38] [PASSED] Cannot be interrupted, locks straight away
[13:57:38] [PASSED] Can be interrupted, sleeps
[13:57:38] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[13:57:38] [PASSED] ttm_bo_reserve_locked_no_sleep
[13:57:38] [PASSED] ttm_bo_reserve_no_wait_ticket
[13:57:38] [PASSED] ttm_bo_reserve_double_resv
[13:57:38] [PASSED] ttm_bo_reserve_interrupted
[13:57:38] [PASSED] ttm_bo_reserve_deadlock
[13:57:38] [PASSED] ttm_bo_unreserve_basic
[13:57:38] [PASSED] ttm_bo_unreserve_pinned
[13:57:38] [PASSED] ttm_bo_unreserve_bulk
[13:57:38] [PASSED] ttm_bo_fini_basic
[13:57:38] [PASSED] ttm_bo_fini_shared_resv
[13:57:38] [PASSED] ttm_bo_pin_basic
[13:57:38] [PASSED] ttm_bo_pin_unpin_resource
[13:57:38] [PASSED] ttm_bo_multiple_pin_one_unpin
[13:57:38] ===================== [PASSED] ttm_bo ======================
[13:57:38] ============== ttm_bo_validate (22 subtests) ===============
[13:57:38] ============== ttm_bo_init_reserved_sys_man  ===============
[13:57:38] [PASSED] Buffer object for userspace
[13:57:38] [PASSED] Kernel buffer object
[13:57:38] [PASSED] Shared buffer object
[13:57:38] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[13:57:38] ============== ttm_bo_init_reserved_mock_man  ==============
[13:57:38] [PASSED] Buffer object for userspace
[13:57:38] [PASSED] Kernel buffer object
[13:57:38] [PASSED] Shared buffer object
[13:57:38] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[13:57:38] [PASSED] ttm_bo_init_reserved_resv
[13:57:38] ================== ttm_bo_validate_basic  ==================
[13:57:38] [PASSED] Buffer object for userspace
[13:57:38] [PASSED] Kernel buffer object
[13:57:38] [PASSED] Shared buffer object
[13:57:38] ============== [PASSED] ttm_bo_validate_basic ==============
[13:57:38] [PASSED] ttm_bo_validate_invalid_placement
[13:57:38] ============= ttm_bo_validate_same_placement  ==============
[13:57:38] [PASSED] System manager
[13:57:38] [PASSED] VRAM manager
[13:57:38] ========= [PASSED] ttm_bo_validate_same_placement ==========
[13:57:38] [PASSED] ttm_bo_validate_failed_alloc
[13:57:38] [PASSED] ttm_bo_validate_pinned
[13:57:38] [PASSED] ttm_bo_validate_busy_placement
[13:57:38] ================ ttm_bo_validate_multihop  =================
[13:57:38] [PASSED] Buffer object for userspace
[13:57:38] [PASSED] Kernel buffer object
[13:57:38] [PASSED] Shared buffer object
[13:57:38] ============ [PASSED] ttm_bo_validate_multihop =============
[13:57:38] ========== ttm_bo_validate_no_placement_signaled  ==========
[13:57:38] [PASSED] Buffer object in system domain, no page vector
[13:57:38] [PASSED] Buffer object in system domain with an existing page vector
[13:57:38] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[13:57:38] ======== ttm_bo_validate_no_placement_not_signaled  ========
[13:57:38] [PASSED] Buffer object for userspace
[13:57:38] [PASSED] Kernel buffer object
[13:57:38] [PASSED] Shared buffer object
[13:57:38] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[13:57:38] [PASSED] ttm_bo_validate_move_fence_signaled
[13:57:38] ========= ttm_bo_validate_move_fence_not_signaled  =========
[13:57:38] [PASSED] Waits for GPU
[13:57:38] [PASSED] Tries to lock straight away
[13:57:38] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[13:57:38] [PASSED] ttm_bo_validate_swapout
[13:57:38] [PASSED] ttm_bo_validate_happy_evict
[13:57:38] [PASSED] ttm_bo_validate_all_pinned_evict
[13:57:38] [PASSED] ttm_bo_validate_allowed_only_evict
[13:57:38] [PASSED] ttm_bo_validate_deleted_evict
[13:57:38] [PASSED] ttm_bo_validate_busy_domain_evict
[13:57:38] [PASSED] ttm_bo_validate_evict_gutting
[13:57:38] [PASSED] ttm_bo_validate_recrusive_evict
[13:57:38] ================= [PASSED] ttm_bo_validate =================
[13:57:38] ============================================================
[13:57:38] Testing complete. Ran 102 tests: passed: 102
[13:57:38] Elapsed time: 11.534s total, 1.723s configuring, 9.596s building, 0.181s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for GuC paging engine support (rev2)

[Patchwork]

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== Series Details ==

Series: GuC paging engine support (rev2)
URL   : https://patchwork.freedesktop.org/series/166960/
State : success

== Summary ==

CI Bug Log - changes from xe-5116-127c8434a6a018110189cdb654719a9844702ff7_BAT -> xe-pw-166960v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5116-127c8434a6a018110189cdb654719a9844702ff7 -> xe-pw-166960v2

  IGT_8936: 98b65acc4f6edf68cd52b30f27b83049c4c5c83b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5116-127c8434a6a018110189cdb654719a9844702ff7: 127c8434a6a018110189cdb654719a9844702ff7
  xe-pw-166960v2: 166960v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/index.html

[-- Attachment #2: Type: text/html, Size: 1494 bytes --]

✗ Xe.CI.FULL: failure for GuC paging engine support (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 26405 bytes --]

== Series Details ==

Series: GuC paging engine support (rev2)
URL   : https://patchwork.freedesktop.org/series/166960/
State : failure

== Summary ==

CI Bug Log - changes from xe-5116-127c8434a6a018110189cdb654719a9844702ff7_FULL -> xe-pw-166960v2_FULL
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with xe-pw-166960v2_FULL need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-166960v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-166960v2_FULL:

### IGT changes ###

#### Warnings ####

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][1] ([Intel XE#2311]) -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc.html

  
Known issues
------------

  Here are the changes found in xe-pw-166960v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#1124]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_bw@linear-tiling-1-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#367])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2887]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2252]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-0:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#6969]) +10 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-b-plane-0.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-plane-2:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#6969] / [Intel XE#7006]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-plane-2.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][10] ([Intel XE#8151])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#4422] / [Intel XE#7442])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#4141])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2311]) +9 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#7061]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2313]) +6 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][16] -> [SKIP][17] ([Intel XE#1503])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-10/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [PASS][18] -> [SKIP][19] ([Intel XE#7922]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-1/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-10/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#6901])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2486])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7130]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_plane@pixel-format-4-tiled-modifier@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7283])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#1489])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-pr-basic:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_psr@fbc-pr-basic.html

  * igt@kms_sharpness_filter@filter-tap:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#6503])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@kms_sharpness_filter@filter-tap.html

  * igt@xe_eudebug@multiple-sessions:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7636]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@xe_eudebug@multiple-sessions.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@once-multi-queue-invalid-fault:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#7136])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@xe_exec_fault_mode@once-multi-queue-invalid-fault.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-priority:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#6874]) +3 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@xe_exec_multi_queue@few-execs-preempt-mode-priority.html

  * igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#7866])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@xe_exec_reset@cm-multi-queue-cat-error-on-secondary.html

  * igt@xe_exec_system_allocator@once-new-bo-map-nomemset:
    - shard-lnl:          NOTRUN -> [ABORT][32] ([Intel XE#8007])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-lnl-3/igt@xe_exec_system_allocator@once-new-bo-map-nomemset.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#7138]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr.html

  * igt@xe_live_ktest@xe_bo:
    - shard-bmg:          [PASS][34] -> [DMESG-WARN][35] ([Intel XE#7774]) +1 other test dmesg-warn
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-7/igt@xe_live_ktest@xe_bo.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-2/igt@xe_live_ktest@xe_bo.html

  * igt@xe_multigpu_svm@mgpu-pagefault-conflict:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#6964])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-1/igt@xe_multigpu_svm@mgpu-pagefault-conflict.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a3:
    - shard-bmg:          [FAIL][37] ([Intel XE#3149] / [Intel XE#3321]) -> [PASS][38] +1 other test pass
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-4/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a3.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank@d-hdmi-a3.html

  * igt@xe_exec_system_allocator@many-64k-mmap-file-nomemset:
    - shard-bmg:          [SKIP][39] ([Intel XE#6703]) -> [PASS][40] +74 other tests pass
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@xe_exec_system_allocator@many-64k-mmap-file-nomemset.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@xe_exec_system_allocator@many-64k-mmap-file-nomemset.html

  * igt@xe_live_ktest@xe_dma_buf:
    - shard-bmg:          [FAIL][41] ([Intel XE#7736]) -> [PASS][42] +1 other test pass
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@xe_live_ktest@xe_dma_buf.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@xe_live_ktest@xe_dma_buf.html

  * igt@xe_module_load@reload-no-display:
    - shard-bmg:          [DMESG-WARN][43] -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@xe_module_load@reload-no-display.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@xe_module_load@reload-no-display.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-lnl:          [ABORT][45] ([Intel XE#8007]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-lnl-8/igt@xe_wedged@wedged-mode-toggle.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-lnl-3/igt@xe_wedged@wedged-mode-toggle.html

  
#### Warnings ####

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-bmg:          [SKIP][47] ([Intel XE#6703]) -> [SKIP][48] ([Intel XE#2327])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_big_fb@linear-32bpp-rotate-90.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs:
    - shard-bmg:          [SKIP][49] ([Intel XE#6703]) -> [SKIP][50] ([Intel XE#2887]) +3 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html

  * igt@kms_content_protection@mei-interface:
    - shard-bmg:          [SKIP][51] ([Intel XE#6703]) -> [SKIP][52] ([Intel XE#7642])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_content_protection@mei-interface.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-offscreen-64x21:
    - shard-bmg:          [SKIP][53] ([Intel XE#6703]) -> [SKIP][54] ([Intel XE#2320])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-64x21.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_cursor_crc@cursor-offscreen-64x21.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-bmg:          [SKIP][55] ([Intel XE#6703]) -> [SKIP][56] ([Intel XE#2244])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-bmg:          [SKIP][57] ([Intel XE#6703]) -> [SKIP][58] ([Intel XE#4156] / [Intel XE#7425])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_fbcon_fbt@fbc-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          [SKIP][59] ([Intel XE#6703]) -> [SKIP][60] ([Intel XE#2311]) +6 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt:
    - shard-bmg:          [SKIP][61] ([Intel XE#6703]) -> [SKIP][62] ([Intel XE#7061] / [Intel XE#7356])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
    - shard-bmg:          [SKIP][63] ([Intel XE#6703]) -> [SKIP][64] ([Intel XE#2313]) +5 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y:
    - shard-bmg:          [SKIP][65] ([Intel XE#6703]) -> [SKIP][66] ([Intel XE#7399]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][67] ([Intel XE#3544] / [Intel XE#7915] / [Intel XE#7916]) -> [SKIP][68] ([Intel XE#3544] / [Intel XE#7916])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][69] ([Intel XE#7915]) -> [SKIP][70] ([Intel XE#7916]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-7/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-2/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          [SKIP][71] ([Intel XE#6703]) -> [SKIP][72] ([Intel XE#1489]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-psr-sprite-plane-move:
    - shard-bmg:          [SKIP][73] ([Intel XE#6703]) -> [SKIP][74] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_psr@fbc-psr-sprite-plane-move.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_psr@fbc-psr-sprite-plane-move.html

  * igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor:
    - shard-bmg:          [SKIP][75] ([Intel XE#6703]) -> [SKIP][76] ([Intel XE#6503])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][77] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][78] ([Intel XE#2509] / [Intel XE#7437])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_eudebug_online@interrupt-reconnect:
    - shard-bmg:          [SKIP][79] ([Intel XE#6703]) -> [SKIP][80] ([Intel XE#7636]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@xe_eudebug_online@interrupt-reconnect.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@xe_eudebug_online@interrupt-reconnect.html

  * igt@xe_exec_fault_mode@twice-multi-queue-rebind:
    - shard-bmg:          [SKIP][81] ([Intel XE#6703]) -> [SKIP][82] ([Intel XE#7136]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@xe_exec_fault_mode@twice-multi-queue-rebind.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@xe_exec_fault_mode@twice-multi-queue-rebind.html

  * igt@xe_exec_multi_queue@two-queues-userptr:
    - shard-bmg:          [SKIP][83] ([Intel XE#6703]) -> [SKIP][84] ([Intel XE#6874]) +4 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@xe_exec_multi_queue@two-queues-userptr.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@xe_exec_multi_queue@two-queues-userptr.html

  * igt@xe_exec_threads@threads-multi-queue-userptr:
    - shard-bmg:          [SKIP][85] ([Intel XE#6703]) -> [SKIP][86] ([Intel XE#7138]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-userptr.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@xe_exec_threads@threads-multi-queue-userptr.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          [SKIP][87] ([Intel XE#6703]) -> [SKIP][88] ([Intel XE#944])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5116-127c8434a6a018110189cdb654719a9844702ff7/shard-bmg-2/igt@xe_query@multigpu-query-hwconfig.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/shard-bmg-8/igt@xe_query@multigpu-query-hwconfig.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7130
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7425
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7736]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7736
  [Intel XE#7774]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7774
  [Intel XE#7866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7866
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#7916]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7916
  [Intel XE#7922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7922
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8151
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5116-127c8434a6a018110189cdb654719a9844702ff7 -> xe-pw-166960v2

  IGT_8936: 98b65acc4f6edf68cd52b30f27b83049c4c5c83b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5116-127c8434a6a018110189cdb654719a9844702ff7: 127c8434a6a018110189cdb654719a9844702ff7
  xe-pw-166960v2: 166960v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-166960v2/index.html

[-- Attachment #2: Type: text/html, Size: 30898 bytes --]

Re: [PATCH v2 01/10] drm/xe/guc: refactor ads to use guc_class

[Daniele Ceraolo Spurio]

On 5/22/2026 5:37 AM, Matthew Auld wrote:
> Currently in the lrc init flow on the ads side, we loop through each
> generic engine class and convert that to the respective guc engine
> class. However, with some upcoming changes, it will be better to go the
> opposite way and loop through every guc engine class, and convert that
> to the generic engine class.
>
> This also reworks engine_enable_mask to operate on the guc_class, that
> way we can easily filter out the PAGING vs normal BSC, when applicable.

nit: this sentence looks like it should go after the next one, because 
here you mention PAGING directly but below you introduce the "new engine 
class".

>
> This will be needed in an upcoming patch where we have a new guc engine
> class that just matches up to the existing blitter/copy class, but needs
> to be treated as separate entity from the normal copy lrc, when setting
> up the ADS.
>
> As a bonus this also gets rid of two xe_engine_class_to_guc_class()
> users which will be helpful for the next patch.
>
> No functional changes.
>
> Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_guc_ads.c | 67 ++++++++++++++++++++++-----------
>   1 file changed, 45 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index b9bca6084a4f..ffe60d77b713 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -251,15 +251,37 @@ static size_t calculate_regset_size(struct xe_gt *gt)
>   	return count * sizeof(struct guc_mmio_reg);
>   }
>   
> -static u32 engine_enable_mask(struct xe_gt *gt, enum xe_engine_class class)
> +static inline enum xe_engine_class guc_class_to_engine_class(u16 guc_class)
> +{
> +	switch (guc_class) {
> +	case GUC_RENDER_CLASS:
> +		return XE_ENGINE_CLASS_RENDER;
> +	case GUC_VIDEO_CLASS:
> +		return XE_ENGINE_CLASS_VIDEO_DECODE;
> +	case GUC_VIDEOENHANCE_CLASS:
> +		return XE_ENGINE_CLASS_VIDEO_ENHANCE;
> +	case GUC_BLITTER_CLASS:
> +		return XE_ENGINE_CLASS_COPY;
> +	case GUC_COMPUTE_CLASS:
> +		return XE_ENGINE_CLASS_COMPUTE;
> +	case GUC_GSC_OTHER_CLASS:
> +		return XE_ENGINE_CLASS_OTHER;
> +	default:
> +		XE_WARN_ON(guc_class);
> +		return -1;
> +	}
> +}
> +
> +static u32 engine_enable_mask(struct xe_gt *gt, u16 guc_class)
>   {
>   	struct xe_hw_engine *hwe;
>   	enum xe_hw_engine_id id;
>   	u32 mask = 0;
>   
> -	for_each_hw_engine(hwe, gt, id)
> -		if (hwe->class == class)
> +	for_each_hw_engine(hwe, gt, id) {
> +		if (xe_engine_class_to_guc_class(hwe->class) == guc_class)
>   			mask |= BIT(hwe->instance);
> +	}

nit: the brackets aren't really needed here.

>   
>   	return mask;
>   }
> @@ -268,10 +290,13 @@ static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads)
>   {
>   	struct xe_gt *gt = ads_to_gt(ads);
>   	size_t total_size = 0, alloc_size, real_size;
> -	int class;
> +	u16 guc_class;
>   
> -	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
> -		if (!engine_enable_mask(gt, class))
> +	for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) {
> +		enum xe_engine_class class =
> +			guc_class_to_engine_class(guc_class);
> +
> +		if (!engine_enable_mask(gt, guc_class))
>   			continue;
>   
>   		real_size = xe_gt_lrc_size(gt, class);
> @@ -465,18 +490,18 @@ static void fill_engine_enable_masks(struct xe_gt *gt,
>   	struct xe_device *xe = gt_to_xe(gt);
>   
>   	info_map_write(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS],
> -		       engine_enable_mask(gt, XE_ENGINE_CLASS_RENDER));
> +		       engine_enable_mask(gt, GUC_RENDER_CLASS));
>   	info_map_write(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS],
> -		       engine_enable_mask(gt, XE_ENGINE_CLASS_COPY));
> +		       engine_enable_mask(gt, GUC_BLITTER_CLASS));
>   	info_map_write(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS],
> -		       engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_DECODE));
> +		       engine_enable_mask(gt, GUC_VIDEO_CLASS));
>   	info_map_write(xe, info_map,
>   		       engine_enabled_masks[GUC_VIDEOENHANCE_CLASS],
> -		       engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE));
> +		       engine_enable_mask(gt, GUC_VIDEOENHANCE_CLASS));
>   	info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS],
> -		       engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE));
> +		       engine_enable_mask(gt, GUC_COMPUTE_CLASS));
>   	info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
> -		       engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER));
> +		       engine_enable_mask(gt, GUC_GSC_OTHER_CLASS));

Would it be worth making this a loop now that we use the GuC class 
everywhere?
Something like:

for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class)
	info_map_write(xe, info_map,
		       engine_enabled_masks[guc_class],
		       engine_enable_mask(gt, guc_class));


Not a blocker.

Apart from the nits this LGTM, so:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

>   }
>   
>   /*
> @@ -491,15 +516,14 @@ static void guc_golden_lrc_init(struct xe_guc_ads *ads)
>   			offsetof(struct __guc_ads_blob, system_info));
>   	size_t alloc_size, real_size;
>   	u32 addr_ggtt, offset;
> -	int class;
> +	u16 guc_class;
>   
>   	offset = guc_ads_golden_lrc_offset(ads);
>   	addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset;
>   
> -	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
> -		u8 guc_class;
> -
> -		guc_class = xe_engine_class_to_guc_class(class);
> +	for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) {
> +		enum xe_engine_class class =
> +			guc_class_to_engine_class(guc_class);
>   
>   		if (!info_map_read(xe, &info_map,
>   				   engine_enabled_masks[guc_class]))
> @@ -943,14 +967,13 @@ static void guc_golden_lrc_populate(struct xe_guc_ads *ads)
>   			offsetof(struct __guc_ads_blob, system_info));
>   	size_t total_size = 0, alloc_size, real_size;
>   	u32 offset;
> -	int class;
> +	u16 guc_class;
>   
>   	offset = guc_ads_golden_lrc_offset(ads);
>   
> -	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
> -		u8 guc_class;
> -
> -		guc_class = xe_engine_class_to_guc_class(class);
> +	for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) {
> +		enum xe_engine_class class =
> +			guc_class_to_engine_class(guc_class);
>   
>   		if (!info_map_read(xe, &info_map,
>   				   engine_enabled_masks[guc_class]))

Re: [PATCH v2 02/10] drm/xe/guc: refactor to_guc_class() to accept hwe

[Daniele Ceraolo Spurio]

On 5/22/2026 5:37 AM, Matthew Auld wrote:
> Rather then inferring the GuC engine class from the generic hw engine
> class, pass in the hwe itself, which gives the complete view, like
> instance etc.  On future GuC version, there is dedicated PAGING class to
> identify the KMD reserved BCS engine, so we need more info here in order
> to return the correct GuC specific engine class.
>
> With this everything should now be using the new hwe based interface. No
> functional changes.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c |  2 +-
>   drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c  |  2 +-
>   drivers/gpu/drm/xe/xe_guc.h                 | 21 +---------------
>   drivers/gpu/drm/xe/xe_guc_ads.c             | 27 ++++++++++++++++++---
>   drivers/gpu/drm/xe/xe_guc_capture.c         | 12 ++++-----
>   drivers/gpu/drm/xe/xe_guc_capture.h         |  4 +--
>   drivers/gpu/drm/xe/xe_guc_engine_activity.c |  4 +--
>   drivers/gpu/drm/xe/xe_guc_submit.c          |  2 +-
>   8 files changed, 38 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
> index ffa27f66bba7..f28c7ae0e8c2 100644
> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c
> @@ -381,7 +381,7 @@ static ssize_t sched_group_engines_read(struct file *file, char __user *buf,
>   
>   	if (group < num_groups) {
>   		for_each_hw_engine(hwe, gt, id) {
> -			u8 guc_class = xe_engine_class_to_guc_class(hwe->class);
> +			u8 guc_class = xe_hwe_to_guc_class(hwe);
>   			u32 mask = groups[group].engines[guc_class];
>   
>   			if (mask & BIT(hwe->logical_instance)) {
> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
> index e8458d63742d..cf117bf52d41 100644
> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
> @@ -471,7 +471,7 @@ static void pf_sched_group_media_slices(struct xe_gt *gt, struct guc_sched_group
>   		return;
>   
>   	for_each_hw_engine(hwe, gt, id) {
> -		u8 guc_class = xe_engine_class_to_guc_class(hwe->class);
> +		u8 guc_class = xe_hwe_to_guc_class(hwe);
>   
>   		switch (hwe->class) {
>   		case XE_ENGINE_CLASS_VIDEO_DECODE:
> diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
> index 02514914f404..12faf0ba7229 100644
> --- a/drivers/gpu/drm/xe/xe_guc.h
> +++ b/drivers/gpu/drm/xe/xe_guc.h
> @@ -67,26 +67,7 @@ bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc);
>   int xe_guc_g2g_test_notification(struct xe_guc *guc, u32 *payload, u32 len);
>   #endif
>   
> -static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class)
> -{
> -	switch (class) {
> -	case XE_ENGINE_CLASS_RENDER:
> -		return GUC_RENDER_CLASS;
> -	case XE_ENGINE_CLASS_VIDEO_DECODE:
> -		return GUC_VIDEO_CLASS;
> -	case XE_ENGINE_CLASS_VIDEO_ENHANCE:
> -		return GUC_VIDEOENHANCE_CLASS;
> -	case XE_ENGINE_CLASS_COPY:
> -		return GUC_BLITTER_CLASS;
> -	case XE_ENGINE_CLASS_COMPUTE:
> -		return GUC_COMPUTE_CLASS;
> -	case XE_ENGINE_CLASS_OTHER:
> -		return GUC_GSC_OTHER_CLASS;
> -	default:
> -		XE_WARN_ON(class);
> -		return -1;
> -	}
> -}
> +u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe);
>   
>   static inline struct xe_gt *guc_to_gt(struct xe_guc *guc)
>   {
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index ffe60d77b713..6626803d75b5 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -279,7 +279,7 @@ static u32 engine_enable_mask(struct xe_gt *gt, u16 guc_class)
>   	u32 mask = 0;
>   
>   	for_each_hw_engine(hwe, gt, id) {
> -		if (xe_engine_class_to_guc_class(hwe->class) == guc_class)
> +		if (xe_hwe_to_guc_class(hwe) == guc_class)
>   			mask |= BIT(hwe->instance);
>   	}
>   
> @@ -504,6 +504,27 @@ static void fill_engine_enable_masks(struct xe_gt *gt,
>   		       engine_enable_mask(gt, GUC_GSC_OTHER_CLASS));
>   }
>   
> +u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe)
> +{
> +	switch (hwe->class) {
> +	case XE_ENGINE_CLASS_RENDER:
> +		return GUC_RENDER_CLASS;
> +	case XE_ENGINE_CLASS_VIDEO_DECODE:
> +		return GUC_VIDEO_CLASS;
> +	case XE_ENGINE_CLASS_VIDEO_ENHANCE:
> +		return GUC_VIDEOENHANCE_CLASS;
> +	case XE_ENGINE_CLASS_COPY:
> +		return GUC_BLITTER_CLASS;
> +	case XE_ENGINE_CLASS_COMPUTE:
> +		return GUC_COMPUTE_CLASS;
> +	case XE_ENGINE_CLASS_OTHER:
> +		return GUC_GSC_OTHER_CLASS;
> +	default:
> +		XE_WARN_ON(hwe->class);
> +		return -1;
> +	}
> +}
> +
>   /*
>    * Write the offsets corresponding to the golden LRCs. The actual data is
>    * populated later by guc_golden_lrc_populate()
> @@ -574,7 +595,7 @@ static void guc_mapping_table_init(struct xe_gt *gt,
>   	for_each_hw_engine(hwe, gt, id) {
>   		u8 guc_class;
>   
> -		guc_class = xe_engine_class_to_guc_class(hwe->class);
> +		guc_class = xe_hwe_to_guc_class(hwe);
>   		info_map_write(xe, info_map,
>   			       mapping_table[guc_class][hwe->logical_instance],
>   			       hwe->instance);
> @@ -824,7 +845,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
>   		 * 2. Record in the header (ads.reg_state_list) the address
>   		 * location and number of entries
>   		 */
> -		gc = xe_engine_class_to_guc_class(hwe->class);
> +		gc = xe_hwe_to_guc_class(hwe);
>   		ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].address, addr);
>   		ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].count, count);
>   
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
> index 21f7caf9ea08..50c6b9466c14 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.c
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.c
> @@ -440,7 +440,7 @@ static void guc_capture_alloc_steered_lists(struct xe_guc *guc)
>   	 * to be extended
>   	 */
>   	for_each_hw_engine(hwe, gt, id) {
> -		if (xe_engine_class_to_guc_capture_class(hwe->class) ==
> +		if (xe_hwe_to_guc_capture_class(hwe) ==
>   		    GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE) {
>   			has_rcs_ccs = true;
>   			break;
> @@ -812,7 +812,7 @@ static int guc_capture_output_size_est(struct xe_guc *guc)
>   	for_each_hw_engine(hwe, gt, id) {
>   		enum guc_capture_list_class_type capture_class;
>   
> -		capture_class = xe_engine_class_to_guc_capture_class(hwe->class);
> +		capture_class = xe_hwe_to_guc_capture_class(hwe);
>   		capture_size += sizeof(struct guc_state_capture_group_header_t) +
>   					 (3 * sizeof(struct guc_state_capture_header_t));
>   
> @@ -1620,7 +1620,7 @@ xe_engine_manual_capture(struct xe_hw_engine *hwe, struct xe_hw_engine_snapshot
>   	if (!new)
>   		return;
>   
> -	capture_class = xe_engine_class_to_guc_capture_class(hwe->class);
> +	capture_class = xe_hwe_to_guc_capture_class(hwe);
>   	for (type = GUC_STATE_CAPTURE_TYPE_GLOBAL; type < GUC_STATE_CAPTURE_TYPE_MAX; type++) {
>   		struct gcap_reg_list_info *reginfo = &new->reginfo[type];
>   		/*
> @@ -1662,7 +1662,7 @@ xe_engine_manual_capture(struct xe_hw_engine *hwe, struct xe_hw_engine_snapshot
>   		}
>   	}
>   
> -	new->eng_class = xe_engine_class_to_guc_class(hwe->class);
> +	new->eng_class = xe_hwe_to_guc_class(hwe);
>   	new->eng_inst = hwe->instance;
>   	new->guc_id = guc_id;
>   	new->lrca = lrca;
> @@ -1826,7 +1826,7 @@ void xe_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot, struct drm
>   
>   	xe_gt_assert(gt, snapshot->hwe);
>   
> -	capture_class = xe_engine_class_to_guc_capture_class(snapshot->hwe->class);
> +	capture_class = xe_hwe_to_guc_capture_class(snapshot->hwe);
>   
>   	drm_printf(p, "%s (physical), logical instance=%d\n",
>   		   snapshot->name ? snapshot->name : "",
> @@ -1898,7 +1898,7 @@ xe_guc_capture_get_matching_and_lock(struct xe_exec_queue *q)
>   	for_each_hw_engine(hwe, q->gt, id) {
>   		if (hwe != q->hwe)
>   			continue;
> -		guc_class = xe_engine_class_to_guc_class(hwe->class);
> +		guc_class = xe_hwe_to_guc_class(hwe);
>   		break;
>   	}
>   
> diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h
> index dca97d52b192..eb954f4d1ffd 100644
> --- a/drivers/gpu/drm/xe/xe_guc_capture.h
> +++ b/drivers/gpu/drm/xe/xe_guc_capture.h
> @@ -35,9 +35,9 @@ static inline enum guc_capture_list_class_type xe_guc_class_to_capture_class(u16
>   }
>   
>   static inline enum guc_capture_list_class_type
> -xe_engine_class_to_guc_capture_class(enum xe_engine_class class)
> +xe_hwe_to_guc_capture_class(struct xe_hw_engine *hwe)
>   {
> -	return xe_guc_class_to_capture_class(xe_engine_class_to_guc_class(class));
> +	return xe_guc_class_to_capture_class(xe_hwe_to_guc_class(hwe));
>   }
>   
>   void xe_guc_capture_process(struct xe_guc *guc);
> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> index 2b99c1ebdd58..150d891d5a09 100644
> --- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> @@ -27,7 +27,7 @@ static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_eng
>   {
>   	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>   	struct engine_activity_buffer *buffer;
> -	u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
> +	u16 guc_class = xe_hwe_to_guc_class(hwe);
>   	size_t offset;
>   
>   	if (engine_activity->num_functions) {
> @@ -150,7 +150,7 @@ static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine
>   {
>   	struct xe_guc *guc = &hwe->gt->uc.guc;
>   	struct engine_activity_group *eag = &guc->engine_activity.eag[index];
> -	u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
> +	u16 guc_class = xe_hwe_to_guc_class(hwe);
>   
>   	return &eag->engine[guc_class][hwe->logical_instance];
>   }
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index afd8cc7bd231..1ee4f2434876 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -985,7 +985,7 @@ static void register_exec_queue(struct xe_exec_queue *q, int ctx_type)
>   
>   	memset(&info, 0, sizeof(info));
>   	info.context_idx = q->guc->id;
> -	info.engine_class = xe_engine_class_to_guc_class(q->class);
> +	info.engine_class = xe_hwe_to_guc_class(q->hwe);
>   	info.engine_submit_mask = q->logical_mask;
>   	info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc));
>   	info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));

Re: [PATCH v2 04/10] drm/xe/hw_engine: don't open code is_usm_hwe()

[Daniele Ceraolo Spurio]

On 5/22/2026 5:37 AM, Matthew Auld wrote:
> Prefer is_usm_hwe() here.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/xe/xe_hw_engine.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 8c66ff6f3d3c..768b0cd4c16a 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -1037,8 +1037,7 @@ bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe)
>   	    hwe->logical_instance >= gt->ccs_mode)
>   		return true;
>   
> -	return xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY &&
> -		hwe->instance == gt->usm.reserved_bcs_instance;
> +	return xe_gt_is_usm_hwe(gt, hwe);
>   }
>   
>   const char *xe_hw_engine_class_to_str(enum xe_engine_class class)

Re: [PATCH v2 01/10] drm/xe/guc: refactor ads to use guc_class

[Matthew Auld]

On 23/05/2026 02:03, Daniele Ceraolo Spurio wrote:
> 
> 
> On 5/22/2026 5:37 AM, Matthew Auld wrote:
>> Currently in the lrc init flow on the ads side, we loop through each
>> generic engine class and convert that to the respective guc engine
>> class. However, with some upcoming changes, it will be better to go the
>> opposite way and loop through every guc engine class, and convert that
>> to the generic engine class.
>>
>> This also reworks engine_enable_mask to operate on the guc_class, that
>> way we can easily filter out the PAGING vs normal BSC, when applicable.
> 
> nit: this sentence looks like it should go after the next one, because 
> here you mention PAGING directly but below you introduce the "new engine 
> class".

Will fix.

> 
>>
>> This will be needed in an upcoming patch where we have a new guc engine
>> class that just matches up to the existing blitter/copy class, but needs
>> to be treated as separate entity from the normal copy lrc, when setting
>> up the ADS.
>>
>> As a bonus this also gets rid of two xe_engine_class_to_guc_class()
>> users which will be helpful for the next patch.
>>
>> No functional changes.
>>
>> Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_guc_ads.c | 67 ++++++++++++++++++++++-----------
>>   1 file changed, 45 insertions(+), 22 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/ 
>> xe_guc_ads.c
>> index b9bca6084a4f..ffe60d77b713 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
>> @@ -251,15 +251,37 @@ static size_t calculate_regset_size(struct xe_gt 
>> *gt)
>>       return count * sizeof(struct guc_mmio_reg);
>>   }
>> -static u32 engine_enable_mask(struct xe_gt *gt, enum xe_engine_class 
>> class)
>> +static inline enum xe_engine_class guc_class_to_engine_class(u16 
>> guc_class)
>> +{
>> +    switch (guc_class) {
>> +    case GUC_RENDER_CLASS:
>> +        return XE_ENGINE_CLASS_RENDER;
>> +    case GUC_VIDEO_CLASS:
>> +        return XE_ENGINE_CLASS_VIDEO_DECODE;
>> +    case GUC_VIDEOENHANCE_CLASS:
>> +        return XE_ENGINE_CLASS_VIDEO_ENHANCE;
>> +    case GUC_BLITTER_CLASS:
>> +        return XE_ENGINE_CLASS_COPY;
>> +    case GUC_COMPUTE_CLASS:
>> +        return XE_ENGINE_CLASS_COMPUTE;
>> +    case GUC_GSC_OTHER_CLASS:
>> +        return XE_ENGINE_CLASS_OTHER;
>> +    default:
>> +        XE_WARN_ON(guc_class);
>> +        return -1;
>> +    }
>> +}
>> +
>> +static u32 engine_enable_mask(struct xe_gt *gt, u16 guc_class)
>>   {
>>       struct xe_hw_engine *hwe;
>>       enum xe_hw_engine_id id;
>>       u32 mask = 0;
>> -    for_each_hw_engine(hwe, gt, id)
>> -        if (hwe->class == class)
>> +    for_each_hw_engine(hwe, gt, id) {
>> +        if (xe_engine_class_to_guc_class(hwe->class) == guc_class)
>>               mask |= BIT(hwe->instance);
>> +    }
> 
> nit: the brackets aren't really needed here.
> 
>>       return mask;
>>   }
>> @@ -268,10 +290,13 @@ static size_t calculate_golden_lrc_size(struct 
>> xe_guc_ads *ads)
>>   {
>>       struct xe_gt *gt = ads_to_gt(ads);
>>       size_t total_size = 0, alloc_size, real_size;
>> -    int class;
>> +    u16 guc_class;
>> -    for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
>> -        if (!engine_enable_mask(gt, class))
>> +    for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; + 
>> +guc_class) {
>> +        enum xe_engine_class class =
>> +            guc_class_to_engine_class(guc_class);
>> +
>> +        if (!engine_enable_mask(gt, guc_class))
>>               continue;
>>           real_size = xe_gt_lrc_size(gt, class);
>> @@ -465,18 +490,18 @@ static void fill_engine_enable_masks(struct 
>> xe_gt *gt,
>>       struct xe_device *xe = gt_to_xe(gt);
>>       info_map_write(xe, info_map, 
>> engine_enabled_masks[GUC_RENDER_CLASS],
>> -               engine_enable_mask(gt, XE_ENGINE_CLASS_RENDER));
>> +               engine_enable_mask(gt, GUC_RENDER_CLASS));
>>       info_map_write(xe, info_map, 
>> engine_enabled_masks[GUC_BLITTER_CLASS],
>> -               engine_enable_mask(gt, XE_ENGINE_CLASS_COPY));
>> +               engine_enable_mask(gt, GUC_BLITTER_CLASS));
>>       info_map_write(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS],
>> -               engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_DECODE));
>> +               engine_enable_mask(gt, GUC_VIDEO_CLASS));
>>       info_map_write(xe, info_map,
>>                  engine_enabled_masks[GUC_VIDEOENHANCE_CLASS],
>> -               engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE));
>> +               engine_enable_mask(gt, GUC_VIDEOENHANCE_CLASS));
>>       info_map_write(xe, info_map, 
>> engine_enabled_masks[GUC_COMPUTE_CLASS],
>> -               engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE));
>> +               engine_enable_mask(gt, GUC_COMPUTE_CLASS));
>>       info_map_write(xe, info_map, 
>> engine_enabled_masks[GUC_GSC_OTHER_CLASS],
>> -               engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER));
>> +               engine_enable_mask(gt, GUC_GSC_OTHER_CLASS));
> 
> Would it be worth making this a loop now that we use the GuC class 
> everywhere?
> Something like:
> 
> for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class)
>      info_map_write(xe, info_map,
>                 engine_enabled_masks[guc_class],
>                 engine_enable_mask(gt, guc_class));
 > >
> Not a blocker.

That looks a lot better. Will incorporate this. Thanks.

> 
> Apart from the nits this LGTM, so:
> 
> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> 
> Daniele
> 
>>   }
>>   /*
>> @@ -491,15 +516,14 @@ static void guc_golden_lrc_init(struct 
>> xe_guc_ads *ads)
>>               offsetof(struct __guc_ads_blob, system_info));
>>       size_t alloc_size, real_size;
>>       u32 addr_ggtt, offset;
>> -    int class;
>> +    u16 guc_class;
>>       offset = guc_ads_golden_lrc_offset(ads);
>>       addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset;
>> -    for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
>> -        u8 guc_class;
>> -
>> -        guc_class = xe_engine_class_to_guc_class(class);
>> +    for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; + 
>> +guc_class) {
>> +        enum xe_engine_class class =
>> +            guc_class_to_engine_class(guc_class);
>>           if (!info_map_read(xe, &info_map,
>>                      engine_enabled_masks[guc_class]))
>> @@ -943,14 +967,13 @@ static void guc_golden_lrc_populate(struct 
>> xe_guc_ads *ads)
>>               offsetof(struct __guc_ads_blob, system_info));
>>       size_t total_size = 0, alloc_size, real_size;
>>       u32 offset;
>> -    int class;
>> +    u16 guc_class;
>>       offset = guc_ads_golden_lrc_offset(ads);
>> -    for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
>> -        u8 guc_class;
>> -
>> -        guc_class = xe_engine_class_to_guc_class(class);
>> +    for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; + 
>> +guc_class) {
>> +        enum xe_engine_class class =
>> +            guc_class_to_engine_class(guc_class);
>>           if (!info_map_read(xe, &info_map,
>>                      engine_enabled_masks[guc_class]))
>