[PATCH 0/2] drm/i915/display: Couple of DC3co fixes

[Suraj Kandpal <suraj.kandpal@intel.com>]

While looking at why DC3co sequences I came across some steps
that were missed or miscoded.
The first one is a plain missing register write. DC3co enabling is
double buffered on a CMTG delayed vblank and CHICKEN_DCPR_1 bit 5 picks
which CMTG that is, but we never program it. Setups running on CMTG B
end up armed off CMTG A's vblank and only work because the reset value
happens to be the one we want half the time.
The second one is us being stricter than the spec. We only allow DC3co
when pipe A drives port A or pipe B drives port B, but Bspec has no such
restriction and neither does CMTG, so an eDP panel on the other port
just loses DC3co for no reason.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Suraj Kandpal (2):
  drm/i915/cmtg: Select the right CMTG vblank for DC3co
  drm/i915/display: Don't require a 1:1 pipe to port mapping for DC3co

 drivers/gpu/drm/i915/display/intel_cmtg.c          |  2 ++
 drivers/gpu/drm/i915/display/intel_display_power.c | 10 +++-------
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  1 +
 3 files changed, 6 insertions(+), 7 deletions(-)

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2.34.1