From: sashiko-bot@kernel.org
To: "Suraj Kandpal" <suraj.kandpal@intel.com>
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915/display: Don't require a 1:1 pipe to port mapping for DC3co
Date: Thu, 24 Sep 2026 06:05:35 +0000 [thread overview]
Message-ID: <20260924060535.E81611F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260924055734.2138787-3-suraj.kandpal@intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/display: DC3CO accidentally disabled for DISPLAY_VER > 35
--
commit fe8edcc01c82523ff83cda52b4cdaab761f57f66
Author: Suraj Kandpal <suraj.kandpal@intel.com>
drm/i915/display: Don't require a 1:1 pipe to port mapping for DC3co
This commit relaxes the strict 1:1 pipe-to-port mapping requirement for DC3co
on Xe3p_LPD (DISPLAY_VER 35). It replaces the previous if/else conditional
with a simplified check to allow DC3co on eDP panels wired to non-matching
ports.
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2e534ddb73479..d475e62e8f40b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -428,18 +428,14 @@ void intel_display_power_dc3co_update(struct intel_display *display, u32 trigger
> static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> enum port port = dig_port->base.port;
> int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
>
> - /* Need to follow 1:1 mapping because of CMTG restriction */
> - if (DISPLAY_VER(to_intel_display(crtc_state)) == 35)
> - return num_pipes == 1 &&
> - ((pipe == PIPE_A && port == PORT_A) ||
> - (pipe == PIPE_B && port == PORT_B));
> - else
> - return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B;
> + return DISPLAY_VER(display) == 35 && num_pipes == 1 && pipe <= PIPE_B &&
> + port <= PORT_B;
[Severity: Medium]
Will this inadvertently disable DC3co for platforms where DISPLAY_VER is
greater than 35?
By replacing the entire if/else block with a single return statement that
explicitly checks DISPLAY_VER(display) == 35, it appears
intel_dc3co_port_pipe_compatible() will now unconditionally return false for
any future hardware with a version > 35.
Since the HAS_DC3CO() macro usually guards entry into DC3co paths for
platforms where DISPLAY_VER >= 35, does it make sense to drop the strict
version equality check here so that future platforms aren't unintentionally
restricted?
> }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260924055734.2138787-1-suraj.kandpal@intel.com?part=2
next prev parent reply other threads:[~2026-09-24 6:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-24 5:57 [PATCH 0/2] drm/i915/display: Couple of DC3co fixes Suraj Kandpal
2026-09-24 5:57 ` [PATCH 1/2] drm/i915/cmtg: Select the right CMTG vblank for DC3co Suraj Kandpal
2026-09-25 10:52 ` Jani Nikula
2026-09-24 5:57 ` [PATCH 2/2] drm/i915/display: Don't require a 1:1 pipe to port mapping " Suraj Kandpal
2026-09-24 6:05 ` sashiko-bot [this message]
2026-09-24 6:12 ` Kandpal, Suraj
2026-09-28 7:01 ` Dibin Moolakadan Subrahmanian
2026-09-29 4:09 ` Kandpal, Suraj
2026-09-24 6:06 ` ✓ CI.KUnit: success for drm/i915/display: Couple of DC3co fixes Patchwork
2026-09-24 6:47 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-24 19:57 ` ✓ Xe.CI.FULL: " Patchwork
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