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From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>,
	<intel-gfx@lists.freedesktop.org>,
	<intel-xe@lists.freedesktop.org>
Cc: <ankit.k.nautiyal@intel.com>, <animesh.manna@intel.com>,
	"Shankar, Uma" <uma.shankar@intel.com>
Subject: Re: [PATCH 2/2] drm/i915/display: Don't require a 1:1 pipe to port mapping for DC3co
Date: Mon, 28 Sep 2026 12:31:41 +0530	[thread overview]
Message-ID: <26087b72-fd59-42d2-9791-adff6924a645@intel.com> (raw)
In-Reply-To: <20260924055734.2138787-3-suraj.kandpal@intel.com>

On 9/24/2026 11:27 AM, Suraj Kandpal wrote:
> Bspec allows transcoder A and transcoder B to drive either port A or
> port B with DC3co, and CMTG doesn't restrict this. Requiring
> a strict 1:1 mapping on Xe3p_LPD just loses DC3co on eDP panels wired to
> the other port.

You are right that DC3CO does not require the 1:1 restriction.
As mentioned in the comment, the restriction was added due to the CMTG limitation.
While this is not explicitly stated, some relevant information is available in BSpec 68915.

Could you please check whether the newly enabled combinations,
PORT A – PIPE B or PORT B – PIPE A, are working for DC3CO tests?

> Bspec: 75253
> Fixes: d75ea53314db ("drm/i915/display: Add DC3CO compute and set target state in commit tail")
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display_power.c | 10 +++-------
>   1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 1b60ce2dd00c..4ce941319664 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -427,18 +427,14 @@ void intel_display_power_dc3co_update(struct intel_display *display, u32 trigger
>   static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
>   					     const struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_display *display = to_intel_display(intel_dp);
>   	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>   	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>   	enum port port = dig_port->base.port;
>   	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
>   
> -	/* Need to follow 1:1 mapping because of CMTG restriction */
> -	if (DISPLAY_VER(to_intel_display(crtc_state)) == 35)
> -		return num_pipes == 1 &&
> -		       ((pipe == PIPE_A && port == PORT_A) ||
> -			(pipe == PIPE_B && port == PORT_B));
> -	else
> -		return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B;
> +	return DISPLAY_VER(display) == 35 && num_pipes == 1 && pipe <= PIPE_B &&
> +		port <= PORT_B;
>   }
>   
>   void intel_display_power_dc3co_compute(struct intel_atomic_state *state)


  parent reply	other threads:[~2026-09-28  7:01 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-24  5:57 [PATCH 0/2] drm/i915/display: Couple of DC3co fixes Suraj Kandpal
2026-09-24  5:57 ` [PATCH 1/2] drm/i915/cmtg: Select the right CMTG vblank for DC3co Suraj Kandpal
2026-09-25 10:52   ` Jani Nikula
2026-09-24  5:57 ` [PATCH 2/2] drm/i915/display: Don't require a 1:1 pipe to port mapping " Suraj Kandpal
2026-09-24  6:05   ` sashiko-bot
2026-09-24  6:12     ` Kandpal, Suraj
2026-09-28  7:01   ` Dibin Moolakadan Subrahmanian [this message]
2026-09-29  4:09     ` Kandpal, Suraj
2026-09-24  6:06 ` ✓ CI.KUnit: success for drm/i915/display: Couple of DC3co fixes Patchwork
2026-09-24  6:47 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-24 19:57 ` ✓ Xe.CI.FULL: " Patchwork

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