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From: Riana Tauro <riana.tauro@intel.com>
To: "Anoop, Vijay" <anoop.c.vijay@intel.com>,
	<intel-xe@lists.freedesktop.org>
Cc: <umesh.nerlige.ramappa@intel.com>, <badal.nilawar@intel.com>,
	<rodrigo.vivi@intel.com>, <aravind.iddamsetty@intel.com>,
	<anshuman.gupta@intel.com>, <matthew.d.roper@intel.com>,
	<michael.j.ruhl@intel.com>, <paul.e.luse@intel.com>,
	<mohamed.mansoor.v@intel.com>, <kam.nasim@intel.com>
Subject: Re: [PATCH v9 6/6] drm/xe/pci: Enable System Controller for CRI platform
Date: Wed, 11 Mar 2026 17:01:49 +0530	[thread overview]
Message-ID: <282f4211-12e5-4fe0-96dc-72f7b718cbe9@intel.com> (raw)
In-Reply-To: <20260310182336.611041-14-anoop.c.vijay@intel.com>

Hi Anoop

Title should be

  drm/xe/xe_pci: Enable System Controller for CRI platform

Thanks
Riana

On 3/10/2026 11:53 PM, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> Enable System Controller support for CRI platform by setting
> has_sysctrl flag in device descriptor and runtime device info.
> 
> This allows the System Controller subsystem and mailbox communication
> to be initialized on CRI platform.
> 
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> ---
> v8: (Matt, Michal)
> - Reordered patches for logical flow
> ---
>   drivers/gpu/drm/xe/xe_pci.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 29f976e66848..3d4a6619315f 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -465,6 +465,7 @@ static const struct xe_device_desc cri_desc = {
>   	.has_soc_remapper_sysctrl = true,
>   	.has_soc_remapper_telem = true,
>   	.has_sriov = true,
> +	.has_sysctrl = true,
>   	.max_gt_per_tile = 2,
>   	MULTI_LRC_MASK,
>   	.require_force_probe = true,
> @@ -764,6 +765,7 @@ static int xe_info_init_early(struct xe_device *xe,
>   	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
>   	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
>   		desc->has_sriov;
> +	xe->info.has_sysctrl = desc->has_sysctrl;
>   	xe->info.skip_guc_pc = desc->skip_guc_pc;
>   	xe->info.skip_mtcfg = desc->skip_mtcfg;
>   	xe->info.skip_pcode = desc->skip_pcode;


  reply	other threads:[~2026-03-11 11:32 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-10 18:23 [PATCH v9 0/6] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Anoop, Vijay
2026-03-10 18:23 ` [PATCH v9 1/6] drm/xe/sysctrl: Add System Controller types and device integration Anoop, Vijay
2026-03-18 16:07   ` Umesh Nerlige Ramappa
2026-03-10 18:23 ` [PATCH v9 2/6] drm/xe/sysctrl: Add System Controller register definitions Anoop, Vijay
2026-03-10 18:23 ` [PATCH v9 3/6] drm/xe/sysctrl: Add mailbox communication headers Anoop, Vijay
2026-03-11  7:29   ` Riana Tauro
2026-03-13  4:47     ` Nilawar, Badal
2026-03-10 18:23 ` [PATCH v9 4/6] drm/xe/sysctrl: Add System Controller initialization Anoop, Vijay
2026-03-11 10:16   ` Gupta, Anshuman
2026-03-11 10:59   ` Riana Tauro
2026-03-12  4:32     ` Umesh Nerlige Ramappa
2026-03-10 18:23 ` [PATCH v9 5/6] drm/xe/sysctrl: Add mailbox communication implementation Anoop, Vijay
2026-03-12  5:13   ` Riana Tauro
2026-03-10 18:23 ` [PATCH v9 6/6] drm/xe/pci: Enable System Controller for CRI platform Anoop, Vijay
2026-03-11 11:31   ` Riana Tauro [this message]
2026-03-12  5:54   ` Umesh Nerlige Ramappa
2026-03-10 18:30 ` ✗ CI.checkpatch: warning for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10) Patchwork
2026-03-10 18:31 ` ✓ CI.KUnit: success " Patchwork
2026-03-10 19:08 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-11 12:30 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-12  5:18 ` [PATCH v9 0/6] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Riana Tauro

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