From: Riana Tauro <riana.tauro@intel.com>
To: "Anoop, Vijay" <anoop.c.vijay@intel.com>,
<intel-xe@lists.freedesktop.org>
Cc: <umesh.nerlige.ramappa@intel.com>, <badal.nilawar@intel.com>,
<rodrigo.vivi@intel.com>, <aravind.iddamsetty@intel.com>,
<anshuman.gupta@intel.com>, <matthew.d.roper@intel.com>,
<michael.j.ruhl@intel.com>, <paul.e.luse@intel.com>,
<mohamed.mansoor.v@intel.com>, <kam.nasim@intel.com>
Subject: Re: [PATCH v9 3/6] drm/xe/sysctrl: Add mailbox communication headers
Date: Wed, 11 Mar 2026 12:59:02 +0530 [thread overview]
Message-ID: <d7eeb026-2de9-4dc3-ba4e-610cc9a97e17@intel.com> (raw)
In-Reply-To: <20260310182336.611041-11-anoop.c.vijay@intel.com>
Hi Anoop
On 3/10/2026 11:53 PM, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
>
> Add ABI definitions, mailbox API, and command structures for
> System Controller communication.
>
> No functional code yet. Only protocol layer definitions are added.
>
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> ---
> v8: (Matt, Michal)
> - Reordered patches for logical flow
> - Moved ABI definitions to dedicated header
>
> v9: (Badal)
> - Renamed MKHI to SCHI (System Controller Host Interface)
> ---
>
> drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h | 31 ++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 31 ++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 35 +++++++++++++++++++
> 3 files changed, 97 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>
> diff --git a/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
> new file mode 100644
> index 000000000000..bc4793fb21e5
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_ABI_H_
> +#define _XE_SYSCTRL_ABI_H_
> +
> +#include <linux/types.h>
> +
Add documentation. Anyone not seeing the version history will not know
what SCHI is.
What is the reason of using SCHI? why not just mailbox_msg_hdr?
> +struct xe_sysctrl_mailbox_schi_msg_hdr {
> + __le32 data;
> +} __packed;
> +
I don't see this getting used outside sysctrl file. Will there be any
users for this else move it to .c
> +struct xe_sysctrl_app_msg_hdr {
> + __le32 data;
> +} __packed;
> +
This should be u32. Any conversions should be done in sc_send_command
not by upper layer.
> +#define SCHI_HDR_GROUP_ID_MASK GENMASK(7, 0)
> +#define SCHI_HDR_COMMAND_MASK GENMASK(14, 8)
> +#define SCHI_HDR_COMMAND_MAX 0x7f
> +#define SCHI_HDR_IS_RESPONSE BIT(15)
> +#define SCHI_HDR_RESERVED_MASK GENMASK(23, 16)
> +#define SCHI_HDR_RESULT_MASK GENMASK(31, 24)
> +
> +#define APP_HDR_GROUP_ID_MASK GENMASK(7, 0)
> +#define APP_HDR_COMMAND_MASK GENMASK(15, 8)
> +#define APP_HDR_VERSION_MASK GENMASK(23, 16)
> +#define APP_HDR_RESERVED_MASK GENMASK(31, 24)
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> new file mode 100644
> index 000000000000..91460be9e22c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_MAILBOX_H_
> +#define _XE_SYSCTRL_MAILBOX_H_
> +
> +#include <linux/bitfield.h>
> +#include <linux/types.h>
> +
> +#include "abi/xe_sysctrl_abi.h"
> +
> +struct xe_sysctrl;
> +struct xe_sysctrl_mailbox_command;
> +
> +#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr) \
> + FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
> +
> +#define XE_SYSCTRL_APP_HDR_COMMAND(hdr) \
> + FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
> +
> +#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> + FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
> +
> +void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> +int xe_sysctrl_send_command(struct xe_sysctrl *sc,
> + struct xe_sysctrl_mailbox_command *cmd,
> + size_t *rdata_len);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> new file mode 100644
> index 000000000000..fdf8d1d4e3cd
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_MAILBOX_TYPES_H_
> +#define _XE_SYSCTRL_MAILBOX_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#include "abi/xe_sysctrl_abi.h"
> +
> +/**
> + * struct xe_sysctrl_mailbox_command - System Controller mailbox command
> + */
> +struct xe_sysctrl_mailbox_command {
> + /** @header: Application message header containing command information */
> + struct xe_sysctrl_app_msg_hdr header;
> + /** @data_in: Pointer to input payload data (can be NULL if no input data) */
> + void *data_in;
> + /** @data_in_len: Size of input payload in bytes (0 if no input data) */
> + size_t data_in_len;
> + /** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
> + void *data_out;
> + /** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
> + size_t data_out_len;
> +};
> +
> +#define XE_SYSCTRL_MB_FRAME_SIZE 16
> +#define XE_SYSCTRL_MB_MAX_FRAMES 64
> +#define XE_SYSCTRL_MB_MAX_MESSAGE_SIZE (XE_SYSCTRL_MB_FRAME_SIZE * XE_SYSCTRL_MB_MAX_FRAMES)
Maybe use another tab and keep the macros aligned
Also if these are unused by other layers, define it in .c
Thanks
Riana
> +
> +#define XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS 500
> +
> +#endif
next prev parent reply other threads:[~2026-03-11 7:29 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-10 18:23 [PATCH v9 0/6] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Anoop, Vijay
2026-03-10 18:23 ` [PATCH v9 1/6] drm/xe/sysctrl: Add System Controller types and device integration Anoop, Vijay
2026-03-18 16:07 ` Umesh Nerlige Ramappa
2026-03-10 18:23 ` [PATCH v9 2/6] drm/xe/sysctrl: Add System Controller register definitions Anoop, Vijay
2026-03-10 18:23 ` [PATCH v9 3/6] drm/xe/sysctrl: Add mailbox communication headers Anoop, Vijay
2026-03-11 7:29 ` Riana Tauro [this message]
2026-03-13 4:47 ` Nilawar, Badal
2026-03-10 18:23 ` [PATCH v9 4/6] drm/xe/sysctrl: Add System Controller initialization Anoop, Vijay
2026-03-11 10:16 ` Gupta, Anshuman
2026-03-11 10:59 ` Riana Tauro
2026-03-12 4:32 ` Umesh Nerlige Ramappa
2026-03-10 18:23 ` [PATCH v9 5/6] drm/xe/sysctrl: Add mailbox communication implementation Anoop, Vijay
2026-03-12 5:13 ` Riana Tauro
2026-03-10 18:23 ` [PATCH v9 6/6] drm/xe/pci: Enable System Controller for CRI platform Anoop, Vijay
2026-03-11 11:31 ` Riana Tauro
2026-03-12 5:54 ` Umesh Nerlige Ramappa
2026-03-10 18:30 ` ✗ CI.checkpatch: warning for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10) Patchwork
2026-03-10 18:31 ` ✓ CI.KUnit: success " Patchwork
2026-03-10 19:08 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-11 12:30 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-12 5:18 ` [PATCH v9 0/6] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms Riana Tauro
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