[PATCH v9 0/6] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms

[PATCH v9 0/6] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

This patch series introduces System Controller (sysctrl) component for Intel Xe3p 
dGPU platforms.

This component provides the foundational infrastructure for communication
with the System Controller firmware using MKHI protocol over a mailbox interface.

Key features introduced:
- Detection and initialization of System Controller interface on Xe3p dGPU platforms
- Mailbox communication with System Controller firmware
- Fragmented message transfer for large command payloads

This implementation establishes the base for future System Controller feature
enablement and firmware command handling.
---
v2: (Umesh)
- Fix commit message to 75 chars per line
- Address CI.Hooks and checkpatch warnings
- Add sc_to_xe() helper for cleaner conversions
- Alphabetical order for headers
- Simplify write/read frame logic using memcpy
- Drop redundant frame length checks
- Use xe_mmio_rmw32() for register updates
- Align FIELD_PREP macros
- Improve error handling and timeout messages
- Handle phase_bit revert on write-frame failure
- Update rdata_len on partial receive before return
- Remove unnecessary headers

v3: (Matt, Riana, Umesh)
- Split patch into logical series
- Rename SC_* macros to SYSCTRL_* for consistency
- Move MKHI_* defines to .c file
- Pass xe directly to helpers
- Place devm_add_action_or_reset() after set_sysctrl_region()
- Add kernel-doc for xe_sysctrl_mailbox_init()
- Add short documentation for System Controller in xe_sysctrl.c
- Avoid hardcoded sizes
- Move structs to _types.h

v4: (Matt, Mike)
- Code style improvements
- Add domain-specific MMIO accessor
- Change phase_bit to bool type
- Add input validation and buffer overflow protection

v5: (Umesh, Riana)
- Reset phase bit to 0 on error conditions
- Refactor mailbox receive path
- Updated xe_err messages for consistency

v6: (Matt)
- Move protocol constants from xe_sysctrl_regs.h to xe_sysctrl_mailbox_types.h
- Add SYSCTRL_MB_CTRL_MKHI_CMD helper macro

v7:
- Fix for CI failure

v8: (Matt, Michal, Shuicheng)
- Reordered patches for logical flow
- Moved ABI definitions to dedicated header
- Static functions renamed with short prefix
- Fixed include order
- Added VF check
- Converted runtime checks to assertions
- Changed xe_sysctrl_send_command() function parameter from 'xe' to 'sc'
- Added frame length validation and command overflow protection
- Use REG_FIELD_PREP for hardware registers
- Changed error format to %pe
- Removed unnecessary NULL checks and explicit zeros
- Fixed kernel-doc syntax
- Added sc_to_xe() helper

v9: (Matt, Umesh, Badal)
- Extended commit message to explain System Controller and purpose of
  `has_sysctrl` flag
- Normalized hexadecimal literal casing
- Renamed MKHI to SCHI (System Controller Host Interface)
- Fixed kernel-doc syntax
---

Anoop Vijay (6):
  drm/xe/sysctrl: Add System Controller types and device integration
  drm/xe/sysctrl: Add System Controller register definitions
  drm/xe/sysctrl: Add mailbox communication headers
  drm/xe/sysctrl: Add System Controller initialization
  drm/xe/sysctrl: Add mailbox communication implementation
  drm/xe/pci: Enable System Controller for CRI platform

 drivers/gpu/drm/xe/Makefile                   |   2 +
 drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h       |  31 ++
 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h     |  36 ++
 drivers/gpu/drm/xe/xe_device.c                |   5 +
 drivers/gpu/drm/xe/xe_device_types.h          |   6 +
 drivers/gpu/drm/xe/xe_pci.c                   |   2 +
 drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
 drivers/gpu/drm/xe/xe_sysctrl.c               |  84 ++++
 drivers/gpu/drm/xe/xe_sysctrl.h               |  21 +
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c       | 364 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h       |  31 ++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |  35 ++
 drivers/gpu/drm/xe/xe_sysctrl_types.h         |  32 ++
 13 files changed, 650 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
 create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h

-- 
2.43.0

[PATCH v9 1/6] drm/xe/sysctrl: Add System Controller types and device integration

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Add foundational type definitions for System Controller (sysctrl)
support and integrate them into xe_device structure. Also add a
 capability flag to device descriptor and runtime
info.

System Controller is a separate management entity responsible for
certain platform-level control and coordination tasks in Intel Xe3p
dGPU platforms. Driver communicates with it via a mailbox interface
using SCHI (System Controller Host Interface) protocol for operations
delegated to this controller.

This commit introduces core data structures required for sysctrl
support, including MMIO region, command mutex, and phase bit used
by SCHI protocol.  flag explicitly records presence of
sysctrl hardware on supported platforms.

No functional changes. This is preparatory infrastructure for System
Controller support.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
---
v4: (Matt, Mike)
- Add domain-specific MMIO accessor
- Change phase_bit type from u32 to bool

v6: (Matt)
- Add mailbox protocol constants

v8: (Matt, Michal)
- Reordered patches for logical flow

v9: (Matt)
- Extended commit message to explain System Controller and purpose of
  `has_sysctrl` flag
---
 drivers/gpu/drm/xe/xe_device_types.h  |  6 +++++
 drivers/gpu/drm/xe/xe_pci_types.h     |  1 +
 drivers/gpu/drm/xe/xe_sysctrl_types.h | 32 +++++++++++++++++++++++++++
 3 files changed, 39 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 3e04e80e0815..2990c1e76687 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -27,6 +27,7 @@
 #include "xe_sriov_vf_ccs_types.h"
 #include "xe_step_types.h"
 #include "xe_survivability_mode_types.h"
+#include "xe_sysctrl_types.h"
 #include "xe_tile_types.h"
 #include "xe_validation.h"
 
@@ -206,6 +207,8 @@ struct xe_device {
 		u8 has_soc_remapper_telem:1;
 		/** @info.has_sriov: Supports SR-IOV */
 		u8 has_sriov:1;
+		/** @info.has_sysctrl: Supports System Controller */
+		u8 has_sysctrl:1;
 		/** @info.has_usm: Device has unified shared memory support */
 		u8 has_usm:1;
 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
@@ -518,6 +521,9 @@ struct xe_device {
 	/** @i2c: I2C host controller */
 	struct xe_i2c *i2c;
 
+	/** @sc: System Controller */
+	struct xe_sysctrl sc;
+
 	/** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */
 	u32 atomic_svm_timeslice_ms;
 
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 8eee4fb1c57c..08386c5eca27 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -57,6 +57,7 @@ struct xe_device_desc {
 	u8 has_soc_remapper_sysctrl:1;
 	u8 has_soc_remapper_telem:1;
 	u8 has_sriov:1;
+	u8 has_sysctrl:1;
 	u8 needs_scratch:1;
 	u8 skip_guc_pc:1;
 	u8 skip_mtcfg:1;
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
new file mode 100644
index 000000000000..8217f6befe70
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_TYPES_H_
+#define _XE_SYSCTRL_TYPES_H_
+
+#include <linux/mutex.h>
+#include <linux/types.h>
+
+struct xe_mmio;
+
+/**
+ * struct xe_sysctrl - System Controller driver context
+ *
+ * This structure maintains the runtime state for System Controller
+ * communication. All fields are initialized during xe_sysctrl_init()
+ * and protected appropriately for concurrent access.
+ */
+struct xe_sysctrl {
+	/** @mmio: MMIO region for system control registers */
+	struct xe_mmio *mmio;
+
+	/** @cmd_lock: Mutex protecting mailbox command operations */
+	struct mutex cmd_lock;
+
+	/** @phase_bit: Message boundary phase toggle bit (0 or 1) */
+	bool phase_bit;
+};
+
+#endif
-- 
2.43.0

Re: [PATCH v9 1/6] drm/xe/sysctrl: Add System Controller types and device integration

[Umesh Nerlige Ramappa]

On Tue, Mar 10, 2026 at 11:23:20AM -0700, Anoop, Vijay wrote:
>From: Anoop Vijay <anoop.c.vijay@intel.com>
>
>Add foundational type definitions for System Controller (sysctrl)
>support and integrate them into xe_device structure. Also add a
> capability flag to device descriptor and runtime
>info.

To me, the below 2 paras look complete for this commit. The above para 
can be dropped.

>
>System Controller is a separate management entity responsible for
>certain platform-level control and coordination tasks in Intel Xe3p
>dGPU platforms. Driver communicates with it via a mailbox interface
>using SCHI (System Controller Host Interface) protocol for operations
>delegated to this controller.
>
>This commit introduces core data structures required for sysctrl
>support, including MMIO region, command mutex, and phase bit used
>by SCHI protocol.  flag explicitly records presence of

has_sysctrl flah explicitly ...

>sysctrl hardware on supported platforms.
>
>No functional changes. This is preparatory infrastructure for System
>Controller support.

This sentence can be dropped.

>
>Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>

The commit message needs cleanup. With that this is

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Thanks,
Umesh

>---
>v4: (Matt, Mike)
>- Add domain-specific MMIO accessor
>- Change phase_bit type from u32 to bool
>
>v6: (Matt)
>- Add mailbox protocol constants
>
>v8: (Matt, Michal)
>- Reordered patches for logical flow
>
>v9: (Matt)
>- Extended commit message to explain System Controller and purpose of
>  `has_sysctrl` flag
>---
> drivers/gpu/drm/xe/xe_device_types.h  |  6 +++++
> drivers/gpu/drm/xe/xe_pci_types.h     |  1 +
> drivers/gpu/drm/xe/xe_sysctrl_types.h | 32 +++++++++++++++++++++++++++
> 3 files changed, 39 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h
>
>diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>index 3e04e80e0815..2990c1e76687 100644
>--- a/drivers/gpu/drm/xe/xe_device_types.h
>+++ b/drivers/gpu/drm/xe/xe_device_types.h
>@@ -27,6 +27,7 @@
> #include "xe_sriov_vf_ccs_types.h"
> #include "xe_step_types.h"
> #include "xe_survivability_mode_types.h"
>+#include "xe_sysctrl_types.h"
> #include "xe_tile_types.h"
> #include "xe_validation.h"
>
>@@ -206,6 +207,8 @@ struct xe_device {
> 		u8 has_soc_remapper_telem:1;
> 		/** @info.has_sriov: Supports SR-IOV */
> 		u8 has_sriov:1;
>+		/** @info.has_sysctrl: Supports System Controller */
>+		u8 has_sysctrl:1;
> 		/** @info.has_usm: Device has unified shared memory support */
> 		u8 has_usm:1;
> 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
>@@ -518,6 +521,9 @@ struct xe_device {
> 	/** @i2c: I2C host controller */
> 	struct xe_i2c *i2c;
>
>+	/** @sc: System Controller */
>+	struct xe_sysctrl sc;
>+
> 	/** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */
> 	u32 atomic_svm_timeslice_ms;
>
>diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>index 8eee4fb1c57c..08386c5eca27 100644
>--- a/drivers/gpu/drm/xe/xe_pci_types.h
>+++ b/drivers/gpu/drm/xe/xe_pci_types.h
>@@ -57,6 +57,7 @@ struct xe_device_desc {
> 	u8 has_soc_remapper_sysctrl:1;
> 	u8 has_soc_remapper_telem:1;
> 	u8 has_sriov:1;
>+	u8 has_sysctrl:1;
> 	u8 needs_scratch:1;
> 	u8 skip_guc_pc:1;
> 	u8 skip_mtcfg:1;
>diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
>new file mode 100644
>index 000000000000..8217f6befe70
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
>@@ -0,0 +1,32 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2026 Intel Corporation
>+ */
>+
>+#ifndef _XE_SYSCTRL_TYPES_H_
>+#define _XE_SYSCTRL_TYPES_H_
>+
>+#include <linux/mutex.h>
>+#include <linux/types.h>
>+
>+struct xe_mmio;
>+
>+/**
>+ * struct xe_sysctrl - System Controller driver context
>+ *
>+ * This structure maintains the runtime state for System Controller
>+ * communication. All fields are initialized during xe_sysctrl_init()
>+ * and protected appropriately for concurrent access.
>+ */
>+struct xe_sysctrl {
>+	/** @mmio: MMIO region for system control registers */
>+	struct xe_mmio *mmio;
>+
>+	/** @cmd_lock: Mutex protecting mailbox command operations */
>+	struct mutex cmd_lock;
>+
>+	/** @phase_bit: Message boundary phase toggle bit (0 or 1) */
>+	bool phase_bit;
>+};
>+
>+#endif
>-- 
>2.43.0
>

[PATCH v9 2/6] drm/xe/sysctrl: Add System Controller register definitions

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Add register definitions for System Controller mailbox interface:
- Control and data registers
- Protocol frame control fields
- Base address and BAR configuration

No functional changes, just register definitions.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
v4: (Matt)
- Use lowercase hex values
- Align macro definitions to column 49
- Change to relative register offsets

v6: (Matt)
- Move protocol constants to xe_sysctrl_mailbox_types.h
- Add SYSCTRL_MB_CTRL_MKHI_CMD helper macro

v9: (Umesh, Badal)
- Normalized hexadecimal literal casing
- Renamed MKHI to SCHI (System Controller Host Interface)
---
 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h | 36 +++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h

diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
new file mode 100644
index 000000000000..30dd78780ea9
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_REGS_H_
+#define _XE_SYSCTRL_REGS_H_
+
+#include "xe_regs.h"
+
+#define SYSCTRL_BASE_OFFSET			0xdb000
+#define SYSCTRL_BASE				(SOC_BASE + SYSCTRL_BASE_OFFSET)
+#define SYSCTRL_MAILBOX_INDEX			0x03
+#define SYSCTRL_BAR_LENGTH			0x1000
+
+#define SYSCTRL_MB_CTRL				XE_REG(0x10)
+#define   SYSCTRL_MB_CTRL_RUN_BUSY		REG_BIT(31)
+#define   SYSCTRL_MB_CTRL_IRQ			REG_BIT(30)
+#define   SYSCTRL_MB_CTRL_RUN_BUSY_OUT		REG_BIT(29)
+#define   SYSCTRL_MB_CTRL_PARAM3_MASK		REG_GENMASK(28, 24)
+#define   SYSCTRL_MB_CTRL_PARAM2_MASK		REG_GENMASK(23, 16)
+#define   SYSCTRL_MB_CTRL_PARAM1_MASK		REG_GENMASK(15, 8)
+#define   SYSCTRL_MB_CTRL_COMMAND_MASK		REG_GENMASK(7, 0)
+#define   SYSCTRL_MB_CTRL_SCHI_CMD		REG_FIELD_PREP(SYSCTRL_MB_CTRL_COMMAND_MASK, 5)
+
+#define SYSCTRL_MB_DATA0			XE_REG(0x14)
+#define SYSCTRL_MB_DATA1			XE_REG(0x18)
+#define SYSCTRL_MB_DATA2			XE_REG(0x1c)
+#define SYSCTRL_MB_DATA3			XE_REG(0x20)
+
+#define SCHI_FRAME_PHASE			REG_BIT(24)
+#define SCHI_FRAME_CURRENT_MASK			REG_GENMASK(21, 16)
+#define SCHI_FRAME_TOTAL_MASK			REG_GENMASK(13, 8)
+#define SCHI_FRAME_COMMAND_MASK			REG_GENMASK(7, 0)
+
+#endif
-- 
2.43.0

[PATCH v9 3/6] drm/xe/sysctrl: Add mailbox communication headers

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Add ABI definitions, mailbox API, and command structures for
System Controller communication.

No functional code yet. Only protocol layer definitions are added.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
---
v8: (Matt, Michal)
- Reordered patches for logical flow
- Moved ABI definitions to dedicated header

v9: (Badal)
- Renamed MKHI to SCHI (System Controller Host Interface)
---

 drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h       | 31 ++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h       | 31 ++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 35 +++++++++++++++++++
 3 files changed, 97 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h

diff --git a/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
new file mode 100644
index 000000000000..bc4793fb21e5
--- /dev/null
+++ b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_ABI_H_
+#define _XE_SYSCTRL_ABI_H_
+
+#include <linux/types.h>
+
+struct xe_sysctrl_mailbox_schi_msg_hdr {
+	__le32 data;
+} __packed;
+
+struct xe_sysctrl_app_msg_hdr {
+	__le32 data;
+} __packed;
+
+#define SCHI_HDR_GROUP_ID_MASK		GENMASK(7, 0)
+#define SCHI_HDR_COMMAND_MASK		GENMASK(14, 8)
+#define SCHI_HDR_COMMAND_MAX		0x7f
+#define SCHI_HDR_IS_RESPONSE		BIT(15)
+#define SCHI_HDR_RESERVED_MASK		GENMASK(23, 16)
+#define SCHI_HDR_RESULT_MASK		GENMASK(31, 24)
+
+#define APP_HDR_GROUP_ID_MASK		GENMASK(7, 0)
+#define APP_HDR_COMMAND_MASK		GENMASK(15, 8)
+#define APP_HDR_VERSION_MASK		GENMASK(23, 16)
+#define APP_HDR_RESERVED_MASK		GENMASK(31, 24)
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
new file mode 100644
index 000000000000..91460be9e22c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_MAILBOX_H_
+#define _XE_SYSCTRL_MAILBOX_H_
+
+#include <linux/bitfield.h>
+#include <linux/types.h>
+
+#include "abi/xe_sysctrl_abi.h"
+
+struct xe_sysctrl;
+struct xe_sysctrl_mailbox_command;
+
+#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr) \
+	FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_APP_HDR_COMMAND(hdr) \
+	FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
+	FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
+
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
+int xe_sysctrl_send_command(struct xe_sysctrl *sc,
+			    struct xe_sysctrl_mailbox_command *cmd,
+			    size_t *rdata_len);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
new file mode 100644
index 000000000000..fdf8d1d4e3cd
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_MAILBOX_TYPES_H_
+#define _XE_SYSCTRL_MAILBOX_TYPES_H_
+
+#include <linux/types.h>
+
+#include "abi/xe_sysctrl_abi.h"
+
+/**
+ * struct xe_sysctrl_mailbox_command - System Controller mailbox command
+ */
+struct xe_sysctrl_mailbox_command {
+	/** @header: Application message header containing command information */
+	struct xe_sysctrl_app_msg_hdr header;
+	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
+	void *data_in;
+	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
+	size_t data_in_len;
+	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
+	void *data_out;
+	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
+	size_t data_out_len;
+};
+
+#define XE_SYSCTRL_MB_FRAME_SIZE	16
+#define XE_SYSCTRL_MB_MAX_FRAMES	64
+#define XE_SYSCTRL_MB_MAX_MESSAGE_SIZE	(XE_SYSCTRL_MB_FRAME_SIZE * XE_SYSCTRL_MB_MAX_FRAMES)
+
+#define XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS	500
+
+#endif
-- 
2.43.0

Re: [PATCH v9 3/6] drm/xe/sysctrl: Add mailbox communication headers

[Riana Tauro]

Hi Anoop

On 3/10/2026 11:53 PM, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> Add ABI definitions, mailbox API, and command structures for
> System Controller communication.
> 
> No functional code yet. Only protocol layer definitions are added.
> 
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> ---
> v8: (Matt, Michal)
> - Reordered patches for logical flow
> - Moved ABI definitions to dedicated header
> 
> v9: (Badal)
> - Renamed MKHI to SCHI (System Controller Host Interface)
> ---
> 
>   drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h       | 31 ++++++++++++++++
>   drivers/gpu/drm/xe/xe_sysctrl_mailbox.h       | 31 ++++++++++++++++
>   drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 35 +++++++++++++++++++
>   3 files changed, 97 insertions(+)
>   create mode 100644 drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> 
> diff --git a/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
> new file mode 100644
> index 000000000000..bc4793fb21e5
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_ABI_H_
> +#define _XE_SYSCTRL_ABI_H_
> +
> +#include <linux/types.h>
> +

Add documentation. Anyone not seeing the version history will not know 
what SCHI is.

What is the reason of using SCHI? why not just mailbox_msg_hdr?

> +struct xe_sysctrl_mailbox_schi_msg_hdr {
> +	__le32 data;
> +} __packed;
> +

I don't see this getting used outside sysctrl file. Will there be any
users for this else move it to .c

> +struct xe_sysctrl_app_msg_hdr {
> +	__le32 data;
> +} __packed;
> +

This should be u32. Any conversions should be done in sc_send_command
not by upper layer.

> +#define SCHI_HDR_GROUP_ID_MASK		GENMASK(7, 0)
> +#define SCHI_HDR_COMMAND_MASK		GENMASK(14, 8)
> +#define SCHI_HDR_COMMAND_MAX		0x7f
> +#define SCHI_HDR_IS_RESPONSE		BIT(15)
> +#define SCHI_HDR_RESERVED_MASK		GENMASK(23, 16)
> +#define SCHI_HDR_RESULT_MASK		GENMASK(31, 24)
> +
> +#define APP_HDR_GROUP_ID_MASK		GENMASK(7, 0)
> +#define APP_HDR_COMMAND_MASK		GENMASK(15, 8)
> +#define APP_HDR_VERSION_MASK		GENMASK(23, 16)
> +#define APP_HDR_RESERVED_MASK		GENMASK(31, 24)
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> new file mode 100644
> index 000000000000..91460be9e22c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_MAILBOX_H_
> +#define _XE_SYSCTRL_MAILBOX_H_
> +
> +#include <linux/bitfield.h>
> +#include <linux/types.h>
> +
> +#include "abi/xe_sysctrl_abi.h"
> +
> +struct xe_sysctrl;
> +struct xe_sysctrl_mailbox_command;
> +
> +#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr) \
> +	FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
> +
> +#define XE_SYSCTRL_APP_HDR_COMMAND(hdr) \
> +	FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
> +
> +#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> +	FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
> +
> +void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> +int xe_sysctrl_send_command(struct xe_sysctrl *sc,
> +			    struct xe_sysctrl_mailbox_command *cmd,
> +			    size_t *rdata_len);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> new file mode 100644
> index 000000000000..fdf8d1d4e3cd
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_MAILBOX_TYPES_H_
> +#define _XE_SYSCTRL_MAILBOX_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#include "abi/xe_sysctrl_abi.h"
> +
> +/**
> + * struct xe_sysctrl_mailbox_command - System Controller mailbox command
> + */
> +struct xe_sysctrl_mailbox_command {
> +	/** @header: Application message header containing command information */
> +	struct xe_sysctrl_app_msg_hdr header;
> +	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
> +	void *data_in;
> +	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
> +	size_t data_in_len;
> +	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
> +	void *data_out;
> +	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
> +	size_t data_out_len;
> +};
> +
> +#define XE_SYSCTRL_MB_FRAME_SIZE	16
> +#define XE_SYSCTRL_MB_MAX_FRAMES	64
> +#define XE_SYSCTRL_MB_MAX_MESSAGE_SIZE	(XE_SYSCTRL_MB_FRAME_SIZE * XE_SYSCTRL_MB_MAX_FRAMES)

Maybe use another tab and keep the macros aligned
Also if these are unused by other layers, define it in .c

Thanks
Riana

> +
> +#define XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS	500
> +
> +#endif

Re: [PATCH v9 3/6] drm/xe/sysctrl: Add mailbox communication headers

[Nilawar, Badal]

[-- Attachment #1: Type: text/plain, Size: 295 bytes --]


On 11-03-2026 12:59, Riana Tauro wrote:
> What is the reason of using SCHI? why not just mailbox_msg_hdr?

Agree, no need to introduce new term, just xe_sysctrl_mailbox_msg_hdr is 
fine.

Thanks,
Badal

>
>> +struct xe_sysctrl_mailbox_schi_msg_hdr {
>> +    __le32 data;
>> +} __packed;
>> +

[-- Attachment #2: Type: text/html, Size: 921 bytes --]

[PATCH v9 4/6] drm/xe/sysctrl: Add System Controller initialization

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Add initialization infrastructure for System Controller subsystem:
- xe_sysctrl_init() and cleanup handler
- Integration into xe_device_probe()
- Makefile build inclusion

Initialization flow will check platform support via has_sysctrl flag and
configure mailbox region through SOC remapper interface

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
v8: (Matt, Michal, Shuicheng)
- Fixed include order
- Added VF check
- Converted runtime checks to assertions
- Added sc_to_xe() helper
- Fixed kernel-doc syntax
---
 drivers/gpu/drm/xe/Makefile     |  1 +
 drivers/gpu/drm/xe/xe_device.c  |  5 ++
 drivers/gpu/drm/xe/xe_sysctrl.c | 82 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl.h | 21 +++++++++
 4 files changed, 109 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index f63fdf80055a..76a86818986a 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -123,6 +123,7 @@ xe-y += xe_bb.o \
 	xe_step.o \
 	xe_survivability_mode.o \
 	xe_sync.o \
+	xe_sysctrl.o \
 	xe_tile.o \
 	xe_tile_sysfs.o \
 	xe_tlb_inval.o \
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index e77a3a3db73d..c70d4ae413a9 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -65,6 +65,7 @@
 #include "xe_survivability_mode.h"
 #include "xe_sriov.h"
 #include "xe_svm.h"
+#include "xe_sysctrl.h"
 #include "xe_tile.h"
 #include "xe_ttm_stolen_mgr.h"
 #include "xe_ttm_sys_mgr.h"
@@ -985,6 +986,10 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		goto err_unregister_display;
 
+	err = xe_sysctrl_init(xe);
+	if (err)
+		goto err_unregister_display;
+
 	err = xe_device_sysfs_init(xe);
 	if (err)
 		goto err_unregister_display;
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
new file mode 100644
index 000000000000..2751fe25a6ff
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/device.h>
+#include <linux/mutex.h>
+
+#include <drm/drm_managed.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_assert.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+#include "xe_printk.h"
+#include "xe_soc_remapper.h"
+#include "xe_sriov.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_types.h"
+
+/**
+ * DOC: System Controller (sysctrl)
+ *
+ * The System Controller (sysctrl) is an embedded microcontroller in Intel GPUs
+ * responsible for managing various low-level platform functions. Communication
+ * between the driver and the System Controller occurs via a mailbox interface,
+ * enabling the exchange of commands and responses.
+ *
+ * This module provides initialization routines and helper functions to interact
+ * with the System Controller through the mailbox.
+ */
+static void sysctrl_fini(void *arg)
+{
+	struct xe_device *xe = arg;
+
+	xe->soc_remapper.set_sysctrl_region(xe, 0);
+}
+
+/**
+ * xe_sysctrl_init() - Initialize System Controller subsystem
+ * @xe: xe device instance
+ *
+ * Entry point for System Controller initialization, called from xe_device_probe.
+ * This function checks platform support and initializes the system controller.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_sysctrl_init(struct xe_device *xe)
+{
+	struct xe_tile *tile = xe_device_get_root_tile(xe);
+	struct xe_sysctrl *sc = &xe->sc;
+	int ret;
+
+	if (!xe->info.has_sysctrl)
+		return 0;
+
+	if (IS_SRIOV_VF(xe))
+		return 0;
+
+	xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
+
+	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
+
+	ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
+	if (ret)
+		return ret;
+
+	sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
+	if (!sc->mmio)
+		return -ENOMEM;
+
+	xe_mmio_init(sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
+	sc->mmio->adj_offset = SYSCTRL_BASE;
+	sc->mmio->adj_limit = U32_MAX;
+
+	ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
new file mode 100644
index 000000000000..d5d8735038ae
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_H_
+#define _XE_SYSCTRL_H_
+
+#include <linux/container_of.h>
+
+#include "xe_device_types.h"
+#include "xe_sysctrl_types.h"
+
+static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
+{
+	return container_of(sc, struct xe_device, sc);
+}
+
+int xe_sysctrl_init(struct xe_device *xe);
+
+#endif
-- 
2.43.0

RE: [PATCH v9 4/6] drm/xe/sysctrl: Add System Controller initialization

[Gupta, Anshuman]

> -----Original Message-----
> From: Vijay, Anoop C <anoop.c.vijay@intel.com>
> Sent: Tuesday, March 10, 2026 11:53 PM
> To: intel-xe@lists.freedesktop.org
> Cc: Nerlige Ramappa, Umesh <umesh.nerlige.ramappa@intel.com>; Nilawar,
> Badal <badal.nilawar@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> Iddamsetty, Aravind <aravind.iddamsetty@intel.com>; Tauro, Riana
> <riana.tauro@intel.com>; Gupta, Anshuman <anshuman.gupta@intel.com>;
> Roper, Matthew D <matthew.d.roper@intel.com>; Ruhl, Michael J
> <michael.j.ruhl@intel.com>; Luse, Paul E <paul.e.luse@intel.com>; V,
> Mohamed Mansoor <mohamed.mansoor.v@intel.com>; Nasim, Kam
> <kam.nasim@intel.com>; Vijay, Anoop C <anoop.c.vijay@intel.com>
> Subject: [PATCH v9 4/6] drm/xe/sysctrl: Add System Controller initialization
> 
> From: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> Add initialization infrastructure for System Controller subsystem:
> - xe_sysctrl_init() and cleanup handler
> - Integration into xe_device_probe()
> - Makefile build inclusion
> 
> Initialization flow will check platform support via has_sysctrl flag and configure
> mailbox region through SOC remapper interface
> 
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> v8: (Matt, Michal, Shuicheng)
> - Fixed include order
> - Added VF check
> - Converted runtime checks to assertions
> - Added sc_to_xe() helper
> - Fixed kernel-doc syntax
> ---
>  drivers/gpu/drm/xe/Makefile     |  1 +
>  drivers/gpu/drm/xe/xe_device.c  |  5 ++  drivers/gpu/drm/xe/xe_sysctrl.c | 82
> +++++++++++++++++++++++++++++++++  drivers/gpu/drm/xe/xe_sysctrl.h | 21
> +++++++++
>  4 files changed, 109 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c  create mode 100644
> drivers/gpu/drm/xe/xe_sysctrl.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index
> f63fdf80055a..76a86818986a 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -123,6 +123,7 @@ xe-y += xe_bb.o \
>  	xe_step.o \
>  	xe_survivability_mode.o \
>  	xe_sync.o \
> +	xe_sysctrl.o \
>  	xe_tile.o \
>  	xe_tile_sysfs.o \
>  	xe_tlb_inval.o \
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index e77a3a3db73d..c70d4ae413a9 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -65,6 +65,7 @@
>  #include "xe_survivability_mode.h"
>  #include "xe_sriov.h"
>  #include "xe_svm.h"
> +#include "xe_sysctrl.h"
>  #include "xe_tile.h"
>  #include "xe_ttm_stolen_mgr.h"
>  #include "xe_ttm_sys_mgr.h"
> @@ -985,6 +986,10 @@ int xe_device_probe(struct xe_device *xe)
>  	if (err)
>  		goto err_unregister_display;
> 
> +	err = xe_sysctrl_init(xe);
> +	if (err)
> +		goto err_unregister_display;
> +
>  	err = xe_device_sysfs_init(xe);
>  	if (err)
>  		goto err_unregister_display;
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> new file mode 100644 index 000000000000..2751fe25a6ff
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <linux/device.h>
> +#include <linux/mutex.h>
> +
> +#include <drm/drm_managed.h>
> +
> +#include "regs/xe_sysctrl_regs.h"
> +#include "xe_assert.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +#include "xe_printk.h"
> +#include "xe_soc_remapper.h"
> +#include "xe_sriov.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_mailbox.h"
> +#include "xe_sysctrl_types.h"
> +
> +/**
> + * DOC: System Controller (sysctrl)
> + *
> + * The System Controller (sysctrl) is an embedded microcontroller in
> +Intel GPUs
Nitpick , it should be intel dGPU
> + * responsible for managing various low-level platform functions.
> +Communication
> + * between the driver and the System Controller occurs via a mailbox
> +interface,
> + * enabling the exchange of commands and responses.
> + *
> + * This module provides initialization routines and helper functions to
> +interact
> + * with the System Controller through the mailbox.
> + */
> +static void sysctrl_fini(void *arg)
> +{
> +	struct xe_device *xe = arg;
> +
> +	xe->soc_remapper.set_sysctrl_region(xe, 0); }
> +
> +/**
> + * xe_sysctrl_init() - Initialize System Controller subsystem
> + * @xe: xe device instance
> + *
> + * Entry point for System Controller initialization, called from
> xe_device_probe.
> + * This function checks platform support and initializes the system controller.
> + *
> + * Return: 0 on success, error code on failure  */ int
> +xe_sysctrl_init(struct xe_device *xe) {
> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> +	struct xe_sysctrl *sc = &xe->sc;
> +	int ret;
> +
> +	if (!xe->info.has_sysctrl)
> +		return 0;
> +
> +	if (IS_SRIOV_VF(xe))
> +		return 0;
> +
> +	xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
> +
> +	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> +
> +	ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> +	if (ret)
> +		return ret;
> +
> +	sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio),
> GFP_KERNEL);
> +	if (!sc->mmio)
> +		return -ENOMEM;
> +
> +	xe_mmio_init(sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
> +	sc->mmio->adj_offset = SYSCTRL_BASE;
> +	sc->mmio->adj_limit = U32_MAX;
> +
> +	ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> new file mode 100644 index 000000000000..d5d8735038ae
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_H_
> +#define _XE_SYSCTRL_H_
> +
> +#include <linux/container_of.h>
> +
> +#include "xe_device_types.h"
> +#include "xe_sysctrl_types.h"
> +
> +static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc) {
> +	return container_of(sc, struct xe_device, sc); }
> +
> +int xe_sysctrl_init(struct xe_device *xe);
> +
> +#endif
> --
> 2.43.0

Re: [PATCH v9 4/6] drm/xe/sysctrl: Add System Controller initialization

[Riana Tauro]

On 3/10/2026 11:53 PM, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> Add initialization infrastructure for System Controller subsystem:
> - xe_sysctrl_init() and cleanup handler
> - Integration into xe_device_probe()
> - Makefile build inclusion

The description should be a brief of what the patch is.
Mentioning 'makefile inclusions' is unnecessary

> 
> Initialization flow will check platform support via has_sysctrl flag and
> configure mailbox region through SOC remapper interface

punctuation..

> 
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> v8: (Matt, Michal, Shuicheng)
> - Fixed include order
> - Added VF check
> - Converted runtime checks to assertions
> - Added sc_to_xe() helper
> - Fixed kernel-doc syntax
> ---
>   drivers/gpu/drm/xe/Makefile     |  1 +
>   drivers/gpu/drm/xe/xe_device.c  |  5 ++
>   drivers/gpu/drm/xe/xe_sysctrl.c | 82 +++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_sysctrl.h | 21 +++++++++
>   4 files changed, 109 insertions(+)
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index f63fdf80055a..76a86818986a 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -123,6 +123,7 @@ xe-y += xe_bb.o \
>   	xe_step.o \
>   	xe_survivability_mode.o \
>   	xe_sync.o \
> +	xe_sysctrl.o \
>   	xe_tile.o \
>   	xe_tile_sysfs.o \
>   	xe_tlb_inval.o \
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index e77a3a3db73d..c70d4ae413a9 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -65,6 +65,7 @@
>   #include "xe_survivability_mode.h"
>   #include "xe_sriov.h"
>   #include "xe_svm.h"
> +#include "xe_sysctrl.h"
>   #include "xe_tile.h"
>   #include "xe_ttm_stolen_mgr.h"
>   #include "xe_ttm_sys_mgr.h"
> @@ -985,6 +986,10 @@ int xe_device_probe(struct xe_device *xe)
>   	if (err)
>   		goto err_unregister_display;
>   
> +	err = xe_sysctrl_init(xe);
> +	if (err)
> +		goto err_unregister_display;
> +
>   	err = xe_device_sysfs_init(xe);
>   	if (err)
>   		goto err_unregister_display;
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> new file mode 100644
> index 000000000000..2751fe25a6ff
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <linux/device.h>
> +#include <linux/mutex.h>
> +
> +#include <drm/drm_managed.h>
> +
> +#include "regs/xe_sysctrl_regs.h"
> +#include "xe_assert.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +#include "xe_printk.h"
> +#include "xe_soc_remapper.h"
> +#include "xe_sriov.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_mailbox.h"
> +#include "xe_sysctrl_types.h"
> +
> +/**
> + * DOC: System Controller (sysctrl)
> + *
> + * The System Controller (sysctrl) is an embedded microcontroller in Intel GPUs
> + * responsible for managing various low-level platform functions. Communication
> + * between the driver and the System Controller occurs via a mailbox interface,
> + * enabling the exchange of commands and responses.
> + *
> + * This module provides initialization routines and helper functions to interact
> + * with the System Controller through the mailbox.
> + */
> +static void sysctrl_fini(void *arg)
> +{
> +	struct xe_device *xe = arg;
> +
> +	xe->soc_remapper.set_sysctrl_region(xe, 0);
> +}
> +
> +/**
> + * xe_sysctrl_init() - Initialize System Controller subsystem
> + * @xe: xe device instance
> + *
> + * Entry point for System Controller initialization, called from xe_device_probe.

How about suspend/resume?

> + * This function checks platform support and initializes the system controller.
> + *
> + * Return: 0 on success, error code on failure
> + */
> +int xe_sysctrl_init(struct xe_device *xe)
> +{
> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> +	struct xe_sysctrl *sc = &xe->sc;
> +	int ret;
> +
> +	if (!xe->info.has_sysctrl)
> +		return 0;
> +
> +	if (IS_SRIOV_VF(xe))
> +		return 0;
> +
> +	xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
> +
> +	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> +
> +	ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> +	if (ret)
> +		return ret;
> +
> +	sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
> +	if (!sc->mmio)
> +		return -ENOMEM;
> +
> +	xe_mmio_init(sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
> +	sc->mmio->adj_offset = SYSCTRL_BASE;
> +	sc->mmio->adj_limit = U32_MAX;
> +
> +	ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);

Let's use devm or drmm. Not a mix of both.
Sc is specific to device so devm would be appropriate.

Thanks
Riana

> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> new file mode 100644
> index 000000000000..d5d8735038ae
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_H_
> +#define _XE_SYSCTRL_H_
> +
> +#include <linux/container_of.h>
> +
> +#include "xe_device_types.h"
> +#include "xe_sysctrl_types.h"
> +
> +static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> +{
> +	return container_of(sc, struct xe_device, sc);
> +}
> +
> +int xe_sysctrl_init(struct xe_device *xe);
> +
> +#endif

Re: [PATCH v9 4/6] drm/xe/sysctrl: Add System Controller initialization

[Umesh Nerlige Ramappa]

On Wed, Mar 11, 2026 at 04:29:58PM +0530, Riana Tauro wrote:
>
>
>On 3/10/2026 11:53 PM, Anoop, Vijay wrote:
>>From: Anoop Vijay <anoop.c.vijay@intel.com>
>>
>>Add initialization infrastructure for System Controller subsystem:
>>- xe_sysctrl_init() and cleanup handler
>>- Integration into xe_device_probe()
>>- Makefile build inclusion
>
>The description should be a brief of what the patch is.
>Mentioning 'makefile inclusions' is unnecessary
>
>>
>>Initialization flow will check platform support via has_sysctrl flag and
>>configure mailbox region through SOC remapper interface
>
>punctuation..
>
>>
>>Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
>>Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>---
>>v8: (Matt, Michal, Shuicheng)
>>- Fixed include order
>>- Added VF check
>>- Converted runtime checks to assertions
>>- Added sc_to_xe() helper
>>- Fixed kernel-doc syntax
>>---
>>  drivers/gpu/drm/xe/Makefile     |  1 +
>>  drivers/gpu/drm/xe/xe_device.c  |  5 ++
>>  drivers/gpu/drm/xe/xe_sysctrl.c | 82 +++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/xe/xe_sysctrl.h | 21 +++++++++
>>  4 files changed, 109 insertions(+)
>>  create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
>>  create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
>>
>>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>index f63fdf80055a..76a86818986a 100644
>>--- a/drivers/gpu/drm/xe/Makefile
>>+++ b/drivers/gpu/drm/xe/Makefile
>>@@ -123,6 +123,7 @@ xe-y += xe_bb.o \
>>  	xe_step.o \
>>  	xe_survivability_mode.o \
>>  	xe_sync.o \
>>+	xe_sysctrl.o \
>>  	xe_tile.o \
>>  	xe_tile_sysfs.o \
>>  	xe_tlb_inval.o \
>>diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>>index e77a3a3db73d..c70d4ae413a9 100644
>>--- a/drivers/gpu/drm/xe/xe_device.c
>>+++ b/drivers/gpu/drm/xe/xe_device.c
>>@@ -65,6 +65,7 @@
>>  #include "xe_survivability_mode.h"
>>  #include "xe_sriov.h"
>>  #include "xe_svm.h"
>>+#include "xe_sysctrl.h"
>>  #include "xe_tile.h"
>>  #include "xe_ttm_stolen_mgr.h"
>>  #include "xe_ttm_sys_mgr.h"
>>@@ -985,6 +986,10 @@ int xe_device_probe(struct xe_device *xe)
>>  	if (err)
>>  		goto err_unregister_display;
>>+	err = xe_sysctrl_init(xe);
>>+	if (err)
>>+		goto err_unregister_display;
>>+
>>  	err = xe_device_sysfs_init(xe);
>>  	if (err)
>>  		goto err_unregister_display;
>>diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
>>new file mode 100644
>>index 000000000000..2751fe25a6ff
>>--- /dev/null
>>+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
>>@@ -0,0 +1,82 @@
>>+// SPDX-License-Identifier: MIT
>>+/*
>>+ * Copyright © 2026 Intel Corporation
>>+ */
>>+
>>+#include <linux/device.h>
>>+#include <linux/mutex.h>
>>+
>>+#include <drm/drm_managed.h>
>>+
>>+#include "regs/xe_sysctrl_regs.h"
>>+#include "xe_assert.h"
>>+#include "xe_device.h"
>>+#include "xe_mmio.h"
>>+#include "xe_printk.h"
>>+#include "xe_soc_remapper.h"
>>+#include "xe_sriov.h"
>>+#include "xe_sysctrl.h"
>>+#include "xe_sysctrl_mailbox.h"
>>+#include "xe_sysctrl_types.h"
>>+
>>+/**
>>+ * DOC: System Controller (sysctrl)
>>+ *
>>+ * The System Controller (sysctrl) is an embedded microcontroller in Intel GPUs
>>+ * responsible for managing various low-level platform functions. Communication
>>+ * between the driver and the System Controller occurs via a mailbox interface,
>>+ * enabling the exchange of commands and responses.
>>+ *
>>+ * This module provides initialization routines and helper functions to interact
>>+ * with the System Controller through the mailbox.
>>+ */
>>+static void sysctrl_fini(void *arg)
>>+{
>>+	struct xe_device *xe = arg;
>>+
>>+	xe->soc_remapper.set_sysctrl_region(xe, 0);
>>+}
>>+
>>+/**
>>+ * xe_sysctrl_init() - Initialize System Controller subsystem
>>+ * @xe: xe device instance
>>+ *
>>+ * Entry point for System Controller initialization, called from xe_device_probe.
>
>How about suspend/resume?
>

Right, forgot about that, thanks for catching that. Suspend/resume is no 
longer handled within SoC remapper. It must be handled by the user. The 
telemetry user does not need it since each access to the registers is 
preceded by soc remapper configuration.

In system controller, that's not the case, so we should add hooks to 
suspend/resume to reconfigure the SoC remapper.

Regards,
Umesh
>>+ * This function checks platform support and initializes the system controller.
>>+ *
>>+ * Return: 0 on success, error code on failure
>>+ */
>>+int xe_sysctrl_init(struct xe_device *xe)
>>+{
>>+	struct xe_tile *tile = xe_device_get_root_tile(xe);
>>+	struct xe_sysctrl *sc = &xe->sc;
>>+	int ret;
>>+
>>+	if (!xe->info.has_sysctrl)
>>+		return 0;
>>+
>>+	if (IS_SRIOV_VF(xe))
>>+		return 0;
>>+
>>+	xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
>>+
>>+	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
>>+
>>+	ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
>>+	if (ret)
>>+		return ret;
>>+
>>+	sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
>>+	if (!sc->mmio)
>>+		return -ENOMEM;
>>+
>>+	xe_mmio_init(sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
>>+	sc->mmio->adj_offset = SYSCTRL_BASE;
>>+	sc->mmio->adj_limit = U32_MAX;
>>+
>>+	ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);
>
>Let's use devm or drmm. Not a mix of both.
>Sc is specific to device so devm would be appropriate.
>
>Thanks
>Riana
>
>>+	if (ret)
>>+		return ret;
>>+
>>+	return 0;
>>+}
>>diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
>>new file mode 100644
>>index 000000000000..d5d8735038ae
>>--- /dev/null
>>+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
>>@@ -0,0 +1,21 @@
>>+/* SPDX-License-Identifier: MIT */
>>+/*
>>+ * Copyright © 2026 Intel Corporation
>>+ */
>>+
>>+#ifndef _XE_SYSCTRL_H_
>>+#define _XE_SYSCTRL_H_
>>+
>>+#include <linux/container_of.h>
>>+
>>+#include "xe_device_types.h"
>>+#include "xe_sysctrl_types.h"
>>+
>>+static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
>>+{
>>+	return container_of(sc, struct xe_device, sc);
>>+}
>>+
>>+int xe_sysctrl_init(struct xe_device *xe);
>>+
>>+#endif
>

[PATCH v9 5/6] drm/xe/sysctrl: Add mailbox communication implementation

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Adding mailbox communication layer for System Controller
interaction. The mailbox interface enables sending commands and
receiving responses from embedded System Controller.

Key features:
- Command/response protocol handling
- Timeout and error management
- Uses protocol headers defined in ABI

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
v4: (Matt, Mike)
- Refactor MMIO access to use domain-specific accessor
- Add input validation and buffer overflow protection
- Add bounds checking for multi-frame operations
- Fix potential NULL pointer dereference

v5: (Umesh, Riana)
- Reset phase bit to 0 on error conditions
- Refactor mailbox receive path
- Updated xe_err messages for consistency

v6: (Matt)
- Use SYSCTRL_MB_CTRL_MKHI_CMD macro instead of FIELD_PREP

v8: (Matt, Michal)
- Reordered patches for logical flow
- Static functions renamed with short prefix
- Changed xe_sysctrl_send_command() function parameter from 'xe' to 'sc'
- Added frame length validation and command overflow protection
- Use REG_FIELD_PREP for hardware registers
- Changed error format to %pe
- Removed unnecessary NULL checks and explicit zeros
- Fixed kernel-doc syntax

v9: (Umesh, Badal)
- Renamed MKHI to SCHI (System Controller Host Interface)
- Fixed kernel-doc syntax
---

 drivers/gpu/drm/xe/Makefile             |   1 +
 drivers/gpu/drm/xe/xe_sysctrl.c         |   2 +
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c | 364 ++++++++++++++++++++++++
 3 files changed, 367 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 76a86818986a..7d13a3e43c9f 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -124,6 +124,7 @@ xe-y += xe_bb.o \
 	xe_survivability_mode.o \
 	xe_sync.o \
 	xe_sysctrl.o \
+	xe_sysctrl_mailbox.o \
 	xe_tile.o \
 	xe_tile_sysfs.o \
 	xe_tlb_inval.o \
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index 2751fe25a6ff..365f73ef680d 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -78,5 +78,7 @@ int xe_sysctrl_init(struct xe_device *xe)
 	if (ret)
 		return ret;
 
+	xe_sysctrl_mailbox_init(sc);
+
 	return 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
new file mode 100644
index 000000000000..b08885cf8dd5
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/container_of.h>
+#include <linux/errno.h>
+#include <linux/minmax.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_device.h"
+#include "xe_device_types.h"
+#include "xe_mmio.h"
+#include "xe_pm.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+#include "xe_sysctrl_types.h"
+
+#define XE_SYSCTRL_SCHI_HDR_GROUP_ID(hdr) \
+	FIELD_GET(SCHI_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_SCHI_HDR_COMMAND(hdr) \
+	FIELD_GET(SCHI_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_SCHI_HDR_IS_RESPONSE(hdr) \
+	FIELD_GET(SCHI_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_SCHI_HDR_RESULT(hdr) \
+	FIELD_GET(SCHI_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
+
+static bool sysctrl_wait_bit_clear(struct xe_sysctrl *sc, u32 bit_mask,
+				   unsigned int timeout_ms)
+{
+	int ret;
+
+	ret = xe_mmio_wait32_not(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+				 timeout_ms * 1000, NULL, false);
+
+	return ret == 0;
+}
+
+static bool sysctrl_wait_bit_set(struct xe_sysctrl *sc, u32 bit_mask,
+				 unsigned int timeout_ms)
+{
+	int ret;
+
+	ret = xe_mmio_wait32(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+			     timeout_ms * 1000, NULL, false);
+
+	return ret == 0;
+}
+
+static int sysctrl_write_frame(struct xe_sysctrl *sc, const void *frame,
+			       size_t len)
+{
+	static const struct xe_reg regs[] = {
+		SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+	};
+	struct xe_device *xe = sc_to_xe(sc);
+	u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+	u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+	u32 i;
+
+	xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE);
+
+	memcpy(val, frame, len);
+
+	for (i = 0; i < dw; i++)
+		xe_mmio_write32(sc->mmio, regs[i], val[i]);
+
+	return 0;
+}
+
+static int sysctrl_read_frame(struct xe_sysctrl *sc, void *frame,
+			      size_t len)
+{
+	static const struct xe_reg regs[] = {
+		SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+	};
+	struct xe_device *xe = sc_to_xe(sc);
+	u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+	u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+	u32 i;
+
+	xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE);
+
+	for (i = 0; i < dw; i++)
+		val[i] = xe_mmio_read32(sc->mmio, regs[i]);
+
+	memcpy(frame, val, len);
+
+	return 0;
+}
+
+static void sysctrl_clear_response(struct xe_sysctrl *sc)
+{
+	xe_mmio_rmw32(sc->mmio, SYSCTRL_MB_CTRL, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, 0);
+}
+
+static int sysctrl_prepare_command(struct xe_device *xe,
+				   u8 group_id, u8 command,
+				   const void *data_in, size_t data_in_len,
+				   u8 **mbox_cmd, size_t *cmd_size)
+{
+	struct xe_sysctrl_mailbox_schi_msg_hdr *schi_hdr;
+	size_t size;
+	u8 *buffer;
+
+	xe_assert(xe, command <= SCHI_HDR_COMMAND_MAX);
+
+	if (data_in_len > XE_SYSCTRL_MB_MAX_MESSAGE_SIZE - sizeof(*schi_hdr)) {
+		xe_err(xe, "sysctrl: Input data too large: %zu bytes\n", data_in_len);
+		return -EINVAL;
+	}
+
+	size = sizeof(*schi_hdr) + data_in_len;
+
+	buffer = kmalloc(size, GFP_KERNEL);
+	if (!buffer)
+		return -ENOMEM;
+
+	schi_hdr = (struct xe_sysctrl_mailbox_schi_msg_hdr *)buffer;
+	schi_hdr->data = cpu_to_le32(FIELD_PREP(SCHI_HDR_GROUP_ID_MASK, group_id) |
+				     FIELD_PREP(SCHI_HDR_COMMAND_MASK, command));
+
+	if (data_in && data_in_len)
+		memcpy(buffer + sizeof(*schi_hdr), data_in, data_in_len);
+
+	*mbox_cmd = buffer;
+	*cmd_size = size;
+
+	return 0;
+}
+
+static int sysctrl_send_frames(struct xe_sysctrl *sc,
+			       const u8 *mbox_cmd,
+			       size_t cmd_size, unsigned int timeout_ms)
+{
+	struct xe_device *xe = sc_to_xe(sc);
+	u32 ctrl_reg, total_frames, frame;
+	size_t bytes_sent, frame_size;
+
+	total_frames = DIV_ROUND_UP(cmd_size, XE_SYSCTRL_MB_FRAME_SIZE);
+
+	if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+		xe_err(xe, "sysctrl: Mailbox busy\n");
+		return -EBUSY;
+	}
+
+	sc->phase_bit ^= 1;
+	bytes_sent = 0;
+
+	for (frame = 0; frame < total_frames; frame++) {
+		frame_size = min_t(size_t, cmd_size - bytes_sent, XE_SYSCTRL_MB_FRAME_SIZE);
+
+		if (sysctrl_write_frame(sc, mbox_cmd + bytes_sent, frame_size)) {
+			xe_err(xe, "sysctrl: Failed to write frame %u\n", frame);
+			sc->phase_bit = 0;
+			return -EIO;
+		}
+
+		ctrl_reg = SYSCTRL_MB_CTRL_RUN_BUSY |
+			   REG_FIELD_PREP(SCHI_FRAME_CURRENT_MASK, frame) |
+			   REG_FIELD_PREP(SCHI_FRAME_TOTAL_MASK, total_frames - 1) |
+			   SYSCTRL_MB_CTRL_SCHI_CMD |
+			   (sc->phase_bit ? SCHI_FRAME_PHASE : 0);
+
+		xe_mmio_write32(sc->mmio, SYSCTRL_MB_CTRL, ctrl_reg);
+
+		if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+			xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", frame);
+			sc->phase_bit = 0;
+			return -ETIMEDOUT;
+		}
+
+		bytes_sent += frame_size;
+	}
+
+	return 0;
+}
+
+static int sysctrl_process_frame(struct xe_sysctrl *sc, void *out,
+				 size_t frame_size, unsigned int timeout_ms,
+				 bool *done)
+{
+	u32 curr_frame, total_frames, ctrl_reg;
+	struct xe_device *xe = sc_to_xe(sc);
+	int ret;
+
+	if (!sysctrl_wait_bit_set(sc, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
+		xe_err(xe, "sysctrl: Response frame timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
+	total_frames = FIELD_GET(SCHI_FRAME_TOTAL_MASK, ctrl_reg);
+	curr_frame = FIELD_GET(SCHI_FRAME_CURRENT_MASK, ctrl_reg);
+
+	ret = sysctrl_read_frame(sc, out, frame_size);
+	if (ret)
+		return ret;
+
+	sysctrl_clear_response(sc);
+
+	if (curr_frame == total_frames)
+		*done = true;
+
+	return 0;
+}
+
+static int sysctrl_receive_frames(struct xe_sysctrl *sc,
+				  const struct xe_sysctrl_mailbox_schi_msg_hdr *req,
+				  void *data_out, size_t data_out_len,
+				  size_t *rdata_len, unsigned int timeout_ms)
+{
+	struct xe_sysctrl_mailbox_schi_msg_hdr *schi_hdr;
+	struct xe_device *xe = sc_to_xe(sc);
+	size_t remain = sizeof(*schi_hdr) + data_out_len;
+	u8 *buffer __free(kfree) = kzalloc(remain, GFP_KERNEL);
+	size_t frame_size;
+	bool done = false;
+	int ret = 0;
+	u8 *out;
+
+	if (!buffer)
+		return -ENOMEM;
+
+	out = buffer;
+	while (!done && remain) {
+		frame_size = min_t(size_t, remain, XE_SYSCTRL_MB_FRAME_SIZE);
+
+		ret = sysctrl_process_frame(sc, out, frame_size, timeout_ms,
+					    &done);
+		if (ret)
+			return ret;
+
+		remain -= frame_size;
+		out += frame_size;
+	}
+
+	schi_hdr = (struct xe_sysctrl_mailbox_schi_msg_hdr *)buffer;
+
+	if (!XE_SYSCTRL_SCHI_HDR_IS_RESPONSE(schi_hdr) ||
+	    XE_SYSCTRL_SCHI_HDR_GROUP_ID(schi_hdr) != XE_SYSCTRL_SCHI_HDR_GROUP_ID(req) ||
+	    XE_SYSCTRL_SCHI_HDR_COMMAND(schi_hdr) != XE_SYSCTRL_SCHI_HDR_COMMAND(req)) {
+		xe_err(xe, "sysctrl: Response header mismatch\n");
+		return -EPROTO;
+	}
+
+	if (XE_SYSCTRL_SCHI_HDR_RESULT(schi_hdr) != 0) {
+		xe_err(xe, "sysctrl: Firmware error: 0x%02lx\n",
+		       XE_SYSCTRL_SCHI_HDR_RESULT(schi_hdr));
+		return -EIO;
+	}
+
+	memcpy(data_out, schi_hdr + 1, data_out_len);
+	*rdata_len = out - buffer - sizeof(*schi_hdr);
+
+	return 0;
+}
+
+static int sysctrl_send_command(struct xe_sysctrl *sc,
+				const u8 *mbox_cmd, size_t cmd_size,
+				void *data_out, size_t data_out_len,
+				size_t *rdata_len, unsigned int timeout_ms)
+{
+	const struct xe_sysctrl_mailbox_schi_msg_hdr *schi_hdr;
+	size_t received;
+	int ret;
+
+	ret = sysctrl_send_frames(sc, mbox_cmd, cmd_size, timeout_ms);
+	if (ret)
+		return ret;
+
+	if (!data_out || !rdata_len)
+		return 0;
+
+	schi_hdr = (const struct xe_sysctrl_mailbox_schi_msg_hdr *)mbox_cmd;
+
+	ret = sysctrl_receive_frames(sc, schi_hdr, data_out, data_out_len,
+				     &received, timeout_ms);
+	if (ret)
+		return ret;
+
+	*rdata_len = received;
+
+	return 0;
+}
+
+/**
+ * xe_sysctrl_mailbox_init - Initialize System Controller mailbox interface
+ * @sc: System controller structure
+ *
+ * Initialize system controller mailbox interface for communication.
+ */
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc)
+{
+	u32 ctrl_reg;
+
+	ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
+	sc->phase_bit = (ctrl_reg & SCHI_FRAME_PHASE) ? 1 : 0;
+}
+
+/**
+ * xe_sysctrl_send_command() - Send command to System Controller via mailbox
+ * @sc: System Controller instance
+ * @cmd: Pointer to xe_sysctrl_mailbox_command structure
+ * @rdata_len: Pointer to store actual response data size (can be NULL)
+ *
+ * Send a command to the System Controller using SCHI protocol. Handles
+ * command preparation, fragmentation, transmission, and response reception.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int xe_sysctrl_send_command(struct xe_sysctrl *sc,
+			    struct xe_sysctrl_mailbox_command *cmd,
+			    size_t *rdata_len)
+{
+	struct xe_device *xe = sc_to_xe(sc);
+	u8 group_id, command_code;
+	u8 *mbox_cmd = NULL;
+	size_t cmd_size = 0;
+	int ret = 0;
+
+	xe_assert(xe, xe->info.has_sysctrl);
+	xe_assert(xe, cmd->data_in || cmd->data_out);
+	xe_assert(xe, !cmd->data_in || cmd->data_in_len);
+	xe_assert(xe, !cmd->data_out || cmd->data_out_len);
+
+	group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header);
+	command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header);
+
+	might_sleep();
+
+	ret = sysctrl_prepare_command(xe, group_id, command_code,
+				      cmd->data_in, cmd->data_in_len,
+				      &mbox_cmd, &cmd_size);
+	if (ret) {
+		xe_err(xe, "sysctrl: Failed to prepare command: %pe\n", ERR_PTR(ret));
+		return ret;
+	}
+
+	guard(xe_pm_runtime)(xe);
+
+	guard(mutex)(&sc->cmd_lock);
+
+	ret = sysctrl_send_command(sc, mbox_cmd, cmd_size,
+				   cmd->data_out, cmd->data_out_len, rdata_len,
+				   XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS);
+	if (ret)
+		xe_err(xe, "sysctrl: Mailbox command failed: %pe\n", ERR_PTR(ret));
+
+	kfree(mbox_cmd);
+
+	return ret;
+}
-- 
2.43.0

Re: [PATCH v9 5/6] drm/xe/sysctrl: Add mailbox communication implementation

[Riana Tauro]

Hi Anoop

On 3/10/2026 11:53 PM, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> Adding mailbox communication layer for System Controller
> interaction. The mailbox interface enables sending commands and
> receiving responses from embedded System Controller.
> 
> Key features:
> - Command/response protocol handling
> - Timeout and error management
> - Uses protocol headers defined in ABI
> 
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> v4: (Matt, Mike)
> - Refactor MMIO access to use domain-specific accessor
> - Add input validation and buffer overflow protection
> - Add bounds checking for multi-frame operations
> - Fix potential NULL pointer dereference
> 
> v5: (Umesh, Riana)
> - Reset phase bit to 0 on error conditions
> - Refactor mailbox receive path
> - Updated xe_err messages for consistency
> 
> v6: (Matt)
> - Use SYSCTRL_MB_CTRL_MKHI_CMD macro instead of FIELD_PREP
> 
> v8: (Matt, Michal)
> - Reordered patches for logical flow
> - Static functions renamed with short prefix
> - Changed xe_sysctrl_send_command() function parameter from 'xe' to 'sc'
> - Added frame length validation and command overflow protection
> - Use REG_FIELD_PREP for hardware registers
> - Changed error format to %pe
> - Removed unnecessary NULL checks and explicit zeros
> - Fixed kernel-doc syntax
> 
> v9: (Umesh, Badal)
> - Renamed MKHI to SCHI (System Controller Host Interface)
> - Fixed kernel-doc syntax
> ---
> 
>   drivers/gpu/drm/xe/Makefile             |   1 +
>   drivers/gpu/drm/xe/xe_sysctrl.c         |   2 +
>   drivers/gpu/drm/xe/xe_sysctrl_mailbox.c | 364 ++++++++++++++++++++++++
>   3 files changed, 367 insertions(+)
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 76a86818986a..7d13a3e43c9f 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -124,6 +124,7 @@ xe-y += xe_bb.o \
>   	xe_survivability_mode.o \
>   	xe_sync.o \
>   	xe_sysctrl.o \
> +	xe_sysctrl_mailbox.o \
>   	xe_tile.o \
>   	xe_tile_sysfs.o \
>   	xe_tlb_inval.o \
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index 2751fe25a6ff..365f73ef680d 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -78,5 +78,7 @@ int xe_sysctrl_init(struct xe_device *xe)
>   	if (ret)
>   		return ret;
>   
> +	xe_sysctrl_mailbox_init(sc);
> +
>   	return 0;
>   }
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
> new file mode 100644
> index 000000000000..b08885cf8dd5
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
> @@ -0,0 +1,364 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/cleanup.h>
> +#include <linux/container_of.h>
> +#include <linux/errno.h>
> +#include <linux/minmax.h>
> +#include <linux/mutex.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/types.h>

These are redundant includes that are already
included by below files.

I don't see an issue removing these

> +
> +#include "regs/xe_sysctrl_regs.h"
> +#include "xe_device.h"
> +#include "xe_device_types.h"
> +#include "xe_mmio.h"
> +#include "xe_pm.h"
> +#include "xe_printk.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_mailbox.h"
> +#include "xe_sysctrl_mailbox_types.h"
> +#include "xe_sysctrl_types.h"
> +
> +#define XE_SYSCTRL_SCHI_HDR_GROUP_ID(hdr) \
> +	FIELD_GET(SCHI_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
> +
> +#define XE_SYSCTRL_SCHI_HDR_COMMAND(hdr) \
> +	FIELD_GET(SCHI_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
> +
> +#define XE_SYSCTRL_SCHI_HDR_IS_RESPONSE(hdr) \
> +	FIELD_GET(SCHI_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
> +
> +#define XE_SYSCTRL_SCHI_HDR_RESULT(hdr) \
> +	FIELD_GET(SCHI_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
> +
> +static bool sysctrl_wait_bit_clear(struct xe_sysctrl *sc, u32 bit_mask,
> +				   unsigned int timeout_ms)
> +{
> +	int ret;
> +
> +	ret = xe_mmio_wait32_not(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
> +				 timeout_ms * 1000, NULL, false);
> +
> +	return ret == 0;
> +}
> +
> +static bool sysctrl_wait_bit_set(struct xe_sysctrl *sc, u32 bit_mask,
> +				 unsigned int timeout_ms)
> +{
> +	int ret;
> +
> +	ret = xe_mmio_wait32(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
> +			     timeout_ms * 1000, NULL, false);
> +
> +	return ret == 0;
> +}
> +
> +static int sysctrl_write_frame(struct xe_sysctrl *sc, const void *frame,
> +			       size_t len)
> +{
> +	static const struct xe_reg regs[] = {
> +		SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
> +	};
> +	struct xe_device *xe = sc_to_xe(sc);
> +	u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
> +	u32 dw = DIV_ROUND_UP(len, sizeof(u32));
> +	u32 i;
> +
> +	xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE);
> +
> +	memcpy(val, frame, len);
> +
> +	for (i = 0; i < dw; i++)
> +		xe_mmio_write32(sc->mmio, regs[i], val[i]);
> +
> +	return 0;
> +}
> +
> +static int sysctrl_read_frame(struct xe_sysctrl *sc, void *frame,
> +			      size_t len)
> +{
> +	static const struct xe_reg regs[] = {
> +		SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
> +	};
> +	struct xe_device *xe = sc_to_xe(sc);
> +	u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
> +	u32 dw = DIV_ROUND_UP(len, sizeof(u32));
> +	u32 i;
> +
> +	xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE);
> +
> +	for (i = 0; i < dw; i++)
> +		val[i] = xe_mmio_read32(sc->mmio, regs[i]);
> +
> +	memcpy(frame, val, len);
> +
> +	return 0;
> +}
> +
> +static void sysctrl_clear_response(struct xe_sysctrl *sc)
> +{
> +	xe_mmio_rmw32(sc->mmio, SYSCTRL_MB_CTRL, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, 0);
> +}
> +
> +static int sysctrl_prepare_command(struct xe_device *xe,
> +				   u8 group_id, u8 command,
> +				   const void *data_in, size_t data_in_len,
> +				   u8 **mbox_cmd, size_t *cmd_size)
> +{
> +	struct xe_sysctrl_mailbox_schi_msg_hdr *schi_hdr;
> +	size_t size;
> +	u8 *buffer;
> +
> +	xe_assert(xe, command <= SCHI_HDR_COMMAND_MAX);
> +
> +	if (data_in_len > XE_SYSCTRL_MB_MAX_MESSAGE_SIZE - sizeof(*schi_hdr)) {
> +		xe_err(xe, "sysctrl: Input data too large: %zu bytes\n", data_in_len);
> +		return -EINVAL;
> +	}
> +
> +	size = sizeof(*schi_hdr) + data_in_len;
> +
> +	buffer = kmalloc(size, GFP_KERNEL);
> +	if (!buffer)
> +		return -ENOMEM;
> +
> +	schi_hdr = (struct xe_sysctrl_mailbox_schi_msg_hdr *)buffer;
> +	schi_hdr->data = cpu_to_le32(FIELD_PREP(SCHI_HDR_GROUP_ID_MASK, group_id) |
> +				     FIELD_PREP(SCHI_HDR_COMMAND_MASK, command));
> +
> +	if (data_in && data_in_len)
> +		memcpy(buffer + sizeof(*schi_hdr), data_in, data_in_len);
> +
> +	*mbox_cmd = buffer;
> +	*cmd_size = size;
> +
> +	return 0;
> +}
> +
> +static int sysctrl_send_frames(struct xe_sysctrl *sc,
> +			       const u8 *mbox_cmd,
> +			       size_t cmd_size, unsigned int timeout_ms)
> +{
> +	struct xe_device *xe = sc_to_xe(sc);
> +	u32 ctrl_reg, total_frames, frame;
> +	size_t bytes_sent, frame_size;
> +
> +	total_frames = DIV_ROUND_UP(cmd_size, XE_SYSCTRL_MB_FRAME_SIZE);
> +
> +	if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
> +		xe_err(xe, "sysctrl: Mailbox busy\n");
> +		return -EBUSY;
> +	}
> +
> +	sc->phase_bit ^= 1;
> +	bytes_sent = 0;
> +
> +	for (frame = 0; frame < total_frames; frame++) {
> +		frame_size = min_t(size_t, cmd_size - bytes_sent, XE_SYSCTRL_MB_FRAME_SIZE);
> +
> +		if (sysctrl_write_frame(sc, mbox_cmd + bytes_sent, frame_size)) {
> +			xe_err(xe, "sysctrl: Failed to write frame %u\n", frame);
> +			sc->phase_bit = 0;
> +			return -EIO;
> +		}
> +
> +		ctrl_reg = SYSCTRL_MB_CTRL_RUN_BUSY |
> +			   REG_FIELD_PREP(SCHI_FRAME_CURRENT_MASK, frame) |
> +			   REG_FIELD_PREP(SCHI_FRAME_TOTAL_MASK, total_frames - 1) |
> +			   SYSCTRL_MB_CTRL_SCHI_CMD |
> +			   (sc->phase_bit ? SCHI_FRAME_PHASE : 0);
> +
> +		xe_mmio_write32(sc->mmio, SYSCTRL_MB_CTRL, ctrl_reg);
> +
> +		if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
> +			xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", frame);
> +			sc->phase_bit = 0;
> +			return -ETIMEDOUT;
> +		}
> +
> +		bytes_sent += frame_size;
> +	}
> +
> +	return 0;
> +}
> +
> +static int sysctrl_process_frame(struct xe_sysctrl *sc, void *out,
> +				 size_t frame_size, unsigned int timeout_ms,
> +				 bool *done)
> +{
> +	u32 curr_frame, total_frames, ctrl_reg;
> +	struct xe_device *xe = sc_to_xe(sc);
> +	int ret;
> +
> +	if (!sysctrl_wait_bit_set(sc, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
> +		xe_err(xe, "sysctrl: Response frame timeout\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
> +	total_frames = FIELD_GET(SCHI_FRAME_TOTAL_MASK, ctrl_reg);
> +	curr_frame = FIELD_GET(SCHI_FRAME_CURRENT_MASK, ctrl_reg);
> +
> +	ret = sysctrl_read_frame(sc, out, frame_size);
> +	if (ret)
> +		return ret;
> +
> +	sysctrl_clear_response(sc);
> +
> +	if (curr_frame == total_frames)
> +		*done = true;
> +
> +	return 0;
> +}
> +
> +static int sysctrl_receive_frames(struct xe_sysctrl *sc,
> +				  const struct xe_sysctrl_mailbox_schi_msg_hdr *req,
> +				  void *data_out, size_t data_out_len,
> +				  size_t *rdata_len, unsigned int timeout_ms)
> +{
> +	struct xe_sysctrl_mailbox_schi_msg_hdr *schi_hdr;
> +	struct xe_device *xe = sc_to_xe(sc);
> +	size_t remain = sizeof(*schi_hdr) + data_out_len;
> +	u8 *buffer __free(kfree) = kzalloc(remain, GFP_KERNEL);
> +	size_t frame_size;
> +	bool done = false;
> +	int ret = 0;
> +	u8 *out;
> +
> +	if (!buffer)
> +		return -ENOMEM;
> +
> +	out = buffer;
> +	while (!done && remain) {
> +		frame_size = min_t(size_t, remain, XE_SYSCTRL_MB_FRAME_SIZE);
> +
> +		ret = sysctrl_process_frame(sc, out, frame_size, timeout_ms,
> +					    &done);
> +		if (ret)
> +			return ret;
> +
> +		remain -= frame_size;
> +		out += frame_size;
> +	}
> +
> +	schi_hdr = (struct xe_sysctrl_mailbox_schi_msg_hdr *)buffer;
> +
> +	if (!XE_SYSCTRL_SCHI_HDR_IS_RESPONSE(schi_hdr) ||
> +	    XE_SYSCTRL_SCHI_HDR_GROUP_ID(schi_hdr) != XE_SYSCTRL_SCHI_HDR_GROUP_ID(req) ||
> +	    XE_SYSCTRL_SCHI_HDR_COMMAND(schi_hdr) != XE_SYSCTRL_SCHI_HDR_COMMAND(req)) {
> +		xe_err(xe, "sysctrl: Response header mismatch\n");
> +		return -EPROTO;
> +	}
> +
> +	if (XE_SYSCTRL_SCHI_HDR_RESULT(schi_hdr) != 0) {
> +		xe_err(xe, "sysctrl: Firmware error: 0x%02lx\n",
> +		       XE_SYSCTRL_SCHI_HDR_RESULT(schi_hdr));
> +		return -EIO;
> +	}
> +
> +	memcpy(data_out, schi_hdr + 1, data_out_len);
> +	*rdata_len = out - buffer - sizeof(*schi_hdr);
> +
> +	return 0;
> +}
> +
> +static int sysctrl_send_command(struct xe_sysctrl *sc,
> +				const u8 *mbox_cmd, size_t cmd_size,
> +				void *data_out, size_t data_out_len,
> +				size_t *rdata_len, unsigned int timeout_ms)
> +{
> +	const struct xe_sysctrl_mailbox_schi_msg_hdr *schi_hdr;
> +	size_t received;
> +	int ret;
> +
> +	ret = sysctrl_send_frames(sc, mbox_cmd, cmd_size, timeout_ms);
> +	if (ret)
> +		return ret;
> +
> +	if (!data_out || !rdata_len)
> +		return 0;
> +
> +	schi_hdr = (const struct xe_sysctrl_mailbox_schi_msg_hdr *)mbox_cmd;
> +
> +	ret = sysctrl_receive_frames(sc, schi_hdr, data_out, data_out_len,
> +				     &received, timeout_ms);
> +	if (ret)
> +		return ret;
> +
> +	*rdata_len = received;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_sysctrl_mailbox_init - Initialize System Controller mailbox interface
> + * @sc: System controller structure
> + *
> + * Initialize system controller mailbox interface for communication.
> + */
> +void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc)
> +{
> +	u32 ctrl_reg;
> +
> +	ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
> +	sc->phase_bit = (ctrl_reg & SCHI_FRAME_PHASE) ? 1 : 0;
> +}
> +
> +/**
> + * xe_sysctrl_send_command() - Send command to System Controller via mailbox
> + * @sc: System Controller instance
> + * @cmd: Pointer to xe_sysctrl_mailbox_command structure
> + * @rdata_len: Pointer to store actual response data size (can be NULL)
> + *
> + * Send a command to the System Controller using SCHI protocol. Handles

Same as other patches. SCHI protocol is undefined.

> + * command preparation, fragmentation, transmission, and response reception.
> + *
> + * Return: 0 on success, negative error code on failure
> + */
> +int xe_sysctrl_send_command(struct xe_sysctrl *sc,
> +			    struct xe_sysctrl_mailbox_command *cmd,
> +			    size_t *rdata_len)
> +{
> +	struct xe_device *xe = sc_to_xe(sc);
> +	u8 group_id, command_code;
> +	u8 *mbox_cmd = NULL;
> +	size_t cmd_size = 0;
> +	int ret = 0;

Initialization is unnecessary

> +
> +	xe_assert(xe, xe->info.has_sysctrl);
> +	xe_assert(xe, cmd->data_in || cmd->data_out);
> +	xe_assert(xe, !cmd->data_in || cmd->data_in_len);
> +	xe_assert(xe, !cmd->data_out || cmd->data_out_len);
> +
> +	group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header);
> +	command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header);
> +
> +	might_sleep();
> +
> +	ret = sysctrl_prepare_command(xe, group_id, command_code,
> +				      cmd->data_in, cmd->data_in_len,
> +				      &mbox_cmd, &cmd_size);
> +	if (ret) {
> +		xe_err(xe, "sysctrl: Failed to prepare command: %pe\n", ERR_PTR(ret));
> +		return ret;
> +	}
> +
> +	guard(xe_pm_runtime)(xe);

Runtime pm should be in the outermost layer.
Should this be here or the upper layers?

++ @Rodrigo thoughts?


> +
> +	guard(mutex)(&sc->cmd_lock);
> +
> +	ret = sysctrl_send_command(sc, mbox_cmd, cmd_size,
> +				   cmd->data_out, cmd->data_out_len, rdata_len,
> +				   XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS);

Why not use the macro directly instead of sending it as a parameter?

Thanks
Riana

> +	if (ret)
> +		xe_err(xe, "sysctrl: Mailbox command failed: %pe\n", ERR_PTR(ret));
> +
> +	kfree(mbox_cmd);
> +
> +	return ret;
> +}

[PATCH v9 6/6] drm/xe/pci: Enable System Controller for CRI platform

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Enable System Controller support for CRI platform by setting
has_sysctrl flag in device descriptor and runtime device info.

This allows the System Controller subsystem and mailbox communication
to be initialized on CRI platform.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
---
v8: (Matt, Michal)
- Reordered patches for logical flow
---
 drivers/gpu/drm/xe/xe_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 29f976e66848..3d4a6619315f 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -465,6 +465,7 @@ static const struct xe_device_desc cri_desc = {
 	.has_soc_remapper_sysctrl = true,
 	.has_soc_remapper_telem = true,
 	.has_sriov = true,
+	.has_sysctrl = true,
 	.max_gt_per_tile = 2,
 	MULTI_LRC_MASK,
 	.require_force_probe = true,
@@ -764,6 +765,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
 	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
 		desc->has_sriov;
+	xe->info.has_sysctrl = desc->has_sysctrl;
 	xe->info.skip_guc_pc = desc->skip_guc_pc;
 	xe->info.skip_mtcfg = desc->skip_mtcfg;
 	xe->info.skip_pcode = desc->skip_pcode;
-- 
2.43.0

Re: [PATCH v9 6/6] drm/xe/pci: Enable System Controller for CRI platform

[Riana Tauro]

Hi Anoop

Title should be

  drm/xe/xe_pci: Enable System Controller for CRI platform

Thanks
Riana

On 3/10/2026 11:53 PM, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> Enable System Controller support for CRI platform by setting
> has_sysctrl flag in device descriptor and runtime device info.
> 
> This allows the System Controller subsystem and mailbox communication
> to be initialized on CRI platform.
> 
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> ---
> v8: (Matt, Michal)
> - Reordered patches for logical flow
> ---
>   drivers/gpu/drm/xe/xe_pci.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 29f976e66848..3d4a6619315f 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -465,6 +465,7 @@ static const struct xe_device_desc cri_desc = {
>   	.has_soc_remapper_sysctrl = true,
>   	.has_soc_remapper_telem = true,
>   	.has_sriov = true,
> +	.has_sysctrl = true,
>   	.max_gt_per_tile = 2,
>   	MULTI_LRC_MASK,
>   	.require_force_probe = true,
> @@ -764,6 +765,7 @@ static int xe_info_init_early(struct xe_device *xe,
>   	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
>   	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
>   		desc->has_sriov;
> +	xe->info.has_sysctrl = desc->has_sysctrl;
>   	xe->info.skip_guc_pc = desc->skip_guc_pc;
>   	xe->info.skip_mtcfg = desc->skip_mtcfg;
>   	xe->info.skip_pcode = desc->skip_pcode;

Re: [PATCH v9 6/6] drm/xe/pci: Enable System Controller for CRI platform

[Umesh Nerlige Ramappa]

On Tue, Mar 10, 2026 at 11:23:25AM -0700, Anoop, Vijay wrote:
>From: Anoop Vijay <anoop.c.vijay@intel.com>
>
>Enable System Controller support for CRI platform by setting
>has_sysctrl flag in device descriptor and runtime device info.
>
>This allows the System Controller subsystem and mailbox communication
>to be initialized on CRI platform.
>
>Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>

LGTM,

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Umesh
>---
>v8: (Matt, Michal)
>- Reordered patches for logical flow
>---
> drivers/gpu/drm/xe/xe_pci.c | 2 ++
> 1 file changed, 2 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index 29f976e66848..3d4a6619315f 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -465,6 +465,7 @@ static const struct xe_device_desc cri_desc = {
> 	.has_soc_remapper_sysctrl = true,
> 	.has_soc_remapper_telem = true,
> 	.has_sriov = true,
>+	.has_sysctrl = true,
> 	.max_gt_per_tile = 2,
> 	MULTI_LRC_MASK,
> 	.require_force_probe = true,
>@@ -764,6 +765,7 @@ static int xe_info_init_early(struct xe_device *xe,
> 	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
> 	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
> 		desc->has_sriov;
>+	xe->info.has_sysctrl = desc->has_sysctrl;
> 	xe->info.skip_guc_pc = desc->skip_guc_pc;
> 	xe->info.skip_mtcfg = desc->skip_mtcfg;
> 	xe->info.skip_pcode = desc->skip_pcode;
>-- 
>2.43.0
>

✗ CI.checkpatch: warning for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10)

[Patchwork]

== Series Details ==

Series: drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10)
URL   : https://patchwork.freedesktop.org/series/159554/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b6ecd0a031a4d3b8975d51d867817f40969d701c
Author: Anoop Vijay <anoop.c.vijay@intel.com>
Date:   Tue Mar 10 11:23:25 2026 -0700

    drm/xe/pci: Enable System Controller for CRI platform
    
    Enable System Controller support for CRI platform by setting
    has_sysctrl flag in device descriptor and runtime device info.
    
    This allows the System Controller subsystem and mailbox communication
    to be initialized on CRI platform.
    
    Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
+ /mt/dim checkpatch 4115adfa36043651de04d911c3a98d821a8fa040 drm-intel
f917e5ad2fa3 drm/xe/sysctrl: Add System Controller types and device integration
-:72: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#72: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 63 lines checked
13d661d8c8ea drm/xe/sysctrl: Add System Controller register definitions
-:17: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#17: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 36 lines checked
7ffa40388c97 drm/xe/sysctrl: Add mailbox communication headers
-:14: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#14: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 97 lines checked
95573fe5fbe4 drm/xe/sysctrl: Add System Controller initialization
-:53: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#53: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 127 lines checked
9488b7660b5b drm/xe/sysctrl: Add mailbox communication implementation
-:43: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#43: 
new file mode 100644

-:274: WARNING:LINE_SPACING: Missing a blank line after declarations
#274: FILE: drivers/gpu/drm/xe/xe_sysctrl_mailbox.c:227:
+	size_t remain = sizeof(*schi_hdr) + data_out_len;
+	u8 *buffer __free(kfree) = kzalloc(remain, GFP_KERNEL);

total: 0 errors, 2 warnings, 0 checks, 378 lines checked
b6ecd0a031a4 drm/xe/pci: Enable System Controller for CRI platform

✓ CI.KUnit: success for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10)

[Patchwork]

== Series Details ==

Series: drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10)
URL   : https://patchwork.freedesktop.org/series/159554/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[18:30:01] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:30:05] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:30:36] Starting KUnit Kernel (1/1)...
[18:30:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:30:36] ================== guc_buf (11 subtests) ===================
[18:30:36] [PASSED] test_smallest
[18:30:36] [PASSED] test_largest
[18:30:36] [PASSED] test_granular
[18:30:36] [PASSED] test_unique
[18:30:36] [PASSED] test_overlap
[18:30:36] [PASSED] test_reusable
[18:30:36] [PASSED] test_too_big
[18:30:36] [PASSED] test_flush
[18:30:36] [PASSED] test_lookup
[18:30:36] [PASSED] test_data
[18:30:36] [PASSED] test_class
[18:30:36] ===================== [PASSED] guc_buf =====================
[18:30:36] =================== guc_dbm (7 subtests) ===================
[18:30:36] [PASSED] test_empty
[18:30:36] [PASSED] test_default
[18:30:36] ======================== test_size  ========================
[18:30:36] [PASSED] 4
[18:30:36] [PASSED] 8
[18:30:36] [PASSED] 32
[18:30:36] [PASSED] 256
[18:30:36] ==================== [PASSED] test_size ====================
[18:30:36] ======================= test_reuse  ========================
[18:30:36] [PASSED] 4
[18:30:36] [PASSED] 8
[18:30:36] [PASSED] 32
[18:30:36] [PASSED] 256
[18:30:36] =================== [PASSED] test_reuse ====================
[18:30:36] =================== test_range_overlap  ====================
[18:30:36] [PASSED] 4
[18:30:36] [PASSED] 8
[18:30:36] [PASSED] 32
[18:30:36] [PASSED] 256
[18:30:36] =============== [PASSED] test_range_overlap ================
[18:30:36] =================== test_range_compact  ====================
[18:30:36] [PASSED] 4
[18:30:36] [PASSED] 8
[18:30:36] [PASSED] 32
[18:30:36] [PASSED] 256
[18:30:36] =============== [PASSED] test_range_compact ================
[18:30:36] ==================== test_range_spare  =====================
[18:30:36] [PASSED] 4
[18:30:36] [PASSED] 8
[18:30:36] [PASSED] 32
[18:30:36] [PASSED] 256
[18:30:36] ================ [PASSED] test_range_spare =================
[18:30:36] ===================== [PASSED] guc_dbm =====================
[18:30:36] =================== guc_idm (6 subtests) ===================
[18:30:36] [PASSED] bad_init
[18:30:36] [PASSED] no_init
[18:30:36] [PASSED] init_fini
[18:30:36] [PASSED] check_used
[18:30:36] [PASSED] check_quota
[18:30:36] [PASSED] check_all
[18:30:36] ===================== [PASSED] guc_idm =====================
[18:30:36] ================== no_relay (3 subtests) ===================
[18:30:36] [PASSED] xe_drops_guc2pf_if_not_ready
[18:30:36] [PASSED] xe_drops_guc2vf_if_not_ready
[18:30:36] [PASSED] xe_rejects_send_if_not_ready
[18:30:36] ==================== [PASSED] no_relay =====================
[18:30:36] ================== pf_relay (14 subtests) ==================
[18:30:36] [PASSED] pf_rejects_guc2pf_too_short
[18:30:36] [PASSED] pf_rejects_guc2pf_too_long
[18:30:36] [PASSED] pf_rejects_guc2pf_no_payload
[18:30:36] [PASSED] pf_fails_no_payload
[18:30:36] [PASSED] pf_fails_bad_origin
[18:30:36] [PASSED] pf_fails_bad_type
[18:30:36] [PASSED] pf_txn_reports_error
[18:30:36] [PASSED] pf_txn_sends_pf2guc
[18:30:36] [PASSED] pf_sends_pf2guc
[18:30:36] [SKIPPED] pf_loopback_nop
[18:30:36] [SKIPPED] pf_loopback_echo
[18:30:36] [SKIPPED] pf_loopback_fail
[18:30:36] [SKIPPED] pf_loopback_busy
[18:30:36] [SKIPPED] pf_loopback_retry
[18:30:36] ==================== [PASSED] pf_relay =====================
[18:30:36] ================== vf_relay (3 subtests) ===================
[18:30:36] [PASSED] vf_rejects_guc2vf_too_short
[18:30:36] [PASSED] vf_rejects_guc2vf_too_long
[18:30:36] [PASSED] vf_rejects_guc2vf_no_payload
[18:30:36] ==================== [PASSED] vf_relay =====================
[18:30:36] ================ pf_gt_config (9 subtests) =================
[18:30:36] [PASSED] fair_contexts_1vf
[18:30:36] [PASSED] fair_doorbells_1vf
[18:30:36] [PASSED] fair_ggtt_1vf
[18:30:36] ====================== fair_vram_1vf  ======================
[18:30:36] [PASSED] 3.50 GiB
[18:30:36] [PASSED] 11.5 GiB
[18:30:36] [PASSED] 15.5 GiB
[18:30:36] [PASSED] 31.5 GiB
[18:30:36] [PASSED] 63.5 GiB
[18:30:36] [PASSED] 1.91 GiB
[18:30:36] ================== [PASSED] fair_vram_1vf ==================
[18:30:36] ================ fair_vram_1vf_admin_only  =================
[18:30:36] [PASSED] 3.50 GiB
[18:30:36] [PASSED] 11.5 GiB
[18:30:36] [PASSED] 15.5 GiB
[18:30:36] [PASSED] 31.5 GiB
[18:30:36] [PASSED] 63.5 GiB
[18:30:36] [PASSED] 1.91 GiB
[18:30:36] ============ [PASSED] fair_vram_1vf_admin_only =============
[18:30:36] ====================== fair_contexts  ======================
[18:30:36] [PASSED] 1 VF
[18:30:36] [PASSED] 2 VFs
[18:30:36] [PASSED] 3 VFs
[18:30:36] [PASSED] 4 VFs
[18:30:36] [PASSED] 5 VFs
[18:30:36] [PASSED] 6 VFs
[18:30:36] [PASSED] 7 VFs
[18:30:36] [PASSED] 8 VFs
[18:30:36] [PASSED] 9 VFs
[18:30:36] [PASSED] 10 VFs
[18:30:36] [PASSED] 11 VFs
[18:30:36] [PASSED] 12 VFs
[18:30:36] [PASSED] 13 VFs
[18:30:36] [PASSED] 14 VFs
[18:30:36] [PASSED] 15 VFs
[18:30:36] [PASSED] 16 VFs
[18:30:36] [PASSED] 17 VFs
[18:30:36] [PASSED] 18 VFs
[18:30:36] [PASSED] 19 VFs
[18:30:36] [PASSED] 20 VFs
[18:30:36] [PASSED] 21 VFs
[18:30:36] [PASSED] 22 VFs
[18:30:36] [PASSED] 23 VFs
[18:30:36] [PASSED] 24 VFs
[18:30:36] [PASSED] 25 VFs
[18:30:36] [PASSED] 26 VFs
[18:30:36] [PASSED] 27 VFs
[18:30:36] [PASSED] 28 VFs
[18:30:36] [PASSED] 29 VFs
[18:30:36] [PASSED] 30 VFs
[18:30:36] [PASSED] 31 VFs
[18:30:36] [PASSED] 32 VFs
[18:30:36] [PASSED] 33 VFs
[18:30:36] [PASSED] 34 VFs
[18:30:36] [PASSED] 35 VFs
[18:30:36] [PASSED] 36 VFs
[18:30:36] [PASSED] 37 VFs
[18:30:36] [PASSED] 38 VFs
[18:30:36] [PASSED] 39 VFs
[18:30:36] [PASSED] 40 VFs
[18:30:36] [PASSED] 41 VFs
[18:30:36] [PASSED] 42 VFs
[18:30:36] [PASSED] 43 VFs
[18:30:36] [PASSED] 44 VFs
[18:30:36] [PASSED] 45 VFs
[18:30:36] [PASSED] 46 VFs
[18:30:36] [PASSED] 47 VFs
[18:30:36] [PASSED] 48 VFs
[18:30:36] [PASSED] 49 VFs
[18:30:36] [PASSED] 50 VFs
[18:30:36] [PASSED] 51 VFs
[18:30:36] [PASSED] 52 VFs
[18:30:36] [PASSED] 53 VFs
[18:30:36] [PASSED] 54 VFs
[18:30:36] [PASSED] 55 VFs
[18:30:36] [PASSED] 56 VFs
[18:30:36] [PASSED] 57 VFs
[18:30:36] [PASSED] 58 VFs
[18:30:36] [PASSED] 59 VFs
[18:30:36] [PASSED] 60 VFs
[18:30:36] [PASSED] 61 VFs
[18:30:36] [PASSED] 62 VFs
[18:30:36] [PASSED] 63 VFs
[18:30:36] ================== [PASSED] fair_contexts ==================
[18:30:36] ===================== fair_doorbells  ======================
[18:30:36] [PASSED] 1 VF
[18:30:36] [PASSED] 2 VFs
[18:30:36] [PASSED] 3 VFs
[18:30:36] [PASSED] 4 VFs
[18:30:36] [PASSED] 5 VFs
[18:30:36] [PASSED] 6 VFs
[18:30:36] [PASSED] 7 VFs
[18:30:36] [PASSED] 8 VFs
[18:30:36] [PASSED] 9 VFs
[18:30:36] [PASSED] 10 VFs
[18:30:36] [PASSED] 11 VFs
[18:30:36] [PASSED] 12 VFs
[18:30:36] [PASSED] 13 VFs
[18:30:36] [PASSED] 14 VFs
[18:30:36] [PASSED] 15 VFs
[18:30:36] [PASSED] 16 VFs
[18:30:36] [PASSED] 17 VFs
[18:30:36] [PASSED] 18 VFs
[18:30:36] [PASSED] 19 VFs
[18:30:36] [PASSED] 20 VFs
[18:30:36] [PASSED] 21 VFs
[18:30:36] [PASSED] 22 VFs
[18:30:36] [PASSED] 23 VFs
[18:30:36] [PASSED] 24 VFs
[18:30:36] [PASSED] 25 VFs
[18:30:36] [PASSED] 26 VFs
[18:30:36] [PASSED] 27 VFs
[18:30:36] [PASSED] 28 VFs
[18:30:36] [PASSED] 29 VFs
[18:30:36] [PASSED] 30 VFs
[18:30:36] [PASSED] 31 VFs
[18:30:36] [PASSED] 32 VFs
[18:30:36] [PASSED] 33 VFs
[18:30:36] [PASSED] 34 VFs
[18:30:36] [PASSED] 35 VFs
[18:30:36] [PASSED] 36 VFs
[18:30:36] [PASSED] 37 VFs
[18:30:36] [PASSED] 38 VFs
[18:30:36] [PASSED] 39 VFs
[18:30:36] [PASSED] 40 VFs
[18:30:36] [PASSED] 41 VFs
[18:30:36] [PASSED] 42 VFs
[18:30:36] [PASSED] 43 VFs
[18:30:36] [PASSED] 44 VFs
[18:30:36] [PASSED] 45 VFs
[18:30:36] [PASSED] 46 VFs
[18:30:36] [PASSED] 47 VFs
[18:30:36] [PASSED] 48 VFs
[18:30:36] [PASSED] 49 VFs
[18:30:36] [PASSED] 50 VFs
[18:30:36] [PASSED] 51 VFs
[18:30:36] [PASSED] 52 VFs
[18:30:36] [PASSED] 53 VFs
[18:30:36] [PASSED] 54 VFs
[18:30:36] [PASSED] 55 VFs
[18:30:36] [PASSED] 56 VFs
[18:30:36] [PASSED] 57 VFs
[18:30:36] [PASSED] 58 VFs
[18:30:36] [PASSED] 59 VFs
[18:30:36] [PASSED] 60 VFs
[18:30:36] [PASSED] 61 VFs
[18:30:36] [PASSED] 62 VFs
[18:30:36] [PASSED] 63 VFs
[18:30:36] ================= [PASSED] fair_doorbells ==================
[18:30:36] ======================== fair_ggtt  ========================
[18:30:36] [PASSED] 1 VF
[18:30:36] [PASSED] 2 VFs
[18:30:36] [PASSED] 3 VFs
[18:30:36] [PASSED] 4 VFs
[18:30:36] [PASSED] 5 VFs
[18:30:36] [PASSED] 6 VFs
[18:30:36] [PASSED] 7 VFs
[18:30:36] [PASSED] 8 VFs
[18:30:36] [PASSED] 9 VFs
[18:30:36] [PASSED] 10 VFs
[18:30:36] [PASSED] 11 VFs
[18:30:36] [PASSED] 12 VFs
[18:30:36] [PASSED] 13 VFs
[18:30:36] [PASSED] 14 VFs
[18:30:36] [PASSED] 15 VFs
[18:30:36] [PASSED] 16 VFs
[18:30:36] [PASSED] 17 VFs
[18:30:36] [PASSED] 18 VFs
[18:30:36] [PASSED] 19 VFs
[18:30:36] [PASSED] 20 VFs
[18:30:36] [PASSED] 21 VFs
[18:30:36] [PASSED] 22 VFs
[18:30:36] [PASSED] 23 VFs
[18:30:36] [PASSED] 24 VFs
[18:30:36] [PASSED] 25 VFs
[18:30:36] [PASSED] 26 VFs
[18:30:36] [PASSED] 27 VFs
[18:30:36] [PASSED] 28 VFs
[18:30:36] [PASSED] 29 VFs
[18:30:36] [PASSED] 30 VFs
[18:30:36] [PASSED] 31 VFs
[18:30:36] [PASSED] 32 VFs
[18:30:36] [PASSED] 33 VFs
[18:30:36] [PASSED] 34 VFs
[18:30:36] [PASSED] 35 VFs
[18:30:36] [PASSED] 36 VFs
[18:30:36] [PASSED] 37 VFs
[18:30:36] [PASSED] 38 VFs
[18:30:36] [PASSED] 39 VFs
[18:30:36] [PASSED] 40 VFs
[18:30:36] [PASSED] 41 VFs
[18:30:36] [PASSED] 42 VFs
[18:30:36] [PASSED] 43 VFs
[18:30:36] [PASSED] 44 VFs
[18:30:36] [PASSED] 45 VFs
[18:30:36] [PASSED] 46 VFs
[18:30:36] [PASSED] 47 VFs
[18:30:36] [PASSED] 48 VFs
[18:30:36] [PASSED] 49 VFs
[18:30:36] [PASSED] 50 VFs
[18:30:36] [PASSED] 51 VFs
[18:30:36] [PASSED] 52 VFs
[18:30:36] [PASSED] 53 VFs
[18:30:36] [PASSED] 54 VFs
[18:30:36] [PASSED] 55 VFs
[18:30:36] [PASSED] 56 VFs
[18:30:36] [PASSED] 57 VFs
[18:30:36] [PASSED] 58 VFs
[18:30:36] [PASSED] 59 VFs
[18:30:36] [PASSED] 60 VFs
[18:30:36] [PASSED] 61 VFs
[18:30:36] [PASSED] 62 VFs
[18:30:36] [PASSED] 63 VFs
[18:30:36] ==================== [PASSED] fair_ggtt ====================
[18:30:36] ======================== fair_vram  ========================
[18:30:36] [PASSED] 1 VF
[18:30:36] [PASSED] 2 VFs
[18:30:36] [PASSED] 3 VFs
[18:30:36] [PASSED] 4 VFs
[18:30:36] [PASSED] 5 VFs
[18:30:36] [PASSED] 6 VFs
[18:30:36] [PASSED] 7 VFs
[18:30:36] [PASSED] 8 VFs
[18:30:36] [PASSED] 9 VFs
[18:30:36] [PASSED] 10 VFs
[18:30:36] [PASSED] 11 VFs
[18:30:36] [PASSED] 12 VFs
[18:30:36] [PASSED] 13 VFs
[18:30:36] [PASSED] 14 VFs
[18:30:36] [PASSED] 15 VFs
[18:30:36] [PASSED] 16 VFs
[18:30:36] [PASSED] 17 VFs
[18:30:36] [PASSED] 18 VFs
[18:30:36] [PASSED] 19 VFs
[18:30:36] [PASSED] 20 VFs
[18:30:36] [PASSED] 21 VFs
[18:30:36] [PASSED] 22 VFs
[18:30:36] [PASSED] 23 VFs
[18:30:36] [PASSED] 24 VFs
[18:30:36] [PASSED] 25 VFs
[18:30:36] [PASSED] 26 VFs
[18:30:36] [PASSED] 27 VFs
[18:30:36] [PASSED] 28 VFs
[18:30:36] [PASSED] 29 VFs
[18:30:36] [PASSED] 30 VFs
[18:30:36] [PASSED] 31 VFs
[18:30:36] [PASSED] 32 VFs
[18:30:36] [PASSED] 33 VFs
[18:30:36] [PASSED] 34 VFs
[18:30:36] [PASSED] 35 VFs
[18:30:36] [PASSED] 36 VFs
[18:30:36] [PASSED] 37 VFs
[18:30:36] [PASSED] 38 VFs
[18:30:36] [PASSED] 39 VFs
[18:30:36] [PASSED] 40 VFs
[18:30:36] [PASSED] 41 VFs
[18:30:36] [PASSED] 42 VFs
[18:30:36] [PASSED] 43 VFs
[18:30:36] [PASSED] 44 VFs
[18:30:36] [PASSED] 45 VFs
[18:30:36] [PASSED] 46 VFs
[18:30:36] [PASSED] 47 VFs
[18:30:36] [PASSED] 48 VFs
[18:30:36] [PASSED] 49 VFs
[18:30:36] [PASSED] 50 VFs
[18:30:36] [PASSED] 51 VFs
[18:30:36] [PASSED] 52 VFs
[18:30:36] [PASSED] 53 VFs
[18:30:36] [PASSED] 54 VFs
[18:30:37] [PASSED] 55 VFs
[18:30:37] [PASSED] 56 VFs
[18:30:37] [PASSED] 57 VFs
[18:30:37] [PASSED] 58 VFs
[18:30:37] [PASSED] 59 VFs
[18:30:37] [PASSED] 60 VFs
[18:30:37] [PASSED] 61 VFs
[18:30:37] [PASSED] 62 VFs
[18:30:37] [PASSED] 63 VFs
[18:30:37] ==================== [PASSED] fair_vram ====================
[18:30:37] ================== [PASSED] pf_gt_config ===================
[18:30:37] ===================== lmtt (1 subtest) =====================
[18:30:37] ======================== test_ops  =========================
[18:30:37] [PASSED] 2-level
[18:30:37] [PASSED] multi-level
[18:30:37] ==================== [PASSED] test_ops =====================
[18:30:37] ====================== [PASSED] lmtt =======================
[18:30:37] ================= pf_service (11 subtests) =================
[18:30:37] [PASSED] pf_negotiate_any
[18:30:37] [PASSED] pf_negotiate_base_match
[18:30:37] [PASSED] pf_negotiate_base_newer
[18:30:37] [PASSED] pf_negotiate_base_next
[18:30:37] [SKIPPED] pf_negotiate_base_older
[18:30:37] [PASSED] pf_negotiate_base_prev
[18:30:37] [PASSED] pf_negotiate_latest_match
[18:30:37] [PASSED] pf_negotiate_latest_newer
[18:30:37] [PASSED] pf_negotiate_latest_next
[18:30:37] [SKIPPED] pf_negotiate_latest_older
[18:30:37] [SKIPPED] pf_negotiate_latest_prev
[18:30:37] =================== [PASSED] pf_service ====================
[18:30:37] ================= xe_guc_g2g (2 subtests) ==================
[18:30:37] ============== xe_live_guc_g2g_kunit_default  ==============
[18:30:37] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[18:30:37] ============== xe_live_guc_g2g_kunit_allmem  ===============
[18:30:37] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[18:30:37] =================== [SKIPPED] xe_guc_g2g ===================
[18:30:37] =================== xe_mocs (2 subtests) ===================
[18:30:37] ================ xe_live_mocs_kernel_kunit  ================
[18:30:37] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[18:30:37] ================ xe_live_mocs_reset_kunit  =================
[18:30:37] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[18:30:37] ==================== [SKIPPED] xe_mocs =====================
[18:30:37] ================= xe_migrate (2 subtests) ==================
[18:30:37] ================= xe_migrate_sanity_kunit  =================
[18:30:37] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[18:30:37] ================== xe_validate_ccs_kunit  ==================
[18:30:37] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[18:30:37] =================== [SKIPPED] xe_migrate ===================
[18:30:37] ================== xe_dma_buf (1 subtest) ==================
[18:30:37] ==================== xe_dma_buf_kunit  =====================
[18:30:37] ================ [SKIPPED] xe_dma_buf_kunit ================
[18:30:37] =================== [SKIPPED] xe_dma_buf ===================
[18:30:37] ================= xe_bo_shrink (1 subtest) =================
[18:30:37] =================== xe_bo_shrink_kunit  ====================
[18:30:37] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[18:30:37] ================== [SKIPPED] xe_bo_shrink ==================
[18:30:37] ==================== xe_bo (2 subtests) ====================
[18:30:37] ================== xe_ccs_migrate_kunit  ===================
[18:30:37] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[18:30:37] ==================== xe_bo_evict_kunit  ====================
[18:30:37] =============== [SKIPPED] xe_bo_evict_kunit ================
[18:30:37] ===================== [SKIPPED] xe_bo ======================
[18:30:37] ==================== args (13 subtests) ====================
[18:30:37] [PASSED] count_args_test
[18:30:37] [PASSED] call_args_example
[18:30:37] [PASSED] call_args_test
[18:30:37] [PASSED] drop_first_arg_example
[18:30:37] [PASSED] drop_first_arg_test
[18:30:37] [PASSED] first_arg_example
[18:30:37] [PASSED] first_arg_test
[18:30:37] [PASSED] last_arg_example
[18:30:37] [PASSED] last_arg_test
[18:30:37] [PASSED] pick_arg_example
[18:30:37] [PASSED] if_args_example
[18:30:37] [PASSED] if_args_test
[18:30:37] [PASSED] sep_comma_example
[18:30:37] ====================== [PASSED] args =======================
[18:30:37] =================== xe_pci (3 subtests) ====================
[18:30:37] ==================== check_graphics_ip  ====================
[18:30:37] [PASSED] 12.00 Xe_LP
[18:30:37] [PASSED] 12.10 Xe_LP+
[18:30:37] [PASSED] 12.55 Xe_HPG
[18:30:37] [PASSED] 12.60 Xe_HPC
[18:30:37] [PASSED] 12.70 Xe_LPG
[18:30:37] [PASSED] 12.71 Xe_LPG
[18:30:37] [PASSED] 12.74 Xe_LPG+
[18:30:37] [PASSED] 20.01 Xe2_HPG
[18:30:37] [PASSED] 20.02 Xe2_HPG
[18:30:37] [PASSED] 20.04 Xe2_LPG
[18:30:37] [PASSED] 30.00 Xe3_LPG
[18:30:37] [PASSED] 30.01 Xe3_LPG
[18:30:37] [PASSED] 30.03 Xe3_LPG
[18:30:37] [PASSED] 30.04 Xe3_LPG
[18:30:37] [PASSED] 30.05 Xe3_LPG
[18:30:37] [PASSED] 35.10 Xe3p_LPG
[18:30:37] [PASSED] 35.11 Xe3p_XPC
[18:30:37] ================ [PASSED] check_graphics_ip ================
[18:30:37] ===================== check_media_ip  ======================
[18:30:37] [PASSED] 12.00 Xe_M
[18:30:37] [PASSED] 12.55 Xe_HPM
[18:30:37] [PASSED] 13.00 Xe_LPM+
[18:30:37] [PASSED] 13.01 Xe2_HPM
[18:30:37] [PASSED] 20.00 Xe2_LPM
[18:30:37] [PASSED] 30.00 Xe3_LPM
[18:30:37] [PASSED] 30.02 Xe3_LPM
[18:30:37] [PASSED] 35.00 Xe3p_LPM
[18:30:37] [PASSED] 35.03 Xe3p_HPM
[18:30:37] ================= [PASSED] check_media_ip ==================
[18:30:37] =================== check_platform_desc  ===================
[18:30:37] [PASSED] 0x9A60 (TIGERLAKE)
[18:30:37] [PASSED] 0x9A68 (TIGERLAKE)
[18:30:37] [PASSED] 0x9A70 (TIGERLAKE)
[18:30:37] [PASSED] 0x9A40 (TIGERLAKE)
[18:30:37] [PASSED] 0x9A49 (TIGERLAKE)
[18:30:37] [PASSED] 0x9A59 (TIGERLAKE)
[18:30:37] [PASSED] 0x9A78 (TIGERLAKE)
[18:30:37] [PASSED] 0x9AC0 (TIGERLAKE)
[18:30:37] [PASSED] 0x9AC9 (TIGERLAKE)
[18:30:37] [PASSED] 0x9AD9 (TIGERLAKE)
[18:30:37] [PASSED] 0x9AF8 (TIGERLAKE)
[18:30:37] [PASSED] 0x4C80 (ROCKETLAKE)
[18:30:37] [PASSED] 0x4C8A (ROCKETLAKE)
[18:30:37] [PASSED] 0x4C8B (ROCKETLAKE)
[18:30:37] [PASSED] 0x4C8C (ROCKETLAKE)
[18:30:37] [PASSED] 0x4C90 (ROCKETLAKE)
[18:30:37] [PASSED] 0x4C9A (ROCKETLAKE)
[18:30:37] [PASSED] 0x4680 (ALDERLAKE_S)
[18:30:37] [PASSED] 0x4682 (ALDERLAKE_S)
[18:30:37] [PASSED] 0x4688 (ALDERLAKE_S)
[18:30:37] [PASSED] 0x468A (ALDERLAKE_S)
[18:30:37] [PASSED] 0x468B (ALDERLAKE_S)
[18:30:37] [PASSED] 0x4690 (ALDERLAKE_S)
[18:30:37] [PASSED] 0x4692 (ALDERLAKE_S)
[18:30:37] [PASSED] 0x4693 (ALDERLAKE_S)
[18:30:37] [PASSED] 0x46A0 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46A1 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46A2 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46A3 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46A6 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46A8 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46AA (ALDERLAKE_P)
[18:30:37] [PASSED] 0x462A (ALDERLAKE_P)
[18:30:37] [PASSED] 0x4626 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x4628 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46B0 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46B1 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46B2 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46B3 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46C0 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46C1 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46C2 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46C3 (ALDERLAKE_P)
[18:30:37] [PASSED] 0x46D0 (ALDERLAKE_N)
[18:30:37] [PASSED] 0x46D1 (ALDERLAKE_N)
[18:30:37] [PASSED] 0x46D2 (ALDERLAKE_N)
[18:30:37] [PASSED] 0x46D3 (ALDERLAKE_N)
[18:30:37] [PASSED] 0x46D4 (ALDERLAKE_N)
[18:30:37] [PASSED] 0xA721 (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA7A1 (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA7A9 (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA7AC (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA7AD (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA720 (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA7A0 (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA7A8 (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA7AA (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA7AB (ALDERLAKE_P)
[18:30:37] [PASSED] 0xA780 (ALDERLAKE_S)
[18:30:37] [PASSED] 0xA781 (ALDERLAKE_S)
[18:30:37] [PASSED] 0xA782 (ALDERLAKE_S)
[18:30:37] [PASSED] 0xA783 (ALDERLAKE_S)
[18:30:37] [PASSED] 0xA788 (ALDERLAKE_S)
[18:30:37] [PASSED] 0xA789 (ALDERLAKE_S)
[18:30:37] [PASSED] 0xA78A (ALDERLAKE_S)
[18:30:37] [PASSED] 0xA78B (ALDERLAKE_S)
[18:30:37] [PASSED] 0x4905 (DG1)
[18:30:37] [PASSED] 0x4906 (DG1)
[18:30:37] [PASSED] 0x4907 (DG1)
[18:30:37] [PASSED] 0x4908 (DG1)
[18:30:37] [PASSED] 0x4909 (DG1)
[18:30:37] [PASSED] 0x56C0 (DG2)
[18:30:37] [PASSED] 0x56C2 (DG2)
[18:30:37] [PASSED] 0x56C1 (DG2)
[18:30:37] [PASSED] 0x7D51 (METEORLAKE)
[18:30:37] [PASSED] 0x7DD1 (METEORLAKE)
[18:30:37] [PASSED] 0x7D41 (METEORLAKE)
[18:30:37] [PASSED] 0x7D67 (METEORLAKE)
[18:30:37] [PASSED] 0xB640 (METEORLAKE)
[18:30:37] [PASSED] 0x56A0 (DG2)
[18:30:37] [PASSED] 0x56A1 (DG2)
[18:30:37] [PASSED] 0x56A2 (DG2)
[18:30:37] [PASSED] 0x56BE (DG2)
[18:30:37] [PASSED] 0x56BF (DG2)
[18:30:37] [PASSED] 0x5690 (DG2)
[18:30:37] [PASSED] 0x5691 (DG2)
[18:30:37] [PASSED] 0x5692 (DG2)
[18:30:37] [PASSED] 0x56A5 (DG2)
[18:30:37] [PASSED] 0x56A6 (DG2)
[18:30:37] [PASSED] 0x56B0 (DG2)
[18:30:37] [PASSED] 0x56B1 (DG2)
[18:30:37] [PASSED] 0x56BA (DG2)
[18:30:37] [PASSED] 0x56BB (DG2)
[18:30:37] [PASSED] 0x56BC (DG2)
[18:30:37] [PASSED] 0x56BD (DG2)
[18:30:37] [PASSED] 0x5693 (DG2)
[18:30:37] [PASSED] 0x5694 (DG2)
[18:30:37] [PASSED] 0x5695 (DG2)
[18:30:37] [PASSED] 0x56A3 (DG2)
[18:30:37] [PASSED] 0x56A4 (DG2)
[18:30:37] [PASSED] 0x56B2 (DG2)
[18:30:37] [PASSED] 0x56B3 (DG2)
[18:30:37] [PASSED] 0x5696 (DG2)
[18:30:37] [PASSED] 0x5697 (DG2)
[18:30:37] [PASSED] 0xB69 (PVC)
[18:30:37] [PASSED] 0xB6E (PVC)
[18:30:37] [PASSED] 0xBD4 (PVC)
[18:30:37] [PASSED] 0xBD5 (PVC)
[18:30:37] [PASSED] 0xBD6 (PVC)
[18:30:37] [PASSED] 0xBD7 (PVC)
[18:30:37] [PASSED] 0xBD8 (PVC)
[18:30:37] [PASSED] 0xBD9 (PVC)
[18:30:37] [PASSED] 0xBDA (PVC)
[18:30:37] [PASSED] 0xBDB (PVC)
[18:30:37] [PASSED] 0xBE0 (PVC)
[18:30:37] [PASSED] 0xBE1 (PVC)
[18:30:37] [PASSED] 0xBE5 (PVC)
[18:30:37] [PASSED] 0x7D40 (METEORLAKE)
[18:30:37] [PASSED] 0x7D45 (METEORLAKE)
[18:30:37] [PASSED] 0x7D55 (METEORLAKE)
[18:30:37] [PASSED] 0x7D60 (METEORLAKE)
[18:30:37] [PASSED] 0x7DD5 (METEORLAKE)
[18:30:37] [PASSED] 0x6420 (LUNARLAKE)
[18:30:37] [PASSED] 0x64A0 (LUNARLAKE)
[18:30:37] [PASSED] 0x64B0 (LUNARLAKE)
[18:30:37] [PASSED] 0xE202 (BATTLEMAGE)
[18:30:37] [PASSED] 0xE209 (BATTLEMAGE)
[18:30:37] [PASSED] 0xE20B (BATTLEMAGE)
[18:30:37] [PASSED] 0xE20C (BATTLEMAGE)
[18:30:37] [PASSED] 0xE20D (BATTLEMAGE)
[18:30:37] [PASSED] 0xE210 (BATTLEMAGE)
[18:30:37] [PASSED] 0xE211 (BATTLEMAGE)
[18:30:37] [PASSED] 0xE212 (BATTLEMAGE)
[18:30:37] [PASSED] 0xE216 (BATTLEMAGE)
[18:30:37] [PASSED] 0xE220 (BATTLEMAGE)
[18:30:37] [PASSED] 0xE221 (BATTLEMAGE)
[18:30:37] [PASSED] 0xE222 (BATTLEMAGE)
[18:30:37] [PASSED] 0xE223 (BATTLEMAGE)
[18:30:37] [PASSED] 0xB080 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB081 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB082 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB083 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB084 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB085 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB086 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB087 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB08F (PANTHERLAKE)
[18:30:37] [PASSED] 0xB090 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB0A0 (PANTHERLAKE)
[18:30:37] [PASSED] 0xB0B0 (PANTHERLAKE)
[18:30:37] [PASSED] 0xFD80 (PANTHERLAKE)
[18:30:37] [PASSED] 0xFD81 (PANTHERLAKE)
[18:30:37] [PASSED] 0xD740 (NOVALAKE_S)
[18:30:37] [PASSED] 0xD741 (NOVALAKE_S)
[18:30:37] [PASSED] 0xD742 (NOVALAKE_S)
[18:30:37] [PASSED] 0xD743 (NOVALAKE_S)
[18:30:37] [PASSED] 0xD744 (NOVALAKE_S)
[18:30:37] [PASSED] 0xD745 (NOVALAKE_S)
[18:30:37] [PASSED] 0x674C (CRESCENTISLAND)
[18:30:37] [PASSED] 0xD750 (NOVALAKE_P)
[18:30:37] [PASSED] 0xD751 (NOVALAKE_P)
[18:30:37] [PASSED] 0xD752 (NOVALAKE_P)
[18:30:37] [PASSED] 0xD753 (NOVALAKE_P)
[18:30:37] [PASSED] 0xD754 (NOVALAKE_P)
[18:30:37] [PASSED] 0xD755 (NOVALAKE_P)
[18:30:37] [PASSED] 0xD756 (NOVALAKE_P)
[18:30:37] [PASSED] 0xD757 (NOVALAKE_P)
[18:30:37] [PASSED] 0xD75F (NOVALAKE_P)
[18:30:37] =============== [PASSED] check_platform_desc ===============
[18:30:37] ===================== [PASSED] xe_pci ======================
[18:30:37] =================== xe_rtp (2 subtests) ====================
[18:30:37] =============== xe_rtp_process_to_sr_tests  ================
[18:30:37] [PASSED] coalesce-same-reg
[18:30:37] [PASSED] no-match-no-add
[18:30:37] [PASSED] match-or
[18:30:37] [PASSED] match-or-xfail
[18:30:37] [PASSED] no-match-no-add-multiple-rules
[18:30:37] [PASSED] two-regs-two-entries
[18:30:37] [PASSED] clr-one-set-other
[18:30:37] [PASSED] set-field
[18:30:37] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[18:30:37] [PASSED] conflict-not-disjoint
[18:30:37] [PASSED] conflict-reg-type
[18:30:37] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[18:30:37] ================== xe_rtp_process_tests  ===================
[18:30:37] [PASSED] active1
[18:30:37] [PASSED] active2
[18:30:37] [PASSED] active-inactive
[18:30:37] [PASSED] inactive-active
[18:30:37] [PASSED] inactive-1st_or_active-inactive
[18:30:37] [PASSED] inactive-2nd_or_active-inactive
[18:30:37] [PASSED] inactive-last_or_active-inactive
[18:30:37] [PASSED] inactive-no_or_active-inactive
[18:30:37] ============== [PASSED] xe_rtp_process_tests ===============
[18:30:37] ===================== [PASSED] xe_rtp ======================
[18:30:37] ==================== xe_wa (1 subtest) =====================
[18:30:37] ======================== xe_wa_gt  =========================
[18:30:37] [PASSED] TIGERLAKE B0
[18:30:37] [PASSED] DG1 A0
[18:30:37] [PASSED] DG1 B0
[18:30:37] [PASSED] ALDERLAKE_S A0
[18:30:37] [PASSED] ALDERLAKE_S B0
[18:30:37] [PASSED] ALDERLAKE_S C0
[18:30:37] [PASSED] ALDERLAKE_S D0
[18:30:37] [PASSED] ALDERLAKE_P A0
[18:30:37] [PASSED] ALDERLAKE_P B0
[18:30:37] [PASSED] ALDERLAKE_P C0
[18:30:37] [PASSED] ALDERLAKE_S RPLS D0
[18:30:37] [PASSED] ALDERLAKE_P RPLU E0
[18:30:37] [PASSED] DG2 G10 C0
[18:30:37] [PASSED] DG2 G11 B1
[18:30:37] [PASSED] DG2 G12 A1
[18:30:37] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:30:37] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[18:30:37] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[18:30:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[18:30:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[18:30:37] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[18:30:37] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[18:30:37] ==================== [PASSED] xe_wa_gt =====================
[18:30:37] ====================== [PASSED] xe_wa ======================
[18:30:37] ============================================================
[18:30:37] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[18:30:37] Elapsed time: 35.561s total, 4.298s configuring, 30.646s building, 0.609s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[18:30:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:30:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:31:02] Starting KUnit Kernel (1/1)...
[18:31:02] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:31:03] ============ drm_test_pick_cmdline (2 subtests) ============
[18:31:03] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[18:31:03] =============== drm_test_pick_cmdline_named  ===============
[18:31:03] [PASSED] NTSC
[18:31:03] [PASSED] NTSC-J
[18:31:03] [PASSED] PAL
[18:31:03] [PASSED] PAL-M
[18:31:03] =========== [PASSED] drm_test_pick_cmdline_named ===========
[18:31:03] ============== [PASSED] drm_test_pick_cmdline ==============
[18:31:03] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[18:31:03] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[18:31:03] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[18:31:03] =========== drm_validate_clone_mode (2 subtests) ===========
[18:31:03] ============== drm_test_check_in_clone_mode  ===============
[18:31:03] [PASSED] in_clone_mode
[18:31:03] [PASSED] not_in_clone_mode
[18:31:03] ========== [PASSED] drm_test_check_in_clone_mode ===========
[18:31:03] =============== drm_test_check_valid_clones  ===============
[18:31:03] [PASSED] not_in_clone_mode
[18:31:03] [PASSED] valid_clone
[18:31:03] [PASSED] invalid_clone
[18:31:03] =========== [PASSED] drm_test_check_valid_clones ===========
[18:31:03] ============= [PASSED] drm_validate_clone_mode =============
[18:31:03] ============= drm_validate_modeset (1 subtest) =============
[18:31:03] [PASSED] drm_test_check_connector_changed_modeset
[18:31:03] ============== [PASSED] drm_validate_modeset ===============
[18:31:03] ====== drm_test_bridge_get_current_state (2 subtests) ======
[18:31:03] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[18:31:03] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[18:31:03] ======== [PASSED] drm_test_bridge_get_current_state ========
[18:31:03] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[18:31:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[18:31:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[18:31:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[18:31:03] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[18:31:03] ============== drm_bridge_alloc (2 subtests) ===============
[18:31:03] [PASSED] drm_test_drm_bridge_alloc_basic
[18:31:03] [PASSED] drm_test_drm_bridge_alloc_get_put
[18:31:03] ================ [PASSED] drm_bridge_alloc =================
[18:31:03] ============= drm_cmdline_parser (40 subtests) =============
[18:31:03] [PASSED] drm_test_cmdline_force_d_only
[18:31:03] [PASSED] drm_test_cmdline_force_D_only_dvi
[18:31:03] [PASSED] drm_test_cmdline_force_D_only_hdmi
[18:31:03] [PASSED] drm_test_cmdline_force_D_only_not_digital
[18:31:03] [PASSED] drm_test_cmdline_force_e_only
[18:31:03] [PASSED] drm_test_cmdline_res
[18:31:03] [PASSED] drm_test_cmdline_res_vesa
[18:31:03] [PASSED] drm_test_cmdline_res_vesa_rblank
[18:31:03] [PASSED] drm_test_cmdline_res_rblank
[18:31:03] [PASSED] drm_test_cmdline_res_bpp
[18:31:03] [PASSED] drm_test_cmdline_res_refresh
[18:31:03] [PASSED] drm_test_cmdline_res_bpp_refresh
[18:31:03] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[18:31:03] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[18:31:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[18:31:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[18:31:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[18:31:03] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[18:31:03] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[18:31:03] [PASSED] drm_test_cmdline_res_margins_force_on
[18:31:03] [PASSED] drm_test_cmdline_res_vesa_margins
[18:31:03] [PASSED] drm_test_cmdline_name
[18:31:03] [PASSED] drm_test_cmdline_name_bpp
[18:31:03] [PASSED] drm_test_cmdline_name_option
[18:31:03] [PASSED] drm_test_cmdline_name_bpp_option
[18:31:03] [PASSED] drm_test_cmdline_rotate_0
[18:31:03] [PASSED] drm_test_cmdline_rotate_90
[18:31:03] [PASSED] drm_test_cmdline_rotate_180
[18:31:03] [PASSED] drm_test_cmdline_rotate_270
[18:31:03] [PASSED] drm_test_cmdline_hmirror
[18:31:03] [PASSED] drm_test_cmdline_vmirror
[18:31:03] [PASSED] drm_test_cmdline_margin_options
[18:31:03] [PASSED] drm_test_cmdline_multiple_options
[18:31:03] [PASSED] drm_test_cmdline_bpp_extra_and_option
[18:31:03] [PASSED] drm_test_cmdline_extra_and_option
[18:31:03] [PASSED] drm_test_cmdline_freestanding_options
[18:31:03] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[18:31:03] [PASSED] drm_test_cmdline_panel_orientation
[18:31:03] ================ drm_test_cmdline_invalid  =================
[18:31:03] [PASSED] margin_only
[18:31:03] [PASSED] interlace_only
[18:31:03] [PASSED] res_missing_x
[18:31:03] [PASSED] res_missing_y
[18:31:03] [PASSED] res_bad_y
[18:31:03] [PASSED] res_missing_y_bpp
[18:31:03] [PASSED] res_bad_bpp
[18:31:03] [PASSED] res_bad_refresh
[18:31:03] [PASSED] res_bpp_refresh_force_on_off
[18:31:03] [PASSED] res_invalid_mode
[18:31:03] [PASSED] res_bpp_wrong_place_mode
[18:31:03] [PASSED] name_bpp_refresh
[18:31:03] [PASSED] name_refresh
[18:31:03] [PASSED] name_refresh_wrong_mode
[18:31:03] [PASSED] name_refresh_invalid_mode
[18:31:03] [PASSED] rotate_multiple
[18:31:03] [PASSED] rotate_invalid_val
[18:31:03] [PASSED] rotate_truncated
[18:31:03] [PASSED] invalid_option
[18:31:03] [PASSED] invalid_tv_option
[18:31:03] [PASSED] truncated_tv_option
[18:31:03] ============ [PASSED] drm_test_cmdline_invalid =============
[18:31:03] =============== drm_test_cmdline_tv_options  ===============
[18:31:03] [PASSED] NTSC
[18:31:03] [PASSED] NTSC_443
[18:31:03] [PASSED] NTSC_J
[18:31:03] [PASSED] PAL
[18:31:03] [PASSED] PAL_M
[18:31:03] [PASSED] PAL_N
[18:31:03] [PASSED] SECAM
[18:31:03] [PASSED] MONO_525
[18:31:03] [PASSED] MONO_625
[18:31:03] =========== [PASSED] drm_test_cmdline_tv_options ===========
[18:31:03] =============== [PASSED] drm_cmdline_parser ================
[18:31:03] ========== drmm_connector_hdmi_init (20 subtests) ==========
[18:31:03] [PASSED] drm_test_connector_hdmi_init_valid
[18:31:03] [PASSED] drm_test_connector_hdmi_init_bpc_8
[18:31:03] [PASSED] drm_test_connector_hdmi_init_bpc_10
[18:31:03] [PASSED] drm_test_connector_hdmi_init_bpc_12
[18:31:03] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[18:31:03] [PASSED] drm_test_connector_hdmi_init_bpc_null
[18:31:03] [PASSED] drm_test_connector_hdmi_init_formats_empty
[18:31:03] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[18:31:03] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[18:31:03] [PASSED] supported_formats=0x9 yuv420_allowed=1
[18:31:03] [PASSED] supported_formats=0x9 yuv420_allowed=0
[18:31:03] [PASSED] supported_formats=0x3 yuv420_allowed=1
[18:31:03] [PASSED] supported_formats=0x3 yuv420_allowed=0
[18:31:03] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[18:31:03] [PASSED] drm_test_connector_hdmi_init_null_ddc
[18:31:03] [PASSED] drm_test_connector_hdmi_init_null_product
[18:31:03] [PASSED] drm_test_connector_hdmi_init_null_vendor
[18:31:03] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[18:31:03] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[18:31:03] [PASSED] drm_test_connector_hdmi_init_product_valid
[18:31:03] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[18:31:03] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[18:31:03] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[18:31:03] ========= drm_test_connector_hdmi_init_type_valid  =========
[18:31:03] [PASSED] HDMI-A
[18:31:03] [PASSED] HDMI-B
[18:31:03] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[18:31:03] ======== drm_test_connector_hdmi_init_type_invalid  ========
[18:31:03] [PASSED] Unknown
[18:31:03] [PASSED] VGA
[18:31:03] [PASSED] DVI-I
[18:31:03] [PASSED] DVI-D
[18:31:03] [PASSED] DVI-A
[18:31:03] [PASSED] Composite
[18:31:03] [PASSED] SVIDEO
[18:31:03] [PASSED] LVDS
[18:31:03] [PASSED] Component
[18:31:03] [PASSED] DIN
[18:31:03] [PASSED] DP
[18:31:03] [PASSED] TV
[18:31:03] [PASSED] eDP
[18:31:03] [PASSED] Virtual
[18:31:03] [PASSED] DSI
[18:31:03] [PASSED] DPI
[18:31:03] [PASSED] Writeback
[18:31:03] [PASSED] SPI
[18:31:03] [PASSED] USB
[18:31:03] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[18:31:03] ============ [PASSED] drmm_connector_hdmi_init =============
[18:31:03] ============= drmm_connector_init (3 subtests) =============
[18:31:03] [PASSED] drm_test_drmm_connector_init
[18:31:03] [PASSED] drm_test_drmm_connector_init_null_ddc
[18:31:03] ========= drm_test_drmm_connector_init_type_valid  =========
[18:31:03] [PASSED] Unknown
[18:31:03] [PASSED] VGA
[18:31:03] [PASSED] DVI-I
[18:31:03] [PASSED] DVI-D
[18:31:03] [PASSED] DVI-A
[18:31:03] [PASSED] Composite
[18:31:03] [PASSED] SVIDEO
[18:31:03] [PASSED] LVDS
[18:31:03] [PASSED] Component
[18:31:03] [PASSED] DIN
[18:31:03] [PASSED] DP
[18:31:03] [PASSED] HDMI-A
[18:31:03] [PASSED] HDMI-B
[18:31:03] [PASSED] TV
[18:31:03] [PASSED] eDP
[18:31:03] [PASSED] Virtual
[18:31:03] [PASSED] DSI
[18:31:03] [PASSED] DPI
[18:31:03] [PASSED] Writeback
[18:31:03] [PASSED] SPI
[18:31:03] [PASSED] USB
[18:31:03] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[18:31:03] =============== [PASSED] drmm_connector_init ===============
[18:31:03] ========= drm_connector_dynamic_init (6 subtests) ==========
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_init
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_init_properties
[18:31:03] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[18:31:03] [PASSED] Unknown
[18:31:03] [PASSED] VGA
[18:31:03] [PASSED] DVI-I
[18:31:03] [PASSED] DVI-D
[18:31:03] [PASSED] DVI-A
[18:31:03] [PASSED] Composite
[18:31:03] [PASSED] SVIDEO
[18:31:03] [PASSED] LVDS
[18:31:03] [PASSED] Component
[18:31:03] [PASSED] DIN
[18:31:03] [PASSED] DP
[18:31:03] [PASSED] HDMI-A
[18:31:03] [PASSED] HDMI-B
[18:31:03] [PASSED] TV
[18:31:03] [PASSED] eDP
[18:31:03] [PASSED] Virtual
[18:31:03] [PASSED] DSI
[18:31:03] [PASSED] DPI
[18:31:03] [PASSED] Writeback
[18:31:03] [PASSED] SPI
[18:31:03] [PASSED] USB
[18:31:03] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[18:31:03] ======== drm_test_drm_connector_dynamic_init_name  =========
[18:31:03] [PASSED] Unknown
[18:31:03] [PASSED] VGA
[18:31:03] [PASSED] DVI-I
[18:31:03] [PASSED] DVI-D
[18:31:03] [PASSED] DVI-A
[18:31:03] [PASSED] Composite
[18:31:03] [PASSED] SVIDEO
[18:31:03] [PASSED] LVDS
[18:31:03] [PASSED] Component
[18:31:03] [PASSED] DIN
[18:31:03] [PASSED] DP
[18:31:03] [PASSED] HDMI-A
[18:31:03] [PASSED] HDMI-B
[18:31:03] [PASSED] TV
[18:31:03] [PASSED] eDP
[18:31:03] [PASSED] Virtual
[18:31:03] [PASSED] DSI
[18:31:03] [PASSED] DPI
[18:31:03] [PASSED] Writeback
[18:31:03] [PASSED] SPI
[18:31:03] [PASSED] USB
[18:31:03] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[18:31:03] =========== [PASSED] drm_connector_dynamic_init ============
[18:31:03] ==== drm_connector_dynamic_register_early (4 subtests) =====
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[18:31:03] ====== [PASSED] drm_connector_dynamic_register_early =======
[18:31:03] ======= drm_connector_dynamic_register (7 subtests) ========
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[18:31:03] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[18:31:03] ========= [PASSED] drm_connector_dynamic_register ==========
[18:31:03] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[18:31:03] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[18:31:03] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[18:31:03] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[18:31:03] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[18:31:03] ========== drm_test_get_tv_mode_from_name_valid  ===========
[18:31:03] [PASSED] NTSC
[18:31:03] [PASSED] NTSC-443
[18:31:03] [PASSED] NTSC-J
[18:31:03] [PASSED] PAL
[18:31:03] [PASSED] PAL-M
[18:31:03] [PASSED] PAL-N
[18:31:03] [PASSED] SECAM
[18:31:03] [PASSED] Mono
[18:31:03] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[18:31:03] [PASSED] drm_test_get_tv_mode_from_name_truncated
[18:31:03] ============ [PASSED] drm_get_tv_mode_from_name ============
[18:31:03] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[18:31:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[18:31:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[18:31:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[18:31:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[18:31:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[18:31:03] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[18:31:03] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[18:31:03] [PASSED] VIC 96
[18:31:03] [PASSED] VIC 97
[18:31:03] [PASSED] VIC 101
[18:31:03] [PASSED] VIC 102
[18:31:03] [PASSED] VIC 106
[18:31:03] [PASSED] VIC 107
[18:31:03] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[18:31:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[18:31:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[18:31:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[18:31:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[18:31:03] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[18:31:03] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[18:31:03] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[18:31:03] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[18:31:03] [PASSED] Automatic
[18:31:03] [PASSED] Full
[18:31:03] [PASSED] Limited 16:235
[18:31:03] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[18:31:03] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[18:31:03] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[18:31:03] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[18:31:03] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[18:31:03] [PASSED] RGB
[18:31:03] [PASSED] YUV 4:2:0
[18:31:03] [PASSED] YUV 4:2:2
[18:31:03] [PASSED] YUV 4:4:4
[18:31:03] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[18:31:03] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[18:31:03] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[18:31:03] ============= drm_damage_helper (21 subtests) ==============
[18:31:03] [PASSED] drm_test_damage_iter_no_damage
[18:31:03] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[18:31:03] [PASSED] drm_test_damage_iter_no_damage_src_moved
[18:31:03] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[18:31:03] [PASSED] drm_test_damage_iter_no_damage_not_visible
[18:31:03] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[18:31:03] [PASSED] drm_test_damage_iter_no_damage_no_fb
[18:31:03] [PASSED] drm_test_damage_iter_simple_damage
[18:31:03] [PASSED] drm_test_damage_iter_single_damage
[18:31:03] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[18:31:03] [PASSED] drm_test_damage_iter_single_damage_outside_src
[18:31:03] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[18:31:03] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[18:31:03] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[18:31:03] [PASSED] drm_test_damage_iter_single_damage_src_moved
[18:31:03] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[18:31:03] [PASSED] drm_test_damage_iter_damage
[18:31:03] [PASSED] drm_test_damage_iter_damage_one_intersect
[18:31:03] [PASSED] drm_test_damage_iter_damage_one_outside
[18:31:03] [PASSED] drm_test_damage_iter_damage_src_moved
[18:31:03] [PASSED] drm_test_damage_iter_damage_not_visible
[18:31:03] ================ [PASSED] drm_damage_helper ================
[18:31:03] ============== drm_dp_mst_helper (3 subtests) ==============
[18:31:03] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[18:31:03] [PASSED] Clock 154000 BPP 30 DSC disabled
[18:31:03] [PASSED] Clock 234000 BPP 30 DSC disabled
[18:31:03] [PASSED] Clock 297000 BPP 24 DSC disabled
[18:31:03] [PASSED] Clock 332880 BPP 24 DSC enabled
[18:31:03] [PASSED] Clock 324540 BPP 24 DSC enabled
[18:31:03] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[18:31:03] ============== drm_test_dp_mst_calc_pbn_div  ===============
[18:31:03] [PASSED] Link rate 2000000 lane count 4
[18:31:03] [PASSED] Link rate 2000000 lane count 2
[18:31:03] [PASSED] Link rate 2000000 lane count 1
[18:31:03] [PASSED] Link rate 1350000 lane count 4
[18:31:03] [PASSED] Link rate 1350000 lane count 2
[18:31:03] [PASSED] Link rate 1350000 lane count 1
[18:31:03] [PASSED] Link rate 1000000 lane count 4
[18:31:03] [PASSED] Link rate 1000000 lane count 2
[18:31:03] [PASSED] Link rate 1000000 lane count 1
[18:31:03] [PASSED] Link rate 810000 lane count 4
[18:31:03] [PASSED] Link rate 810000 lane count 2
[18:31:03] [PASSED] Link rate 810000 lane count 1
[18:31:03] [PASSED] Link rate 540000 lane count 4
[18:31:03] [PASSED] Link rate 540000 lane count 2
[18:31:03] [PASSED] Link rate 540000 lane count 1
[18:31:03] [PASSED] Link rate 270000 lane count 4
[18:31:03] [PASSED] Link rate 270000 lane count 2
[18:31:03] [PASSED] Link rate 270000 lane count 1
[18:31:03] [PASSED] Link rate 162000 lane count 4
[18:31:03] [PASSED] Link rate 162000 lane count 2
[18:31:03] [PASSED] Link rate 162000 lane count 1
[18:31:03] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[18:31:03] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[18:31:03] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[18:31:03] [PASSED] DP_POWER_UP_PHY with port number
[18:31:03] [PASSED] DP_POWER_DOWN_PHY with port number
[18:31:03] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[18:31:03] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[18:31:03] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[18:31:03] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[18:31:03] [PASSED] DP_QUERY_PAYLOAD with port number
[18:31:03] [PASSED] DP_QUERY_PAYLOAD with VCPI
[18:31:03] [PASSED] DP_REMOTE_DPCD_READ with port number
[18:31:03] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[18:31:03] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[18:31:03] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[18:31:03] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[18:31:03] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[18:31:03] [PASSED] DP_REMOTE_I2C_READ with port number
[18:31:03] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[18:31:03] [PASSED] DP_REMOTE_I2C_READ with transactions array
[18:31:03] [PASSED] DP_REMOTE_I2C_WRITE with port number
[18:31:03] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[18:31:03] [PASSED] DP_REMOTE_I2C_WRITE with data array
[18:31:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[18:31:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[18:31:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[18:31:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[18:31:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[18:31:03] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[18:31:03] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[18:31:03] ================ [PASSED] drm_dp_mst_helper ================
[18:31:03] ================== drm_exec (7 subtests) ===================
[18:31:03] [PASSED] sanitycheck
[18:31:03] [PASSED] test_lock
[18:31:03] [PASSED] test_lock_unlock
[18:31:03] [PASSED] test_duplicates
[18:31:03] [PASSED] test_prepare
[18:31:03] [PASSED] test_prepare_array
[18:31:03] [PASSED] test_multiple_loops
[18:31:03] ==================== [PASSED] drm_exec =====================
[18:31:03] =========== drm_format_helper_test (17 subtests) ===========
[18:31:03] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[18:31:03] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[18:31:03] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[18:31:03] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[18:31:03] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[18:31:03] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[18:31:03] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[18:31:03] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[18:31:03] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[18:31:03] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[18:31:03] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[18:31:03] ============== drm_test_fb_xrgb8888_to_mono  ===============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[18:31:03] ==================== drm_test_fb_swab  =====================
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ================ [PASSED] drm_test_fb_swab =================
[18:31:03] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[18:31:03] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[18:31:03] [PASSED] single_pixel_source_buffer
[18:31:03] [PASSED] single_pixel_clip_rectangle
[18:31:03] [PASSED] well_known_colors
[18:31:03] [PASSED] destination_pitch
[18:31:03] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[18:31:03] ================= drm_test_fb_clip_offset  =================
[18:31:03] [PASSED] pass through
[18:31:03] [PASSED] horizontal offset
[18:31:03] [PASSED] vertical offset
[18:31:03] [PASSED] horizontal and vertical offset
[18:31:03] [PASSED] horizontal offset (custom pitch)
[18:31:03] [PASSED] vertical offset (custom pitch)
[18:31:03] [PASSED] horizontal and vertical offset (custom pitch)
[18:31:03] ============= [PASSED] drm_test_fb_clip_offset =============
[18:31:03] =================== drm_test_fb_memcpy  ====================
[18:31:03] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[18:31:03] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[18:31:03] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[18:31:03] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[18:31:03] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[18:31:03] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[18:31:03] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[18:31:03] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[18:31:03] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[18:31:03] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[18:31:03] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[18:31:03] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[18:31:03] =============== [PASSED] drm_test_fb_memcpy ================
[18:31:03] ============= [PASSED] drm_format_helper_test ==============
[18:31:03] ================= drm_format (18 subtests) =================
[18:31:03] [PASSED] drm_test_format_block_width_invalid
[18:31:03] [PASSED] drm_test_format_block_width_one_plane
[18:31:03] [PASSED] drm_test_format_block_width_two_plane
[18:31:03] [PASSED] drm_test_format_block_width_three_plane
[18:31:03] [PASSED] drm_test_format_block_width_tiled
[18:31:03] [PASSED] drm_test_format_block_height_invalid
[18:31:03] [PASSED] drm_test_format_block_height_one_plane
[18:31:03] [PASSED] drm_test_format_block_height_two_plane
[18:31:03] [PASSED] drm_test_format_block_height_three_plane
[18:31:03] [PASSED] drm_test_format_block_height_tiled
[18:31:03] [PASSED] drm_test_format_min_pitch_invalid
[18:31:03] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[18:31:03] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[18:31:03] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[18:31:03] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[18:31:03] [PASSED] drm_test_format_min_pitch_two_plane
[18:31:03] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[18:31:03] [PASSED] drm_test_format_min_pitch_tiled
[18:31:03] =================== [PASSED] drm_format ====================
[18:31:03] ============== drm_framebuffer (10 subtests) ===============
[18:31:03] ========== drm_test_framebuffer_check_src_coords  ==========
[18:31:03] [PASSED] Success: source fits into fb
[18:31:03] [PASSED] Fail: overflowing fb with x-axis coordinate
[18:31:03] [PASSED] Fail: overflowing fb with y-axis coordinate
[18:31:03] [PASSED] Fail: overflowing fb with source width
[18:31:03] [PASSED] Fail: overflowing fb with source height
[18:31:03] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[18:31:03] [PASSED] drm_test_framebuffer_cleanup
[18:31:03] =============== drm_test_framebuffer_create  ===============
[18:31:03] [PASSED] ABGR8888 normal sizes
[18:31:03] [PASSED] ABGR8888 max sizes
[18:31:03] [PASSED] ABGR8888 pitch greater than min required
[18:31:03] [PASSED] ABGR8888 pitch less than min required
[18:31:03] [PASSED] ABGR8888 Invalid width
[18:31:03] [PASSED] ABGR8888 Invalid buffer handle
[18:31:03] [PASSED] No pixel format
[18:31:03] [PASSED] ABGR8888 Width 0
[18:31:03] [PASSED] ABGR8888 Height 0
[18:31:03] [PASSED] ABGR8888 Out of bound height * pitch combination
[18:31:03] [PASSED] ABGR8888 Large buffer offset
[18:31:03] [PASSED] ABGR8888 Buffer offset for inexistent plane
[18:31:03] [PASSED] ABGR8888 Invalid flag
[18:31:03] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[18:31:03] [PASSED] ABGR8888 Valid buffer modifier
[18:31:03] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[18:31:03] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[18:31:03] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[18:31:03] [PASSED] NV12 Normal sizes
[18:31:03] [PASSED] NV12 Max sizes
[18:31:03] [PASSED] NV12 Invalid pitch
[18:31:03] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[18:31:03] [PASSED] NV12 different  modifier per-plane
[18:31:03] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[18:31:03] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[18:31:03] [PASSED] NV12 Modifier for inexistent plane
[18:31:03] [PASSED] NV12 Handle for inexistent plane
[18:31:03] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[18:31:03] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[18:31:03] [PASSED] YVU420 Normal sizes
[18:31:03] [PASSED] YVU420 Max sizes
[18:31:03] [PASSED] YVU420 Invalid pitch
[18:31:03] [PASSED] YVU420 Different pitches
[18:31:03] [PASSED] YVU420 Different buffer offsets/pitches
[18:31:03] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[18:31:03] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[18:31:03] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[18:31:03] [PASSED] YVU420 Valid modifier
[18:31:03] [PASSED] YVU420 Different modifiers per plane
[18:31:03] [PASSED] YVU420 Modifier for inexistent plane
[18:31:03] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[18:31:03] [PASSED] X0L2 Normal sizes
[18:31:03] [PASSED] X0L2 Max sizes
[18:31:03] [PASSED] X0L2 Invalid pitch
[18:31:03] [PASSED] X0L2 Pitch greater than minimum required
[18:31:03] [PASSED] X0L2 Handle for inexistent plane
[18:31:03] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[18:31:03] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[18:31:03] [PASSED] X0L2 Valid modifier
[18:31:03] [PASSED] X0L2 Modifier for inexistent plane
[18:31:03] =========== [PASSED] drm_test_framebuffer_create ===========
[18:31:03] [PASSED] drm_test_framebuffer_free
[18:31:03] [PASSED] drm_test_framebuffer_init
[18:31:03] [PASSED] drm_test_framebuffer_init_bad_format
[18:31:03] [PASSED] drm_test_framebuffer_init_dev_mismatch
[18:31:03] [PASSED] drm_test_framebuffer_lookup
[18:31:03] [PASSED] drm_test_framebuffer_lookup_inexistent
[18:31:03] [PASSED] drm_test_framebuffer_modifiers_not_supported
[18:31:03] ================= [PASSED] drm_framebuffer =================
[18:31:03] ================ drm_gem_shmem (8 subtests) ================
[18:31:03] [PASSED] drm_gem_shmem_test_obj_create
[18:31:03] [PASSED] drm_gem_shmem_test_obj_create_private
[18:31:03] [PASSED] drm_gem_shmem_test_pin_pages
[18:31:03] [PASSED] drm_gem_shmem_test_vmap
[18:31:03] [PASSED] drm_gem_shmem_test_get_sg_table
[18:31:03] [PASSED] drm_gem_shmem_test_get_pages_sgt
[18:31:03] [PASSED] drm_gem_shmem_test_madvise
[18:31:03] [PASSED] drm_gem_shmem_test_purge
[18:31:03] ================== [PASSED] drm_gem_shmem ==================
[18:31:03] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[18:31:03] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[18:31:03] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[18:31:03] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[18:31:03] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[18:31:03] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[18:31:03] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[18:31:03] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[18:31:03] [PASSED] Automatic
[18:31:03] [PASSED] Full
[18:31:03] [PASSED] Limited 16:235
[18:31:03] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[18:31:03] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[18:31:03] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[18:31:03] [PASSED] drm_test_check_disable_connector
[18:31:03] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[18:31:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[18:31:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[18:31:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[18:31:03] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[18:31:03] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[18:31:03] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[18:31:03] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[18:31:03] [PASSED] drm_test_check_output_bpc_dvi
[18:31:03] [PASSED] drm_test_check_output_bpc_format_vic_1
[18:31:03] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[18:31:03] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[18:31:03] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[18:31:03] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[18:31:03] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[18:31:03] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[18:31:03] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[18:31:03] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[18:31:03] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[18:31:03] [PASSED] drm_test_check_broadcast_rgb_value
[18:31:03] [PASSED] drm_test_check_bpc_8_value
[18:31:03] [PASSED] drm_test_check_bpc_10_value
[18:31:03] [PASSED] drm_test_check_bpc_12_value
[18:31:03] [PASSED] drm_test_check_format_value
[18:31:03] [PASSED] drm_test_check_tmds_char_value
[18:31:03] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[18:31:03] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[18:31:03] [PASSED] drm_test_check_mode_valid
[18:31:03] [PASSED] drm_test_check_mode_valid_reject
[18:31:03] [PASSED] drm_test_check_mode_valid_reject_rate
[18:31:03] [PASSED] drm_test_check_mode_valid_reject_max_clock
[18:31:03] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[18:31:03] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[18:31:03] [PASSED] drm_test_check_infoframes
[18:31:03] [PASSED] drm_test_check_reject_avi_infoframe
[18:31:03] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[18:31:03] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[18:31:03] [PASSED] drm_test_check_reject_audio_infoframe
[18:31:03] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[18:31:03] ================= drm_managed (2 subtests) =================
[18:31:03] [PASSED] drm_test_managed_release_action
[18:31:03] [PASSED] drm_test_managed_run_action
[18:31:03] =================== [PASSED] drm_managed ===================
[18:31:03] =================== drm_mm (6 subtests) ====================
[18:31:03] [PASSED] drm_test_mm_init
[18:31:03] [PASSED] drm_test_mm_debug
[18:31:03] [PASSED] drm_test_mm_align32
[18:31:03] [PASSED] drm_test_mm_align64
[18:31:03] [PASSED] drm_test_mm_lowest
[18:31:03] [PASSED] drm_test_mm_highest
[18:31:03] ===================== [PASSED] drm_mm ======================
[18:31:03] ============= drm_modes_analog_tv (5 subtests) =============
[18:31:03] [PASSED] drm_test_modes_analog_tv_mono_576i
[18:31:03] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[18:31:03] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[18:31:03] [PASSED] drm_test_modes_analog_tv_pal_576i
[18:31:03] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[18:31:03] =============== [PASSED] drm_modes_analog_tv ===============
[18:31:03] ============== drm_plane_helper (2 subtests) ===============
[18:31:03] =============== drm_test_check_plane_state  ================
[18:31:03] [PASSED] clipping_simple
[18:31:03] [PASSED] clipping_rotate_reflect
[18:31:03] [PASSED] positioning_simple
[18:31:03] [PASSED] upscaling
[18:31:03] [PASSED] downscaling
[18:31:03] [PASSED] rounding1
[18:31:03] [PASSED] rounding2
[18:31:03] [PASSED] rounding3
[18:31:03] [PASSED] rounding4
[18:31:03] =========== [PASSED] drm_test_check_plane_state ============
[18:31:03] =========== drm_test_check_invalid_plane_state  ============
[18:31:03] [PASSED] positioning_invalid
[18:31:03] [PASSED] upscaling_invalid
[18:31:03] [PASSED] downscaling_invalid
[18:31:03] ======= [PASSED] drm_test_check_invalid_plane_state ========
[18:31:03] ================ [PASSED] drm_plane_helper =================
[18:31:03] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[18:31:03] ====== drm_test_connector_helper_tv_get_modes_check  =======
[18:31:03] [PASSED] None
[18:31:03] [PASSED] PAL
[18:31:03] [PASSED] NTSC
[18:31:03] [PASSED] Both, NTSC Default
[18:31:03] [PASSED] Both, PAL Default
[18:31:03] [PASSED] Both, NTSC Default, with PAL on command-line
[18:31:03] [PASSED] Both, PAL Default, with NTSC on command-line
[18:31:03] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[18:31:03] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[18:31:03] ================== drm_rect (9 subtests) ===================
[18:31:03] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[18:31:03] [PASSED] drm_test_rect_clip_scaled_not_clipped
[18:31:03] [PASSED] drm_test_rect_clip_scaled_clipped
[18:31:03] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[18:31:03] ================= drm_test_rect_intersect  =================
[18:31:03] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[18:31:03] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[18:31:03] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[18:31:03] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[18:31:03] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[18:31:03] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[18:31:03] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[18:31:03] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[18:31:03] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[18:31:03] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[18:31:03] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[18:31:03] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[18:31:03] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[18:31:03] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[18:31:03] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[18:31:03] ============= [PASSED] drm_test_rect_intersect =============
[18:31:03] ================ drm_test_rect_calc_hscale  ================
[18:31:03] [PASSED] normal use
[18:31:03] [PASSED] out of max range
[18:31:03] [PASSED] out of min range
[18:31:03] [PASSED] zero dst
[18:31:03] [PASSED] negative src
[18:31:03] [PASSED] negative dst
[18:31:03] ============ [PASSED] drm_test_rect_calc_hscale ============
[18:31:03] ================ drm_test_rect_calc_vscale  ================
[18:31:03] [PASSED] normal use
[18:31:03] [PASSED] out of max range
[18:31:03] [PASSED] out of min range
[18:31:03] [PASSED] zero dst
[18:31:03] [PASSED] negative src
[18:31:03] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[18:31:03] ============ [PASSED] drm_test_rect_calc_vscale ============
[18:31:03] ================== drm_test_rect_rotate  ===================
[18:31:03] [PASSED] reflect-x
[18:31:03] [PASSED] reflect-y
[18:31:03] [PASSED] rotate-0
[18:31:03] [PASSED] rotate-90
[18:31:03] [PASSED] rotate-180
[18:31:03] [PASSED] rotate-270
[18:31:03] ============== [PASSED] drm_test_rect_rotate ===============
[18:31:03] ================ drm_test_rect_rotate_inv  =================
[18:31:03] [PASSED] reflect-x
[18:31:03] [PASSED] reflect-y
[18:31:03] [PASSED] rotate-0
[18:31:03] [PASSED] rotate-90
[18:31:03] [PASSED] rotate-180
[18:31:03] [PASSED] rotate-270
[18:31:03] ============ [PASSED] drm_test_rect_rotate_inv =============
[18:31:03] ==================== [PASSED] drm_rect =====================
[18:31:03] ============ drm_sysfb_modeset_test (1 subtest) ============
[18:31:03] ============ drm_test_sysfb_build_fourcc_list  =============
[18:31:03] [PASSED] no native formats
[18:31:03] [PASSED] XRGB8888 as native format
[18:31:03] [PASSED] remove duplicates
[18:31:03] [PASSED] convert alpha formats
[18:31:03] [PASSED] random formats
[18:31:03] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[18:31:03] ============= [PASSED] drm_sysfb_modeset_test ==============
[18:31:03] ================== drm_fixp (2 subtests) ===================
[18:31:03] [PASSED] drm_test_int2fixp
[18:31:03] [PASSED] drm_test_sm2fixp
[18:31:03] ==================== [PASSED] drm_fixp =====================
[18:31:03] ============================================================
[18:31:03] Testing complete. Ran 621 tests: passed: 621
[18:31:03] Elapsed time: 25.979s total, 1.678s configuring, 24.134s building, 0.132s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[18:31:03] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[18:31:05] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[18:31:14] Starting KUnit Kernel (1/1)...
[18:31:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[18:31:14] ================= ttm_device (5 subtests) ==================
[18:31:14] [PASSED] ttm_device_init_basic
[18:31:14] [PASSED] ttm_device_init_multiple
[18:31:14] [PASSED] ttm_device_fini_basic
[18:31:14] [PASSED] ttm_device_init_no_vma_man
[18:31:14] ================== ttm_device_init_pools  ==================
[18:31:14] [PASSED] No DMA allocations, no DMA32 required
[18:31:14] [PASSED] DMA allocations, DMA32 required
[18:31:14] [PASSED] No DMA allocations, DMA32 required
[18:31:14] [PASSED] DMA allocations, no DMA32 required
[18:31:14] ============== [PASSED] ttm_device_init_pools ==============
[18:31:14] =================== [PASSED] ttm_device ====================
[18:31:14] ================== ttm_pool (8 subtests) ===================
[18:31:14] ================== ttm_pool_alloc_basic  ===================
[18:31:14] [PASSED] One page
[18:31:14] [PASSED] More than one page
[18:31:14] [PASSED] Above the allocation limit
[18:31:14] [PASSED] One page, with coherent DMA mappings enabled
[18:31:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:31:14] ============== [PASSED] ttm_pool_alloc_basic ===============
[18:31:14] ============== ttm_pool_alloc_basic_dma_addr  ==============
[18:31:14] [PASSED] One page
[18:31:14] [PASSED] More than one page
[18:31:14] [PASSED] Above the allocation limit
[18:31:14] [PASSED] One page, with coherent DMA mappings enabled
[18:31:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[18:31:14] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[18:31:14] [PASSED] ttm_pool_alloc_order_caching_match
[18:31:14] [PASSED] ttm_pool_alloc_caching_mismatch
[18:31:14] [PASSED] ttm_pool_alloc_order_mismatch
[18:31:14] [PASSED] ttm_pool_free_dma_alloc
[18:31:14] [PASSED] ttm_pool_free_no_dma_alloc
[18:31:14] [PASSED] ttm_pool_fini_basic
[18:31:14] ==================== [PASSED] ttm_pool =====================
[18:31:14] ================ ttm_resource (8 subtests) =================
[18:31:14] ================= ttm_resource_init_basic  =================
[18:31:14] [PASSED] Init resource in TTM_PL_SYSTEM
[18:31:14] [PASSED] Init resource in TTM_PL_VRAM
[18:31:14] [PASSED] Init resource in a private placement
[18:31:14] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[18:31:14] ============= [PASSED] ttm_resource_init_basic =============
[18:31:14] [PASSED] ttm_resource_init_pinned
[18:31:14] [PASSED] ttm_resource_fini_basic
[18:31:14] [PASSED] ttm_resource_manager_init_basic
[18:31:14] [PASSED] ttm_resource_manager_usage_basic
[18:31:14] [PASSED] ttm_resource_manager_set_used_basic
[18:31:14] [PASSED] ttm_sys_man_alloc_basic
[18:31:14] [PASSED] ttm_sys_man_free_basic
[18:31:14] ================== [PASSED] ttm_resource ===================
[18:31:14] =================== ttm_tt (15 subtests) ===================
[18:31:14] ==================== ttm_tt_init_basic  ====================
[18:31:14] [PASSED] Page-aligned size
[18:31:14] [PASSED] Extra pages requested
[18:31:14] ================ [PASSED] ttm_tt_init_basic ================
[18:31:14] [PASSED] ttm_tt_init_misaligned
[18:31:14] [PASSED] ttm_tt_fini_basic
[18:31:14] [PASSED] ttm_tt_fini_sg
[18:31:14] [PASSED] ttm_tt_fini_shmem
[18:31:14] [PASSED] ttm_tt_create_basic
[18:31:14] [PASSED] ttm_tt_create_invalid_bo_type
[18:31:14] [PASSED] ttm_tt_create_ttm_exists
[18:31:14] [PASSED] ttm_tt_create_failed
[18:31:14] [PASSED] ttm_tt_destroy_basic
[18:31:14] [PASSED] ttm_tt_populate_null_ttm
[18:31:14] [PASSED] ttm_tt_populate_populated_ttm
[18:31:14] [PASSED] ttm_tt_unpopulate_basic
[18:31:14] [PASSED] ttm_tt_unpopulate_empty_ttm
[18:31:14] [PASSED] ttm_tt_swapin_basic
[18:31:14] ===================== [PASSED] ttm_tt ======================
[18:31:14] =================== ttm_bo (14 subtests) ===================
[18:31:14] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[18:31:14] [PASSED] Cannot be interrupted and sleeps
[18:31:14] [PASSED] Cannot be interrupted, locks straight away
[18:31:14] [PASSED] Can be interrupted, sleeps
[18:31:14] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[18:31:14] [PASSED] ttm_bo_reserve_locked_no_sleep
[18:31:14] [PASSED] ttm_bo_reserve_no_wait_ticket
[18:31:14] [PASSED] ttm_bo_reserve_double_resv
[18:31:14] [PASSED] ttm_bo_reserve_interrupted
[18:31:14] [PASSED] ttm_bo_reserve_deadlock
[18:31:14] [PASSED] ttm_bo_unreserve_basic
[18:31:14] [PASSED] ttm_bo_unreserve_pinned
[18:31:14] [PASSED] ttm_bo_unreserve_bulk
[18:31:14] [PASSED] ttm_bo_fini_basic
[18:31:14] [PASSED] ttm_bo_fini_shared_resv
[18:31:14] [PASSED] ttm_bo_pin_basic
[18:31:14] [PASSED] ttm_bo_pin_unpin_resource
[18:31:14] [PASSED] ttm_bo_multiple_pin_one_unpin
[18:31:14] ===================== [PASSED] ttm_bo ======================
[18:31:14] ============== ttm_bo_validate (21 subtests) ===============
[18:31:14] ============== ttm_bo_init_reserved_sys_man  ===============
[18:31:14] [PASSED] Buffer object for userspace
[18:31:14] [PASSED] Kernel buffer object
[18:31:14] [PASSED] Shared buffer object
[18:31:14] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[18:31:14] ============== ttm_bo_init_reserved_mock_man  ==============
[18:31:14] [PASSED] Buffer object for userspace
[18:31:14] [PASSED] Kernel buffer object
[18:31:14] [PASSED] Shared buffer object
[18:31:14] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[18:31:14] [PASSED] ttm_bo_init_reserved_resv
[18:31:14] ================== ttm_bo_validate_basic  ==================
[18:31:14] [PASSED] Buffer object for userspace
[18:31:14] [PASSED] Kernel buffer object
[18:31:14] [PASSED] Shared buffer object
[18:31:14] ============== [PASSED] ttm_bo_validate_basic ==============
[18:31:14] [PASSED] ttm_bo_validate_invalid_placement
[18:31:14] ============= ttm_bo_validate_same_placement  ==============
[18:31:14] [PASSED] System manager
[18:31:14] [PASSED] VRAM manager
[18:31:14] ========= [PASSED] ttm_bo_validate_same_placement ==========
[18:31:14] [PASSED] ttm_bo_validate_failed_alloc
[18:31:14] [PASSED] ttm_bo_validate_pinned
[18:31:14] [PASSED] ttm_bo_validate_busy_placement
[18:31:14] ================ ttm_bo_validate_multihop  =================
[18:31:14] [PASSED] Buffer object for userspace
[18:31:14] [PASSED] Kernel buffer object
[18:31:14] [PASSED] Shared buffer object
[18:31:14] ============ [PASSED] ttm_bo_validate_multihop =============
[18:31:14] ========== ttm_bo_validate_no_placement_signaled  ==========
[18:31:14] [PASSED] Buffer object in system domain, no page vector
[18:31:14] [PASSED] Buffer object in system domain with an existing page vector
[18:31:14] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[18:31:14] ======== ttm_bo_validate_no_placement_not_signaled  ========
[18:31:14] [PASSED] Buffer object for userspace
[18:31:14] [PASSED] Kernel buffer object
[18:31:14] [PASSED] Shared buffer object
[18:31:14] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[18:31:14] [PASSED] ttm_bo_validate_move_fence_signaled
[18:31:14] ========= ttm_bo_validate_move_fence_not_signaled  =========
[18:31:14] [PASSED] Waits for GPU
[18:31:14] [PASSED] Tries to lock straight away
[18:31:14] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[18:31:14] [PASSED] ttm_bo_validate_happy_evict
[18:31:14] [PASSED] ttm_bo_validate_all_pinned_evict
[18:31:14] [PASSED] ttm_bo_validate_allowed_only_evict
[18:31:14] [PASSED] ttm_bo_validate_deleted_evict
[18:31:14] [PASSED] ttm_bo_validate_busy_domain_evict
[18:31:14] [PASSED] ttm_bo_validate_evict_gutting
[18:31:14] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[18:31:14] ================= [PASSED] ttm_bo_validate =================
[18:31:14] ============================================================
[18:31:14] Testing complete. Ran 101 tests: passed: 101
[18:31:14] Elapsed time: 11.577s total, 1.752s configuring, 9.609s building, 0.185s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1592 bytes --]

== Series Details ==

Series: drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10)
URL   : https://patchwork.freedesktop.org/series/159554/
State : success

== Summary ==

CI Bug Log - changes from xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7_BAT -> xe-pw-159554v10_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-159554v10_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [FAIL][1] ([Intel XE#6520]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * IGT: IGT_8791 -> IGT_8792
  * Linux: xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7 -> xe-pw-159554v10

  IGT_8791: b319fd1815d426b3f24094113d614d08dee374d8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8792: 8792
  xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7: bf3ba6a508ffb59323357535a459eb64f02d94f7
  xe-pw-159554v10: 159554v10

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/index.html

[-- Attachment #2: Type: text/html, Size: 2172 bytes --]

✗ Xe.CI.FULL: failure for drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 49435 bytes --]

== Series Details ==

Series: drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms (rev10)
URL   : https://patchwork.freedesktop.org/series/159554/
State : failure

== Summary ==

CI Bug Log - changes from xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7_FULL -> xe-pw-159554v10_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-159554v10_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-159554v10_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-159554v10_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_pm@s4-basic-exec:
    - shard-bmg:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-8/igt@xe_pm@s4-basic-exec.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-1/igt@xe_pm@s4-basic-exec.html

  
Known issues
------------

  Here are the changes found in xe-pw-159554v10_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
    - shard-lnl:          [PASS][3] -> [FAIL][4] ([Intel XE#6054]) +3 other tests fail
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-lnl-4/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-6/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2370])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][6] ([Intel XE#2705]) +1 other test incomplete
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2327]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-1/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#7059] / [Intel XE#7085]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-8/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +7 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [PASS][10] -> [SKIP][11] ([Intel XE#2314] / [Intel XE#2894] / [Intel XE#7373])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-7/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2314] / [Intel XE#2894] / [Intel XE#7373])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2652]) +8 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-1/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#2887])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#3432])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2887]) +9 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-4/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2724] / [Intel XE#7449])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2325] / [Intel XE#7358])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2252]) +8 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][20] ([Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#7194])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][22] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +4 other tests fail
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-10/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2320]) +8 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-1/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][24] -> [SKIP][25] ([Intel XE#2291]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2286] / [Intel XE#6035])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#1508])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-9/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2244]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#2244]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-5/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#6126] / [Intel XE#776])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-10/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [PASS][31] -> [SKIP][32] ([Intel XE#2373] / [Intel XE#7344])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-7/igt@kms_feature_discovery@display-2x.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2316]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [PASS][34] -> [SKIP][35] ([Intel XE#2316]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-6/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#7178] / [Intel XE#7351]) +2 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-10/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#1397] / [Intel XE#7385])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7179])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@kms_flip_scaled_crc@flip-nv12-linear-to-nv12-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2311]) +23 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2312]) +4 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#656]) +2 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#7061] / [Intel XE#7356]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#4141]) +6 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2313]) +20 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#6911] / [Intel XE#7466])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#6900] / [Intel XE#7362])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-5/igt@kms_joiner@basic-ultra-joiner.html
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#6911] / [Intel XE#7378])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#6912] / [Intel XE#7375])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#7283]) +3 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier-source-clamping.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2393])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#5020] / [Intel XE#7348])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2763] / [Intel XE#6886]) +14 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#3309] / [Intel XE#7368])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-lnl:          [PASS][55] -> [FAIL][56] ([Intel XE#2029] / [Intel XE#7395])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-lnl-3/igt@kms_pm_dc@deep-pkgc.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-7/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#1489]) +3 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-9/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr@psr2-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2234] / [Intel XE#2850]) +10 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_psr@psr2-sprite-plane-onoff.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#1406] / [Intel XE#2414])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#2413]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-bmg:          [PASS][62] -> [SKIP][63] ([Intel XE#1435])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-9/igt@kms_setmode@invalid-clone-single-crtc.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          NOTRUN -> [FAIL][64] ([Intel XE#1729] / [Intel XE#7424])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#2426] / [Intel XE#5848])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#1499])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@lobf:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#2168] / [Intel XE#7444])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_vrr@lobf.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#2504] / [Intel XE#7319] / [Intel XE#7350])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_eudebug@vm-bind-clear:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#4837]) +7 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@xe_eudebug@vm-bind-clear.html

  * igt@xe_eudebug_online@pagefault-one-of-many:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#6665])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@xe_eudebug_online@pagefault-one-of-many.html

  * igt@xe_eudebug_online@set-breakpoint-sigint-debugger:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#4837] / [Intel XE#6665]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@xe_eudebug_online@set-breakpoint-sigint-debugger.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][72] -> [INCOMPLETE][73] ([Intel XE#6321])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-6/igt@xe_evict@evict-mixed-many-threads-small.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict@evict-mixed-threads-small-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#7140])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-8/igt@xe_evict@evict-mixed-threads-small-multi-queue.html

  * igt@xe_exec_balancer@twice-virtual-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#7482])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-5/igt@xe_exec_balancer@twice-virtual-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-null:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#2322] / [Intel XE#7372]) +5 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@xe_exec_basic@multigpu-no-exec-null.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#7136]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-5/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-prefetch.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#7136]) +13 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-9/igt@xe_exec_fault_mode@twice-multi-queue-userptr.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#6874]) +20 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-priority-smem:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#6874])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-2/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-priority-smem.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#7138]) +6 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-mixed-userptr-invalidate-race.html

  * igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#2229])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-4/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html

  * igt@xe_media_fill@media-fill:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#2459] / [Intel XE#2596] / [Intel XE#7321] / [Intel XE#7453])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@xe_media_fill@media-fill.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108]) -> ([PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [SKIP][131], [PASS][132], [PASS][133], [PASS][134]) ([Intel XE#2457] / [Intel XE#7405])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-8/igt@xe_module_load@load.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-1/igt@xe_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-3/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-10/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-5/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-3/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-2/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-1/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-4/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-4/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-10/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-10/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-9/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-9/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-7/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-2/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-3/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-2/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-6/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-7/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-5/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-6/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-6/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-3/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-8/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-8/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-2/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-1/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-1/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-4/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-3/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-10/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-9/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-9/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-10/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-8/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-4/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-8/igt@xe_module_load@load.html

  * igt@xe_multigpu_svm@mgpu-coherency-fail-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][135] ([Intel XE#6964]) +2 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@xe_multigpu_svm@mgpu-coherency-fail-prefetch.html

  * igt@xe_multigpu_svm@mgpu-latency-basic:
    - shard-lnl:          NOTRUN -> [SKIP][136] ([Intel XE#6964])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-6/igt@xe_multigpu_svm@mgpu-latency-basic.html

  * igt@xe_pat@pat-index-xelp:
    - shard-bmg:          NOTRUN -> [SKIP][137] ([Intel XE#2245])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-8/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-bmg:          NOTRUN -> [SKIP][138] ([Intel XE#2284] / [Intel XE#7370])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@s3-multiple-execs:
    - shard-lnl:          NOTRUN -> [SKIP][139] ([Intel XE#584] / [Intel XE#7369])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-5/igt@xe_pm@s3-multiple-execs.html

  * igt@xe_pxp@display-black-pxp-fb:
    - shard-bmg:          NOTRUN -> [SKIP][140] ([Intel XE#4733] / [Intel XE#7417]) +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@xe_pxp@display-black-pxp-fb.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3:
    - shard-bmg:          [FAIL][141] -> [PASS][142] +1 other test pass
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-5/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-bmg:          [SKIP][143] ([Intel XE#2291]) -> [PASS][144]
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][145] ([Intel XE#7571]) -> [PASS][146]
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-bmg:          [SKIP][147] ([Intel XE#2316]) -> [PASS][148] +1 other test pass
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-5/igt@kms_flip@2x-blocking-wf_vblank.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-10/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][149] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][150] +1 other test pass
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [FAIL][151] ([Intel XE#5625]) -> [PASS][152]
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_run:
    - shard-bmg:          [ABORT][153] -> [PASS][154]
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-3/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_run.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-6/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_run.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic-dpms:
    - shard-bmg:          [FAIL][155] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) -> [SKIP][156] ([Intel XE#2341])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-8/igt@kms_content_protection@atomic-dpms.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          [SKIP][157] ([Intel XE#2341]) -> [FAIL][158] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-5/igt@kms_content_protection@legacy.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-4/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0-hdcp14:
    - shard-bmg:          [FAIL][159] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) -> [SKIP][160] ([Intel XE#7194])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-8/igt@kms_content_protection@lic-type-0-hdcp14.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_content_protection@lic-type-0-hdcp14.html

  * igt@kms_content_protection@uevent-hdcp14:
    - shard-bmg:          [FAIL][161] ([Intel XE#6707] / [Intel XE#7439]) -> [SKIP][162] ([Intel XE#7194])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-3/igt@kms_content_protection@uevent-hdcp14.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_content_protection@uevent-hdcp14.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          [SKIP][163] ([Intel XE#2312]) -> [SKIP][164] ([Intel XE#2311]) +4 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][165] ([Intel XE#4141]) -> [SKIP][166] ([Intel XE#2312]) +5 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][167] ([Intel XE#2312]) -> [SKIP][168] ([Intel XE#4141]) +2 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
    - shard-bmg:          [SKIP][169] ([Intel XE#2311]) -> [SKIP][170] ([Intel XE#2312]) +13 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][171] ([Intel XE#2313]) -> [SKIP][172] ([Intel XE#2312]) +11 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][173] ([Intel XE#2312]) -> [SKIP][174] ([Intel XE#2313]) +6 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][175] ([Intel XE#3544]) -> [SKIP][176] ([Intel XE#3374] / [Intel XE#3544])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7/shard-bmg-9/igt@kms_hdr@brightness-with-hdr.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/shard-bmg-8/igt@kms_hdr@brightness-with-hdr.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
  [Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7194]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7194
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7319
  [Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
  [Intel XE#7350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7350
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7362
  [Intel XE#7368]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7368
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7373
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
  [Intel XE#7378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7378
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7395
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
  [Intel XE#7444]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7444
  [Intel XE#7449]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7449
  [Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
  [Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776


Build changes
-------------

  * IGT: IGT_8791 -> IGT_8792
  * Linux: xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7 -> xe-pw-159554v10

  IGT_8791: b319fd1815d426b3f24094113d614d08dee374d8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8792: 8792
  xe-4691-bf3ba6a508ffb59323357535a459eb64f02d94f7: bf3ba6a508ffb59323357535a459eb64f02d94f7
  xe-pw-159554v10: 159554v10

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159554v10/index.html

[-- Attachment #2: Type: text/html, Size: 55457 bytes --]

Re: [PATCH v9 0/6] drm/xe/sysctrl: Add system controller component for Xe3p dGPU platforms

[Riana Tauro]

Hi Anoop

Fix Title: drm/xe/xe_sysctrl in all patches

On 3/10/2026 11:53 PM, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> This patch series introduces System Controller (sysctrl) component for Intel Xe3p
> dGPU platforms.
> 
> This component provides the foundational infrastructure for communication
> with the System Controller firmware using MKHI protocol over a mailbox interface.

Add a brief about what System controller is.
Use either MKHI or SCHI. Not a mix of both

Maybe add a link to the usage patch series.

Thanks
Riana

> 
> Key features introduced:
> - Detection and initialization of System Controller interface on Xe3p dGPU platforms
> - Mailbox communication with System Controller firmware
> - Fragmented message transfer for large command payloads
> 
> This implementation establishes the base for future System Controller feature
> enablement and firmware command handling.
> ---
> v2: (Umesh)
> - Fix commit message to 75 chars per line
> - Address CI.Hooks and checkpatch warnings
> - Add sc_to_xe() helper for cleaner conversions
> - Alphabetical order for headers
> - Simplify write/read frame logic using memcpy
> - Drop redundant frame length checks
> - Use xe_mmio_rmw32() for register updates
> - Align FIELD_PREP macros
> - Improve error handling and timeout messages
> - Handle phase_bit revert on write-frame failure
> - Update rdata_len on partial receive before return
> - Remove unnecessary headers
> 
> v3: (Matt, Riana, Umesh)
> - Split patch into logical series
> - Rename SC_* macros to SYSCTRL_* for consistency
> - Move MKHI_* defines to .c file
> - Pass xe directly to helpers
> - Place devm_add_action_or_reset() after set_sysctrl_region()
> - Add kernel-doc for xe_sysctrl_mailbox_init()
> - Add short documentation for System Controller in xe_sysctrl.c
> - Avoid hardcoded sizes
> - Move structs to _types.h
> 
> v4: (Matt, Mike)
> - Code style improvements
> - Add domain-specific MMIO accessor
> - Change phase_bit to bool type
> - Add input validation and buffer overflow protection
> 
> v5: (Umesh, Riana)
> - Reset phase bit to 0 on error conditions
> - Refactor mailbox receive path
> - Updated xe_err messages for consistency
> 
> v6: (Matt)
> - Move protocol constants from xe_sysctrl_regs.h to xe_sysctrl_mailbox_types.h
> - Add SYSCTRL_MB_CTRL_MKHI_CMD helper macro
> 
> v7:
> - Fix for CI failure
> 
> v8: (Matt, Michal, Shuicheng)
> - Reordered patches for logical flow
> - Moved ABI definitions to dedicated header
> - Static functions renamed with short prefix
> - Fixed include order
> - Added VF check
> - Converted runtime checks to assertions
> - Changed xe_sysctrl_send_command() function parameter from 'xe' to 'sc'
> - Added frame length validation and command overflow protection
> - Use REG_FIELD_PREP for hardware registers
> - Changed error format to %pe
> - Removed unnecessary NULL checks and explicit zeros
> - Fixed kernel-doc syntax
> - Added sc_to_xe() helper
> 
> v9: (Matt, Umesh, Badal)
> - Extended commit message to explain System Controller and purpose of
>    `has_sysctrl` flag
> - Normalized hexadecimal literal casing
> - Renamed MKHI to SCHI (System Controller Host Interface)
> - Fixed kernel-doc syntax
> ---
> 
> Anoop Vijay (6):
>    drm/xe/sysctrl: Add System Controller types and device integration
>    drm/xe/sysctrl: Add System Controller register definitions
>    drm/xe/sysctrl: Add mailbox communication headers
>    drm/xe/sysctrl: Add System Controller initialization
>    drm/xe/sysctrl: Add mailbox communication implementation
>    drm/xe/pci: Enable System Controller for CRI platform
> 
>   drivers/gpu/drm/xe/Makefile                   |   2 +
>   drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h       |  31 ++
>   drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h     |  36 ++
>   drivers/gpu/drm/xe/xe_device.c                |   5 +
>   drivers/gpu/drm/xe/xe_device_types.h          |   6 +
>   drivers/gpu/drm/xe/xe_pci.c                   |   2 +
>   drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
>   drivers/gpu/drm/xe/xe_sysctrl.c               |  84 ++++
>   drivers/gpu/drm/xe/xe_sysctrl.h               |  21 +
>   drivers/gpu/drm/xe/xe_sysctrl_mailbox.c       | 364 ++++++++++++++++++
>   drivers/gpu/drm/xe/xe_sysctrl_mailbox.h       |  31 ++
>   drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |  35 ++
>   drivers/gpu/drm/xe/xe_sysctrl_types.h         |  32 ++
>   13 files changed, 650 insertions(+)
>   create mode 100644 drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
>   create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h
>