* [PATCH v2 00/10] CMTG enablement
@ 2026-02-03 13:43 Animesh Manna
2026-02-03 13:43 ` [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards Animesh Manna
` (18 more replies)
0 siblings, 19 replies; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:43 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
Common mode timing generator (CMTG) support is added LNL onwards.
Enable CMTG which will be needed by other fearure like dynamic dc
state enablement later.
Testing ongoing, currently counters are incrementing as expected.
Animesh Manna (8):
drm/i915/cmtg: enable cmtg LNL onwards
drm/i915/cmtg: cmtg set clock select
drm/i915/cmtg: set timings for cmtg
drm/i915/cmtg: program vrr registers of cmtg
drm/i915/cmtg: program set context latency of cmtg
drm/i915/cmtg: set transcoder mn for cmtg
drm/i915/cmtg: program sync to port for cmtg
drm/i915/cmtg: enable cmtg ctl
Dibin Moolakadan Subrahmanian (2):
drm/i915/cmtg: enable cmtg in secondary mode
drm/i915/cmtg: disable CMTG on transcoder disable
drivers/gpu/drm/i915/display/intel_cmtg.c | 140 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_cmtg.h | 4 +
.../gpu/drm/i915/display/intel_cmtg_regs.h | 22 +++
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +
drivers/gpu/drm/i915/display/intel_display.c | 52 ++++---
.../drm/i915/display/intel_display_types.h | 7 +
drivers/gpu/drm/i915/display/intel_dp.c | 4 +
drivers/gpu/drm/i915/display/intel_lt_phy.c | 9 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 4 +
10 files changed, 225 insertions(+), 23 deletions(-)
--
2.29.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
@ 2026-02-03 13:43 ` Animesh Manna
2026-02-05 5:18 ` Kandpal, Suraj
2026-02-03 13:43 ` [PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select Animesh Manna
` (17 subsequent siblings)
18 siblings, 1 reply; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:43 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
Introduce a flag for cmtg. LNL onwards CMTG support will be added.
Set the flag as per DISPLAY_VER() check.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 4 ++++
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e6298279dc89..1081615a14fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1569,6 +1569,10 @@ struct intel_crtc {
#endif
bool vblank_psr_notify;
+
+ struct {
+ bool enable;
+ } cmtg;
};
struct intel_plane_error {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e2fd01d1a1e4..ecf8ed0c0265 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3445,6 +3445,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
const struct drm_display_mode *fixed_mode;
struct intel_connector *connector = intel_dp->attached_connector;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
int ret = 0, link_bpp_x16;
fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
@@ -3549,6 +3550,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
+ if (DISPLAY_VER(display) >= 15 && intel_dp_is_edp(intel_dp))
+ crtc->cmtg.enable = true;
+
return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
pipe_config);
}
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
2026-02-03 13:43 ` [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards Animesh Manna
@ 2026-02-03 13:43 ` Animesh Manna
2026-02-05 5:25 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg Animesh Manna
` (16 subsequent siblings)
18 siblings, 1 reply; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:43 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
Program CMTG Clk Select.
v2:
- Correct mask for PHY B. [Jani]
- Use REG_FIELD_PREP() for enable value. [Dibin]
- Extend cmtg clock select for xe3plpd. [Dibin]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 22 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_cmtg.h | 2 ++
.../gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++++
drivers/gpu/drm/i915/display/intel_lt_phy.c | 9 ++++++--
5 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index e1fdc6fe9762..f5364f5a848f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
#include "intel_display_device.h"
#include "intel_display_power.h"
#include "intel_display_regs.h"
+#include "intel_display_types.h"
/**
* DOC: Common Primary Timing Generator (CMTG)
@@ -185,3 +186,24 @@ void intel_cmtg_sanitize(struct intel_display *display)
intel_cmtg_disable(display, &cmtg_config);
}
+
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 clk_sel_clr = 0;
+ u32 clk_sel_set = 0;
+
+ if (cpu_transcoder == TRANSCODER_A) {
+ clk_sel_clr = CMTG_CLK_SEL_A_MASK;
+ clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
+ }
+
+ if (cpu_transcoder == TRANSCODER_B) {
+ clk_sel_clr = CMTG_CLK_SEL_B_MASK;
+ clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
+ }
+
+ if (clk_sel_set)
+ intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ba62199adaa2..bef2426b2787 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -7,7 +7,9 @@
#define __INTEL_CMTG_H__
struct intel_display;
+struct intel_crtc_state;
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
void intel_cmtg_sanitize(struct intel_display *display);
#endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 945a35578284..8a767b659a23 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -10,8 +10,10 @@
#define CMTG_CLK_SEL _MMIO(0x46160)
#define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29)
+#define CMTG_CLK_SELECT_PHYA_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
#define CMTG_CLK_SEL_A_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
#define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13)
+#define CMTG_CLK_SELECT_PHYB_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x6)
#define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
#define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6a471c021c0e..a88f013e472b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -9,6 +9,7 @@
#include <drm/drm_print.h>
#include "intel_alpm.h"
+#include "intel_cmtg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
#include "intel_display_regs.h"
@@ -3417,9 +3418,13 @@ void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
if (intel_tc_port_in_tbt_alt_mode(dig_port))
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
+
+ if (crtc->cmtg.enable)
+ intel_cmtg_set_clk_select(crtc_state);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 04f63bdd0b87..f6c45bf9d0f3 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -6,6 +6,7 @@
#include <drm/drm_print.h>
#include "i915_reg.h"
+#include "intel_cmtg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
@@ -2246,11 +2247,15 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- if (intel_tc_port_in_tbt_alt_mode(dig_port))
+ if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
- else
+ } else {
intel_lt_phy_pll_enable(encoder, crtc_state);
+ if (crtc->cmtg.enable)
+ intel_cmtg_set_clk_select(crtc_state);
+ }
}
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
2026-02-03 13:43 ` [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards Animesh Manna
2026-02-03 13:43 ` [PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select Animesh Manna
@ 2026-02-03 13:44 ` Animesh Manna
2026-02-05 5:35 ` Kandpal, Suraj
2026-02-05 8:47 ` Jani Nikula
2026-02-03 13:44 ` [PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg Animesh Manna
` (15 subsequent siblings)
18 siblings, 2 replies; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:44 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
Timing registers are separate for CMTG, read transcoder register
and program cmtg transcoder with those values.
v2:
- Use sw state instead of reading directly from hardware. [Jani]
- Move set_timing later after encoder enable. [Dibin]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 24 +++++++++
drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
.../gpu/drm/i915/display/intel_cmtg_regs.h | 7 +++
drivers/gpu/drm/i915/display/intel_display.c | 51 ++++++++++++-------
.../drm/i915/display/intel_display_types.h | 2 +
5 files changed, 67 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index f5364f5a848f..4220eeece07f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -207,3 +207,27 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
if (clk_sel_set)
intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
}
+
+static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder), crtc->cmtg.htotal);
+ intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder), crtc->cmtg.hblank);
+ intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder), crtc->cmtg.hsync);
+ intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc->cmtg.vtotal);
+ intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc->cmtg.vblank);
+ intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder), crtc->cmtg.vsync);
+}
+
+void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
+{
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
+ return;
+
+ intel_cmtg_set_timings(crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index bef2426b2787..b2bb60d160fa 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -9,6 +9,7 @@
struct intel_display;
struct intel_crtc_state;
+void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
void intel_cmtg_sanitize(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 8a767b659a23..eb24827d22f5 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -20,4 +20,11 @@
#define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
#define CMTG_ENABLE REG_BIT(31)
+#define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) * 0x100)
+#define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) * 0x100)
+#define TRANS_HSYNC_CMTG(id) _MMIO(0x6F008 + (id) * 0x100)
+#define TRANS_VTOTAL_CMTG(id) _MMIO(0x6F00C + (id) * 0x100)
+#define TRANS_VBLANK_CMTG(id) _MMIO(0x6F010 + (id) * 0x100)
+#define TRANS_VSYNC_CMTG(id) _MMIO(0x6F014 + (id) * 0x100)
+
#endif /* __INTEL_CMTG_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 564d11925af3..976af9eb3c3a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -62,6 +62,7 @@
#include "intel_casf.h"
#include "intel_cdclk.h"
#include "intel_clock_gating.h"
+#include "intel_cmtg.h"
#include "intel_color.h"
#include "intel_crt.h"
#include "intel_crtc.h"
@@ -1722,6 +1723,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
intel_crtc_wait_for_next_vblank(wa_crtc);
}
}
+
+ if (crtc->cmtg.enable)
+ intel_cmtg_enable(new_crtc_state);
}
static void ilk_crtc_disable(struct intel_atomic_state *state,
@@ -2654,6 +2658,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
int vsyncshift = 0;
+ u32 trans_htotal_val, trans_hblank_val, trans_hsync_val;
+ u32 trans_vtotal_val, trans_vblank_val, trans_vsync_val;
drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
@@ -2702,15 +2708,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
TRANS_VSYNCSHIFT(display, cpu_transcoder),
vsyncshift);
- intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
- HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
- HTOTAL(adjusted_mode->crtc_htotal - 1));
- intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
- HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
- HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
- intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
- HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
- HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
+ trans_htotal_val = HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
+ HTOTAL(adjusted_mode->crtc_htotal - 1);
+ trans_hblank_val = HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
+ HBLANK_END(adjusted_mode->crtc_hblank_end - 1);
+ trans_hsync_val = HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
+ HSYNC_END(adjusted_mode->crtc_hsync_end - 1);
+ intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), trans_htotal_val);
+ intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), trans_hblank_val);
+ intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), trans_hsync_val);
/*
* For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
@@ -2721,15 +2727,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
if (intel_vrr_always_use_vrr_tg(display))
crtc_vtotal = 1;
- intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
- VACTIVE(crtc_vdisplay - 1) |
- VTOTAL(crtc_vtotal - 1));
- intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
- VBLANK_START(crtc_vblank_start - 1) |
- VBLANK_END(crtc_vblank_end - 1));
- intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
- VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
- VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
+ trans_vtotal_val = VACTIVE(crtc_vdisplay - 1) |
+ VTOTAL(crtc_vtotal - 1);
+ trans_vblank_val = VBLANK_START(crtc_vblank_start - 1) |
+ VBLANK_END(crtc_vblank_end - 1);
+ trans_vsync_val = VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
+ VSYNC_END(adjusted_mode->crtc_vsync_end - 1);
+ intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), trans_vtotal_val);
+ intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), trans_vblank_val);
+ intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), trans_vsync_val);
/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
@@ -2753,6 +2759,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
crtc_state->min_hblank);
}
+
+ if (crtc->cmtg.enable) {
+ crtc->cmtg.htotal = trans_htotal_val;
+ crtc->cmtg.hblank = trans_hblank_val;
+ crtc->cmtg.hsync = trans_hsync_val;
+ crtc->cmtg.vtotal = trans_vtotal_val;
+ crtc->cmtg.vblank = trans_vblank_val;
+ crtc->cmtg.vsync = trans_vsync_val;
+ }
}
static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1081615a14fb..defb54dd0bbe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1572,6 +1572,8 @@ struct intel_crtc {
struct {
bool enable;
+ u32 htotal, hblank, hsync;
+ u32 vtotal, vblank, vsync;
} cmtg;
};
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (2 preceding siblings ...)
2026-02-03 13:44 ` [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg Animesh Manna
@ 2026-02-03 13:44 ` Animesh Manna
2026-02-06 2:54 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 05/10] drm/i915/cmtg: program set context latency " Animesh Manna
` (14 subsequent siblings)
18 siblings, 1 reply; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:44 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
Enable vrr if it is enabled on cmtg registers.
v2: Use sw state instead of reading from hardware. [Jani]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 5 +++++
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++
4 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 4220eeece07f..26adf70cdd00 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -17,6 +17,7 @@
#include "intel_display_power.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
+#include "intel_vrr.h"
/**
* DOC: Common Primary Timing Generator (CMTG)
@@ -220,6 +221,17 @@ static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc->cmtg.vtotal);
intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc->cmtg.vblank);
intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder), crtc->cmtg.vsync);
+
+ if (intel_vrr_possible(crtc_state) && intel_vrr_always_use_vrr_tg(display)) {
+ intel_de_write(display, TRANS_VRR_VMIN_CMTG(cpu_transcoder),
+ crtc_state->vrr.vmin - 1);
+ intel_de_write(display, TRANS_VRR_VMAX_CMTG(cpu_transcoder),
+ crtc_state->vrr.vmax - 1);
+ intel_de_write(display, TRANS_VRR_FLIPLINE_CMTG(cpu_transcoder),
+ crtc_state->vrr.flipline - 1);
+ intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder),
+ crtc->cmtg.vrr_ctl);
+ }
}
void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index eb24827d22f5..eab90415d0da 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -27,4 +27,9 @@
#define TRANS_VBLANK_CMTG(id) _MMIO(0x6F010 + (id) * 0x100)
#define TRANS_VSYNC_CMTG(id) _MMIO(0x6F014 + (id) * 0x100)
+#define TRANS_VRR_CTL_CMTG(id) _MMIO(0x6F420 + (id) * 0x100)
+#define TRANS_VRR_VMAX_CMTG(id) _MMIO(0x6F424 + (id) * 0x100)
+#define TRANS_VRR_VMIN_CMTG(id) _MMIO(0x6F434 + (id) * 0x100)
+#define TRANS_VRR_FLIPLINE_CMTG(id) _MMIO(0x6F438 + (id) * 0x100)
+
#endif /* __INTEL_CMTG_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index defb54dd0bbe..a87f3ec10aea 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1574,6 +1574,7 @@ struct intel_crtc {
bool enable;
u32 htotal, hblank, hsync;
u32 vtotal, vblank, vsync;
+ u32 vrr_ctl;
} cmtg;
};
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 9d814cc2d608..2c1ae685400f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -892,6 +892,7 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
u32 vrr_ctl;
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
@@ -907,6 +908,9 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
if (cmrr_enable)
vrr_ctl |= VRR_CTL_CMRR_ENABLE;
+ if (crtc->cmtg.enable)
+ crtc->cmtg.vrr_ctl = vrr_ctl;
+
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
}
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 05/10] drm/i915/cmtg: program set context latency of cmtg
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (3 preceding siblings ...)
2026-02-03 13:44 ` [PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg Animesh Manna
@ 2026-02-03 13:44 ` Animesh Manna
2026-02-06 3:08 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg Animesh Manna
` (13 subsequent siblings)
18 siblings, 1 reply; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:44 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
Program context latency for delayed vblank timings to create window2.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 4 ++++
drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 26adf70cdd00..cb1376f4c13f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -236,10 +236,14 @@ static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
return;
intel_cmtg_set_timings(crtc_state);
+
+ intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
+ intel_de_read(display, TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index eab90415d0da..3cfd8eedb321 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -32,4 +32,6 @@
#define TRANS_VRR_VMIN_CMTG(id) _MMIO(0x6F434 + (id) * 0x100)
#define TRANS_VRR_FLIPLINE_CMTG(id) _MMIO(0x6F438 + (id) * 0x100)
+#define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) * 0x100)
+
#endif /* __INTEL_CMTG_REGS_H__ */
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (4 preceding siblings ...)
2026-02-03 13:44 ` [PATCH v2 05/10] drm/i915/cmtg: program set context latency " Animesh Manna
@ 2026-02-03 13:44 ` Animesh Manna
2026-02-06 3:22 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 07/10] drm/i915/cmtg: program sync to port " Animesh Manna
` (12 subsequent siblings)
18 siblings, 1 reply; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:44 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
Program CMTG link M/N.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 3 +++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index cb1376f4c13f..12a081dd7e4d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -234,6 +234,16 @@ static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
}
}
+static void intel_cpu_cmtg_transcoder_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+ intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n->link_m);
+ intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
+}
+
void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -246,4 +256,6 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
intel_de_read(display, TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
+
+ intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 3cfd8eedb321..b766ded8686c 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -32,6 +32,9 @@
#define TRANS_VRR_VMIN_CMTG(id) _MMIO(0x6F434 + (id) * 0x100)
#define TRANS_VRR_FLIPLINE_CMTG(id) _MMIO(0x6F438 + (id) * 0x100)
+#define TRANS_LINKM1_CMTG(id) _MMIO(0x6F040 + (id) * 0x100)
+#define TRANS_LINKN1_CMTG(id) _MMIO(0x6F044 + (id) * 0x100)
+
#define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) * 0x100)
#endif /* __INTEL_CMTG_REGS_H__ */
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 07/10] drm/i915/cmtg: program sync to port for cmtg
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (5 preceding siblings ...)
2026-02-03 13:44 ` [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg Animesh Manna
@ 2026-02-03 13:44 ` Animesh Manna
2026-02-06 3:28 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl Animesh Manna
` (11 subsequent siblings)
18 siblings, 1 reply; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:44 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
Program Cmtg Sync to Port Sync. Set before enabling the timing generator.
While cmtg start running this bit will be cleared.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 3 +++
drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 12a081dd7e4d..3af4aefc760e 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -258,4 +258,7 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
intel_de_read(display, TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
+
+ /* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
+ intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index b766ded8686c..0ed767a797c0 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -18,7 +18,9 @@
#define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
#define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
+#define TRANS_CMTG_CTL(id) _MMIO(0x6fa88 + (id) * 0x100)
#define CMTG_ENABLE REG_BIT(31)
+#define CMTG_SYNC_TO_PORT REG_BIT(29)
#define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) * 0x100)
#define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) * 0x100)
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (6 preceding siblings ...)
2026-02-03 13:44 ` [PATCH v2 07/10] drm/i915/cmtg: program sync to port " Animesh Manna
@ 2026-02-03 13:44 ` Animesh Manna
2026-02-05 8:50 ` Jani Nikula
2026-02-03 13:44 ` [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode Animesh Manna
` (10 subsequent siblings)
18 siblings, 1 reply; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:44 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
Enable CMTG through control register.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 3af4aefc760e..f7364c7408d5 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -244,6 +244,19 @@ static void intel_cpu_cmtg_transcoder_set_m_n(const struct intel_crtc_state *crt
intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
}
+static void intel_cmtg_ctl_enable(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 val = 0;
+
+ val = intel_de_read(display, TRANS_CMTG_CTL(cpu_transcoder));
+
+ val |= CMTG_ENABLE;
+
+ intel_de_write(display, TRANS_CMTG_CTL(cpu_transcoder), val);
+}
+
void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -261,4 +274,7 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
/* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
+
+ /* Program Enable Cmtg */
+ intel_cmtg_ctl_enable(crtc_state);
}
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (7 preceding siblings ...)
2026-02-03 13:44 ` [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl Animesh Manna
@ 2026-02-03 13:44 ` Animesh Manna
2026-02-05 8:53 ` Jani Nikula
2026-02-03 13:44 ` [PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder disable Animesh Manna
` (9 subsequent siblings)
18 siblings, 1 reply; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:44 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, jani.nikula, Animesh Manna
From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Wait for CMTG_SYNC_TO_PORT bit clear in cmtg enable sequence
and then enable secondary mode for cmtg.
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index f7364c7408d5..d1ec9b79cef2 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -277,4 +277,18 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
/* Program Enable Cmtg */
intel_cmtg_ctl_enable(crtc_state);
+
+ if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
+ CMTG_SYNC_TO_PORT, 50)) {
+ drm_WARN(display->drm, 1, "CMTG:%d enable timeout\n", cpu_transcoder);
+ return;
+ }
+
+ /*
+ * eDP transcoder registers as secondary to CMTG by setting
+ * TRANS_DDI_FUNC_CTL2[CMTG Secondary Mode].
+ */
+ intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+
+ drm_dbg_kms(display->drm, "CMTG:%d enabled\n", cpu_transcoder);
}
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder disable
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (8 preceding siblings ...)
2026-02-03 13:44 ` [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode Animesh Manna
@ 2026-02-03 13:44 ` Animesh Manna
2026-02-06 3:31 ` Kandpal, Suraj
2026-02-03 14:53 ` ✓ CI.KUnit: success for CMTG enablement (rev2) Patchwork
` (8 subsequent siblings)
18 siblings, 1 reply; 35+ messages in thread
From: Animesh Manna @ 2026-02-03 13:44 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: dibin.moolakadan.subrahmanian, jani.nikula
From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Add intel_cmtg_disable() to disable CMTG when the transcoder is disabled.
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 33 +++++++++++++++++--
drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
.../gpu/drm/i915/display/intel_cmtg_regs.h | 1 +
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
5 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index d1ec9b79cef2..844e01b6fc9f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -18,6 +18,7 @@
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_vrr.h"
+#include "intel_vrr_regs.h"
/**
* DOC: Common Primary Timing Generator (CMTG)
@@ -126,8 +127,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
}
-static void intel_cmtg_disable(struct intel_display *display,
- struct intel_cmtg_config *cmtg_config)
+static void intel_cmtg_disable_all(struct intel_display *display,
+ struct intel_cmtg_config *cmtg_config)
{
u32 clk_sel_clr = 0;
u32 clk_sel_set = 0;
@@ -158,6 +159,32 @@ static void intel_cmtg_disable(struct intel_display *display,
intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
}
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 val;
+
+ if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
+ return;
+
+ val = intel_de_read(display, TRANS_VRR_CTL_CMTG(cpu_transcoder));
+ val &= ~VRR_CTL_VRR_ENABLE;
+ val &= ~VRR_CTL_FLIP_LINE_EN;
+ intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), val);
+
+ intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
+ PORT_SYNC_MODE_ENABLE, 0);
+
+ intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
+
+ if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
+ drm_WARN(display->drm, 1, "CMTG:%d disable timeout\n", cpu_transcoder);
+ return;
+ }
+
+ drm_dbg_kms(display->drm, "CMTG:%d disabled\n", cpu_transcoder);
+}
/*
* Read out CMTG configuration and, on platforms that allow disabling it without
* a modeset, do it.
@@ -185,7 +212,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
return;
- intel_cmtg_disable(display, &cmtg_config);
+ intel_cmtg_disable_all(display, &cmtg_config);
}
void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index b2bb60d160fa..4f70577be136 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -10,6 +10,7 @@ struct intel_display;
struct intel_crtc_state;
void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
void intel_cmtg_sanitize(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 0ed767a797c0..f11d5514c376 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -21,6 +21,7 @@
#define TRANS_CMTG_CTL(id) _MMIO(0x6fa88 + (id) * 0x100)
#define CMTG_ENABLE REG_BIT(31)
#define CMTG_SYNC_TO_PORT REG_BIT(29)
+#define CMTG_STATE REG_BIT(23)
#define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) * 0x100)
#define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) * 0x100)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index b71a8d97cdbb..37a6a139f67b 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -35,6 +35,7 @@
#include <drm/drm_probe_helper.h>
#include <video/vga.h>
+#include "intel_cmtg.h"
#include "intel_connector.h"
#include "intel_crt.h"
#include "intel_crt_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 976af9eb3c3a..622f9b690342 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1773,6 +1773,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
struct intel_crtc *pipe_crtc;
int i;
+ intel_cmtg_disable(old_crtc_state);
/*
* FIXME collapse everything to one hook.
* Need care with mst->ddi interactions.
--
2.29.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* ✓ CI.KUnit: success for CMTG enablement (rev2)
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (9 preceding siblings ...)
2026-02-03 13:44 ` [PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder disable Animesh Manna
@ 2026-02-03 14:53 ` Patchwork
2026-02-03 15:08 ` ✗ CI.checksparse: warning " Patchwork
` (7 subsequent siblings)
18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2026-02-03 14:53 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-xe
== Series Details ==
Series: CMTG enablement (rev2)
URL : https://patchwork.freedesktop.org/series/157663/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:51:44] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:51:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:52:21] Starting KUnit Kernel (1/1)...
[14:52:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:52:21] ================== guc_buf (11 subtests) ===================
[14:52:21] [PASSED] test_smallest
[14:52:21] [PASSED] test_largest
[14:52:21] [PASSED] test_granular
[14:52:21] [PASSED] test_unique
[14:52:21] [PASSED] test_overlap
[14:52:21] [PASSED] test_reusable
[14:52:21] [PASSED] test_too_big
[14:52:21] [PASSED] test_flush
[14:52:21] [PASSED] test_lookup
[14:52:21] [PASSED] test_data
[14:52:21] [PASSED] test_class
[14:52:21] ===================== [PASSED] guc_buf =====================
[14:52:21] =================== guc_dbm (7 subtests) ===================
[14:52:21] [PASSED] test_empty
[14:52:21] [PASSED] test_default
[14:52:21] ======================== test_size ========================
[14:52:21] [PASSED] 4
[14:52:21] [PASSED] 8
[14:52:21] [PASSED] 32
[14:52:21] [PASSED] 256
[14:52:21] ==================== [PASSED] test_size ====================
[14:52:21] ======================= test_reuse ========================
[14:52:21] [PASSED] 4
[14:52:21] [PASSED] 8
[14:52:21] [PASSED] 32
[14:52:21] [PASSED] 256
[14:52:21] =================== [PASSED] test_reuse ====================
[14:52:21] =================== test_range_overlap ====================
[14:52:21] [PASSED] 4
[14:52:21] [PASSED] 8
[14:52:21] [PASSED] 32
[14:52:21] [PASSED] 256
[14:52:21] =============== [PASSED] test_range_overlap ================
[14:52:21] =================== test_range_compact ====================
[14:52:21] [PASSED] 4
[14:52:21] [PASSED] 8
[14:52:21] [PASSED] 32
[14:52:21] [PASSED] 256
[14:52:21] =============== [PASSED] test_range_compact ================
[14:52:21] ==================== test_range_spare =====================
[14:52:21] [PASSED] 4
[14:52:21] [PASSED] 8
[14:52:21] [PASSED] 32
[14:52:21] [PASSED] 256
[14:52:21] ================ [PASSED] test_range_spare =================
[14:52:21] ===================== [PASSED] guc_dbm =====================
[14:52:21] =================== guc_idm (6 subtests) ===================
[14:52:21] [PASSED] bad_init
[14:52:21] [PASSED] no_init
[14:52:21] [PASSED] init_fini
[14:52:21] [PASSED] check_used
[14:52:21] [PASSED] check_quota
[14:52:21] [PASSED] check_all
[14:52:21] ===================== [PASSED] guc_idm =====================
[14:52:21] ================== no_relay (3 subtests) ===================
[14:52:21] [PASSED] xe_drops_guc2pf_if_not_ready
[14:52:21] [PASSED] xe_drops_guc2vf_if_not_ready
[14:52:21] [PASSED] xe_rejects_send_if_not_ready
[14:52:21] ==================== [PASSED] no_relay =====================
[14:52:21] ================== pf_relay (14 subtests) ==================
[14:52:21] [PASSED] pf_rejects_guc2pf_too_short
[14:52:21] [PASSED] pf_rejects_guc2pf_too_long
[14:52:21] [PASSED] pf_rejects_guc2pf_no_payload
[14:52:21] [PASSED] pf_fails_no_payload
[14:52:21] [PASSED] pf_fails_bad_origin
[14:52:21] [PASSED] pf_fails_bad_type
[14:52:21] [PASSED] pf_txn_reports_error
[14:52:21] [PASSED] pf_txn_sends_pf2guc
[14:52:21] [PASSED] pf_sends_pf2guc
[14:52:21] [SKIPPED] pf_loopback_nop
[14:52:21] [SKIPPED] pf_loopback_echo
[14:52:21] [SKIPPED] pf_loopback_fail
[14:52:21] [SKIPPED] pf_loopback_busy
[14:52:21] [SKIPPED] pf_loopback_retry
[14:52:21] ==================== [PASSED] pf_relay =====================
[14:52:21] ================== vf_relay (3 subtests) ===================
[14:52:21] [PASSED] vf_rejects_guc2vf_too_short
[14:52:21] [PASSED] vf_rejects_guc2vf_too_long
[14:52:21] [PASSED] vf_rejects_guc2vf_no_payload
[14:52:21] ==================== [PASSED] vf_relay =====================
[14:52:21] ================ pf_gt_config (6 subtests) =================
[14:52:21] [PASSED] fair_contexts_1vf
[14:52:21] [PASSED] fair_doorbells_1vf
[14:52:21] [PASSED] fair_ggtt_1vf
[14:52:21] ====================== fair_contexts ======================
[14:52:21] [PASSED] 1 VF
[14:52:21] [PASSED] 2 VFs
[14:52:21] [PASSED] 3 VFs
[14:52:21] [PASSED] 4 VFs
[14:52:21] [PASSED] 5 VFs
[14:52:21] [PASSED] 6 VFs
[14:52:21] [PASSED] 7 VFs
[14:52:21] [PASSED] 8 VFs
[14:52:21] [PASSED] 9 VFs
[14:52:21] [PASSED] 10 VFs
[14:52:21] [PASSED] 11 VFs
[14:52:21] [PASSED] 12 VFs
[14:52:21] [PASSED] 13 VFs
[14:52:21] [PASSED] 14 VFs
[14:52:21] [PASSED] 15 VFs
[14:52:21] [PASSED] 16 VFs
[14:52:21] [PASSED] 17 VFs
[14:52:21] [PASSED] 18 VFs
[14:52:21] [PASSED] 19 VFs
[14:52:21] [PASSED] 20 VFs
[14:52:21] [PASSED] 21 VFs
[14:52:21] [PASSED] 22 VFs
[14:52:21] [PASSED] 23 VFs
[14:52:21] [PASSED] 24 VFs
[14:52:21] [PASSED] 25 VFs
[14:52:21] [PASSED] 26 VFs
[14:52:21] [PASSED] 27 VFs
[14:52:21] [PASSED] 28 VFs
[14:52:21] [PASSED] 29 VFs
[14:52:21] [PASSED] 30 VFs
[14:52:21] [PASSED] 31 VFs
[14:52:21] [PASSED] 32 VFs
[14:52:21] [PASSED] 33 VFs
[14:52:21] [PASSED] 34 VFs
[14:52:21] [PASSED] 35 VFs
[14:52:21] [PASSED] 36 VFs
[14:52:21] [PASSED] 37 VFs
[14:52:21] [PASSED] 38 VFs
[14:52:21] [PASSED] 39 VFs
[14:52:21] [PASSED] 40 VFs
[14:52:21] [PASSED] 41 VFs
[14:52:21] [PASSED] 42 VFs
[14:52:21] [PASSED] 43 VFs
[14:52:21] [PASSED] 44 VFs
[14:52:21] [PASSED] 45 VFs
[14:52:21] [PASSED] 46 VFs
[14:52:21] [PASSED] 47 VFs
[14:52:21] [PASSED] 48 VFs
[14:52:21] [PASSED] 49 VFs
[14:52:21] [PASSED] 50 VFs
[14:52:21] [PASSED] 51 VFs
[14:52:21] [PASSED] 52 VFs
[14:52:21] [PASSED] 53 VFs
[14:52:21] [PASSED] 54 VFs
[14:52:21] [PASSED] 55 VFs
[14:52:21] [PASSED] 56 VFs
[14:52:21] [PASSED] 57 VFs
[14:52:21] [PASSED] 58 VFs
[14:52:21] [PASSED] 59 VFs
[14:52:21] [PASSED] 60 VFs
[14:52:21] [PASSED] 61 VFs
[14:52:21] [PASSED] 62 VFs
[14:52:21] [PASSED] 63 VFs
[14:52:21] ================== [PASSED] fair_contexts ==================
[14:52:21] ===================== fair_doorbells ======================
[14:52:21] [PASSED] 1 VF
[14:52:21] [PASSED] 2 VFs
[14:52:21] [PASSED] 3 VFs
[14:52:21] [PASSED] 4 VFs
[14:52:21] [PASSED] 5 VFs
[14:52:21] [PASSED] 6 VFs
[14:52:21] [PASSED] 7 VFs
[14:52:21] [PASSED] 8 VFs
[14:52:21] [PASSED] 9 VFs
[14:52:21] [PASSED] 10 VFs
[14:52:21] [PASSED] 11 VFs
[14:52:21] [PASSED] 12 VFs
[14:52:21] [PASSED] 13 VFs
[14:52:21] [PASSED] 14 VFs
[14:52:21] [PASSED] 15 VFs
[14:52:21] [PASSED] 16 VFs
[14:52:21] [PASSED] 17 VFs
[14:52:21] [PASSED] 18 VFs
[14:52:21] [PASSED] 19 VFs
[14:52:21] [PASSED] 20 VFs
[14:52:21] [PASSED] 21 VFs
[14:52:21] [PASSED] 22 VFs
[14:52:21] [PASSED] 23 VFs
[14:52:21] [PASSED] 24 VFs
[14:52:21] [PASSED] 25 VFs
[14:52:21] [PASSED] 26 VFs
[14:52:21] [PASSED] 27 VFs
[14:52:21] [PASSED] 28 VFs
[14:52:21] [PASSED] 29 VFs
[14:52:21] [PASSED] 30 VFs
[14:52:21] [PASSED] 31 VFs
[14:52:21] [PASSED] 32 VFs
[14:52:21] [PASSED] 33 VFs
[14:52:21] [PASSED] 34 VFs
[14:52:21] [PASSED] 35 VFs
[14:52:21] [PASSED] 36 VFs
[14:52:21] [PASSED] 37 VFs
[14:52:21] [PASSED] 38 VFs
[14:52:21] [PASSED] 39 VFs
[14:52:21] [PASSED] 40 VFs
[14:52:21] [PASSED] 41 VFs
[14:52:21] [PASSED] 42 VFs
[14:52:21] [PASSED] 43 VFs
[14:52:21] [PASSED] 44 VFs
[14:52:21] [PASSED] 45 VFs
[14:52:21] [PASSED] 46 VFs
[14:52:21] [PASSED] 47 VFs
[14:52:21] [PASSED] 48 VFs
[14:52:21] [PASSED] 49 VFs
[14:52:21] [PASSED] 50 VFs
[14:52:21] [PASSED] 51 VFs
[14:52:21] [PASSED] 52 VFs
[14:52:21] [PASSED] 53 VFs
[14:52:21] [PASSED] 54 VFs
[14:52:21] [PASSED] 55 VFs
[14:52:21] [PASSED] 56 VFs
[14:52:21] [PASSED] 57 VFs
[14:52:21] [PASSED] 58 VFs
[14:52:21] [PASSED] 59 VFs
[14:52:21] [PASSED] 60 VFs
[14:52:21] [PASSED] 61 VFs
[14:52:21] [PASSED] 62 VFs
[14:52:21] [PASSED] 63 VFs
[14:52:21] ================= [PASSED] fair_doorbells ==================
[14:52:21] ======================== fair_ggtt ========================
[14:52:21] [PASSED] 1 VF
[14:52:21] [PASSED] 2 VFs
[14:52:21] [PASSED] 3 VFs
[14:52:21] [PASSED] 4 VFs
[14:52:21] [PASSED] 5 VFs
[14:52:21] [PASSED] 6 VFs
[14:52:21] [PASSED] 7 VFs
[14:52:21] [PASSED] 8 VFs
[14:52:21] [PASSED] 9 VFs
[14:52:21] [PASSED] 10 VFs
[14:52:21] [PASSED] 11 VFs
[14:52:21] [PASSED] 12 VFs
[14:52:21] [PASSED] 13 VFs
[14:52:21] [PASSED] 14 VFs
[14:52:21] [PASSED] 15 VFs
[14:52:21] [PASSED] 16 VFs
[14:52:21] [PASSED] 17 VFs
[14:52:21] [PASSED] 18 VFs
[14:52:21] [PASSED] 19 VFs
[14:52:21] [PASSED] 20 VFs
[14:52:21] [PASSED] 21 VFs
[14:52:21] [PASSED] 22 VFs
[14:52:21] [PASSED] 23 VFs
[14:52:21] [PASSED] 24 VFs
[14:52:21] [PASSED] 25 VFs
[14:52:21] [PASSED] 26 VFs
[14:52:21] [PASSED] 27 VFs
[14:52:21] [PASSED] 28 VFs
[14:52:21] [PASSED] 29 VFs
[14:52:21] [PASSED] 30 VFs
[14:52:21] [PASSED] 31 VFs
[14:52:21] [PASSED] 32 VFs
[14:52:21] [PASSED] 33 VFs
[14:52:21] [PASSED] 34 VFs
[14:52:21] [PASSED] 35 VFs
[14:52:21] [PASSED] 36 VFs
[14:52:21] [PASSED] 37 VFs
[14:52:21] [PASSED] 38 VFs
[14:52:21] [PASSED] 39 VFs
[14:52:21] [PASSED] 40 VFs
[14:52:21] [PASSED] 41 VFs
[14:52:21] [PASSED] 42 VFs
[14:52:21] [PASSED] 43 VFs
[14:52:21] [PASSED] 44 VFs
[14:52:21] [PASSED] 45 VFs
[14:52:21] [PASSED] 46 VFs
[14:52:21] [PASSED] 47 VFs
[14:52:21] [PASSED] 48 VFs
[14:52:21] [PASSED] 49 VFs
[14:52:21] [PASSED] 50 VFs
[14:52:21] [PASSED] 51 VFs
[14:52:21] [PASSED] 52 VFs
[14:52:21] [PASSED] 53 VFs
[14:52:21] [PASSED] 54 VFs
[14:52:21] [PASSED] 55 VFs
[14:52:21] [PASSED] 56 VFs
[14:52:21] [PASSED] 57 VFs
[14:52:21] [PASSED] 58 VFs
[14:52:21] [PASSED] 59 VFs
[14:52:21] [PASSED] 60 VFs
[14:52:21] [PASSED] 61 VFs
[14:52:21] [PASSED] 62 VFs
[14:52:21] [PASSED] 63 VFs
[14:52:21] ==================== [PASSED] fair_ggtt ====================
[14:52:21] ================== [PASSED] pf_gt_config ===================
[14:52:21] ===================== lmtt (1 subtest) =====================
[14:52:21] ======================== test_ops =========================
[14:52:21] [PASSED] 2-level
[14:52:21] [PASSED] multi-level
[14:52:21] ==================== [PASSED] test_ops =====================
[14:52:21] ====================== [PASSED] lmtt =======================
[14:52:21] ================= pf_service (11 subtests) =================
[14:52:21] [PASSED] pf_negotiate_any
[14:52:21] [PASSED] pf_negotiate_base_match
[14:52:21] [PASSED] pf_negotiate_base_newer
[14:52:21] [PASSED] pf_negotiate_base_next
[14:52:21] [SKIPPED] pf_negotiate_base_older
[14:52:21] [PASSED] pf_negotiate_base_prev
[14:52:21] [PASSED] pf_negotiate_latest_match
[14:52:21] [PASSED] pf_negotiate_latest_newer
[14:52:21] [PASSED] pf_negotiate_latest_next
[14:52:21] [SKIPPED] pf_negotiate_latest_older
[14:52:21] [SKIPPED] pf_negotiate_latest_prev
[14:52:21] =================== [PASSED] pf_service ====================
[14:52:21] ================= xe_guc_g2g (2 subtests) ==================
[14:52:21] ============== xe_live_guc_g2g_kunit_default ==============
[14:52:21] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[14:52:21] ============== xe_live_guc_g2g_kunit_allmem ===============
[14:52:21] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[14:52:21] =================== [SKIPPED] xe_guc_g2g ===================
[14:52:21] =================== xe_mocs (2 subtests) ===================
[14:52:21] ================ xe_live_mocs_kernel_kunit ================
[14:52:21] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[14:52:21] ================ xe_live_mocs_reset_kunit =================
[14:52:21] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[14:52:21] ==================== [SKIPPED] xe_mocs =====================
[14:52:21] ================= xe_migrate (2 subtests) ==================
[14:52:21] ================= xe_migrate_sanity_kunit =================
[14:52:21] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[14:52:21] ================== xe_validate_ccs_kunit ==================
[14:52:21] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[14:52:21] =================== [SKIPPED] xe_migrate ===================
[14:52:21] ================== xe_dma_buf (1 subtest) ==================
[14:52:21] ==================== xe_dma_buf_kunit =====================
[14:52:21] ================ [SKIPPED] xe_dma_buf_kunit ================
[14:52:21] =================== [SKIPPED] xe_dma_buf ===================
[14:52:21] ================= xe_bo_shrink (1 subtest) =================
[14:52:21] =================== xe_bo_shrink_kunit ====================
[14:52:21] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[14:52:21] ================== [SKIPPED] xe_bo_shrink ==================
[14:52:21] ==================== xe_bo (2 subtests) ====================
[14:52:21] ================== xe_ccs_migrate_kunit ===================
[14:52:21] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[14:52:21] ==================== xe_bo_evict_kunit ====================
[14:52:21] =============== [SKIPPED] xe_bo_evict_kunit ================
[14:52:21] ===================== [SKIPPED] xe_bo ======================
[14:52:21] ==================== args (13 subtests) ====================
[14:52:21] [PASSED] count_args_test
[14:52:21] [PASSED] call_args_example
[14:52:21] [PASSED] call_args_test
[14:52:21] [PASSED] drop_first_arg_example
[14:52:21] [PASSED] drop_first_arg_test
[14:52:21] [PASSED] first_arg_example
[14:52:21] [PASSED] first_arg_test
[14:52:21] [PASSED] last_arg_example
[14:52:21] [PASSED] last_arg_test
[14:52:21] [PASSED] pick_arg_example
[14:52:21] [PASSED] if_args_example
[14:52:21] [PASSED] if_args_test
[14:52:21] [PASSED] sep_comma_example
[14:52:21] ====================== [PASSED] args =======================
[14:52:21] =================== xe_pci (3 subtests) ====================
[14:52:21] ==================== check_graphics_ip ====================
[14:52:21] [PASSED] 12.00 Xe_LP
[14:52:21] [PASSED] 12.10 Xe_LP+
[14:52:21] [PASSED] 12.55 Xe_HPG
[14:52:21] [PASSED] 12.60 Xe_HPC
[14:52:21] [PASSED] 12.70 Xe_LPG
[14:52:21] [PASSED] 12.71 Xe_LPG
[14:52:21] [PASSED] 12.74 Xe_LPG+
[14:52:21] [PASSED] 20.01 Xe2_HPG
[14:52:21] [PASSED] 20.02 Xe2_HPG
[14:52:21] [PASSED] 20.04 Xe2_LPG
[14:52:21] [PASSED] 30.00 Xe3_LPG
[14:52:21] [PASSED] 30.01 Xe3_LPG
[14:52:21] [PASSED] 30.03 Xe3_LPG
[14:52:21] [PASSED] 30.04 Xe3_LPG
[14:52:21] [PASSED] 30.05 Xe3_LPG
[14:52:21] [PASSED] 35.11 Xe3p_XPC
[14:52:21] ================ [PASSED] check_graphics_ip ================
[14:52:21] ===================== check_media_ip ======================
[14:52:21] [PASSED] 12.00 Xe_M
[14:52:21] [PASSED] 12.55 Xe_HPM
[14:52:21] [PASSED] 13.00 Xe_LPM+
[14:52:21] [PASSED] 13.01 Xe2_HPM
[14:52:21] [PASSED] 20.00 Xe2_LPM
[14:52:21] [PASSED] 30.00 Xe3_LPM
[14:52:21] [PASSED] 30.02 Xe3_LPM
[14:52:21] [PASSED] 35.00 Xe3p_LPM
[14:52:21] [PASSED] 35.03 Xe3p_HPM
[14:52:21] ================= [PASSED] check_media_ip ==================
[14:52:21] =================== check_platform_desc ===================
[14:52:21] [PASSED] 0x9A60 (TIGERLAKE)
[14:52:21] [PASSED] 0x9A68 (TIGERLAKE)
[14:52:21] [PASSED] 0x9A70 (TIGERLAKE)
[14:52:21] [PASSED] 0x9A40 (TIGERLAKE)
[14:52:21] [PASSED] 0x9A49 (TIGERLAKE)
[14:52:21] [PASSED] 0x9A59 (TIGERLAKE)
[14:52:21] [PASSED] 0x9A78 (TIGERLAKE)
[14:52:21] [PASSED] 0x9AC0 (TIGERLAKE)
[14:52:21] [PASSED] 0x9AC9 (TIGERLAKE)
[14:52:21] [PASSED] 0x9AD9 (TIGERLAKE)
[14:52:21] [PASSED] 0x9AF8 (TIGERLAKE)
[14:52:21] [PASSED] 0x4C80 (ROCKETLAKE)
[14:52:21] [PASSED] 0x4C8A (ROCKETLAKE)
[14:52:21] [PASSED] 0x4C8B (ROCKETLAKE)
[14:52:21] [PASSED] 0x4C8C (ROCKETLAKE)
[14:52:21] [PASSED] 0x4C90 (ROCKETLAKE)
[14:52:21] [PASSED] 0x4C9A (ROCKETLAKE)
[14:52:21] [PASSED] 0x4680 (ALDERLAKE_S)
[14:52:21] [PASSED] 0x4682 (ALDERLAKE_S)
[14:52:21] [PASSED] 0x4688 (ALDERLAKE_S)
[14:52:21] [PASSED] 0x468A (ALDERLAKE_S)
[14:52:21] [PASSED] 0x468B (ALDERLAKE_S)
[14:52:21] [PASSED] 0x4690 (ALDERLAKE_S)
[14:52:21] [PASSED] 0x4692 (ALDERLAKE_S)
[14:52:21] [PASSED] 0x4693 (ALDERLAKE_S)
[14:52:21] [PASSED] 0x46A0 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46A1 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46A2 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46A3 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46A6 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46A8 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46AA (ALDERLAKE_P)
[14:52:21] [PASSED] 0x462A (ALDERLAKE_P)
[14:52:21] [PASSED] 0x4626 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[14:52:21] [PASSED] 0x46B0 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46B1 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46B2 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46B3 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46C0 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46C1 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46C2 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46C3 (ALDERLAKE_P)
[14:52:21] [PASSED] 0x46D0 (ALDERLAKE_N)
[14:52:21] [PASSED] 0x46D1 (ALDERLAKE_N)
[14:52:21] [PASSED] 0x46D2 (ALDERLAKE_N)
[14:52:21] [PASSED] 0x46D3 (ALDERLAKE_N)
[14:52:21] [PASSED] 0x46D4 (ALDERLAKE_N)
[14:52:21] [PASSED] 0xA721 (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA7A1 (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA7A9 (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA7AC (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA7AD (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA720 (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA7A0 (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA7A8 (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA7AA (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA7AB (ALDERLAKE_P)
[14:52:21] [PASSED] 0xA780 (ALDERLAKE_S)
[14:52:21] [PASSED] 0xA781 (ALDERLAKE_S)
[14:52:21] [PASSED] 0xA782 (ALDERLAKE_S)
[14:52:21] [PASSED] 0xA783 (ALDERLAKE_S)
[14:52:21] [PASSED] 0xA788 (ALDERLAKE_S)
[14:52:21] [PASSED] 0xA789 (ALDERLAKE_S)
[14:52:21] [PASSED] 0xA78A (ALDERLAKE_S)
[14:52:21] [PASSED] 0xA78B (ALDERLAKE_S)
[14:52:21] [PASSED] 0x4905 (DG1)
[14:52:21] [PASSED] 0x4906 (DG1)
[14:52:21] [PASSED] 0x4907 (DG1)
[14:52:21] [PASSED] 0x4908 (DG1)
[14:52:21] [PASSED] 0x4909 (DG1)
[14:52:21] [PASSED] 0x56C0 (DG2)
[14:52:21] [PASSED] 0x56C2 (DG2)
[14:52:21] [PASSED] 0x56C1 (DG2)
[14:52:21] [PASSED] 0x7D51 (METEORLAKE)
[14:52:21] [PASSED] 0x7DD1 (METEORLAKE)
[14:52:21] [PASSED] 0x7D41 (METEORLAKE)
[14:52:21] [PASSED] 0x7D67 (METEORLAKE)
[14:52:21] [PASSED] 0xB640 (METEORLAKE)
[14:52:21] [PASSED] 0x56A0 (DG2)
[14:52:21] [PASSED] 0x56A1 (DG2)
[14:52:21] [PASSED] 0x56A2 (DG2)
[14:52:21] [PASSED] 0x56BE (DG2)
[14:52:21] [PASSED] 0x56BF (DG2)
[14:52:21] [PASSED] 0x5690 (DG2)
[14:52:21] [PASSED] 0x5691 (DG2)
[14:52:21] [PASSED] 0x5692 (DG2)
[14:52:21] [PASSED] 0x56A5 (DG2)
[14:52:21] [PASSED] 0x56A6 (DG2)
[14:52:21] [PASSED] 0x56B0 (DG2)
[14:52:21] [PASSED] 0x56B1 (DG2)
[14:52:21] [PASSED] 0x56BA (DG2)
[14:52:21] [PASSED] 0x56BB (DG2)
[14:52:21] [PASSED] 0x56BC (DG2)
[14:52:21] [PASSED] 0x56BD (DG2)
[14:52:21] [PASSED] 0x5693 (DG2)
[14:52:21] [PASSED] 0x5694 (DG2)
[14:52:21] [PASSED] 0x5695 (DG2)
[14:52:21] [PASSED] 0x56A3 (DG2)
[14:52:21] [PASSED] 0x56A4 (DG2)
[14:52:21] [PASSED] 0x56B2 (DG2)
[14:52:21] [PASSED] 0x56B3 (DG2)
[14:52:21] [PASSED] 0x5696 (DG2)
[14:52:21] [PASSED] 0x5697 (DG2)
[14:52:21] [PASSED] 0xB69 (PVC)
[14:52:21] [PASSED] 0xB6E (PVC)
[14:52:21] [PASSED] 0xBD4 (PVC)
[14:52:21] [PASSED] 0xBD5 (PVC)
[14:52:21] [PASSED] 0xBD6 (PVC)
[14:52:21] [PASSED] 0xBD7 (PVC)
[14:52:21] [PASSED] 0xBD8 (PVC)
[14:52:21] [PASSED] 0xBD9 (PVC)
[14:52:21] [PASSED] 0xBDA (PVC)
[14:52:21] [PASSED] 0xBDB (PVC)
[14:52:21] [PASSED] 0xBE0 (PVC)
[14:52:21] [PASSED] 0xBE1 (PVC)
[14:52:21] [PASSED] 0xBE5 (PVC)
[14:52:21] [PASSED] 0x7D40 (METEORLAKE)
[14:52:21] [PASSED] 0x7D45 (METEORLAKE)
[14:52:21] [PASSED] 0x7D55 (METEORLAKE)
[14:52:21] [PASSED] 0x7D60 (METEORLAKE)
[14:52:21] [PASSED] 0x7DD5 (METEORLAKE)
[14:52:21] [PASSED] 0x6420 (LUNARLAKE)
[14:52:21] [PASSED] 0x64A0 (LUNARLAKE)
[14:52:21] [PASSED] 0x64B0 (LUNARLAKE)
[14:52:21] [PASSED] 0xE202 (BATTLEMAGE)
[14:52:21] [PASSED] 0xE209 (BATTLEMAGE)
[14:52:21] [PASSED] 0xE20B (BATTLEMAGE)
[14:52:21] [PASSED] 0xE20C (BATTLEMAGE)
[14:52:21] [PASSED] 0xE20D (BATTLEMAGE)
[14:52:21] [PASSED] 0xE210 (BATTLEMAGE)
[14:52:21] [PASSED] 0xE211 (BATTLEMAGE)
[14:52:21] [PASSED] 0xE212 (BATTLEMAGE)
[14:52:21] [PASSED] 0xE216 (BATTLEMAGE)
[14:52:21] [PASSED] 0xE220 (BATTLEMAGE)
[14:52:21] [PASSED] 0xE221 (BATTLEMAGE)
[14:52:21] [PASSED] 0xE222 (BATTLEMAGE)
[14:52:21] [PASSED] 0xE223 (BATTLEMAGE)
[14:52:21] [PASSED] 0xB080 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB081 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB082 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB083 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB084 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB085 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB086 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB087 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB08F (PANTHERLAKE)
[14:52:21] [PASSED] 0xB090 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB0A0 (PANTHERLAKE)
[14:52:21] [PASSED] 0xB0B0 (PANTHERLAKE)
[14:52:21] [PASSED] 0xFD80 (PANTHERLAKE)
[14:52:21] [PASSED] 0xFD81 (PANTHERLAKE)
[14:52:21] [PASSED] 0xD740 (NOVALAKE_S)
[14:52:21] [PASSED] 0xD741 (NOVALAKE_S)
[14:52:21] [PASSED] 0xD742 (NOVALAKE_S)
[14:52:21] [PASSED] 0xD743 (NOVALAKE_S)
[14:52:21] [PASSED] 0xD744 (NOVALAKE_S)
[14:52:21] [PASSED] 0xD745 (NOVALAKE_S)
[14:52:21] [PASSED] 0x674C (CRESCENTISLAND)
[14:52:21] =============== [PASSED] check_platform_desc ===============
[14:52:21] ===================== [PASSED] xe_pci ======================
[14:52:21] =================== xe_rtp (2 subtests) ====================
[14:52:21] =============== xe_rtp_process_to_sr_tests ================
[14:52:21] [PASSED] coalesce-same-reg
[14:52:21] [PASSED] no-match-no-add
[14:52:21] [PASSED] match-or
[14:52:21] [PASSED] match-or-xfail
[14:52:21] [PASSED] no-match-no-add-multiple-rules
[14:52:21] [PASSED] two-regs-two-entries
[14:52:21] [PASSED] clr-one-set-other
[14:52:21] [PASSED] set-field
[14:52:21] [PASSED] conflict-duplicate
[14:52:21] [PASSED] conflict-not-disjoint
[14:52:21] [PASSED] conflict-reg-type
[14:52:21] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[14:52:21] ================== xe_rtp_process_tests ===================
[14:52:21] [PASSED] active1
[14:52:21] [PASSED] active2
[14:52:21] [PASSED] active-inactive
[14:52:21] [PASSED] inactive-active
[14:52:21] [PASSED] inactive-1st_or_active-inactive
[14:52:21] [PASSED] inactive-2nd_or_active-inactive
[14:52:21] [PASSED] inactive-last_or_active-inactive
[14:52:21] [PASSED] inactive-no_or_active-inactive
[14:52:21] ============== [PASSED] xe_rtp_process_tests ===============
[14:52:21] ===================== [PASSED] xe_rtp ======================
[14:52:21] ==================== xe_wa (1 subtest) =====================
[14:52:21] ======================== xe_wa_gt =========================
[14:52:21] [PASSED] TIGERLAKE B0
[14:52:21] [PASSED] DG1 A0
[14:52:21] [PASSED] DG1 B0
[14:52:21] [PASSED] ALDERLAKE_S A0
[14:52:21] [PASSED] ALDERLAKE_S B0
[14:52:21] [PASSED] ALDERLAKE_S C0
[14:52:21] [PASSED] ALDERLAKE_S D0
[14:52:21] [PASSED] ALDERLAKE_P A0
[14:52:21] [PASSED] ALDERLAKE_P B0
[14:52:21] [PASSED] ALDERLAKE_P C0
[14:52:21] [PASSED] ALDERLAKE_S RPLS D0
[14:52:21] [PASSED] ALDERLAKE_P RPLU E0
[14:52:21] [PASSED] DG2 G10 C0
[14:52:21] [PASSED] DG2 G11 B1
[14:52:21] [PASSED] DG2 G12 A1
[14:52:21] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:52:21] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:52:21] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[14:52:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[14:52:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[14:52:21] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[14:52:21] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[14:52:21] ==================== [PASSED] xe_wa_gt =====================
[14:52:21] ====================== [PASSED] xe_wa ======================
[14:52:21] ============================================================
[14:52:21] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[14:52:22] Elapsed time: 37.081s total, 4.216s configuring, 32.348s building, 0.467s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[14:52:22] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:52:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:52:49] Starting KUnit Kernel (1/1)...
[14:52:49] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:52:49] ============ drm_test_pick_cmdline (2 subtests) ============
[14:52:49] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[14:52:49] =============== drm_test_pick_cmdline_named ===============
[14:52:49] [PASSED] NTSC
[14:52:49] [PASSED] NTSC-J
[14:52:49] [PASSED] PAL
[14:52:49] [PASSED] PAL-M
[14:52:49] =========== [PASSED] drm_test_pick_cmdline_named ===========
[14:52:49] ============== [PASSED] drm_test_pick_cmdline ==============
[14:52:49] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:52:49] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:52:49] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:52:49] =========== drm_validate_clone_mode (2 subtests) ===========
[14:52:49] ============== drm_test_check_in_clone_mode ===============
[14:52:49] [PASSED] in_clone_mode
[14:52:49] [PASSED] not_in_clone_mode
[14:52:49] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:52:49] =============== drm_test_check_valid_clones ===============
[14:52:49] [PASSED] not_in_clone_mode
[14:52:49] [PASSED] valid_clone
[14:52:49] [PASSED] invalid_clone
[14:52:49] =========== [PASSED] drm_test_check_valid_clones ===========
[14:52:49] ============= [PASSED] drm_validate_clone_mode =============
[14:52:49] ============= drm_validate_modeset (1 subtest) =============
[14:52:49] [PASSED] drm_test_check_connector_changed_modeset
[14:52:49] ============== [PASSED] drm_validate_modeset ===============
[14:52:49] ====== drm_test_bridge_get_current_state (2 subtests) ======
[14:52:49] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:52:49] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[14:52:49] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:52:49] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:52:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:52:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:52:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[14:52:49] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:52:49] ============== drm_bridge_alloc (2 subtests) ===============
[14:52:49] [PASSED] drm_test_drm_bridge_alloc_basic
[14:52:49] [PASSED] drm_test_drm_bridge_alloc_get_put
[14:52:49] ================ [PASSED] drm_bridge_alloc =================
[14:52:49] ================== drm_buddy (9 subtests) ==================
[14:52:49] [PASSED] drm_test_buddy_alloc_limit
[14:52:49] [PASSED] drm_test_buddy_alloc_optimistic
[14:52:49] [PASSED] drm_test_buddy_alloc_pessimistic
[14:52:49] [PASSED] drm_test_buddy_alloc_pathological
[14:52:49] [PASSED] drm_test_buddy_alloc_contiguous
[14:52:49] [PASSED] drm_test_buddy_alloc_clear
[14:52:50] [PASSED] drm_test_buddy_alloc_range_bias
[14:52:50] [PASSED] drm_test_buddy_fragmentation_performance
[14:52:50] [PASSED] drm_test_buddy_alloc_exceeds_max_order
[14:52:50] ==================== [PASSED] drm_buddy ====================
[14:52:50] ============= drm_cmdline_parser (40 subtests) =============
[14:52:50] [PASSED] drm_test_cmdline_force_d_only
[14:52:50] [PASSED] drm_test_cmdline_force_D_only_dvi
[14:52:50] [PASSED] drm_test_cmdline_force_D_only_hdmi
[14:52:50] [PASSED] drm_test_cmdline_force_D_only_not_digital
[14:52:50] [PASSED] drm_test_cmdline_force_e_only
[14:52:50] [PASSED] drm_test_cmdline_res
[14:52:50] [PASSED] drm_test_cmdline_res_vesa
[14:52:50] [PASSED] drm_test_cmdline_res_vesa_rblank
[14:52:50] [PASSED] drm_test_cmdline_res_rblank
[14:52:50] [PASSED] drm_test_cmdline_res_bpp
[14:52:50] [PASSED] drm_test_cmdline_res_refresh
[14:52:50] [PASSED] drm_test_cmdline_res_bpp_refresh
[14:52:50] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[14:52:50] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[14:52:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[14:52:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[14:52:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[14:52:50] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[14:52:50] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[14:52:50] [PASSED] drm_test_cmdline_res_margins_force_on
[14:52:50] [PASSED] drm_test_cmdline_res_vesa_margins
[14:52:50] [PASSED] drm_test_cmdline_name
[14:52:50] [PASSED] drm_test_cmdline_name_bpp
[14:52:50] [PASSED] drm_test_cmdline_name_option
[14:52:50] [PASSED] drm_test_cmdline_name_bpp_option
[14:52:50] [PASSED] drm_test_cmdline_rotate_0
[14:52:50] [PASSED] drm_test_cmdline_rotate_90
[14:52:50] [PASSED] drm_test_cmdline_rotate_180
[14:52:50] [PASSED] drm_test_cmdline_rotate_270
[14:52:50] [PASSED] drm_test_cmdline_hmirror
[14:52:50] [PASSED] drm_test_cmdline_vmirror
[14:52:50] [PASSED] drm_test_cmdline_margin_options
[14:52:50] [PASSED] drm_test_cmdline_multiple_options
[14:52:50] [PASSED] drm_test_cmdline_bpp_extra_and_option
[14:52:50] [PASSED] drm_test_cmdline_extra_and_option
[14:52:50] [PASSED] drm_test_cmdline_freestanding_options
[14:52:50] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[14:52:50] [PASSED] drm_test_cmdline_panel_orientation
[14:52:50] ================ drm_test_cmdline_invalid =================
[14:52:50] [PASSED] margin_only
[14:52:50] [PASSED] interlace_only
[14:52:50] [PASSED] res_missing_x
[14:52:50] [PASSED] res_missing_y
[14:52:50] [PASSED] res_bad_y
[14:52:50] [PASSED] res_missing_y_bpp
[14:52:50] [PASSED] res_bad_bpp
[14:52:50] [PASSED] res_bad_refresh
[14:52:50] [PASSED] res_bpp_refresh_force_on_off
[14:52:50] [PASSED] res_invalid_mode
[14:52:50] [PASSED] res_bpp_wrong_place_mode
[14:52:50] [PASSED] name_bpp_refresh
[14:52:50] [PASSED] name_refresh
[14:52:50] [PASSED] name_refresh_wrong_mode
[14:52:50] [PASSED] name_refresh_invalid_mode
[14:52:50] [PASSED] rotate_multiple
[14:52:50] [PASSED] rotate_invalid_val
[14:52:50] [PASSED] rotate_truncated
[14:52:50] [PASSED] invalid_option
[14:52:50] [PASSED] invalid_tv_option
[14:52:50] [PASSED] truncated_tv_option
[14:52:50] ============ [PASSED] drm_test_cmdline_invalid =============
[14:52:50] =============== drm_test_cmdline_tv_options ===============
[14:52:50] [PASSED] NTSC
[14:52:50] [PASSED] NTSC_443
[14:52:50] [PASSED] NTSC_J
[14:52:50] [PASSED] PAL
[14:52:50] [PASSED] PAL_M
[14:52:50] [PASSED] PAL_N
[14:52:50] [PASSED] SECAM
[14:52:50] [PASSED] MONO_525
[14:52:50] [PASSED] MONO_625
[14:52:50] =========== [PASSED] drm_test_cmdline_tv_options ===========
[14:52:50] =============== [PASSED] drm_cmdline_parser ================
[14:52:50] ========== drmm_connector_hdmi_init (20 subtests) ==========
[14:52:50] [PASSED] drm_test_connector_hdmi_init_valid
[14:52:50] [PASSED] drm_test_connector_hdmi_init_bpc_8
[14:52:50] [PASSED] drm_test_connector_hdmi_init_bpc_10
[14:52:50] [PASSED] drm_test_connector_hdmi_init_bpc_12
[14:52:50] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[14:52:50] [PASSED] drm_test_connector_hdmi_init_bpc_null
[14:52:50] [PASSED] drm_test_connector_hdmi_init_formats_empty
[14:52:50] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[14:52:50] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:52:50] [PASSED] supported_formats=0x9 yuv420_allowed=1
[14:52:50] [PASSED] supported_formats=0x9 yuv420_allowed=0
[14:52:50] [PASSED] supported_formats=0x3 yuv420_allowed=1
[14:52:50] [PASSED] supported_formats=0x3 yuv420_allowed=0
[14:52:50] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:52:50] [PASSED] drm_test_connector_hdmi_init_null_ddc
[14:52:50] [PASSED] drm_test_connector_hdmi_init_null_product
[14:52:50] [PASSED] drm_test_connector_hdmi_init_null_vendor
[14:52:50] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[14:52:50] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[14:52:50] [PASSED] drm_test_connector_hdmi_init_product_valid
[14:52:50] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[14:52:50] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[14:52:50] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[14:52:50] ========= drm_test_connector_hdmi_init_type_valid =========
[14:52:50] [PASSED] HDMI-A
[14:52:50] [PASSED] HDMI-B
[14:52:50] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[14:52:50] ======== drm_test_connector_hdmi_init_type_invalid ========
[14:52:50] [PASSED] Unknown
[14:52:50] [PASSED] VGA
[14:52:50] [PASSED] DVI-I
[14:52:50] [PASSED] DVI-D
[14:52:50] [PASSED] DVI-A
[14:52:50] [PASSED] Composite
[14:52:50] [PASSED] SVIDEO
[14:52:50] [PASSED] LVDS
[14:52:50] [PASSED] Component
[14:52:50] [PASSED] DIN
[14:52:50] [PASSED] DP
[14:52:50] [PASSED] TV
[14:52:50] [PASSED] eDP
[14:52:50] [PASSED] Virtual
[14:52:50] [PASSED] DSI
[14:52:50] [PASSED] DPI
[14:52:50] [PASSED] Writeback
[14:52:50] [PASSED] SPI
[14:52:50] [PASSED] USB
[14:52:50] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[14:52:50] ============ [PASSED] drmm_connector_hdmi_init =============
[14:52:50] ============= drmm_connector_init (3 subtests) =============
[14:52:50] [PASSED] drm_test_drmm_connector_init
[14:52:50] [PASSED] drm_test_drmm_connector_init_null_ddc
[14:52:50] ========= drm_test_drmm_connector_init_type_valid =========
[14:52:50] [PASSED] Unknown
[14:52:50] [PASSED] VGA
[14:52:50] [PASSED] DVI-I
[14:52:50] [PASSED] DVI-D
[14:52:50] [PASSED] DVI-A
[14:52:50] [PASSED] Composite
[14:52:50] [PASSED] SVIDEO
[14:52:50] [PASSED] LVDS
[14:52:50] [PASSED] Component
[14:52:50] [PASSED] DIN
[14:52:50] [PASSED] DP
[14:52:50] [PASSED] HDMI-A
[14:52:50] [PASSED] HDMI-B
[14:52:50] [PASSED] TV
[14:52:50] [PASSED] eDP
[14:52:50] [PASSED] Virtual
[14:52:50] [PASSED] DSI
[14:52:50] [PASSED] DPI
[14:52:50] [PASSED] Writeback
[14:52:50] [PASSED] SPI
[14:52:50] [PASSED] USB
[14:52:50] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[14:52:50] =============== [PASSED] drmm_connector_init ===============
[14:52:50] ========= drm_connector_dynamic_init (6 subtests) ==========
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_init
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_init_properties
[14:52:50] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[14:52:50] [PASSED] Unknown
[14:52:50] [PASSED] VGA
[14:52:50] [PASSED] DVI-I
[14:52:50] [PASSED] DVI-D
[14:52:50] [PASSED] DVI-A
[14:52:50] [PASSED] Composite
[14:52:50] [PASSED] SVIDEO
[14:52:50] [PASSED] LVDS
[14:52:50] [PASSED] Component
[14:52:50] [PASSED] DIN
[14:52:50] [PASSED] DP
[14:52:50] [PASSED] HDMI-A
[14:52:50] [PASSED] HDMI-B
[14:52:50] [PASSED] TV
[14:52:50] [PASSED] eDP
[14:52:50] [PASSED] Virtual
[14:52:50] [PASSED] DSI
[14:52:50] [PASSED] DPI
[14:52:50] [PASSED] Writeback
[14:52:50] [PASSED] SPI
[14:52:50] [PASSED] USB
[14:52:50] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[14:52:50] ======== drm_test_drm_connector_dynamic_init_name =========
[14:52:50] [PASSED] Unknown
[14:52:50] [PASSED] VGA
[14:52:50] [PASSED] DVI-I
[14:52:50] [PASSED] DVI-D
[14:52:50] [PASSED] DVI-A
[14:52:50] [PASSED] Composite
[14:52:50] [PASSED] SVIDEO
[14:52:50] [PASSED] LVDS
[14:52:50] [PASSED] Component
[14:52:50] [PASSED] DIN
[14:52:50] [PASSED] DP
[14:52:50] [PASSED] HDMI-A
[14:52:50] [PASSED] HDMI-B
[14:52:50] [PASSED] TV
[14:52:50] [PASSED] eDP
[14:52:50] [PASSED] Virtual
[14:52:50] [PASSED] DSI
[14:52:50] [PASSED] DPI
[14:52:50] [PASSED] Writeback
[14:52:50] [PASSED] SPI
[14:52:50] [PASSED] USB
[14:52:50] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[14:52:50] =========== [PASSED] drm_connector_dynamic_init ============
[14:52:50] ==== drm_connector_dynamic_register_early (4 subtests) =====
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[14:52:50] ====== [PASSED] drm_connector_dynamic_register_early =======
[14:52:50] ======= drm_connector_dynamic_register (7 subtests) ========
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[14:52:50] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[14:52:50] ========= [PASSED] drm_connector_dynamic_register ==========
[14:52:50] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[14:52:50] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[14:52:50] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[14:52:50] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[14:52:50] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[14:52:50] ========== drm_test_get_tv_mode_from_name_valid ===========
[14:52:50] [PASSED] NTSC
[14:52:50] [PASSED] NTSC-443
[14:52:50] [PASSED] NTSC-J
[14:52:50] [PASSED] PAL
[14:52:50] [PASSED] PAL-M
[14:52:50] [PASSED] PAL-N
[14:52:50] [PASSED] SECAM
[14:52:50] [PASSED] Mono
[14:52:50] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[14:52:50] [PASSED] drm_test_get_tv_mode_from_name_truncated
[14:52:50] ============ [PASSED] drm_get_tv_mode_from_name ============
[14:52:50] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[14:52:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[14:52:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[14:52:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[14:52:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[14:52:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[14:52:50] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[14:52:50] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[14:52:50] [PASSED] VIC 96
[14:52:50] [PASSED] VIC 97
[14:52:50] [PASSED] VIC 101
[14:52:50] [PASSED] VIC 102
[14:52:50] [PASSED] VIC 106
[14:52:50] [PASSED] VIC 107
[14:52:50] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[14:52:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[14:52:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[14:52:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[14:52:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[14:52:50] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[14:52:50] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[14:52:50] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[14:52:50] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[14:52:50] [PASSED] Automatic
[14:52:50] [PASSED] Full
[14:52:50] [PASSED] Limited 16:235
[14:52:50] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[14:52:50] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[14:52:50] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[14:52:50] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[14:52:50] === drm_test_drm_hdmi_connector_get_output_format_name ====
[14:52:50] [PASSED] RGB
[14:52:50] [PASSED] YUV 4:2:0
[14:52:50] [PASSED] YUV 4:2:2
[14:52:50] [PASSED] YUV 4:4:4
[14:52:50] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[14:52:50] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[14:52:50] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[14:52:50] ============= drm_damage_helper (21 subtests) ==============
[14:52:50] [PASSED] drm_test_damage_iter_no_damage
[14:52:50] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[14:52:50] [PASSED] drm_test_damage_iter_no_damage_src_moved
[14:52:50] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[14:52:50] [PASSED] drm_test_damage_iter_no_damage_not_visible
[14:52:50] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[14:52:50] [PASSED] drm_test_damage_iter_no_damage_no_fb
[14:52:50] [PASSED] drm_test_damage_iter_simple_damage
[14:52:50] [PASSED] drm_test_damage_iter_single_damage
[14:52:50] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[14:52:50] [PASSED] drm_test_damage_iter_single_damage_outside_src
[14:52:50] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[14:52:50] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[14:52:50] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[14:52:50] [PASSED] drm_test_damage_iter_single_damage_src_moved
[14:52:50] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[14:52:50] [PASSED] drm_test_damage_iter_damage
[14:52:50] [PASSED] drm_test_damage_iter_damage_one_intersect
[14:52:50] [PASSED] drm_test_damage_iter_damage_one_outside
[14:52:50] [PASSED] drm_test_damage_iter_damage_src_moved
[14:52:50] [PASSED] drm_test_damage_iter_damage_not_visible
[14:52:50] ================ [PASSED] drm_damage_helper ================
[14:52:50] ============== drm_dp_mst_helper (3 subtests) ==============
[14:52:50] ============== drm_test_dp_mst_calc_pbn_mode ==============
[14:52:50] [PASSED] Clock 154000 BPP 30 DSC disabled
[14:52:50] [PASSED] Clock 234000 BPP 30 DSC disabled
[14:52:50] [PASSED] Clock 297000 BPP 24 DSC disabled
[14:52:50] [PASSED] Clock 332880 BPP 24 DSC enabled
[14:52:50] [PASSED] Clock 324540 BPP 24 DSC enabled
[14:52:50] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[14:52:50] ============== drm_test_dp_mst_calc_pbn_div ===============
[14:52:50] [PASSED] Link rate 2000000 lane count 4
[14:52:50] [PASSED] Link rate 2000000 lane count 2
[14:52:50] [PASSED] Link rate 2000000 lane count 1
[14:52:50] [PASSED] Link rate 1350000 lane count 4
[14:52:50] [PASSED] Link rate 1350000 lane count 2
[14:52:50] [PASSED] Link rate 1350000 lane count 1
[14:52:50] [PASSED] Link rate 1000000 lane count 4
[14:52:50] [PASSED] Link rate 1000000 lane count 2
[14:52:50] [PASSED] Link rate 1000000 lane count 1
[14:52:50] [PASSED] Link rate 810000 lane count 4
[14:52:50] [PASSED] Link rate 810000 lane count 2
[14:52:50] [PASSED] Link rate 810000 lane count 1
[14:52:50] [PASSED] Link rate 540000 lane count 4
[14:52:50] [PASSED] Link rate 540000 lane count 2
[14:52:50] [PASSED] Link rate 540000 lane count 1
[14:52:50] [PASSED] Link rate 270000 lane count 4
[14:52:50] [PASSED] Link rate 270000 lane count 2
[14:52:50] [PASSED] Link rate 270000 lane count 1
[14:52:50] [PASSED] Link rate 162000 lane count 4
[14:52:50] [PASSED] Link rate 162000 lane count 2
[14:52:50] [PASSED] Link rate 162000 lane count 1
[14:52:50] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[14:52:50] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[14:52:50] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[14:52:50] [PASSED] DP_POWER_UP_PHY with port number
[14:52:50] [PASSED] DP_POWER_DOWN_PHY with port number
[14:52:50] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[14:52:50] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[14:52:50] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[14:52:50] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[14:52:50] [PASSED] DP_QUERY_PAYLOAD with port number
[14:52:50] [PASSED] DP_QUERY_PAYLOAD with VCPI
[14:52:50] [PASSED] DP_REMOTE_DPCD_READ with port number
[14:52:50] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[14:52:50] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[14:52:50] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[14:52:50] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[14:52:50] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[14:52:50] [PASSED] DP_REMOTE_I2C_READ with port number
[14:52:50] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[14:52:50] [PASSED] DP_REMOTE_I2C_READ with transactions array
[14:52:50] [PASSED] DP_REMOTE_I2C_WRITE with port number
[14:52:50] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[14:52:50] [PASSED] DP_REMOTE_I2C_WRITE with data array
[14:52:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[14:52:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[14:52:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[14:52:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[14:52:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[14:52:50] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[14:52:50] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[14:52:50] ================ [PASSED] drm_dp_mst_helper ================
[14:52:50] ================== drm_exec (7 subtests) ===================
[14:52:50] [PASSED] sanitycheck
[14:52:50] [PASSED] test_lock
[14:52:50] [PASSED] test_lock_unlock
[14:52:50] [PASSED] test_duplicates
[14:52:50] [PASSED] test_prepare
[14:52:50] [PASSED] test_prepare_array
[14:52:50] [PASSED] test_multiple_loops
[14:52:50] ==================== [PASSED] drm_exec =====================
[14:52:50] =========== drm_format_helper_test (17 subtests) ===========
[14:52:50] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[14:52:50] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[14:52:50] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[14:52:50] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[14:52:50] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[14:52:50] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[14:52:50] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[14:52:50] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[14:52:50] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[14:52:50] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[14:52:50] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[14:52:50] ============== drm_test_fb_xrgb8888_to_mono ===============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[14:52:50] ==================== drm_test_fb_swab =====================
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ================ [PASSED] drm_test_fb_swab =================
[14:52:50] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[14:52:50] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[14:52:50] [PASSED] single_pixel_source_buffer
[14:52:50] [PASSED] single_pixel_clip_rectangle
[14:52:50] [PASSED] well_known_colors
[14:52:50] [PASSED] destination_pitch
[14:52:50] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[14:52:50] ================= drm_test_fb_clip_offset =================
[14:52:50] [PASSED] pass through
[14:52:50] [PASSED] horizontal offset
[14:52:50] [PASSED] vertical offset
[14:52:50] [PASSED] horizontal and vertical offset
[14:52:50] [PASSED] horizontal offset (custom pitch)
[14:52:50] [PASSED] vertical offset (custom pitch)
[14:52:50] [PASSED] horizontal and vertical offset (custom pitch)
[14:52:50] ============= [PASSED] drm_test_fb_clip_offset =============
[14:52:50] =================== drm_test_fb_memcpy ====================
[14:52:50] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[14:52:50] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[14:52:50] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[14:52:50] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[14:52:50] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[14:52:50] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[14:52:50] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[14:52:50] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[14:52:50] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[14:52:50] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[14:52:50] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[14:52:50] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[14:52:50] =============== [PASSED] drm_test_fb_memcpy ================
[14:52:50] ============= [PASSED] drm_format_helper_test ==============
[14:52:50] ================= drm_format (18 subtests) =================
[14:52:50] [PASSED] drm_test_format_block_width_invalid
[14:52:50] [PASSED] drm_test_format_block_width_one_plane
[14:52:50] [PASSED] drm_test_format_block_width_two_plane
[14:52:50] [PASSED] drm_test_format_block_width_three_plane
[14:52:50] [PASSED] drm_test_format_block_width_tiled
[14:52:50] [PASSED] drm_test_format_block_height_invalid
[14:52:50] [PASSED] drm_test_format_block_height_one_plane
[14:52:50] [PASSED] drm_test_format_block_height_two_plane
[14:52:50] [PASSED] drm_test_format_block_height_three_plane
[14:52:50] [PASSED] drm_test_format_block_height_tiled
[14:52:50] [PASSED] drm_test_format_min_pitch_invalid
[14:52:50] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[14:52:50] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[14:52:50] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[14:52:50] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[14:52:50] [PASSED] drm_test_format_min_pitch_two_plane
[14:52:50] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[14:52:50] [PASSED] drm_test_format_min_pitch_tiled
[14:52:50] =================== [PASSED] drm_format ====================
[14:52:50] ============== drm_framebuffer (10 subtests) ===============
[14:52:50] ========== drm_test_framebuffer_check_src_coords ==========
[14:52:50] [PASSED] Success: source fits into fb
[14:52:50] [PASSED] Fail: overflowing fb with x-axis coordinate
[14:52:50] [PASSED] Fail: overflowing fb with y-axis coordinate
[14:52:50] [PASSED] Fail: overflowing fb with source width
[14:52:50] [PASSED] Fail: overflowing fb with source height
[14:52:50] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[14:52:50] [PASSED] drm_test_framebuffer_cleanup
[14:52:50] =============== drm_test_framebuffer_create ===============
[14:52:50] [PASSED] ABGR8888 normal sizes
[14:52:50] [PASSED] ABGR8888 max sizes
[14:52:50] [PASSED] ABGR8888 pitch greater than min required
[14:52:50] [PASSED] ABGR8888 pitch less than min required
[14:52:50] [PASSED] ABGR8888 Invalid width
[14:52:50] [PASSED] ABGR8888 Invalid buffer handle
[14:52:50] [PASSED] No pixel format
[14:52:50] [PASSED] ABGR8888 Width 0
[14:52:50] [PASSED] ABGR8888 Height 0
[14:52:50] [PASSED] ABGR8888 Out of bound height * pitch combination
[14:52:50] [PASSED] ABGR8888 Large buffer offset
[14:52:50] [PASSED] ABGR8888 Buffer offset for inexistent plane
[14:52:50] [PASSED] ABGR8888 Invalid flag
[14:52:50] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[14:52:50] [PASSED] ABGR8888 Valid buffer modifier
[14:52:50] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[14:52:50] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[14:52:50] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[14:52:50] [PASSED] NV12 Normal sizes
[14:52:50] [PASSED] NV12 Max sizes
[14:52:50] [PASSED] NV12 Invalid pitch
[14:52:50] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[14:52:50] [PASSED] NV12 different modifier per-plane
[14:52:50] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[14:52:50] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[14:52:50] [PASSED] NV12 Modifier for inexistent plane
[14:52:50] [PASSED] NV12 Handle for inexistent plane
[14:52:50] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[14:52:50] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[14:52:50] [PASSED] YVU420 Normal sizes
[14:52:50] [PASSED] YVU420 Max sizes
[14:52:50] [PASSED] YVU420 Invalid pitch
[14:52:50] [PASSED] YVU420 Different pitches
[14:52:50] [PASSED] YVU420 Different buffer offsets/pitches
[14:52:50] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[14:52:50] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[14:52:50] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[14:52:50] [PASSED] YVU420 Valid modifier
[14:52:50] [PASSED] YVU420 Different modifiers per plane
[14:52:50] [PASSED] YVU420 Modifier for inexistent plane
[14:52:50] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[14:52:50] [PASSED] X0L2 Normal sizes
[14:52:50] [PASSED] X0L2 Max sizes
[14:52:50] [PASSED] X0L2 Invalid pitch
[14:52:50] [PASSED] X0L2 Pitch greater than minimum required
[14:52:50] [PASSED] X0L2 Handle for inexistent plane
[14:52:50] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[14:52:50] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[14:52:50] [PASSED] X0L2 Valid modifier
[14:52:50] [PASSED] X0L2 Modifier for inexistent plane
[14:52:50] =========== [PASSED] drm_test_framebuffer_create ===========
[14:52:50] [PASSED] drm_test_framebuffer_free
[14:52:50] [PASSED] drm_test_framebuffer_init
[14:52:50] [PASSED] drm_test_framebuffer_init_bad_format
[14:52:50] [PASSED] drm_test_framebuffer_init_dev_mismatch
[14:52:50] [PASSED] drm_test_framebuffer_lookup
[14:52:50] [PASSED] drm_test_framebuffer_lookup_inexistent
[14:52:50] [PASSED] drm_test_framebuffer_modifiers_not_supported
[14:52:50] ================= [PASSED] drm_framebuffer =================
[14:52:50] ================ drm_gem_shmem (8 subtests) ================
[14:52:50] [PASSED] drm_gem_shmem_test_obj_create
[14:52:50] [PASSED] drm_gem_shmem_test_obj_create_private
[14:52:50] [PASSED] drm_gem_shmem_test_pin_pages
[14:52:50] [PASSED] drm_gem_shmem_test_vmap
[14:52:50] [PASSED] drm_gem_shmem_test_get_sg_table
[14:52:50] [PASSED] drm_gem_shmem_test_get_pages_sgt
[14:52:50] [PASSED] drm_gem_shmem_test_madvise
[14:52:50] [PASSED] drm_gem_shmem_test_purge
[14:52:50] ================== [PASSED] drm_gem_shmem ==================
[14:52:50] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[14:52:50] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[14:52:50] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[14:52:50] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[14:52:50] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[14:52:50] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[14:52:50] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[14:52:50] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[14:52:50] [PASSED] Automatic
[14:52:50] [PASSED] Full
[14:52:50] [PASSED] Limited 16:235
[14:52:50] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[14:52:50] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[14:52:50] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[14:52:50] [PASSED] drm_test_check_disable_connector
[14:52:50] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[14:52:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[14:52:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[14:52:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[14:52:50] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[14:52:50] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[14:52:50] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[14:52:50] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[14:52:50] [PASSED] drm_test_check_output_bpc_dvi
[14:52:50] [PASSED] drm_test_check_output_bpc_format_vic_1
[14:52:50] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[14:52:50] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[14:52:50] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[14:52:50] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[14:52:50] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[14:52:50] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[14:52:50] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[14:52:50] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[14:52:50] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[14:52:50] [PASSED] drm_test_check_broadcast_rgb_value
[14:52:50] [PASSED] drm_test_check_bpc_8_value
[14:52:50] [PASSED] drm_test_check_bpc_10_value
[14:52:50] [PASSED] drm_test_check_bpc_12_value
[14:52:50] [PASSED] drm_test_check_format_value
[14:52:50] [PASSED] drm_test_check_tmds_char_value
[14:52:50] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[14:52:50] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[14:52:50] [PASSED] drm_test_check_mode_valid
[14:52:50] [PASSED] drm_test_check_mode_valid_reject
[14:52:50] [PASSED] drm_test_check_mode_valid_reject_rate
[14:52:50] [PASSED] drm_test_check_mode_valid_reject_max_clock
[14:52:50] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[14:52:50] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[14:52:50] [PASSED] drm_test_check_infoframes
[14:52:50] [PASSED] drm_test_check_reject_avi_infoframe
[14:52:50] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[14:52:50] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[14:52:50] [PASSED] drm_test_check_reject_audio_infoframe
[14:52:50] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[14:52:50] ================= drm_managed (2 subtests) =================
[14:52:50] [PASSED] drm_test_managed_release_action
[14:52:50] [PASSED] drm_test_managed_run_action
[14:52:50] =================== [PASSED] drm_managed ===================
[14:52:50] =================== drm_mm (6 subtests) ====================
[14:52:50] [PASSED] drm_test_mm_init
[14:52:50] [PASSED] drm_test_mm_debug
[14:52:50] [PASSED] drm_test_mm_align32
[14:52:50] [PASSED] drm_test_mm_align64
[14:52:50] [PASSED] drm_test_mm_lowest
[14:52:50] [PASSED] drm_test_mm_highest
[14:52:50] ===================== [PASSED] drm_mm ======================
[14:52:50] ============= drm_modes_analog_tv (5 subtests) =============
[14:52:50] [PASSED] drm_test_modes_analog_tv_mono_576i
[14:52:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[14:52:50] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[14:52:50] [PASSED] drm_test_modes_analog_tv_pal_576i
[14:52:50] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[14:52:50] =============== [PASSED] drm_modes_analog_tv ===============
[14:52:50] ============== drm_plane_helper (2 subtests) ===============
[14:52:50] =============== drm_test_check_plane_state ================
[14:52:50] [PASSED] clipping_simple
[14:52:50] [PASSED] clipping_rotate_reflect
[14:52:50] [PASSED] positioning_simple
[14:52:50] [PASSED] upscaling
[14:52:50] [PASSED] downscaling
[14:52:50] [PASSED] rounding1
[14:52:50] [PASSED] rounding2
[14:52:50] [PASSED] rounding3
[14:52:50] [PASSED] rounding4
[14:52:50] =========== [PASSED] drm_test_check_plane_state ============
[14:52:50] =========== drm_test_check_invalid_plane_state ============
[14:52:50] [PASSED] positioning_invalid
[14:52:50] [PASSED] upscaling_invalid
[14:52:50] [PASSED] downscaling_invalid
[14:52:50] ======= [PASSED] drm_test_check_invalid_plane_state ========
[14:52:50] ================ [PASSED] drm_plane_helper =================
[14:52:50] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[14:52:50] ====== drm_test_connector_helper_tv_get_modes_check =======
[14:52:50] [PASSED] None
[14:52:50] [PASSED] PAL
[14:52:50] [PASSED] NTSC
[14:52:50] [PASSED] Both, NTSC Default
[14:52:50] [PASSED] Both, PAL Default
[14:52:50] [PASSED] Both, NTSC Default, with PAL on command-line
[14:52:50] [PASSED] Both, PAL Default, with NTSC on command-line
[14:52:50] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[14:52:50] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[14:52:50] ================== drm_rect (9 subtests) ===================
[14:52:50] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[14:52:50] [PASSED] drm_test_rect_clip_scaled_not_clipped
[14:52:50] [PASSED] drm_test_rect_clip_scaled_clipped
[14:52:50] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[14:52:50] ================= drm_test_rect_intersect =================
[14:52:50] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[14:52:50] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[14:52:50] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[14:52:50] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[14:52:50] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[14:52:50] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[14:52:50] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[14:52:50] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[14:52:50] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[14:52:50] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[14:52:50] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[14:52:50] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[14:52:50] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[14:52:50] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[14:52:50] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[14:52:50] ============= [PASSED] drm_test_rect_intersect =============
[14:52:50] ================ drm_test_rect_calc_hscale ================
[14:52:50] [PASSED] normal use
[14:52:50] [PASSED] out of max range
[14:52:50] [PASSED] out of min range
[14:52:50] [PASSED] zero dst
[14:52:50] [PASSED] negative src
[14:52:50] [PASSED] negative dst
[14:52:50] ============ [PASSED] drm_test_rect_calc_hscale ============
[14:52:50] ================ drm_test_rect_calc_vscale ================
[14:52:50] [PASSED] normal use
[14:52:50] [PASSED] out of max range
[14:52:50] [PASSED] out of min range
[14:52:50] [PASSED] zero dst
[14:52:50] [PASSED] negative src
[14:52:50] [PASSED] negative dst
[14:52:50] ============ [PASSED] drm_test_rect_calc_vscale ============
[14:52:50] ================== drm_test_rect_rotate ===================
[14:52:50] [PASSED] reflect-x
[14:52:50] [PASSED] reflect-y
[14:52:50] [PASSED] rotate-0
[14:52:50] [PASSED] rotate-90
[14:52:50] [PASSED] rotate-180
[14:52:50] [PASSED] rotate-270
[14:52:50] ============== [PASSED] drm_test_rect_rotate ===============
[14:52:50] ================ drm_test_rect_rotate_inv =================
[14:52:50] [PASSED] reflect-x
[14:52:50] [PASSED] reflect-y
[14:52:50] [PASSED] rotate-0
[14:52:50] [PASSED] rotate-90
[14:52:50] [PASSED] rotate-180
[14:52:50] [PASSED] rotate-270
[14:52:50] ============ [PASSED] drm_test_rect_rotate_inv =============
[14:52:50] ==================== [PASSED] drm_rect =====================
[14:52:50] ============ drm_sysfb_modeset_test (1 subtest) ============
[14:52:50] ============ drm_test_sysfb_build_fourcc_list =============
[14:52:50] [PASSED] no native formats
[14:52:50] [PASSED] XRGB8888 as native format
[14:52:50] [PASSED] remove duplicates
[14:52:50] [PASSED] convert alpha formats
[14:52:50] [PASSED] random formats
[14:52:50] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[14:52:50] ============= [PASSED] drm_sysfb_modeset_test ==============
[14:52:50] ================== drm_fixp (2 subtests) ===================
[14:52:50] [PASSED] drm_test_int2fixp
[14:52:50] [PASSED] drm_test_sm2fixp
[14:52:50] ==================== [PASSED] drm_fixp =====================
[14:52:50] ============================================================
[14:52:50] Testing complete. Ran 630 tests: passed: 630
[14:52:50] Elapsed time: 28.034s total, 1.692s configuring, 25.925s building, 0.405s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[14:52:50] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:52:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:53:01] Starting KUnit Kernel (1/1)...
[14:53:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:53:01] ================= ttm_device (5 subtests) ==================
[14:53:01] [PASSED] ttm_device_init_basic
[14:53:01] [PASSED] ttm_device_init_multiple
[14:53:01] [PASSED] ttm_device_fini_basic
[14:53:01] [PASSED] ttm_device_init_no_vma_man
[14:53:01] ================== ttm_device_init_pools ==================
[14:53:01] [PASSED] No DMA allocations, no DMA32 required
[14:53:01] [PASSED] DMA allocations, DMA32 required
[14:53:01] [PASSED] No DMA allocations, DMA32 required
[14:53:01] [PASSED] DMA allocations, no DMA32 required
[14:53:01] ============== [PASSED] ttm_device_init_pools ==============
[14:53:01] =================== [PASSED] ttm_device ====================
[14:53:01] ================== ttm_pool (8 subtests) ===================
[14:53:01] ================== ttm_pool_alloc_basic ===================
[14:53:01] [PASSED] One page
[14:53:01] [PASSED] More than one page
[14:53:01] [PASSED] Above the allocation limit
[14:53:01] [PASSED] One page, with coherent DMA mappings enabled
[14:53:01] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:53:01] ============== [PASSED] ttm_pool_alloc_basic ===============
[14:53:01] ============== ttm_pool_alloc_basic_dma_addr ==============
[14:53:01] [PASSED] One page
[14:53:01] [PASSED] More than one page
[14:53:01] [PASSED] Above the allocation limit
[14:53:01] [PASSED] One page, with coherent DMA mappings enabled
[14:53:01] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:53:01] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[14:53:01] [PASSED] ttm_pool_alloc_order_caching_match
[14:53:01] [PASSED] ttm_pool_alloc_caching_mismatch
[14:53:01] [PASSED] ttm_pool_alloc_order_mismatch
[14:53:01] [PASSED] ttm_pool_free_dma_alloc
[14:53:01] [PASSED] ttm_pool_free_no_dma_alloc
[14:53:01] [PASSED] ttm_pool_fini_basic
[14:53:01] ==================== [PASSED] ttm_pool =====================
[14:53:01] ================ ttm_resource (8 subtests) =================
[14:53:01] ================= ttm_resource_init_basic =================
[14:53:01] [PASSED] Init resource in TTM_PL_SYSTEM
[14:53:01] [PASSED] Init resource in TTM_PL_VRAM
[14:53:01] [PASSED] Init resource in a private placement
[14:53:01] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[14:53:01] ============= [PASSED] ttm_resource_init_basic =============
[14:53:01] [PASSED] ttm_resource_init_pinned
[14:53:01] [PASSED] ttm_resource_fini_basic
[14:53:01] [PASSED] ttm_resource_manager_init_basic
[14:53:01] [PASSED] ttm_resource_manager_usage_basic
[14:53:01] [PASSED] ttm_resource_manager_set_used_basic
[14:53:01] [PASSED] ttm_sys_man_alloc_basic
[14:53:01] [PASSED] ttm_sys_man_free_basic
[14:53:01] ================== [PASSED] ttm_resource ===================
[14:53:01] =================== ttm_tt (15 subtests) ===================
[14:53:01] ==================== ttm_tt_init_basic ====================
[14:53:01] [PASSED] Page-aligned size
[14:53:01] [PASSED] Extra pages requested
[14:53:01] ================ [PASSED] ttm_tt_init_basic ================
[14:53:01] [PASSED] ttm_tt_init_misaligned
[14:53:01] [PASSED] ttm_tt_fini_basic
[14:53:01] [PASSED] ttm_tt_fini_sg
[14:53:01] [PASSED] ttm_tt_fini_shmem
[14:53:01] [PASSED] ttm_tt_create_basic
[14:53:01] [PASSED] ttm_tt_create_invalid_bo_type
[14:53:01] [PASSED] ttm_tt_create_ttm_exists
[14:53:01] [PASSED] ttm_tt_create_failed
[14:53:01] [PASSED] ttm_tt_destroy_basic
[14:53:01] [PASSED] ttm_tt_populate_null_ttm
[14:53:01] [PASSED] ttm_tt_populate_populated_ttm
[14:53:01] [PASSED] ttm_tt_unpopulate_basic
[14:53:01] [PASSED] ttm_tt_unpopulate_empty_ttm
[14:53:01] [PASSED] ttm_tt_swapin_basic
[14:53:01] ===================== [PASSED] ttm_tt ======================
[14:53:01] =================== ttm_bo (14 subtests) ===================
[14:53:01] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[14:53:01] [PASSED] Cannot be interrupted and sleeps
[14:53:01] [PASSED] Cannot be interrupted, locks straight away
[14:53:01] [PASSED] Can be interrupted, sleeps
[14:53:01] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[14:53:01] [PASSED] ttm_bo_reserve_locked_no_sleep
[14:53:01] [PASSED] ttm_bo_reserve_no_wait_ticket
[14:53:01] [PASSED] ttm_bo_reserve_double_resv
[14:53:01] [PASSED] ttm_bo_reserve_interrupted
[14:53:01] [PASSED] ttm_bo_reserve_deadlock
[14:53:01] [PASSED] ttm_bo_unreserve_basic
[14:53:01] [PASSED] ttm_bo_unreserve_pinned
[14:53:01] [PASSED] ttm_bo_unreserve_bulk
[14:53:01] [PASSED] ttm_bo_fini_basic
[14:53:01] [PASSED] ttm_bo_fini_shared_resv
[14:53:01] [PASSED] ttm_bo_pin_basic
[14:53:01] [PASSED] ttm_bo_pin_unpin_resource
[14:53:01] [PASSED] ttm_bo_multiple_pin_one_unpin
[14:53:01] ===================== [PASSED] ttm_bo ======================
[14:53:01] ============== ttm_bo_validate (21 subtests) ===============
[14:53:01] ============== ttm_bo_init_reserved_sys_man ===============
[14:53:01] [PASSED] Buffer object for userspace
[14:53:01] [PASSED] Kernel buffer object
[14:53:01] [PASSED] Shared buffer object
[14:53:01] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[14:53:01] ============== ttm_bo_init_reserved_mock_man ==============
[14:53:01] [PASSED] Buffer object for userspace
[14:53:01] [PASSED] Kernel buffer object
[14:53:01] [PASSED] Shared buffer object
[14:53:01] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[14:53:01] [PASSED] ttm_bo_init_reserved_resv
[14:53:01] ================== ttm_bo_validate_basic ==================
[14:53:01] [PASSED] Buffer object for userspace
[14:53:01] [PASSED] Kernel buffer object
[14:53:01] [PASSED] Shared buffer object
[14:53:01] ============== [PASSED] ttm_bo_validate_basic ==============
[14:53:01] [PASSED] ttm_bo_validate_invalid_placement
[14:53:01] ============= ttm_bo_validate_same_placement ==============
[14:53:01] [PASSED] System manager
[14:53:01] [PASSED] VRAM manager
[14:53:01] ========= [PASSED] ttm_bo_validate_same_placement ==========
[14:53:01] [PASSED] ttm_bo_validate_failed_alloc
[14:53:01] [PASSED] ttm_bo_validate_pinned
[14:53:01] [PASSED] ttm_bo_validate_busy_placement
[14:53:01] ================ ttm_bo_validate_multihop =================
[14:53:01] [PASSED] Buffer object for userspace
[14:53:01] [PASSED] Kernel buffer object
[14:53:01] [PASSED] Shared buffer object
[14:53:01] ============ [PASSED] ttm_bo_validate_multihop =============
[14:53:01] ========== ttm_bo_validate_no_placement_signaled ==========
[14:53:01] [PASSED] Buffer object in system domain, no page vector
[14:53:01] [PASSED] Buffer object in system domain with an existing page vector
[14:53:01] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[14:53:01] ======== ttm_bo_validate_no_placement_not_signaled ========
[14:53:01] [PASSED] Buffer object for userspace
[14:53:01] [PASSED] Kernel buffer object
[14:53:01] [PASSED] Shared buffer object
[14:53:01] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[14:53:01] [PASSED] ttm_bo_validate_move_fence_signaled
[14:53:01] ========= ttm_bo_validate_move_fence_not_signaled =========
[14:53:01] [PASSED] Waits for GPU
[14:53:01] [PASSED] Tries to lock straight away
[14:53:01] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[14:53:01] [PASSED] ttm_bo_validate_happy_evict
[14:53:01] [PASSED] ttm_bo_validate_all_pinned_evict
[14:53:01] [PASSED] ttm_bo_validate_allowed_only_evict
[14:53:01] [PASSED] ttm_bo_validate_deleted_evict
[14:53:01] [PASSED] ttm_bo_validate_busy_domain_evict
[14:53:01] [PASSED] ttm_bo_validate_evict_gutting
[14:53:01] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[14:53:01] ================= [PASSED] ttm_bo_validate =================
[14:53:01] ============================================================
[14:53:01] Testing complete. Ran 101 tests: passed: 101
[14:53:01] Elapsed time: 11.545s total, 1.631s configuring, 9.699s building, 0.187s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ CI.checksparse: warning for CMTG enablement (rev2)
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (10 preceding siblings ...)
2026-02-03 14:53 ` ✓ CI.KUnit: success for CMTG enablement (rev2) Patchwork
@ 2026-02-03 15:08 ` Patchwork
2026-02-03 15:28 ` ✗ Xe.CI.BAT: failure " Patchwork
` (6 subsequent siblings)
18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2026-02-03 15:08 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-xe
== Series Details ==
Series: CMTG enablement (rev2)
URL : https://patchwork.freedesktop.org/series/157663/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 9f5242e63f0bab74d47ae6792e0c25a324184a6b
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/dvo_ch7017.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_ch7xxx.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_ivch.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_ns2501.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_sil164.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_tfp410.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/hsw_ips.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/icl_dsi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_dsi.h):
+drivers/gpu/drm/i915/display/intel_acpi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_atomic.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_audio.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_backlight.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_bios.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_bw.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_casf.c:153:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_casf.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cmtg.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_color.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_colorop.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_color_pipeline.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_combo_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_connector.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_crtc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_crtc_state_dump.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cursor.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cx0_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dbuf_bw.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_debugfs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_device.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_driver.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_display_power.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_map.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_well.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_reset.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_rps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dmc.c:131:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:134:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:137:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:140:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:143:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:146:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:149:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:153:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:154:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:157:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:160:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:163:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:166:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:170:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:174:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:178:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:182:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:186:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_aux.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpio_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_link_training.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll_mgr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_mst.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt_common.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_test.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_drrs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_dsi.h):
+drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi_vbt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_encoder.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fb_bo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fbc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_fb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fb_pin.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fdi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fifo_underrun.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_flipq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_frontbuffer.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_global_state.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_gmbus.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hotplug_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_initial_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_link_bw.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_load_detect.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lspcon.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lt_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lvds.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_lock.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_verify.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_opregion.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_overlay.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_panel.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pch_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_refclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pfit.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pipe_crc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_pmdemand.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_quirks.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sdvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sprite.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sprite_uapi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tv.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vblank.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vdsc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vga.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vrr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_prefill.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_scaler.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/skl_universal_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_watermark.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_clock.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_dsi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_dsi_pll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_sideband.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/gem/i915_gem_pages.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/i915_initial_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/i915_panic.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ Xe.CI.BAT: failure for CMTG enablement (rev2)
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (11 preceding siblings ...)
2026-02-03 15:08 ` ✗ CI.checksparse: warning " Patchwork
@ 2026-02-03 15:28 ` Patchwork
2026-02-04 5:45 ` ✗ Xe.CI.FULL: " Patchwork
` (5 subsequent siblings)
18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2026-02-03 15:28 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 352 bytes --]
== Series Details ==
Series: CMTG enablement (rev2)
URL : https://patchwork.freedesktop.org/series/157663/
State : failure
== Summary ==
ERROR: The runconfig 'xe-4490-9f5242e63f0bab74d47ae6792e0c25a324184a6b_BAT' does not exist in the database
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v2/index.html
[-- Attachment #2: Type: text/html, Size: 917 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ Xe.CI.FULL: failure for CMTG enablement (rev2)
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (12 preceding siblings ...)
2026-02-03 15:28 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2026-02-04 5:45 ` Patchwork
2026-02-04 17:52 ` ✓ CI.KUnit: success for CMTG enablement (rev3) Patchwork
` (4 subsequent siblings)
18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2026-02-04 5:45 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 353 bytes --]
== Series Details ==
Series: CMTG enablement (rev2)
URL : https://patchwork.freedesktop.org/series/157663/
State : failure
== Summary ==
ERROR: The runconfig 'xe-4490-9f5242e63f0bab74d47ae6792e0c25a324184a6b_FULL' does not exist in the database
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v2/index.html
[-- Attachment #2: Type: text/html, Size: 918 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✓ CI.KUnit: success for CMTG enablement (rev3)
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (13 preceding siblings ...)
2026-02-04 5:45 ` ✗ Xe.CI.FULL: " Patchwork
@ 2026-02-04 17:52 ` Patchwork
2026-02-04 18:08 ` ✗ CI.checksparse: warning " Patchwork
` (3 subsequent siblings)
18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2026-02-04 17:52 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-xe
== Series Details ==
Series: CMTG enablement (rev3)
URL : https://patchwork.freedesktop.org/series/157663/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:51:21] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:51:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:51:57] Starting KUnit Kernel (1/1)...
[17:51:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:51:58] ================== guc_buf (11 subtests) ===================
[17:51:58] [PASSED] test_smallest
[17:51:58] [PASSED] test_largest
[17:51:58] [PASSED] test_granular
[17:51:58] [PASSED] test_unique
[17:51:58] [PASSED] test_overlap
[17:51:58] [PASSED] test_reusable
[17:51:58] [PASSED] test_too_big
[17:51:58] [PASSED] test_flush
[17:51:58] [PASSED] test_lookup
[17:51:58] [PASSED] test_data
[17:51:58] [PASSED] test_class
[17:51:58] ===================== [PASSED] guc_buf =====================
[17:51:58] =================== guc_dbm (7 subtests) ===================
[17:51:58] [PASSED] test_empty
[17:51:58] [PASSED] test_default
[17:51:58] ======================== test_size ========================
[17:51:58] [PASSED] 4
[17:51:58] [PASSED] 8
[17:51:58] [PASSED] 32
[17:51:58] [PASSED] 256
[17:51:58] ==================== [PASSED] test_size ====================
[17:51:58] ======================= test_reuse ========================
[17:51:58] [PASSED] 4
[17:51:58] [PASSED] 8
[17:51:58] [PASSED] 32
[17:51:58] [PASSED] 256
[17:51:58] =================== [PASSED] test_reuse ====================
[17:51:58] =================== test_range_overlap ====================
[17:51:58] [PASSED] 4
[17:51:58] [PASSED] 8
[17:51:58] [PASSED] 32
[17:51:58] [PASSED] 256
[17:51:58] =============== [PASSED] test_range_overlap ================
[17:51:58] =================== test_range_compact ====================
[17:51:58] [PASSED] 4
[17:51:58] [PASSED] 8
[17:51:58] [PASSED] 32
[17:51:58] [PASSED] 256
[17:51:58] =============== [PASSED] test_range_compact ================
[17:51:58] ==================== test_range_spare =====================
[17:51:58] [PASSED] 4
[17:51:58] [PASSED] 8
[17:51:58] [PASSED] 32
[17:51:58] [PASSED] 256
[17:51:58] ================ [PASSED] test_range_spare =================
[17:51:58] ===================== [PASSED] guc_dbm =====================
[17:51:58] =================== guc_idm (6 subtests) ===================
[17:51:58] [PASSED] bad_init
[17:51:58] [PASSED] no_init
[17:51:58] [PASSED] init_fini
[17:51:58] [PASSED] check_used
[17:51:58] [PASSED] check_quota
[17:51:58] [PASSED] check_all
[17:51:58] ===================== [PASSED] guc_idm =====================
[17:51:58] ================== no_relay (3 subtests) ===================
[17:51:58] [PASSED] xe_drops_guc2pf_if_not_ready
[17:51:58] [PASSED] xe_drops_guc2vf_if_not_ready
[17:51:58] [PASSED] xe_rejects_send_if_not_ready
[17:51:58] ==================== [PASSED] no_relay =====================
[17:51:58] ================== pf_relay (14 subtests) ==================
[17:51:58] [PASSED] pf_rejects_guc2pf_too_short
[17:51:58] [PASSED] pf_rejects_guc2pf_too_long
[17:51:58] [PASSED] pf_rejects_guc2pf_no_payload
[17:51:58] [PASSED] pf_fails_no_payload
[17:51:58] [PASSED] pf_fails_bad_origin
[17:51:58] [PASSED] pf_fails_bad_type
[17:51:58] [PASSED] pf_txn_reports_error
[17:51:58] [PASSED] pf_txn_sends_pf2guc
[17:51:58] [PASSED] pf_sends_pf2guc
[17:51:58] [SKIPPED] pf_loopback_nop
[17:51:58] [SKIPPED] pf_loopback_echo
[17:51:58] [SKIPPED] pf_loopback_fail
[17:51:58] [SKIPPED] pf_loopback_busy
[17:51:58] [SKIPPED] pf_loopback_retry
[17:51:58] ==================== [PASSED] pf_relay =====================
[17:51:58] ================== vf_relay (3 subtests) ===================
[17:51:58] [PASSED] vf_rejects_guc2vf_too_short
[17:51:58] [PASSED] vf_rejects_guc2vf_too_long
[17:51:58] [PASSED] vf_rejects_guc2vf_no_payload
[17:51:58] ==================== [PASSED] vf_relay =====================
[17:51:58] ================ pf_gt_config (6 subtests) =================
[17:51:58] [PASSED] fair_contexts_1vf
[17:51:58] [PASSED] fair_doorbells_1vf
[17:51:58] [PASSED] fair_ggtt_1vf
[17:51:58] ====================== fair_contexts ======================
[17:51:58] [PASSED] 1 VF
[17:51:58] [PASSED] 2 VFs
[17:51:58] [PASSED] 3 VFs
[17:51:58] [PASSED] 4 VFs
[17:51:58] [PASSED] 5 VFs
[17:51:58] [PASSED] 6 VFs
[17:51:58] [PASSED] 7 VFs
[17:51:58] [PASSED] 8 VFs
[17:51:58] [PASSED] 9 VFs
[17:51:58] [PASSED] 10 VFs
[17:51:58] [PASSED] 11 VFs
[17:51:58] [PASSED] 12 VFs
[17:51:58] [PASSED] 13 VFs
[17:51:58] [PASSED] 14 VFs
[17:51:58] [PASSED] 15 VFs
[17:51:58] [PASSED] 16 VFs
[17:51:58] [PASSED] 17 VFs
[17:51:58] [PASSED] 18 VFs
[17:51:58] [PASSED] 19 VFs
[17:51:58] [PASSED] 20 VFs
[17:51:58] [PASSED] 21 VFs
[17:51:58] [PASSED] 22 VFs
[17:51:58] [PASSED] 23 VFs
[17:51:58] [PASSED] 24 VFs
[17:51:58] [PASSED] 25 VFs
[17:51:58] [PASSED] 26 VFs
[17:51:58] [PASSED] 27 VFs
[17:51:58] [PASSED] 28 VFs
[17:51:58] [PASSED] 29 VFs
[17:51:58] [PASSED] 30 VFs
[17:51:58] [PASSED] 31 VFs
[17:51:58] [PASSED] 32 VFs
[17:51:58] [PASSED] 33 VFs
[17:51:58] [PASSED] 34 VFs
[17:51:58] [PASSED] 35 VFs
[17:51:58] [PASSED] 36 VFs
[17:51:58] [PASSED] 37 VFs
[17:51:58] [PASSED] 38 VFs
[17:51:58] [PASSED] 39 VFs
[17:51:58] [PASSED] 40 VFs
[17:51:58] [PASSED] 41 VFs
[17:51:58] [PASSED] 42 VFs
[17:51:58] [PASSED] 43 VFs
[17:51:58] [PASSED] 44 VFs
[17:51:58] [PASSED] 45 VFs
[17:51:58] [PASSED] 46 VFs
[17:51:58] [PASSED] 47 VFs
[17:51:58] [PASSED] 48 VFs
[17:51:58] [PASSED] 49 VFs
[17:51:58] [PASSED] 50 VFs
[17:51:58] [PASSED] 51 VFs
[17:51:58] [PASSED] 52 VFs
[17:51:58] [PASSED] 53 VFs
[17:51:58] [PASSED] 54 VFs
[17:51:58] [PASSED] 55 VFs
[17:51:58] [PASSED] 56 VFs
[17:51:58] [PASSED] 57 VFs
[17:51:58] [PASSED] 58 VFs
[17:51:58] [PASSED] 59 VFs
[17:51:58] [PASSED] 60 VFs
[17:51:58] [PASSED] 61 VFs
[17:51:58] [PASSED] 62 VFs
[17:51:58] [PASSED] 63 VFs
[17:51:58] ================== [PASSED] fair_contexts ==================
[17:51:58] ===================== fair_doorbells ======================
[17:51:58] [PASSED] 1 VF
[17:51:58] [PASSED] 2 VFs
[17:51:58] [PASSED] 3 VFs
[17:51:58] [PASSED] 4 VFs
[17:51:58] [PASSED] 5 VFs
[17:51:58] [PASSED] 6 VFs
[17:51:58] [PASSED] 7 VFs
[17:51:58] [PASSED] 8 VFs
[17:51:58] [PASSED] 9 VFs
[17:51:58] [PASSED] 10 VFs
[17:51:58] [PASSED] 11 VFs
[17:51:58] [PASSED] 12 VFs
[17:51:58] [PASSED] 13 VFs
[17:51:58] [PASSED] 14 VFs
[17:51:58] [PASSED] 15 VFs
[17:51:58] [PASSED] 16 VFs
[17:51:58] [PASSED] 17 VFs
[17:51:58] [PASSED] 18 VFs
[17:51:58] [PASSED] 19 VFs
[17:51:58] [PASSED] 20 VFs
[17:51:58] [PASSED] 21 VFs
[17:51:58] [PASSED] 22 VFs
[17:51:58] [PASSED] 23 VFs
[17:51:58] [PASSED] 24 VFs
[17:51:58] [PASSED] 25 VFs
[17:51:58] [PASSED] 26 VFs
[17:51:58] [PASSED] 27 VFs
[17:51:58] [PASSED] 28 VFs
[17:51:58] [PASSED] 29 VFs
[17:51:58] [PASSED] 30 VFs
[17:51:58] [PASSED] 31 VFs
[17:51:58] [PASSED] 32 VFs
[17:51:58] [PASSED] 33 VFs
[17:51:58] [PASSED] 34 VFs
[17:51:58] [PASSED] 35 VFs
[17:51:58] [PASSED] 36 VFs
[17:51:58] [PASSED] 37 VFs
[17:51:58] [PASSED] 38 VFs
[17:51:58] [PASSED] 39 VFs
[17:51:58] [PASSED] 40 VFs
[17:51:58] [PASSED] 41 VFs
[17:51:58] [PASSED] 42 VFs
[17:51:58] [PASSED] 43 VFs
[17:51:58] [PASSED] 44 VFs
[17:51:58] [PASSED] 45 VFs
[17:51:58] [PASSED] 46 VFs
[17:51:58] [PASSED] 47 VFs
[17:51:58] [PASSED] 48 VFs
[17:51:58] [PASSED] 49 VFs
[17:51:58] [PASSED] 50 VFs
[17:51:58] [PASSED] 51 VFs
[17:51:58] [PASSED] 52 VFs
[17:51:58] [PASSED] 53 VFs
[17:51:58] [PASSED] 54 VFs
[17:51:58] [PASSED] 55 VFs
[17:51:58] [PASSED] 56 VFs
[17:51:58] [PASSED] 57 VFs
[17:51:58] [PASSED] 58 VFs
[17:51:58] [PASSED] 59 VFs
[17:51:58] [PASSED] 60 VFs
[17:51:58] [PASSED] 61 VFs
[17:51:58] [PASSED] 62 VFs
[17:51:58] [PASSED] 63 VFs
[17:51:58] ================= [PASSED] fair_doorbells ==================
[17:51:58] ======================== fair_ggtt ========================
[17:51:58] [PASSED] 1 VF
[17:51:58] [PASSED] 2 VFs
[17:51:58] [PASSED] 3 VFs
[17:51:58] [PASSED] 4 VFs
[17:51:58] [PASSED] 5 VFs
[17:51:58] [PASSED] 6 VFs
[17:51:58] [PASSED] 7 VFs
[17:51:58] [PASSED] 8 VFs
[17:51:58] [PASSED] 9 VFs
[17:51:58] [PASSED] 10 VFs
[17:51:58] [PASSED] 11 VFs
[17:51:58] [PASSED] 12 VFs
[17:51:58] [PASSED] 13 VFs
[17:51:58] [PASSED] 14 VFs
[17:51:58] [PASSED] 15 VFs
[17:51:58] [PASSED] 16 VFs
[17:51:58] [PASSED] 17 VFs
[17:51:58] [PASSED] 18 VFs
[17:51:58] [PASSED] 19 VFs
[17:51:58] [PASSED] 20 VFs
[17:51:58] [PASSED] 21 VFs
[17:51:58] [PASSED] 22 VFs
[17:51:58] [PASSED] 23 VFs
[17:51:58] [PASSED] 24 VFs
[17:51:58] [PASSED] 25 VFs
[17:51:58] [PASSED] 26 VFs
[17:51:58] [PASSED] 27 VFs
[17:51:58] [PASSED] 28 VFs
[17:51:58] [PASSED] 29 VFs
[17:51:58] [PASSED] 30 VFs
[17:51:58] [PASSED] 31 VFs
[17:51:58] [PASSED] 32 VFs
[17:51:58] [PASSED] 33 VFs
[17:51:58] [PASSED] 34 VFs
[17:51:58] [PASSED] 35 VFs
[17:51:58] [PASSED] 36 VFs
[17:51:58] [PASSED] 37 VFs
[17:51:58] [PASSED] 38 VFs
[17:51:58] [PASSED] 39 VFs
[17:51:58] [PASSED] 40 VFs
[17:51:58] [PASSED] 41 VFs
[17:51:58] [PASSED] 42 VFs
[17:51:58] [PASSED] 43 VFs
[17:51:58] [PASSED] 44 VFs
[17:51:58] [PASSED] 45 VFs
[17:51:58] [PASSED] 46 VFs
[17:51:58] [PASSED] 47 VFs
[17:51:58] [PASSED] 48 VFs
[17:51:58] [PASSED] 49 VFs
[17:51:58] [PASSED] 50 VFs
[17:51:58] [PASSED] 51 VFs
[17:51:58] [PASSED] 52 VFs
[17:51:58] [PASSED] 53 VFs
[17:51:58] [PASSED] 54 VFs
[17:51:58] [PASSED] 55 VFs
[17:51:58] [PASSED] 56 VFs
[17:51:58] [PASSED] 57 VFs
[17:51:58] [PASSED] 58 VFs
[17:51:58] [PASSED] 59 VFs
[17:51:58] [PASSED] 60 VFs
[17:51:58] [PASSED] 61 VFs
[17:51:58] [PASSED] 62 VFs
[17:51:58] [PASSED] 63 VFs
[17:51:58] ==================== [PASSED] fair_ggtt ====================
[17:51:58] ================== [PASSED] pf_gt_config ===================
[17:51:58] ===================== lmtt (1 subtest) =====================
[17:51:58] ======================== test_ops =========================
[17:51:58] [PASSED] 2-level
[17:51:58] [PASSED] multi-level
[17:51:58] ==================== [PASSED] test_ops =====================
[17:51:58] ====================== [PASSED] lmtt =======================
[17:51:58] ================= pf_service (11 subtests) =================
[17:51:58] [PASSED] pf_negotiate_any
[17:51:58] [PASSED] pf_negotiate_base_match
[17:51:58] [PASSED] pf_negotiate_base_newer
[17:51:58] [PASSED] pf_negotiate_base_next
[17:51:58] [SKIPPED] pf_negotiate_base_older
[17:51:58] [PASSED] pf_negotiate_base_prev
[17:51:58] [PASSED] pf_negotiate_latest_match
[17:51:58] [PASSED] pf_negotiate_latest_newer
[17:51:58] [PASSED] pf_negotiate_latest_next
[17:51:58] [SKIPPED] pf_negotiate_latest_older
[17:51:58] [SKIPPED] pf_negotiate_latest_prev
[17:51:58] =================== [PASSED] pf_service ====================
[17:51:58] ================= xe_guc_g2g (2 subtests) ==================
[17:51:58] ============== xe_live_guc_g2g_kunit_default ==============
[17:51:58] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:51:58] ============== xe_live_guc_g2g_kunit_allmem ===============
[17:51:58] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:51:58] =================== [SKIPPED] xe_guc_g2g ===================
[17:51:58] =================== xe_mocs (2 subtests) ===================
[17:51:58] ================ xe_live_mocs_kernel_kunit ================
[17:51:58] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:51:58] ================ xe_live_mocs_reset_kunit =================
[17:51:58] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:51:58] ==================== [SKIPPED] xe_mocs =====================
[17:51:58] ================= xe_migrate (2 subtests) ==================
[17:51:58] ================= xe_migrate_sanity_kunit =================
[17:51:58] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:51:58] ================== xe_validate_ccs_kunit ==================
[17:51:58] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:51:58] =================== [SKIPPED] xe_migrate ===================
[17:51:58] ================== xe_dma_buf (1 subtest) ==================
[17:51:58] ==================== xe_dma_buf_kunit =====================
[17:51:58] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:51:58] =================== [SKIPPED] xe_dma_buf ===================
[17:51:58] ================= xe_bo_shrink (1 subtest) =================
[17:51:58] =================== xe_bo_shrink_kunit ====================
[17:51:58] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:51:58] ================== [SKIPPED] xe_bo_shrink ==================
[17:51:58] ==================== xe_bo (2 subtests) ====================
[17:51:58] ================== xe_ccs_migrate_kunit ===================
[17:51:58] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:51:58] ==================== xe_bo_evict_kunit ====================
[17:51:58] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:51:58] ===================== [SKIPPED] xe_bo ======================
[17:51:58] ==================== args (13 subtests) ====================
[17:51:58] [PASSED] count_args_test
[17:51:58] [PASSED] call_args_example
[17:51:58] [PASSED] call_args_test
[17:51:58] [PASSED] drop_first_arg_example
[17:51:58] [PASSED] drop_first_arg_test
[17:51:58] [PASSED] first_arg_example
[17:51:58] [PASSED] first_arg_test
[17:51:58] [PASSED] last_arg_example
[17:51:58] [PASSED] last_arg_test
[17:51:58] [PASSED] pick_arg_example
[17:51:58] [PASSED] if_args_example
[17:51:58] [PASSED] if_args_test
[17:51:58] [PASSED] sep_comma_example
[17:51:58] ====================== [PASSED] args =======================
[17:51:58] =================== xe_pci (3 subtests) ====================
[17:51:58] ==================== check_graphics_ip ====================
[17:51:58] [PASSED] 12.00 Xe_LP
[17:51:58] [PASSED] 12.10 Xe_LP+
[17:51:58] [PASSED] 12.55 Xe_HPG
[17:51:58] [PASSED] 12.60 Xe_HPC
[17:51:58] [PASSED] 12.70 Xe_LPG
[17:51:58] [PASSED] 12.71 Xe_LPG
[17:51:58] [PASSED] 12.74 Xe_LPG+
[17:51:58] [PASSED] 20.01 Xe2_HPG
[17:51:58] [PASSED] 20.02 Xe2_HPG
[17:51:58] [PASSED] 20.04 Xe2_LPG
[17:51:58] [PASSED] 30.00 Xe3_LPG
[17:51:58] [PASSED] 30.01 Xe3_LPG
[17:51:58] [PASSED] 30.03 Xe3_LPG
[17:51:58] [PASSED] 30.04 Xe3_LPG
[17:51:58] [PASSED] 30.05 Xe3_LPG
[17:51:58] [PASSED] 35.11 Xe3p_XPC
[17:51:58] ================ [PASSED] check_graphics_ip ================
[17:51:58] ===================== check_media_ip ======================
[17:51:58] [PASSED] 12.00 Xe_M
[17:51:58] [PASSED] 12.55 Xe_HPM
[17:51:58] [PASSED] 13.00 Xe_LPM+
[17:51:58] [PASSED] 13.01 Xe2_HPM
[17:51:58] [PASSED] 20.00 Xe2_LPM
[17:51:58] [PASSED] 30.00 Xe3_LPM
[17:51:58] [PASSED] 30.02 Xe3_LPM
[17:51:58] [PASSED] 35.00 Xe3p_LPM
[17:51:58] [PASSED] 35.03 Xe3p_HPM
[17:51:58] ================= [PASSED] check_media_ip ==================
[17:51:58] =================== check_platform_desc ===================
[17:51:58] [PASSED] 0x9A60 (TIGERLAKE)
[17:51:58] [PASSED] 0x9A68 (TIGERLAKE)
[17:51:58] [PASSED] 0x9A70 (TIGERLAKE)
[17:51:58] [PASSED] 0x9A40 (TIGERLAKE)
[17:51:58] [PASSED] 0x9A49 (TIGERLAKE)
[17:51:58] [PASSED] 0x9A59 (TIGERLAKE)
[17:51:58] [PASSED] 0x9A78 (TIGERLAKE)
[17:51:58] [PASSED] 0x9AC0 (TIGERLAKE)
[17:51:58] [PASSED] 0x9AC9 (TIGERLAKE)
[17:51:58] [PASSED] 0x9AD9 (TIGERLAKE)
[17:51:58] [PASSED] 0x9AF8 (TIGERLAKE)
[17:51:58] [PASSED] 0x4C80 (ROCKETLAKE)
[17:51:58] [PASSED] 0x4C8A (ROCKETLAKE)
[17:51:58] [PASSED] 0x4C8B (ROCKETLAKE)
[17:51:58] [PASSED] 0x4C8C (ROCKETLAKE)
[17:51:58] [PASSED] 0x4C90 (ROCKETLAKE)
[17:51:58] [PASSED] 0x4C9A (ROCKETLAKE)
[17:51:58] [PASSED] 0x4680 (ALDERLAKE_S)
[17:51:58] [PASSED] 0x4682 (ALDERLAKE_S)
[17:51:58] [PASSED] 0x4688 (ALDERLAKE_S)
[17:51:58] [PASSED] 0x468A (ALDERLAKE_S)
[17:51:58] [PASSED] 0x468B (ALDERLAKE_S)
[17:51:58] [PASSED] 0x4690 (ALDERLAKE_S)
[17:51:58] [PASSED] 0x4692 (ALDERLAKE_S)
[17:51:58] [PASSED] 0x4693 (ALDERLAKE_S)
[17:51:58] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46AA (ALDERLAKE_P)
[17:51:58] [PASSED] 0x462A (ALDERLAKE_P)
[17:51:58] [PASSED] 0x4626 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[17:51:58] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:51:58] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:51:58] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:51:58] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:51:58] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:51:58] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:51:58] [PASSED] 0xA721 (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA720 (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:51:58] [PASSED] 0xA780 (ALDERLAKE_S)
[17:51:58] [PASSED] 0xA781 (ALDERLAKE_S)
[17:51:58] [PASSED] 0xA782 (ALDERLAKE_S)
[17:51:58] [PASSED] 0xA783 (ALDERLAKE_S)
[17:51:58] [PASSED] 0xA788 (ALDERLAKE_S)
[17:51:58] [PASSED] 0xA789 (ALDERLAKE_S)
[17:51:58] [PASSED] 0xA78A (ALDERLAKE_S)
[17:51:58] [PASSED] 0xA78B (ALDERLAKE_S)
[17:51:58] [PASSED] 0x4905 (DG1)
[17:51:58] [PASSED] 0x4906 (DG1)
[17:51:58] [PASSED] 0x4907 (DG1)
[17:51:58] [PASSED] 0x4908 (DG1)
[17:51:58] [PASSED] 0x4909 (DG1)
[17:51:58] [PASSED] 0x56C0 (DG2)
[17:51:58] [PASSED] 0x56C2 (DG2)
[17:51:58] [PASSED] 0x56C1 (DG2)
[17:51:58] [PASSED] 0x7D51 (METEORLAKE)
[17:51:58] [PASSED] 0x7DD1 (METEORLAKE)
[17:51:58] [PASSED] 0x7D41 (METEORLAKE)
[17:51:58] [PASSED] 0x7D67 (METEORLAKE)
[17:51:58] [PASSED] 0xB640 (METEORLAKE)
[17:51:58] [PASSED] 0x56A0 (DG2)
[17:51:58] [PASSED] 0x56A1 (DG2)
[17:51:58] [PASSED] 0x56A2 (DG2)
[17:51:58] [PASSED] 0x56BE (DG2)
[17:51:58] [PASSED] 0x56BF (DG2)
[17:51:58] [PASSED] 0x5690 (DG2)
[17:51:58] [PASSED] 0x5691 (DG2)
[17:51:58] [PASSED] 0x5692 (DG2)
[17:51:58] [PASSED] 0x56A5 (DG2)
[17:51:58] [PASSED] 0x56A6 (DG2)
[17:51:58] [PASSED] 0x56B0 (DG2)
[17:51:58] [PASSED] 0x56B1 (DG2)
[17:51:58] [PASSED] 0x56BA (DG2)
[17:51:58] [PASSED] 0x56BB (DG2)
[17:51:58] [PASSED] 0x56BC (DG2)
[17:51:58] [PASSED] 0x56BD (DG2)
[17:51:58] [PASSED] 0x5693 (DG2)
[17:51:58] [PASSED] 0x5694 (DG2)
[17:51:58] [PASSED] 0x5695 (DG2)
[17:51:58] [PASSED] 0x56A3 (DG2)
[17:51:58] [PASSED] 0x56A4 (DG2)
[17:51:58] [PASSED] 0x56B2 (DG2)
[17:51:58] [PASSED] 0x56B3 (DG2)
[17:51:58] [PASSED] 0x5696 (DG2)
[17:51:58] [PASSED] 0x5697 (DG2)
[17:51:58] [PASSED] 0xB69 (PVC)
[17:51:58] [PASSED] 0xB6E (PVC)
[17:51:58] [PASSED] 0xBD4 (PVC)
[17:51:58] [PASSED] 0xBD5 (PVC)
[17:51:58] [PASSED] 0xBD6 (PVC)
[17:51:58] [PASSED] 0xBD7 (PVC)
[17:51:58] [PASSED] 0xBD8 (PVC)
[17:51:58] [PASSED] 0xBD9 (PVC)
[17:51:58] [PASSED] 0xBDA (PVC)
[17:51:58] [PASSED] 0xBDB (PVC)
[17:51:58] [PASSED] 0xBE0 (PVC)
[17:51:58] [PASSED] 0xBE1 (PVC)
[17:51:58] [PASSED] 0xBE5 (PVC)
[17:51:58] [PASSED] 0x7D40 (METEORLAKE)
[17:51:58] [PASSED] 0x7D45 (METEORLAKE)
[17:51:58] [PASSED] 0x7D55 (METEORLAKE)
[17:51:58] [PASSED] 0x7D60 (METEORLAKE)
[17:51:58] [PASSED] 0x7DD5 (METEORLAKE)
[17:51:58] [PASSED] 0x6420 (LUNARLAKE)
[17:51:58] [PASSED] 0x64A0 (LUNARLAKE)
[17:51:58] [PASSED] 0x64B0 (LUNARLAKE)
[17:51:58] [PASSED] 0xE202 (BATTLEMAGE)
[17:51:58] [PASSED] 0xE209 (BATTLEMAGE)
[17:51:58] [PASSED] 0xE20B (BATTLEMAGE)
[17:51:58] [PASSED] 0xE20C (BATTLEMAGE)
[17:51:58] [PASSED] 0xE20D (BATTLEMAGE)
[17:51:58] [PASSED] 0xE210 (BATTLEMAGE)
[17:51:58] [PASSED] 0xE211 (BATTLEMAGE)
[17:51:58] [PASSED] 0xE212 (BATTLEMAGE)
[17:51:58] [PASSED] 0xE216 (BATTLEMAGE)
[17:51:58] [PASSED] 0xE220 (BATTLEMAGE)
[17:51:58] [PASSED] 0xE221 (BATTLEMAGE)
[17:51:58] [PASSED] 0xE222 (BATTLEMAGE)
[17:51:58] [PASSED] 0xE223 (BATTLEMAGE)
[17:51:58] [PASSED] 0xB080 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB081 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB082 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB083 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB084 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB085 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB086 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB087 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB08F (PANTHERLAKE)
[17:51:58] [PASSED] 0xB090 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:51:58] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:51:58] [PASSED] 0xFD80 (PANTHERLAKE)
[17:51:58] [PASSED] 0xFD81 (PANTHERLAKE)
[17:51:58] [PASSED] 0xD740 (NOVALAKE_S)
[17:51:58] [PASSED] 0xD741 (NOVALAKE_S)
[17:51:58] [PASSED] 0xD742 (NOVALAKE_S)
[17:51:58] [PASSED] 0xD743 (NOVALAKE_S)
[17:51:58] [PASSED] 0xD744 (NOVALAKE_S)
[17:51:58] [PASSED] 0xD745 (NOVALAKE_S)
[17:51:58] [PASSED] 0x674C (CRESCENTISLAND)
[17:51:58] =============== [PASSED] check_platform_desc ===============
[17:51:58] ===================== [PASSED] xe_pci ======================
[17:51:58] =================== xe_rtp (2 subtests) ====================
[17:51:58] =============== xe_rtp_process_to_sr_tests ================
[17:51:58] [PASSED] coalesce-same-reg
[17:51:58] [PASSED] no-match-no-add
[17:51:58] [PASSED] match-or
[17:51:58] [PASSED] match-or-xfail
[17:51:58] [PASSED] no-match-no-add-multiple-rules
[17:51:58] [PASSED] two-regs-two-entries
[17:51:58] [PASSED] clr-one-set-other
[17:51:58] [PASSED] set-field
[17:51:58] [PASSED] conflict-duplicate
[17:51:58] [PASSED] conflict-not-disjoint
[17:51:58] [PASSED] conflict-reg-type
[17:51:58] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:51:58] ================== xe_rtp_process_tests ===================
[17:51:58] [PASSED] active1
[17:51:58] [PASSED] active2
[17:51:58] [PASSED] active-inactive
[17:51:58] [PASSED] inactive-active
[17:51:58] [PASSED] inactive-1st_or_active-inactive
[17:51:58] [PASSED] inactive-2nd_or_active-inactive
[17:51:58] [PASSED] inactive-last_or_active-inactive
[17:51:58] [PASSED] inactive-no_or_active-inactive
[17:51:58] ============== [PASSED] xe_rtp_process_tests ===============
[17:51:58] ===================== [PASSED] xe_rtp ======================
[17:51:58] ==================== xe_wa (1 subtest) =====================
[17:51:58] ======================== xe_wa_gt =========================
[17:51:58] [PASSED] TIGERLAKE B0
[17:51:58] [PASSED] DG1 A0
[17:51:58] [PASSED] DG1 B0
[17:51:58] [PASSED] ALDERLAKE_S A0
[17:51:58] [PASSED] ALDERLAKE_S B0
[17:51:58] [PASSED] ALDERLAKE_S C0
[17:51:58] [PASSED] ALDERLAKE_S D0
[17:51:58] [PASSED] ALDERLAKE_P A0
[17:51:58] [PASSED] ALDERLAKE_P B0
[17:51:58] [PASSED] ALDERLAKE_P C0
[17:51:58] [PASSED] ALDERLAKE_S RPLS D0
[17:51:58] [PASSED] ALDERLAKE_P RPLU E0
[17:51:58] [PASSED] DG2 G10 C0
[17:51:58] [PASSED] DG2 G11 B1
[17:51:58] [PASSED] DG2 G12 A1
[17:51:58] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:51:58] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:51:58] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:51:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:51:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:51:58] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:51:58] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:51:58] ==================== [PASSED] xe_wa_gt =====================
[17:51:58] ====================== [PASSED] xe_wa ======================
[17:51:58] ============================================================
[17:51:58] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[17:51:58] Elapsed time: 36.707s total, 4.174s configuring, 32.016s building, 0.471s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:51:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:52:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:52:25] Starting KUnit Kernel (1/1)...
[17:52:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:52:25] ============ drm_test_pick_cmdline (2 subtests) ============
[17:52:25] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:52:25] =============== drm_test_pick_cmdline_named ===============
[17:52:25] [PASSED] NTSC
[17:52:25] [PASSED] NTSC-J
[17:52:25] [PASSED] PAL
[17:52:25] [PASSED] PAL-M
[17:52:25] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:52:25] ============== [PASSED] drm_test_pick_cmdline ==============
[17:52:25] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:52:25] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:52:25] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:52:25] =========== drm_validate_clone_mode (2 subtests) ===========
[17:52:25] ============== drm_test_check_in_clone_mode ===============
[17:52:25] [PASSED] in_clone_mode
[17:52:25] [PASSED] not_in_clone_mode
[17:52:25] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:52:25] =============== drm_test_check_valid_clones ===============
[17:52:25] [PASSED] not_in_clone_mode
[17:52:25] [PASSED] valid_clone
[17:52:25] [PASSED] invalid_clone
[17:52:25] =========== [PASSED] drm_test_check_valid_clones ===========
[17:52:25] ============= [PASSED] drm_validate_clone_mode =============
[17:52:25] ============= drm_validate_modeset (1 subtest) =============
[17:52:25] [PASSED] drm_test_check_connector_changed_modeset
[17:52:25] ============== [PASSED] drm_validate_modeset ===============
[17:52:25] ====== drm_test_bridge_get_current_state (2 subtests) ======
[17:52:25] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:52:25] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[17:52:25] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:52:25] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:52:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:52:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:52:25] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[17:52:25] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:52:25] ============== drm_bridge_alloc (2 subtests) ===============
[17:52:25] [PASSED] drm_test_drm_bridge_alloc_basic
[17:52:25] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:52:25] ================ [PASSED] drm_bridge_alloc =================
[17:52:25] ================== drm_buddy (9 subtests) ==================
[17:52:25] [PASSED] drm_test_buddy_alloc_limit
[17:52:25] [PASSED] drm_test_buddy_alloc_optimistic
[17:52:25] [PASSED] drm_test_buddy_alloc_pessimistic
[17:52:25] [PASSED] drm_test_buddy_alloc_pathological
[17:52:25] [PASSED] drm_test_buddy_alloc_contiguous
[17:52:25] [PASSED] drm_test_buddy_alloc_clear
[17:52:26] [PASSED] drm_test_buddy_alloc_range_bias
[17:52:26] [PASSED] drm_test_buddy_fragmentation_performance
[17:52:26] [PASSED] drm_test_buddy_alloc_exceeds_max_order
[17:52:26] ==================== [PASSED] drm_buddy ====================
[17:52:26] ============= drm_cmdline_parser (40 subtests) =============
[17:52:26] [PASSED] drm_test_cmdline_force_d_only
[17:52:26] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:52:26] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:52:26] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:52:26] [PASSED] drm_test_cmdline_force_e_only
[17:52:26] [PASSED] drm_test_cmdline_res
[17:52:26] [PASSED] drm_test_cmdline_res_vesa
[17:52:26] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:52:26] [PASSED] drm_test_cmdline_res_rblank
[17:52:26] [PASSED] drm_test_cmdline_res_bpp
[17:52:26] [PASSED] drm_test_cmdline_res_refresh
[17:52:26] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:52:26] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:52:26] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:52:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:52:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:52:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:52:26] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:52:26] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:52:26] [PASSED] drm_test_cmdline_res_margins_force_on
[17:52:26] [PASSED] drm_test_cmdline_res_vesa_margins
[17:52:26] [PASSED] drm_test_cmdline_name
[17:52:26] [PASSED] drm_test_cmdline_name_bpp
[17:52:26] [PASSED] drm_test_cmdline_name_option
[17:52:26] [PASSED] drm_test_cmdline_name_bpp_option
[17:52:26] [PASSED] drm_test_cmdline_rotate_0
[17:52:26] [PASSED] drm_test_cmdline_rotate_90
[17:52:26] [PASSED] drm_test_cmdline_rotate_180
[17:52:26] [PASSED] drm_test_cmdline_rotate_270
[17:52:26] [PASSED] drm_test_cmdline_hmirror
[17:52:26] [PASSED] drm_test_cmdline_vmirror
[17:52:26] [PASSED] drm_test_cmdline_margin_options
[17:52:26] [PASSED] drm_test_cmdline_multiple_options
[17:52:26] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:52:26] [PASSED] drm_test_cmdline_extra_and_option
[17:52:26] [PASSED] drm_test_cmdline_freestanding_options
[17:52:26] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:52:26] [PASSED] drm_test_cmdline_panel_orientation
[17:52:26] ================ drm_test_cmdline_invalid =================
[17:52:26] [PASSED] margin_only
[17:52:26] [PASSED] interlace_only
[17:52:26] [PASSED] res_missing_x
[17:52:26] [PASSED] res_missing_y
[17:52:26] [PASSED] res_bad_y
[17:52:26] [PASSED] res_missing_y_bpp
[17:52:26] [PASSED] res_bad_bpp
[17:52:26] [PASSED] res_bad_refresh
[17:52:26] [PASSED] res_bpp_refresh_force_on_off
[17:52:26] [PASSED] res_invalid_mode
[17:52:26] [PASSED] res_bpp_wrong_place_mode
[17:52:26] [PASSED] name_bpp_refresh
[17:52:26] [PASSED] name_refresh
[17:52:26] [PASSED] name_refresh_wrong_mode
[17:52:26] [PASSED] name_refresh_invalid_mode
[17:52:26] [PASSED] rotate_multiple
[17:52:26] [PASSED] rotate_invalid_val
[17:52:26] [PASSED] rotate_truncated
[17:52:26] [PASSED] invalid_option
[17:52:26] [PASSED] invalid_tv_option
[17:52:26] [PASSED] truncated_tv_option
[17:52:26] ============ [PASSED] drm_test_cmdline_invalid =============
[17:52:26] =============== drm_test_cmdline_tv_options ===============
[17:52:26] [PASSED] NTSC
[17:52:26] [PASSED] NTSC_443
[17:52:26] [PASSED] NTSC_J
[17:52:26] [PASSED] PAL
[17:52:26] [PASSED] PAL_M
[17:52:26] [PASSED] PAL_N
[17:52:26] [PASSED] SECAM
[17:52:26] [PASSED] MONO_525
[17:52:26] [PASSED] MONO_625
[17:52:26] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:52:26] =============== [PASSED] drm_cmdline_parser ================
[17:52:26] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:52:26] [PASSED] drm_test_connector_hdmi_init_valid
[17:52:26] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:52:26] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:52:26] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:52:26] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:52:26] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:52:26] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:52:26] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:52:26] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:52:26] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:52:26] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:52:26] [PASSED] supported_formats=0x3 yuv420_allowed=1
[17:52:26] [PASSED] supported_formats=0x3 yuv420_allowed=0
[17:52:26] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:52:26] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:52:26] [PASSED] drm_test_connector_hdmi_init_null_product
[17:52:26] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:52:26] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:52:26] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:52:26] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:52:26] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:52:26] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:52:26] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:52:26] ========= drm_test_connector_hdmi_init_type_valid =========
[17:52:26] [PASSED] HDMI-A
[17:52:26] [PASSED] HDMI-B
[17:52:26] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:52:26] ======== drm_test_connector_hdmi_init_type_invalid ========
[17:52:26] [PASSED] Unknown
[17:52:26] [PASSED] VGA
[17:52:26] [PASSED] DVI-I
[17:52:26] [PASSED] DVI-D
[17:52:26] [PASSED] DVI-A
[17:52:26] [PASSED] Composite
[17:52:26] [PASSED] SVIDEO
[17:52:26] [PASSED] LVDS
[17:52:26] [PASSED] Component
[17:52:26] [PASSED] DIN
[17:52:26] [PASSED] DP
[17:52:26] [PASSED] TV
[17:52:26] [PASSED] eDP
[17:52:26] [PASSED] Virtual
[17:52:26] [PASSED] DSI
[17:52:26] [PASSED] DPI
[17:52:26] [PASSED] Writeback
[17:52:26] [PASSED] SPI
[17:52:26] [PASSED] USB
[17:52:26] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:52:26] ============ [PASSED] drmm_connector_hdmi_init =============
[17:52:26] ============= drmm_connector_init (3 subtests) =============
[17:52:26] [PASSED] drm_test_drmm_connector_init
[17:52:26] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:52:26] ========= drm_test_drmm_connector_init_type_valid =========
[17:52:26] [PASSED] Unknown
[17:52:26] [PASSED] VGA
[17:52:26] [PASSED] DVI-I
[17:52:26] [PASSED] DVI-D
[17:52:26] [PASSED] DVI-A
[17:52:26] [PASSED] Composite
[17:52:26] [PASSED] SVIDEO
[17:52:26] [PASSED] LVDS
[17:52:26] [PASSED] Component
[17:52:26] [PASSED] DIN
[17:52:26] [PASSED] DP
[17:52:26] [PASSED] HDMI-A
[17:52:26] [PASSED] HDMI-B
[17:52:26] [PASSED] TV
[17:52:26] [PASSED] eDP
[17:52:26] [PASSED] Virtual
[17:52:26] [PASSED] DSI
[17:52:26] [PASSED] DPI
[17:52:26] [PASSED] Writeback
[17:52:26] [PASSED] SPI
[17:52:26] [PASSED] USB
[17:52:26] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:52:26] =============== [PASSED] drmm_connector_init ===============
[17:52:26] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_init
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:52:26] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[17:52:26] [PASSED] Unknown
[17:52:26] [PASSED] VGA
[17:52:26] [PASSED] DVI-I
[17:52:26] [PASSED] DVI-D
[17:52:26] [PASSED] DVI-A
[17:52:26] [PASSED] Composite
[17:52:26] [PASSED] SVIDEO
[17:52:26] [PASSED] LVDS
[17:52:26] [PASSED] Component
[17:52:26] [PASSED] DIN
[17:52:26] [PASSED] DP
[17:52:26] [PASSED] HDMI-A
[17:52:26] [PASSED] HDMI-B
[17:52:26] [PASSED] TV
[17:52:26] [PASSED] eDP
[17:52:26] [PASSED] Virtual
[17:52:26] [PASSED] DSI
[17:52:26] [PASSED] DPI
[17:52:26] [PASSED] Writeback
[17:52:26] [PASSED] SPI
[17:52:26] [PASSED] USB
[17:52:26] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:52:26] ======== drm_test_drm_connector_dynamic_init_name =========
[17:52:26] [PASSED] Unknown
[17:52:26] [PASSED] VGA
[17:52:26] [PASSED] DVI-I
[17:52:26] [PASSED] DVI-D
[17:52:26] [PASSED] DVI-A
[17:52:26] [PASSED] Composite
[17:52:26] [PASSED] SVIDEO
[17:52:26] [PASSED] LVDS
[17:52:26] [PASSED] Component
[17:52:26] [PASSED] DIN
[17:52:26] [PASSED] DP
[17:52:26] [PASSED] HDMI-A
[17:52:26] [PASSED] HDMI-B
[17:52:26] [PASSED] TV
[17:52:26] [PASSED] eDP
[17:52:26] [PASSED] Virtual
[17:52:26] [PASSED] DSI
[17:52:26] [PASSED] DPI
[17:52:26] [PASSED] Writeback
[17:52:26] [PASSED] SPI
[17:52:26] [PASSED] USB
[17:52:26] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:52:26] =========== [PASSED] drm_connector_dynamic_init ============
[17:52:26] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:52:26] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:52:26] ======= drm_connector_dynamic_register (7 subtests) ========
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:52:26] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:52:26] ========= [PASSED] drm_connector_dynamic_register ==========
[17:52:26] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:52:26] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:52:26] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:52:26] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:52:26] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:52:26] ========== drm_test_get_tv_mode_from_name_valid ===========
[17:52:26] [PASSED] NTSC
[17:52:26] [PASSED] NTSC-443
[17:52:26] [PASSED] NTSC-J
[17:52:26] [PASSED] PAL
[17:52:26] [PASSED] PAL-M
[17:52:26] [PASSED] PAL-N
[17:52:26] [PASSED] SECAM
[17:52:26] [PASSED] Mono
[17:52:26] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:52:26] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:52:26] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:52:26] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:52:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:52:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:52:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:52:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:52:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:52:26] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:52:26] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[17:52:26] [PASSED] VIC 96
[17:52:26] [PASSED] VIC 97
[17:52:26] [PASSED] VIC 101
[17:52:26] [PASSED] VIC 102
[17:52:26] [PASSED] VIC 106
[17:52:26] [PASSED] VIC 107
[17:52:26] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:52:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:52:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:52:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:52:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:52:26] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:52:26] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:52:26] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:52:26] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[17:52:26] [PASSED] Automatic
[17:52:26] [PASSED] Full
[17:52:26] [PASSED] Limited 16:235
[17:52:26] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:52:26] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:52:26] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:52:26] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:52:26] === drm_test_drm_hdmi_connector_get_output_format_name ====
[17:52:26] [PASSED] RGB
[17:52:26] [PASSED] YUV 4:2:0
[17:52:26] [PASSED] YUV 4:2:2
[17:52:26] [PASSED] YUV 4:4:4
[17:52:26] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:52:26] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:52:26] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:52:26] ============= drm_damage_helper (21 subtests) ==============
[17:52:26] [PASSED] drm_test_damage_iter_no_damage
[17:52:26] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:52:26] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:52:26] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:52:26] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:52:26] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:52:26] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:52:26] [PASSED] drm_test_damage_iter_simple_damage
[17:52:26] [PASSED] drm_test_damage_iter_single_damage
[17:52:26] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:52:26] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:52:26] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:52:26] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:52:26] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:52:26] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:52:26] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:52:26] [PASSED] drm_test_damage_iter_damage
[17:52:26] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:52:26] [PASSED] drm_test_damage_iter_damage_one_outside
[17:52:26] [PASSED] drm_test_damage_iter_damage_src_moved
[17:52:26] [PASSED] drm_test_damage_iter_damage_not_visible
[17:52:26] ================ [PASSED] drm_damage_helper ================
[17:52:26] ============== drm_dp_mst_helper (3 subtests) ==============
[17:52:26] ============== drm_test_dp_mst_calc_pbn_mode ==============
[17:52:26] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:52:26] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:52:26] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:52:26] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:52:26] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:52:26] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:52:26] ============== drm_test_dp_mst_calc_pbn_div ===============
[17:52:26] [PASSED] Link rate 2000000 lane count 4
[17:52:26] [PASSED] Link rate 2000000 lane count 2
[17:52:26] [PASSED] Link rate 2000000 lane count 1
[17:52:26] [PASSED] Link rate 1350000 lane count 4
[17:52:26] [PASSED] Link rate 1350000 lane count 2
[17:52:26] [PASSED] Link rate 1350000 lane count 1
[17:52:26] [PASSED] Link rate 1000000 lane count 4
[17:52:26] [PASSED] Link rate 1000000 lane count 2
[17:52:26] [PASSED] Link rate 1000000 lane count 1
[17:52:26] [PASSED] Link rate 810000 lane count 4
[17:52:26] [PASSED] Link rate 810000 lane count 2
[17:52:26] [PASSED] Link rate 810000 lane count 1
[17:52:26] [PASSED] Link rate 540000 lane count 4
[17:52:26] [PASSED] Link rate 540000 lane count 2
[17:52:26] [PASSED] Link rate 540000 lane count 1
[17:52:26] [PASSED] Link rate 270000 lane count 4
[17:52:26] [PASSED] Link rate 270000 lane count 2
[17:52:26] [PASSED] Link rate 270000 lane count 1
[17:52:26] [PASSED] Link rate 162000 lane count 4
[17:52:26] [PASSED] Link rate 162000 lane count 2
[17:52:26] [PASSED] Link rate 162000 lane count 1
[17:52:26] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:52:26] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[17:52:26] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:52:26] [PASSED] DP_POWER_UP_PHY with port number
[17:52:26] [PASSED] DP_POWER_DOWN_PHY with port number
[17:52:26] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:52:26] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:52:26] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:52:26] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:52:26] [PASSED] DP_QUERY_PAYLOAD with port number
[17:52:26] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:52:26] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:52:26] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:52:26] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:52:26] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:52:26] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:52:26] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:52:26] [PASSED] DP_REMOTE_I2C_READ with port number
[17:52:26] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:52:26] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:52:26] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:52:26] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:52:26] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:52:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:52:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:52:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:52:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:52:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:52:26] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:52:26] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:52:26] ================ [PASSED] drm_dp_mst_helper ================
[17:52:26] ================== drm_exec (7 subtests) ===================
[17:52:26] [PASSED] sanitycheck
[17:52:26] [PASSED] test_lock
[17:52:26] [PASSED] test_lock_unlock
[17:52:26] [PASSED] test_duplicates
[17:52:26] [PASSED] test_prepare
[17:52:26] [PASSED] test_prepare_array
[17:52:26] [PASSED] test_multiple_loops
[17:52:26] ==================== [PASSED] drm_exec =====================
[17:52:26] =========== drm_format_helper_test (17 subtests) ===========
[17:52:26] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:52:26] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:52:26] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:52:26] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:52:26] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:52:26] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:52:26] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:52:26] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:52:26] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:52:26] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:52:26] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:52:26] ============== drm_test_fb_xrgb8888_to_mono ===============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:52:26] ==================== drm_test_fb_swab =====================
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ================ [PASSED] drm_test_fb_swab =================
[17:52:26] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:52:26] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[17:52:26] [PASSED] single_pixel_source_buffer
[17:52:26] [PASSED] single_pixel_clip_rectangle
[17:52:26] [PASSED] well_known_colors
[17:52:26] [PASSED] destination_pitch
[17:52:26] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:52:26] ================= drm_test_fb_clip_offset =================
[17:52:26] [PASSED] pass through
[17:52:26] [PASSED] horizontal offset
[17:52:26] [PASSED] vertical offset
[17:52:26] [PASSED] horizontal and vertical offset
[17:52:26] [PASSED] horizontal offset (custom pitch)
[17:52:26] [PASSED] vertical offset (custom pitch)
[17:52:26] [PASSED] horizontal and vertical offset (custom pitch)
[17:52:26] ============= [PASSED] drm_test_fb_clip_offset =============
[17:52:26] =================== drm_test_fb_memcpy ====================
[17:52:26] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:52:26] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:52:26] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:52:26] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:52:26] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:52:26] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:52:26] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:52:26] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:52:26] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:52:26] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:52:26] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:52:26] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:52:26] =============== [PASSED] drm_test_fb_memcpy ================
[17:52:26] ============= [PASSED] drm_format_helper_test ==============
[17:52:26] ================= drm_format (18 subtests) =================
[17:52:26] [PASSED] drm_test_format_block_width_invalid
[17:52:26] [PASSED] drm_test_format_block_width_one_plane
[17:52:26] [PASSED] drm_test_format_block_width_two_plane
[17:52:26] [PASSED] drm_test_format_block_width_three_plane
[17:52:26] [PASSED] drm_test_format_block_width_tiled
[17:52:26] [PASSED] drm_test_format_block_height_invalid
[17:52:26] [PASSED] drm_test_format_block_height_one_plane
[17:52:26] [PASSED] drm_test_format_block_height_two_plane
[17:52:26] [PASSED] drm_test_format_block_height_three_plane
[17:52:26] [PASSED] drm_test_format_block_height_tiled
[17:52:26] [PASSED] drm_test_format_min_pitch_invalid
[17:52:26] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:52:26] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:52:26] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:52:26] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:52:26] [PASSED] drm_test_format_min_pitch_two_plane
[17:52:26] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:52:26] [PASSED] drm_test_format_min_pitch_tiled
[17:52:26] =================== [PASSED] drm_format ====================
[17:52:26] ============== drm_framebuffer (10 subtests) ===============
[17:52:26] ========== drm_test_framebuffer_check_src_coords ==========
[17:52:26] [PASSED] Success: source fits into fb
[17:52:26] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:52:26] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:52:26] [PASSED] Fail: overflowing fb with source width
[17:52:26] [PASSED] Fail: overflowing fb with source height
[17:52:26] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:52:26] [PASSED] drm_test_framebuffer_cleanup
[17:52:26] =============== drm_test_framebuffer_create ===============
[17:52:26] [PASSED] ABGR8888 normal sizes
[17:52:26] [PASSED] ABGR8888 max sizes
[17:52:26] [PASSED] ABGR8888 pitch greater than min required
[17:52:26] [PASSED] ABGR8888 pitch less than min required
[17:52:26] [PASSED] ABGR8888 Invalid width
[17:52:26] [PASSED] ABGR8888 Invalid buffer handle
[17:52:26] [PASSED] No pixel format
[17:52:26] [PASSED] ABGR8888 Width 0
[17:52:26] [PASSED] ABGR8888 Height 0
[17:52:26] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:52:26] [PASSED] ABGR8888 Large buffer offset
[17:52:26] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:52:26] [PASSED] ABGR8888 Invalid flag
[17:52:26] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:52:26] [PASSED] ABGR8888 Valid buffer modifier
[17:52:26] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:52:26] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:52:26] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:52:26] [PASSED] NV12 Normal sizes
[17:52:26] [PASSED] NV12 Max sizes
[17:52:26] [PASSED] NV12 Invalid pitch
[17:52:26] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:52:26] [PASSED] NV12 different modifier per-plane
[17:52:26] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:52:26] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:52:26] [PASSED] NV12 Modifier for inexistent plane
[17:52:26] [PASSED] NV12 Handle for inexistent plane
[17:52:26] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:52:26] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:52:26] [PASSED] YVU420 Normal sizes
[17:52:26] [PASSED] YVU420 Max sizes
[17:52:26] [PASSED] YVU420 Invalid pitch
[17:52:26] [PASSED] YVU420 Different pitches
[17:52:26] [PASSED] YVU420 Different buffer offsets/pitches
[17:52:26] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:52:26] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:52:26] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:52:26] [PASSED] YVU420 Valid modifier
[17:52:26] [PASSED] YVU420 Different modifiers per plane
[17:52:26] [PASSED] YVU420 Modifier for inexistent plane
[17:52:26] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:52:26] [PASSED] X0L2 Normal sizes
[17:52:26] [PASSED] X0L2 Max sizes
[17:52:26] [PASSED] X0L2 Invalid pitch
[17:52:26] [PASSED] X0L2 Pitch greater than minimum required
[17:52:26] [PASSED] X0L2 Handle for inexistent plane
[17:52:26] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:52:26] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:52:26] [PASSED] X0L2 Valid modifier
[17:52:26] [PASSED] X0L2 Modifier for inexistent plane
[17:52:26] =========== [PASSED] drm_test_framebuffer_create ===========
[17:52:26] [PASSED] drm_test_framebuffer_free
[17:52:26] [PASSED] drm_test_framebuffer_init
[17:52:26] [PASSED] drm_test_framebuffer_init_bad_format
[17:52:26] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:52:26] [PASSED] drm_test_framebuffer_lookup
[17:52:26] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:52:26] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:52:26] ================= [PASSED] drm_framebuffer =================
[17:52:26] ================ drm_gem_shmem (8 subtests) ================
[17:52:26] [PASSED] drm_gem_shmem_test_obj_create
[17:52:26] [PASSED] drm_gem_shmem_test_obj_create_private
[17:52:26] [PASSED] drm_gem_shmem_test_pin_pages
[17:52:26] [PASSED] drm_gem_shmem_test_vmap
[17:52:26] [PASSED] drm_gem_shmem_test_get_sg_table
[17:52:26] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:52:26] [PASSED] drm_gem_shmem_test_madvise
[17:52:26] [PASSED] drm_gem_shmem_test_purge
[17:52:26] ================== [PASSED] drm_gem_shmem ==================
[17:52:26] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[17:52:26] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:52:26] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:52:26] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:52:26] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:52:26] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:52:26] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:52:26] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[17:52:26] [PASSED] Automatic
[17:52:26] [PASSED] Full
[17:52:26] [PASSED] Limited 16:235
[17:52:26] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:52:26] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:52:26] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:52:26] [PASSED] drm_test_check_disable_connector
[17:52:26] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:52:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:52:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:52:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:52:26] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:52:26] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:52:26] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:52:26] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:52:26] [PASSED] drm_test_check_output_bpc_dvi
[17:52:26] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:52:26] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:52:26] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:52:26] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:52:26] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:52:26] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:52:26] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:52:26] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:52:26] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:52:26] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:52:26] [PASSED] drm_test_check_broadcast_rgb_value
[17:52:26] [PASSED] drm_test_check_bpc_8_value
[17:52:26] [PASSED] drm_test_check_bpc_10_value
[17:52:26] [PASSED] drm_test_check_bpc_12_value
[17:52:26] [PASSED] drm_test_check_format_value
[17:52:26] [PASSED] drm_test_check_tmds_char_value
[17:52:26] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:52:26] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[17:52:26] [PASSED] drm_test_check_mode_valid
[17:52:26] [PASSED] drm_test_check_mode_valid_reject
[17:52:26] [PASSED] drm_test_check_mode_valid_reject_rate
[17:52:26] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:52:26] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:52:26] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[17:52:26] [PASSED] drm_test_check_infoframes
[17:52:26] [PASSED] drm_test_check_reject_avi_infoframe
[17:52:26] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[17:52:26] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[17:52:26] [PASSED] drm_test_check_reject_audio_infoframe
[17:52:26] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[17:52:26] ================= drm_managed (2 subtests) =================
[17:52:26] [PASSED] drm_test_managed_release_action
[17:52:26] [PASSED] drm_test_managed_run_action
[17:52:26] =================== [PASSED] drm_managed ===================
[17:52:26] =================== drm_mm (6 subtests) ====================
[17:52:26] [PASSED] drm_test_mm_init
[17:52:26] [PASSED] drm_test_mm_debug
[17:52:26] [PASSED] drm_test_mm_align32
[17:52:26] [PASSED] drm_test_mm_align64
[17:52:26] [PASSED] drm_test_mm_lowest
[17:52:26] [PASSED] drm_test_mm_highest
[17:52:26] ===================== [PASSED] drm_mm ======================
[17:52:26] ============= drm_modes_analog_tv (5 subtests) =============
[17:52:26] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:52:26] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:52:26] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:52:26] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:52:26] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:52:26] =============== [PASSED] drm_modes_analog_tv ===============
[17:52:26] ============== drm_plane_helper (2 subtests) ===============
[17:52:26] =============== drm_test_check_plane_state ================
[17:52:26] [PASSED] clipping_simple
[17:52:26] [PASSED] clipping_rotate_reflect
[17:52:26] [PASSED] positioning_simple
[17:52:26] [PASSED] upscaling
[17:52:26] [PASSED] downscaling
[17:52:26] [PASSED] rounding1
[17:52:26] [PASSED] rounding2
[17:52:26] [PASSED] rounding3
[17:52:26] [PASSED] rounding4
[17:52:26] =========== [PASSED] drm_test_check_plane_state ============
[17:52:26] =========== drm_test_check_invalid_plane_state ============
[17:52:26] [PASSED] positioning_invalid
[17:52:26] [PASSED] upscaling_invalid
[17:52:26] [PASSED] downscaling_invalid
[17:52:26] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:52:26] ================ [PASSED] drm_plane_helper =================
[17:52:26] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:52:26] ====== drm_test_connector_helper_tv_get_modes_check =======
[17:52:26] [PASSED] None
[17:52:26] [PASSED] PAL
[17:52:26] [PASSED] NTSC
[17:52:26] [PASSED] Both, NTSC Default
[17:52:26] [PASSED] Both, PAL Default
[17:52:26] [PASSED] Both, NTSC Default, with PAL on command-line
[17:52:26] [PASSED] Both, PAL Default, with NTSC on command-line
[17:52:26] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:52:26] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:52:26] ================== drm_rect (9 subtests) ===================
[17:52:26] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:52:26] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:52:26] [PASSED] drm_test_rect_clip_scaled_clipped
[17:52:26] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:52:26] ================= drm_test_rect_intersect =================
[17:52:26] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:52:26] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:52:26] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:52:26] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:52:26] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:52:26] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:52:26] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:52:26] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:52:26] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:52:26] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:52:26] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:52:26] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:52:26] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:52:26] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:52:26] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[17:52:26] ============= [PASSED] drm_test_rect_intersect =============
[17:52:26] ================ drm_test_rect_calc_hscale ================
[17:52:26] [PASSED] normal use
[17:52:26] [PASSED] out of max range
[17:52:26] [PASSED] out of min range
[17:52:26] [PASSED] zero dst
[17:52:26] [PASSED] negative src
[17:52:26] [PASSED] negative dst
[17:52:26] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:52:26] ================ drm_test_rect_calc_vscale ================
[17:52:26] [PASSED] normal use
[17:52:26] [PASSED] out of max range
[17:52:26] [PASSED] out of min range
[17:52:26] [PASSED] zero dst
[17:52:26] [PASSED] negative src
[17:52:26] [PASSED] negative dst
[17:52:26] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:52:26] ================== drm_test_rect_rotate ===================
[17:52:26] [PASSED] reflect-x
[17:52:26] [PASSED] reflect-y
[17:52:26] [PASSED] rotate-0
[17:52:26] [PASSED] rotate-90
[17:52:26] [PASSED] rotate-180
[17:52:26] [PASSED] rotate-270
[17:52:26] ============== [PASSED] drm_test_rect_rotate ===============
[17:52:26] ================ drm_test_rect_rotate_inv =================
[17:52:26] [PASSED] reflect-x
[17:52:26] [PASSED] reflect-y
[17:52:26] [PASSED] rotate-0
[17:52:26] [PASSED] rotate-90
[17:52:26] [PASSED] rotate-180
[17:52:26] [PASSED] rotate-270
[17:52:26] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:52:26] ==================== [PASSED] drm_rect =====================
[17:52:26] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:52:26] ============ drm_test_sysfb_build_fourcc_list =============
[17:52:26] [PASSED] no native formats
[17:52:26] [PASSED] XRGB8888 as native format
[17:52:26] [PASSED] remove duplicates
[17:52:26] [PASSED] convert alpha formats
[17:52:26] [PASSED] random formats
[17:52:26] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:52:26] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:52:26] ================== drm_fixp (2 subtests) ===================
[17:52:26] [PASSED] drm_test_int2fixp
[17:52:26] [PASSED] drm_test_sm2fixp
[17:52:26] ==================== [PASSED] drm_fixp =====================
[17:52:26] ============================================================
[17:52:26] Testing complete. Ran 630 tests: passed: 630
[17:52:26] Elapsed time: 27.869s total, 1.635s configuring, 25.767s building, 0.424s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:52:26] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:52:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:52:37] Starting KUnit Kernel (1/1)...
[17:52:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:52:37] ================= ttm_device (5 subtests) ==================
[17:52:37] [PASSED] ttm_device_init_basic
[17:52:37] [PASSED] ttm_device_init_multiple
[17:52:37] [PASSED] ttm_device_fini_basic
[17:52:37] [PASSED] ttm_device_init_no_vma_man
[17:52:37] ================== ttm_device_init_pools ==================
[17:52:37] [PASSED] No DMA allocations, no DMA32 required
[17:52:37] [PASSED] DMA allocations, DMA32 required
[17:52:37] [PASSED] No DMA allocations, DMA32 required
[17:52:37] [PASSED] DMA allocations, no DMA32 required
[17:52:37] ============== [PASSED] ttm_device_init_pools ==============
[17:52:37] =================== [PASSED] ttm_device ====================
[17:52:37] ================== ttm_pool (8 subtests) ===================
[17:52:37] ================== ttm_pool_alloc_basic ===================
[17:52:37] [PASSED] One page
[17:52:37] [PASSED] More than one page
[17:52:37] [PASSED] Above the allocation limit
[17:52:37] [PASSED] One page, with coherent DMA mappings enabled
[17:52:37] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:52:37] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:52:37] ============== ttm_pool_alloc_basic_dma_addr ==============
[17:52:37] [PASSED] One page
[17:52:37] [PASSED] More than one page
[17:52:37] [PASSED] Above the allocation limit
[17:52:37] [PASSED] One page, with coherent DMA mappings enabled
[17:52:37] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:52:37] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:52:37] [PASSED] ttm_pool_alloc_order_caching_match
[17:52:37] [PASSED] ttm_pool_alloc_caching_mismatch
[17:52:37] [PASSED] ttm_pool_alloc_order_mismatch
[17:52:37] [PASSED] ttm_pool_free_dma_alloc
[17:52:37] [PASSED] ttm_pool_free_no_dma_alloc
[17:52:37] [PASSED] ttm_pool_fini_basic
[17:52:37] ==================== [PASSED] ttm_pool =====================
[17:52:37] ================ ttm_resource (8 subtests) =================
[17:52:37] ================= ttm_resource_init_basic =================
[17:52:37] [PASSED] Init resource in TTM_PL_SYSTEM
[17:52:37] [PASSED] Init resource in TTM_PL_VRAM
[17:52:37] [PASSED] Init resource in a private placement
[17:52:37] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:52:37] ============= [PASSED] ttm_resource_init_basic =============
[17:52:37] [PASSED] ttm_resource_init_pinned
[17:52:37] [PASSED] ttm_resource_fini_basic
[17:52:37] [PASSED] ttm_resource_manager_init_basic
[17:52:37] [PASSED] ttm_resource_manager_usage_basic
[17:52:37] [PASSED] ttm_resource_manager_set_used_basic
[17:52:37] [PASSED] ttm_sys_man_alloc_basic
[17:52:37] [PASSED] ttm_sys_man_free_basic
[17:52:37] ================== [PASSED] ttm_resource ===================
[17:52:37] =================== ttm_tt (15 subtests) ===================
[17:52:37] ==================== ttm_tt_init_basic ====================
[17:52:37] [PASSED] Page-aligned size
[17:52:37] [PASSED] Extra pages requested
[17:52:37] ================ [PASSED] ttm_tt_init_basic ================
[17:52:37] [PASSED] ttm_tt_init_misaligned
[17:52:37] [PASSED] ttm_tt_fini_basic
[17:52:37] [PASSED] ttm_tt_fini_sg
[17:52:37] [PASSED] ttm_tt_fini_shmem
[17:52:37] [PASSED] ttm_tt_create_basic
[17:52:37] [PASSED] ttm_tt_create_invalid_bo_type
[17:52:37] [PASSED] ttm_tt_create_ttm_exists
[17:52:37] [PASSED] ttm_tt_create_failed
[17:52:37] [PASSED] ttm_tt_destroy_basic
[17:52:37] [PASSED] ttm_tt_populate_null_ttm
[17:52:37] [PASSED] ttm_tt_populate_populated_ttm
[17:52:37] [PASSED] ttm_tt_unpopulate_basic
[17:52:37] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:52:37] [PASSED] ttm_tt_swapin_basic
[17:52:37] ===================== [PASSED] ttm_tt ======================
[17:52:37] =================== ttm_bo (14 subtests) ===================
[17:52:37] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[17:52:37] [PASSED] Cannot be interrupted and sleeps
[17:52:37] [PASSED] Cannot be interrupted, locks straight away
[17:52:37] [PASSED] Can be interrupted, sleeps
[17:52:37] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:52:37] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:52:37] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:52:37] [PASSED] ttm_bo_reserve_double_resv
[17:52:37] [PASSED] ttm_bo_reserve_interrupted
[17:52:37] [PASSED] ttm_bo_reserve_deadlock
[17:52:37] [PASSED] ttm_bo_unreserve_basic
[17:52:37] [PASSED] ttm_bo_unreserve_pinned
[17:52:37] [PASSED] ttm_bo_unreserve_bulk
[17:52:37] [PASSED] ttm_bo_fini_basic
[17:52:37] [PASSED] ttm_bo_fini_shared_resv
[17:52:37] [PASSED] ttm_bo_pin_basic
[17:52:37] [PASSED] ttm_bo_pin_unpin_resource
[17:52:37] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:52:37] ===================== [PASSED] ttm_bo ======================
[17:52:37] ============== ttm_bo_validate (21 subtests) ===============
[17:52:37] ============== ttm_bo_init_reserved_sys_man ===============
[17:52:37] [PASSED] Buffer object for userspace
[17:52:37] [PASSED] Kernel buffer object
[17:52:37] [PASSED] Shared buffer object
[17:52:37] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:52:37] ============== ttm_bo_init_reserved_mock_man ==============
[17:52:37] [PASSED] Buffer object for userspace
[17:52:37] [PASSED] Kernel buffer object
[17:52:37] [PASSED] Shared buffer object
[17:52:37] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:52:37] [PASSED] ttm_bo_init_reserved_resv
[17:52:37] ================== ttm_bo_validate_basic ==================
[17:52:37] [PASSED] Buffer object for userspace
[17:52:37] [PASSED] Kernel buffer object
[17:52:37] [PASSED] Shared buffer object
[17:52:37] ============== [PASSED] ttm_bo_validate_basic ==============
[17:52:37] [PASSED] ttm_bo_validate_invalid_placement
[17:52:37] ============= ttm_bo_validate_same_placement ==============
[17:52:37] [PASSED] System manager
[17:52:37] [PASSED] VRAM manager
[17:52:37] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:52:37] [PASSED] ttm_bo_validate_failed_alloc
[17:52:37] [PASSED] ttm_bo_validate_pinned
[17:52:37] [PASSED] ttm_bo_validate_busy_placement
[17:52:37] ================ ttm_bo_validate_multihop =================
[17:52:37] [PASSED] Buffer object for userspace
[17:52:37] [PASSED] Kernel buffer object
[17:52:37] [PASSED] Shared buffer object
[17:52:37] ============ [PASSED] ttm_bo_validate_multihop =============
[17:52:37] ========== ttm_bo_validate_no_placement_signaled ==========
[17:52:37] [PASSED] Buffer object in system domain, no page vector
[17:52:37] [PASSED] Buffer object in system domain with an existing page vector
[17:52:37] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:52:37] ======== ttm_bo_validate_no_placement_not_signaled ========
[17:52:37] [PASSED] Buffer object for userspace
[17:52:37] [PASSED] Kernel buffer object
[17:52:37] [PASSED] Shared buffer object
[17:52:37] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:52:37] [PASSED] ttm_bo_validate_move_fence_signaled
[17:52:37] ========= ttm_bo_validate_move_fence_not_signaled =========
[17:52:37] [PASSED] Waits for GPU
[17:52:37] [PASSED] Tries to lock straight away
[17:52:37] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:52:37] [PASSED] ttm_bo_validate_happy_evict
[17:52:37] [PASSED] ttm_bo_validate_all_pinned_evict
[17:52:37] [PASSED] ttm_bo_validate_allowed_only_evict
[17:52:37] [PASSED] ttm_bo_validate_deleted_evict
[17:52:37] [PASSED] ttm_bo_validate_busy_domain_evict
[17:52:37] [PASSED] ttm_bo_validate_evict_gutting
[17:52:37] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[17:52:37] ================= [PASSED] ttm_bo_validate =================
[17:52:37] ============================================================
[17:52:37] Testing complete. Ran 101 tests: passed: 101
[17:52:37] Elapsed time: 11.458s total, 1.694s configuring, 9.548s building, 0.181s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ CI.checksparse: warning for CMTG enablement (rev3)
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (14 preceding siblings ...)
2026-02-04 17:52 ` ✓ CI.KUnit: success for CMTG enablement (rev3) Patchwork
@ 2026-02-04 18:08 ` Patchwork
2026-02-04 19:03 ` ✗ Xe.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2026-02-04 18:08 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-xe
== Series Details ==
Series: CMTG enablement (rev3)
URL : https://patchwork.freedesktop.org/series/157663/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 241994730989320c926da9f2d0a5ec80b48f993d
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/dvo_ch7017.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_ch7xxx.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_ivch.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_ns2501.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_sil164.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/dvo_tfp410.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/hsw_ips.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/icl_dsi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_dsi.h):
+drivers/gpu/drm/i915/display/intel_acpi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_atomic.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_audio.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_backlight.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_bios.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_bw.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_casf.c:153:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_casf.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cmtg.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_color.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_colorop.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_color_pipeline.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_combo_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_connector.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_crtc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_crtc_state_dump.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cursor.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cx0_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dbuf_bw.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_debugfs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_device.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_driver.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_display_power.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_map.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_well.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_reset.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_rps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dmc.c:131:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:134:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:137:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:140:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:143:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:146:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:149:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:153:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:154:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:157:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:160:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:163:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:166:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:170:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:174:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:178:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:182:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c:186:1: error: bad constant expression
+drivers/gpu/drm/i915/display/intel_dmc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_aux.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpio_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_link_training.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll_mgr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_mst.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt_common.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_test.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_drrs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_dsi.h):
+drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi_vbt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_encoder.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fb_bo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fbc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_fb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fb_pin.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fdi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fifo_underrun.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_flipq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_frontbuffer.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_global_state.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_gmbus.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hotplug_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_initial_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_link_bw.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_load_detect.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lspcon.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lt_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lvds.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_lock.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_verify.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_opregion.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_overlay.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_panel.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pch_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_refclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pfit.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pipe_crc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_pmdemand.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_quirks.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sdvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sprite.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sprite_uapi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tv.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vblank.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vdsc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vga.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vrr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_prefill.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_scaler.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/skl_universal_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_watermark.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_clock.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_dsi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_dsi_pll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/vlv_sideband.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/gem/i915_gem_pages.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/i915_initial_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/i915_panic.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ Xe.CI.BAT: failure for CMTG enablement (rev3)
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (15 preceding siblings ...)
2026-02-04 18:08 ` ✗ CI.checksparse: warning " Patchwork
@ 2026-02-04 19:03 ` Patchwork
2026-02-04 20:33 ` Patchwork
2026-02-05 5:33 ` ✗ Xe.CI.FULL: " Patchwork
18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2026-02-04 19:03 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 352 bytes --]
== Series Details ==
Series: CMTG enablement (rev3)
URL : https://patchwork.freedesktop.org/series/157663/
State : failure
== Summary ==
ERROR: The runconfig 'xe-4495-241994730989320c926da9f2d0a5ec80b48f993d_BAT' does not exist in the database
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/index.html
[-- Attachment #2: Type: text/html, Size: 917 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ Xe.CI.BAT: failure for CMTG enablement (rev3)
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (16 preceding siblings ...)
2026-02-04 19:03 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2026-02-04 20:33 ` Patchwork
2026-02-05 5:33 ` ✗ Xe.CI.FULL: " Patchwork
18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2026-02-04 20:33 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2474 bytes --]
== Series Details ==
Series: CMTG enablement (rev3)
URL : https://patchwork.freedesktop.org/series/157663/
State : failure
== Summary ==
CI Bug Log - changes from xe-4497-241994730989320c926da9f2d0a5ec80b48f993d_BAT -> xe-pw-157663v3_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-157663v3_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-157663v3_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-157663v3_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@basic-flip-vs-modeset:
- bat-ptl-2: [PASS][1] -> [ABORT][2] +1 other test abort
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/bat-ptl-2/igt@kms_flip@basic-flip-vs-modeset.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/bat-ptl-2/igt@kms_flip@basic-flip-vs-modeset.html
Known issues
------------
Here are the changes found in xe-pw-157663v3_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-modeset:
- bat-lnl-1: [PASS][3] -> [ABORT][4] ([Intel XE#1727] / [Intel XE#2705]) +1 other test abort
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/bat-lnl-1/igt@kms_flip@basic-flip-vs-modeset.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/bat-lnl-1/igt@kms_flip@basic-flip-vs-modeset.html
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
Build changes
-------------
* IGT: IGT_8735 -> IGT_8736
* Linux: xe-4497-241994730989320c926da9f2d0a5ec80b48f993d -> xe-pw-157663v3
IGT_8735: 8735
IGT_8736: 8736
xe-4497-241994730989320c926da9f2d0a5ec80b48f993d: 241994730989320c926da9f2d0a5ec80b48f993d
xe-pw-157663v3: 157663v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/index.html
[-- Attachment #2: Type: text/html, Size: 3087 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards
2026-02-03 13:43 ` [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards Animesh Manna
@ 2026-02-05 5:18 ` Kandpal, Suraj
2026-02-05 8:43 ` Jani Nikula
0 siblings, 1 reply; 35+ messages in thread
From: Kandpal, Suraj @ 2026-02-05 5:18 UTC (permalink / raw)
To: Manna, Animesh, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian, Nikula, Jani, Manna, Animesh,
Nautiyal, Ankit K, Shankar, Uma
> Subject: [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards
>
> Introduce a flag for cmtg. LNL onwards CMTG support will be added.
> Set the flag as per DISPLAY_VER() check.
>
Use Capitalized versions of acronyms unless unavoidable(if you mention it as a part of a function)
both in commit subject and message, this review stands for all patch in series it should be *CMTG
Also please Bspec references to registers, sequences on all patches this makes life very easy to review
This is also a review for all the patches in the series
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 4 ++++
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e6298279dc89..1081615a14fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1569,6 +1569,10 @@ struct intel_crtc { #endif
>
> bool vblank_psr_notify;
> +
> + struct {
> + bool enable;
> + } cmtg;
> };
>
> struct intel_plane_error {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e2fd01d1a1e4..ecf8ed0c0265 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3445,6 +3445,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> const struct drm_display_mode *fixed_mode;
> struct intel_connector *connector = intel_dp->attached_connector;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> int ret = 0, link_bpp_x16;
>
> fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
> @@ -3549,6 +3550,9 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp,
> pipe_config, conn_state);
>
> + if (DISPLAY_VER(display) >= 15 && intel_dp_is_edp(intel_dp))
> + crtc->cmtg.enable = true;
Should be >= 20 since LNL's version was 20.
Also I don't see a point of having this as a variable in intel_crtc this can be checked as a macro or a function
Maybe you have to use intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) instead on intel_dp_is_edp but it should be better option
According to me.
Regards,
Suraj Kandpal
> +
> return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp,
> connector,
> pipe_config);
> }
> --
> 2.29.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select
2026-02-03 13:43 ` [PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select Animesh Manna
@ 2026-02-05 5:25 ` Kandpal, Suraj
0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2026-02-05 5:25 UTC (permalink / raw)
To: Manna, Animesh, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian, Nikula, Jani, Manna, Animesh
> Subject: [PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select
>
> Program CMTG Clk Select.
>
Capitalize the CMTG is commit subject
Add Bspec link for register and sequences you are using
Regards,
Suraj Kandpal
> v2:
> - Correct mask for PHY B. [Jani]
> - Use REG_FIELD_PREP() for enable value. [Dibin]
> - Extend cmtg clock select for xe3plpd. [Dibin]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 22 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cmtg.h | 2 ++
> .../gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 9 ++++++--
> 5 files changed, 38 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..f5364f5a848f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -16,6 +16,7 @@
> #include "intel_display_device.h"
> #include "intel_display_power.h"
> #include "intel_display_regs.h"
> +#include "intel_display_types.h"
>
> /**
> * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +186,24 @@
> void intel_cmtg_sanitize(struct intel_display *display)
>
> intel_cmtg_disable(display, &cmtg_config); }
> +
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> +*crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 clk_sel_clr = 0;
> + u32 clk_sel_set = 0;
> +
> + if (cpu_transcoder == TRANSCODER_A) {
> + clk_sel_clr = CMTG_CLK_SEL_A_MASK;
> + clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
> + }
> +
> + if (cpu_transcoder == TRANSCODER_B) {
> + clk_sel_clr = CMTG_CLK_SEL_B_MASK;
> + clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
> + }
> +
> + if (clk_sel_set)
> + intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set); }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..bef2426b2787 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -7,7 +7,9 @@
> #define __INTEL_CMTG_H__
>
> struct intel_display;
> +struct intel_crtc_state;
>
> +void intel_cmtg_set_clk_select(const struct intel_crtc_state
> +*crtc_state);
> void intel_cmtg_sanitize(struct intel_display *display);
>
> #endif /* __INTEL_CMTG_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 945a35578284..8a767b659a23 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -10,8 +10,10 @@
>
> #define CMTG_CLK_SEL _MMIO(0x46160)
> #define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29)
> +#define CMTG_CLK_SELECT_PHYA_ENABLE
> REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
> #define CMTG_CLK_SEL_A_DISABLED
> REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
> #define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13)
> +#define CMTG_CLK_SELECT_PHYB_ENABLE
> REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x6)
> #define CMTG_CLK_SEL_B_DISABLED
> REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
>
> #define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6a471c021c0e..a88f013e472b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -9,6 +9,7 @@
> #include <drm/drm_print.h>
>
> #include "intel_alpm.h"
> +#include "intel_cmtg.h"
> #include "intel_cx0_phy.h"
> #include "intel_cx0_phy_regs.h"
> #include "intel_display_regs.h"
> @@ -3417,9 +3418,13 @@ void intel_mtl_pll_enable_clock(struct
> intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> if (intel_tc_port_in_tbt_alt_mode(dig_port))
> intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
> +
> + if (crtc->cmtg.enable)
> + intel_cmtg_set_clk_select(crtc_state);
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 04f63bdd0b87..f6c45bf9d0f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -6,6 +6,7 @@
> #include <drm/drm_print.h>
>
> #include "i915_reg.h"
> +#include "intel_cmtg.h"
> #include "intel_cx0_phy.h"
> #include "intel_cx0_phy_regs.h"
> #include "intel_ddi.h"
> @@ -2246,11 +2247,15 @@ void intel_xe3plpd_pll_enable(struct
> intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>
> - if (intel_tc_port_in_tbt_alt_mode(dig_port))
> + if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
> intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
> - else
> + } else {
> intel_lt_phy_pll_enable(encoder, crtc_state);
> + if (crtc->cmtg.enable)
> + intel_cmtg_set_clk_select(crtc_state);
> + }
> }
>
> void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
> --
> 2.29.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* ✗ Xe.CI.FULL: failure for CMTG enablement (rev3)
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
` (17 preceding siblings ...)
2026-02-04 20:33 ` Patchwork
@ 2026-02-05 5:33 ` Patchwork
18 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2026-02-05 5:33 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 62084 bytes --]
== Series Details ==
Series: CMTG enablement (rev3)
URL : https://patchwork.freedesktop.org/series/157663/
State : failure
== Summary ==
CI Bug Log - changes from xe-4497-241994730989320c926da9f2d0a5ec80b48f993d_FULL -> xe-pw-157663v3_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-157663v3_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-157663v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-157663v3_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@xe_fault_injection@vm-create-fail-xe_exec_queue_create_bind:
- shard-bmg: [PASS][1] -> [ABORT][2] +1 other test abort
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-7/igt@xe_fault_injection@vm-create-fail-xe_exec_queue_create_bind.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-9/igt@xe_fault_injection@vm-create-fail-xe_exec_queue_create_bind.html
Known issues
------------
Here are the changes found in xe-pw-157663v3_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_hwmon@hwmon-write:
- shard-bmg: [PASS][3] -> [FAIL][4] ([Intel XE#4665])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-9/igt@intel_hwmon@hwmon-write.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@intel_hwmon@hwmon-write.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#2327])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#1124]) +6 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
- shard-bmg: [PASS][7] -> [SKIP][8] ([Intel XE#2314] / [Intel XE#2894])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-10/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2314] / [Intel XE#2894])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-8/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
* igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
- shard-lnl: NOTRUN -> [SKIP][10] ([Intel XE#1512])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#3432])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#2887]) +8 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_chamelium_color@gamma:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2325])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-10/igt@kms_chamelium_color@gamma.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2252]) +6 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-3/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_color_pipeline@plane-lut3d-green-only@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#6969]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-a-dp-2.html
* igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-dp-2:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#6969] / [Intel XE#7006])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-d-dp-2.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][17] ([Intel XE#1178] / [Intel XE#3304])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-7/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html
* igt@kms_content_protection@type1:
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#3278])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-6/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-offscreen-128x42:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#2320]) +3 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-10/igt@kms_cursor_crc@cursor-offscreen-128x42.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-bmg: [PASS][20] -> [SKIP][21] ([Intel XE#2291]) +2 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-1/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-bmg: NOTRUN -> [DMESG-WARN][22] ([Intel XE#5354])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2286])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#4354])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2244])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-bmg: [PASS][26] -> [SKIP][27] ([Intel XE#2316]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-9/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#2316]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#7179])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-10/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-32bpp-linear-reflect-x.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-lnl: NOTRUN -> [SKIP][30] ([Intel XE#352])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][31] ([Intel XE#651])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#2311]) +11 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#7061]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#4141]) +7 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2312]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#2313]) +15 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@plane-fbc-rte:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#2350])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_frontbuffer_tracking@plane-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][38] ([Intel XE#656]) +2 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#6911])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_panel_fitting@legacy:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#2486]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-4/igt@kms_panel_fitting@legacy.html
* igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#7111] / [Intel XE#7130] / [Intel XE#7131])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html
* igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping@pipe-a-plane-3:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#7130]) +13 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping@pipe-a-plane-3.html
* igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping@pipe-a-plane-5:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#7131])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping@pipe-a-plane-5.html
* igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping@pipe-b-plane-5:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#7111] / [Intel XE#7131])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping@pipe-b-plane-5.html
* igt@kms_plane@pixel-format-y-tiled-modifier:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#7111] / [Intel XE#7130]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-8/igt@kms_plane@pixel-format-y-tiled-modifier.html
* igt@kms_plane_lowres@tiling-4@pipe-a-dp-2:
- shard-bmg: [PASS][46] -> [DMESG-FAIL][47] ([Intel XE#5545]) +1 other test dmesg-fail
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-1/igt@kms_plane_lowres@tiling-4@pipe-a-dp-2.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_plane_lowres@tiling-4@pipe-a-dp-2.html
* igt@kms_plane_lowres@tiling-y:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#2393])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_plane_lowres@tiling-y.html
* igt@kms_pm_backlight@bad-brightness:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#870])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_dc@dc6-psr:
- shard-lnl: NOTRUN -> [ABORT][50] ([Intel XE#2705]) +4 other tests abort
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@kms_pm_dc@dc6-psr.html
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#2392])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [SKIP][52] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-b-edp-1.html
* igt@kms_psr2_sf@psr2-cursor-plane-update-sf@pipe-a-edp-1:
- shard-lnl: [PASS][53] -> [ABORT][54] ([Intel XE#1727] / [Intel XE#2705]) +7 other tests abort
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-2/igt@kms_psr2_sf@psr2-cursor-plane-update-sf@pipe-a-edp-1.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-8/igt@kms_psr2_sf@psr2-cursor-plane-update-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-9/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [ABORT][56] ([Intel XE#1727] / [Intel XE#2705]) +1 other test abort
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-4/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area@pipe-b-edp-1:
- shard-lnl: [PASS][57] -> [INCOMPLETE][58] ([Intel XE#2705]) +2 other tests incomplete
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-5/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area@pipe-b-edp-1.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-1/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area@pipe-b-edp-1.html
* igt@kms_psr2_su@page_flip-p010:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#1406] / [Intel XE#2387])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-7/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-psr-dpms:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +7 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_psr@fbc-psr-dpms.html
* igt@kms_psr@fbc-psr2-dpms:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#1406] / [Intel XE#6703])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_psr@fbc-psr2-dpms.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-10/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-lnl: NOTRUN -> [SKIP][63] ([Intel XE#1127])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-bmg: [PASS][64] -> [SKIP][65] ([Intel XE#1435])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_sharpness_filter@filter-suspend:
- shard-lnl: [PASS][66] -> [ABORT][67] ([Intel XE#2705]) +1 other test abort
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-4/igt@kms_sharpness_filter@filter-suspend.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-8/igt@kms_sharpness_filter@filter-suspend.html
* igt@kms_sharpness_filter@invalid-filter-with-plane:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#6503]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-8/igt@kms_sharpness_filter@invalid-filter-with-plane.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-bmg: NOTRUN -> [SKIP][69] ([Intel XE#1499])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-4/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@xe_eudebug@basic-vm-access-userptr:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#4837]) +2 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-8/igt@xe_eudebug@basic-vm-access-userptr.html
* igt@xe_eudebug@multiple-sessions:
- shard-lnl: NOTRUN -> [SKIP][71] ([Intel XE#4837])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-7/igt@xe_eudebug@multiple-sessions.html
* igt@xe_eudebug_online@pagefault-read-stress:
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#6665] / [Intel XE#6681])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-10/igt@xe_eudebug_online@pagefault-read-stress.html
* igt@xe_evict@evict-beng-cm-threads-large-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][73] ([Intel XE#688])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-5/igt@xe_evict@evict-beng-cm-threads-large-multi-vm.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: [PASS][74] -> [INCOMPLETE][75] ([Intel XE#6321])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-7/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_exec_basic@multigpu-once-basic-defer-bind:
- shard-bmg: NOTRUN -> [SKIP][76] ([Intel XE#2322]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-4/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
* igt@xe_exec_fault_mode@many-multi-queue-userptr-prefetch:
- shard-lnl: NOTRUN -> [SKIP][77] ([Intel XE#7136])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-1/igt@xe_exec_fault_mode@many-multi-queue-userptr-prefetch.html
* igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-imm:
- shard-bmg: NOTRUN -> [SKIP][78] ([Intel XE#7136]) +7 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-imm.html
* igt@xe_exec_multi_queue@one-queue-close-fd-smem:
- shard-lnl: NOTRUN -> [SKIP][79] ([Intel XE#6874]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@xe_exec_multi_queue@one-queue-close-fd-smem.html
* igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem:
- shard-bmg: NOTRUN -> [SKIP][80] ([Intel XE#6874]) +13 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-9/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem.html
* igt@xe_exec_system_allocator@many-large-execqueues-new-bo-map-nomemset:
- shard-lnl: [PASS][81] -> [ABORT][82] ([Intel XE#1727]) +8 other tests abort
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-3/igt@xe_exec_system_allocator@many-large-execqueues-new-bo-map-nomemset.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-1/igt@xe_exec_system_allocator@many-large-execqueues-new-bo-map-nomemset.html
* igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset:
- shard-bmg: NOTRUN -> [SKIP][83] ([Intel XE#6703]) +11 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset.html
* igt@xe_exec_system_allocator@many-mmap-shared:
- shard-lnl: NOTRUN -> [ABORT][84] ([Intel XE#1727])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-4/igt@xe_exec_system_allocator@many-mmap-shared.html
* igt@xe_exec_system_allocator@once-large-malloc-bo-unmap:
- shard-bmg: [PASS][85] -> [ABORT][86] ([Intel XE#7169])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-4/igt@xe_exec_system_allocator@once-large-malloc-bo-unmap.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-4/igt@xe_exec_system_allocator@once-large-malloc-bo-unmap.html
* igt@xe_exec_system_allocator@once-large-mmap-new-huge-nomemset:
- shard-lnl: NOTRUN -> [SKIP][87] ([Intel XE#4943]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-5/igt@xe_exec_system_allocator@once-large-mmap-new-huge-nomemset.html
* igt@xe_exec_system_allocator@once-mmap-race-nomemset:
- shard-bmg: [PASS][88] -> [SKIP][89] ([Intel XE#6557] / [Intel XE#6703]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@xe_exec_system_allocator@once-mmap-race-nomemset.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_system_allocator@once-mmap-race-nomemset.html
* igt@xe_exec_system_allocator@threads-many-execqueues-mmap:
- shard-bmg: [PASS][90] -> [SKIP][91] ([Intel XE#6703]) +62 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-7/igt@xe_exec_system_allocator@threads-many-execqueues-mmap.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-execqueues-mmap.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge:
- shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#4943]) +14 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-9/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-new-huge.html
* igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-invalidate:
- shard-bmg: NOTRUN -> [SKIP][93] ([Intel XE#7138]) +3 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-invalidate.html
* igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate:
- shard-lnl: NOTRUN -> [SKIP][94] ([Intel XE#7138]) +1 other test skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-8/igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate.html
* igt@xe_multigpu_svm@mgpu-pagefault-conflict:
- shard-bmg: NOTRUN -> [SKIP][95] ([Intel XE#6964]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@xe_multigpu_svm@mgpu-pagefault-conflict.html
* igt@xe_pm@s3-d3cold-basic-exec:
- shard-bmg: NOTRUN -> [SKIP][96] ([Intel XE#2284])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-3/igt@xe_pm@s3-d3cold-basic-exec.html
* igt@xe_pm@vram-d3cold-threshold:
- shard-bmg: NOTRUN -> [SKIP][97] ([Intel XE#579])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@xe_pm@vram-d3cold-threshold.html
* igt@xe_pxp@pxp-termination-key-update-post-rpm:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#4733])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-7/igt@xe_pxp@pxp-termination-key-update-post-rpm.html
* igt@xe_query@multigpu-query-invalid-extension:
- shard-bmg: NOTRUN -> [SKIP][99] ([Intel XE#944]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@xe_query@multigpu-query-invalid-extension.html
#### Possible fixes ####
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-bmg: [DMESG-FAIL][100] ([Intel XE#1727]) -> [PASS][101] +1 other test pass
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-bmg: [SKIP][102] ([Intel XE#2291]) -> [PASS][103] +1 other test pass
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-10/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-bmg: [DMESG-WARN][104] ([Intel XE#5354]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-2/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-bmg: [SKIP][106] ([Intel XE#2316]) -> [PASS][107] +5 other tests pass
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-10/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-2:
- shard-bmg: [SKIP][108] -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-3/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-2.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-3/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-2.html
* igt@kms_hdr@static-toggle-suspend:
- shard-bmg: [SKIP][110] ([Intel XE#1503]) -> [PASS][111] +1 other test pass
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_hdr@static-toggle-suspend.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-7/igt@kms_hdr@static-toggle-suspend.html
* igt@xe_module_load@load:
- shard-lnl: ([PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [SKIP][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136]) ([Intel XE#378]) -> ([PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-2/igt@xe_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-1/igt@xe_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-3/igt@xe_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-8/igt@xe_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-6/igt@xe_module_load@load.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-7/igt@xe_module_load@load.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-3/igt@xe_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-3/igt@xe_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-3/igt@xe_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-4/igt@xe_module_load@load.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-7/igt@xe_module_load@load.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-5/igt@xe_module_load@load.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-4/igt@xe_module_load@load.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-8/igt@xe_module_load@load.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-8/igt@xe_module_load@load.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-1/igt@xe_module_load@load.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-4/igt@xe_module_load@load.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-7/igt@xe_module_load@load.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-5/igt@xe_module_load@load.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-5/igt@xe_module_load@load.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-2/igt@xe_module_load@load.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-2/igt@xe_module_load@load.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-1/igt@xe_module_load@load.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-1/igt@xe_module_load@load.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-7/igt@xe_module_load@load.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-1/igt@xe_module_load@load.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@xe_module_load@load.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-8/igt@xe_module_load@load.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@xe_module_load@load.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@xe_module_load@load.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@xe_module_load@load.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-5/igt@xe_module_load@load.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-5/igt@xe_module_load@load.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-5/igt@xe_module_load@load.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-8/igt@xe_module_load@load.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-8/igt@xe_module_load@load.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-5/igt@xe_module_load@load.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-6/igt@xe_module_load@load.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-6/igt@xe_module_load@load.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-4/igt@xe_module_load@load.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-7/igt@xe_module_load@load.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-7/igt@xe_module_load@load.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-7/igt@xe_module_load@load.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-1/igt@xe_module_load@load.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-2/igt@xe_module_load@load.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-4/igt@xe_module_load@load.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-1/igt@xe_module_load@load.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-2/igt@xe_module_load@load.html
* igt@xe_pm@d3hot-multiple-execs:
- shard-lnl: [TIMEOUT][160] ([Intel XE#7180]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-4/igt@xe_pm@d3hot-multiple-execs.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-1/igt@xe_pm@d3hot-multiple-execs.html
#### Warnings ####
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-bmg: [SKIP][162] ([Intel XE#2370]) -> [SKIP][163] ([Intel XE#6703])
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-9/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-bmg: [SKIP][164] ([Intel XE#1124]) -> [SKIP][165] ([Intel XE#6703])
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-9/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs:
- shard-bmg: [SKIP][166] ([Intel XE#2887]) -> [SKIP][167] ([Intel XE#6703])
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-10/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs.html
* igt@kms_chamelium_audio@dp-audio:
- shard-bmg: [SKIP][168] ([Intel XE#2252]) -> [SKIP][169] ([Intel XE#6703])
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-10/igt@kms_chamelium_audio@dp-audio.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_color@ctm-limited-range:
- shard-bmg: [SKIP][170] ([Intel XE#2325]) -> [SKIP][171] ([Intel XE#6703])
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-10/igt@kms_chamelium_color@ctm-limited-range.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_chamelium_color@ctm-limited-range.html
* igt@kms_content_protection@atomic-dpms-hdcp14:
- shard-bmg: [FAIL][172] ([Intel XE#3304]) -> [SKIP][173] ([Intel XE#7194])
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-4/igt@kms_content_protection@atomic-dpms-hdcp14.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_content_protection@atomic-dpms-hdcp14.html
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [SKIP][174] ([Intel XE#2341]) -> [FAIL][175] ([Intel XE#1178] / [Intel XE#3304])
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_content_protection@lic-type-0.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-7/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@srm:
- shard-bmg: [FAIL][176] ([Intel XE#1178] / [Intel XE#3304]) -> [SKIP][177] ([Intel XE#2341])
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-2/igt@kms_content_protection@srm.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-lnl: [SKIP][178] ([Intel XE#1424]) -> [ABORT][179] ([Intel XE#1727]) +1 other test abort
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-8/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-1/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [FAIL][180] ([Intel XE#4633]) -> [FAIL][181] ([Intel XE#6715])
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-bmg: [SKIP][182] ([Intel XE#2316]) -> [SKIP][183] ([Intel XE#6703])
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][184] ([Intel XE#2311]) -> [SKIP][185] ([Intel XE#2312]) +8 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt:
- shard-bmg: [SKIP][186] ([Intel XE#2311]) -> [SKIP][187] ([Intel XE#6703]) +1 other test skip
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][188] ([Intel XE#4141]) -> [SKIP][189] ([Intel XE#2312]) +3 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
- shard-bmg: [SKIP][190] ([Intel XE#2312]) -> [SKIP][191] ([Intel XE#6703])
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][192] ([Intel XE#4141]) -> [SKIP][193] ([Intel XE#6703]) +1 other test skip
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][194] ([Intel XE#2312]) -> [SKIP][195] ([Intel XE#4141]) +2 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render:
- shard-bmg: [SKIP][196] ([Intel XE#2312]) -> [SKIP][197] ([Intel XE#2311]) +10 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt:
- shard-bmg: [SKIP][198] ([Intel XE#2312]) -> [SKIP][199] ([Intel XE#2313]) +9 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
- shard-bmg: [SKIP][200] ([Intel XE#2313]) -> [SKIP][201] ([Intel XE#6703]) +2 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][202] ([Intel XE#2313]) -> [SKIP][203] ([Intel XE#2312]) +9 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][204] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][205] ([Intel XE#6703])
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-c:
- shard-lnl: [SKIP][206] ([Intel XE#6886]) -> [ABORT][207] ([Intel XE#1727]) +1 other test abort
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-c.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-c.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
- shard-bmg: [SKIP][208] ([Intel XE#1406] / [Intel XE#1489]) -> [SKIP][209] ([Intel XE#1406] / [Intel XE#6703])
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-9/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
- shard-lnl: [SKIP][210] ([Intel XE#1406] / [Intel XE#2893]) -> [ABORT][211] ([Intel XE#2705]) +1 other test abort
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-2/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-5/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
- shard-lnl: [SKIP][212] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608]) -> [ABORT][213] ([Intel XE#2705])
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-4/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf@pipe-a-edp-1:
- shard-lnl: [SKIP][214] ([Intel XE#1406] / [Intel XE#4608]) -> [ABORT][215] ([Intel XE#2705])
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-lnl-4/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf@pipe-a-edp-1.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf@pipe-a-edp-1.html
* igt@kms_psr@pr-sprite-plane-onoff:
- shard-bmg: [SKIP][216] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) -> [SKIP][217] ([Intel XE#1406] / [Intel XE#6703])
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@kms_psr@pr-sprite-plane-onoff.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_psr@pr-sprite-plane-onoff.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][218] ([Intel XE#2509]) -> [SKIP][219] ([Intel XE#2426])
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-bmg: [SKIP][220] ([Intel XE#1499]) -> [SKIP][221] ([Intel XE#6703])
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-7/igt@kms_vrr@seamless-rr-switch-vrr.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@xe_eudebug_online@set-breakpoint-faultable:
- shard-bmg: [SKIP][222] ([Intel XE#4837] / [Intel XE#6665]) -> [SKIP][223] ([Intel XE#6703])
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-10/igt@xe_eudebug_online@set-breakpoint-faultable.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_eudebug_online@set-breakpoint-faultable.html
* igt@xe_exec_basic@multigpu-once-null-rebind:
- shard-bmg: [SKIP][224] ([Intel XE#2322]) -> [SKIP][225] ([Intel XE#6703])
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-4/igt@xe_exec_basic@multigpu-once-null-rebind.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_basic@multigpu-once-null-rebind.html
* igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race:
- shard-bmg: [SKIP][226] ([Intel XE#7136]) -> [SKIP][227] ([Intel XE#6703]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-10/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate:
- shard-bmg: [ABORT][228] ([Intel XE#7169]) -> [SKIP][229] ([Intel XE#7136])
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-9/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-1/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate.html
* igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-dyn-priority:
- shard-bmg: [SKIP][230] ([Intel XE#6874]) -> [SKIP][231] ([Intel XE#6703]) +2 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-10/igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-dyn-priority.html
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-dyn-priority.html
* igt@xe_exec_system_allocator@process-many-mmap-huge-nomemset:
- shard-bmg: [SKIP][232] ([Intel XE#4943]) -> [SKIP][233] ([Intel XE#6703]) +2 other tests skip
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-9/igt@xe_exec_system_allocator@process-many-mmap-huge-nomemset.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_system_allocator@process-many-mmap-huge-nomemset.html
* igt@xe_exec_threads@threads-multi-queue-mixed-rebind:
- shard-bmg: [SKIP][234] ([Intel XE#7138]) -> [SKIP][235] ([Intel XE#6703]) +1 other test skip
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-mixed-rebind.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-rebind.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-bmg: [ABORT][236] ([Intel XE#5466] / [Intel XE#6652]) -> [ABORT][237] ([Intel XE#5466])
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
* igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs:
- shard-bmg: [FAIL][238] ([Intel XE#5937]) -> [SKIP][239] ([Intel XE#6703])
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4497-241994730989320c926da9f2d0a5ec80b48f993d/shard-bmg-7/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/shard-bmg-2/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2350
[Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4665
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
[Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
[Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6681]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6681
[Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
[Intel XE#6715]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6715
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
[Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7111]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7111
[Intel XE#7130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7130
[Intel XE#7131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7131
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7169]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7169
[Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
[Intel XE#7180]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7180
[Intel XE#7194]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7194
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* IGT: IGT_8735 -> IGT_8736
* Linux: xe-4497-241994730989320c926da9f2d0a5ec80b48f993d -> xe-pw-157663v3
IGT_8735: 8735
IGT_8736: 8736
xe-4497-241994730989320c926da9f2d0a5ec80b48f993d: 241994730989320c926da9f2d0a5ec80b48f993d
xe-pw-157663v3: 157663v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v3/index.html
[-- Attachment #2: Type: text/html, Size: 73877 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg
2026-02-03 13:44 ` [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg Animesh Manna
@ 2026-02-05 5:35 ` Kandpal, Suraj
2026-02-05 8:47 ` Jani Nikula
1 sibling, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2026-02-05 5:35 UTC (permalink / raw)
To: Manna, Animesh, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian, Nikula, Jani, Manna, Animesh,
Shankar, Uma
> Subject: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg
>
* CMTG
> Timing registers are separate for CMTG, read transcoder register and program
> cmtg transcoder with those values.
*CMTG
>
> v2:
> - Use sw state instead of reading directly from hardware. [Jani]
> - Move set_timing later after encoder enable. [Dibin]
Why also I don't see this comment from Dibin anywhere
Bspec Links
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 24 +++++++++
> drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
> .../gpu/drm/i915/display/intel_cmtg_regs.h | 7 +++
> drivers/gpu/drm/i915/display/intel_display.c | 51 ++++++++++++-------
> .../drm/i915/display/intel_display_types.h | 2 +
> 5 files changed, 67 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index f5364f5a848f..4220eeece07f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -207,3 +207,27 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
> if (clk_sel_set)
> intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set); }
> +
> +static void intel_cmtg_set_timings(const struct intel_crtc_state
> +*crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.htotal);
> + intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.hblank);
> + intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder), crtc-
> >cmtg.hsync);
> + intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.vtotal);
> + intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.vblank);
> + intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> +crtc->cmtg.vsync); }
> +
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) {
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + if (cpu_transcoder != TRANSCODER_A && cpu_transcoder !=
> TRANSCODER_B)
> + return;
> +
> + intel_cmtg_set_timings(crtc_state);
I don't like the idea of this being called here this belongs at intel_set_transcoder_timings with others
Unless Bspec says otherwise.
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index bef2426b2787..b2bb60d160fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -9,6 +9,7 @@
> struct intel_display;
> struct intel_crtc_state;
>
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_sanitize(struct intel_display *display);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 8a767b659a23..eb24827d22f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -20,4 +20,11 @@
> #define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
> #define CMTG_ENABLE REG_BIT(31)
>
> +#define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) *
> 0x100)
> +#define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) *
> 0x100)
> +#define TRANS_HSYNC_CMTG(id) _MMIO(0x6F008 + (id) *
> 0x100)
> +#define TRANS_VTOTAL_CMTG(id) _MMIO(0x6F00C + (id) *
> 0x100)
> +#define TRANS_VBLANK_CMTG(id) _MMIO(0x6F010 + (id) *
> 0x100)
> +#define TRANS_VSYNC_CMTG(id) _MMIO(0x6F014 + (id) *
> 0x100)
> +
> #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 564d11925af3..976af9eb3c3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -62,6 +62,7 @@
> #include "intel_casf.h"
> #include "intel_cdclk.h"
> #include "intel_clock_gating.h"
> +#include "intel_cmtg.h"
> #include "intel_color.h"
> #include "intel_crt.h"
> #include "intel_crtc.h"
> @@ -1722,6 +1723,9 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> intel_crtc_wait_for_next_vblank(wa_crtc);
> }
> }
> +
> + if (crtc->cmtg.enable)
> + intel_cmtg_enable(new_crtc_state);
I would rather have you have a separate function which you be the last patch that finally calls intel_cmtg_enable so that you don't enable
a half baked feature in between the patch series. Complete all the parts of your code and join them at last with the intel_cmtg_enable
> }
>
> static void ilk_crtc_disable(struct intel_atomic_state *state, @@ -2654,6
> +2658,8 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
> const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> int vsyncshift = 0;
> + u32 trans_htotal_val, trans_hblank_val, trans_hsync_val;
> + u32 trans_vtotal_val, trans_vblank_val, trans_vsync_val;
>
> drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
>
> @@ -2702,15 +2708,15 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
> TRANS_VSYNCSHIFT(display, cpu_transcoder),
> vsyncshift);
>
> - intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> - HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> - HTOTAL(adjusted_mode->crtc_htotal - 1));
> - intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> - HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> - HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> - intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> - HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> - HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> + trans_htotal_val = HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> + HTOTAL(adjusted_mode->crtc_htotal - 1);
> + trans_hblank_val = HBLANK_START(adjusted_mode-
> >crtc_hblank_start - 1) |
> + HBLANK_END(adjusted_mode->crtc_hblank_end -
> 1);
> + trans_hsync_val = HSYNC_START(adjusted_mode->crtc_hsync_start -
> 1) |
> + HSYNC_END(adjusted_mode->crtc_hsync_end - 1);
> + intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> trans_htotal_val);
> + intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> trans_hblank_val);
> + intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> +trans_hsync_val);
>
> /*
> * For platforms that always use VRR Timing Generator, the
> VTOTAL.Vtotal @@ -2721,15 +2727,15 @@ static void
> intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> if (intel_vrr_always_use_vrr_tg(display))
> crtc_vtotal = 1;
>
> - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> - VACTIVE(crtc_vdisplay - 1) |
> - VTOTAL(crtc_vtotal - 1));
> - intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> - VBLANK_START(crtc_vblank_start - 1) |
> - VBLANK_END(crtc_vblank_end - 1));
> - intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> - VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> - VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> + trans_vtotal_val = VACTIVE(crtc_vdisplay - 1) |
> + VTOTAL(crtc_vtotal - 1);
> + trans_vblank_val = VBLANK_START(crtc_vblank_start - 1) |
> + VBLANK_END(crtc_vblank_end - 1);
> + trans_vsync_val = VSYNC_START(adjusted_mode->crtc_vsync_start -
> 1) |
> + VSYNC_END(adjusted_mode->crtc_vsync_end - 1);
> + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> trans_vtotal_val);
> + intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> trans_vblank_val);
> + intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> +trans_vsync_val);
Rather than this pass adjusted mode to intel_cmtg_set_timing and do that calculation there
>
> /* Workaround: when the EDP input selection is B, the VTOTAL_B
> must be
> * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This
> is @@ -2753,6 +2759,15 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
> intel_de_write(display,
> DP_MIN_HBLANK_CTL(cpu_transcoder),
> crtc_state->min_hblank);
> }
> +
> + if (crtc->cmtg.enable) {
> + crtc->cmtg.htotal = trans_htotal_val;
> + crtc->cmtg.hblank = trans_hblank_val;
> + crtc->cmtg.hsync = trans_hsync_val;
> + crtc->cmtg.vtotal = trans_vtotal_val;
> + crtc->cmtg.vblank = trans_vblank_val;
> + crtc->cmtg.vsync = trans_vsync_val;
> + }
> }
If my above advice is taken this is not needed
>
> static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state
> *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1081615a14fb..defb54dd0bbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1572,6 +1572,8 @@ struct intel_crtc {
>
> struct {
> bool enable;
> + u32 htotal, hblank, hsync;
> + u32 vtotal, vblank, vsync;
Again this also wont be needed then
Regards,
Suraj Kandpal
> } cmtg;
> };
>
> --
> 2.29.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards
2026-02-05 5:18 ` Kandpal, Suraj
@ 2026-02-05 8:43 ` Jani Nikula
0 siblings, 0 replies; 35+ messages in thread
From: Jani Nikula @ 2026-02-05 8:43 UTC (permalink / raw)
To: Kandpal, Suraj, Manna, Animesh, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian, Manna, Animesh, Nautiyal, Ankit K,
Shankar, Uma
On Thu, 05 Feb 2026, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> Subject: [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards
>>
>> Introduce a flag for cmtg. LNL onwards CMTG support will be added.
>> Set the flag as per DISPLAY_VER() check.
>>
>
> Use Capitalized versions of acronyms unless unavoidable(if you mention it as a part of a function)
> both in commit subject and message, this review stands for all patch in series it should be *CMTG
>
> Also please Bspec references to registers, sequences on all patches this makes life very easy to review
> This is also a review for all the patches in the series
>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display_types.h | 4 ++++
>> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++
>> 2 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index e6298279dc89..1081615a14fb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1569,6 +1569,10 @@ struct intel_crtc { #endif
>>
>> bool vblank_psr_notify;
>> +
>> + struct {
>> + bool enable;
>> + } cmtg;
>> };
>>
>> struct intel_plane_error {
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index e2fd01d1a1e4..ecf8ed0c0265 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -3445,6 +3445,7 @@ intel_dp_compute_config(struct intel_encoder
>> *encoder,
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> const struct drm_display_mode *fixed_mode;
>> struct intel_connector *connector = intel_dp->attached_connector;
>> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>> int ret = 0, link_bpp_x16;
>>
>> fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
>> @@ -3549,6 +3550,9 @@ intel_dp_compute_config(struct intel_encoder
>> *encoder,
>> intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
>> intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp,
>> pipe_config, conn_state);
>>
>> + if (DISPLAY_VER(display) >= 15 && intel_dp_is_edp(intel_dp))
>> + crtc->cmtg.enable = true;
>
> Should be >= 20 since LNL's version was 20.
> Also I don't see a point of having this as a variable in intel_crtc this can be checked as a macro or a function
Yeah, compute config should not modify anything but the crtc state.
BR,
Jani.
> Maybe you have to use intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) instead on intel_dp_is_edp but it should be better option
> According to me.
>
> Regards,
> Suraj Kandpal
>
>> +
>> return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp,
>> connector,
>> pipe_config);
>> }
>> --
>> 2.29.0
>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg
2026-02-03 13:44 ` [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg Animesh Manna
2026-02-05 5:35 ` Kandpal, Suraj
@ 2026-02-05 8:47 ` Jani Nikula
2026-02-06 5:50 ` Manna, Animesh
1 sibling, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2026-02-05 8:47 UTC (permalink / raw)
To: Animesh Manna, intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, Animesh Manna
On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> Timing registers are separate for CMTG, read transcoder register
> and program cmtg transcoder with those values.
>
> v2:
> - Use sw state instead of reading directly from hardware. [Jani]
> - Move set_timing later after encoder enable. [Dibin]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 24 +++++++++
> drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
> .../gpu/drm/i915/display/intel_cmtg_regs.h | 7 +++
> drivers/gpu/drm/i915/display/intel_display.c | 51 ++++++++++++-------
> .../drm/i915/display/intel_display_types.h | 2 +
> 5 files changed, 67 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index f5364f5a848f..4220eeece07f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -207,3 +207,27 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
> if (clk_sel_set)
> intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
> }
> +
> +static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder), crtc->cmtg.htotal);
> + intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder), crtc->cmtg.hblank);
> + intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder), crtc->cmtg.hsync);
> + intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc->cmtg.vtotal);
> + intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc->cmtg.vblank);
> + intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder), crtc->cmtg.vsync);
> +}
> +
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
> +{
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + if (cpu_transcoder != TRANSCODER_A && cpu_transcoder != TRANSCODER_B)
> + return;
> +
> + intel_cmtg_set_timings(crtc_state);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index bef2426b2787..b2bb60d160fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -9,6 +9,7 @@
> struct intel_display;
> struct intel_crtc_state;
>
> +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_sanitize(struct intel_display *display);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 8a767b659a23..eb24827d22f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -20,4 +20,11 @@
> #define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
> #define CMTG_ENABLE REG_BIT(31)
>
> +#define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) * 0x100)
What is id? If it's a transcoder, please use trans for the param name.
> +#define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) * 0x100)
> +#define TRANS_HSYNC_CMTG(id) _MMIO(0x6F008 + (id) * 0x100)
> +#define TRANS_VTOTAL_CMTG(id) _MMIO(0x6F00C + (id) * 0x100)
> +#define TRANS_VBLANK_CMTG(id) _MMIO(0x6F010 + (id) * 0x100)
> +#define TRANS_VSYNC_CMTG(id) _MMIO(0x6F014 + (id) * 0x100)
> +
> #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 564d11925af3..976af9eb3c3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -62,6 +62,7 @@
> #include "intel_casf.h"
> #include "intel_cdclk.h"
> #include "intel_clock_gating.h"
> +#include "intel_cmtg.h"
> #include "intel_color.h"
> #include "intel_crt.h"
> #include "intel_crtc.h"
> @@ -1722,6 +1723,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
> intel_crtc_wait_for_next_vblank(wa_crtc);
> }
> }
> +
> + if (crtc->cmtg.enable)
> + intel_cmtg_enable(new_crtc_state);
> }
>
> static void ilk_crtc_disable(struct intel_atomic_state *state,
> @@ -2654,6 +2658,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> int vsyncshift = 0;
> + u32 trans_htotal_val, trans_hblank_val, trans_hsync_val;
> + u32 trans_vtotal_val, trans_vblank_val, trans_vsync_val;
>
> drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
>
> @@ -2702,15 +2708,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> TRANS_VSYNCSHIFT(display, cpu_transcoder),
> vsyncshift);
>
> - intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> - HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> - HTOTAL(adjusted_mode->crtc_htotal - 1));
> - intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> - HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> - HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> - intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> - HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> - HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> + trans_htotal_val = HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> + HTOTAL(adjusted_mode->crtc_htotal - 1);
> + trans_hblank_val = HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> + HBLANK_END(adjusted_mode->crtc_hblank_end - 1);
> + trans_hsync_val = HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> + HSYNC_END(adjusted_mode->crtc_hsync_end - 1);
> + intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), trans_htotal_val);
> + intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), trans_hblank_val);
> + intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), trans_hsync_val);
>
> /*
> * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> @@ -2721,15 +2727,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> if (intel_vrr_always_use_vrr_tg(display))
> crtc_vtotal = 1;
>
> - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> - VACTIVE(crtc_vdisplay - 1) |
> - VTOTAL(crtc_vtotal - 1));
> - intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> - VBLANK_START(crtc_vblank_start - 1) |
> - VBLANK_END(crtc_vblank_end - 1));
> - intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> - VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> - VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> + trans_vtotal_val = VACTIVE(crtc_vdisplay - 1) |
> + VTOTAL(crtc_vtotal - 1);
> + trans_vblank_val = VBLANK_START(crtc_vblank_start - 1) |
> + VBLANK_END(crtc_vblank_end - 1);
> + trans_vsync_val = VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> + VSYNC_END(adjusted_mode->crtc_vsync_end - 1);
> + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), trans_vtotal_val);
> + intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), trans_vblank_val);
> + intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), trans_vsync_val);
>
> /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
> * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
> @@ -2753,6 +2759,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
> crtc_state->min_hblank);
> }
> +
> + if (crtc->cmtg.enable) {
> + crtc->cmtg.htotal = trans_htotal_val;
> + crtc->cmtg.hblank = trans_hblank_val;
> + crtc->cmtg.hsync = trans_hsync_val;
> + crtc->cmtg.vtotal = trans_vtotal_val;
> + crtc->cmtg.vblank = trans_vblank_val;
> + crtc->cmtg.vsync = trans_vsync_val;
> + }
> }
>
> static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1081615a14fb..defb54dd0bbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1572,6 +1572,8 @@ struct intel_crtc {
>
> struct {
> bool enable;
> + u32 htotal, hblank, hsync;
> + u32 vtotal, vblank, vsync;
Why are these stored in the crtc?
> } cmtg;
> };
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl
2026-02-03 13:44 ` [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl Animesh Manna
@ 2026-02-05 8:50 ` Jani Nikula
2026-02-06 5:52 ` Manna, Animesh
0 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2026-02-05 8:50 UTC (permalink / raw)
To: Animesh Manna, intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, Animesh Manna
On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> Enable CMTG through control register.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 3af4aefc760e..f7364c7408d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -244,6 +244,19 @@ static void intel_cpu_cmtg_transcoder_set_m_n(const struct intel_crtc_state *crt
> intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
> }
>
> +static void intel_cmtg_ctl_enable(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 val = 0;
> +
> + val = intel_de_read(display, TRANS_CMTG_CTL(cpu_transcoder));
> +
> + val |= CMTG_ENABLE;
> +
> + intel_de_write(display, TRANS_CMTG_CTL(cpu_transcoder), val);
This is just a single line intel_de_rmw().
> +}
> +
> void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> @@ -261,4 +274,7 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
>
> /* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
> intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
> +
> + /* Program Enable Cmtg */
> + intel_cmtg_ctl_enable(crtc_state);
If there's intel_de_rmw() before, why is this a function?
> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode
2026-02-03 13:44 ` [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode Animesh Manna
@ 2026-02-05 8:53 ` Jani Nikula
2026-02-06 5:56 ` Manna, Animesh
0 siblings, 1 reply; 35+ messages in thread
From: Jani Nikula @ 2026-02-05 8:53 UTC (permalink / raw)
To: Animesh Manna, intel-gfx, intel-xe
Cc: dibin.moolakadan.subrahmanian, Animesh Manna
On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
>
> Wait for CMTG_SYNC_TO_PORT bit clear in cmtg enable sequence
> and then enable secondary mode for cmtg.
>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index f7364c7408d5..d1ec9b79cef2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -277,4 +277,18 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
>
> /* Program Enable Cmtg */
> intel_cmtg_ctl_enable(crtc_state);
> +
> + if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
> + CMTG_SYNC_TO_PORT, 50)) {
> + drm_WARN(display->drm, 1, "CMTG:%d enable timeout\n", cpu_transcoder);
> + return;
> + }
This should be part of the previous patch, right?
> +
> + /*
> + * eDP transcoder registers as secondary to CMTG by setting
> + * TRANS_DDI_FUNC_CTL2[CMTG Secondary Mode].
What does this even mean?
> + */
> + intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
> +
> + drm_dbg_kms(display->drm, "CMTG:%d enabled\n", cpu_transcoder);
See transcoder_name().
> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg
2026-02-03 13:44 ` [PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg Animesh Manna
@ 2026-02-06 2:54 ` Kandpal, Suraj
0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2026-02-06 2:54 UTC (permalink / raw)
To: Manna, Animesh, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian, Nikula, Jani, Manna, Animesh,
Nautiyal, Ankit K, Shankar, Uma, Golani, Mitulkumar Ajitkumar
> Subject: [PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg
* CMTG
* VRR
>
> Enable vrr if it is enabled on cmtg registers.
*VRR
* CMTG
>
> v2: Use sw state instead of reading from hardware. [Jani]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 12 ++++++++++++
> drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 5 +++++
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++
> 4 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 4220eeece07f..26adf70cdd00 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -17,6 +17,7 @@
> #include "intel_display_power.h"
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> +#include "intel_vrr.h"
>
> /**
> * DOC: Common Primary Timing Generator (CMTG) @@ -220,6 +221,17 @@
> static void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state)
> intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.vtotal);
> intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.vblank);
> intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder), crtc-
> >cmtg.vsync);
> +
> + if (intel_vrr_possible(crtc_state) &&
> intel_vrr_always_use_vrr_tg(display)) {
> + intel_de_write(display,
> TRANS_VRR_VMIN_CMTG(cpu_transcoder),
> + crtc_state->vrr.vmin - 1);
> + intel_de_write(display,
> TRANS_VRR_VMAX_CMTG(cpu_transcoder),
> + crtc_state->vrr.vmax - 1);
> + intel_de_write(display,
> TRANS_VRR_FLIPLINE_CMTG(cpu_transcoder),
> + crtc_state->vrr.flipline - 1);
IMHO These three need to be called from
intel_vrr_set_fixed_rr_timings()
you can wrap this up in a function of its own called intel_cmtg_set_fixed_rr_timings()
> + intel_de_write(display,
> TRANS_VRR_CTL_CMTG(cpu_transcoder),
> + crtc->cmtg.vrr_ctl);
This needs to directly be called from intel_vrr_tg_enable
Which also saves you from having you save the variable in intel_crtc
Which shouldn't be there in the first place (maybe in crtc_state if needed but I don't see the real need of having it at all.
Regards,
Suraj Kandpal
> + }
> }
>
> void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index eb24827d22f5..eab90415d0da 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -27,4 +27,9 @@
> #define TRANS_VBLANK_CMTG(id) _MMIO(0x6F010 + (id) *
> 0x100)
> #define TRANS_VSYNC_CMTG(id) _MMIO(0x6F014 + (id) *
> 0x100)
>
> +#define TRANS_VRR_CTL_CMTG(id) _MMIO(0x6F420 + (id) *
> 0x100)
> +#define TRANS_VRR_VMAX_CMTG(id) _MMIO(0x6F424 + (id) *
> 0x100)
> +#define TRANS_VRR_VMIN_CMTG(id) _MMIO(0x6F434 + (id) *
> 0x100)
> +#define TRANS_VRR_FLIPLINE_CMTG(id) _MMIO(0x6F438 + (id) *
> 0x100)
> +
> #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index defb54dd0bbe..a87f3ec10aea 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1574,6 +1574,7 @@ struct intel_crtc {
> bool enable;
> u32 htotal, hblank, hsync;
> u32 vtotal, vblank, vsync;
> + u32 vrr_ctl;
> } cmtg;
> };
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 9d814cc2d608..2c1ae685400f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -892,6 +892,7 @@ static void intel_vrr_tg_enable(const struct
> intel_crtc_state *crtc_state, {
> struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> u32 vrr_ctl;
>
> intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), @@ -
> 907,6 +908,9 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state
> *crtc_state,
> if (cmrr_enable)
> vrr_ctl |= VRR_CTL_CMRR_ENABLE;
>
> + if (crtc->cmtg.enable)
> + crtc->cmtg.vrr_ctl = vrr_ctl;
> +
> intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> vrr_ctl); }
>
> --
> 2.29.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 05/10] drm/i915/cmtg: program set context latency of cmtg
2026-02-03 13:44 ` [PATCH v2 05/10] drm/i915/cmtg: program set context latency " Animesh Manna
@ 2026-02-06 3:08 ` Kandpal, Suraj
0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2026-02-06 3:08 UTC (permalink / raw)
To: Manna, Animesh, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian, Nikula, Jani, Manna, Animesh,
Nautiyal, Ankit K, Shankar, Uma
> Subject: [PATCH v2 05/10] drm/i915/cmtg: program set context latency of
> cmtg
* CMTG
>
> Program context latency for delayed vblank timings to create window2.
>
Bspec link
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 4 ++++
> drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 26adf70cdd00..cb1376f4c13f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -236,10 +236,14 @@ static void intel_cmtg_set_timings(const struct
> intel_crtc_state *crtc_state)
>
> void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> if (cpu_transcoder != TRANSCODER_A && cpu_transcoder !=
> TRANSCODER_B)
> return;
>
> intel_cmtg_set_timings(crtc_state);
> +
> + intel_de_write(display,
> TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> + intel_de_read(display,
> TRANS_SET_CONTEXT_LATENCY(display,
> +cpu_transcoder)));
So at least three things need to change here:
- We are actively trying to move away from doing inline intel_de_reads like this with arguments passed to function.
- We also try not to read from HW and write back to HW . We need to write our derived S/w value to HW. Readback needs to only
be for verification purpose. We only use H/w read when we are sort of out of options on a viable solution to derive the value at that place.
From what I can see since you are using the exact values that is coded in TRANS_CONTEXT_LATENCY your work can be done by crtc_state->set_context_latency
- This belongs in intel_cmtg_set_timings (which I said before needs to be called from intel_set_transcoder_timings ( Also I think you should rename function to intel_cmtg_set_transcoder_timings))
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index eab90415d0da..3cfd8eedb321 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -32,4 +32,6 @@
> #define TRANS_VRR_VMIN_CMTG(id) _MMIO(0x6F434 + (id) *
> 0x100)
> #define TRANS_VRR_FLIPLINE_CMTG(id) _MMIO(0x6F438 + (id) *
> 0x100)
>
> +#define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) *
> 0x100)
> +
Usually we call this index instead of id
Regards,
Suraj Kandpal
> #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg
2026-02-03 13:44 ` [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg Animesh Manna
@ 2026-02-06 3:22 ` Kandpal, Suraj
0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2026-02-06 3:22 UTC (permalink / raw)
To: Manna, Animesh, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian, Nikula, Jani, Manna, Animesh
> Subject: [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg
* CMTG
>
> Program CMTG link M/N.
>
Bspec link
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 12 ++++++++++++
> drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 3 +++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index cb1376f4c13f..12a081dd7e4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -234,6 +234,16 @@ static void intel_cmtg_set_timings(const struct
> intel_crtc_state *crtc_state)
> }
> }
>
> +static void intel_cpu_cmtg_transcoder_set_m_n(const struct
Should be intel_cmtg_transcoder_set_m_n
Regards,
Suraj Kandpal
> +intel_crtc_state *crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
> +
> + intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n-
> >link_m);
> + intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder),
> +m_n->link_n); }
> +
> void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) {
> struct intel_display *display = to_intel_display(crtc_state); @@ -246,4
> +256,6 @@ void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
>
> intel_de_write(display,
> TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> intel_de_read(display,
> TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
> +
> + intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 3cfd8eedb321..b766ded8686c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -32,6 +32,9 @@
> #define TRANS_VRR_VMIN_CMTG(id) _MMIO(0x6F434 + (id) *
> 0x100)
> #define TRANS_VRR_FLIPLINE_CMTG(id) _MMIO(0x6F438 + (id) *
> 0x100)
>
> +#define TRANS_LINKM1_CMTG(id) _MMIO(0x6F040 + (id) * 0x100)
> +#define TRANS_LINKN1_CMTG(id) _MMIO(0x6F044 + (id) * 0x100)
> +
> #define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) *
> 0x100)
>
> #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 07/10] drm/i915/cmtg: program sync to port for cmtg
2026-02-03 13:44 ` [PATCH v2 07/10] drm/i915/cmtg: program sync to port " Animesh Manna
@ 2026-02-06 3:28 ` Kandpal, Suraj
0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2026-02-06 3:28 UTC (permalink / raw)
To: Manna, Animesh, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian, Nikula, Jani, Manna, Animesh,
Nautiyal, Ankit K, Shankar, Uma
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> Animesh Manna
> Sent: Tuesday, February 3, 2026 7:14 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Manna, Animesh <animesh.manna@intel.com>
> Subject: [PATCH v2 07/10] drm/i915/cmtg: program sync to port for cmtg
* CMTG
>
> Program Cmtg Sync to Port Sync. Set before enabling the timing generator.
> While cmtg start running this bit will be cleared.
* CMTG
Bspec link
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 3 +++
> drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 12a081dd7e4d..3af4aefc760e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -258,4 +258,7 @@ void intel_cmtg_enable(const struct intel_crtc_state
> *crtc_state)
> intel_de_read(display,
> TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
>
> intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
> +
> + /* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
> + intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index b766ded8686c..0ed767a797c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -18,7 +18,9 @@
>
> #define TRANS_CMTG_CTL_A _MMIO(0x6fa88)
> #define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
> +#define TRANS_CMTG_CTL(id) _MMIO(0x6fa88 + (id) * 0x100)
What's the point of defining TRANS_CMTG_CTL_A/B if you are not going to use it
Also have a look at how _TRANS_MMIO works
Use that a lot of you register definitions can use that without having to use a formula for
Every def.
Regards,
Suraj Kandpal
> #define CMTG_ENABLE REG_BIT(31)
> +#define CMTG_SYNC_TO_PORT REG_BIT(29)
>
> #define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) *
> 0x100)
> #define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) *
> 0x100)
> --
> 2.29.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder disable
2026-02-03 13:44 ` [PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder disable Animesh Manna
@ 2026-02-06 3:31 ` Kandpal, Suraj
0 siblings, 0 replies; 35+ messages in thread
From: Kandpal, Suraj @ 2026-02-06 3:31 UTC (permalink / raw)
To: Manna, Animesh, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian, Nikula, Jani, Nautiyal, Ankit K,
Shankar, Uma
> Subject: [PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder
> disable
>
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
>
> Add intel_cmtg_disable() to disable CMTG when the transcoder is disabled.
>
Bspec link
Adding comment here unrelated but I see no patches which redout your CMTG state dump it and verify it I think
You need to added those patches as well
Regards,
Suraj Kandpal
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 33 +++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
> .../gpu/drm/i915/display/intel_cmtg_regs.h | 1 +
> drivers/gpu/drm/i915/display/intel_crt.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> 5 files changed, 34 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index d1ec9b79cef2..844e01b6fc9f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -18,6 +18,7 @@
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> #include "intel_vrr.h"
> +#include "intel_vrr_regs.h"
>
> /**
> * DOC: Common Primary Timing Generator (CMTG) @@ -126,8 +127,8 @@
> static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
> return cmtg_config->trans_a_secondary || cmtg_config-
> >trans_b_secondary; }
>
> -static void intel_cmtg_disable(struct intel_display *display,
> - struct intel_cmtg_config *cmtg_config)
> +static void intel_cmtg_disable_all(struct intel_display *display,
> + struct intel_cmtg_config *cmtg_config)
> {
> u32 clk_sel_clr = 0;
> u32 clk_sel_set = 0;
> @@ -158,6 +159,32 @@ static void intel_cmtg_disable(struct intel_display
> *display,
> intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set); }
>
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 val;
> +
> + if (cpu_transcoder != TRANSCODER_A && cpu_transcoder !=
> TRANSCODER_B)
> + return;
> +
> + val = intel_de_read(display,
> TRANS_VRR_CTL_CMTG(cpu_transcoder));
> + val &= ~VRR_CTL_VRR_ENABLE;
> + val &= ~VRR_CTL_FLIP_LINE_EN;
> + intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), val);
> +
> + intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> + PORT_SYNC_MODE_ENABLE, 0);
> +
> + intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_ENABLE, 0);
> +
> + if (intel_de_wait_for_clear_ms(display,
> TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
> + drm_WARN(display->drm, 1, "CMTG:%d disable timeout\n",
> cpu_transcoder);
> + return;
> + }
> +
> + drm_dbg_kms(display->drm, "CMTG:%d disabled\n", cpu_transcoder);
> }
> /*
> * Read out CMTG configuration and, on platforms that allow disabling it
> without
> * a modeset, do it.
> @@ -185,7 +212,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
> if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
> return;
>
> - intel_cmtg_disable(display, &cmtg_config);
> + intel_cmtg_disable_all(display, &cmtg_config);
> }
>
> void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state) diff -
> -git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index b2bb60d160fa..4f70577be136 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -10,6 +10,7 @@ struct intel_display;
> struct intel_crtc_state;
>
> void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
> +void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
> void intel_cmtg_sanitize(struct intel_display *display);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 0ed767a797c0..f11d5514c376 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -21,6 +21,7 @@
> #define TRANS_CMTG_CTL(id) _MMIO(0x6fa88 + (id) * 0x100)
> #define CMTG_ENABLE REG_BIT(31)
> #define CMTG_SYNC_TO_PORT REG_BIT(29)
> +#define CMTG_STATE REG_BIT(23)
>
> #define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) *
> 0x100)
> #define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) *
> 0x100)
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index b71a8d97cdbb..37a6a139f67b 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -35,6 +35,7 @@
> #include <drm/drm_probe_helper.h>
> #include <video/vga.h>
>
> +#include "intel_cmtg.h"
> #include "intel_connector.h"
> #include "intel_crt.h"
> #include "intel_crt_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 976af9eb3c3a..622f9b690342 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1773,6 +1773,7 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
> struct intel_crtc *pipe_crtc;
> int i;
>
> + intel_cmtg_disable(old_crtc_state);
> /*
> * FIXME collapse everything to one hook.
> * Need care with mst->ddi interactions.
> --
> 2.29.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg
2026-02-05 8:47 ` Jani Nikula
@ 2026-02-06 5:50 ` Manna, Animesh
0 siblings, 0 replies; 35+ messages in thread
From: Manna, Animesh @ 2026-02-06 5:50 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, February 5, 2026 2:17 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: Re: [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg
>
> On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > Timing registers are separate for CMTG, read transcoder register and
> > program cmtg transcoder with those values.
> >
> > v2:
> > - Use sw state instead of reading directly from hardware. [Jani]
> > - Move set_timing later after encoder enable. [Dibin]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cmtg.c | 24 +++++++++
> > drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
> > .../gpu/drm/i915/display/intel_cmtg_regs.h | 7 +++
> > drivers/gpu/drm/i915/display/intel_display.c | 51 ++++++++++++-------
> > .../drm/i915/display/intel_display_types.h | 2 +
> > 5 files changed, 67 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index f5364f5a848f..4220eeece07f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -207,3 +207,27 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
> > if (clk_sel_set)
> > intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set); }
> > +
> > +static void intel_cmtg_set_timings(const struct intel_crtc_state
> > +*crtc_state) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > + intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.htotal);
> > + intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.hblank);
> > + intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder), crtc-
> >cmtg.hsync);
> > + intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder), crtc-
> >cmtg.vtotal);
> > + intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder), crtc-
> >cmtg.vblank);
> > + intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> > +crtc->cmtg.vsync); }
> > +
> > +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) {
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > + if (cpu_transcoder != TRANSCODER_A && cpu_transcoder !=
> TRANSCODER_B)
> > + return;
> > +
> > + intel_cmtg_set_timings(crtc_state);
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index bef2426b2787..b2bb60d160fa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -9,6 +9,7 @@
> > struct intel_display;
> > struct intel_crtc_state;
> >
> > +void intel_cmtg_enable(const struct intel_crtc_state *crtc_state);
> > void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > *crtc_state); void intel_cmtg_sanitize(struct intel_display
> > *display);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > index 8a767b659a23..eb24827d22f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > @@ -20,4 +20,11 @@
> > #define TRANS_CMTG_CTL_B _MMIO(0x6fb88)
> > #define CMTG_ENABLE REG_BIT(31)
> >
> > +#define TRANS_HTOTAL_CMTG(id) _MMIO(0x6F000 + (id) *
> 0x100)
>
> What is id? If it's a transcoder, please use trans for the param name.
Ok.
>
> > +#define TRANS_HBLANK_CMTG(id) _MMIO(0x6F004 + (id) *
> 0x100)
> > +#define TRANS_HSYNC_CMTG(id) _MMIO(0x6F008 + (id) *
> 0x100)
> > +#define TRANS_VTOTAL_CMTG(id) _MMIO(0x6F00C + (id) *
> 0x100)
> > +#define TRANS_VBLANK_CMTG(id) _MMIO(0x6F010 + (id) *
> 0x100)
> > +#define TRANS_VSYNC_CMTG(id) _MMIO(0x6F014 + (id) *
> 0x100)
> > +
> > #endif /* __INTEL_CMTG_REGS_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 564d11925af3..976af9eb3c3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -62,6 +62,7 @@
> > #include "intel_casf.h"
> > #include "intel_cdclk.h"
> > #include "intel_clock_gating.h"
> > +#include "intel_cmtg.h"
> > #include "intel_color.h"
> > #include "intel_crt.h"
> > #include "intel_crtc.h"
> > @@ -1722,6 +1723,9 @@ static void hsw_crtc_enable(struct
> intel_atomic_state *state,
> > intel_crtc_wait_for_next_vblank(wa_crtc);
> > }
> > }
> > +
> > + if (crtc->cmtg.enable)
> > + intel_cmtg_enable(new_crtc_state);
> > }
> >
> > static void ilk_crtc_disable(struct intel_atomic_state *state, @@
> > -2654,6 +2658,8 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
> > const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> > u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> > int vsyncshift = 0;
> > + u32 trans_htotal_val, trans_hblank_val, trans_hsync_val;
> > + u32 trans_vtotal_val, trans_vblank_val, trans_vsync_val;
> >
> > drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
> >
> > @@ -2702,15 +2708,15 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
> > TRANS_VSYNCSHIFT(display, cpu_transcoder),
> > vsyncshift);
> >
> > - intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> > - HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > - HTOTAL(adjusted_mode->crtc_htotal - 1));
> > - intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> > - HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > - HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > - intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> > - HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > - HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > + trans_htotal_val = HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > + HTOTAL(adjusted_mode->crtc_htotal - 1);
> > + trans_hblank_val = HBLANK_START(adjusted_mode-
> >crtc_hblank_start - 1) |
> > + HBLANK_END(adjusted_mode->crtc_hblank_end -
> 1);
> > + trans_hsync_val = HSYNC_START(adjusted_mode->crtc_hsync_start -
> 1) |
> > + HSYNC_END(adjusted_mode->crtc_hsync_end - 1);
> > + intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
> trans_htotal_val);
> > + intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
> trans_hblank_val);
> > + intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
> > +trans_hsync_val);
> >
> > /*
> > * For platforms that always use VRR Timing Generator, the
> > VTOTAL.Vtotal @@ -2721,15 +2727,15 @@ static void
> intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> > if (intel_vrr_always_use_vrr_tg(display))
> > crtc_vtotal = 1;
> >
> > - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> > - VACTIVE(crtc_vdisplay - 1) |
> > - VTOTAL(crtc_vtotal - 1));
> > - intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> > - VBLANK_START(crtc_vblank_start - 1) |
> > - VBLANK_END(crtc_vblank_end - 1));
> > - intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> > - VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > - VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > + trans_vtotal_val = VACTIVE(crtc_vdisplay - 1) |
> > + VTOTAL(crtc_vtotal - 1);
> > + trans_vblank_val = VBLANK_START(crtc_vblank_start - 1) |
> > + VBLANK_END(crtc_vblank_end - 1);
> > + trans_vsync_val = VSYNC_START(adjusted_mode->crtc_vsync_start -
> 1) |
> > + VSYNC_END(adjusted_mode->crtc_vsync_end - 1);
> > + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> trans_vtotal_val);
> > + intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> trans_vblank_val);
> > + intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
> > +trans_vsync_val);
> >
> > /* Workaround: when the EDP input selection is B, the VTOTAL_B
> must be
> > * programmed with the VTOTAL_EDP value. Same for VTOTAL_C.
> This is
> > @@ -2753,6 +2759,15 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
> > intel_de_write(display,
> DP_MIN_HBLANK_CTL(cpu_transcoder),
> > crtc_state->min_hblank);
> > }
> > +
> > + if (crtc->cmtg.enable) {
> > + crtc->cmtg.htotal = trans_htotal_val;
> > + crtc->cmtg.hblank = trans_hblank_val;
> > + crtc->cmtg.hsync = trans_hsync_val;
> > + crtc->cmtg.vtotal = trans_vtotal_val;
> > + crtc->cmtg.vblank = trans_vblank_val;
> > + crtc->cmtg.vsync = trans_vsync_val;
> > + }
> > }
> >
> > static void intel_set_transcoder_timings_lrr(const struct
> > intel_crtc_state *crtc_state) diff --git
> > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 1081615a14fb..defb54dd0bbe 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1572,6 +1572,8 @@ struct intel_crtc {
> >
> > struct {
> > bool enable;
> > + u32 htotal, hblank, hsync;
> > + u32 vtotal, vblank, vsync;
>
> Why are these stored in the crtc?
Cannot store in crtc_state store as it is const. Some adjustment is done before writing to these registers.
So exact same register value need to keep for cmtg as it need to enable as secondary mode after modeset.
Storing in Intel_crtc I felt is a way, but open for any better approach.
Regards,
Animesh
>
> > } cmtg;
> > };
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl
2026-02-05 8:50 ` Jani Nikula
@ 2026-02-06 5:52 ` Manna, Animesh
0 siblings, 0 replies; 35+ messages in thread
From: Manna, Animesh @ 2026-02-06 5:52 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, February 5, 2026 2:20 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: Re: [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl
>
> On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > Enable CMTG through control register.
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cmtg.c | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index 3af4aefc760e..f7364c7408d5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -244,6 +244,19 @@ static void
> intel_cpu_cmtg_transcoder_set_m_n(const struct intel_crtc_state *crt
> > intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder),
> > m_n->link_n); }
> >
> > +static void intel_cmtg_ctl_enable(const struct intel_crtc_state
> > +*crtc_state) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > + u32 val = 0;
> > +
> > + val = intel_de_read(display, TRANS_CMTG_CTL(cpu_transcoder));
> > +
> > + val |= CMTG_ENABLE;
> > +
> > + intel_de_write(display, TRANS_CMTG_CTL(cpu_transcoder), val);
>
> This is just a single line intel_de_rmw().
>
> > +}
> > +
> > void intel_cmtg_enable(const struct intel_crtc_state *crtc_state) {
> > struct intel_display *display = to_intel_display(crtc_state); @@
> > -261,4 +274,7 @@ void intel_cmtg_enable(const struct intel_crtc_state
> > *crtc_state)
> >
> > /* Program Cmtg Sync to Port Sync, TRANS_CMTG_CTL */
> > intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> > CMTG_SYNC_TO_PORT, CMTG_SYNC_TO_PORT);
> > +
> > + /* Program Enable Cmtg */
> > + intel_cmtg_ctl_enable(crtc_state);
>
> If there's intel_de_rmw() before, why is this a function?
Got it, will take care in next version.
>
> > }
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode
2026-02-05 8:53 ` Jani Nikula
@ 2026-02-06 5:56 ` Manna, Animesh
0 siblings, 0 replies; 35+ messages in thread
From: Manna, Animesh @ 2026-02-06 5:56 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: Dibin Moolakadan Subrahmanian
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, February 5, 2026 2:23 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: Re: [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary
> mode
>
> On Tue, 03 Feb 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > From: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> >
> > Wait for CMTG_SYNC_TO_PORT bit clear in cmtg enable sequence and then
> > enable secondary mode for cmtg.
> >
> > Signed-off-by: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cmtg.c | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index f7364c7408d5..d1ec9b79cef2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -277,4 +277,18 @@ void intel_cmtg_enable(const struct
> > intel_crtc_state *crtc_state)
> >
> > /* Program Enable Cmtg */
> > intel_cmtg_ctl_enable(crtc_state);
> > +
> > + if (intel_de_wait_for_clear_ms(display,
> TRANS_CMTG_CTL(cpu_transcoder),
> > + CMTG_SYNC_TO_PORT, 50)) {
> > + drm_WARN(display->drm, 1, "CMTG:%d enable timeout\n",
> cpu_transcoder);
> > + return;
> > + }
>
> This should be part of the previous patch, right?
Yes, will take care in next version.
>
> > +
> > + /*
> > + * eDP transcoder registers as secondary to CMTG by setting
> > + * TRANS_DDI_FUNC_CTL2[CMTG Secondary Mode].
>
> What does this even mean?
CMTG will be enabled in secondary mode. Some copy-paste issue, will rephrase the above comment.
>
> > + */
> > + intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> > +0, CMTG_SECONDARY_MODE);
> > +
> > + drm_dbg_kms(display->drm, "CMTG:%d enabled\n",
> cpu_transcoder);
>
> See transcoder_name().
>
> > }
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2026-02-06 5:56 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-03 13:43 [PATCH v2 00/10] CMTG enablement Animesh Manna
2026-02-03 13:43 ` [PATCH v2 01/10] drm/i915/cmtg: enable cmtg LNL onwards Animesh Manna
2026-02-05 5:18 ` Kandpal, Suraj
2026-02-05 8:43 ` Jani Nikula
2026-02-03 13:43 ` [PATCH v2 02/10] drm/i915/cmtg: cmtg set clock select Animesh Manna
2026-02-05 5:25 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 03/10] drm/i915/cmtg: set timings for cmtg Animesh Manna
2026-02-05 5:35 ` Kandpal, Suraj
2026-02-05 8:47 ` Jani Nikula
2026-02-06 5:50 ` Manna, Animesh
2026-02-03 13:44 ` [PATCH v2 04/10] drm/i915/cmtg: program vrr registers of cmtg Animesh Manna
2026-02-06 2:54 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 05/10] drm/i915/cmtg: program set context latency " Animesh Manna
2026-02-06 3:08 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 06/10] drm/i915/cmtg: set transcoder mn for cmtg Animesh Manna
2026-02-06 3:22 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 07/10] drm/i915/cmtg: program sync to port " Animesh Manna
2026-02-06 3:28 ` Kandpal, Suraj
2026-02-03 13:44 ` [PATCH v2 08/10] drm/i915/cmtg: enable cmtg ctl Animesh Manna
2026-02-05 8:50 ` Jani Nikula
2026-02-06 5:52 ` Manna, Animesh
2026-02-03 13:44 ` [PATCH v2 09/10] drm/i915/cmtg: enable cmtg in secondary mode Animesh Manna
2026-02-05 8:53 ` Jani Nikula
2026-02-06 5:56 ` Manna, Animesh
2026-02-03 13:44 ` [PATCH v2 10/10] drm/i915/cmtg: disable CMTG on transcoder disable Animesh Manna
2026-02-06 3:31 ` Kandpal, Suraj
2026-02-03 14:53 ` ✓ CI.KUnit: success for CMTG enablement (rev2) Patchwork
2026-02-03 15:08 ` ✗ CI.checksparse: warning " Patchwork
2026-02-03 15:28 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-02-04 5:45 ` ✗ Xe.CI.FULL: " Patchwork
2026-02-04 17:52 ` ✓ CI.KUnit: success for CMTG enablement (rev3) Patchwork
2026-02-04 18:08 ` ✗ CI.checksparse: warning " Patchwork
2026-02-04 19:03 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-02-04 20:33 ` Patchwork
2026-02-05 5:33 ` ✗ Xe.CI.FULL: " Patchwork
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