[PATCH 00/11] drm/xe/display: Program double buffered LUT registers

[PATCH 00/11] drm/xe/display: Program double buffered LUT registers

[Chaitanya Kumar Borah]

From PTL, LUT registers are made double buffered. This helps us
to program them in the active region without any concern of tearing.
This particulary helps in case of displays with high refresh rates
where vblank periods are shorter. Add MMIO and DSB path to program them.

Chaitanya Kumar Borah (7):
  drm/i915/dsb: add intel_dsb_gosub_finish()
  drm/i915/dsb: Add support for GOSUB interrupt
  drm/i915: s/dsb_color_vblank/dsb_color
  drm/i915: use GOSUB to program doubled buffered LUT registers
  drm/i915: Program DB LUT registers before vblank
  drm/i915/color: Do not pre-load LUTs with DB registers
  drm/i915: Disable updating of LUT values during vblank

Ville Syrjälä (4):
  drm/i915/dsb: Extract intel_dsb_ins_align()
  drm/i915/dsb: Extract assert_dsb_tail_is_aligned()
  drm/i915/dsb: Extract intel_dsb_{head,tail}()
  drm/i915/dsb: Implement intel_dsb_gosub()

 drivers/gpu/drm/i915/display/intel_atomic.c   |   4 +-
 drivers/gpu/drm/i915/display/intel_color.c    |  51 +++++---
 drivers/gpu/drm/i915/display/intel_crtc.c     |   5 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  36 +++++-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_dsb.c      | 115 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dsb.h      |   3 +
 drivers/gpu/drm/i915/display/intel_dsb_regs.h |   2 +
 9 files changed, 176 insertions(+), 43 deletions(-)

-- 
2.25.1

[PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()

[Chaitanya Kumar Borah]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the code that alings the next instruction to the next
QW boundary into a small helper. I'll have some more uses for
this later.

Also explain why we don't have to zero out the extra DW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 0ddcdedf5453..c166e02b8af0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -228,13 +228,25 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
 	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
 }
 
+static void intel_dsb_ins_align(struct intel_dsb *dsb)
+{
+	/*
+	 * Every instruction should be 8 byte aligned.
+	 *
+	 * The only way to get unaligned free_pos is via
+	 * intel_dsb_reg_write_indexed() which already
+	 * makes sure the next dword is zeroed, so no need
+	 * to clear it here.
+	 */
+	dsb->free_pos = ALIGN(dsb->free_pos, 2);
+}
+
 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
 {
 	if (!assert_dsb_has_room(dsb))
 		return;
 
-	/* Every instruction should be 8 byte aligned. */
-	dsb->free_pos = ALIGN(dsb->free_pos, 2);
+	intel_dsb_ins_align(dsb);
 
 	dsb->ins_start_offset = dsb->free_pos;
 	dsb->ins[0] = ldw;
-- 
2.25.1

RE: [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()

[Shankar, Uma]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: Monday, April 7, 2025 7:54 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>;
> Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extract the code that alings the next instruction to the next QW boundary into a

Not: Typo in "align"

Change Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> small helper. I'll have some more uses for this later.
> 
> Also explain why we don't have to zero out the extra DW.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 0ddcdedf5453..c166e02b8af0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -228,13 +228,25 @@ static bool is_dsb_busy(struct intel_display *display,
> enum pipe pipe,
>  	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) &
> DSB_STATUS_BUSY;  }
> 
> +static void intel_dsb_ins_align(struct intel_dsb *dsb) {
> +	/*
> +	 * Every instruction should be 8 byte aligned.
> +	 *
> +	 * The only way to get unaligned free_pos is via
> +	 * intel_dsb_reg_write_indexed() which already
> +	 * makes sure the next dword is zeroed, so no need
> +	 * to clear it here.
> +	 */
> +	dsb->free_pos = ALIGN(dsb->free_pos, 2); }
> +
>  static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)  {
>  	if (!assert_dsb_has_room(dsb))
>  		return;
> 
> -	/* Every instruction should be 8 byte aligned. */
> -	dsb->free_pos = ALIGN(dsb->free_pos, 2);
> +	intel_dsb_ins_align(dsb);
> 
>  	dsb->ins_start_offset = dsb->free_pos;
>  	dsb->ins[0] = ldw;
> --
> 2.25.1

Re: [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()

[Jani Nikula]

On Mon, 07 Apr 2025, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the code that alings the next instruction to the next
> QW boundary into a small helper. I'll have some more uses for
> this later.
>
> Also explain why we don't have to zero out the extra DW.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Chaitanya, your Signed-off-by is *required* in addition.

See https://developercertificate.org/.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 0ddcdedf5453..c166e02b8af0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -228,13 +228,25 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
>  	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
>  }
>  
> +static void intel_dsb_ins_align(struct intel_dsb *dsb)
> +{
> +	/*
> +	 * Every instruction should be 8 byte aligned.
> +	 *
> +	 * The only way to get unaligned free_pos is via
> +	 * intel_dsb_reg_write_indexed() which already
> +	 * makes sure the next dword is zeroed, so no need
> +	 * to clear it here.
> +	 */
> +	dsb->free_pos = ALIGN(dsb->free_pos, 2);
> +}
> +
>  static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
>  {
>  	if (!assert_dsb_has_room(dsb))
>  		return;
>  
> -	/* Every instruction should be 8 byte aligned. */
> -	dsb->free_pos = ALIGN(dsb->free_pos, 2);
> +	intel_dsb_ins_align(dsb);
>  
>  	dsb->ins_start_offset = dsb->free_pos;
>  	dsb->ins[0] = ldw;

-- 
Jani Nikula, Intel

RE: [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()

[Borah, Chaitanya Kumar]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Wednesday, May 14, 2025 4:47 PM
> To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; intel-
> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>;
> Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; Manna,
> Animesh <animesh.manna@intel.com>
> Subject: Re: [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()
> 
> On Mon, 07 Apr 2025, Chaitanya Kumar Borah
> <chaitanya.kumar.borah@intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Extract the code that alings the next instruction to the next QW
> > boundary into a small helper. I'll have some more uses for this later.
> >
> > Also explain why we don't have to zero out the extra DW.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Chaitanya, your Signed-off-by is *required* in addition.
> 
> See https://developercertificate.org/.
> 

Thank you, Jani, for pointing it out. Pardon my ignorance. I will add it in the next version.

Regards

Chaitanya

> BR,
> Jani.
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++--
> >  1 file changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index 0ddcdedf5453..c166e02b8af0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -228,13 +228,25 @@ static bool is_dsb_busy(struct intel_display
> *display, enum pipe pipe,
> >  	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) &
> > DSB_STATUS_BUSY;  }
> >
> > +static void intel_dsb_ins_align(struct intel_dsb *dsb) {
> > +	/*
> > +	 * Every instruction should be 8 byte aligned.
> > +	 *
> > +	 * The only way to get unaligned free_pos is via
> > +	 * intel_dsb_reg_write_indexed() which already
> > +	 * makes sure the next dword is zeroed, so no need
> > +	 * to clear it here.
> > +	 */
> > +	dsb->free_pos = ALIGN(dsb->free_pos, 2); }
> > +
> >  static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
> > {
> >  	if (!assert_dsb_has_room(dsb))
> >  		return;
> >
> > -	/* Every instruction should be 8 byte aligned. */
> > -	dsb->free_pos = ALIGN(dsb->free_pos, 2);
> > +	intel_dsb_ins_align(dsb);
> >
> >  	dsb->ins_start_offset = dsb->free_pos;
> >  	dsb->ins[0] = ldw;
> 
> --
> Jani Nikula, Intel

[PATCH 02/11] drm/i915/dsb: Extract assert_dsb_tail_is_aligned()

[Chaitanya Kumar Borah]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the DSB tail alignment checks into helper. We already
have two uses of this, and soo we'll get a third.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index c166e02b8af0..08e3bbea1a67 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -204,6 +204,15 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb)
 			 crtc->base.base.id, crtc->base.name, dsb->id);
 }
 
+static bool assert_dsb_tail_is_aligned(struct intel_dsb *dsb)
+{
+	struct intel_crtc *crtc = dsb->crtc;
+	struct intel_display *display = to_intel_display(crtc->base.dev);
+
+	return !drm_WARN_ON(display->drm,
+			    !IS_ALIGNED(dsb->free_pos * 4, CACHELINE_BYTES));
+}
+
 static void intel_dsb_dump(struct intel_dsb *dsb)
 {
 	struct intel_crtc *crtc = dsb->crtc;
@@ -621,10 +630,11 @@ static void _intel_dsb_chain(struct intel_atomic_state *state,
 	if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))
 		return;
 
-	tail = chained_dsb->free_pos * 4;
-	if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES)))
+	if (!assert_dsb_tail_is_aligned(chained_dsb))
 		return;
 
+	tail = chained_dsb->free_pos * 4;
+
 	intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id),
 			    ctrl | DSB_ENABLE);
 
@@ -695,10 +705,11 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
 	enum pipe pipe = crtc->pipe;
 	u32 tail;
 
-	tail = dsb->free_pos * 4;
-	if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES)))
+	if (!assert_dsb_tail_is_aligned(dsb))
 		return;
 
+	tail = dsb->free_pos * 4;
+
 	if (is_dsb_busy(display, pipe, dsb->id)) {
 		drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n",
 			crtc->base.base.id, crtc->base.name, dsb->id);
-- 
2.25.1

[PATCH 03/11] drm/i915/dsb: Extract intel_dsb_{head,tail}()

[Chaitanya Kumar Borah]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the code that calculates the DSB_HEAD/TAIL register
values into small helpers. We already have two copies of this,
and soon there will be a third.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 08e3bbea1a67..0de15e3a9a56 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -237,6 +237,16 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
 	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
 }
 
+static unsigned int intel_dsb_head(struct intel_dsb *dsb)
+{
+	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf);
+}
+
+static unsigned int intel_dsb_tail(struct intel_dsb *dsb)
+{
+	return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + dsb->free_pos * 4;
+}
+
 static void intel_dsb_ins_align(struct intel_dsb *dsb)
 {
 	/*
@@ -625,7 +635,6 @@ static void _intel_dsb_chain(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(state->base.dev);
 	struct intel_crtc *crtc = dsb->crtc;
 	enum pipe pipe = crtc->pipe;
-	u32 tail;
 
 	if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id))
 		return;
@@ -633,8 +642,6 @@ static void _intel_dsb_chain(struct intel_atomic_state *state,
 	if (!assert_dsb_tail_is_aligned(chained_dsb))
 		return;
 
-	tail = chained_dsb->free_pos * 4;
-
 	intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id),
 			    ctrl | DSB_ENABLE);
 
@@ -655,10 +662,10 @@ static void _intel_dsb_chain(struct intel_atomic_state *state,
 	}
 
 	intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id),
-			    intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf));
+			    intel_dsb_head(chained_dsb));
 
 	intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id),
-			    intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail);
+			    intel_dsb_tail(chained_dsb));
 
 	if (ctrl & DSB_WAIT_FOR_VBLANK) {
 		/*
@@ -703,13 +710,10 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
 	struct intel_crtc *crtc = dsb->crtc;
 	struct intel_display *display = to_intel_display(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	u32 tail;
 
 	if (!assert_dsb_tail_is_aligned(dsb))
 		return;
 
-	tail = dsb->free_pos * 4;
-
 	if (is_dsb_busy(display, pipe, dsb->id)) {
 		drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n",
 			crtc->base.base.id, crtc->base.name, dsb->id);
@@ -727,7 +731,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
 			  dsb_error_int_en(display) | DSB_PROG_INT_EN);
 
 	intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),
-			  intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf));
+			  intel_dsb_head(dsb));
 
 	if (hw_dewake_scanline >= 0) {
 		int diff, position;
@@ -749,7 +753,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
 	}
 
 	intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id),
-			  intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail);
+			  intel_dsb_tail(dsb));
 }
 
 /**
-- 
2.25.1

[PATCH 04/11] drm/i915/dsb: Implement intel_dsb_gosub()

[Chaitanya Kumar Borah]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add support for the new GOSUB DSB instruction (available on ptl+),
which instructs the DSB to jump to a different buffer, executie
the commands there, and then return execution to the next
instruction in the original buffer.

There are a few alignment related workarounds that need to
be dealt with when emitting GOSUB instruction.

v2: Right shift head and tail pointer passed to gosub command (chaitanya)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 52 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dsb.h |  2 +
 2 files changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 0de15e3a9a56..2cda6fc7857b 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -93,6 +93,9 @@ struct intel_dsb {
 /* see DSB_REG_VALUE_MASK */
 #define DSB_OPCODE_POLL			0xA
 /* see DSB_REG_VALUE_MASK */
+#define DSB_OPCODE_GOSUB		0xC /* ptl+ */
+#define   DSB_GOSUB_HEAD_SHIFT		26
+#define   DSB_GOSUB_TAIL_SHIFT		0
 
 static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
 				     struct intel_crtc *crtc)
@@ -533,6 +536,55 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb)
 	dsb->free_pos = aligned_tail / 4;
 }
 
+static void intel_dsb_gosub_align(struct intel_dsb *dsb)
+{
+	u32 aligned_tail, tail;
+
+	intel_dsb_ins_align(dsb);
+
+	tail = dsb->free_pos * 4;
+	aligned_tail = ALIGN(tail, CACHELINE_BYTES);
+
+	/*
+	 * "The GOSUB instruction cannot be placed in
+	 *  cacheline QW slot 6 or 7 (numbered 0-7)"
+	 */
+	if (aligned_tail - tail <= 2 * 8)
+		intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0,
+					aligned_tail - tail);
+
+	dsb->free_pos = aligned_tail / 4;
+}
+
+void intel_dsb_gosub(struct intel_dsb *dsb,
+		     struct intel_dsb *sub_dsb)
+{
+	struct intel_crtc *crtc = dsb->crtc;
+	struct intel_display *display = to_intel_display(crtc->base.dev);
+	u64 head_tail;
+
+	if (drm_WARN_ON(display->drm, dsb->id != sub_dsb->id))
+		return;
+
+	if (!assert_dsb_tail_is_aligned(sub_dsb))
+		return;
+
+	intel_dsb_gosub_align(dsb);
+
+	head_tail = ((u64)(intel_dsb_head(sub_dsb) >> 6) << DSB_GOSUB_HEAD_SHIFT) |
+		((u64)(intel_dsb_tail(sub_dsb) >> 6) << DSB_GOSUB_TAIL_SHIFT);
+
+	intel_dsb_emit(dsb, lower_32_bits(head_tail),
+		       (DSB_OPCODE_GOSUB << DSB_OPCODE_SHIFT) |
+		       upper_32_bits(head_tail));
+
+	/*
+	 * "NOTE: the instructions within the cacheline
+	 *  FOLLOWING the GOSUB instruction must be NOPs."
+	 */
+	intel_dsb_align_tail(dsb);
+}
+
 void intel_dsb_finish(struct intel_dsb *dsb)
 {
 	struct intel_crtc *crtc = dsb->crtc;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index e843c52bf97c..8b2cf0a7b7e6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -57,6 +57,8 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 void intel_dsb_poll(struct intel_dsb *dsb,
 		    i915_reg_t reg, u32 mask, u32 val,
 		    int wait_us, int count);
+void intel_dsb_gosub(struct intel_dsb *dsb,
+		     struct intel_dsb *sub_dsb);
 void intel_dsb_chain(struct intel_atomic_state *state,
 		     struct intel_dsb *dsb,
 		     struct intel_dsb *chained_dsb,
-- 
2.25.1

RE: [PATCH 04/11] drm/i915/dsb: Implement intel_dsb_gosub()

[Shankar, Uma]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: Monday, April 7, 2025 7:54 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>;
> Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: [PATCH 04/11] drm/i915/dsb: Implement intel_dsb_gosub()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add support for the new GOSUB DSB instruction (available on ptl+), which
> instructs the DSB to jump to a different buffer, executie the commands there, and

Nit: Typo in "execute"

> then return execution to the next instruction in the original buffer.
> 
> There are a few alignment related workarounds that need to be dealt with when
> emitting GOSUB instruction.
> 
> v2: Right shift head and tail pointer passed to gosub command (chaitanya)

Changes Look Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 52 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dsb.h |  2 +
>  2 files changed, 54 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 0de15e3a9a56..2cda6fc7857b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -93,6 +93,9 @@ struct intel_dsb {
>  /* see DSB_REG_VALUE_MASK */
>  #define DSB_OPCODE_POLL			0xA
>  /* see DSB_REG_VALUE_MASK */
> +#define DSB_OPCODE_GOSUB		0xC /* ptl+ */
> +#define   DSB_GOSUB_HEAD_SHIFT		26
> +#define   DSB_GOSUB_TAIL_SHIFT		0
> 
>  static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
>  				     struct intel_crtc *crtc)
> @@ -533,6 +536,55 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb)
>  	dsb->free_pos = aligned_tail / 4;
>  }
> 
> +static void intel_dsb_gosub_align(struct intel_dsb *dsb) {
> +	u32 aligned_tail, tail;
> +
> +	intel_dsb_ins_align(dsb);
> +
> +	tail = dsb->free_pos * 4;
> +	aligned_tail = ALIGN(tail, CACHELINE_BYTES);
> +
> +	/*
> +	 * "The GOSUB instruction cannot be placed in
> +	 *  cacheline QW slot 6 or 7 (numbered 0-7)"
> +	 */
> +	if (aligned_tail - tail <= 2 * 8)
> +		intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0,
> +					aligned_tail - tail);
> +
> +	dsb->free_pos = aligned_tail / 4;
> +}
> +
> +void intel_dsb_gosub(struct intel_dsb *dsb,
> +		     struct intel_dsb *sub_dsb)
> +{
> +	struct intel_crtc *crtc = dsb->crtc;
> +	struct intel_display *display = to_intel_display(crtc->base.dev);
> +	u64 head_tail;
> +
> +	if (drm_WARN_ON(display->drm, dsb->id != sub_dsb->id))
> +		return;
> +
> +	if (!assert_dsb_tail_is_aligned(sub_dsb))
> +		return;
> +
> +	intel_dsb_gosub_align(dsb);
> +
> +	head_tail = ((u64)(intel_dsb_head(sub_dsb) >> 6) <<
> DSB_GOSUB_HEAD_SHIFT) |
> +		((u64)(intel_dsb_tail(sub_dsb) >> 6) <<
> DSB_GOSUB_TAIL_SHIFT);
> +
> +	intel_dsb_emit(dsb, lower_32_bits(head_tail),
> +		       (DSB_OPCODE_GOSUB << DSB_OPCODE_SHIFT) |
> +		       upper_32_bits(head_tail));
> +
> +	/*
> +	 * "NOTE: the instructions within the cacheline
> +	 *  FOLLOWING the GOSUB instruction must be NOPs."
> +	 */
> +	intel_dsb_align_tail(dsb);
> +}
> +
>  void intel_dsb_finish(struct intel_dsb *dsb)  {
>  	struct intel_crtc *crtc = dsb->crtc;
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> index e843c52bf97c..8b2cf0a7b7e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -57,6 +57,8 @@ void intel_dsb_vblank_evade(struct intel_atomic_state
> *state,  void intel_dsb_poll(struct intel_dsb *dsb,
>  		    i915_reg_t reg, u32 mask, u32 val,
>  		    int wait_us, int count);
> +void intel_dsb_gosub(struct intel_dsb *dsb,
> +		     struct intel_dsb *sub_dsb);
>  void intel_dsb_chain(struct intel_atomic_state *state,
>  		     struct intel_dsb *dsb,
>  		     struct intel_dsb *chained_dsb,
> --
> 2.25.1

[PATCH 05/11] drm/i915/dsb: add intel_dsb_gosub_finish()

[Chaitanya Kumar Borah]

A DSB buffer which will be used for GOSUB execution does not need
the DEWAKE mechanism but still need to be 64 bit aligned. Add helper
to finish preparation of a dsb buffer to be executed with GOSUB
instruction.

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 7 +++++++
 drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2cda6fc7857b..bffa02a0442c 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -585,6 +585,13 @@ void intel_dsb_gosub(struct intel_dsb *dsb,
 	intel_dsb_align_tail(dsb);
 }
 
+void intel_dsb_gosub_finish(struct intel_dsb *dsb)
+{
+	intel_dsb_align_tail(dsb);
+
+	intel_dsb_buffer_flush_map(&dsb->dsb_buf);
+}
+
 void intel_dsb_finish(struct intel_dsb *dsb)
 {
 	struct intel_crtc *crtc = dsb->crtc;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 8b2cf0a7b7e6..6900acd603b8 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -31,6 +31,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
 				    enum intel_dsb_id dsb_id,
 				    unsigned int max_cmds);
 void intel_dsb_finish(struct intel_dsb *dsb);
+void intel_dsb_gosub_finish(struct intel_dsb *dsb);
 void intel_dsb_cleanup(struct intel_dsb *dsb);
 void intel_dsb_reg_write(struct intel_dsb *dsb,
 			 i915_reg_t reg, u32 val);
-- 
2.25.1

Re: [PATCH 05/11] drm/i915/dsb: add intel_dsb_gosub_finish()

[Ville Syrjälä]

On Mon, Apr 07, 2025 at 07:53:53PM +0530, Chaitanya Kumar Borah wrote:
> A DSB buffer which will be used for GOSUB execution does not need
> the DEWAKE mechanism but still need to be 64 bit aligned. Add helper
> to finish preparation of a dsb buffer to be executed with GOSUB
> instruction.
> 
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 7 +++++++
>  drivers/gpu/drm/i915/display/intel_dsb.h | 1 +
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 2cda6fc7857b..bffa02a0442c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -585,6 +585,13 @@ void intel_dsb_gosub(struct intel_dsb *dsb,
>  	intel_dsb_align_tail(dsb);
>  }
>  
> +void intel_dsb_gosub_finish(struct intel_dsb *dsb)
> +{
> +	intel_dsb_align_tail(dsb);

There is one more w/a listd that may require us to do something like::

/* "All subroutines called by the GOSUB instruction must end with a cacheline of NOPs" */
intel_dsb_noop(8);

> +
> +	intel_dsb_buffer_flush_map(&dsb->dsb_buf);
> +}
> +
>  void intel_dsb_finish(struct intel_dsb *dsb)
>  {
>  	struct intel_crtc *crtc = dsb->crtc;
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 8b2cf0a7b7e6..6900acd603b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -31,6 +31,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
>  				    enum intel_dsb_id dsb_id,
>  				    unsigned int max_cmds);
>  void intel_dsb_finish(struct intel_dsb *dsb);
> +void intel_dsb_gosub_finish(struct intel_dsb *dsb);
>  void intel_dsb_cleanup(struct intel_dsb *dsb);
>  void intel_dsb_reg_write(struct intel_dsb *dsb,
>  			 i915_reg_t reg, u32 val);
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

[PATCH 06/11] drm/i915/dsb: Add support for GOSUB interrupt

[Chaitanya Kumar Borah]

DSB raises an interrupt when there is a nested GOSUB command or
illegal Head/Tail. Add support to log such errors in the DSB
interrupt handler.

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c      | 5 ++++-
 drivers/gpu/drm/i915/display/intel_dsb_regs.h | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index bffa02a0442c..da58f1c821c3 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -787,7 +787,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
 
 	intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),
 			  dsb_error_int_status(display) | DSB_PROG_INT_STATUS |
-			  dsb_error_int_en(display) | DSB_PROG_INT_EN);
+			  dsb_error_int_en(display) | DSB_PROG_INT_EN | DSB_GOSUB_INT_EN);
 
 	intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),
 			  intel_dsb_head(dsb));
@@ -980,4 +980,7 @@ void intel_dsb_irq_handler(struct intel_display *display,
 	if (errors & DSB_POLL_ERR_INT_STATUS)
 		drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n",
 			crtc->base.base.id, crtc->base.name, dsb_id);
+	if (errors & DSB_GOSUB_INT_STATUS)
+		drm_err(display->drm, "[CRTC:%d:%s] DSB %d gosub int error\n",
+			crtc->base.base.id, crtc->base.name, dsb_id);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h
index cb6e0e5624a6..230104f36145 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h
@@ -51,11 +51,13 @@
 #define   DSB_RESET_SM_STATE_MASK	REG_GENMASK(5, 4)
 #define   DSB_RUN_SM_STATE_MASK		REG_GENMASK(2, 0)
 #define DSB_INTERRUPT(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
+#define   DSB_GOSUB_INT_EN		REG_BIT(21) /* ptl+ */
 #define   DSB_ATS_FAULT_INT_EN		REG_BIT(20) /* mtl+ */
 #define   DSB_GTT_FAULT_INT_EN		REG_BIT(19)
 #define   DSB_RSPTIMEOUT_INT_EN		REG_BIT(18)
 #define   DSB_POLL_ERR_INT_EN		REG_BIT(17)
 #define   DSB_PROG_INT_EN		REG_BIT(16)
+#define   DSB_GOSUB_INT_STATUS		REG_BIT(5) /* ptl+ */
 #define   DSB_ATS_FAULT_INT_STATUS	REG_BIT(4) /* mtl+ */
 #define   DSB_GTT_FAULT_INT_STATUS	REG_BIT(3)
 #define   DSB_RSPTIMEOUT_INT_STATUS	REG_BIT(2)
-- 
2.25.1

Re: [PATCH 06/11] drm/i915/dsb: Add support for GOSUB interrupt

[Ville Syrjälä]

On Mon, Apr 07, 2025 at 07:53:54PM +0530, Chaitanya Kumar Borah wrote:
> DSB raises an interrupt when there is a nested GOSUB command or
> illegal Head/Tail. Add support to log such errors in the DSB
> interrupt handler.
> 
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c      | 5 ++++-
>  drivers/gpu/drm/i915/display/intel_dsb_regs.h | 2 ++
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index bffa02a0442c..da58f1c821c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -787,7 +787,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
>  
>  	intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id),
>  			  dsb_error_int_status(display) | DSB_PROG_INT_STATUS |
> -			  dsb_error_int_en(display) | DSB_PROG_INT_EN);
> +			  dsb_error_int_en(display) | DSB_PROG_INT_EN | DSB_GOSUB_INT_EN);

You need to add that to dsb_error_int_{en,status}(), with the
appropriate platform checks to avoid the interrupt handler getting
confused on platforms that don't have GOSUB.

>  
>  	intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id),
>  			  intel_dsb_head(dsb));
> @@ -980,4 +980,7 @@ void intel_dsb_irq_handler(struct intel_display *display,
>  	if (errors & DSB_POLL_ERR_INT_STATUS)
>  		drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n",
>  			crtc->base.base.id, crtc->base.name, dsb_id);
> +	if (errors & DSB_GOSUB_INT_STATUS)
> +		drm_err(display->drm, "[CRTC:%d:%s] DSB %d gosub int error\n",

Maybe something like:
"... GOSUB programming error"

> +			crtc->base.base.id, crtc->base.name, dsb_id);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h
> index cb6e0e5624a6..230104f36145 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h
> @@ -51,11 +51,13 @@
>  #define   DSB_RESET_SM_STATE_MASK	REG_GENMASK(5, 4)
>  #define   DSB_RUN_SM_STATE_MASK		REG_GENMASK(2, 0)
>  #define DSB_INTERRUPT(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
> +#define   DSB_GOSUB_INT_EN		REG_BIT(21) /* ptl+ */
>  #define   DSB_ATS_FAULT_INT_EN		REG_BIT(20) /* mtl+ */
>  #define   DSB_GTT_FAULT_INT_EN		REG_BIT(19)
>  #define   DSB_RSPTIMEOUT_INT_EN		REG_BIT(18)
>  #define   DSB_POLL_ERR_INT_EN		REG_BIT(17)
>  #define   DSB_PROG_INT_EN		REG_BIT(16)
> +#define   DSB_GOSUB_INT_STATUS		REG_BIT(5) /* ptl+ */
>  #define   DSB_ATS_FAULT_INT_STATUS	REG_BIT(4) /* mtl+ */
>  #define   DSB_GTT_FAULT_INT_STATUS	REG_BIT(3)
>  #define   DSB_RSPTIMEOUT_INT_STATUS	REG_BIT(2)
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

[PATCH 07/11] drm/i915: s/dsb_color_vblank/dsb_color

[Chaitanya Kumar Borah]

With double buffer gamma registers in the mix, we need not wait for
vblank to execute gamma writes through dsb. Before we implement
that s/dsb_color_vblank/dsb_color.

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.c   |  4 +-
 drivers/gpu/drm/i915/display/intel_color.c    | 38 +++++++++----------
 drivers/gpu/drm/i915/display/intel_display.c  | 10 ++---
 .../drm/i915/display/intel_display_types.h    |  2 +-
 4 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index e83feca5c9c9..f85edb374c97 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -274,7 +274,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
 	crtc_state->do_async_flip = false;
 	crtc_state->fb_bits = 0;
 	crtc_state->update_planes = 0;
-	crtc_state->dsb_color_vblank = NULL;
+	crtc_state->dsb_color = NULL;
 	crtc_state->dsb_commit = NULL;
 	crtc_state->use_dsb = false;
 
@@ -310,7 +310,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
 {
 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
 
-	drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank);
+	drm_WARN_ON(crtc->dev, crtc_state->dsb_color);
 	drm_WARN_ON(crtc->dev, crtc_state->dsb_commit);
 
 	__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 98dddf72c0eb..bb2da3a53e9c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1339,8 +1339,8 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	if (crtc_state->dsb_color_vblank)
-		intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val);
+	if (crtc_state->dsb_color)
+		intel_dsb_reg_write(crtc_state->dsb_color, reg, val);
 	else
 		intel_de_write_fw(display, reg, val);
 }
@@ -1350,8 +1350,8 @@ static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state,
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	if (crtc_state->dsb_color_vblank)
-		intel_dsb_reg_write_indexed(crtc_state->dsb_color_vblank, reg, val);
+	if (crtc_state->dsb_color)
+		intel_dsb_reg_write_indexed(crtc_state->dsb_color, reg, val);
 	else
 		intel_de_write_fw(display, reg, val);
 }
@@ -1389,7 +1389,7 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,
 	for (i = 0; i < 256; i++) {
 		ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
 			      i9xx_lut_8(&lut[i]));
-		if (crtc_state->dsb_color_vblank)
+		if (crtc_state->dsb_color)
 			ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
 				      i9xx_lut_8(&lut[i]));
 	}
@@ -1917,7 +1917,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	if (crtc_state->dsb_color_vblank)
+	if (crtc_state->dsb_color)
 		return;
 
 	display->funcs.color->load_luts(crtc_state);
@@ -1982,39 +1982,39 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
 	if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
 		return;
 
-	crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
-	if (!crtc_state->dsb_color_vblank)
+	crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
+	if (!crtc_state->dsb_color)
 		return;
 
 	display->funcs.color->load_luts(crtc_state);
 
 	if (crtc_state->use_dsb) {
-		intel_vrr_send_push(crtc_state->dsb_color_vblank, crtc_state);
-		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank);
-		intel_vrr_check_push_sent(crtc_state->dsb_color_vblank, crtc_state);
-		intel_dsb_interrupt(crtc_state->dsb_color_vblank);
+		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
+		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
+		intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
+		intel_dsb_interrupt(crtc_state->dsb_color);
 	}
 
-	intel_dsb_finish(crtc_state->dsb_color_vblank);
+	intel_dsb_finish(crtc_state->dsb_color);
 }
 
 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
 {
-	if (crtc_state->dsb_color_vblank) {
-		intel_dsb_cleanup(crtc_state->dsb_color_vblank);
-		crtc_state->dsb_color_vblank = NULL;
+	if (crtc_state->dsb_color) {
+		intel_dsb_cleanup(crtc_state->dsb_color);
+		crtc_state->dsb_color = NULL;
 	}
 }
 
 void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
 {
-	if (crtc_state->dsb_color_vblank)
-		intel_dsb_wait(crtc_state->dsb_color_vblank);
+	if (crtc_state->dsb_color)
+		intel_dsb_wait(crtc_state->dsb_color);
 }
 
 bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
 {
-	return crtc_state->dsb_color_vblank;
+	return crtc_state->dsb_color;
 }
 
 static bool intel_can_preload_luts(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dc7517da2ed5..69c1790199d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7182,7 +7182,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)
+	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color)
 		return;
 
 	/*
@@ -7229,7 +7229,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 			skl_detach_scalers(new_crtc_state->dsb_commit,
 					   new_crtc_state);
 
-		if (!new_crtc_state->dsb_color_vblank) {
+		if (!new_crtc_state->dsb_color) {
 			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
 
 			intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
@@ -7239,9 +7239,9 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		}
 	}
 
-	if (new_crtc_state->dsb_color_vblank)
+	if (new_crtc_state->dsb_color)
 		intel_dsb_chain(state, new_crtc_state->dsb_commit,
-				new_crtc_state->dsb_color_vblank, true);
+				new_crtc_state->dsb_color, true);
 
 	intel_dsb_finish(new_crtc_state->dsb_commit);
 }
@@ -7430,7 +7430,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 *
 		 * FIXME get rid of this funny new->old swapping
 		 */
-		old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank);
+		old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color);
 		old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 367b53a9eae2..99244c2449d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1292,7 +1292,7 @@ struct intel_crtc_state {
 	enum transcoder mst_master_transcoder;
 
 	/* For DSB based pipe updates */
-	struct intel_dsb *dsb_color_vblank, *dsb_commit;
+	struct intel_dsb *dsb_color, *dsb_commit;
 	bool use_dsb;
 
 	u32 psr2_man_track_ctl;
-- 
2.25.1

Re: [PATCH 07/11] drm/i915: s/dsb_color_vblank/dsb_color

[Ville Syrjälä]

On Mon, Apr 07, 2025 at 07:53:55PM +0530, Chaitanya Kumar Borah wrote:
> With double buffer gamma registers in the mix, we need not wait for
> vblank to execute gamma writes through dsb. Before we implement
> that s/dsb_color_vblank/dsb_color.
> 
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_atomic.c   |  4 +-
>  drivers/gpu/drm/i915/display/intel_color.c    | 38 +++++++++----------
>  drivers/gpu/drm/i915/display/intel_display.c  | 10 ++---
>  .../drm/i915/display/intel_display_types.h    |  2 +-
>  4 files changed, 27 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index e83feca5c9c9..f85edb374c97 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -274,7 +274,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>  	crtc_state->do_async_flip = false;
>  	crtc_state->fb_bits = 0;
>  	crtc_state->update_planes = 0;
> -	crtc_state->dsb_color_vblank = NULL;
> +	crtc_state->dsb_color = NULL;
>  	crtc_state->dsb_commit = NULL;
>  	crtc_state->use_dsb = false;
>  
> @@ -310,7 +310,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
>  {
>  	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
>  
> -	drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank);
> +	drm_WARN_ON(crtc->dev, crtc_state->dsb_color);
>  	drm_WARN_ON(crtc->dev, crtc_state->dsb_commit);
>  
>  	__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 98dddf72c0eb..bb2da3a53e9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1339,8 +1339,8 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state,
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  
> -	if (crtc_state->dsb_color_vblank)
> -		intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val);
> +	if (crtc_state->dsb_color)
> +		intel_dsb_reg_write(crtc_state->dsb_color, reg, val);
>  	else
>  		intel_de_write_fw(display, reg, val);
>  }
> @@ -1350,8 +1350,8 @@ static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state,
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  
> -	if (crtc_state->dsb_color_vblank)
> -		intel_dsb_reg_write_indexed(crtc_state->dsb_color_vblank, reg, val);
> +	if (crtc_state->dsb_color)
> +		intel_dsb_reg_write_indexed(crtc_state->dsb_color, reg, val);
>  	else
>  		intel_de_write_fw(display, reg, val);
>  }
> @@ -1389,7 +1389,7 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,
>  	for (i = 0; i < 256; i++) {
>  		ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
>  			      i9xx_lut_8(&lut[i]));
> -		if (crtc_state->dsb_color_vblank)
> +		if (crtc_state->dsb_color)
>  			ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
>  				      i9xx_lut_8(&lut[i]));
>  	}
> @@ -1917,7 +1917,7 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  
> -	if (crtc_state->dsb_color_vblank)
> +	if (crtc_state->dsb_color)
>  		return;
>  
>  	display->funcs.color->load_luts(crtc_state);
> @@ -1982,39 +1982,39 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
>  	if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
>  		return;
>  
> -	crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
> -	if (!crtc_state->dsb_color_vblank)
> +	crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
> +	if (!crtc_state->dsb_color)
>  		return;
>  
>  	display->funcs.color->load_luts(crtc_state);
>  
>  	if (crtc_state->use_dsb) {
> -		intel_vrr_send_push(crtc_state->dsb_color_vblank, crtc_state);
> -		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank);
> -		intel_vrr_check_push_sent(crtc_state->dsb_color_vblank, crtc_state);
> -		intel_dsb_interrupt(crtc_state->dsb_color_vblank);
> +		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
> +		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
> +		intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
> +		intel_dsb_interrupt(crtc_state->dsb_color);
>  	}
>  
> -	intel_dsb_finish(crtc_state->dsb_color_vblank);
> +	intel_dsb_finish(crtc_state->dsb_color);
>  }
>  
>  void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
>  {
> -	if (crtc_state->dsb_color_vblank) {
> -		intel_dsb_cleanup(crtc_state->dsb_color_vblank);
> -		crtc_state->dsb_color_vblank = NULL;
> +	if (crtc_state->dsb_color) {
> +		intel_dsb_cleanup(crtc_state->dsb_color);
> +		crtc_state->dsb_color = NULL;
>  	}
>  }
>  
>  void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
>  {
> -	if (crtc_state->dsb_color_vblank)
> -		intel_dsb_wait(crtc_state->dsb_color_vblank);
> +	if (crtc_state->dsb_color)
> +		intel_dsb_wait(crtc_state->dsb_color);
>  }
>  
>  bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
>  {
> -	return crtc_state->dsb_color_vblank;
> +	return crtc_state->dsb_color;
>  }
>  
>  static bool intel_can_preload_luts(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index dc7517da2ed5..69c1790199d3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7182,7 +7182,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  
> -	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)
> +	if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color)
>  		return;
>  
>  	/*
> @@ -7229,7 +7229,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  			skl_detach_scalers(new_crtc_state->dsb_commit,
>  					   new_crtc_state);
>  
> -		if (!new_crtc_state->dsb_color_vblank) {
> +		if (!new_crtc_state->dsb_color) {
>  			intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
>  
>  			intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
> @@ -7239,9 +7239,9 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  		}
>  	}
>  
> -	if (new_crtc_state->dsb_color_vblank)
> +	if (new_crtc_state->dsb_color)
>  		intel_dsb_chain(state, new_crtc_state->dsb_commit,
> -				new_crtc_state->dsb_color_vblank, true);
> +				new_crtc_state->dsb_color, true);
>  
>  	intel_dsb_finish(new_crtc_state->dsb_commit);
>  }
> @@ -7430,7 +7430,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		 *
>  		 * FIXME get rid of this funny new->old swapping
>  		 */
> -		old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank);
> +		old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color);
>  		old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 367b53a9eae2..99244c2449d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1292,7 +1292,7 @@ struct intel_crtc_state {
>  	enum transcoder mst_master_transcoder;
>  
>  	/* For DSB based pipe updates */
> -	struct intel_dsb *dsb_color_vblank, *dsb_commit;
> +	struct intel_dsb *dsb_color, *dsb_commit;
>  	bool use_dsb;
>  
>  	u32 psr2_man_track_ctl;
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

[PATCH 08/11] drm/i915: use GOSUB to program doubled buffered LUT registers

[Chaitanya Kumar Borah]

With addition of double buffered GAMMA registers in PTL, we can now
program them in the active region. Use GOSUB instruction of DSB to
program them.

It is done in the following steps:
	1. intel_color_prepare_commit()
		- If the platform supports, prepare a dsb instance (dsb_color)
		  hooked to DSB0.
		- Add all the register write instructions to dsb_color through
		  the load_lut() hook
                - Do not add the vrr_send_push() logic to the buffer as it
		  should be taken care by dsb_commit instance of DSB0
                - Finish preparation of the buffer by aligning it to 64 bit

	2. intel_atomic_dsb_finish()
		- Add the gosub instruction into the dsb_commit instance of DSB0
		  using intel_dsb_gosub()
		- If needed, add the vrr_send_push() logic to dsb_commit after it

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c    | 13 ++++++++---
 drivers/gpu/drm/i915/display/intel_display.c  | 22 ++++++++++++++++---
 .../drm/i915/display/intel_display_device.h   |  1 +
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index bb2da3a53e9c..49429404bd82 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1982,20 +1982,27 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
 	if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
 		return;
 
-	crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
+	if (HAS_DOUBLE_BUFFERED_LUT(display))
+		crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024);
+	else
+		crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
+
 	if (!crtc_state->dsb_color)
 		return;
 
 	display->funcs.color->load_luts(crtc_state);
 
-	if (crtc_state->use_dsb) {
+	if (crtc_state->use_dsb && !HAS_DOUBLE_BUFFERED_LUT(display)) {
 		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
 		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
 		intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
 		intel_dsb_interrupt(crtc_state->dsb_color);
 	}
 
-	intel_dsb_finish(crtc_state->dsb_color);
+	if (HAS_DOUBLE_BUFFERED_LUT(display))
+		intel_dsb_gosub_finish(crtc_state->dsb_color);
+	else
+		intel_dsb_finish(crtc_state->dsb_color);
 }
 
 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 69c1790199d3..85e28b4c9e66 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7239,9 +7239,25 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 		}
 	}
 
-	if (new_crtc_state->dsb_color)
-		intel_dsb_chain(state, new_crtc_state->dsb_commit,
-				new_crtc_state->dsb_color, true);
+	if (new_crtc_state->dsb_color) {
+		if (HAS_DOUBLE_BUFFERED_LUT(display)) {
+			intel_dsb_gosub(new_crtc_state->dsb_commit,
+					new_crtc_state->dsb_color);
+
+			if (new_crtc_state->use_dsb) {
+				intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
+
+				intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
+				intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
+				intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
+							  new_crtc_state);
+				intel_dsb_interrupt(new_crtc_state->dsb_commit);
+			}
+		} else {
+			intel_dsb_chain(state, new_crtc_state->dsb_commit,
+					new_crtc_state->dsb_color, true);
+		}
+	}
 
 	intel_dsb_finish(new_crtc_state->dsb_commit);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 368b0d3417c2..14943b47824b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -157,6 +157,7 @@ struct intel_display_platforms {
 #define HAS_DMC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dmc)
 #define HAS_DMC_WAKELOCK(__display)	(DISPLAY_VER(__display) >= 20)
 #define HAS_DOUBLE_BUFFERED_M_N(__display)	(DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell)
+#define HAS_DOUBLE_BUFFERED_LUT(__display)	(DISPLAY_VER(__display) >= 30)
 #define HAS_DOUBLE_WIDE(__display)	(DISPLAY_VER(__display) < 4)
 #define HAS_DP20(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
 #define HAS_DPT(__display)		(DISPLAY_VER(__display) >= 13)
-- 
2.25.1

Re: [PATCH 08/11] drm/i915: use GOSUB to program doubled buffered LUT registers

[Ville Syrjälä]

On Mon, Apr 07, 2025 at 07:53:56PM +0530, Chaitanya Kumar Borah wrote:
> With addition of double buffered GAMMA registers in PTL, we can now
> program them in the active region. Use GOSUB instruction of DSB to
> program them.
> 
> It is done in the following steps:
> 	1. intel_color_prepare_commit()
> 		- If the platform supports, prepare a dsb instance (dsb_color)
> 		  hooked to DSB0.
> 		- Add all the register write instructions to dsb_color through
> 		  the load_lut() hook
>                 - Do not add the vrr_send_push() logic to the buffer as it
> 		  should be taken care by dsb_commit instance of DSB0
>                 - Finish preparation of the buffer by aligning it to 64 bit
> 
> 	2. intel_atomic_dsb_finish()
> 		- Add the gosub instruction into the dsb_commit instance of DSB0
> 		  using intel_dsb_gosub()
> 		- If needed, add the vrr_send_push() logic to dsb_commit after it
> 
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c    | 13 ++++++++---
>  drivers/gpu/drm/i915/display/intel_display.c  | 22 ++++++++++++++++---
>  .../drm/i915/display/intel_display_device.h   |  1 +
>  3 files changed, 30 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index bb2da3a53e9c..49429404bd82 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1982,20 +1982,27 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
>  	if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
>  		return;
>  
> -	crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
> +	if (HAS_DOUBLE_BUFFERED_LUT(display))
> +		crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024);
> +	else
> +		crtc_state->dsb_color = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024);
> +
>  	if (!crtc_state->dsb_color)
>  		return;
>  
>  	display->funcs.color->load_luts(crtc_state);
>  
> -	if (crtc_state->use_dsb) {
> +	if (crtc_state->use_dsb && !HAS_DOUBLE_BUFFERED_LUT(display)) {
>  		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
>  		intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color);
>  		intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
>  		intel_dsb_interrupt(crtc_state->dsb_color);
>  	}
>  
> -	intel_dsb_finish(crtc_state->dsb_color);
> +	if (HAS_DOUBLE_BUFFERED_LUT(display))
> +		intel_dsb_gosub_finish(crtc_state->dsb_color);
> +	else
> +		intel_dsb_finish(crtc_state->dsb_color);
>  }
>  
>  void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 69c1790199d3..85e28b4c9e66 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7239,9 +7239,25 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  		}
>  	}
>  
> -	if (new_crtc_state->dsb_color)
> -		intel_dsb_chain(state, new_crtc_state->dsb_commit,
> -				new_crtc_state->dsb_color, true);
> +	if (new_crtc_state->dsb_color) {
> +		if (HAS_DOUBLE_BUFFERED_LUT(display)) {
> +			intel_dsb_gosub(new_crtc_state->dsb_commit,
> +					new_crtc_state->dsb_color);
> +
> +			if (new_crtc_state->use_dsb) {
> +				intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
> +
> +				intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
> +				intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
> +				intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
> +							  new_crtc_state);
> +				intel_dsb_interrupt(new_crtc_state->dsb_commit);
> +			}
> +		} else {
> +			intel_dsb_chain(state, new_crtc_state->dsb_commit,
> +					new_crtc_state->dsb_color, true);
> +		}
> +	}

The logic around the commit completion is getting very messy (it already
was pretty bad though).

maybe something like this:

bool intel_color_use_chained_dsb()
{
	return dsb_color && !HAS_DOUBLE_BUFFERED_LUT;
}

if (use_dsb) {
	do pipe/plane programming
}

if (use_chained_dsb())
	dsb_chain();
else if (dsb_color)
	dsb_gosub();

if (use_dsb && !use_chained_dsb() {
	do commit completion
}

>  
>  	intel_dsb_finish(new_crtc_state->dsb_commit);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 368b0d3417c2..14943b47824b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -157,6 +157,7 @@ struct intel_display_platforms {
>  #define HAS_DMC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dmc)
>  #define HAS_DMC_WAKELOCK(__display)	(DISPLAY_VER(__display) >= 20)
>  #define HAS_DOUBLE_BUFFERED_M_N(__display)	(DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell)
> +#define HAS_DOUBLE_BUFFERED_LUT(__display)	(DISPLAY_VER(__display) >= 30)
>  #define HAS_DOUBLE_WIDE(__display)	(DISPLAY_VER(__display) < 4)
>  #define HAS_DP20(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
>  #define HAS_DPT(__display)		(DISPLAY_VER(__display) >= 13)
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

[PATCH 09/11] drm/i915: Program DB LUT registers before vblank

[Chaitanya Kumar Borah]

Double Buffered LUT registers can be programmed in the active region.
This patch implements the MMIO path for it. Program the registers after
evading vblank. The HW latches on to the registers after delayed vblank.
It takes around 1024 cdclk cycles(~one scanline) for this.

Following assumptions have been made while making this change

 - Current vblank evasion time is sufficient for programming
   the LUT registers.
 - Current guardband calculation would be sufficient for the HW
   to latch on to the new values

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 85e28b4c9e66..df9c992d2939 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6725,10 +6725,12 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
 static void intel_update_crtc(struct intel_atomic_state *state,
 			      struct intel_crtc *crtc)
 {
+	struct intel_display *display = to_intel_display(crtc);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
+	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
 
 	if (new_crtc_state->use_dsb) {
 		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);
@@ -6738,6 +6740,12 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 		/* Perform vblank evasion around commit operation */
 		intel_pipe_update_start(state, crtc);
 
+		if (!modeset &&
+		    intel_crtc_needs_color_update(new_crtc_state) &&
+		    !new_crtc_state->dsb_color &&
+		    HAS_DOUBLE_BUFFERED_LUT(display))
+			intel_color_load_luts(new_crtc_state);
+
 		if (new_crtc_state->dsb_commit)
 			intel_dsb_commit(new_crtc_state->dsb_commit, false);
 
-- 
2.25.1

Re: [PATCH 09/11] drm/i915: Program DB LUT registers before vblank

[Ville Syrjälä]

On Mon, Apr 07, 2025 at 07:53:57PM +0530, Chaitanya Kumar Borah wrote:
> Double Buffered LUT registers can be programmed in the active region.
> This patch implements the MMIO path for it. Program the registers after
> evading vblank. The HW latches on to the registers after delayed vblank.
> It takes around 1024 cdclk cycles(~one scanline) for this.
> 
> Following assumptions have been made while making this change
> 
>  - Current vblank evasion time is sufficient for programming
>    the LUT registers.
>  - Current guardband calculation would be sufficient for the HW
>    to latch on to the new values
> 
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 85e28b4c9e66..df9c992d2939 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6725,10 +6725,12 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
>  static void intel_update_crtc(struct intel_atomic_state *state,
>  			      struct intel_crtc *crtc)
>  {
> +	struct intel_display *display = to_intel_display(crtc);
>  	const struct intel_crtc_state *old_crtc_state =
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> +	bool modeset = intel_crtc_needs_modeset(new_crtc_state);
>  
>  	if (new_crtc_state->use_dsb) {
>  		intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event);
> @@ -6738,6 +6740,12 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>  		/* Perform vblank evasion around commit operation */
>  		intel_pipe_update_start(state, crtc);
>  
> +		if (!modeset &&
> +		    intel_crtc_needs_color_update(new_crtc_state) &&
> +		    !new_crtc_state->dsb_color &&
> +		    HAS_DOUBLE_BUFFERED_LUT(display))
> +			intel_color_load_luts(new_crtc_state);
> +

I think we want to do this in commit_pipe_post_planes() since
a vblank evasion failure for this is probably less drastic than
for plane programming.

>  		if (new_crtc_state->dsb_commit)
>  			intel_dsb_commit(new_crtc_state->dsb_commit, false);
>  
> -- 
> 2.25.1

-- 
Ville Syrjälä
Intel

[PATCH 10/11] drm/i915/color: Do not pre-load LUTs with DB registers

[Chaitanya Kumar Borah]

Since Double Buffered LUT registers can be written in active region
no need to preload them.

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 49429404bd82..ba2b2498d1da 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2027,9 +2027,13 @@ bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
 static bool intel_can_preload_luts(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
+	struct intel_display *display = to_intel_display(state);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 
+	if (HAS_DOUBLE_BUFFERED_LUT(display))
+		return false;
+
 	return !old_crtc_state->post_csc_lut &&
 		!old_crtc_state->pre_csc_lut;
 }
-- 
2.25.1

[PATCH 11/11] drm/i915: Disable updating of LUT values during vblank

[Chaitanya Kumar Borah]

Do not schedule vblank worker for LUT update if the registers are
double buffered

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 5b2603ef2ff7..fd6d52712462 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -418,10 +418,13 @@ int intel_crtc_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
 
 static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
+
 	return crtc_state->hw.active &&
 		!crtc_state->preload_luts &&
 		!intel_crtc_needs_modeset(crtc_state) &&
-		intel_crtc_needs_color_update(crtc_state) &&
+		(intel_crtc_needs_color_update(crtc_state) &&
+		 !HAS_DOUBLE_BUFFERED_LUT(display)) &&
 		!intel_color_uses_dsb(crtc_state) &&
 		!crtc_state->use_dsb;
 }
-- 
2.25.1

✓ CI.Patch_applied: success for drm/xe/display: Program double buffered LUT registers (rev5)

[Patchwork]

== Series Details ==

Series: drm/xe/display: Program double buffered LUT registers (rev5)
URL   : https://patchwork.freedesktop.org/series/142436/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 100ba24787e8 drm-tip: 2025y-04m-07d-13h-47m-40s UTC integration manifest
=== git am output follows ===
Applying: drm/i915/dsb: Extract intel_dsb_ins_align()
Applying: drm/i915/dsb: Extract assert_dsb_tail_is_aligned()
Applying: drm/i915/dsb: Extract intel_dsb_{head,tail}()
Applying: drm/i915/dsb: Implement intel_dsb_gosub()
Applying: drm/i915/dsb: add intel_dsb_gosub_finish()
Applying: drm/i915/dsb: Add support for GOSUB interrupt
Applying: drm/i915: s/dsb_color_vblank/dsb_color
Applying: drm/i915: use GOSUB to program doubled buffered LUT registers
Applying: drm/i915: Program DB LUT registers before vblank
Applying: drm/i915/color: Do not pre-load LUTs with DB registers
Applying: drm/i915: Disable updating of LUT values during vblank

✓ CI.checkpatch: success for drm/xe/display: Program double buffered LUT registers (rev5)

[Patchwork]

== Series Details ==

Series: drm/xe/display: Program double buffered LUT registers (rev5)
URL   : https://patchwork.freedesktop.org/series/142436/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
99e5a866b5e13f134e606a3e29d9508d97826fb3
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 28dba834a7757294aea78b9fbdad1774b1b0a871
Author: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Date:   Mon Apr 7 19:53:59 2025 +0530

    drm/i915: Disable updating of LUT values during vblank
    
    Do not schedule vblank worker for LUT update if the registers are
    double buffered
    
    Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
+ /mt/dim checkpatch 100ba24787e877cd422caa7d08cb046ef4bb769c drm-intel
03d17860f7a4 drm/i915/dsb: Extract intel_dsb_ins_align()
c85187803828 drm/i915/dsb: Extract assert_dsb_tail_is_aligned()
8e7c52bafe7e drm/i915/dsb: Extract intel_dsb_{head,tail}()
09aa328420e2 drm/i915/dsb: Implement intel_dsb_gosub()
60469eedaf5a drm/i915/dsb: add intel_dsb_gosub_finish()
eef14448b9d2 drm/i915/dsb: Add support for GOSUB interrupt
0e393f2fc9d4 drm/i915: s/dsb_color_vblank/dsb_color
dd8cf57cb48d drm/i915: use GOSUB to program doubled buffered LUT registers
7b3935029402 drm/i915: Program DB LUT registers before vblank
131e5b8fbbb4 drm/i915/color: Do not pre-load LUTs with DB registers
28dba834a775 drm/i915: Disable updating of LUT values during vblank

✓ CI.KUnit: success for drm/xe/display: Program double buffered LUT registers (rev5)

[Patchwork]

== Series Details ==

Series: drm/xe/display: Program double buffered LUT registers (rev5)
URL   : https://patchwork.freedesktop.org/series/142436/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:49:43] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:49:47] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:50:13] Starting KUnit Kernel (1/1)...
[14:50:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:50:13] ================== guc_buf (11 subtests) ===================
[14:50:13] [PASSED] test_smallest
[14:50:13] [PASSED] test_largest
[14:50:13] [PASSED] test_granular
[14:50:13] [PASSED] test_unique
[14:50:13] [PASSED] test_overlap
[14:50:13] [PASSED] test_reusable
[14:50:13] [PASSED] test_too_big
[14:50:13] [PASSED] test_flush
[14:50:13] [PASSED] test_lookup
[14:50:13] [PASSED] test_data
[14:50:13] [PASSED] test_class
[14:50:13] ===================== [PASSED] guc_buf =====================
[14:50:13] =================== guc_dbm (7 subtests) ===================
[14:50:13] [PASSED] test_empty
[14:50:13] [PASSED] test_default
[14:50:13] ======================== test_size  ========================
[14:50:13] [PASSED] 4
[14:50:13] [PASSED] 8
[14:50:13] [PASSED] 32
[14:50:13] [PASSED] 256
[14:50:13] ==================== [PASSED] test_size ====================
[14:50:13] ======================= test_reuse  ========================
[14:50:13] [PASSED] 4
[14:50:13] [PASSED] 8
[14:50:13] [PASSED] 32
[14:50:13] [PASSED] 256
[14:50:13] =================== [PASSED] test_reuse ====================
[14:50:13] =================== test_range_overlap  ====================
[14:50:13] [PASSED] 4
[14:50:13] [PASSED] 8
[14:50:13] [PASSED] 32
[14:50:13] [PASSED] 256
[14:50:13] =============== [PASSED] test_range_overlap ================
[14:50:13] =================== test_range_compact  ====================
[14:50:13] [PASSED] 4
[14:50:13] [PASSED] 8
[14:50:13] [PASSED] 32
[14:50:13] [PASSED] 256
[14:50:13] =============== [PASSED] test_range_compact ================
[14:50:13] ==================== test_range_spare  =====================
[14:50:13] [PASSED] 4
[14:50:13] [PASSED] 8
[14:50:13] [PASSED] 32
[14:50:13] [PASSED] 256
[14:50:13] ================ [PASSED] test_range_spare =================
[14:50:13] ===================== [PASSED] guc_dbm =====================
[14:50:13] =================== guc_idm (6 subtests) ===================
[14:50:13] [PASSED] bad_init
[14:50:13] [PASSED] no_init
[14:50:13] [PASSED] init_fini
[14:50:13] [PASSED] check_used
[14:50:13] [PASSED] check_quota
[14:50:13] [PASSED] check_all
[14:50:13] ===================== [PASSED] guc_idm =====================
[14:50:13] ================== no_relay (3 subtests) ===================
[14:50:13] [PASSED] xe_drops_guc2pf_if_not_ready
[14:50:13] [PASSED] xe_drops_guc2vf_if_not_ready
[14:50:13] [PASSED] xe_rejects_send_if_not_ready
[14:50:13] ==================== [PASSED] no_relay =====================
[14:50:13] ================== pf_relay (14 subtests) ==================
[14:50:13] [PASSED] pf_rejects_guc2pf_too_short
[14:50:13] [PASSED] pf_rejects_guc2pf_too_long
[14:50:13] [PASSED] pf_rejects_guc2pf_no_payload
[14:50:13] [PASSED] pf_fails_no_payload
[14:50:13] [PASSED] pf_fails_bad_origin
[14:50:13] [PASSED] pf_fails_bad_type
[14:50:14] [PASSED] pf_txn_reports_error
[14:50:14] [PASSED] pf_txn_sends_pf2guc
[14:50:14] [PASSED] pf_sends_pf2guc
[14:50:14] [SKIPPED] pf_loopback_nop
[14:50:14] [SKIPPED] pf_loopback_echo
[14:50:14] [SKIPPED] pf_loopback_fail
[14:50:14] [SKIPPED] pf_loopback_busy
[14:50:14] [SKIPPED] pf_loopback_retry
[14:50:14] ==================== [PASSED] pf_relay =====================
[14:50:14] ================== vf_relay (3 subtests) ===================
[14:50:14] [PASSED] vf_rejects_guc2vf_too_short
[14:50:14] [PASSED] vf_rejects_guc2vf_too_long
[14:50:14] [PASSED] vf_rejects_guc2vf_no_payload
[14:50:14] ==================== [PASSED] vf_relay =====================
[14:50:14] ================= pf_service (11 subtests) =================
[14:50:14] [PASSED] pf_negotiate_any
[14:50:14] [PASSED] pf_negotiate_base_match
[14:50:14] [PASSED] pf_negotiate_base_newer
[14:50:14] [PASSED] pf_negotiate_base_next
[14:50:14] [SKIPPED] pf_negotiate_base_older
[14:50:14] [PASSED] pf_negotiate_base_prev
[14:50:14] [PASSED] pf_negotiate_latest_match
[14:50:14] [PASSED] pf_negotiate_latest_newer
[14:50:14] [PASSED] pf_negotiate_latest_next
[14:50:14] [SKIPPED] pf_negotiate_latest_older
[14:50:14] [SKIPPED] pf_negotiate_latest_prev
[14:50:14] =================== [PASSED] pf_service ====================
[14:50:14] ===================== lmtt (1 subtest) =====================
[14:50:14] ======================== test_ops  =========================
[14:50:14] [PASSED] 2-level
[14:50:14] [PASSED] multi-level
[14:50:14] ==================== [PASSED] test_ops =====================
[14:50:14] ====================== [PASSED] lmtt =======================
[14:50:14] =================== xe_mocs (2 subtests) ===================
[14:50:14] ================ xe_live_mocs_kernel_kunit  ================
[14:50:14] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[14:50:14] ================ xe_live_mocs_reset_kunit  =================
[14:50:14] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[14:50:14] ==================== [SKIPPED] xe_mocs =====================
[14:50:14] ================= xe_migrate (2 subtests) ==================
[14:50:14] ================= xe_migrate_sanity_kunit  =================
[14:50:14] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[14:50:14] ================== xe_validate_ccs_kunit  ==================
[14:50:14] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[14:50:14] =================== [SKIPPED] xe_migrate ===================
[14:50:14] ================== xe_dma_buf (1 subtest) ==================
[14:50:14] ==================== xe_dma_buf_kunit  =====================
[14:50:14] ================ [SKIPPED] xe_dma_buf_kunit ================
[14:50:14] =================== [SKIPPED] xe_dma_buf ===================
[14:50:14] ================= xe_bo_shrink (1 subtest) =================
[14:50:14] =================== xe_bo_shrink_kunit  ====================
[14:50:14] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[14:50:14] ================== [SKIPPED] xe_bo_shrink ==================
[14:50:14] ==================== xe_bo (2 subtests) ====================
[14:50:14] ================== xe_ccs_migrate_kunit  ===================
[14:50:14] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[14:50:14] ==================== xe_bo_evict_kunit  ====================
[14:50:14] =============== [SKIPPED] xe_bo_evict_kunit ================
[14:50:14] ===================== [SKIPPED] xe_bo ======================
[14:50:14] ==================== args (11 subtests) ====================
[14:50:14] [PASSED] count_args_test
[14:50:14] [PASSED] call_args_example
[14:50:14] [PASSED] call_args_test
[14:50:14] [PASSED] drop_first_arg_example
[14:50:14] [PASSED] drop_first_arg_test
[14:50:14] [PASSED] first_arg_example
[14:50:14] [PASSED] first_arg_test
[14:50:14] [PASSED] last_arg_example
[14:50:14] [PASSED] last_arg_test
[14:50:14] [PASSED] pick_arg_example
[14:50:14] [PASSED] sep_comma_example
[14:50:14] ====================== [PASSED] args =======================
[14:50:14] =================== xe_pci (2 subtests) ====================
[14:50:14] [PASSED] xe_gmdid_graphics_ip
[14:50:14] [PASSED] xe_gmdid_media_ip
[14:50:14] ===================== [PASSED] xe_pci ======================
[14:50:14] =================== xe_rtp (2 subtests) ====================
[14:50:14] =============== xe_rtp_process_to_sr_tests  ================
[14:50:14] [PASSED] coalesce-same-reg
[14:50:14] [PASSED] no-match-no-add
[14:50:14] [PASSED] match-or
[14:50:14] [PASSED] match-or-xfail
[14:50:14] [PASSED] no-match-no-add-multiple-rules
[14:50:14] [PASSED] two-regs-two-entries
[14:50:14] [PASSED] clr-one-set-other
[14:50:14] [PASSED] set-field
[14:50:14] [PASSED] conflict-duplicate
[14:50:14] [PASSED] conflict-not-disjoint
stty: 'standard input': Inappropriate ioctl for device
[14:50:14] [PASSED] conflict-reg-type
[14:50:14] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[14:50:14] ================== xe_rtp_process_tests  ===================
[14:50:14] [PASSED] active1
[14:50:14] [PASSED] active2
[14:50:14] [PASSED] active-inactive
[14:50:14] [PASSED] inactive-active
[14:50:14] [PASSED] inactive-1st_or_active-inactive
[14:50:14] [PASSED] inactive-2nd_or_active-inactive
[14:50:14] [PASSED] inactive-last_or_active-inactive
[14:50:14] [PASSED] inactive-no_or_active-inactive
[14:50:14] ============== [PASSED] xe_rtp_process_tests ===============
[14:50:14] ===================== [PASSED] xe_rtp ======================
[14:50:14] ==================== xe_wa (1 subtest) =====================
[14:50:14] ======================== xe_wa_gt  =========================
[14:50:14] [PASSED] TIGERLAKE (B0)
[14:50:14] [PASSED] DG1 (A0)
[14:50:14] [PASSED] DG1 (B0)
[14:50:14] [PASSED] ALDERLAKE_S (A0)
[14:50:14] [PASSED] ALDERLAKE_S (B0)
[14:50:14] [PASSED] ALDERLAKE_S (C0)
[14:50:14] [PASSED] ALDERLAKE_S (D0)
[14:50:14] [PASSED] ALDERLAKE_P (A0)
[14:50:14] [PASSED] ALDERLAKE_P (B0)
[14:50:14] [PASSED] ALDERLAKE_P (C0)
[14:50:14] [PASSED] ALDERLAKE_S_RPLS (D0)
[14:50:14] [PASSED] ALDERLAKE_P_RPLU (E0)
[14:50:14] [PASSED] DG2_G10 (C0)
[14:50:14] [PASSED] DG2_G11 (B1)
[14:50:14] [PASSED] DG2_G12 (A1)
[14:50:14] [PASSED] METEORLAKE (g:A0, m:A0)
[14:50:14] [PASSED] METEORLAKE (g:A0, m:A0)
[14:50:14] [PASSED] METEORLAKE (g:A0, m:A0)
[14:50:14] [PASSED] LUNARLAKE (g:A0, m:A0)
[14:50:14] [PASSED] LUNARLAKE (g:B0, m:A0)
[14:50:14] [PASSED] BATTLEMAGE (g:A0, m:A1)
[14:50:14] ==================== [PASSED] xe_wa_gt =====================
[14:50:14] ====================== [PASSED] xe_wa ======================
[14:50:14] ============================================================
[14:50:14] Testing complete. Ran 133 tests: passed: 117, skipped: 16
[14:50:14] Elapsed time: 30.875s total, 4.268s configuring, 26.338s building, 0.242s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[14:50:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:50:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:50:36] Starting KUnit Kernel (1/1)...
[14:50:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:50:37] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:50:37] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:50:37] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:50:37] =========== drm_validate_clone_mode (2 subtests) ===========
[14:50:37] ============== drm_test_check_in_clone_mode  ===============
[14:50:37] [PASSED] in_clone_mode
[14:50:37] [PASSED] not_in_clone_mode
[14:50:37] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:50:37] =============== drm_test_check_valid_clones  ===============
[14:50:37] [PASSED] not_in_clone_mode
[14:50:37] [PASSED] valid_clone
[14:50:37] [PASSED] invalid_clone
[14:50:37] =========== [PASSED] drm_test_check_valid_clones ===========
[14:50:37] ============= [PASSED] drm_validate_clone_mode =============
[14:50:37] ============= drm_validate_modeset (1 subtest) =============
[14:50:37] [PASSED] drm_test_check_connector_changed_modeset
[14:50:37] ============== [PASSED] drm_validate_modeset ===============
[14:50:37] ====== drm_test_bridge_get_current_state (2 subtests) ======
[14:50:37] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:50:37] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[14:50:37] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:50:37] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:50:37] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:50:37] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:50:37] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[14:50:37] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:50:37] ================== drm_buddy (7 subtests) ==================
[14:50:37] [PASSED] drm_test_buddy_alloc_limit
[14:50:37] [PASSED] drm_test_buddy_alloc_optimistic
[14:50:37] [PASSED] drm_test_buddy_alloc_pessimistic
[14:50:37] [PASSED] drm_test_buddy_alloc_pathological
[14:50:37] [PASSED] drm_test_buddy_alloc_contiguous
[14:50:37] [PASSED] drm_test_buddy_alloc_clear
[14:50:37] [PASSED] drm_test_buddy_alloc_range_bias
[14:50:37] ==================== [PASSED] drm_buddy ====================
[14:50:37] ============= drm_cmdline_parser (40 subtests) =============
[14:50:37] [PASSED] drm_test_cmdline_force_d_only
[14:50:37] [PASSED] drm_test_cmdline_force_D_only_dvi
[14:50:37] [PASSED] drm_test_cmdline_force_D_only_hdmi
[14:50:37] [PASSED] drm_test_cmdline_force_D_only_not_digital
[14:50:37] [PASSED] drm_test_cmdline_force_e_only
[14:50:37] [PASSED] drm_test_cmdline_res
[14:50:37] [PASSED] drm_test_cmdline_res_vesa
[14:50:37] [PASSED] drm_test_cmdline_res_vesa_rblank
[14:50:37] [PASSED] drm_test_cmdline_res_rblank
[14:50:37] [PASSED] drm_test_cmdline_res_bpp
[14:50:37] [PASSED] drm_test_cmdline_res_refresh
[14:50:37] [PASSED] drm_test_cmdline_res_bpp_refresh
[14:50:37] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[14:50:37] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[14:50:37] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[14:50:37] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[14:50:37] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[14:50:37] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[14:50:37] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[14:50:37] [PASSED] drm_test_cmdline_res_margins_force_on
[14:50:37] [PASSED] drm_test_cmdline_res_vesa_margins
[14:50:37] [PASSED] drm_test_cmdline_name
[14:50:37] [PASSED] drm_test_cmdline_name_bpp
[14:50:37] [PASSED] drm_test_cmdline_name_option
[14:50:37] [PASSED] drm_test_cmdline_name_bpp_option
[14:50:37] [PASSED] drm_test_cmdline_rotate_0
[14:50:37] [PASSED] drm_test_cmdline_rotate_90
[14:50:37] [PASSED] drm_test_cmdline_rotate_180
[14:50:37] [PASSED] drm_test_cmdline_rotate_270
[14:50:37] [PASSED] drm_test_cmdline_hmirror
[14:50:37] [PASSED] drm_test_cmdline_vmirror
[14:50:37] [PASSED] drm_test_cmdline_margin_options
[14:50:37] [PASSED] drm_test_cmdline_multiple_options
[14:50:37] [PASSED] drm_test_cmdline_bpp_extra_and_option
[14:50:37] [PASSED] drm_test_cmdline_extra_and_option
[14:50:37] [PASSED] drm_test_cmdline_freestanding_options
[14:50:37] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[14:50:37] [PASSED] drm_test_cmdline_panel_orientation
[14:50:37] ================ drm_test_cmdline_invalid  =================
[14:50:37] [PASSED] margin_only
[14:50:37] [PASSED] interlace_only
[14:50:37] [PASSED] res_missing_x
[14:50:37] [PASSED] res_missing_y
[14:50:37] [PASSED] res_bad_y
[14:50:37] [PASSED] res_missing_y_bpp
[14:50:37] [PASSED] res_bad_bpp
[14:50:37] [PASSED] res_bad_refresh
[14:50:37] [PASSED] res_bpp_refresh_force_on_off
[14:50:37] [PASSED] res_invalid_mode
[14:50:37] [PASSED] res_bpp_wrong_place_mode
[14:50:37] [PASSED] name_bpp_refresh
[14:50:37] [PASSED] name_refresh
[14:50:37] [PASSED] name_refresh_wrong_mode
[14:50:37] [PASSED] name_refresh_invalid_mode
[14:50:37] [PASSED] rotate_multiple
[14:50:37] [PASSED] rotate_invalid_val
[14:50:37] [PASSED] rotate_truncated
[14:50:37] [PASSED] invalid_option
[14:50:37] [PASSED] invalid_tv_option
[14:50:37] [PASSED] truncated_tv_option
[14:50:37] ============ [PASSED] drm_test_cmdline_invalid =============
[14:50:37] =============== drm_test_cmdline_tv_options  ===============
[14:50:37] [PASSED] NTSC
[14:50:37] [PASSED] NTSC_443
[14:50:37] [PASSED] NTSC_J
[14:50:37] [PASSED] PAL
[14:50:37] [PASSED] PAL_M
[14:50:37] [PASSED] PAL_N
[14:50:37] [PASSED] SECAM
[14:50:37] [PASSED] MONO_525
[14:50:37] [PASSED] MONO_625
[14:50:37] =========== [PASSED] drm_test_cmdline_tv_options ===========
[14:50:37] =============== [PASSED] drm_cmdline_parser ================
[14:50:37] ========== drmm_connector_hdmi_init (20 subtests) ==========
[14:50:37] [PASSED] drm_test_connector_hdmi_init_valid
[14:50:37] [PASSED] drm_test_connector_hdmi_init_bpc_8
[14:50:37] [PASSED] drm_test_connector_hdmi_init_bpc_10
[14:50:37] [PASSED] drm_test_connector_hdmi_init_bpc_12
[14:50:37] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[14:50:37] [PASSED] drm_test_connector_hdmi_init_bpc_null
[14:50:37] [PASSED] drm_test_connector_hdmi_init_formats_empty
[14:50:37] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[14:50:37] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[14:50:37] [PASSED] supported_formats=0x9 yuv420_allowed=1
[14:50:37] [PASSED] supported_formats=0x9 yuv420_allowed=0
[14:50:37] [PASSED] supported_formats=0x3 yuv420_allowed=1
[14:50:37] [PASSED] supported_formats=0x3 yuv420_allowed=0
[14:50:37] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:50:37] [PASSED] drm_test_connector_hdmi_init_null_ddc
[14:50:37] [PASSED] drm_test_connector_hdmi_init_null_product
[14:50:37] [PASSED] drm_test_connector_hdmi_init_null_vendor
[14:50:37] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[14:50:37] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[14:50:37] [PASSED] drm_test_connector_hdmi_init_product_valid
[14:50:37] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[14:50:37] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[14:50:37] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[14:50:37] ========= drm_test_connector_hdmi_init_type_valid  =========
[14:50:37] [PASSED] HDMI-A
[14:50:37] [PASSED] HDMI-B
[14:50:37] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[14:50:37] ======== drm_test_connector_hdmi_init_type_invalid  ========
[14:50:37] [PASSED] Unknown
[14:50:37] [PASSED] VGA
[14:50:37] [PASSED] DVI-I
[14:50:37] [PASSED] DVI-D
[14:50:37] [PASSED] DVI-A
[14:50:37] [PASSED] Composite
[14:50:37] [PASSED] SVIDEO
[14:50:37] [PASSED] LVDS
[14:50:37] [PASSED] Component
[14:50:37] [PASSED] DIN
[14:50:37] [PASSED] DP
[14:50:37] [PASSED] TV
[14:50:37] [PASSED] eDP
[14:50:37] [PASSED] Virtual
[14:50:37] [PASSED] DSI
[14:50:37] [PASSED] DPI
[14:50:37] [PASSED] Writeback
[14:50:37] [PASSED] SPI
[14:50:37] [PASSED] USB
[14:50:37] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[14:50:37] ============ [PASSED] drmm_connector_hdmi_init =============
[14:50:37] ============= drmm_connector_init (3 subtests) =============
[14:50:37] [PASSED] drm_test_drmm_connector_init
[14:50:37] [PASSED] drm_test_drmm_connector_init_null_ddc
[14:50:37] ========= drm_test_drmm_connector_init_type_valid  =========
[14:50:37] [PASSED] Unknown
[14:50:37] [PASSED] VGA
[14:50:37] [PASSED] DVI-I
[14:50:37] [PASSED] DVI-D
[14:50:37] [PASSED] DVI-A
[14:50:37] [PASSED] Composite
[14:50:37] [PASSED] SVIDEO
[14:50:37] [PASSED] LVDS
[14:50:37] [PASSED] Component
[14:50:37] [PASSED] DIN
[14:50:37] [PASSED] DP
[14:50:37] [PASSED] HDMI-A
[14:50:37] [PASSED] HDMI-B
[14:50:37] [PASSED] TV
[14:50:37] [PASSED] eDP
[14:50:37] [PASSED] Virtual
[14:50:37] [PASSED] DSI
[14:50:37] [PASSED] DPI
[14:50:37] [PASSED] Writeback
[14:50:37] [PASSED] SPI
[14:50:37] [PASSED] USB
[14:50:37] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[14:50:37] =============== [PASSED] drmm_connector_init ===============
[14:50:37] ========= drm_connector_dynamic_init (6 subtests) ==========
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_init
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_init_properties
[14:50:37] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[14:50:37] [PASSED] Unknown
[14:50:37] [PASSED] VGA
[14:50:37] [PASSED] DVI-I
[14:50:37] [PASSED] DVI-D
[14:50:37] [PASSED] DVI-A
[14:50:37] [PASSED] Composite
[14:50:37] [PASSED] SVIDEO
[14:50:37] [PASSED] LVDS
[14:50:37] [PASSED] Component
[14:50:37] [PASSED] DIN
[14:50:37] [PASSED] DP
[14:50:37] [PASSED] HDMI-A
[14:50:37] [PASSED] HDMI-B
[14:50:37] [PASSED] TV
[14:50:37] [PASSED] eDP
[14:50:37] [PASSED] Virtual
[14:50:37] [PASSED] DSI
[14:50:37] [PASSED] DPI
[14:50:37] [PASSED] Writeback
[14:50:37] [PASSED] SPI
[14:50:37] [PASSED] USB
[14:50:37] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[14:50:37] ======== drm_test_drm_connector_dynamic_init_name  =========
[14:50:37] [PASSED] Unknown
[14:50:37] [PASSED] VGA
[14:50:37] [PASSED] DVI-I
[14:50:37] [PASSED] DVI-D
[14:50:37] [PASSED] DVI-A
[14:50:37] [PASSED] Composite
[14:50:37] [PASSED] SVIDEO
[14:50:37] [PASSED] LVDS
[14:50:37] [PASSED] Component
[14:50:37] [PASSED] DIN
[14:50:37] [PASSED] DP
[14:50:37] [PASSED] HDMI-A
[14:50:37] [PASSED] HDMI-B
[14:50:37] [PASSED] TV
[14:50:37] [PASSED] eDP
[14:50:37] [PASSED] Virtual
[14:50:37] [PASSED] DSI
[14:50:37] [PASSED] DPI
[14:50:37] [PASSED] Writeback
[14:50:37] [PASSED] SPI
[14:50:37] [PASSED] USB
[14:50:37] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[14:50:37] =========== [PASSED] drm_connector_dynamic_init ============
[14:50:37] ==== drm_connector_dynamic_register_early (4 subtests) =====
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[14:50:37] ====== [PASSED] drm_connector_dynamic_register_early =======
[14:50:37] ======= drm_connector_dynamic_register (7 subtests) ========
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[14:50:37] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[14:50:37] ========= [PASSED] drm_connector_dynamic_register ==========
[14:50:37] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[14:50:37] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[14:50:37] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[14:50:37] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[14:50:37] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[14:50:37] ========== drm_test_get_tv_mode_from_name_valid  ===========
[14:50:37] [PASSED] NTSC
[14:50:37] [PASSED] NTSC-443
[14:50:37] [PASSED] NTSC-J
[14:50:37] [PASSED] PAL
[14:50:37] [PASSED] PAL-M
[14:50:37] [PASSED] PAL-N
[14:50:37] [PASSED] SECAM
[14:50:37] [PASSED] Mono
[14:50:37] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[14:50:37] [PASSED] drm_test_get_tv_mode_from_name_truncated
[14:50:37] ============ [PASSED] drm_get_tv_mode_from_name ============
[14:50:37] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[14:50:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[14:50:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[14:50:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[14:50:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[14:50:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[14:50:37] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[14:50:37] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[14:50:37] [PASSED] VIC 96
[14:50:37] [PASSED] VIC 97
[14:50:37] [PASSED] VIC 101
[14:50:37] [PASSED] VIC 102
[14:50:37] [PASSED] VIC 106
[14:50:37] [PASSED] VIC 107
[14:50:37] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[14:50:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[14:50:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[14:50:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[14:50:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[14:50:37] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[14:50:37] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[14:50:37] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[14:50:37] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[14:50:37] [PASSED] Automatic
[14:50:37] [PASSED] Full
[14:50:37] [PASSED] Limited 16:235
[14:50:37] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[14:50:37] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[14:50:37] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[14:50:37] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[14:50:37] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[14:50:37] [PASSED] RGB
[14:50:37] [PASSED] YUV 4:2:0
[14:50:37] [PASSED] YUV 4:2:2
[14:50:37] [PASSED] YUV 4:4:4
[14:50:37] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[14:50:37] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[14:50:37] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[14:50:37] ============= drm_damage_helper (21 subtests) ==============
[14:50:37] [PASSED] drm_test_damage_iter_no_damage
[14:50:37] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[14:50:37] [PASSED] drm_test_damage_iter_no_damage_src_moved
[14:50:37] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[14:50:37] [PASSED] drm_test_damage_iter_no_damage_not_visible
[14:50:37] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[14:50:37] [PASSED] drm_test_damage_iter_no_damage_no_fb
[14:50:37] [PASSED] drm_test_damage_iter_simple_damage
[14:50:37] [PASSED] drm_test_damage_iter_single_damage
[14:50:37] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[14:50:37] [PASSED] drm_test_damage_iter_single_damage_outside_src
[14:50:37] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[14:50:37] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[14:50:37] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[14:50:37] [PASSED] drm_test_damage_iter_single_damage_src_moved
[14:50:37] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[14:50:37] [PASSED] drm_test_damage_iter_damage
[14:50:37] [PASSED] drm_test_damage_iter_damage_one_intersect
[14:50:37] [PASSED] drm_test_damage_iter_damage_one_outside
[14:50:37] [PASSED] drm_test_damage_iter_damage_src_moved
[14:50:37] [PASSED] drm_test_damage_iter_damage_not_visible
[14:50:37] ================ [PASSED] drm_damage_helper ================
[14:50:37] ============== drm_dp_mst_helper (3 subtests) ==============
[14:50:37] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[14:50:37] [PASSED] Clock 154000 BPP 30 DSC disabled
[14:50:37] [PASSED] Clock 234000 BPP 30 DSC disabled
[14:50:37] [PASSED] Clock 297000 BPP 24 DSC disabled
[14:50:37] [PASSED] Clock 332880 BPP 24 DSC enabled
[14:50:37] [PASSED] Clock 324540 BPP 24 DSC enabled
[14:50:37] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[14:50:37] ============== drm_test_dp_mst_calc_pbn_div  ===============
[14:50:37] [PASSED] Link rate 2000000 lane count 4
[14:50:37] [PASSED] Link rate 2000000 lane count 2
[14:50:37] [PASSED] Link rate 2000000 lane count 1
[14:50:37] [PASSED] Link rate 1350000 lane count 4
[14:50:37] [PASSED] Link rate 1350000 lane count 2
[14:50:37] [PASSED] Link rate 1350000 lane count 1
[14:50:37] [PASSED] Link rate 1000000 lane count 4
[14:50:37] [PASSED] Link rate 1000000 lane count 2
[14:50:37] [PASSED] Link rate 1000000 lane count 1
[14:50:37] [PASSED] Link rate 810000 lane count 4
[14:50:37] [PASSED] Link rate 810000 lane count 2
[14:50:37] [PASSED] Link rate 810000 lane count 1
[14:50:37] [PASSED] Link rate 540000 lane count 4
[14:50:37] [PASSED] Link rate 540000 lane count 2
[14:50:37] [PASSED] Link rate 540000 lane count 1
[14:50:37] [PASSED] Link rate 270000 lane count 4
[14:50:37] [PASSED] Link rate 270000 lane count 2
[14:50:37] [PASSED] Link rate 270000 lane count 1
[14:50:37] [PASSED] Link rate 162000 lane count 4
[14:50:37] [PASSED] Link rate 162000 lane count 2
[14:50:37] [PASSED] Link rate 162000 lane count 1
[14:50:37] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[14:50:37] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[14:50:37] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[14:50:37] [PASSED] DP_POWER_UP_PHY with port number
[14:50:37] [PASSED] DP_POWER_DOWN_PHY with port number
[14:50:37] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[14:50:37] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[14:50:37] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[14:50:37] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[14:50:37] [PASSED] DP_QUERY_PAYLOAD with port number
[14:50:37] [PASSED] DP_QUERY_PAYLOAD with VCPI
[14:50:37] [PASSED] DP_REMOTE_DPCD_READ with port number
[14:50:37] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[14:50:37] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[14:50:37] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[14:50:37] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[14:50:37] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[14:50:37] [PASSED] DP_REMOTE_I2C_READ with port number
[14:50:37] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[14:50:37] [PASSED] DP_REMOTE_I2C_READ with transactions array
[14:50:37] [PASSED] DP_REMOTE_I2C_WRITE with port number
[14:50:37] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[14:50:37] [PASSED] DP_REMOTE_I2C_WRITE with data array
[14:50:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[14:50:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[14:50:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[14:50:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[14:50:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[14:50:37] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[14:50:37] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[14:50:37] ================ [PASSED] drm_dp_mst_helper ================
[14:50:37] ================== drm_exec (7 subtests) ===================
[14:50:37] [PASSED] sanitycheck
[14:50:37] [PASSED] test_lock
[14:50:37] [PASSED] test_lock_unlock
[14:50:37] [PASSED] test_duplicates
[14:50:37] [PASSED] test_prepare
[14:50:37] [PASSED] test_prepare_array
[14:50:37] [PASSED] test_multiple_loops
[14:50:37] ==================== [PASSED] drm_exec =====================
[14:50:37] =========== drm_format_helper_test (18 subtests) ===========
[14:50:37] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[14:50:37] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[14:50:37] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[14:50:37] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[14:50:37] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[14:50:37] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[14:50:37] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[14:50:37] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[14:50:37] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[14:50:37] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[14:50:37] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[14:50:37] ============== drm_test_fb_xrgb8888_to_mono  ===============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[14:50:37] ==================== drm_test_fb_swab  =====================
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ================ [PASSED] drm_test_fb_swab =================
[14:50:37] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[14:50:37] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[14:50:37] [PASSED] single_pixel_source_buffer
[14:50:37] [PASSED] single_pixel_clip_rectangle
[14:50:37] [PASSED] well_known_colors
[14:50:37] [PASSED] destination_pitch
[14:50:37] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[14:50:37] ================= drm_test_fb_clip_offset  =================
[14:50:37] [PASSED] pass through
[14:50:37] [PASSED] horizontal offset
[14:50:37] [PASSED] vertical offset
[14:50:37] [PASSED] horizontal and vertical offset
[14:50:37] [PASSED] horizontal offset (custom pitch)
[14:50:37] [PASSED] vertical offset (custom pitch)
[14:50:37] [PASSED] horizontal and vertical offset (custom pitch)
[14:50:37] ============= [PASSED] drm_test_fb_clip_offset =============
[14:50:37] ============== drm_test_fb_build_fourcc_list  ==============
[14:50:37] [PASSED] no native formats
[14:50:37] [PASSED] XRGB8888 as native format
[14:50:37] [PASSED] remove duplicates
[14:50:37] [PASSED] convert alpha formats
[14:50:37] [PASSED] random formats
[14:50:37] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[14:50:37] =================== drm_test_fb_memcpy  ====================
[14:50:37] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[14:50:37] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[14:50:37] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[14:50:37] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[14:50:37] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[14:50:37] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[14:50:37] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[14:50:37] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[14:50:37] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[14:50:37] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[14:50:37] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[14:50:37] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[14:50:37] =============== [PASSED] drm_test_fb_memcpy ================
[14:50:37] ============= [PASSED] drm_format_helper_test ==============
[14:50:37] ================= drm_format (18 subtests) =================
[14:50:37] [PASSED] drm_test_format_block_width_invalid
[14:50:37] [PASSED] drm_test_format_block_width_one_plane
[14:50:37] [PASSED] drm_test_format_block_width_two_plane
[14:50:37] [PASSED] drm_test_format_block_width_three_plane
[14:50:37] [PASSED] drm_test_format_block_width_tiled
[14:50:37] [PASSED] drm_test_format_block_height_invalid
[14:50:37] [PASSED] drm_test_format_block_height_one_plane
[14:50:37] [PASSED] drm_test_format_block_height_two_plane
[14:50:37] [PASSED] drm_test_format_block_height_three_plane
[14:50:37] [PASSED] drm_test_format_block_height_tiled
[14:50:37] [PASSED] drm_test_format_min_pitch_invalid
[14:50:37] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[14:50:37] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[14:50:37] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[14:50:37] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[14:50:37] [PASSED] drm_test_format_min_pitch_two_plane
[14:50:37] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[14:50:37] [PASSED] drm_test_format_min_pitch_tiled
[14:50:37] =================== [PASSED] drm_format ====================
[14:50:37] ============== drm_framebuffer (10 subtests) ===============
[14:50:37] ========== drm_test_framebuffer_check_src_coords  ==========
[14:50:37] [PASSED] Success: source fits into fb
[14:50:37] [PASSED] Fail: overflowing fb with x-axis coordinate
[14:50:37] [PASSED] Fail: overflowing fb with y-axis coordinate
[14:50:37] [PASSED] Fail: overflowing fb with source width
[14:50:37] [PASSED] Fail: overflowing fb with source height
[14:50:37] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[14:50:37] [PASSED] drm_test_framebuffer_cleanup
[14:50:37] =============== drm_test_framebuffer_create  ===============
[14:50:37] [PASSED] ABGR8888 normal sizes
[14:50:37] [PASSED] ABGR8888 max sizes
[14:50:37] [PASSED] ABGR8888 pitch greater than min required
[14:50:37] [PASSED] ABGR8888 pitch less than min required
[14:50:37] [PASSED] ABGR8888 Invalid width
[14:50:37] [PASSED] ABGR8888 Invalid buffer handle
[14:50:37] [PASSED] No pixel format
[14:50:37] [PASSED] ABGR8888 Width 0
[14:50:37] [PASSED] ABGR8888 Height 0
[14:50:37] [PASSED] ABGR8888 Out of bound height * pitch combination
[14:50:37] [PASSED] ABGR8888 Large buffer offset
[14:50:37] [PASSED] ABGR8888 Buffer offset for inexistent plane
[14:50:37] [PASSED] ABGR8888 Invalid flag
[14:50:37] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[14:50:37] [PASSED] ABGR8888 Valid buffer modifier
[14:50:37] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[14:50:37] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[14:50:37] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[14:50:37] [PASSED] NV12 Normal sizes
[14:50:37] [PASSED] NV12 Max sizes
[14:50:37] [PASSED] NV12 Invalid pitch
[14:50:37] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[14:50:37] [PASSED] NV12 different  modifier per-plane
[14:50:37] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[14:50:37] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[14:50:37] [PASSED] NV12 Modifier for inexistent plane
[14:50:37] [PASSED] NV12 Handle for inexistent plane
[14:50:37] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[14:50:37] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[14:50:37] [PASSED] YVU420 Normal sizes
[14:50:37] [PASSED] YVU420 Max sizes
[14:50:37] [PASSED] YVU420 Invalid pitch
[14:50:37] [PASSED] YVU420 Different pitches
[14:50:37] [PASSED] YVU420 Different buffer offsets/pitches
[14:50:37] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[14:50:37] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[14:50:37] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[14:50:37] [PASSED] YVU420 Valid modifier
[14:50:37] [PASSED] YVU420 Different modifiers per plane
[14:50:37] [PASSED] YVU420 Modifier for inexistent plane
[14:50:37] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[14:50:37] [PASSED] X0L2 Normal sizes
[14:50:37] [PASSED] X0L2 Max sizes
[14:50:37] [PASSED] X0L2 Invalid pitch
[14:50:37] [PASSED] X0L2 Pitch greater than minimum required
[14:50:37] [PASSED] X0L2 Handle for inexistent plane
[14:50:37] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[14:50:37] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[14:50:37] [PASSED] X0L2 Valid modifier
[14:50:37] [PASSED] X0L2 Modifier for inexistent plane
[14:50:37] =========== [PASSED] drm_test_framebuffer_create ===========
[14:50:37] [PASSED] drm_test_framebuffer_free
[14:50:37] [PASSED] drm_test_framebuffer_init
[14:50:37] [PASSED] drm_test_framebuffer_init_bad_format
[14:50:37] [PASSED] drm_test_framebuffer_init_dev_mismatch
[14:50:37] [PASSED] drm_test_framebuffer_lookup
[14:50:37] [PASSED] drm_test_framebuffer_lookup_inexistent
[14:50:37] [PASSED] drm_test_framebuffer_modifiers_not_supported
[14:50:37] ================= [PASSED] drm_framebuffer =================
[14:50:37] ================ drm_gem_shmem (8 subtests) ================
[14:50:37] [PASSED] drm_gem_shmem_test_obj_create
[14:50:37] [PASSED] drm_gem_shmem_test_obj_create_private
[14:50:37] [PASSED] drm_gem_shmem_test_pin_pages
[14:50:37] [PASSED] drm_gem_shmem_test_vmap
[14:50:37] [PASSED] drm_gem_shmem_test_get_pages_sgt
[14:50:37] [PASSED] drm_gem_shmem_test_get_sg_table
[14:50:37] [PASSED] drm_gem_shmem_test_madvise
[14:50:37] [PASSED] drm_gem_shmem_test_purge
[14:50:37] ================== [PASSED] drm_gem_shmem ==================
[14:50:37] === drm_atomic_helper_connector_hdmi_check (23 subtests) ===
[14:50:37] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[14:50:37] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[14:50:37] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[14:50:37] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[14:50:37] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[14:50:37] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[14:50:37] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[14:50:37] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[14:50:37] [PASSED] drm_test_check_disable_connector
[14:50:37] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[14:50:37] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[14:50:37] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[14:50:37] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[14:50:37] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[14:50:37] [PASSED] drm_test_check_output_bpc_dvi
[14:50:37] [PASSED] drm_test_check_output_bpc_format_vic_1
[14:50:37] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[14:50:37] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[14:50:37] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[14:50:37] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[14:50:37] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[14:50:37] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[14:50:37] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[14:50:37] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[14:50:37] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[14:50:37] [PASSED] drm_test_check_broadcast_rgb_value
[14:50:37] [PASSED] drm_test_check_bpc_8_value
[14:50:37] [PASSED] drm_test_check_bpc_10_value
[14:50:37] [PASSED] drm_test_check_bpc_12_value
[14:50:37] [PASSED] drm_test_check_format_value
[14:50:37] [PASSED] drm_test_check_tmds_char_value
[14:50:37] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[14:50:37] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[14:50:37] [PASSED] drm_test_check_mode_valid
[14:50:37] [PASSED] drm_test_check_mode_valid_reject
[14:50:37] [PASSED] drm_test_check_mode_valid_reject_rate
[14:50:37] [PASSED] drm_test_check_mode_valid_reject_max_clock
[14:50:37] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[14:50:37] ================= drm_managed (2 subtests) =================
[14:50:37] [PASSED] drm_test_managed_release_action
[14:50:37] [PASSED] drm_test_managed_run_action
[14:50:37] =================== [PASSED] drm_managed ===================
[14:50:37] =================== drm_mm (6 subtests) ====================
[14:50:37] [PASSED] drm_test_mm_init
[14:50:37] [PASSED] drm_test_mm_debug
[14:50:37] [PASSED] drm_test_mm_align32
[14:50:37] [PASSED] drm_test_mm_align64
[14:50:37] [PASSED] drm_test_mm_lowest
[14:50:37] [PASSED] drm_test_mm_highest
[14:50:37] ===================== [PASSED] drm_mm ======================
[14:50:37] ============= drm_modes_analog_tv (5 subtests) =============
[14:50:37] [PASSED] drm_test_modes_analog_tv_mono_576i
[14:50:37] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[14:50:37] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[14:50:37] [PASSED] drm_test_modes_analog_tv_pal_576i
[14:50:37] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[14:50:37] =============== [PASSED] drm_modes_analog_tv ===============
[14:50:37] ============== drm_plane_helper (2 subtests) ===============
[14:50:37] =============== drm_test_check_plane_state  ================
[14:50:37] [PASSED] clipping_simple
[14:50:37] [PASSED] clipping_rotate_reflect
[14:50:37] [PASSED] positioning_simple
[14:50:37] [PASSED] upscaling
[14:50:37] [PASSED] downscaling
[14:50:37] [PASSED] rounding1
[14:50:37] [PASSED] rounding2
[14:50:37] [PASSED] rounding3
[14:50:37] [PASSED] rounding4
[14:50:37] =========== [PASSED] drm_test_check_plane_state ============
[14:50:37] =========== drm_test_check_invalid_plane_state  ============
[14:50:37] [PASSED] positioning_invalid
[14:50:37] [PASSED] upscaling_invalid
[14:50:37] [PASSED] downscaling_invalid
[14:50:37] ======= [PASSED] drm_test_check_invalid_plane_state ========
[14:50:37] ================ [PASSED] drm_plane_helper =================
[14:50:37] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[14:50:37] ====== drm_test_connector_helper_tv_get_modes_check  =======
[14:50:37] [PASSED] None
[14:50:37] [PASSED] PAL
[14:50:37] [PASSED] NTSC
[14:50:37] [PASSED] Both, NTSC Default
[14:50:37] [PASSED] Both, PAL Default
[14:50:37] [PASSED] Both, NTSC Default, with PAL on command-line
[14:50:37] [PASSED] Both, PAL Default, with NTSC on command-line
[14:50:37] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[14:50:37] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[14:50:37] ================== drm_rect (9 subtests) ===================
[14:50:37] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[14:50:37] [PASSED] drm_test_rect_clip_scaled_not_clipped
[14:50:37] [PASSED] drm_test_rect_clip_scaled_clipped
[14:50:37] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[14:50:37] ================= drm_test_rect_intersect  =================
[14:50:37] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[14:50:37] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[14:50:37] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[14:50:37] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[14:50:37] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[14:50:37] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[14:50:37] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[14:50:37] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[14:50:37] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[14:50:37] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[14:50:37] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[14:50:37] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[14:50:37] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[14:50:37] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[14:50:37] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[14:50:37] ============= [PASSED] drm_test_rect_intersect =============
[14:50:37] ================ drm_test_rect_calc_hscale  ================
[14:50:37] [PASSED] normal use
[14:50:37] [PASSED] out of max range
[14:50:37] [PASSED] out of min range
[14:50:37] [PASSED] zero dst
[14:50:37] [PASSED] negative src
[14:50:37] [PASSED] negative dst
[14:50:37] ============ [PASSED] drm_test_rect_calc_hscale ============
[14:50:37] ================ drm_test_rect_calc_vscale  ================
[14:50:37] [PASSED] normal use
[14:50:37] [PASSED] out of max range
[14:50:37] [PASSED] out of min range
[14:50:37] [PASSED] zero dst
[14:50:37] [PASSED] negative src
[14:50:37] [PASSED] negative dst
[14:50:37] ============ [PASSED] drm_test_rect_calc_vscale ============
[14:50:37] ================== drm_test_rect_rotate  ===================
[14:50:37] [PASSED] reflect-x
[14:50:37] [PASSED] reflect-y
[14:50:37] [PASSED] rotate-0
[14:50:37] [PASSED] rotate-90
[14:50:37] [PASSED] rotate-180
[14:50:37] [PASSED] rotate-270
[14:50:37] ============== [PASSED] drm_test_rect_rotate ===============
[14:50:37] ================ drm_test_rect_rotate_inv  =================
[14:50:37] [PASSED] reflect-x
[14:50:37] [PASSED] reflect-y
[14:50:37] [PASSED] rotate-0
[14:50:37] [PASSED] rotate-90
[14:50:37] [PASSED] rotate-180
[14:50:37] [PASSED] rotate-270
[14:50:37] ============ [PASSED] drm_test_rect_rotate_inv =============
stty: 'standard input': Inappropriate ioctl for device
[14:50:37] ==================== [PASSED] drm_rect =====================
[14:50:37] ============================================================
[14:50:37] Testing complete. Ran 608 tests: passed: 608
[14:50:37] Elapsed time: 22.997s total, 1.726s configuring, 21.097s building, 0.141s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[14:50:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:50:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[14:50:46] Starting KUnit Kernel (1/1)...
[14:50:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:50:46] ================= ttm_device (5 subtests) ==================
[14:50:46] [PASSED] ttm_device_init_basic
[14:50:46] [PASSED] ttm_device_init_multiple
[14:50:46] [PASSED] ttm_device_fini_basic
[14:50:46] [PASSED] ttm_device_init_no_vma_man
[14:50:46] ================== ttm_device_init_pools  ==================
[14:50:46] [PASSED] No DMA allocations, no DMA32 required
[14:50:46] [PASSED] DMA allocations, DMA32 required
[14:50:46] [PASSED] No DMA allocations, DMA32 required
[14:50:46] [PASSED] DMA allocations, no DMA32 required
[14:50:46] ============== [PASSED] ttm_device_init_pools ==============
[14:50:46] =================== [PASSED] ttm_device ====================
[14:50:46] ================== ttm_pool (8 subtests) ===================
[14:50:46] ================== ttm_pool_alloc_basic  ===================
[14:50:46] [PASSED] One page
[14:50:46] [PASSED] More than one page
[14:50:46] [PASSED] Above the allocation limit
[14:50:46] [PASSED] One page, with coherent DMA mappings enabled
[14:50:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:50:46] ============== [PASSED] ttm_pool_alloc_basic ===============
[14:50:46] ============== ttm_pool_alloc_basic_dma_addr  ==============
[14:50:46] [PASSED] One page
[14:50:46] [PASSED] More than one page
[14:50:46] [PASSED] Above the allocation limit
[14:50:46] [PASSED] One page, with coherent DMA mappings enabled
[14:50:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:50:46] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[14:50:46] [PASSED] ttm_pool_alloc_order_caching_match
[14:50:46] [PASSED] ttm_pool_alloc_caching_mismatch
[14:50:46] [PASSED] ttm_pool_alloc_order_mismatch
[14:50:46] [PASSED] ttm_pool_free_dma_alloc
[14:50:46] [PASSED] ttm_pool_free_no_dma_alloc
[14:50:46] [PASSED] ttm_pool_fini_basic
[14:50:46] ==================== [PASSED] ttm_pool =====================
[14:50:46] ================ ttm_resource (8 subtests) =================
[14:50:46] ================= ttm_resource_init_basic  =================
[14:50:46] [PASSED] Init resource in TTM_PL_SYSTEM
[14:50:46] [PASSED] Init resource in TTM_PL_VRAM
[14:50:46] [PASSED] Init resource in a private placement
[14:50:46] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[14:50:46] ============= [PASSED] ttm_resource_init_basic =============
[14:50:46] [PASSED] ttm_resource_init_pinned
[14:50:46] [PASSED] ttm_resource_fini_basic
[14:50:46] [PASSED] ttm_resource_manager_init_basic
[14:50:46] [PASSED] ttm_resource_manager_usage_basic
[14:50:46] [PASSED] ttm_resource_manager_set_used_basic
[14:50:46] [PASSED] ttm_sys_man_alloc_basic
[14:50:46] [PASSED] ttm_sys_man_free_basic
[14:50:46] ================== [PASSED] ttm_resource ===================
[14:50:46] =================== ttm_tt (15 subtests) ===================
[14:50:46] ==================== ttm_tt_init_basic  ====================
[14:50:46] [PASSED] Page-aligned size
[14:50:46] [PASSED] Extra pages requested
[14:50:46] ================ [PASSED] ttm_tt_init_basic ================
[14:50:46] [PASSED] ttm_tt_init_misaligned
[14:50:46] [PASSED] ttm_tt_fini_basic
[14:50:46] [PASSED] ttm_tt_fini_sg
[14:50:46] [PASSED] ttm_tt_fini_shmem
[14:50:46] [PASSED] ttm_tt_create_basic
[14:50:46] [PASSED] ttm_tt_create_invalid_bo_type
[14:50:46] [PASSED] ttm_tt_create_ttm_exists
[14:50:46] [PASSED] ttm_tt_create_failed
[14:50:46] [PASSED] ttm_tt_destroy_basic
[14:50:46] [PASSED] ttm_tt_populate_null_ttm
[14:50:46] [PASSED] ttm_tt_populate_populated_ttm
[14:50:46] [PASSED] ttm_tt_unpopulate_basic
[14:50:46] [PASSED] ttm_tt_unpopulate_empty_ttm
[14:50:46] [PASSED] ttm_tt_swapin_basic
[14:50:46] ===================== [PASSED] ttm_tt ======================
[14:50:46] =================== ttm_bo (14 subtests) ===================
[14:50:46] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[14:50:46] [PASSED] Cannot be interrupted and sleeps
[14:50:46] [PASSED] Cannot be interrupted, locks straight away
[14:50:46] [PASSED] Can be interrupted, sleeps
[14:50:46] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[14:50:46] [PASSED] ttm_bo_reserve_locked_no_sleep
[14:50:46] [PASSED] ttm_bo_reserve_no_wait_ticket
[14:50:46] [PASSED] ttm_bo_reserve_double_resv
[14:50:46] [PASSED] ttm_bo_reserve_interrupted
[14:50:46] [PASSED] ttm_bo_reserve_deadlock
[14:50:46] [PASSED] ttm_bo_unreserve_basic
[14:50:46] [PASSED] ttm_bo_unreserve_pinned
[14:50:46] [PASSED] ttm_bo_unreserve_bulk
[14:50:46] [PASSED] ttm_bo_put_basic
[14:50:46] [PASSED] ttm_bo_put_shared_resv
[14:50:46] [PASSED] ttm_bo_pin_basic
[14:50:46] [PASSED] ttm_bo_pin_unpin_resource
[14:50:46] [PASSED] ttm_bo_multiple_pin_one_unpin
[14:50:46] ===================== [PASSED] ttm_bo ======================
[14:50:46] ============== ttm_bo_validate (22 subtests) ===============
[14:50:46] ============== ttm_bo_init_reserved_sys_man  ===============
[14:50:46] [PASSED] Buffer object for userspace
[14:50:46] [PASSED] Kernel buffer object
[14:50:46] [PASSED] Shared buffer object
[14:50:46] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[14:50:46] ============== ttm_bo_init_reserved_mock_man  ==============
[14:50:46] [PASSED] Buffer object for userspace
[14:50:46] [PASSED] Kernel buffer object
[14:50:46] [PASSED] Shared buffer object
[14:50:46] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[14:50:46] [PASSED] ttm_bo_init_reserved_resv
[14:50:46] ================== ttm_bo_validate_basic  ==================
[14:50:46] [PASSED] Buffer object for userspace
[14:50:46] [PASSED] Kernel buffer object
[14:50:46] [PASSED] Shared buffer object
[14:50:46] ============== [PASSED] ttm_bo_validate_basic ==============
[14:50:46] [PASSED] ttm_bo_validate_invalid_placement
[14:50:46] ============= ttm_bo_validate_same_placement  ==============
[14:50:46] [PASSED] System manager
[14:50:46] [PASSED] VRAM manager
[14:50:46] ========= [PASSED] ttm_bo_validate_same_placement ==========
[14:50:46] [PASSED] ttm_bo_validate_failed_alloc
[14:50:46] [PASSED] ttm_bo_validate_pinned
[14:50:46] [PASSED] ttm_bo_validate_busy_placement
[14:50:46] ================ ttm_bo_validate_multihop  =================
[14:50:46] [PASSED] Buffer object for userspace
[14:50:46] [PASSED] Kernel buffer object
[14:50:46] [PASSED] Shared buffer object
[14:50:46] ============ [PASSED] ttm_bo_validate_multihop =============
[14:50:46] ========== ttm_bo_validate_no_placement_signaled  ==========
[14:50:46] [PASSED] Buffer object in system domain, no page vector
[14:50:46] [PASSED] Buffer object in system domain with an existing page vector
[14:50:46] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[14:50:46] ======== ttm_bo_validate_no_placement_not_signaled  ========
[14:50:46] [PASSED] Buffer object for userspace
[14:50:46] [PASSED] Kernel buffer object
[14:50:46] [PASSED] Shared buffer object
[14:50:46] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[14:50:46] [PASSED] ttm_bo_validate_move_fence_signaled
[14:50:46] ========= ttm_bo_validate_move_fence_not_signaled  =========
[14:50:46] [PASSED] Waits for GPU
[14:50:46] [PASSED] Tries to lock straight away
[14:50:47] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[14:50:47] [PASSED] ttm_bo_validate_swapout
[14:50:47] [PASSED] ttm_bo_validate_happy_evict
[14:50:47] [PASSED] ttm_bo_validate_all_pinned_evict
[14:50:47] [PASSED] ttm_bo_validate_allowed_only_evict
[14:50:47] [PASSED] ttm_bo_validate_deleted_evict
[14:50:47] [PASSED] ttm_bo_validate_busy_domain_evict
[14:50:47] [PASSED] ttm_bo_validate_evict_gutting
[14:50:47] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[14:50:47] ================= [PASSED] ttm_bo_validate =================
[14:50:47] ============================================================
[14:50:47] Testing complete. Ran 102 tests: passed: 102
[14:50:47] Elapsed time: 10.064s total, 1.721s configuring, 7.727s building, 0.525s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.Build: failure for drm/xe/display: Program double buffered LUT registers (rev5)

[Patchwork]

== Series Details ==

Series: drm/xe/display: Program double buffered LUT registers (rev5)
URL   : https://patchwork.freedesktop.org/series/142436/
State : failure

== Summary ==

CC      fs/drop_caches.o
  CC [M]  net/netfilter/x_tables.o
  GEN     lib/crc32table.h
  GEN     lib/crc64table.h
  CC [M]  net/netfilter/xt_tcpudp.o
  CC      fs/sysctls.o
  CC [M]  net/netfilter/xt_mark.o
  CC [M]  net/netfilter/xt_connmark.o
  CC      lib/oid_registry.o
  CC [M]  net/netfilter/xt_nat.o
  CC      fs/fhandle.o
  CC [M]  net/netfilter/xt_AUDIT.o
  CC      lib/crc32.o
  CC      fs/bpf_fs_kfuncs.o
  CC [M]  fs/binfmt_misc.o
  CC [M]  net/netfilter/xt_CHECKSUM.o
  CC      lib/crc64.o
  CC [M]  net/netfilter/xt_CLASSIFY.o
  CC [M]  net/netfilter/xt_CONNSECMARK.o
  CC [M]  net/netfilter/xt_CT.o
  CC [M]  net/netfilter/xt_DSCP.o
  CC [M]  net/netfilter/xt_HL.o
  CC [M]  net/netfilter/xt_HMARK.o
  CC [M]  net/netfilter/xt_LED.o
  CC [M]  net/netfilter/xt_LOG.o
  CC [M]  net/netfilter/xt_NETMAP.o
  CC [M]  net/netfilter/xt_NFLOG.o
  CC [M]  net/netfilter/xt_NFQUEUE.o
  CC [M]  net/netfilter/xt_RATEEST.o
  CC [M]  net/netfilter/xt_REDIRECT.o
  CC [M]  net/netfilter/xt_MASQUERADE.o
  CC [M]  net/netfilter/xt_SECMARK.o
  CC [M]  net/netfilter/xt_TPROXY.o
  LD [M]  fs/nfs/nfsv4.o
  CC [M]  net/netfilter/xt_TCPMSS.o
  AR      kernel/built-in.a
  CC [M]  net/netfilter/xt_TCPOPTSTRIP.o
  CC [M]  net/netfilter/xt_TEE.o
  CC [M]  net/netfilter/xt_TRACE.o
  CC [M]  net/netfilter/xt_IDLETIMER.o
  CC [M]  net/netfilter/xt_addrtype.o
  CC [M]  net/netfilter/xt_bpf.o
  CC [M]  net/netfilter/xt_cluster.o
  CC [M]  net/netfilter/xt_comment.o
  CC [M]  net/netfilter/xt_connbytes.o
  CC [M]  net/netfilter/xt_connlabel.o
  CC [M]  net/netfilter/xt_connlimit.o
  CC [M]  net/netfilter/xt_conntrack.o
  CC [M]  net/netfilter/xt_cpu.o
  AR      lib/built-in.a
  CC [M]  net/netfilter/xt_dccp.o
  CC [M]  net/netfilter/xt_devgroup.o
  CC [M]  net/netfilter/xt_dscp.o
  CC [M]  net/netfilter/xt_ecn.o
  CC [M]  net/netfilter/xt_esp.o
  CC [M]  net/netfilter/xt_hashlimit.o
  CC [M]  net/netfilter/xt_helper.o
  CC [M]  net/netfilter/xt_hl.o
  CC [M]  net/netfilter/xt_ipcomp.o
  CC [M]  net/netfilter/xt_iprange.o
  CC [M]  net/netfilter/xt_l2tp.o
  CC [M]  net/netfilter/xt_length.o
  CC [M]  net/netfilter/xt_limit.o
  CC [M]  net/netfilter/xt_mac.o
  CC [M]  net/netfilter/xt_multiport.o
  CC [M]  net/netfilter/xt_nfacct.o
  CC [M]  net/netfilter/xt_osf.o
  CC [M]  net/netfilter/xt_owner.o
  CC [M]  net/netfilter/xt_cgroup.o
  CC [M]  net/netfilter/xt_physdev.o
  CC [M]  net/netfilter/xt_pkttype.o
  CC [M]  net/netfilter/xt_policy.o
  CC [M]  net/netfilter/xt_quota.o
  CC [M]  net/netfilter/xt_rateest.o
  CC [M]  net/netfilter/xt_realm.o
  CC [M]  net/netfilter/xt_recent.o
  CC [M]  net/netfilter/xt_sctp.o
  CC [M]  net/netfilter/xt_socket.o
  CC [M]  net/netfilter/xt_state.o
  CC [M]  net/netfilter/xt_statistic.o
  CC [M]  net/netfilter/xt_string.o
  CC [M]  net/netfilter/xt_tcpmss.o
  CC [M]  net/netfilter/xt_time.o
  CC [M]  net/netfilter/xt_u32.o
  LD [M]  net/netfilter/nf_conntrack.o
  LD [M]  net/netfilter/nf_conntrack_h323.o
  LD [M]  net/netfilter/nf_nat.o
  LD [M]  net/netfilter/nf_tables.o
  LD [M]  net/netfilter/nf_flow_table.o
  AR      net/netfilter/built-in.a
  AR      fs/built-in.a
  AR      net/built-in.a
  CC [M]  kernel/kheaders.o
make[2]: *** [/kernel/Makefile:2006: .] Error 2
make[1]: *** [/kernel/Makefile:248: __sub-make] Error 2
make[1]: Leaving directory '/kernel/build64-default'
make: *** [Makefile:248: __sub-make] Error 2
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

[PATCH 00/11] drm/xe/display: Program double buffered LUT registers

[Chaitanya Kumar Borah]

From PTL, LUT registers are made double buffered. This helps us
to program them in the active region without any concern of tearing.
This particulary helps in case of displays with high refresh rates
where vblank periods are shorter. Add MMIO and DSB path to program them.

Chaitanya Kumar Borah (7):
  drm/i915/dsb: add intel_dsb_gosub_finish()
  drm/i915/dsb: Add support for GOSUB interrupt
  drm/i915: s/dsb_color_vblank/dsb_color
  drm/i915: use GOSUB to program doubled buffered LUT registers
  drm/i915: Program DB LUT registers before vblank
  drm/i915/color: Do not pre-load LUTs with DB registers
  drm/i915: Disable updating of LUT values during vblank

Ville Syrjälä (4):
  drm/i915/dsb: Extract intel_dsb_ins_align()
  drm/i915/dsb: Extract assert_dsb_tail_is_aligned()
  drm/i915/dsb: Extract intel_dsb_{head,tail}()
  drm/i915/dsb: Implement intel_dsb_gosub()

 drivers/gpu/drm/i915/display/intel_atomic.c   |   4 +-
 drivers/gpu/drm/i915/display/intel_color.c    |  73 ++++++----
 drivers/gpu/drm/i915/display/intel_color.h    |   2 +
 drivers/gpu/drm/i915/display/intel_crtc.c     |   5 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  40 +++---
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   2 +-
 drivers/gpu/drm/i915/display/intel_dsb.c      | 125 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dsb.h      |   3 +
 drivers/gpu/drm/i915/display/intel_dsb_regs.h |   2 +
 10 files changed, 202 insertions(+), 55 deletions(-)

-- 
2.25.1

[PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()

[Chaitanya Kumar Borah]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the code that alings the next instruction to the next
QW boundary into a small helper. I'll have some more uses for
this later.

Also explain why we don't have to zero out the extra DW.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 0ddcdedf5453..c166e02b8af0 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -228,13 +228,25 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
 	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
 }
 
+static void intel_dsb_ins_align(struct intel_dsb *dsb)
+{
+	/*
+	 * Every instruction should be 8 byte aligned.
+	 *
+	 * The only way to get unaligned free_pos is via
+	 * intel_dsb_reg_write_indexed() which already
+	 * makes sure the next dword is zeroed, so no need
+	 * to clear it here.
+	 */
+	dsb->free_pos = ALIGN(dsb->free_pos, 2);
+}
+
 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
 {
 	if (!assert_dsb_has_room(dsb))
 		return;
 
-	/* Every instruction should be 8 byte aligned. */
-	dsb->free_pos = ALIGN(dsb->free_pos, 2);
+	intel_dsb_ins_align(dsb);
 
 	dsb->ins_start_offset = dsb->free_pos;
 	dsb->ins[0] = ldw;
-- 
2.25.1

RE: [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()

[Manna, Animesh]

> -----Original Message-----
> From: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Sent: Tuesday, April 8, 2025 4:30 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>;
> Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; Manna,
> Animesh <animesh.manna@intel.com>
> Subject: [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extract the code that alings the next instruction to the next QW boundary
> into a small helper. I'll have some more uses for this later.
> 
> Also explain why we don't have to zero out the extra DW.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 0ddcdedf5453..c166e02b8af0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -228,13 +228,25 @@ static bool is_dsb_busy(struct intel_display
> *display, enum pipe pipe,
>  	return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) &
> DSB_STATUS_BUSY;  }
> 
> +static void intel_dsb_ins_align(struct intel_dsb *dsb) {
> +	/*
> +	 * Every instruction should be 8 byte aligned.
> +	 *
> +	 * The only way to get unaligned free_pos is via
> +	 * intel_dsb_reg_write_indexed() which already
> +	 * makes sure the next dword is zeroed, so no need
> +	 * to clear it here.
> +	 */
> +	dsb->free_pos = ALIGN(dsb->free_pos, 2); }
> +
>  static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)  {
>  	if (!assert_dsb_has_room(dsb))
>  		return;
> 
> -	/* Every instruction should be 8 byte aligned. */
> -	dsb->free_pos = ALIGN(dsb->free_pos, 2);
> +	intel_dsb_ins_align(dsb);
> 
>  	dsb->ins_start_offset = dsb->free_pos;
>  	dsb->ins[0] = ldw;
> --
> 2.25.1