Re: [Intel-xe] [PATCH 04/15] drm/xe/xe2: Add MCR register steering for media GT

[Matt Atwood <matthew.s.atwood@intel.com>]

On Fri, Aug 11, 2023 at 09:06:07AM -0700, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Xe2 media has a few types of MCR registers, but all except for "GPMXMT"
> can safely steer to instance 0,0.  GPMXMT follows the same rules that
> MTL's OADDRM ranges did, so it can re-use the same enum value.
> 
> Bspec: 71186
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_gt_mcr.c | 26 ++++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index ef9f4044ca1fd..c01799b4efcb5 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -214,6 +214,23 @@ static const struct xe_mmio_range xe2lpg_instance0_steering_table[] = {
>  	{},
>  };
>  
> +static const struct xe_mmio_range xe2lpm_gpmxmt_steering_table[] = {
> +	{ 0x388160, 0x38817F },
> +	{ 0x389480, 0x3894CF },
> +	{},
> +};
> +
> +static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
> +	{ 0x384000, 0x3847DF },         /* GAM, rsvd */
in keeping with the format of the previous patch rsvd is 382000->383FFF
> +	{ 0x384900, 0x384AFF },         /* GAM */
> +	{ 0x389560, 0x3895FF },         /* MEDIAINF */
> +	{ 0x38B600, 0x38B8FF },         /* L3BANK */
> +	{ 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */
> +	{ 0x38F000, 0x38F0FF },         /* GAM */
> +	{ 0x393C00, 0x393C7F },         /* MEDIAINF */
> +	{},
> +};
> +
>  static void init_steering_l3bank(struct xe_gt *gt)
>  {
>  	if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
> @@ -322,7 +339,7 @@ static const struct {
>  	[MSLICE] =	{ "MSLICE",	init_steering_mslice },
>  	[LNCF] =	{ "LNCF",	NULL }, /* initialized by mslice init */
>  	[DSS] =		{ "DSS",	init_steering_dss },
> -	[OADDRM] =	{ "OADDRM",	init_steering_oaddrm },
> +	[OADDRM] =	{ "OADDRM / GPMXMT", init_steering_oaddrm },
>  	[SQIDI_PSMI] =  { "SQIDI_PSMI", init_steering_sqidi_psmi },
>  	[INSTANCE0] =	{ "INSTANCE 0",	init_steering_inst0 },
>  	[IMPLICIT_STEERING] = { "IMPLICIT", NULL },
> @@ -340,7 +357,12 @@ void xe_gt_mcr_init(struct xe_gt *gt)
>  	if (gt->info.type == XE_GT_TYPE_MEDIA) {
>  		drm_WARN_ON(&xe->drm, MEDIA_VER(xe) < 13);
>  
> -		gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
> +		if (MEDIA_VER(xe) >= 20) {
> +			gt->steering[OADDRM].ranges = xe2lpm_gpmxmt_steering_table;
> +			gt->steering[INSTANCE0].ranges = xe2lpm_instance0_steering_table;
> +		} else {
> +			gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
> +		}
>  	} else {
>  		if (GRAPHICS_VER(xe) >= 20) {
>  			gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
> -- 
> 2.40.1
>