Re: [Intel-xe] [PATCH 06/15] drm/xe/xe2: Handle fused-off CCS engines

[Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>]

On 11.08.2023 09:06, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> On Xe2 platforms, availability of the CCS engines is reflected in the
> FUSE4 register.
> 
> Bspec: 62483
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  1 +
>  drivers/gpu/drm/xe/xe_hw_engine.c    | 29 +++++++++++++++++++++++++++-
>  2 files changed, 29 insertions(+), 1 deletion(-)

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 5bc6c7fa4759f..b8dde495b8a32 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -154,6 +154,7 @@
>  
>  /* Fuse readout registers for GT */
>  #define XEHP_FUSE4				XE_REG(0x9114)
> +#define   CCS_EN_MASK				REG_GENMASK(19, 16)
>  #define   GT_L3_EXC_MASK			REG_GENMASK(6, 4)
>  
>  #define GT_VEBOX_VDBOX_DISABLE			XE_REG(0x9140)
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index b8fcc6e985cfc..d2c358e711cb6 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -529,7 +529,7 @@ static void read_copy_fuses(struct xe_gt *gt)
>  	}
>  }
>  
> -static void read_compute_fuses(struct xe_gt *gt)
> +static void read_compute_fuses_from_dss(struct xe_gt *gt)
>  {
>  	struct xe_device *xe = gt_to_xe(gt);
>  
> @@ -556,6 +556,33 @@ static void read_compute_fuses(struct xe_gt *gt)
>  	}
>  }
>  
> +static void read_compute_fuses_from_reg(struct xe_gt *gt)
> +{
> +	struct xe_device *xe = gt_to_xe(gt);
> +	u32 ccs_mask;
> +
> +	ccs_mask = xe_mmio_read32(gt, XEHP_FUSE4);
> +	ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask);
> +
> +	for (int i = XE_HW_ENGINE_CCS0, j = 0; i <= XE_HW_ENGINE_CCS3; ++i, ++j) {
> +		if (!(gt->info.engine_mask & BIT(i)))
> +			continue;
> +
> +		if ((ccs_mask & BIT(j)) == 0) {
> +			gt->info.engine_mask &= ~BIT(i);
> +			drm_info(&xe->drm, "ccs%u fused off\n", j);
> +		}
> +	}
> +}
> +
> +static void read_compute_fuses(struct xe_gt *gt)
> +{
> +	if (GRAPHICS_VER(gt_to_xe(gt)) >= 20)
> +		read_compute_fuses_from_reg(gt);
> +	else
> +		read_compute_fuses_from_dss(gt);
> +}
> +
>  int xe_hw_engines_init_early(struct xe_gt *gt)
>  {
>  	int i;
> -- 
> 2.40.1
>