* [PATCH v2 01/43] drm/xe: Move forcewake to 'gt.pm' substructure
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-07 0:07 ` [PATCH v2 02/43] drm/xe: Create dedicated xe_mmio structure Matt Roper
` (49 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
Forcewake is a general GT power management concept that isn't specific
to MMIO register access. Move the forcewake information for a GT out of
the 'mmio' substruct and into a 'pm' substruct. Also use the gt_to_fw()
helper in a few more places where it was being open-coded.
v2:
- Kerneldoc tweaks. (Lucas)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_device.h | 2 +-
drivers/gpu/drm/xe/xe_gt_types.h | 15 ++++++++++++---
drivers/gpu/drm/xe/xe_reg_sr.c | 9 +++++----
3 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 894f04770454..ec726dcd5f99 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -138,7 +138,7 @@ static inline bool xe_device_uc_enabled(struct xe_device *xe)
static inline struct xe_force_wake *gt_to_fw(struct xe_gt *gt)
{
- return >->mmio.fw;
+ return >->pm.fw;
}
void xe_device_assert_mem_access(struct xe_device *xe);
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 3d1c51de0268..dd6bbef0bbcd 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -145,11 +145,9 @@ struct xe_gt {
/**
* @mmio: mmio info for GT. All GTs within a tile share the same
* register space, but have their own copy of GSI registers at a
- * specific offset, as well as their own forcewake handling.
+ * specific offset.
*/
struct {
- /** @mmio.fw: force wake for GT */
- struct xe_force_wake fw;
/**
* @mmio.adj_limit: adjust MMIO address if address is below this
* value
@@ -159,6 +157,17 @@ struct xe_gt {
u32 adj_offset;
} mmio;
+ /**
+ * @pm: power management info for GT. The driver uses the GT's
+ * "force wake" interface to wake up specific parts of the GT hardware
+ * from C6 sleep states and ensure the hardware remains awake while it
+ * is being actively used.
+ */
+ struct {
+ /** @pm.fw: force wake for GT */
+ struct xe_force_wake fw;
+ } pm;
+
/** @sriov: virtualization data related to GT */
union {
/** @sriov.pf: PF data. Valid only if driver is running as PF */
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index 440ac572f6e5..fb209f1e0f1e 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -15,6 +15,7 @@
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
+#include "xe_device.h"
#include "xe_device_types.h"
#include "xe_force_wake.h"
#include "xe_gt.h"
@@ -194,14 +195,14 @@ void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt)
xe_gt_dbg(gt, "Applying %s save-restore MMIOs\n", sr->name);
- err = xe_force_wake_get(>->mmio.fw, XE_FORCEWAKE_ALL);
+ err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
if (err)
goto err_force_wake;
xa_for_each(&sr->xa, reg, entry)
apply_one_mmio(gt, entry);
- err = xe_force_wake_put(>->mmio.fw, XE_FORCEWAKE_ALL);
+ err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
XE_WARN_ON(err);
return;
@@ -227,7 +228,7 @@ void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe)
drm_dbg(&xe->drm, "Whitelisting %s registers\n", sr->name);
- err = xe_force_wake_get(>->mmio.fw, XE_FORCEWAKE_ALL);
+ err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
if (err)
goto err_force_wake;
@@ -253,7 +254,7 @@ void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe)
xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
}
- err = xe_force_wake_put(>->mmio.fw, XE_FORCEWAKE_ALL);
+ err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
XE_WARN_ON(err);
return;
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 02/43] drm/xe: Create dedicated xe_mmio structure
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
2024-09-07 0:07 ` [PATCH v2 01/43] drm/xe: Move forcewake to 'gt.pm' substructure Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-07 0:07 ` [PATCH v2 03/43] drm/xe: Clarify size of MMIO region Matt Roper
` (48 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
Pull the 'mmio' substructure from xe_tile out into a dedicated type.
Future patches will expand this structure and then eventually move MMIO
read/write operations over to using this type.
v2:
- Fix kerneldoc of 'size' field. The rename/refocusing of this field
got moved to the next patch of the series. (Lucas)
- Correct commit message; it's the tile, not the device, mmio that's
been pulled out to a separate type. (Michal)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 24 +++++++++++++++++-------
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index ec7eb7811126..5d5b7a9199d8 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -107,6 +107,22 @@ struct xe_mem_region {
void __iomem *mapping;
};
+/**
+ * struct xe_mmio - register mmio structure
+ *
+ * Represents an MMIO region that the CPU may use to access registers. A
+ * region may share its IO map with other regions (e.g., all GTs within a
+ * tile share the same map with their parent tile, but represent different
+ * subregions of the overall IO space).
+ */
+struct xe_mmio {
+ /** @regs: Map used to access registers. */
+ void __iomem *regs;
+
+ /** @size: Size of the map. */
+ size_t size;
+};
+
/**
* struct xe_tile - hardware tile structure
*
@@ -148,13 +164,7 @@ struct xe_tile {
* * 4MB-8MB: reserved
* * 8MB-16MB: global GTT
*/
- struct {
- /** @mmio.size: size of tile's MMIO space */
- size_t size;
-
- /** @mmio.regs: pointer to tile's MMIO space (starting with registers) */
- void __iomem *regs;
- } mmio;
+ struct xe_mmio mmio;
/**
* @mmio_ext: MMIO-extension info for a tile.
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 03/43] drm/xe: Clarify size of MMIO region
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
2024-09-07 0:07 ` [PATCH v2 01/43] drm/xe: Move forcewake to 'gt.pm' substructure Matt Roper
2024-09-07 0:07 ` [PATCH v2 02/43] drm/xe: Create dedicated xe_mmio structure Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-07 0:07 ` [PATCH v2 04/43] drm/xe: Move GSI offset adjustment fields into 'struct xe_mmio' Matt Roper
` (47 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
xe_mmio currently has a size parameter that is assigned but never used
anywhere. The current values assigned appear to be the size of the BAR
region assigned for the tile (both for registers and other purposes such
as the GGTT). Since the current field isn't being used for anything,
change the assignments to 4MB (the size of the register region on all
current platform) and rename the field to 'regs_size' to more clearly
describe what it represents. We can use this value in later patches to
help ensure no register accesses accidentally go past the end of the
desired register space (which might not be caught easily if they still
fall within the iomap).
v2:
- s/regs_length/regs_size/ (Lucas)
- Clarify kerneldoc description (Lucas)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 10 ++++++++--
drivers/gpu/drm/xe/xe_mmio.c | 10 ++++++++--
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 5d5b7a9199d8..ecf95801743d 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -119,8 +119,14 @@ struct xe_mmio {
/** @regs: Map used to access registers. */
void __iomem *regs;
- /** @size: Size of the map. */
- size_t size;
+ /**
+ * @regs_size: Length of the register region within the map.
+ *
+ * The size of the iomap set in *regs is generally larger than the
+ * register mmio space since it includes unused regions and/or
+ * non-register regions such as the GGTT PTEs.
+ */
+ size_t regs_size;
};
/**
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 3fd462fda625..f210e7470eae 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -36,13 +36,19 @@ static void tiles_fini(void *arg)
/*
* On multi-tile devices, partition the BAR space for MMIO on each tile,
* possibly accounting for register override on the number of tiles available.
+ * tile_mmio_size contains both the tile's 4MB register space, as well as
+ * additional space for the GTT and other (possibly unused) regions).
* Resulting memory layout is like below:
*
* .----------------------. <- tile_count * tile_mmio_size
* | .... |
* |----------------------| <- 2 * tile_mmio_size
+ * | tile1 GTT + other |
+ * |----------------------| <- 1 * tile_mmio_size + 4MB
* | tile1->mmio.regs |
* |----------------------| <- 1 * tile_mmio_size
+ * | tile0 GTT + other |
+ * |----------------------| <- 4MB
* | tile0->mmio.regs |
* '----------------------' <- 0MB
*/
@@ -90,7 +96,7 @@ static void mmio_multi_tile_setup(struct xe_device *xe, size_t tile_mmio_size)
regs = xe->mmio.regs;
for_each_tile(tile, xe, id) {
- tile->mmio.size = tile_mmio_size;
+ tile->mmio.regs_size = SZ_4M;
tile->mmio.regs = regs;
regs += tile_mmio_size;
}
@@ -172,7 +178,7 @@ int xe_mmio_init(struct xe_device *xe)
}
/* Setup first tile; other tiles (if present) will be setup later. */
- root_tile->mmio.size = SZ_16M;
+ root_tile->mmio.regs_size = SZ_4M;
root_tile->mmio.regs = xe->mmio.regs;
return devm_add_action_or_reset(xe->drm.dev, mmio_fini, xe);
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 04/43] drm/xe: Move GSI offset adjustment fields into 'struct xe_mmio'
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (2 preceding siblings ...)
2024-09-07 0:07 ` [PATCH v2 03/43] drm/xe: Clarify size of MMIO region Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-10 18:02 ` Rodrigo Vivi
2024-09-07 0:07 ` [PATCH v2 05/43] drm/xe: Populate GT's mmio iomap from tile during init Matt Roper
` (46 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
By moving the GSI adjustment fields into 'struct xe_mmio' we can replace
the GT's MMIO substructure with another instance of xe_mmio. At the
moment this means MMIO operations wind up pulling information from two
different places (the tile's xe_mmio for the iomap and the GT's xe_mmio
for the adjustment), but we'll address that in future patches.
The type headers change a bit with this change, meaning that various
files should be including xe_device_types.h instead of (or in addition
to) xe_gt_types.h.
v2:
- Fix pre-existing kerneldoc typo while moving the fields (Lucas)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_assert.h | 2 +-
drivers/gpu/drm/xe/xe_device.h | 1 +
drivers/gpu/drm/xe/xe_device_types.h | 7 ++++++-
drivers/gpu/drm/xe/xe_gt_freq.c | 2 +-
drivers/gpu/drm/xe/xe_gt_printk.h | 2 +-
drivers/gpu/drm/xe/xe_gt_types.h | 11 ++---------
6 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_assert.h b/drivers/gpu/drm/xe/xe_assert.h
index e22bbf57fca7..04d6b95c6d87 100644
--- a/drivers/gpu/drm/xe/xe_assert.h
+++ b/drivers/gpu/drm/xe/xe_assert.h
@@ -10,7 +10,7 @@
#include <drm/drm_print.h>
-#include "xe_device_types.h"
+#include "xe_gt_types.h"
#include "xe_step.h"
/**
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index ec726dcd5f99..ca8d8ef6342b 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -9,6 +9,7 @@
#include <drm/drm_util.h>
#include "xe_device_types.h"
+#include "xe_gt_types.h"
static inline struct xe_device *to_xe_device(const struct drm_device *dev)
{
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index ecf95801743d..85ef36c5d040 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -14,7 +14,6 @@
#include "xe_devcoredump_types.h"
#include "xe_heci_gsc.h"
-#include "xe_gt_types.h"
#include "xe_lmtt_types.h"
#include "xe_memirq_types.h"
#include "xe_oa.h"
@@ -127,6 +126,12 @@ struct xe_mmio {
* non-register regions such as the GGTT PTEs.
*/
size_t regs_size;
+
+ /** adj_limit: adjust MMIO address if address is below this value */
+ u32 adj_limit;
+
+ /** @adj_offset: offset to add to MMIO address when adjusting */
+ u32 adj_offset;
};
/**
diff --git a/drivers/gpu/drm/xe/xe_gt_freq.c b/drivers/gpu/drm/xe/xe_gt_freq.c
index 68a5778b4319..552435951f11 100644
--- a/drivers/gpu/drm/xe/xe_gt_freq.c
+++ b/drivers/gpu/drm/xe/xe_gt_freq.c
@@ -11,9 +11,9 @@
#include <drm/drm_managed.h>
#include <drm/drm_print.h>
-#include "xe_device_types.h"
#include "xe_gt_sysfs.h"
#include "xe_gt_throttle.h"
+#include "xe_gt_types.h"
#include "xe_guc_pc.h"
#include "xe_pm.h"
diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h
index d6228baaff1e..5dc71394372d 100644
--- a/drivers/gpu/drm/xe/xe_gt_printk.h
+++ b/drivers/gpu/drm/xe/xe_gt_printk.h
@@ -8,7 +8,7 @@
#include <drm/drm_print.h>
-#include "xe_device_types.h"
+#include "xe_gt_types.h"
#define xe_gt_printk(_gt, _level, _fmt, ...) \
drm_##_level(>_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index dd6bbef0bbcd..a287b98ee70b 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -6,6 +6,7 @@
#ifndef _XE_GT_TYPES_H_
#define _XE_GT_TYPES_H_
+#include "xe_device_types.h"
#include "xe_force_wake_types.h"
#include "xe_gt_idle_types.h"
#include "xe_gt_sriov_pf_types.h"
@@ -147,15 +148,7 @@ struct xe_gt {
* register space, but have their own copy of GSI registers at a
* specific offset.
*/
- struct {
- /**
- * @mmio.adj_limit: adjust MMIO address if address is below this
- * value
- */
- u32 adj_limit;
- /** @mmio.adj_offset: offect to add to MMIO address when adjusting */
- u32 adj_offset;
- } mmio;
+ struct xe_mmio mmio;
/**
* @pm: power management info for GT. The driver uses the GT's
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 04/43] drm/xe: Move GSI offset adjustment fields into 'struct xe_mmio'
2024-09-07 0:07 ` [PATCH v2 04/43] drm/xe: Move GSI offset adjustment fields into 'struct xe_mmio' Matt Roper
@ 2024-09-10 18:02 ` Rodrigo Vivi
2024-09-12 13:30 ` Jani Nikula
0 siblings, 1 reply; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:02 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe, Lucas De Marchi
On Fri, Sep 06, 2024 at 05:07:53PM -0700, Matt Roper wrote:
> By moving the GSI adjustment fields into 'struct xe_mmio' we can replace
> the GT's MMIO substructure with another instance of xe_mmio. At the
> moment this means MMIO operations wind up pulling information from two
> different places (the tile's xe_mmio for the iomap and the GT's xe_mmio
> for the adjustment), but we'll address that in future patches.
>
> The type headers change a bit with this change, meaning that various
> files should be including xe_device_types.h instead of (or in addition
> to) xe_gt_types.h.
>
> v2:
> - Fix pre-existing kerneldoc typo while moving the fields (Lucas)
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_assert.h | 2 +-
> drivers/gpu/drm/xe/xe_device.h | 1 +
> drivers/gpu/drm/xe/xe_device_types.h | 7 ++++++-
> drivers/gpu/drm/xe/xe_gt_freq.c | 2 +-
> drivers/gpu/drm/xe/xe_gt_printk.h | 2 +-
> drivers/gpu/drm/xe/xe_gt_types.h | 11 ++---------
> 6 files changed, 12 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_assert.h b/drivers/gpu/drm/xe/xe_assert.h
> index e22bbf57fca7..04d6b95c6d87 100644
> --- a/drivers/gpu/drm/xe/xe_assert.h
> +++ b/drivers/gpu/drm/xe/xe_assert.h
> @@ -10,7 +10,7 @@
>
> #include <drm/drm_print.h>
>
> -#include "xe_device_types.h"
> +#include "xe_gt_types.h"
> #include "xe_step.h"
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
> index ec726dcd5f99..ca8d8ef6342b 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -9,6 +9,7 @@
> #include <drm/drm_util.h>
>
> #include "xe_device_types.h"
> +#include "xe_gt_types.h"
>
> static inline struct xe_device *to_xe_device(const struct drm_device *dev)
> {
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index ecf95801743d..85ef36c5d040 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -14,7 +14,6 @@
>
> #include "xe_devcoredump_types.h"
> #include "xe_heci_gsc.h"
> -#include "xe_gt_types.h"
> #include "xe_lmtt_types.h"
> #include "xe_memirq_types.h"
> #include "xe_oa.h"
> @@ -127,6 +126,12 @@ struct xe_mmio {
> * non-register regions such as the GGTT PTEs.
> */
> size_t regs_size;
> +
> + /** adj_limit: adjust MMIO address if address is below this value */
^
missing '@' in here.
hard to spot even after seeing CI failure:
drivers/gpu/drm/xe/xe_device_types.h:147: warning: Function parameter or struct member 'adj_limit' not described in 'xe_mmio
> + u32 adj_limit;
> +
> + /** @adj_offset: offset to add to MMIO address when adjusting */
> + u32 adj_offset;
> };
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_gt_freq.c b/drivers/gpu/drm/xe/xe_gt_freq.c
> index 68a5778b4319..552435951f11 100644
> --- a/drivers/gpu/drm/xe/xe_gt_freq.c
> +++ b/drivers/gpu/drm/xe/xe_gt_freq.c
> @@ -11,9 +11,9 @@
> #include <drm/drm_managed.h>
> #include <drm/drm_print.h>
>
> -#include "xe_device_types.h"
> #include "xe_gt_sysfs.h"
> #include "xe_gt_throttle.h"
> +#include "xe_gt_types.h"
> #include "xe_guc_pc.h"
> #include "xe_pm.h"
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h
> index d6228baaff1e..5dc71394372d 100644
> --- a/drivers/gpu/drm/xe/xe_gt_printk.h
> +++ b/drivers/gpu/drm/xe/xe_gt_printk.h
> @@ -8,7 +8,7 @@
>
> #include <drm/drm_print.h>
>
> -#include "xe_device_types.h"
> +#include "xe_gt_types.h"
>
> #define xe_gt_printk(_gt, _level, _fmt, ...) \
> drm_##_level(>_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> index dd6bbef0bbcd..a287b98ee70b 100644
> --- a/drivers/gpu/drm/xe/xe_gt_types.h
> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> @@ -6,6 +6,7 @@
> #ifndef _XE_GT_TYPES_H_
> #define _XE_GT_TYPES_H_
>
> +#include "xe_device_types.h"
> #include "xe_force_wake_types.h"
> #include "xe_gt_idle_types.h"
> #include "xe_gt_sriov_pf_types.h"
> @@ -147,15 +148,7 @@ struct xe_gt {
> * register space, but have their own copy of GSI registers at a
> * specific offset.
> */
> - struct {
> - /**
> - * @mmio.adj_limit: adjust MMIO address if address is below this
> - * value
> - */
> - u32 adj_limit;
> - /** @mmio.adj_offset: offect to add to MMIO address when adjusting */
> - u32 adj_offset;
> - } mmio;
> + struct xe_mmio mmio;
>
> /**
> * @pm: power management info for GT. The driver uses the GT's
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [PATCH v2 04/43] drm/xe: Move GSI offset adjustment fields into 'struct xe_mmio'
2024-09-10 18:02 ` Rodrigo Vivi
@ 2024-09-12 13:30 ` Jani Nikula
0 siblings, 0 replies; 83+ messages in thread
From: Jani Nikula @ 2024-09-12 13:30 UTC (permalink / raw)
To: Rodrigo Vivi, Matt Roper; +Cc: intel-xe, Lucas De Marchi
On Tue, 10 Sep 2024, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Fri, Sep 06, 2024 at 05:07:53PM -0700, Matt Roper wrote:
>> By moving the GSI adjustment fields into 'struct xe_mmio' we can replace
>> the GT's MMIO substructure with another instance of xe_mmio. At the
>> moment this means MMIO operations wind up pulling information from two
>> different places (the tile's xe_mmio for the iomap and the GT's xe_mmio
>> for the adjustment), but we'll address that in future patches.
>>
>> The type headers change a bit with this change, meaning that various
>> files should be including xe_device_types.h instead of (or in addition
>> to) xe_gt_types.h.
>>
>> v2:
>> - Fix pre-existing kerneldoc typo while moving the fields (Lucas)
>>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_assert.h | 2 +-
>> drivers/gpu/drm/xe/xe_device.h | 1 +
>> drivers/gpu/drm/xe/xe_device_types.h | 7 ++++++-
>> drivers/gpu/drm/xe/xe_gt_freq.c | 2 +-
>> drivers/gpu/drm/xe/xe_gt_printk.h | 2 +-
>> drivers/gpu/drm/xe/xe_gt_types.h | 11 ++---------
>> 6 files changed, 12 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_assert.h b/drivers/gpu/drm/xe/xe_assert.h
>> index e22bbf57fca7..04d6b95c6d87 100644
>> --- a/drivers/gpu/drm/xe/xe_assert.h
>> +++ b/drivers/gpu/drm/xe/xe_assert.h
>> @@ -10,7 +10,7 @@
>>
>> #include <drm/drm_print.h>
>>
>> -#include "xe_device_types.h"
>> +#include "xe_gt_types.h"
>> #include "xe_step.h"
>>
>> /**
>> diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
>> index ec726dcd5f99..ca8d8ef6342b 100644
>> --- a/drivers/gpu/drm/xe/xe_device.h
>> +++ b/drivers/gpu/drm/xe/xe_device.h
>> @@ -9,6 +9,7 @@
>> #include <drm/drm_util.h>
>>
>> #include "xe_device_types.h"
>> +#include "xe_gt_types.h"
>>
>> static inline struct xe_device *to_xe_device(const struct drm_device *dev)
>> {
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index ecf95801743d..85ef36c5d040 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -14,7 +14,6 @@
>>
>> #include "xe_devcoredump_types.h"
>> #include "xe_heci_gsc.h"
>> -#include "xe_gt_types.h"
>> #include "xe_lmtt_types.h"
>> #include "xe_memirq_types.h"
>> #include "xe_oa.h"
>> @@ -127,6 +126,12 @@ struct xe_mmio {
>> * non-register regions such as the GGTT PTEs.
>> */
>> size_t regs_size;
>> +
>> + /** adj_limit: adjust MMIO address if address is below this value */
>
> ^
> missing '@' in here.
>
> hard to spot even after seeing CI failure:
>
> drivers/gpu/drm/xe/xe_device_types.h:147: warning: Function parameter or struct member 'adj_limit' not described in 'xe_mmio
i915 does kernel-doc checking during build for both .h and .c when
CONFIG_DRM_I915_WERROR=y. It has reduced these issues a lot.
See the i915 Makefile.
BR,
Jani.
>
>> + u32 adj_limit;
>> +
>> + /** @adj_offset: offset to add to MMIO address when adjusting */
>> + u32 adj_offset;
>> };
>>
>> /**
>> diff --git a/drivers/gpu/drm/xe/xe_gt_freq.c b/drivers/gpu/drm/xe/xe_gt_freq.c
>> index 68a5778b4319..552435951f11 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_freq.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_freq.c
>> @@ -11,9 +11,9 @@
>> #include <drm/drm_managed.h>
>> #include <drm/drm_print.h>
>>
>> -#include "xe_device_types.h"
>> #include "xe_gt_sysfs.h"
>> #include "xe_gt_throttle.h"
>> +#include "xe_gt_types.h"
>> #include "xe_guc_pc.h"
>> #include "xe_pm.h"
>>
>> diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h
>> index d6228baaff1e..5dc71394372d 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_printk.h
>> +++ b/drivers/gpu/drm/xe/xe_gt_printk.h
>> @@ -8,7 +8,7 @@
>>
>> #include <drm/drm_print.h>
>>
>> -#include "xe_device_types.h"
>> +#include "xe_gt_types.h"
>>
>> #define xe_gt_printk(_gt, _level, _fmt, ...) \
>> drm_##_level(>_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
>> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
>> index dd6bbef0bbcd..a287b98ee70b 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_types.h
>> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
>> @@ -6,6 +6,7 @@
>> #ifndef _XE_GT_TYPES_H_
>> #define _XE_GT_TYPES_H_
>>
>> +#include "xe_device_types.h"
>> #include "xe_force_wake_types.h"
>> #include "xe_gt_idle_types.h"
>> #include "xe_gt_sriov_pf_types.h"
>> @@ -147,15 +148,7 @@ struct xe_gt {
>> * register space, but have their own copy of GSI registers at a
>> * specific offset.
>> */
>> - struct {
>> - /**
>> - * @mmio.adj_limit: adjust MMIO address if address is below this
>> - * value
>> - */
>> - u32 adj_limit;
>> - /** @mmio.adj_offset: offect to add to MMIO address when adjusting */
>> - u32 adj_offset;
>> - } mmio;
>> + struct xe_mmio mmio;
>>
>> /**
>> * @pm: power management info for GT. The driver uses the GT's
>> --
>> 2.45.2
>>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 05/43] drm/xe: Populate GT's mmio iomap from tile during init
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (3 preceding siblings ...)
2024-09-07 0:07 ` [PATCH v2 04/43] drm/xe: Move GSI offset adjustment fields into 'struct xe_mmio' Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-07 0:07 ` [PATCH v2 06/43] drm/xe: Switch mmio_ext to use 'struct xe_mmio' Matt Roper
` (45 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
Each GT should share the same register iomap as its parent tile. Future
patches will switch to access the iomap through the GT's mmio substruct
rather than through the tile.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 3bce0e550a63..5a6833bf9f56 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -716,6 +716,8 @@ static int xe_info_init(struct xe_device *xe,
gt->info.type = XE_GT_TYPE_MAIN;
gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
gt->info.engine_mask = graphics_desc->hw_engine_mask;
+ gt->mmio.regs = tile->mmio.regs;
+ gt->mmio.regs_size = tile->mmio.regs_size;
if (MEDIA_VER(xe) < 13 && media_desc)
gt->info.engine_mask |= media_desc->hw_engine_mask;
@@ -734,6 +736,8 @@ static int xe_info_init(struct xe_device *xe,
gt->info.type = XE_GT_TYPE_MEDIA;
gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
gt->info.engine_mask = media_desc->hw_engine_mask;
+ gt->mmio.regs = tile->mmio.regs;
+ gt->mmio.regs_size = tile->mmio.regs_size;
gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET;
gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH;
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 06/43] drm/xe: Switch mmio_ext to use 'struct xe_mmio'
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (4 preceding siblings ...)
2024-09-07 0:07 ` [PATCH v2 05/43] drm/xe: Populate GT's mmio iomap from tile during init Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-07 0:07 ` [PATCH v2 07/43] drm/xe: Add xe_tile backpointer to xe_mmio Matt Roper
` (44 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
The mmio_ext stuff is completely unused right now, but it isn't
providing any functionality that couldn't be treated as a regular mmio
space.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 8 +-------
drivers/gpu/drm/xe/xe_mmio.c | 2 +-
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 85ef36c5d040..e6675e9ba6e1 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -182,13 +182,7 @@ struct xe_tile {
*
* Each tile has its own additional 256MB (28-bit) MMIO-extension space.
*/
- struct {
- /** @mmio_ext.size: size of tile's additional MMIO-extension space */
- size_t size;
-
- /** @mmio_ext.regs: pointer to tile's additional MMIO-extension space */
- void __iomem *regs;
- } mmio_ext;
+ struct xe_mmio mmio_ext;
/** @mem: memory management info for tile */
struct {
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index f210e7470eae..2f72516e0132 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -132,7 +132,7 @@ static void mmio_extension_setup(struct xe_device *xe, size_t tile_mmio_size,
regs = xe->mmio.regs + tile_mmio_size * xe->info.tile_count;
for_each_tile(tile, xe, id) {
- tile->mmio_ext.size = tile_mmio_ext_size;
+ tile->mmio_ext.regs_size = tile_mmio_ext_size;
tile->mmio_ext.regs = regs;
regs += tile_mmio_ext_size;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 07/43] drm/xe: Add xe_tile backpointer to xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (5 preceding siblings ...)
2024-09-07 0:07 ` [PATCH v2 06/43] drm/xe: Switch mmio_ext to use 'struct xe_mmio' Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-07 0:07 ` [PATCH v2 08/43] drm/xe: Adjust mmio code to pass VF substructure to SRIOV code Matt Roper
` (43 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Michal Wajdeczko, Lucas De Marchi
Once MMIO operations stop being (incorrectly) tied to a GT, we'll still
need a backpointer for feature checks, message logging, and tracepoints.
Use a tile backpointer since that may allow the most useful debugging
output, while also providing access to the xe_device.
v2:
- Make backpointer an xe_tile instead of xe_device. (Michal)
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> # v1
---
drivers/gpu/drm/xe/xe_device_types.h | 3 +++
drivers/gpu/drm/xe/xe_mmio.c | 3 +++
drivers/gpu/drm/xe/xe_pci.c | 2 ++
3 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index e6675e9ba6e1..27fd16bedb4a 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -115,6 +115,9 @@ struct xe_mem_region {
* subregions of the overall IO space).
*/
struct xe_mmio {
+ /** @tile: Backpointer to tile, used for tracing */
+ struct xe_tile *tile;
+
/** @regs: Map used to access registers. */
void __iomem *regs;
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 2f72516e0132..46924f404241 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -98,6 +98,7 @@ static void mmio_multi_tile_setup(struct xe_device *xe, size_t tile_mmio_size)
for_each_tile(tile, xe, id) {
tile->mmio.regs_size = SZ_4M;
tile->mmio.regs = regs;
+ tile->mmio.tile = tile;
regs += tile_mmio_size;
}
}
@@ -134,6 +135,7 @@ static void mmio_extension_setup(struct xe_device *xe, size_t tile_mmio_size,
for_each_tile(tile, xe, id) {
tile->mmio_ext.regs_size = tile_mmio_ext_size;
tile->mmio_ext.regs = regs;
+ tile->mmio_ext.tile = tile;
regs += tile_mmio_ext_size;
}
}
@@ -180,6 +182,7 @@ int xe_mmio_init(struct xe_device *xe)
/* Setup first tile; other tiles (if present) will be setup later. */
root_tile->mmio.regs_size = SZ_4M;
root_tile->mmio.regs = xe->mmio.regs;
+ root_tile->mmio.tile = root_tile;
return devm_add_action_or_reset(xe->drm.dev, mmio_fini, xe);
}
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 5a6833bf9f56..9914d7d4b9de 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -718,6 +718,7 @@ static int xe_info_init(struct xe_device *xe,
gt->info.engine_mask = graphics_desc->hw_engine_mask;
gt->mmio.regs = tile->mmio.regs;
gt->mmio.regs_size = tile->mmio.regs_size;
+ gt->mmio.tile = tile;
if (MEDIA_VER(xe) < 13 && media_desc)
gt->info.engine_mask |= media_desc->hw_engine_mask;
@@ -740,6 +741,7 @@ static int xe_info_init(struct xe_device *xe,
gt->mmio.regs_size = tile->mmio.regs_size;
gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET;
gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH;
+ gt->mmio.tile = tile;
/*
* FIXME: At the moment multi-tile and standalone media are
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 08/43] drm/xe: Adjust mmio code to pass VF substructure to SRIOV code
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (6 preceding siblings ...)
2024-09-07 0:07 ` [PATCH v2 07/43] drm/xe: Add xe_tile backpointer to xe_mmio Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-07 0:07 ` [PATCH v2 09/43] drm/xe: Switch MMIO interface to take xe_mmio instead of xe_gt Matt Roper
` (42 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Michal Wajdeczko, Lucas De Marchi
Although we want to break the GT-centric nature of the MMIO code in the
general driver, the SRIOV handling still relies on data in a VF
substructure of the GT. So add a GT backpointer, but name it
sriov_vf_gt to make it clear that it's only for this one specific
special case and will not be set or usable for anything else.
v2:
- Store backpointer to the GT itself rather than the SRIOV-specific
substructure. (Michal)
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> # v1
---
drivers/gpu/drm/xe/xe_device_types.h | 8 ++++++++
drivers/gpu/drm/xe/xe_pci.c | 5 +++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 27fd16bedb4a..1bd6f677a772 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -121,6 +121,14 @@ struct xe_mmio {
/** @regs: Map used to access registers. */
void __iomem *regs;
+ /**
+ * @sriov_vf_gt: Backpointer to GT.
+ *
+ * This pointer is only set for GT MMIO regions and only when running
+ * as an SRIOV VF structure
+ */
+ struct xe_gt *sriov_vf_gt;
+
/**
* @regs_size: Length of the register region within the map.
*
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 9914d7d4b9de..aa0c29450b4a 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -719,6 +719,9 @@ static int xe_info_init(struct xe_device *xe,
gt->mmio.regs = tile->mmio.regs;
gt->mmio.regs_size = tile->mmio.regs_size;
gt->mmio.tile = tile;
+ if (IS_SRIOV_VF(xe))
+ gt->mmio.sriov_vf_gt = gt;
+
if (MEDIA_VER(xe) < 13 && media_desc)
gt->info.engine_mask |= media_desc->hw_engine_mask;
@@ -742,6 +745,8 @@ static int xe_info_init(struct xe_device *xe,
gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET;
gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH;
gt->mmio.tile = tile;
+ if (IS_SRIOV_VF(xe))
+ gt->mmio.sriov_vf_gt = gt;
/*
* FIXME: At the moment multi-tile and standalone media are
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 09/43] drm/xe: Switch MMIO interface to take xe_mmio instead of xe_gt
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (7 preceding siblings ...)
2024-09-07 0:07 ` [PATCH v2 08/43] drm/xe: Adjust mmio code to pass VF substructure to SRIOV code Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-07 0:07 ` [PATCH v2 10/43] drm/xe/irq: Convert register access to use xe_mmio Matt Roper
` (41 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Since much of the MMIO register access done by the driver is to non-GT
registers, use of 'xe_gt' in these interfaces has been a long-standing
design flaw that's been hard to disentangle.
To avoid a flag day across the whole driver, munge the function names
and add temporary compatibility macros with the original function names
that can accept either the new xe_mmio or the old xe_gt structure as a
parameter. This will allow us to slowly convert parts of the driver
over to the new interface independently.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_mmio.c | 131 ++++++++++++++++------------------
drivers/gpu/drm/xe/xe_mmio.h | 76 +++++++++++++++-----
drivers/gpu/drm/xe/xe_trace.h | 7 +-
3 files changed, 126 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 46924f404241..9ea0973337ed 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -67,16 +67,16 @@ static void mmio_multi_tile_setup(struct xe_device *xe, size_t tile_mmio_size)
/* Possibly override number of tile based on configuration register */
if (!xe->info.skip_mtcfg) {
- struct xe_gt *gt = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
u8 tile_count;
u32 mtcfg;
/*
* Although the per-tile mmio regs are not yet initialized, this
- * is fine as it's going to the root gt, that's guaranteed to be
- * initialized earlier in xe_mmio_init()
+ * is fine as it's going to the root tile's mmio, that's
+ * guaranteed to be initialized earlier in xe_mmio_init()
*/
- mtcfg = xe_mmio_read64_2x32(gt, XEHP_MTCFG_ADDR);
+ mtcfg = xe_mmio_read64_2x32(mmio, XEHP_MTCFG_ADDR);
tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
if (tile_count < xe->info.tile_count) {
@@ -187,116 +187,111 @@ int xe_mmio_init(struct xe_device *xe)
return devm_add_action_or_reset(xe->drm.dev, mmio_fini, xe);
}
-static void mmio_flush_pending_writes(struct xe_gt *gt)
+static void mmio_flush_pending_writes(struct xe_mmio *mmio)
{
#define DUMMY_REG_OFFSET 0x130030
- struct xe_tile *tile = gt_to_tile(gt);
int i;
- if (tile->xe->info.platform != XE_LUNARLAKE)
+ if (mmio->tile->xe->info.platform != XE_LUNARLAKE)
return;
/* 4 dummy writes */
for (i = 0; i < 4; i++)
- writel(0, tile->mmio.regs + DUMMY_REG_OFFSET);
+ writel(0, mmio->regs + DUMMY_REG_OFFSET);
}
-u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)
+u8 __xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)
{
- struct xe_tile *tile = gt_to_tile(gt);
- u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
+ u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
u8 val;
/* Wa_15015404425 */
- mmio_flush_pending_writes(gt);
+ mmio_flush_pending_writes(mmio);
- val = readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
- trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
+ val = readb(mmio->regs + addr);
+ trace_xe_reg_rw(mmio, false, addr, val, sizeof(val));
return val;
}
-u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg)
+u16 __xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg)
{
- struct xe_tile *tile = gt_to_tile(gt);
- u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
+ u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
u16 val;
/* Wa_15015404425 */
- mmio_flush_pending_writes(gt);
+ mmio_flush_pending_writes(mmio);
- val = readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
- trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
+ val = readw(mmio->regs + addr);
+ trace_xe_reg_rw(mmio, false, addr, val, sizeof(val));
return val;
}
-void xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val)
+void __xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val)
{
- struct xe_tile *tile = gt_to_tile(gt);
- u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
+ u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
- trace_xe_reg_rw(gt, true, addr, val, sizeof(val));
+ trace_xe_reg_rw(mmio, true, addr, val, sizeof(val));
- if (!reg.vf && IS_SRIOV_VF(gt_to_xe(gt)))
- xe_gt_sriov_vf_write32(gt, reg, val);
+ if (!reg.vf && mmio->sriov_vf_gt)
+ xe_gt_sriov_vf_write32(mmio->sriov_vf_gt, reg, val);
else
- writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
+ writel(val, mmio->regs + addr);
}
-u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)
+u32 __xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg)
{
- struct xe_tile *tile = gt_to_tile(gt);
- u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
+ u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
u32 val;
/* Wa_15015404425 */
- mmio_flush_pending_writes(gt);
+ mmio_flush_pending_writes(mmio);
- if (!reg.vf && IS_SRIOV_VF(gt_to_xe(gt)))
- val = xe_gt_sriov_vf_read32(gt, reg);
+ if (!reg.vf && mmio->sriov_vf_gt)
+ val = xe_gt_sriov_vf_read32(mmio->sriov_vf_gt, reg);
else
- val = readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);
+ val = readl(mmio->regs + addr);
- trace_xe_reg_rw(gt, false, addr, val, sizeof(val));
+ trace_xe_reg_rw(mmio, false, addr, val, sizeof(val));
return val;
}
-u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set)
+u32 __xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set)
{
u32 old, reg_val;
- old = xe_mmio_read32(gt, reg);
+ old = xe_mmio_read32(mmio, reg);
reg_val = (old & ~clr) | set;
- xe_mmio_write32(gt, reg, reg_val);
+ xe_mmio_write32(mmio, reg, reg_val);
return old;
}
-int xe_mmio_write32_and_verify(struct xe_gt *gt,
- struct xe_reg reg, u32 val, u32 mask, u32 eval)
+int __xe_mmio_write32_and_verify(struct xe_mmio *mmio,
+ struct xe_reg reg, u32 val, u32 mask, u32 eval)
{
u32 reg_val;
- xe_mmio_write32(gt, reg, val);
- reg_val = xe_mmio_read32(gt, reg);
+ xe_mmio_write32(mmio, reg, val);
+ reg_val = xe_mmio_read32(mmio, reg);
return (reg_val & mask) != eval ? -EINVAL : 0;
}
-bool xe_mmio_in_range(const struct xe_gt *gt,
- const struct xe_mmio_range *range,
- struct xe_reg reg)
+bool __xe_mmio_in_range(const struct xe_mmio *mmio,
+ const struct xe_mmio_range *range,
+ struct xe_reg reg)
{
- u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
+ u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
return range && addr >= range->start && addr <= range->end;
}
/**
* xe_mmio_read64_2x32() - Read a 64-bit register as two 32-bit reads
- * @gt: MMIO target GT
+ * @mmio: MMIO target
* @reg: register to read value from
*
* Although Intel GPUs have some 64-bit registers, the hardware officially
@@ -316,21 +311,21 @@ bool xe_mmio_in_range(const struct xe_gt *gt,
*
* Returns the value of the 64-bit register.
*/
-u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg)
+u64 __xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg)
{
struct xe_reg reg_udw = { .addr = reg.addr + 0x4 };
u32 ldw, udw, oldudw, retries;
- reg.addr = xe_mmio_adjusted_addr(gt, reg.addr);
- reg_udw.addr = xe_mmio_adjusted_addr(gt, reg_udw.addr);
+ reg.addr = xe_mmio_adjusted_addr(mmio, reg.addr);
+ reg_udw.addr = xe_mmio_adjusted_addr(mmio, reg_udw.addr);
/* we shouldn't adjust just one register address */
- xe_gt_assert(gt, reg_udw.addr == reg.addr + 0x4);
+ xe_tile_assert(mmio->tile, reg_udw.addr == reg.addr + 0x4);
- oldudw = xe_mmio_read32(gt, reg_udw);
+ oldudw = xe_mmio_read32(mmio, reg_udw);
for (retries = 5; retries; --retries) {
- ldw = xe_mmio_read32(gt, reg);
- udw = xe_mmio_read32(gt, reg_udw);
+ ldw = xe_mmio_read32(mmio, reg);
+ udw = xe_mmio_read32(mmio, reg_udw);
if (udw == oldudw)
break;
@@ -338,14 +333,14 @@ u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg)
oldudw = udw;
}
- xe_gt_WARN(gt, retries == 0,
- "64-bit read of %#x did not stabilize\n", reg.addr);
+ drm_WARN(&mmio->tile->xe->drm, retries == 0,
+ "64-bit read of %#x did not stabilize\n", reg.addr);
return (u64)udw << 32 | ldw;
}
-static int __xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
- u32 *out_val, bool atomic, bool expect_match)
+static int ____xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
+ u32 *out_val, bool atomic, bool expect_match)
{
ktime_t cur = ktime_get_raw();
const ktime_t end = ktime_add_us(cur, timeout_us);
@@ -355,7 +350,7 @@ static int __xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 v
bool check;
for (;;) {
- read = xe_mmio_read32(gt, reg);
+ read = xe_mmio_read32(mmio, reg);
check = (read & mask) == val;
if (!expect_match)
@@ -381,7 +376,7 @@ static int __xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 v
}
if (ret != 0) {
- read = xe_mmio_read32(gt, reg);
+ read = xe_mmio_read32(mmio, reg);
check = (read & mask) == val;
if (!expect_match)
@@ -399,7 +394,7 @@ static int __xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 v
/**
* xe_mmio_wait32() - Wait for a register to match the desired masked value
- * @gt: MMIO target GT
+ * @mmio: MMIO target
* @reg: register to read value from
* @mask: mask to be applied to the value read from the register
* @val: desired value after applying the mask
@@ -416,15 +411,15 @@ static int __xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 v
* @timeout_us for different reasons, specially in non-atomic contexts. Thus,
* it is possible that this function succeeds even after @timeout_us has passed.
*/
-int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
- u32 *out_val, bool atomic)
+int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
+ u32 *out_val, bool atomic)
{
- return __xe_mmio_wait32(gt, reg, mask, val, timeout_us, out_val, atomic, true);
+ return ____xe_mmio_wait32(mmio, reg, mask, val, timeout_us, out_val, atomic, true);
}
/**
* xe_mmio_wait32_not() - Wait for a register to return anything other than the given masked value
- * @gt: MMIO target GT
+ * @mmio: MMIO target
* @reg: register to read value from
* @mask: mask to be applied to the value read from the register
* @val: value not to be matched after applying the mask
@@ -435,8 +430,8 @@ int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 t
* This function works exactly like xe_mmio_wait32() with the exception that
* @val is expected not to be matched.
*/
-int xe_mmio_wait32_not(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
- u32 *out_val, bool atomic)
+int __xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
+ u32 *out_val, bool atomic)
{
- return __xe_mmio_wait32(gt, reg, mask, val, timeout_us, out_val, atomic, false);
+ return ____xe_mmio_wait32(mmio, reg, mask, val, timeout_us, out_val, atomic, false);
}
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 26551410ecc8..ac6846447c52 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -14,25 +14,67 @@ struct xe_reg;
int xe_mmio_init(struct xe_device *xe);
int xe_mmio_probe_tiles(struct xe_device *xe);
-u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg);
-u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg);
-void xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val);
-u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg);
-u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set);
-int xe_mmio_write32_and_verify(struct xe_gt *gt, struct xe_reg reg, u32 val, u32 mask, u32 eval);
-bool xe_mmio_in_range(const struct xe_gt *gt, const struct xe_mmio_range *range, struct xe_reg reg);
-
-u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg);
-int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
- u32 *out_val, bool atomic);
-int xe_mmio_wait32_not(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
- u32 *out_val, bool atomic);
-
-static inline u32 xe_mmio_adjusted_addr(const struct xe_gt *gt, u32 addr)
+/*
+ * Temporary transition helper for xe_gt -> xe_mmio conversion. Allows
+ * continued usage of xe_gt as a parameter to MMIO operations which now
+ * take an xe_mmio structure instead. Will be removed once the driver-wide
+ * conversion is complete.
+ */
+#define __to_xe_mmio(ptr) \
+ _Generic(ptr, \
+ const struct xe_gt *: (&((const struct xe_gt *)(ptr))->mmio), \
+ struct xe_gt *: (&((struct xe_gt *)(ptr))->mmio), \
+ const struct xe_mmio *: (ptr), \
+ struct xe_mmio *: (ptr))
+
+u8 __xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);
+#define xe_mmio_read8(p, reg) __xe_mmio_read8(__to_xe_mmio(p), reg)
+
+u16 __xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);
+#define xe_mmio_read16(p, reg) __xe_mmio_read16(__to_xe_mmio(p), reg)
+
+void __xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);
+#define xe_mmio_write32(p, reg, val) __xe_mmio_write32(__to_xe_mmio(p), reg, val)
+
+u32 __xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg);
+#define xe_mmio_read32(p, reg) __xe_mmio_read32(__to_xe_mmio(p), reg)
+
+u32 __xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set);
+#define xe_mmio_rmw32(p, reg, clr, set) __xe_mmio_rmw32(__to_xe_mmio(p), reg, clr, set)
+
+int __xe_mmio_write32_and_verify(struct xe_mmio *mmio, struct xe_reg reg,
+ u32 val, u32 mask, u32 eval);
+#define xe_mmio_write32_and_verify(p, reg, val, mask, eval) \
+ __xe_mmio_write32_and_verify(__to_xe_mmio(p), reg, val, mask, eval)
+
+bool __xe_mmio_in_range(const struct xe_mmio *mmio,
+ const struct xe_mmio_range *range, struct xe_reg reg);
+#define xe_mmio_in_range(p, range, reg) __xe_mmio_in_range(__to_xe_mmio(p), range, reg)
+
+u64 __xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg);
+#define xe_mmio_read64_2x32(p, reg) __xe_mmio_read64_2x32(__to_xe_mmio(p), reg)
+
+int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
+ u32 timeout_us, u32 *out_val, bool atomic);
+#define xe_mmio_wait32(p, reg, mask, val, timeout_us, out_val, atomic) \
+ __xe_mmio_wait32(__to_xe_mmio(p), reg, mask, val, timeout_us, out_val, atomic)
+
+int __xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,
+ u32 val, u32 timeout_us, u32 *out_val, bool atomic);
+#define xe_mmio_wait32_not(p, reg, mask, val, timeout_us, out_val, atomic) \
+ __xe_mmio_wait32_not(__to_xe_mmio(p), reg, mask, val, timeout_us, out_val, atomic)
+
+static inline u32 __xe_mmio_adjusted_addr(const struct xe_mmio *mmio, u32 addr)
{
- if (addr < gt->mmio.adj_limit)
- addr += gt->mmio.adj_offset;
+ if (addr < mmio->adj_limit)
+ addr += mmio->adj_offset;
return addr;
}
+#define xe_mmio_adjusted_addr(p, addr) __xe_mmio_adjusted_addr(__to_xe_mmio(p), addr)
+
+static inline struct xe_mmio *xe_root_tile_mmio(struct xe_device *xe)
+{
+ return &xe->tiles[0].mmio;
+}
#endif
diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
index 8573d7a87d84..91130ad8999c 100644
--- a/drivers/gpu/drm/xe/xe_trace.h
+++ b/drivers/gpu/drm/xe/xe_trace.h
@@ -21,6 +21,7 @@
#include "xe_vm.h"
#define __dev_name_xe(xe) dev_name((xe)->drm.dev)
+#define __dev_name_tile(tile) __dev_name_xe(tile_to_xe((tile)))
#define __dev_name_gt(gt) __dev_name_xe(gt_to_xe((gt)))
#define __dev_name_eq(q) __dev_name_gt((q)->gt)
@@ -342,12 +343,12 @@ DEFINE_EVENT(xe_hw_fence, xe_hw_fence_try_signal,
);
TRACE_EVENT(xe_reg_rw,
- TP_PROTO(struct xe_gt *gt, bool write, u32 reg, u64 val, int len),
+ TP_PROTO(struct xe_mmio *mmio, bool write, u32 reg, u64 val, int len),
- TP_ARGS(gt, write, reg, val, len),
+ TP_ARGS(mmio, write, reg, val, len),
TP_STRUCT__entry(
- __string(dev, __dev_name_gt(gt))
+ __string(dev, __dev_name_tile(mmio->tile))
__field(u64, val)
__field(u32, reg)
__field(u16, write)
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 10/43] drm/xe/irq: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (8 preceding siblings ...)
2024-09-07 0:07 ` [PATCH v2 09/43] drm/xe: Switch MMIO interface to take xe_mmio instead of xe_gt Matt Roper
@ 2024-09-07 0:07 ` Matt Roper
2024-09-07 0:08 ` [PATCH v2 11/43] drm/xe/pcode: " Matt Roper
` (40 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:07 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
Stop using GT pointers for register access. This misusage has been
especially confusing in interrupt code because even though some of the
interrupts are related to GTs (or engines within GTs), the interrupt
registers themselves live outside the GT, in the sgunit.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_irq.c | 63 +++++++++++++++++++------------------
1 file changed, 32 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 14c3a476597a..07577b418205 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -30,14 +30,14 @@
#define IIR(offset) XE_REG(offset + 0x8)
#define IER(offset) XE_REG(offset + 0xc)
-static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
+static void assert_iir_is_zero(struct xe_mmio *mmio, struct xe_reg reg)
{
u32 val = xe_mmio_read32(mmio, reg);
if (val == 0)
return;
- drm_WARN(>_to_xe(mmio)->drm, 1,
+ drm_WARN(&mmio->tile->xe->drm, 1,
"Interrupt register 0x%x is not zero: 0x%08x\n",
reg.addr, val);
xe_mmio_write32(mmio, reg, 0xffffffff);
@@ -52,7 +52,7 @@ static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
*/
static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)
{
- struct xe_gt *mmio = tile->primary_gt;
+ struct xe_mmio *mmio = &tile->mmio;
/*
* If we're just enabling an interrupt now, it shouldn't already
@@ -70,7 +70,7 @@ static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)
/* Mask and disable all interrupts. */
static void mask_and_disable(struct xe_tile *tile, u32 irqregs)
{
- struct xe_gt *mmio = tile->primary_gt;
+ struct xe_mmio *mmio = &tile->mmio;
xe_mmio_write32(mmio, IMR(irqregs), ~0);
/* Posting read */
@@ -87,7 +87,7 @@ static void mask_and_disable(struct xe_tile *tile, u32 irqregs)
static u32 xelp_intr_disable(struct xe_device *xe)
{
- struct xe_gt *mmio = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0);
@@ -103,7 +103,7 @@ static u32 xelp_intr_disable(struct xe_device *xe)
static u32
gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl)
{
- struct xe_gt *mmio = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
u32 iir;
if (!(master_ctl & GU_MISC_IRQ))
@@ -118,7 +118,7 @@ gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl)
static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
{
- struct xe_gt *mmio = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ);
if (stall)
@@ -129,6 +129,7 @@ static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
void xe_irq_enable_hwe(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
+ struct xe_mmio *mmio = >->mmio;
u32 ccs_mask, bcs_mask;
u32 irqs, dmask, smask;
u32 gsc_mask = 0;
@@ -155,35 +156,35 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
if (!xe_gt_is_media_type(gt)) {
/* Enable interrupts for each engine class */
- xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
+ xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
if (ccs_mask)
- xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
+ xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
/* Unmask interrupts for each engine instance */
- xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
- xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
+ xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
+ xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
if (bcs_mask & (BIT(1)|BIT(2)))
- xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
if (bcs_mask & (BIT(3)|BIT(4)))
- xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
if (bcs_mask & (BIT(5)|BIT(6)))
- xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
if (bcs_mask & (BIT(7)|BIT(8)))
- xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
if (ccs_mask & (BIT(0)|BIT(1)))
- xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
if (ccs_mask & (BIT(2)|BIT(3)))
- xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
}
if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
/* Enable interrupts for each engine class */
- xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
+ xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
/* Unmask interrupts for each engine instance */
- xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
- xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
- xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
+ xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
/*
* the heci2 interrupt is enabled via the same register as the
@@ -197,17 +198,17 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
}
if (gsc_mask) {
- xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, gsc_mask | heci_mask);
- xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~gsc_mask);
+ xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, gsc_mask | heci_mask);
+ xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~gsc_mask);
}
if (heci_mask)
- xe_mmio_write32(gt, HECI2_RSVD_INTR_MASK, ~(heci_mask << 16));
+ xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~(heci_mask << 16));
}
}
static u32
gt_engine_identity(struct xe_device *xe,
- struct xe_gt *mmio,
+ struct xe_mmio *mmio,
const unsigned int bank,
const unsigned int bit)
{
@@ -291,7 +292,7 @@ static void gt_irq_handler(struct xe_tile *tile,
u32 *identity)
{
struct xe_device *xe = tile_to_xe(tile);
- struct xe_gt *mmio = tile->primary_gt;
+ struct xe_mmio *mmio = &tile->mmio;
unsigned int bank, bit;
u16 instance, intr_vec;
enum xe_engine_class class;
@@ -376,7 +377,7 @@ static irqreturn_t xelp_irq_handler(int irq, void *arg)
static u32 dg1_intr_disable(struct xe_device *xe)
{
- struct xe_gt *mmio = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
u32 val;
/* First disable interrupts */
@@ -394,7 +395,7 @@ static u32 dg1_intr_disable(struct xe_device *xe)
static void dg1_intr_enable(struct xe_device *xe, bool stall)
{
- struct xe_gt *mmio = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
if (stall)
@@ -431,7 +432,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
}
for_each_tile(tile, xe, id) {
- struct xe_gt *mmio = tile->primary_gt;
+ struct xe_mmio *mmio = &tile->mmio;
if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0)
continue;
@@ -474,7 +475,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
static void gt_irq_reset(struct xe_tile *tile)
{
- struct xe_gt *mmio = tile->primary_gt;
+ struct xe_mmio *mmio = &tile->mmio;
u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
XE_ENGINE_CLASS_COMPUTE);
@@ -547,7 +548,7 @@ static void dg1_irq_reset(struct xe_tile *tile)
static void dg1_irq_reset_mstr(struct xe_tile *tile)
{
- struct xe_gt *mmio = tile->primary_gt;
+ struct xe_mmio *mmio = &tile->mmio;
xe_mmio_write32(mmio, GFX_MSTR_IRQ, ~0);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 11/43] drm/xe/pcode: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (9 preceding siblings ...)
2024-09-07 0:07 ` [PATCH v2 10/43] drm/xe/irq: Convert register access to use xe_mmio Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-07 0:08 ` [PATCH v2 12/43] drm/xe/hwmon: " Matt Roper
` (39 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
Stop using GT pointers for register access. Although some of the pcode
mailboxes are related to GTs, pcode itself (and the register interface
to access it) are outside the GT and should be accessed through the
tile's MMIO.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_pcode.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 7397d556996a..d95d9835de42 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -44,7 +44,7 @@ static int pcode_mailbox_status(struct xe_tile *tile)
[PCODE_ERROR_MASK] = {-EPROTO, "Unknown"},
};
- err = xe_mmio_read32(tile->primary_gt, PCODE_MAILBOX) & PCODE_ERROR_MASK;
+ err = xe_mmio_read32(&tile->mmio, PCODE_MAILBOX) & PCODE_ERROR_MASK;
if (err) {
drm_err(&tile_to_xe(tile)->drm, "PCODE Mailbox failed: %d %s", err,
err_decode[err].str ?: "Unknown");
@@ -58,7 +58,7 @@ static int __pcode_mailbox_rw(struct xe_tile *tile, u32 mbox, u32 *data0, u32 *d
unsigned int timeout_ms, bool return_data,
bool atomic)
{
- struct xe_gt *mmio = tile->primary_gt;
+ struct xe_mmio *mmio = &tile->mmio;
int err;
if (tile_to_xe(tile)->info.skip_pcode)
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 12/43] drm/xe/hwmon: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (10 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 11/43] drm/xe/pcode: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-07 0:08 ` [PATCH v2 13/43] drm/xe/vram: " Matt Roper
` (38 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_hwmon.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index aa11728e7e79..fde56dad3ab7 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -149,7 +149,7 @@ static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, int channel, long *v
u64 reg_val, min, max;
struct xe_device *xe = hwmon->xe;
struct xe_reg rapl_limit, pkg_power_sku;
- struct xe_gt *mmio = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);
pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
@@ -190,7 +190,7 @@ static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, int channel, long *v
static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, int channel, long value)
{
- struct xe_gt *mmio = xe_root_mmio_gt(hwmon->xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
int ret = 0;
u64 reg_val;
struct xe_reg rapl_limit;
@@ -222,7 +222,7 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, int channel, long va
static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, int channel, long *value)
{
- struct xe_gt *mmio = xe_root_mmio_gt(hwmon->xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
u64 reg_val;
@@ -259,7 +259,7 @@ static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, int channel, l
static void
xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy)
{
- struct xe_gt *mmio = xe_root_mmio_gt(hwmon->xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
struct xe_hwmon_energy_info *ei = &hwmon->ei[channel];
u64 reg_val;
@@ -282,7 +282,7 @@ xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *at
char *buf)
{
struct xe_hwmon *hwmon = dev_get_drvdata(dev);
- struct xe_gt *mmio = xe_root_mmio_gt(hwmon->xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
u32 x, y, x_w = 2; /* 2 bits */
u64 r, tau4, out;
int sensor_index = to_sensor_dev_attr(attr)->index;
@@ -323,7 +323,7 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
const char *buf, size_t count)
{
struct xe_hwmon *hwmon = dev_get_drvdata(dev);
- struct xe_gt *mmio = xe_root_mmio_gt(hwmon->xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
u32 x, y, rxy, x_w = 2; /* 2 bits */
u64 tau4, r, max_win;
unsigned long val;
@@ -498,7 +498,7 @@ static int xe_hwmon_power_curr_crit_write(struct xe_hwmon *hwmon, int channel,
static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *value)
{
- struct xe_gt *mmio = xe_root_mmio_gt(hwmon->xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
u64 reg_val;
reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, channel));
@@ -781,7 +781,7 @@ static const struct hwmon_chip_info hwmon_chip_info = {
static void
xe_hwmon_get_preregistration_info(struct xe_device *xe)
{
- struct xe_gt *mmio = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
struct xe_hwmon *hwmon = xe->hwmon;
long energy;
u64 val_sku_unit = 0;
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 13/43] drm/xe/vram: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (11 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 12/43] drm/xe/hwmon: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-07 0:08 ` [PATCH v2 14/43] drm/xe/compat-i915: " Matt Roper
` (37 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
Stop using GT pointers for register access. Note that MIRROR_FUSE3 is a
GT register and is accessed via gt->mmio, whereas GSMBASE is an sgunit
register so it is accessed via tile->mmio.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_vram.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 5bcd59190353..7e765b1499b1 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -169,7 +169,7 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
u64 offset_hi, offset_lo;
u32 nodes, num_enabled;
- reg = xe_mmio_read32(gt, MIRROR_FUSE3);
+ reg = xe_mmio_read32(>->mmio, MIRROR_FUSE3);
nodes = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, reg);
num_enabled = hweight32(nodes); /* Number of enabled l3 nodes */
@@ -184,7 +184,8 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size)
offset *= num_enabled; /* convert to SW view */
/* We don't expect any holes */
- xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(gt, GSMBASE) - ccs_size),
+ xe_assert_msg(xe, offset == (xe_mmio_read64_2x32(>_to_tile(gt)->mmio, GSMBASE) -
+ ccs_size),
"Hole between CCS and GSM.\n");
} else {
reg = xe_gt_mcr_unicast_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);
@@ -256,7 +257,7 @@ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size,
if (xe->info.has_flat_ccs) {
offset = get_flat_ccs_offset(gt, *tile_size);
} else {
- offset = xe_mmio_read64_2x32(gt, GSMBASE);
+ offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);
}
/* remove the tile offset so we have just the available size */
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 14/43] drm/xe/compat-i915: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (12 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 13/43] drm/xe/vram: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:15 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 15/43] drm/xe/lmtt: " Matt Roper
` (36 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Since display (via compat-i915) was the only part of the driver doing
8-bit and 16-bit register reads, this also allows us to drop the
_Generic wrapper macro on these two functions.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
| 36 +++++++++----------
drivers/gpu/drm/xe/xe_mmio.c | 4 +--
drivers/gpu/drm/xe/xe_mmio.h | 7 ++--
3 files changed, 22 insertions(+), 25 deletions(-)
--git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
index eb5b5f0e4bd9..ee3469d4ae73 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
@@ -10,11 +10,11 @@
#include "xe_device_types.h"
#include "xe_mmio.h"
-static inline struct xe_gt *__compat_uncore_to_gt(struct intel_uncore *uncore)
+static inline struct xe_mmio *__compat_uncore_to_mmio(struct intel_uncore *uncore)
{
struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
- return xe_root_mmio_gt(xe);
+ return xe_root_tile_mmio(xe);
}
static inline struct xe_tile *__compat_uncore_to_tile(struct intel_uncore *uncore)
@@ -29,7 +29,7 @@ static inline u32 intel_uncore_read(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- return xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);
+ return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
}
static inline u8 intel_uncore_read8(struct intel_uncore *uncore,
@@ -37,7 +37,7 @@ static inline u8 intel_uncore_read8(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- return xe_mmio_read8(__compat_uncore_to_gt(uncore), reg);
+ return xe_mmio_read8(__compat_uncore_to_mmio(uncore), reg);
}
static inline u16 intel_uncore_read16(struct intel_uncore *uncore,
@@ -45,7 +45,7 @@ static inline u16 intel_uncore_read16(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- return xe_mmio_read16(__compat_uncore_to_gt(uncore), reg);
+ return xe_mmio_read16(__compat_uncore_to_mmio(uncore), reg);
}
static inline u64
@@ -57,11 +57,11 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore,
u32 upper, lower, old_upper;
int loop = 0;
- upper = xe_mmio_read32(__compat_uncore_to_gt(uncore), upper_reg);
+ upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg);
do {
old_upper = upper;
- lower = xe_mmio_read32(__compat_uncore_to_gt(uncore), lower_reg);
- upper = xe_mmio_read32(__compat_uncore_to_gt(uncore), upper_reg);
+ lower = xe_mmio_read32(__compat_uncore_to_mmio(uncore), lower_reg);
+ upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg);
} while (upper != old_upper && loop++ < 2);
return (u64)upper << 32 | lower;
@@ -72,7 +72,7 @@ static inline void intel_uncore_posting_read(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);
+ xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
}
static inline void intel_uncore_write(struct intel_uncore *uncore,
@@ -80,7 +80,7 @@ static inline void intel_uncore_write(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);
+ xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
}
static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,
@@ -88,7 +88,7 @@ static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- return xe_mmio_rmw32(__compat_uncore_to_gt(uncore), reg, clear, set);
+ return xe_mmio_rmw32(__compat_uncore_to_mmio(uncore), reg, clear, set);
}
static inline int intel_wait_for_register(struct intel_uncore *uncore,
@@ -97,7 +97,7 @@ static inline int intel_wait_for_register(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,
+ return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
timeout * USEC_PER_MSEC, NULL, false);
}
@@ -107,7 +107,7 @@ static inline int intel_wait_for_register_fw(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,
+ return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
timeout * USEC_PER_MSEC, NULL, false);
}
@@ -118,7 +118,7 @@ __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,
+ return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
fast_timeout_us + 1000 * slow_timeout_ms,
out_value, false);
}
@@ -128,7 +128,7 @@ static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- return xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);
+ return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
}
static inline void intel_uncore_write_fw(struct intel_uncore *uncore,
@@ -136,7 +136,7 @@ static inline void intel_uncore_write_fw(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);
+ xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
}
static inline u32 intel_uncore_read_notrace(struct intel_uncore *uncore,
@@ -144,7 +144,7 @@ static inline u32 intel_uncore_read_notrace(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- return xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);
+ return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
}
static inline void intel_uncore_write_notrace(struct intel_uncore *uncore,
@@ -152,7 +152,7 @@ static inline void intel_uncore_write_notrace(struct intel_uncore *uncore,
{
struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
- xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);
+ xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
}
static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 9ea0973337ed..29f4e3759106 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -200,7 +200,7 @@ static void mmio_flush_pending_writes(struct xe_mmio *mmio)
writel(0, mmio->regs + DUMMY_REG_OFFSET);
}
-u8 __xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)
+u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)
{
u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
u8 val;
@@ -214,7 +214,7 @@ u8 __xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)
return val;
}
-u16 __xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg)
+u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg)
{
u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
u16 val;
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index ac6846447c52..99e3b58c9bb2 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -27,11 +27,8 @@ int xe_mmio_probe_tiles(struct xe_device *xe);
const struct xe_mmio *: (ptr), \
struct xe_mmio *: (ptr))
-u8 __xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);
-#define xe_mmio_read8(p, reg) __xe_mmio_read8(__to_xe_mmio(p), reg)
-
-u16 __xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);
-#define xe_mmio_read16(p, reg) __xe_mmio_read16(__to_xe_mmio(p), reg)
+u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);
+u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);
void __xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);
#define xe_mmio_write32(p, reg, val) __xe_mmio_write32(__to_xe_mmio(p), reg, val)
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 14/43] drm/xe/compat-i915: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 14/43] drm/xe/compat-i915: " Matt Roper
@ 2024-09-10 18:15 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:15 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:03PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Since display (via compat-i915) was the only part of the driver doing
> 8-bit and 16-bit register reads, this also allows us to drop the
> _Generic wrapper macro on these two functions.
I was wondering if this should be a separate patch, but probably not...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../drm/xe/compat-i915-headers/intel_uncore.h | 36 +++++++++----------
> drivers/gpu/drm/xe/xe_mmio.c | 4 +--
> drivers/gpu/drm/xe/xe_mmio.h | 7 ++--
> 3 files changed, 22 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> index eb5b5f0e4bd9..ee3469d4ae73 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> @@ -10,11 +10,11 @@
> #include "xe_device_types.h"
> #include "xe_mmio.h"
>
> -static inline struct xe_gt *__compat_uncore_to_gt(struct intel_uncore *uncore)
> +static inline struct xe_mmio *__compat_uncore_to_mmio(struct intel_uncore *uncore)
> {
> struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
>
> - return xe_root_mmio_gt(xe);
> + return xe_root_tile_mmio(xe);
> }
>
> static inline struct xe_tile *__compat_uncore_to_tile(struct intel_uncore *uncore)
> @@ -29,7 +29,7 @@ static inline u32 intel_uncore_read(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - return xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);
> + return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
> }
>
> static inline u8 intel_uncore_read8(struct intel_uncore *uncore,
> @@ -37,7 +37,7 @@ static inline u8 intel_uncore_read8(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - return xe_mmio_read8(__compat_uncore_to_gt(uncore), reg);
> + return xe_mmio_read8(__compat_uncore_to_mmio(uncore), reg);
> }
>
> static inline u16 intel_uncore_read16(struct intel_uncore *uncore,
> @@ -45,7 +45,7 @@ static inline u16 intel_uncore_read16(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - return xe_mmio_read16(__compat_uncore_to_gt(uncore), reg);
> + return xe_mmio_read16(__compat_uncore_to_mmio(uncore), reg);
> }
>
> static inline u64
> @@ -57,11 +57,11 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore,
> u32 upper, lower, old_upper;
> int loop = 0;
>
> - upper = xe_mmio_read32(__compat_uncore_to_gt(uncore), upper_reg);
> + upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg);
> do {
> old_upper = upper;
> - lower = xe_mmio_read32(__compat_uncore_to_gt(uncore), lower_reg);
> - upper = xe_mmio_read32(__compat_uncore_to_gt(uncore), upper_reg);
> + lower = xe_mmio_read32(__compat_uncore_to_mmio(uncore), lower_reg);
> + upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg);
> } while (upper != old_upper && loop++ < 2);
>
> return (u64)upper << 32 | lower;
> @@ -72,7 +72,7 @@ static inline void intel_uncore_posting_read(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);
> + xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
> }
>
> static inline void intel_uncore_write(struct intel_uncore *uncore,
> @@ -80,7 +80,7 @@ static inline void intel_uncore_write(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);
> + xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
> }
>
> static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,
> @@ -88,7 +88,7 @@ static inline u32 intel_uncore_rmw(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - return xe_mmio_rmw32(__compat_uncore_to_gt(uncore), reg, clear, set);
> + return xe_mmio_rmw32(__compat_uncore_to_mmio(uncore), reg, clear, set);
> }
>
> static inline int intel_wait_for_register(struct intel_uncore *uncore,
> @@ -97,7 +97,7 @@ static inline int intel_wait_for_register(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,
> + return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
> timeout * USEC_PER_MSEC, NULL, false);
> }
>
> @@ -107,7 +107,7 @@ static inline int intel_wait_for_register_fw(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,
> + return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
> timeout * USEC_PER_MSEC, NULL, false);
> }
>
> @@ -118,7 +118,7 @@ __intel_wait_for_register(struct intel_uncore *uncore, i915_reg_t i915_reg,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - return xe_mmio_wait32(__compat_uncore_to_gt(uncore), reg, mask, value,
> + return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value,
> fast_timeout_us + 1000 * slow_timeout_ms,
> out_value, false);
> }
> @@ -128,7 +128,7 @@ static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - return xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);
> + return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
> }
>
> static inline void intel_uncore_write_fw(struct intel_uncore *uncore,
> @@ -136,7 +136,7 @@ static inline void intel_uncore_write_fw(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);
> + xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
> }
>
> static inline u32 intel_uncore_read_notrace(struct intel_uncore *uncore,
> @@ -144,7 +144,7 @@ static inline u32 intel_uncore_read_notrace(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - return xe_mmio_read32(__compat_uncore_to_gt(uncore), reg);
> + return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg);
> }
>
> static inline void intel_uncore_write_notrace(struct intel_uncore *uncore,
> @@ -152,7 +152,7 @@ static inline void intel_uncore_write_notrace(struct intel_uncore *uncore,
> {
> struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
>
> - xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);
> + xe_mmio_write32(__compat_uncore_to_mmio(uncore), reg, val);
> }
>
> static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore)
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 9ea0973337ed..29f4e3759106 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -200,7 +200,7 @@ static void mmio_flush_pending_writes(struct xe_mmio *mmio)
> writel(0, mmio->regs + DUMMY_REG_OFFSET);
> }
>
> -u8 __xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)
> +u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)
> {
> u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
> u8 val;
> @@ -214,7 +214,7 @@ u8 __xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)
> return val;
> }
>
> -u16 __xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg)
> +u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg)
> {
> u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
> u16 val;
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index ac6846447c52..99e3b58c9bb2 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -27,11 +27,8 @@ int xe_mmio_probe_tiles(struct xe_device *xe);
> const struct xe_mmio *: (ptr), \
> struct xe_mmio *: (ptr))
>
> -u8 __xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);
> -#define xe_mmio_read8(p, reg) __xe_mmio_read8(__to_xe_mmio(p), reg)
> -
> -u16 __xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);
> -#define xe_mmio_read16(p, reg) __xe_mmio_read16(__to_xe_mmio(p), reg)
> +u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);
> +u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);
>
> void __xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);
> #define xe_mmio_write32(p, reg, val) __xe_mmio_write32(__to_xe_mmio(p), reg, val)
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 15/43] drm/xe/lmtt: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (13 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 14/43] drm/xe/compat-i915: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-07 0:08 ` [PATCH v2 16/43] drm/xe/stolen: " Matt Roper
` (35 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_lmtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_lmtt.c b/drivers/gpu/drm/xe/xe_lmtt.c
index 8999ac511555..a60ceae4c6dd 100644
--- a/drivers/gpu/drm/xe/xe_lmtt.c
+++ b/drivers/gpu/drm/xe/xe_lmtt.c
@@ -193,7 +193,7 @@ static void lmtt_setup_dir_ptr(struct xe_lmtt *lmtt)
lmtt_assert(lmtt, xe_bo_is_vram(lmtt->pd->bo));
lmtt_assert(lmtt, IS_ALIGNED(offset, SZ_64K));
- xe_mmio_write32(tile->primary_gt,
+ xe_mmio_write32(&tile->mmio,
GRAPHICS_VER(xe) >= 20 ? XE2_LMEM_CFG : LMEM_CFG,
LMEM_EN | REG_FIELD_PREP(LMTT_DIR_PTR, offset / SZ_64K));
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 16/43] drm/xe/stolen: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (14 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 15/43] drm/xe/lmtt: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-07 0:08 ` [PATCH v2 17/43] drm/xe/device: " Matt Roper
` (34 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Lucas De Marchi
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
index f7113cf6109d..423856cc18d4 100644
--- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
+++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
@@ -60,7 +60,7 @@ bool xe_ttm_stolen_cpu_access_needs_ggtt(struct xe_device *xe)
static s64 detect_bar2_dgfx(struct xe_device *xe, struct xe_ttm_stolen_mgr *mgr)
{
struct xe_tile *tile = xe_device_get_root_tile(xe);
- struct xe_gt *mmio = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
u64 stolen_size;
u64 tile_offset;
@@ -94,7 +94,7 @@ static u32 get_wopcm_size(struct xe_device *xe)
u32 wopcm_size;
u64 val;
- val = xe_mmio_read64_2x32(xe_root_mmio_gt(xe), STOLEN_RESERVED);
+ val = xe_mmio_read64_2x32(xe_root_tile_mmio(xe), STOLEN_RESERVED);
val = REG_FIELD_GET64(WOPCM_SIZE_MASK, val);
switch (val) {
@@ -119,7 +119,7 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
u32 stolen_size, wopcm_size;
u32 ggc, gms;
- ggc = xe_mmio_read32(xe_root_mmio_gt(xe), GGC);
+ ggc = xe_mmio_read32(xe_root_tile_mmio(xe), GGC);
/*
* Check GGMS: it should be fixed 0x3 (8MB), which corresponds to the
@@ -159,7 +159,7 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
stolen_size -= wopcm_size;
if (media_gt && XE_WA(media_gt, 14019821291)) {
- u64 gscpsmi_base = xe_mmio_read64_2x32(media_gt, GSCPSMI_BASE)
+ u64 gscpsmi_base = xe_mmio_read64_2x32(&media_gt->mmio, GSCPSMI_BASE)
& ~GENMASK_ULL(5, 0);
/*
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* [PATCH v2 17/43] drm/xe/device: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (15 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 16/43] drm/xe/stolen: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:05 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 18/43] drm/xe/pci: " Matt Roper
` (33 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_device.c | 37 ++++++++++++++++------------------
1 file changed, 17 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 449b85035d3a..cca17422bc2a 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -399,10 +399,10 @@ struct xe_device *xe_device_create(struct pci_dev *pdev,
static void xe_driver_flr(struct xe_device *xe)
{
const unsigned int flr_timeout = 3 * MICRO; /* specs recommend a 3s wait */
- struct xe_gt *gt = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
int ret;
- if (xe_mmio_read32(gt, GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS) {
+ if (xe_mmio_read32(mmio, GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS) {
drm_info_once(&xe->drm, "BIOS Disabled Driver-FLR\n");
return;
}
@@ -418,25 +418,25 @@ static void xe_driver_flr(struct xe_device *xe)
* is still pending (unless the HW is totally dead), but better to be
* safe in case something unexpected happens
*/
- ret = xe_mmio_wait32(gt, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);
+ ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);
if (ret) {
drm_err(&xe->drm, "Driver-FLR-prepare wait for ready failed! %d\n", ret);
return;
}
- xe_mmio_write32(gt, GU_DEBUG, DRIVERFLR_STATUS);
+ xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS);
/* Trigger the actual Driver-FLR */
- xe_mmio_rmw32(gt, GU_CNTL, 0, DRIVERFLR);
+ xe_mmio_rmw32(mmio, GU_CNTL, 0, DRIVERFLR);
/* Wait for hardware teardown to complete */
- ret = xe_mmio_wait32(gt, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);
+ ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);
if (ret) {
drm_err(&xe->drm, "Driver-FLR-teardown wait completion failed! %d\n", ret);
return;
}
/* Wait for hardware/firmware re-init to complete */
- ret = xe_mmio_wait32(gt, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS,
+ ret = xe_mmio_wait32(mmio, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS,
flr_timeout, NULL, false);
if (ret) {
drm_err(&xe->drm, "Driver-FLR-reinit wait completion failed! %d\n", ret);
@@ -444,7 +444,7 @@ static void xe_driver_flr(struct xe_device *xe)
}
/* Clear sticky completion status */
- xe_mmio_write32(gt, GU_DEBUG, DRIVERFLR_STATUS);
+ xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS);
}
static void xe_driver_flr_fini(void *arg)
@@ -487,16 +487,15 @@ static int xe_set_dma_info(struct xe_device *xe)
return err;
}
-static bool verify_lmem_ready(struct xe_gt *gt)
+static bool verify_lmem_ready(struct xe_device *xe)
{
- u32 val = xe_mmio_read32(gt, GU_CNTL) & LMEM_INIT;
+ u32 val = xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL) & LMEM_INIT;
return !!val;
}
static int wait_for_lmem_ready(struct xe_device *xe)
{
- struct xe_gt *gt = xe_root_mmio_gt(xe);
unsigned long timeout, start;
if (!IS_DGFX(xe))
@@ -505,7 +504,7 @@ static int wait_for_lmem_ready(struct xe_device *xe)
if (IS_SRIOV_VF(xe))
return 0;
- if (verify_lmem_ready(gt))
+ if (verify_lmem_ready(xe))
return 0;
drm_dbg(&xe->drm, "Waiting for lmem initialization\n");
@@ -534,7 +533,7 @@ static int wait_for_lmem_ready(struct xe_device *xe)
msleep(20);
- } while (!verify_lmem_ready(gt));
+ } while (!verify_lmem_ready(xe));
drm_dbg(&xe->drm, "lmem ready after %ums",
jiffies_to_msecs(jiffies - start));
@@ -813,11 +812,9 @@ void xe_device_shutdown(struct xe_device *xe)
*/
void xe_device_wmb(struct xe_device *xe)
{
- struct xe_gt *gt = xe_root_mmio_gt(xe);
-
wmb();
if (IS_DGFX(xe))
- xe_mmio_write32(gt, VF_CAP_REG, 0);
+ xe_mmio_write32(xe_root_tile_mmio(xe), VF_CAP_REG, 0);
}
/**
@@ -858,7 +855,7 @@ void xe_device_td_flush(struct xe_device *xe)
if (xe_force_wake_get(gt_to_fw(gt), XE_FW_GT))
return;
- xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);
+ xe_mmio_write32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);
/*
* FIXME: We can likely do better here with our choice of
* timeout. Currently we just assume the worst case, i.e. 150us,
@@ -866,7 +863,7 @@ void xe_device_td_flush(struct xe_device *xe)
* scenario on current platforms if all cache entries are
* transient and need to be flushed..
*/
- if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,
+ if (xe_mmio_wait32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,
150, NULL, false))
xe_gt_err_once(gt, "TD flush timeout\n");
@@ -889,9 +886,9 @@ void xe_device_l2_flush(struct xe_device *xe)
return;
spin_lock(>->global_invl_lock);
- xe_mmio_write32(gt, XE2_GLOBAL_INVAL, 0x1);
+ xe_mmio_write32(>->mmio, XE2_GLOBAL_INVAL, 0x1);
- if (xe_mmio_wait32(gt, XE2_GLOBAL_INVAL, 0x1, 0x0, 150, NULL, true))
+ if (xe_mmio_wait32(>->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 150, NULL, true))
xe_gt_err_once(gt, "Global invalidation timeout\n");
spin_unlock(>->global_invl_lock);
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 17/43] drm/xe/device: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 17/43] drm/xe/device: " Matt Roper
@ 2024-09-10 18:05 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:05 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:06PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device.c | 37 ++++++++++++++++------------------
> 1 file changed, 17 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 449b85035d3a..cca17422bc2a 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -399,10 +399,10 @@ struct xe_device *xe_device_create(struct pci_dev *pdev,
> static void xe_driver_flr(struct xe_device *xe)
> {
> const unsigned int flr_timeout = 3 * MICRO; /* specs recommend a 3s wait */
> - struct xe_gt *gt = xe_root_mmio_gt(xe);
> + struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> int ret;
>
> - if (xe_mmio_read32(gt, GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS) {
> + if (xe_mmio_read32(mmio, GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS) {
> drm_info_once(&xe->drm, "BIOS Disabled Driver-FLR\n");
> return;
> }
> @@ -418,25 +418,25 @@ static void xe_driver_flr(struct xe_device *xe)
> * is still pending (unless the HW is totally dead), but better to be
> * safe in case something unexpected happens
> */
> - ret = xe_mmio_wait32(gt, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);
> + ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);
> if (ret) {
> drm_err(&xe->drm, "Driver-FLR-prepare wait for ready failed! %d\n", ret);
> return;
> }
> - xe_mmio_write32(gt, GU_DEBUG, DRIVERFLR_STATUS);
> + xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS);
>
> /* Trigger the actual Driver-FLR */
> - xe_mmio_rmw32(gt, GU_CNTL, 0, DRIVERFLR);
> + xe_mmio_rmw32(mmio, GU_CNTL, 0, DRIVERFLR);
>
> /* Wait for hardware teardown to complete */
> - ret = xe_mmio_wait32(gt, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);
> + ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false);
> if (ret) {
> drm_err(&xe->drm, "Driver-FLR-teardown wait completion failed! %d\n", ret);
> return;
> }
>
> /* Wait for hardware/firmware re-init to complete */
> - ret = xe_mmio_wait32(gt, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS,
> + ret = xe_mmio_wait32(mmio, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS,
> flr_timeout, NULL, false);
> if (ret) {
> drm_err(&xe->drm, "Driver-FLR-reinit wait completion failed! %d\n", ret);
> @@ -444,7 +444,7 @@ static void xe_driver_flr(struct xe_device *xe)
> }
>
> /* Clear sticky completion status */
> - xe_mmio_write32(gt, GU_DEBUG, DRIVERFLR_STATUS);
> + xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS);
> }
>
> static void xe_driver_flr_fini(void *arg)
> @@ -487,16 +487,15 @@ static int xe_set_dma_info(struct xe_device *xe)
> return err;
> }
>
> -static bool verify_lmem_ready(struct xe_gt *gt)
> +static bool verify_lmem_ready(struct xe_device *xe)
> {
> - u32 val = xe_mmio_read32(gt, GU_CNTL) & LMEM_INIT;
> + u32 val = xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL) & LMEM_INIT;
>
> return !!val;
> }
>
> static int wait_for_lmem_ready(struct xe_device *xe)
> {
> - struct xe_gt *gt = xe_root_mmio_gt(xe);
> unsigned long timeout, start;
>
> if (!IS_DGFX(xe))
> @@ -505,7 +504,7 @@ static int wait_for_lmem_ready(struct xe_device *xe)
> if (IS_SRIOV_VF(xe))
> return 0;
>
> - if (verify_lmem_ready(gt))
> + if (verify_lmem_ready(xe))
> return 0;
>
> drm_dbg(&xe->drm, "Waiting for lmem initialization\n");
> @@ -534,7 +533,7 @@ static int wait_for_lmem_ready(struct xe_device *xe)
>
> msleep(20);
>
> - } while (!verify_lmem_ready(gt));
> + } while (!verify_lmem_ready(xe));
>
> drm_dbg(&xe->drm, "lmem ready after %ums",
> jiffies_to_msecs(jiffies - start));
> @@ -813,11 +812,9 @@ void xe_device_shutdown(struct xe_device *xe)
> */
> void xe_device_wmb(struct xe_device *xe)
> {
> - struct xe_gt *gt = xe_root_mmio_gt(xe);
This lmem_ready change from gt to xe should deserve a separate change.
But up to you
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> -
> wmb();
> if (IS_DGFX(xe))
> - xe_mmio_write32(gt, VF_CAP_REG, 0);
> + xe_mmio_write32(xe_root_tile_mmio(xe), VF_CAP_REG, 0);
> }
>
> /**
> @@ -858,7 +855,7 @@ void xe_device_td_flush(struct xe_device *xe)
> if (xe_force_wake_get(gt_to_fw(gt), XE_FW_GT))
> return;
>
> - xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);
> + xe_mmio_write32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST);
> /*
> * FIXME: We can likely do better here with our choice of
> * timeout. Currently we just assume the worst case, i.e. 150us,
> @@ -866,7 +863,7 @@ void xe_device_td_flush(struct xe_device *xe)
> * scenario on current platforms if all cache entries are
> * transient and need to be flushed..
> */
> - if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,
> + if (xe_mmio_wait32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0,
> 150, NULL, false))
> xe_gt_err_once(gt, "TD flush timeout\n");
>
> @@ -889,9 +886,9 @@ void xe_device_l2_flush(struct xe_device *xe)
> return;
>
> spin_lock(>->global_invl_lock);
> - xe_mmio_write32(gt, XE2_GLOBAL_INVAL, 0x1);
> + xe_mmio_write32(>->mmio, XE2_GLOBAL_INVAL, 0x1);
>
> - if (xe_mmio_wait32(gt, XE2_GLOBAL_INVAL, 0x1, 0x0, 150, NULL, true))
> + if (xe_mmio_wait32(>->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 150, NULL, true))
> xe_gt_err_once(gt, "Global invalidation timeout\n");
> spin_unlock(>->global_invl_lock);
>
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 18/43] drm/xe/pci: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (16 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 17/43] drm/xe/device: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:40 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 19/43] drm/xe/wa: " Matt Roper
` (32 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index aa0c29450b4a..e0188ef9995e 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -473,13 +473,15 @@ enum xe_gmdid_type {
static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
{
- struct xe_gt *gt = xe_root_mmio_gt(xe);
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
struct xe_reg gmdid_reg = GMD_ID;
u32 val;
KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
if (IS_SRIOV_VF(xe)) {
+ struct xe_gt *gt = xe_root_mmio_gt(xe);
+
/*
* To get the value of the GMDID register, VFs must obtain it
* from the GuC using MMIO communication.
@@ -515,14 +517,15 @@ static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver,
gt->info.type = XE_GT_TYPE_UNINITIALIZED;
} else {
/*
- * We need to apply the GSI offset explicitly here as at this
- * point the xe_gt is not fully uninitialized and only basic
- * access to MMIO registers is possible.
+ * We need to apply the GSI offset explicitly here since we're
+ * reading through the tile-level MMIO accessor (at this
+ * point the GT is not fully uninitialized and only basic
+ * access to MMIO registers is possible).
*/
if (type == GMDID_MEDIA)
gmdid_reg.addr += MEDIA_GT_GSI_OFFSET;
- val = xe_mmio_read32(gt, gmdid_reg);
+ val = xe_mmio_read32(mmio, gmdid_reg);
}
*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 18/43] drm/xe/pci: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 18/43] drm/xe/pci: " Matt Roper
@ 2024-09-10 18:40 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:40 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:07PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_pci.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index aa0c29450b4a..e0188ef9995e 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -473,13 +473,15 @@ enum xe_gmdid_type {
>
> static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
> {
> - struct xe_gt *gt = xe_root_mmio_gt(xe);
> + struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> struct xe_reg gmdid_reg = GMD_ID;
> u32 val;
>
> KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
>
> if (IS_SRIOV_VF(xe)) {
> + struct xe_gt *gt = xe_root_mmio_gt(xe);
> +
> /*
> * To get the value of the GMDID register, VFs must obtain it
> * from the GuC using MMIO communication.
> @@ -515,14 +517,15 @@ static void read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver,
> gt->info.type = XE_GT_TYPE_UNINITIALIZED;
> } else {
> /*
> - * We need to apply the GSI offset explicitly here as at this
> - * point the xe_gt is not fully uninitialized and only basic
> - * access to MMIO registers is possible.
> + * We need to apply the GSI offset explicitly here since we're
> + * reading through the tile-level MMIO accessor (at this
> + * point the GT is not fully uninitialized and only basic
> + * access to MMIO registers is possible).
it is kind of strange to mention GT initialization now that gt struct is
not visible and that we are trying to detach mmio from gt.
But well, perhaps the strange part is this entire manual offset thing and
this change in the comment is needed now that xe_gt struct is not used
and this keep the meaning, so
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> */
> if (type == GMDID_MEDIA)
> gmdid_reg.addr += MEDIA_GT_GSI_OFFSET;
>
> - val = xe_mmio_read32(gt, gmdid_reg);
> + val = xe_mmio_read32(mmio, gmdid_reg);
> }
>
> *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 19/43] drm/xe/wa: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (17 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 18/43] drm/xe/pci: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:07 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 20/43] drm/xe/uc: " Matt Roper
` (31 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_wa.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 28b7f95b6c2f..d8a5a85e9ebd 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -883,11 +883,11 @@ void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
*/
void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
{
- struct xe_gt *mmio = tile->primary_gt;
+ struct xe_mmio *mmio = &tile->mmio;
if (IS_SRIOV_VF(tile->xe))
return;
- if (XE_WA(mmio, 22010954014))
+ if (XE_WA(tile->primary_gt, 22010954014))
xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 19/43] drm/xe/wa: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 19/43] drm/xe/wa: " Matt Roper
@ 2024-09-10 18:07 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:07 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:08PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_wa.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 28b7f95b6c2f..d8a5a85e9ebd 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -883,11 +883,11 @@ void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
> */
> void xe_wa_apply_tile_workarounds(struct xe_tile *tile)
> {
> - struct xe_gt *mmio = tile->primary_gt;
> + struct xe_mmio *mmio = &tile->mmio;
>
> if (IS_SRIOV_VF(tile->xe))
> return;
>
> - if (XE_WA(mmio, 22010954014))
> + if (XE_WA(tile->primary_gt, 22010954014))
this got my head spining... but blame on old xe_gt *mmio
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> xe_mmio_rmw32(mmio, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
> }
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 20/43] drm/xe/uc: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (18 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 19/43] drm/xe/wa: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:42 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 21/43] drm/xe/guc: " Matt Roper
` (30 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_uc_fw.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 821b46c9b4ee..eab9456e051f 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -807,6 +807,7 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
{
struct xe_device *xe = uc_fw_to_xe(uc_fw);
struct xe_gt *gt = uc_fw_to_gt(uc_fw);
+ struct xe_mmio *mmio = >->mmio;
u64 src_offset;
u32 dma_ctrl;
int ret;
@@ -815,34 +816,34 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
/* Set the source address for the uCode */
src_offset = uc_fw_ggtt_offset(uc_fw) + uc_fw->css_offset;
- xe_mmio_write32(gt, DMA_ADDR_0_LOW, lower_32_bits(src_offset));
- xe_mmio_write32(gt, DMA_ADDR_0_HIGH,
+ xe_mmio_write32(mmio, DMA_ADDR_0_LOW, lower_32_bits(src_offset));
+ xe_mmio_write32(mmio, DMA_ADDR_0_HIGH,
upper_32_bits(src_offset) | DMA_ADDRESS_SPACE_GGTT);
/* Set the DMA destination */
- xe_mmio_write32(gt, DMA_ADDR_1_LOW, offset);
- xe_mmio_write32(gt, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
+ xe_mmio_write32(mmio, DMA_ADDR_1_LOW, offset);
+ xe_mmio_write32(mmio, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
/*
* Set the transfer size. The header plus uCode will be copied to WOPCM
* via DMA, excluding any other components
*/
- xe_mmio_write32(gt, DMA_COPY_SIZE,
+ xe_mmio_write32(mmio, DMA_COPY_SIZE,
sizeof(struct uc_css_header) + uc_fw->ucode_size);
/* Start the DMA */
- xe_mmio_write32(gt, DMA_CTRL,
+ xe_mmio_write32(mmio, DMA_CTRL,
_MASKED_BIT_ENABLE(dma_flags | START_DMA));
/* Wait for DMA to finish */
- ret = xe_mmio_wait32(gt, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl,
+ ret = xe_mmio_wait32(mmio, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl,
false);
if (ret)
drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
/* Disable the bits once DMA is over */
- xe_mmio_write32(gt, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
+ xe_mmio_write32(mmio, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
return ret;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 20/43] drm/xe/uc: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 20/43] drm/xe/uc: " Matt Roper
@ 2024-09-10 18:42 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:42 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:09PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_uc_fw.c | 17 +++++++++--------
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
> index 821b46c9b4ee..eab9456e051f 100644
> --- a/drivers/gpu/drm/xe/xe_uc_fw.c
> +++ b/drivers/gpu/drm/xe/xe_uc_fw.c
> @@ -807,6 +807,7 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
> {
> struct xe_device *xe = uc_fw_to_xe(uc_fw);
> struct xe_gt *gt = uc_fw_to_gt(uc_fw);
> + struct xe_mmio *mmio = >->mmio;
> u64 src_offset;
> u32 dma_ctrl;
> int ret;
> @@ -815,34 +816,34 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags)
>
> /* Set the source address for the uCode */
> src_offset = uc_fw_ggtt_offset(uc_fw) + uc_fw->css_offset;
> - xe_mmio_write32(gt, DMA_ADDR_0_LOW, lower_32_bits(src_offset));
> - xe_mmio_write32(gt, DMA_ADDR_0_HIGH,
> + xe_mmio_write32(mmio, DMA_ADDR_0_LOW, lower_32_bits(src_offset));
> + xe_mmio_write32(mmio, DMA_ADDR_0_HIGH,
> upper_32_bits(src_offset) | DMA_ADDRESS_SPACE_GGTT);
>
> /* Set the DMA destination */
> - xe_mmio_write32(gt, DMA_ADDR_1_LOW, offset);
> - xe_mmio_write32(gt, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> + xe_mmio_write32(mmio, DMA_ADDR_1_LOW, offset);
> + xe_mmio_write32(mmio, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>
> /*
> * Set the transfer size. The header plus uCode will be copied to WOPCM
> * via DMA, excluding any other components
> */
> - xe_mmio_write32(gt, DMA_COPY_SIZE,
> + xe_mmio_write32(mmio, DMA_COPY_SIZE,
> sizeof(struct uc_css_header) + uc_fw->ucode_size);
>
> /* Start the DMA */
> - xe_mmio_write32(gt, DMA_CTRL,
> + xe_mmio_write32(mmio, DMA_CTRL,
> _MASKED_BIT_ENABLE(dma_flags | START_DMA));
>
> /* Wait for DMA to finish */
> - ret = xe_mmio_wait32(gt, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl,
> + ret = xe_mmio_wait32(mmio, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl,
> false);
> if (ret)
> drm_err(&xe->drm, "DMA for %s fw failed, DMA_CTRL=%u\n",
> xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
>
> /* Disable the bits once DMA is over */
> - xe_mmio_write32(gt, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
> + xe_mmio_write32(mmio, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
>
> return ret;
> }
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 21/43] drm/xe/guc: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (19 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 20/43] drm/xe/uc: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:48 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 22/43] drm/xe/huc: " Matt Roper
` (29 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Since GuC was the only part of the driver using xe_mmio_wait32_not(), we
can also drop the _Generic wrapper macro for that function as well.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_guc.c | 60 ++++++++++++++++++---------------
drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
drivers/gpu/drm/xe/xe_guc_pc.c | 34 +++++++++----------
drivers/gpu/drm/xe/xe_mmio.c | 4 +--
drivers/gpu/drm/xe/xe_mmio.h | 6 ++--
5 files changed, 54 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 5599464013bd..1eb5bb7e8771 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -236,10 +236,10 @@ static void guc_write_params(struct xe_guc *guc)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- xe_mmio_write32(gt, SOFT_SCRATCH(0), 0);
+ xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- xe_mmio_write32(gt, SOFT_SCRATCH(1 + i), guc->params[i]);
+ xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]);
}
static void guc_fini_hw(void *arg)
@@ -425,6 +425,7 @@ int xe_guc_post_load_init(struct xe_guc *guc)
int xe_guc_reset(struct xe_guc *guc)
{
struct xe_gt *gt = guc_to_gt(guc);
+ struct xe_mmio *mmio = >->mmio;
u32 guc_status, gdrst;
int ret;
@@ -433,15 +434,15 @@ int xe_guc_reset(struct xe_guc *guc)
if (IS_SRIOV_VF(gt_to_xe(gt)))
return xe_gt_sriov_vf_bootstrap(gt);
- xe_mmio_write32(gt, GDRST, GRDOM_GUC);
+ xe_mmio_write32(mmio, GDRST, GRDOM_GUC);
- ret = xe_mmio_wait32(gt, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false);
+ ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false);
if (ret) {
xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst);
goto err_out;
}
- guc_status = xe_mmio_read32(gt, GUC_STATUS);
+ guc_status = xe_mmio_read32(mmio, GUC_STATUS);
if (!(guc_status & GS_MIA_IN_RESET)) {
xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n",
guc_status);
@@ -459,6 +460,7 @@ int xe_guc_reset(struct xe_guc *guc)
static void guc_prepare_xfer(struct xe_guc *guc)
{
struct xe_gt *gt = guc_to_gt(guc);
+ struct xe_mmio *mmio = >->mmio;
struct xe_device *xe = guc_to_xe(guc);
u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
@@ -473,12 +475,12 @@ static void guc_prepare_xfer(struct xe_guc *guc)
shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index);
/* Must program this register before loading the ucode with DMA */
- xe_mmio_write32(gt, GUC_SHIM_CONTROL, shim_flags);
+ xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags);
- xe_mmio_write32(gt, GT_PM_CONFIG, GT_DOORBELL_ENABLE);
+ xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE);
/* Make sure GuC receives ARAT interrupts */
- xe_mmio_rmw32(gt, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0);
+ xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0);
}
/*
@@ -494,7 +496,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
if (guc->fw.rsa_size > 256) {
u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) +
xe_uc_fw_rsa_offset(&guc->fw);
- xe_mmio_write32(gt, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);
+ xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);
return 0;
}
@@ -503,7 +505,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
return -ENOMEM;
for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
- xe_mmio_write32(gt, UOS_RSA_SCRATCH(i), rsa[i]);
+ xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]);
return 0;
}
@@ -593,6 +595,7 @@ static s32 guc_pc_get_cur_freq(struct xe_guc_pc *guc_pc)
static void guc_wait_ucode(struct xe_guc *guc)
{
struct xe_gt *gt = guc_to_gt(guc);
+ struct xe_mmio *mmio = >->mmio;
struct xe_guc_pc *guc_pc = >->uc.guc.pc;
ktime_t before, after, delta;
int load_done;
@@ -619,7 +622,7 @@ static void guc_wait_ucode(struct xe_guc *guc)
* timeouts rather than allowing a huge timeout each time. So basically, need
* to treat a timeout no different to a value change.
*/
- ret = xe_mmio_wait32_not(gt, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK,
+ ret = xe_mmio_wait32_not(mmio, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK,
last_status, 1000 * 1000, &status, false);
if (ret < 0)
count++;
@@ -657,7 +660,7 @@ static void guc_wait_ucode(struct xe_guc *guc)
switch (bootrom) {
case XE_BOOTROM_STATUS_NO_KEY_FOUND:
xe_gt_err(gt, "invalid key requested, header = 0x%08X\n",
- xe_mmio_read32(gt, GUC_HEADER_INFO));
+ xe_mmio_read32(mmio, GUC_HEADER_INFO));
break;
case XE_BOOTROM_STATUS_RSA_FAILED:
@@ -672,7 +675,7 @@ static void guc_wait_ucode(struct xe_guc *guc)
switch (ukernel) {
case XE_GUC_LOAD_STATUS_EXCEPTION:
xe_gt_err(gt, "firmware exception. EIP: %#x\n",
- xe_mmio_read32(gt, SOFT_SCRATCH(13)));
+ xe_mmio_read32(mmio, SOFT_SCRATCH(13)));
break;
case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID:
@@ -824,10 +827,10 @@ static void guc_handle_mmio_msg(struct xe_guc *guc)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- msg = xe_mmio_read32(gt, SOFT_SCRATCH(15));
+ msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15));
msg &= XE_GUC_RECV_MSG_EXCEPTION |
XE_GUC_RECV_MSG_CRASH_DUMP_POSTED;
- xe_mmio_write32(gt, SOFT_SCRATCH(15), 0);
+ xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0);
if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED)
xe_gt_err(gt, "Received early GuC crash dump notification!\n");
@@ -844,14 +847,14 @@ static void guc_enable_irq(struct xe_guc *guc)
REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
/* Primary GuC and media GuC share a single enable bit */
- xe_mmio_write32(gt, GUC_SG_INTR_ENABLE,
+ xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE,
REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST));
/*
* There are separate mask bits for primary and media GuCs, so use
* a RMW operation to avoid clobbering the other GuC's setting.
*/
- xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0);
+ xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0);
}
int xe_guc_enable_communication(struct xe_guc *guc)
@@ -907,7 +910,7 @@ void xe_guc_notify(struct xe_guc *guc)
* additional payload data to the GuC but this capability is not
* used by the firmware yet. Use default value in the meantime.
*/
- xe_mmio_write32(gt, guc->notify_reg, default_notify_data);
+ xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data);
}
int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr)
@@ -925,6 +928,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
{
struct xe_device *xe = guc_to_xe(guc);
struct xe_gt *gt = guc_to_gt(guc);
+ struct xe_mmio *mmio = >->mmio;
u32 header, reply;
struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?
MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);
@@ -947,19 +951,19 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
/* Not in critical data-path, just do if else for GT type */
if (xe_gt_is_media_type(gt)) {
for (i = 0; i < len; ++i)
- xe_mmio_write32(gt, MED_VF_SW_FLAG(i),
+ xe_mmio_write32(mmio, MED_VF_SW_FLAG(i),
request[i]);
- xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX));
+ xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX));
} else {
for (i = 0; i < len; ++i)
- xe_mmio_write32(gt, VF_SW_FLAG(i),
+ xe_mmio_write32(mmio, VF_SW_FLAG(i),
request[i]);
- xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX));
+ xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX));
}
xe_guc_notify(guc);
- ret = xe_mmio_wait32(gt, reply_reg, GUC_HXG_MSG_0_ORIGIN,
+ ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN,
FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC),
50000, &reply, false);
if (ret) {
@@ -969,7 +973,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
return ret;
}
- header = xe_mmio_read32(gt, reply_reg);
+ header = xe_mmio_read32(mmio, reply_reg);
if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
GUC_HXG_TYPE_NO_RESPONSE_BUSY) {
/*
@@ -985,7 +989,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS);
BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1);
- ret = xe_mmio_wait32(gt, reply_reg, resp_mask, resp_mask,
+ ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask,
1000000, &header, false);
if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
@@ -1032,7 +1036,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
for (i = 1; i < VF_SW_FLAG_COUNT; i++) {
reply_reg.addr += sizeof(u32);
- response_buf[i] = xe_mmio_read32(gt, reply_reg);
+ response_buf[i] = xe_mmio_read32(mmio, reply_reg);
}
}
@@ -1155,7 +1159,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
if (err)
return;
- status = xe_mmio_read32(gt, GUC_STATUS);
+ status = xe_mmio_read32(>->mmio, GUC_STATUS);
drm_printf(p, "\nGuC status 0x%08x:\n", status);
drm_printf(p, "\tBootrom status = 0x%x\n",
@@ -1170,7 +1174,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
drm_puts(p, "\nScratch registers:\n");
for (i = 0; i < SOFT_SCRATCH_COUNT; i++) {
drm_printf(p, "\t%2d: \t0x%x\n",
- i, xe_mmio_read32(gt, SOFT_SCRATCH(i)));
+ i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i)));
}
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index d1902a8581ca..66d4e5e95abd 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -684,7 +684,7 @@ static void guc_doorbell_init(struct xe_guc_ads *ads)
if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) {
u32 distdbreg =
- xe_mmio_read32(gt, DIST_DBS_POPULATED);
+ xe_mmio_read32(>->mmio, DIST_DBS_POPULATED);
ads_blob_write(ads,
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 034b29984d5e..2b654f820ae2 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -262,7 +262,7 @@ static void pc_set_manual_rp_ctrl(struct xe_guc_pc *pc, bool enable)
u32 state = enable ? RPSWCTL_ENABLE : RPSWCTL_DISABLE;
/* Allow/Disallow punit to process software freq requests */
- xe_mmio_write32(gt, RP_CONTROL, state);
+ xe_mmio_write32(>->mmio, RP_CONTROL, state);
}
static void pc_set_cur_freq(struct xe_guc_pc *pc, u32 freq)
@@ -274,7 +274,7 @@ static void pc_set_cur_freq(struct xe_guc_pc *pc, u32 freq)
/* Req freq is in units of 16.66 Mhz */
rpnswreq = REG_FIELD_PREP(REQ_RATIO_MASK, encode_freq(freq));
- xe_mmio_write32(gt, RPNSWREQ, rpnswreq);
+ xe_mmio_write32(>->mmio, RPNSWREQ, rpnswreq);
/* Sleep for a small time to allow pcode to respond */
usleep_range(100, 300);
@@ -334,9 +334,9 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
u32 reg;
if (xe_gt_is_media_type(gt))
- reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY);
+ reg = xe_mmio_read32(>->mmio, MTL_MPE_FREQUENCY);
else
- reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY);
+ reg = xe_mmio_read32(>->mmio, MTL_GT_RPE_FREQUENCY);
pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
}
@@ -353,9 +353,9 @@ static void tgl_update_rpe_value(struct xe_guc_pc *pc)
* PCODE at a different register
*/
if (xe->info.platform == XE_PVC)
- reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
+ reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP);
else
- reg = xe_mmio_read32(gt, FREQ_INFO_REC);
+ reg = xe_mmio_read32(>->mmio, FREQ_INFO_REC);
pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
}
@@ -392,10 +392,10 @@ u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc)
/* When in RC6, actual frequency reported will be 0. */
if (GRAPHICS_VERx100(xe) >= 1270) {
- freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
+ freq = xe_mmio_read32(>->mmio, MTL_MIRROR_TARGET_WP1);
freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);
} else {
- freq = xe_mmio_read32(gt, GT_PERF_STATUS);
+ freq = xe_mmio_read32(>->mmio, GT_PERF_STATUS);
freq = REG_FIELD_GET(CAGF_MASK, freq);
}
@@ -425,7 +425,7 @@ int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq)
if (ret)
return ret;
- *freq = xe_mmio_read32(gt, RPNSWREQ);
+ *freq = xe_mmio_read32(>->mmio, RPNSWREQ);
*freq = REG_FIELD_GET(REQ_RATIO_MASK, *freq);
*freq = decode_freq(*freq);
@@ -612,10 +612,10 @@ enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc)
u32 reg, gt_c_state;
if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
- reg = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
+ reg = xe_mmio_read32(>->mmio, MTL_MIRROR_TARGET_WP1);
gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg);
} else {
- reg = xe_mmio_read32(gt, GT_CORE_STATUS);
+ reg = xe_mmio_read32(>->mmio, GT_CORE_STATUS);
gt_c_state = REG_FIELD_GET(RCN_MASK, reg);
}
@@ -638,7 +638,7 @@ u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc)
struct xe_gt *gt = pc_to_gt(pc);
u32 reg;
- reg = xe_mmio_read32(gt, GT_GFX_RC6);
+ reg = xe_mmio_read32(>->mmio, GT_GFX_RC6);
return reg;
}
@@ -652,7 +652,7 @@ u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc)
struct xe_gt *gt = pc_to_gt(pc);
u64 reg;
- reg = xe_mmio_read32(gt, MTL_MEDIA_MC6);
+ reg = xe_mmio_read32(>->mmio, MTL_MEDIA_MC6);
return reg;
}
@@ -665,9 +665,9 @@ static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)
xe_device_assert_mem_access(pc_to_xe(pc));
if (xe_gt_is_media_type(gt))
- reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP);
+ reg = xe_mmio_read32(>->mmio, MTL_MEDIAP_STATE_CAP);
else
- reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP);
+ reg = xe_mmio_read32(>->mmio, MTL_RP_STATE_CAP);
pc->rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg));
@@ -683,9 +683,9 @@ static void tgl_init_fused_rp_values(struct xe_guc_pc *pc)
xe_device_assert_mem_access(pc_to_xe(pc));
if (xe->info.platform == XE_PVC)
- reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
+ reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP);
else
- reg = xe_mmio_read32(gt, RP_STATE_CAP);
+ reg = xe_mmio_read32(>->mmio, RP_STATE_CAP);
pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
}
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 29f4e3759106..ccf53a7840d9 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -430,8 +430,8 @@ int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
* This function works exactly like xe_mmio_wait32() with the exception that
* @val is expected not to be matched.
*/
-int __xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
- u32 *out_val, bool atomic)
+int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
+ u32 *out_val, bool atomic)
{
return ____xe_mmio_wait32(mmio, reg, mask, val, timeout_us, out_val, atomic, false);
}
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 99e3b58c9bb2..2e97dc811d82 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -56,10 +56,8 @@ int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
#define xe_mmio_wait32(p, reg, mask, val, timeout_us, out_val, atomic) \
__xe_mmio_wait32(__to_xe_mmio(p), reg, mask, val, timeout_us, out_val, atomic)
-int __xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,
- u32 val, u32 timeout_us, u32 *out_val, bool atomic);
-#define xe_mmio_wait32_not(p, reg, mask, val, timeout_us, out_val, atomic) \
- __xe_mmio_wait32_not(__to_xe_mmio(p), reg, mask, val, timeout_us, out_val, atomic)
+int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,
+ u32 val, u32 timeout_us, u32 *out_val, bool atomic);
static inline u32 __xe_mmio_adjusted_addr(const struct xe_mmio *mmio, u32 addr)
{
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 21/43] drm/xe/guc: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 21/43] drm/xe/guc: " Matt Roper
@ 2024-09-10 18:48 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:48 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:10PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Since GuC was the only part of the driver using xe_mmio_wait32_not(), we
> can also drop the _Generic wrapper macro for that function as well.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc.c | 60 ++++++++++++++++++---------------
> drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_pc.c | 34 +++++++++----------
> drivers/gpu/drm/xe/xe_mmio.c | 4 +--
> drivers/gpu/drm/xe/xe_mmio.h | 6 ++--
> 5 files changed, 54 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 5599464013bd..1eb5bb7e8771 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -236,10 +236,10 @@ static void guc_write_params(struct xe_guc *guc)
>
> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>
> - xe_mmio_write32(gt, SOFT_SCRATCH(0), 0);
> + xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0);
>
> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> - xe_mmio_write32(gt, SOFT_SCRATCH(1 + i), guc->params[i]);
> + xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]);
> }
>
> static void guc_fini_hw(void *arg)
> @@ -425,6 +425,7 @@ int xe_guc_post_load_init(struct xe_guc *guc)
> int xe_guc_reset(struct xe_guc *guc)
> {
> struct xe_gt *gt = guc_to_gt(guc);
> + struct xe_mmio *mmio = >->mmio;
> u32 guc_status, gdrst;
> int ret;
>
> @@ -433,15 +434,15 @@ int xe_guc_reset(struct xe_guc *guc)
> if (IS_SRIOV_VF(gt_to_xe(gt)))
> return xe_gt_sriov_vf_bootstrap(gt);
>
> - xe_mmio_write32(gt, GDRST, GRDOM_GUC);
> + xe_mmio_write32(mmio, GDRST, GRDOM_GUC);
>
> - ret = xe_mmio_wait32(gt, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false);
> + ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false);
> if (ret) {
> xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst);
> goto err_out;
> }
>
> - guc_status = xe_mmio_read32(gt, GUC_STATUS);
> + guc_status = xe_mmio_read32(mmio, GUC_STATUS);
> if (!(guc_status & GS_MIA_IN_RESET)) {
> xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n",
> guc_status);
> @@ -459,6 +460,7 @@ int xe_guc_reset(struct xe_guc *guc)
> static void guc_prepare_xfer(struct xe_guc *guc)
> {
> struct xe_gt *gt = guc_to_gt(guc);
> + struct xe_mmio *mmio = >->mmio;
> struct xe_device *xe = guc_to_xe(guc);
> u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
> GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
> @@ -473,12 +475,12 @@ static void guc_prepare_xfer(struct xe_guc *guc)
> shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index);
>
> /* Must program this register before loading the ucode with DMA */
> - xe_mmio_write32(gt, GUC_SHIM_CONTROL, shim_flags);
> + xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags);
>
> - xe_mmio_write32(gt, GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> + xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>
> /* Make sure GuC receives ARAT interrupts */
> - xe_mmio_rmw32(gt, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0);
> + xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0);
> }
>
> /*
> @@ -494,7 +496,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
> if (guc->fw.rsa_size > 256) {
> u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) +
> xe_uc_fw_rsa_offset(&guc->fw);
> - xe_mmio_write32(gt, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);
> + xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr);
> return 0;
> }
>
> @@ -503,7 +505,7 @@ static int guc_xfer_rsa(struct xe_guc *guc)
> return -ENOMEM;
>
> for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
> - xe_mmio_write32(gt, UOS_RSA_SCRATCH(i), rsa[i]);
> + xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]);
>
> return 0;
> }
> @@ -593,6 +595,7 @@ static s32 guc_pc_get_cur_freq(struct xe_guc_pc *guc_pc)
> static void guc_wait_ucode(struct xe_guc *guc)
> {
> struct xe_gt *gt = guc_to_gt(guc);
> + struct xe_mmio *mmio = >->mmio;
> struct xe_guc_pc *guc_pc = >->uc.guc.pc;
> ktime_t before, after, delta;
> int load_done;
> @@ -619,7 +622,7 @@ static void guc_wait_ucode(struct xe_guc *guc)
> * timeouts rather than allowing a huge timeout each time. So basically, need
> * to treat a timeout no different to a value change.
> */
> - ret = xe_mmio_wait32_not(gt, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK,
> + ret = xe_mmio_wait32_not(mmio, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK,
> last_status, 1000 * 1000, &status, false);
> if (ret < 0)
> count++;
> @@ -657,7 +660,7 @@ static void guc_wait_ucode(struct xe_guc *guc)
> switch (bootrom) {
> case XE_BOOTROM_STATUS_NO_KEY_FOUND:
> xe_gt_err(gt, "invalid key requested, header = 0x%08X\n",
> - xe_mmio_read32(gt, GUC_HEADER_INFO));
> + xe_mmio_read32(mmio, GUC_HEADER_INFO));
> break;
>
> case XE_BOOTROM_STATUS_RSA_FAILED:
> @@ -672,7 +675,7 @@ static void guc_wait_ucode(struct xe_guc *guc)
> switch (ukernel) {
> case XE_GUC_LOAD_STATUS_EXCEPTION:
> xe_gt_err(gt, "firmware exception. EIP: %#x\n",
> - xe_mmio_read32(gt, SOFT_SCRATCH(13)));
> + xe_mmio_read32(mmio, SOFT_SCRATCH(13)));
> break;
>
> case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID:
> @@ -824,10 +827,10 @@ static void guc_handle_mmio_msg(struct xe_guc *guc)
>
> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>
> - msg = xe_mmio_read32(gt, SOFT_SCRATCH(15));
> + msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15));
> msg &= XE_GUC_RECV_MSG_EXCEPTION |
> XE_GUC_RECV_MSG_CRASH_DUMP_POSTED;
> - xe_mmio_write32(gt, SOFT_SCRATCH(15), 0);
> + xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0);
>
> if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED)
> xe_gt_err(gt, "Received early GuC crash dump notification!\n");
> @@ -844,14 +847,14 @@ static void guc_enable_irq(struct xe_guc *guc)
> REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
>
> /* Primary GuC and media GuC share a single enable bit */
> - xe_mmio_write32(gt, GUC_SG_INTR_ENABLE,
> + xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE,
> REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST));
>
> /*
> * There are separate mask bits for primary and media GuCs, so use
> * a RMW operation to avoid clobbering the other GuC's setting.
> */
> - xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0);
> + xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0);
> }
>
> int xe_guc_enable_communication(struct xe_guc *guc)
> @@ -907,7 +910,7 @@ void xe_guc_notify(struct xe_guc *guc)
> * additional payload data to the GuC but this capability is not
> * used by the firmware yet. Use default value in the meantime.
> */
> - xe_mmio_write32(gt, guc->notify_reg, default_notify_data);
> + xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data);
> }
>
> int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr)
> @@ -925,6 +928,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
> {
> struct xe_device *xe = guc_to_xe(guc);
> struct xe_gt *gt = guc_to_gt(guc);
> + struct xe_mmio *mmio = >->mmio;
> u32 header, reply;
> struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?
> MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);
> @@ -947,19 +951,19 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
> /* Not in critical data-path, just do if else for GT type */
> if (xe_gt_is_media_type(gt)) {
> for (i = 0; i < len; ++i)
> - xe_mmio_write32(gt, MED_VF_SW_FLAG(i),
> + xe_mmio_write32(mmio, MED_VF_SW_FLAG(i),
> request[i]);
> - xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX));
> + xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX));
> } else {
> for (i = 0; i < len; ++i)
> - xe_mmio_write32(gt, VF_SW_FLAG(i),
> + xe_mmio_write32(mmio, VF_SW_FLAG(i),
> request[i]);
> - xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX));
> + xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX));
> }
>
> xe_guc_notify(guc);
>
> - ret = xe_mmio_wait32(gt, reply_reg, GUC_HXG_MSG_0_ORIGIN,
> + ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN,
> FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC),
> 50000, &reply, false);
> if (ret) {
> @@ -969,7 +973,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
> return ret;
> }
>
> - header = xe_mmio_read32(gt, reply_reg);
> + header = xe_mmio_read32(mmio, reply_reg);
> if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) ==
> GUC_HXG_TYPE_NO_RESPONSE_BUSY) {
> /*
> @@ -985,7 +989,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
> BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS);
> BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1);
>
> - ret = xe_mmio_wait32(gt, reply_reg, resp_mask, resp_mask,
> + ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask,
> 1000000, &header, false);
>
> if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
> @@ -1032,7 +1036,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
>
> for (i = 1; i < VF_SW_FLAG_COUNT; i++) {
> reply_reg.addr += sizeof(u32);
> - response_buf[i] = xe_mmio_read32(gt, reply_reg);
> + response_buf[i] = xe_mmio_read32(mmio, reply_reg);
> }
> }
>
> @@ -1155,7 +1159,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
> if (err)
> return;
>
> - status = xe_mmio_read32(gt, GUC_STATUS);
> + status = xe_mmio_read32(>->mmio, GUC_STATUS);
>
> drm_printf(p, "\nGuC status 0x%08x:\n", status);
> drm_printf(p, "\tBootrom status = 0x%x\n",
> @@ -1170,7 +1174,7 @@ void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p)
> drm_puts(p, "\nScratch registers:\n");
> for (i = 0; i < SOFT_SCRATCH_COUNT; i++) {
> drm_printf(p, "\t%2d: \t0x%x\n",
> - i, xe_mmio_read32(gt, SOFT_SCRATCH(i)));
> + i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i)));
> }
>
> xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index d1902a8581ca..66d4e5e95abd 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -684,7 +684,7 @@ static void guc_doorbell_init(struct xe_guc_ads *ads)
>
> if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) {
> u32 distdbreg =
> - xe_mmio_read32(gt, DIST_DBS_POPULATED);
> + xe_mmio_read32(>->mmio, DIST_DBS_POPULATED);
>
> ads_blob_write(ads,
> system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index 034b29984d5e..2b654f820ae2 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -262,7 +262,7 @@ static void pc_set_manual_rp_ctrl(struct xe_guc_pc *pc, bool enable)
> u32 state = enable ? RPSWCTL_ENABLE : RPSWCTL_DISABLE;
>
> /* Allow/Disallow punit to process software freq requests */
> - xe_mmio_write32(gt, RP_CONTROL, state);
> + xe_mmio_write32(>->mmio, RP_CONTROL, state);
> }
>
> static void pc_set_cur_freq(struct xe_guc_pc *pc, u32 freq)
> @@ -274,7 +274,7 @@ static void pc_set_cur_freq(struct xe_guc_pc *pc, u32 freq)
>
> /* Req freq is in units of 16.66 Mhz */
> rpnswreq = REG_FIELD_PREP(REQ_RATIO_MASK, encode_freq(freq));
> - xe_mmio_write32(gt, RPNSWREQ, rpnswreq);
> + xe_mmio_write32(>->mmio, RPNSWREQ, rpnswreq);
>
> /* Sleep for a small time to allow pcode to respond */
> usleep_range(100, 300);
> @@ -334,9 +334,9 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc)
> u32 reg;
>
> if (xe_gt_is_media_type(gt))
> - reg = xe_mmio_read32(gt, MTL_MPE_FREQUENCY);
> + reg = xe_mmio_read32(>->mmio, MTL_MPE_FREQUENCY);
> else
> - reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY);
> + reg = xe_mmio_read32(>->mmio, MTL_GT_RPE_FREQUENCY);
>
> pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg));
> }
> @@ -353,9 +353,9 @@ static void tgl_update_rpe_value(struct xe_guc_pc *pc)
> * PCODE at a different register
> */
> if (xe->info.platform == XE_PVC)
> - reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
> + reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP);
> else
> - reg = xe_mmio_read32(gt, FREQ_INFO_REC);
> + reg = xe_mmio_read32(>->mmio, FREQ_INFO_REC);
>
> pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> }
> @@ -392,10 +392,10 @@ u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc)
>
> /* When in RC6, actual frequency reported will be 0. */
> if (GRAPHICS_VERx100(xe) >= 1270) {
> - freq = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
> + freq = xe_mmio_read32(>->mmio, MTL_MIRROR_TARGET_WP1);
> freq = REG_FIELD_GET(MTL_CAGF_MASK, freq);
> } else {
> - freq = xe_mmio_read32(gt, GT_PERF_STATUS);
> + freq = xe_mmio_read32(>->mmio, GT_PERF_STATUS);
> freq = REG_FIELD_GET(CAGF_MASK, freq);
> }
>
> @@ -425,7 +425,7 @@ int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq)
> if (ret)
> return ret;
>
> - *freq = xe_mmio_read32(gt, RPNSWREQ);
> + *freq = xe_mmio_read32(>->mmio, RPNSWREQ);
>
> *freq = REG_FIELD_GET(REQ_RATIO_MASK, *freq);
> *freq = decode_freq(*freq);
> @@ -612,10 +612,10 @@ enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc)
> u32 reg, gt_c_state;
>
> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
> - reg = xe_mmio_read32(gt, MTL_MIRROR_TARGET_WP1);
> + reg = xe_mmio_read32(>->mmio, MTL_MIRROR_TARGET_WP1);
> gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg);
> } else {
> - reg = xe_mmio_read32(gt, GT_CORE_STATUS);
> + reg = xe_mmio_read32(>->mmio, GT_CORE_STATUS);
> gt_c_state = REG_FIELD_GET(RCN_MASK, reg);
> }
>
> @@ -638,7 +638,7 @@ u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc)
> struct xe_gt *gt = pc_to_gt(pc);
> u32 reg;
>
> - reg = xe_mmio_read32(gt, GT_GFX_RC6);
> + reg = xe_mmio_read32(>->mmio, GT_GFX_RC6);
>
> return reg;
> }
> @@ -652,7 +652,7 @@ u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc)
> struct xe_gt *gt = pc_to_gt(pc);
> u64 reg;
>
> - reg = xe_mmio_read32(gt, MTL_MEDIA_MC6);
> + reg = xe_mmio_read32(>->mmio, MTL_MEDIA_MC6);
>
> return reg;
> }
> @@ -665,9 +665,9 @@ static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)
> xe_device_assert_mem_access(pc_to_xe(pc));
>
> if (xe_gt_is_media_type(gt))
> - reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP);
> + reg = xe_mmio_read32(>->mmio, MTL_MEDIAP_STATE_CAP);
> else
> - reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP);
> + reg = xe_mmio_read32(>->mmio, MTL_RP_STATE_CAP);
>
> pc->rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg));
>
> @@ -683,9 +683,9 @@ static void tgl_init_fused_rp_values(struct xe_guc_pc *pc)
> xe_device_assert_mem_access(pc_to_xe(pc));
>
> if (xe->info.platform == XE_PVC)
> - reg = xe_mmio_read32(gt, PVC_RP_STATE_CAP);
> + reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP);
> else
> - reg = xe_mmio_read32(gt, RP_STATE_CAP);
> + reg = xe_mmio_read32(>->mmio, RP_STATE_CAP);
> pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER;
> }
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index 29f4e3759106..ccf53a7840d9 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -430,8 +430,8 @@ int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
> * This function works exactly like xe_mmio_wait32() with the exception that
> * @val is expected not to be matched.
> */
> -int __xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
> - u32 *out_val, bool atomic)
> +int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
> + u32 *out_val, bool atomic)
> {
> return ____xe_mmio_wait32(mmio, reg, mask, val, timeout_us, out_val, atomic, false);
> }
> diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
> index 99e3b58c9bb2..2e97dc811d82 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.h
> +++ b/drivers/gpu/drm/xe/xe_mmio.h
> @@ -56,10 +56,8 @@ int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
> #define xe_mmio_wait32(p, reg, mask, val, timeout_us, out_val, atomic) \
> __xe_mmio_wait32(__to_xe_mmio(p), reg, mask, val, timeout_us, out_val, atomic)
>
> -int __xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,
> - u32 val, u32 timeout_us, u32 *out_val, bool atomic);
> -#define xe_mmio_wait32_not(p, reg, mask, val, timeout_us, out_val, atomic) \
> - __xe_mmio_wait32_not(__to_xe_mmio(p), reg, mask, val, timeout_us, out_val, atomic)
> +int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,
> + u32 val, u32 timeout_us, u32 *out_val, bool atomic);
>
shouldn't this go with the last patch?
Or avoid the last patch and then in every last usage of a case, like this,
you remove the unused compat layer?
> static inline u32 __xe_mmio_adjusted_addr(const struct xe_mmio *mmio, u32 addr)
> {
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 22/43] drm/xe/huc: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (20 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 21/43] drm/xe/guc: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:44 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 23/43] drm/xe/gsc: " Matt Roper
` (28 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_huc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
index f5459f97af23..77c5830309cf 100644
--- a/drivers/gpu/drm/xe/xe_huc.c
+++ b/drivers/gpu/drm/xe/xe_huc.c
@@ -229,7 +229,7 @@ bool xe_huc_is_authenticated(struct xe_huc *huc, enum xe_huc_auth_types type)
{
struct xe_gt *gt = huc_to_gt(huc);
- return xe_mmio_read32(gt, huc_auth_modes[type].reg) & huc_auth_modes[type].val;
+ return xe_mmio_read32(>->mmio, huc_auth_modes[type].reg) & huc_auth_modes[type].val;
}
int xe_huc_auth(struct xe_huc *huc, enum xe_huc_auth_types type)
@@ -268,7 +268,7 @@ int xe_huc_auth(struct xe_huc *huc, enum xe_huc_auth_types type)
goto fail;
}
- ret = xe_mmio_wait32(gt, huc_auth_modes[type].reg, huc_auth_modes[type].val,
+ ret = xe_mmio_wait32(>->mmio, huc_auth_modes[type].reg, huc_auth_modes[type].val,
huc_auth_modes[type].val, 100000, NULL, false);
if (ret) {
xe_gt_err(gt, "HuC: firmware not verified: %pe\n", ERR_PTR(ret));
@@ -308,7 +308,7 @@ void xe_huc_print_info(struct xe_huc *huc, struct drm_printer *p)
return;
drm_printf(p, "\nHuC status: 0x%08x\n",
- xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO));
+ xe_mmio_read32(>->mmio, HUC_KERNEL_LOAD_INFO));
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 22/43] drm/xe/huc: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 22/43] drm/xe/huc: " Matt Roper
@ 2024-09-10 18:44 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:44 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:11PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_huc.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_huc.c b/drivers/gpu/drm/xe/xe_huc.c
> index f5459f97af23..77c5830309cf 100644
> --- a/drivers/gpu/drm/xe/xe_huc.c
> +++ b/drivers/gpu/drm/xe/xe_huc.c
> @@ -229,7 +229,7 @@ bool xe_huc_is_authenticated(struct xe_huc *huc, enum xe_huc_auth_types type)
> {
> struct xe_gt *gt = huc_to_gt(huc);
>
> - return xe_mmio_read32(gt, huc_auth_modes[type].reg) & huc_auth_modes[type].val;
> + return xe_mmio_read32(>->mmio, huc_auth_modes[type].reg) & huc_auth_modes[type].val;
> }
>
> int xe_huc_auth(struct xe_huc *huc, enum xe_huc_auth_types type)
> @@ -268,7 +268,7 @@ int xe_huc_auth(struct xe_huc *huc, enum xe_huc_auth_types type)
> goto fail;
> }
>
> - ret = xe_mmio_wait32(gt, huc_auth_modes[type].reg, huc_auth_modes[type].val,
> + ret = xe_mmio_wait32(>->mmio, huc_auth_modes[type].reg, huc_auth_modes[type].val,
> huc_auth_modes[type].val, 100000, NULL, false);
> if (ret) {
> xe_gt_err(gt, "HuC: firmware not verified: %pe\n", ERR_PTR(ret));
> @@ -308,7 +308,7 @@ void xe_huc_print_info(struct xe_huc *huc, struct drm_printer *p)
> return;
>
> drm_printf(p, "\nHuC status: 0x%08x\n",
> - xe_mmio_read32(gt, HUC_KERNEL_LOAD_INFO));
> + xe_mmio_read32(>->mmio, HUC_KERNEL_LOAD_INFO));
>
> xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> }
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 23/43] drm/xe/gsc: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (21 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 22/43] drm/xe/huc: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:08 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 24/43] drm/xe/query: " Matt Roper
` (27 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gsc.c | 23 ++++++++++++-----------
drivers/gpu/drm/xe/xe_gsc_proxy.c | 4 ++--
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
index 6fbea70d3d36..9cb326af5931 100644
--- a/drivers/gpu/drm/xe/xe_gsc.c
+++ b/drivers/gpu/drm/xe/xe_gsc.c
@@ -179,7 +179,7 @@ static int query_compatibility_version(struct xe_gsc *gsc)
static int gsc_fw_is_loaded(struct xe_gt *gt)
{
- return xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) &
+ return xe_mmio_read32(>->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) &
HECI1_FWSTS1_INIT_COMPLETE;
}
@@ -190,7 +190,7 @@ static int gsc_fw_wait(struct xe_gt *gt)
* executed by the GSCCS. To account for possible submission delays or
* other issues, we use a 500ms timeout in the wait here.
*/
- return xe_mmio_wait32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE),
+ return xe_mmio_wait32(>->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE),
HECI1_FWSTS1_INIT_COMPLETE,
HECI1_FWSTS1_INIT_COMPLETE,
500 * USEC_PER_MSEC, NULL, false);
@@ -330,7 +330,7 @@ static int gsc_er_complete(struct xe_gt *gt)
* so in that scenario we're always guaranteed to find the correct
* value.
*/
- er_status = xe_mmio_read32(gt, GSCI_TIMER_STATUS) & GSCI_TIMER_STATUS_VALUE;
+ er_status = xe_mmio_read32(>->mmio, GSCI_TIMER_STATUS) & GSCI_TIMER_STATUS_VALUE;
if (er_status == GSCI_TIMER_STATUS_TIMER_EXPIRED) {
/*
@@ -581,11 +581,11 @@ void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep)
if (!XE_WA(gt, 14015076503) || !gsc_fw_is_loaded(gt))
return;
- xe_mmio_rmw32(gt, HECI_H_GS1(MTL_GSC_HECI2_BASE), gs1_clr, gs1_set);
+ xe_mmio_rmw32(>->mmio, HECI_H_GS1(MTL_GSC_HECI2_BASE), gs1_clr, gs1_set);
if (prep) {
/* make sure the reset bit is clear when writing the CSR reg */
- xe_mmio_rmw32(gt, HECI_H_CSR(MTL_GSC_HECI2_BASE),
+ xe_mmio_rmw32(>->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE),
HECI_H_CSR_RST, HECI_H_CSR_IG);
msleep(200);
}
@@ -599,6 +599,7 @@ void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep)
void xe_gsc_print_info(struct xe_gsc *gsc, struct drm_printer *p)
{
struct xe_gt *gt = gsc_to_gt(gsc);
+ struct xe_mmio *mmio = >->mmio;
int err;
xe_uc_fw_print(&gsc->fw, p);
@@ -613,12 +614,12 @@ void xe_gsc_print_info(struct xe_gsc *gsc, struct drm_printer *p)
return;
drm_printf(p, "\nHECI1 FWSTS: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
- xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE)),
- xe_mmio_read32(gt, HECI_FWSTS2(MTL_GSC_HECI1_BASE)),
- xe_mmio_read32(gt, HECI_FWSTS3(MTL_GSC_HECI1_BASE)),
- xe_mmio_read32(gt, HECI_FWSTS4(MTL_GSC_HECI1_BASE)),
- xe_mmio_read32(gt, HECI_FWSTS5(MTL_GSC_HECI1_BASE)),
- xe_mmio_read32(gt, HECI_FWSTS6(MTL_GSC_HECI1_BASE)));
+ xe_mmio_read32(mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(mmio, HECI_FWSTS2(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(mmio, HECI_FWSTS3(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(mmio, HECI_FWSTS4(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(mmio, HECI_FWSTS5(MTL_GSC_HECI1_BASE)),
+ xe_mmio_read32(mmio, HECI_FWSTS6(MTL_GSC_HECI1_BASE)));
xe_force_wake_put(gt_to_fw(gt), XE_FW_GSC);
}
diff --git a/drivers/gpu/drm/xe/xe_gsc_proxy.c b/drivers/gpu/drm/xe/xe_gsc_proxy.c
index 2d6ea8c01445..6d89c22ae811 100644
--- a/drivers/gpu/drm/xe/xe_gsc_proxy.c
+++ b/drivers/gpu/drm/xe/xe_gsc_proxy.c
@@ -65,7 +65,7 @@ gsc_to_gt(struct xe_gsc *gsc)
bool xe_gsc_proxy_init_done(struct xe_gsc *gsc)
{
struct xe_gt *gt = gsc_to_gt(gsc);
- u32 fwsts1 = xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE));
+ u32 fwsts1 = xe_mmio_read32(>->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE));
return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fwsts1) ==
HECI1_FWSTS1_PROXY_STATE_NORMAL;
@@ -78,7 +78,7 @@ static void __gsc_proxy_irq_rmw(struct xe_gsc *gsc, u32 clr, u32 set)
/* make sure we never accidentally write the RST bit */
clr |= HECI_H_CSR_RST;
- xe_mmio_rmw32(gt, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set);
+ xe_mmio_rmw32(>->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set);
}
static void gsc_proxy_irq_clear(struct xe_gsc *gsc)
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 23/43] drm/xe/gsc: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 23/43] drm/xe/gsc: " Matt Roper
@ 2024-09-10 18:08 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:08 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:12PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gsc.c | 23 ++++++++++++-----------
> drivers/gpu/drm/xe/xe_gsc_proxy.c | 4 ++--
> 2 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
> index 6fbea70d3d36..9cb326af5931 100644
> --- a/drivers/gpu/drm/xe/xe_gsc.c
> +++ b/drivers/gpu/drm/xe/xe_gsc.c
> @@ -179,7 +179,7 @@ static int query_compatibility_version(struct xe_gsc *gsc)
>
> static int gsc_fw_is_loaded(struct xe_gt *gt)
> {
> - return xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) &
> + return xe_mmio_read32(>->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) &
> HECI1_FWSTS1_INIT_COMPLETE;
> }
>
> @@ -190,7 +190,7 @@ static int gsc_fw_wait(struct xe_gt *gt)
> * executed by the GSCCS. To account for possible submission delays or
> * other issues, we use a 500ms timeout in the wait here.
> */
> - return xe_mmio_wait32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE),
> + return xe_mmio_wait32(>->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE),
> HECI1_FWSTS1_INIT_COMPLETE,
> HECI1_FWSTS1_INIT_COMPLETE,
> 500 * USEC_PER_MSEC, NULL, false);
> @@ -330,7 +330,7 @@ static int gsc_er_complete(struct xe_gt *gt)
> * so in that scenario we're always guaranteed to find the correct
> * value.
> */
> - er_status = xe_mmio_read32(gt, GSCI_TIMER_STATUS) & GSCI_TIMER_STATUS_VALUE;
> + er_status = xe_mmio_read32(>->mmio, GSCI_TIMER_STATUS) & GSCI_TIMER_STATUS_VALUE;
>
> if (er_status == GSCI_TIMER_STATUS_TIMER_EXPIRED) {
> /*
> @@ -581,11 +581,11 @@ void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep)
> if (!XE_WA(gt, 14015076503) || !gsc_fw_is_loaded(gt))
> return;
>
> - xe_mmio_rmw32(gt, HECI_H_GS1(MTL_GSC_HECI2_BASE), gs1_clr, gs1_set);
> + xe_mmio_rmw32(>->mmio, HECI_H_GS1(MTL_GSC_HECI2_BASE), gs1_clr, gs1_set);
>
> if (prep) {
> /* make sure the reset bit is clear when writing the CSR reg */
> - xe_mmio_rmw32(gt, HECI_H_CSR(MTL_GSC_HECI2_BASE),
> + xe_mmio_rmw32(>->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE),
> HECI_H_CSR_RST, HECI_H_CSR_IG);
> msleep(200);
> }
> @@ -599,6 +599,7 @@ void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep)
> void xe_gsc_print_info(struct xe_gsc *gsc, struct drm_printer *p)
> {
> struct xe_gt *gt = gsc_to_gt(gsc);
> + struct xe_mmio *mmio = >->mmio;
> int err;
>
> xe_uc_fw_print(&gsc->fw, p);
> @@ -613,12 +614,12 @@ void xe_gsc_print_info(struct xe_gsc *gsc, struct drm_printer *p)
> return;
>
> drm_printf(p, "\nHECI1 FWSTS: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
> - xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE)),
> - xe_mmio_read32(gt, HECI_FWSTS2(MTL_GSC_HECI1_BASE)),
> - xe_mmio_read32(gt, HECI_FWSTS3(MTL_GSC_HECI1_BASE)),
> - xe_mmio_read32(gt, HECI_FWSTS4(MTL_GSC_HECI1_BASE)),
> - xe_mmio_read32(gt, HECI_FWSTS5(MTL_GSC_HECI1_BASE)),
> - xe_mmio_read32(gt, HECI_FWSTS6(MTL_GSC_HECI1_BASE)));
> + xe_mmio_read32(mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)),
> + xe_mmio_read32(mmio, HECI_FWSTS2(MTL_GSC_HECI1_BASE)),
> + xe_mmio_read32(mmio, HECI_FWSTS3(MTL_GSC_HECI1_BASE)),
> + xe_mmio_read32(mmio, HECI_FWSTS4(MTL_GSC_HECI1_BASE)),
> + xe_mmio_read32(mmio, HECI_FWSTS5(MTL_GSC_HECI1_BASE)),
> + xe_mmio_read32(mmio, HECI_FWSTS6(MTL_GSC_HECI1_BASE)));
>
> xe_force_wake_put(gt_to_fw(gt), XE_FW_GSC);
> }
> diff --git a/drivers/gpu/drm/xe/xe_gsc_proxy.c b/drivers/gpu/drm/xe/xe_gsc_proxy.c
> index 2d6ea8c01445..6d89c22ae811 100644
> --- a/drivers/gpu/drm/xe/xe_gsc_proxy.c
> +++ b/drivers/gpu/drm/xe/xe_gsc_proxy.c
> @@ -65,7 +65,7 @@ gsc_to_gt(struct xe_gsc *gsc)
> bool xe_gsc_proxy_init_done(struct xe_gsc *gsc)
> {
> struct xe_gt *gt = gsc_to_gt(gsc);
> - u32 fwsts1 = xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE));
> + u32 fwsts1 = xe_mmio_read32(>->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE));
>
> return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fwsts1) ==
> HECI1_FWSTS1_PROXY_STATE_NORMAL;
> @@ -78,7 +78,7 @@ static void __gsc_proxy_irq_rmw(struct xe_gsc *gsc, u32 clr, u32 set)
> /* make sure we never accidentally write the RST bit */
> clr |= HECI_H_CSR_RST;
>
> - xe_mmio_rmw32(gt, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set);
> + xe_mmio_rmw32(>->mmio, HECI_H_CSR(MTL_GSC_HECI2_BASE), clr, set);
> }
>
> static void gsc_proxy_irq_clear(struct xe_gsc *gsc)
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 24/43] drm/xe/query: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (22 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 23/43] drm/xe/gsc: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:44 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 25/43] drm/xe/mcr: " Matt Roper
` (26 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_query.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index 28d9bb3b825d..5246a4a2740e 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -91,16 +91,17 @@ __read_timestamps(struct xe_gt *gt,
u64 *cpu_delta,
__ktime_func_t cpu_clock)
{
+ struct xe_mmio *mmio = >->mmio;
u32 upper, lower, old_upper, loop = 0;
- upper = xe_mmio_read32(gt, upper_reg);
+ upper = xe_mmio_read32(mmio, upper_reg);
do {
*cpu_delta = local_clock();
*cpu_ts = cpu_clock();
- lower = xe_mmio_read32(gt, lower_reg);
+ lower = xe_mmio_read32(mmio, lower_reg);
*cpu_delta = local_clock() - *cpu_delta;
old_upper = upper;
- upper = xe_mmio_read32(gt, upper_reg);
+ upper = xe_mmio_read32(mmio, upper_reg);
} while (upper != old_upper && loop++ < 2);
*engine_ts = (u64)upper << 32 | lower;
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 24/43] drm/xe/query: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 24/43] drm/xe/query: " Matt Roper
@ 2024-09-10 18:44 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:44 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:13PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_query.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
> index 28d9bb3b825d..5246a4a2740e 100644
> --- a/drivers/gpu/drm/xe/xe_query.c
> +++ b/drivers/gpu/drm/xe/xe_query.c
> @@ -91,16 +91,17 @@ __read_timestamps(struct xe_gt *gt,
> u64 *cpu_delta,
> __ktime_func_t cpu_clock)
> {
> + struct xe_mmio *mmio = >->mmio;
> u32 upper, lower, old_upper, loop = 0;
>
> - upper = xe_mmio_read32(gt, upper_reg);
> + upper = xe_mmio_read32(mmio, upper_reg);
> do {
> *cpu_delta = local_clock();
> *cpu_ts = cpu_clock();
> - lower = xe_mmio_read32(gt, lower_reg);
> + lower = xe_mmio_read32(mmio, lower_reg);
> *cpu_delta = local_clock() - *cpu_delta;
> old_upper = upper;
> - upper = xe_mmio_read32(gt, upper_reg);
> + upper = xe_mmio_read32(mmio, upper_reg);
> } while (upper != old_upper && loop++ < 2);
>
> *engine_ts = (u64)upper << 32 | lower;
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 25/43] drm/xe/mcr: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (23 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 24/43] drm/xe/query: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:11 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 26/43] drm/xe/mocs: " Matt Roper
` (25 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt_mcr.c | 39 ++++++++++++++++++----------------
1 file changed, 21 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
index 7d7bd0be6233..2671ce6b1a76 100644
--- a/drivers/gpu/drm/xe/xe_gt_mcr.c
+++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
@@ -239,11 +239,13 @@ static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
static void init_steering_l3bank(struct xe_gt *gt)
{
+ struct xe_mmio *mmio = >->mmio;
+
if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
- xe_mmio_read32(gt, MIRROR_FUSE3));
+ xe_mmio_read32(mmio, MIRROR_FUSE3));
u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,
- xe_mmio_read32(gt, XEHP_FUSE4));
+ xe_mmio_read32(mmio, XEHP_FUSE4));
/*
* Group selects mslice, instance selects bank within mslice.
@@ -254,7 +256,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
bank_mask & BIT(0) ? 0 : 2;
} else if (gt_to_xe(gt)->info.platform == XE_DG2) {
u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
- xe_mmio_read32(gt, MIRROR_FUSE3));
+ xe_mmio_read32(mmio, MIRROR_FUSE3));
u32 bank = __ffs(mslice_mask) * 8;
/*
@@ -266,7 +268,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
gt->steering[L3BANK].instance_target = bank & 0x3;
} else {
u32 fuse = REG_FIELD_GET(L3BANK_MASK,
- ~xe_mmio_read32(gt, MIRROR_FUSE3));
+ ~xe_mmio_read32(mmio, MIRROR_FUSE3));
gt->steering[L3BANK].group_target = 0; /* unused */
gt->steering[L3BANK].instance_target = __ffs(fuse);
@@ -276,7 +278,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
static void init_steering_mslice(struct xe_gt *gt)
{
u32 mask = REG_FIELD_GET(MEML3_EN_MASK,
- xe_mmio_read32(gt, MIRROR_FUSE3));
+ xe_mmio_read32(>->mmio, MIRROR_FUSE3));
/*
* mslice registers are valid (not terminated) if either the meml3
@@ -380,7 +382,7 @@ static void init_steering_oaddrm(struct xe_gt *gt)
static void init_steering_sqidi_psmi(struct xe_gt *gt)
{
u32 mask = REG_FIELD_GET(XE2_NODE_ENABLE_MASK,
- xe_mmio_read32(gt, MIRROR_FUSE3));
+ xe_mmio_read32(>->mmio, MIRROR_FUSE3));
u32 select = __ffs(mask);
gt->steering[SQIDI_PSMI].group_target = select >> 1;
@@ -494,8 +496,8 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);
- xe_mmio_write32(gt, MCFG_MCR_SELECTOR, steer_val);
- xe_mmio_write32(gt, SF_MCR_SELECTOR, steer_val);
+ xe_mmio_write32(>->mmio, MCFG_MCR_SELECTOR, steer_val);
+ xe_mmio_write32(>->mmio, SF_MCR_SELECTOR, steer_val);
/*
* For GAM registers, all reads should be directed to instance 1
* (unicast reads against other instances are not allowed),
@@ -533,7 +535,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
continue;
for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) {
- if (xe_mmio_in_range(gt, >->steering[type].ranges[i], reg)) {
+ if (xe_mmio_in_range(>->mmio, >->steering[type].ranges[i], reg)) {
*group = gt->steering[type].group_target;
*instance = gt->steering[type].instance_target;
return true;
@@ -544,7 +546,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
implicit_ranges = gt->steering[IMPLICIT_STEERING].ranges;
if (implicit_ranges)
for (int i = 0; implicit_ranges[i].end > 0; i++)
- if (xe_mmio_in_range(gt, &implicit_ranges[i], reg))
+ if (xe_mmio_in_range(>->mmio, &implicit_ranges[i], reg))
return false;
/*
@@ -579,7 +581,7 @@ static void mcr_lock(struct xe_gt *gt) __acquires(>->mcr_lock)
* when a read to the relevant register returns 1.
*/
if (GRAPHICS_VERx100(xe) >= 1270)
- ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL,
+ ret = xe_mmio_wait32(>->mmio, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL,
true);
drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);
@@ -589,7 +591,7 @@ static void mcr_unlock(struct xe_gt *gt) __releases(>->mcr_lock)
{
/* Release hardware semaphore - this is done by writing 1 to the register */
if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270)
- xe_mmio_write32(gt, STEER_SEMAPHORE, 0x1);
+ xe_mmio_write32(>->mmio, STEER_SEMAPHORE, 0x1);
spin_unlock(>->mcr_lock);
}
@@ -603,6 +605,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
u8 rw_flag, int group, int instance, u32 value)
{
const struct xe_reg reg = to_xe_reg(reg_mcr);
+ struct xe_mmio *mmio = >->mmio;
struct xe_reg steer_reg;
u32 steer_val, val = 0;
@@ -635,12 +638,12 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
if (rw_flag == MCR_OP_READ)
steer_val |= MCR_MULTICAST;
- xe_mmio_write32(gt, steer_reg, steer_val);
+ xe_mmio_write32(mmio, steer_reg, steer_val);
if (rw_flag == MCR_OP_READ)
- val = xe_mmio_read32(gt, reg);
+ val = xe_mmio_read32(mmio, reg);
else
- xe_mmio_write32(gt, reg, value);
+ xe_mmio_write32(mmio, reg, value);
/*
* If we turned off the multicast bit (during a write) we're required
@@ -649,7 +652,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
* operation.
*/
if (rw_flag == MCR_OP_WRITE)
- xe_mmio_write32(gt, steer_reg, MCR_MULTICAST);
+ xe_mmio_write32(mmio, steer_reg, MCR_MULTICAST);
return val;
}
@@ -684,7 +687,7 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr reg_mcr)
group, instance, 0);
mcr_unlock(gt);
} else {
- val = xe_mmio_read32(gt, reg);
+ val = xe_mmio_read32(>->mmio, reg);
}
return val;
@@ -757,7 +760,7 @@ void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
* to touch the steering register.
*/
mcr_lock(gt);
- xe_mmio_write32(gt, reg, value);
+ xe_mmio_write32(>->mmio, reg, value);
mcr_unlock(gt);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 25/43] drm/xe/mcr: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 25/43] drm/xe/mcr: " Matt Roper
@ 2024-09-10 18:11 ` Rodrigo Vivi
2024-09-10 18:49 ` Matt Roper
0 siblings, 1 reply; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:11 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:14PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt_mcr.c | 39 ++++++++++++++++++----------------
> 1 file changed, 21 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index 7d7bd0be6233..2671ce6b1a76 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -239,11 +239,13 @@ static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
>
> static void init_steering_l3bank(struct xe_gt *gt)
> {
> + struct xe_mmio *mmio = >->mmio;
> +
> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
> u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
> - xe_mmio_read32(gt, MIRROR_FUSE3));
> + xe_mmio_read32(mmio, MIRROR_FUSE3));
> u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,
> - xe_mmio_read32(gt, XEHP_FUSE4));
> + xe_mmio_read32(mmio, XEHP_FUSE4));
>
> /*
> * Group selects mslice, instance selects bank within mslice.
> @@ -254,7 +256,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
> bank_mask & BIT(0) ? 0 : 2;
> } else if (gt_to_xe(gt)->info.platform == XE_DG2) {
> u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
> - xe_mmio_read32(gt, MIRROR_FUSE3));
> + xe_mmio_read32(mmio, MIRROR_FUSE3));
> u32 bank = __ffs(mslice_mask) * 8;
>
> /*
> @@ -266,7 +268,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
> gt->steering[L3BANK].instance_target = bank & 0x3;
> } else {
> u32 fuse = REG_FIELD_GET(L3BANK_MASK,
> - ~xe_mmio_read32(gt, MIRROR_FUSE3));
> + ~xe_mmio_read32(mmio, MIRROR_FUSE3));
>
> gt->steering[L3BANK].group_target = 0; /* unused */
> gt->steering[L3BANK].instance_target = __ffs(fuse);
> @@ -276,7 +278,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
> static void init_steering_mslice(struct xe_gt *gt)
> {
> u32 mask = REG_FIELD_GET(MEML3_EN_MASK,
> - xe_mmio_read32(gt, MIRROR_FUSE3));
> + xe_mmio_read32(>->mmio, MIRROR_FUSE3));
>
> /*
> * mslice registers are valid (not terminated) if either the meml3
> @@ -380,7 +382,7 @@ static void init_steering_oaddrm(struct xe_gt *gt)
> static void init_steering_sqidi_psmi(struct xe_gt *gt)
> {
> u32 mask = REG_FIELD_GET(XE2_NODE_ENABLE_MASK,
> - xe_mmio_read32(gt, MIRROR_FUSE3));
> + xe_mmio_read32(>->mmio, MIRROR_FUSE3));
> u32 select = __ffs(mask);
>
> gt->steering[SQIDI_PSMI].group_target = select >> 1;
> @@ -494,8 +496,8 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
> u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
> REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);
>
> - xe_mmio_write32(gt, MCFG_MCR_SELECTOR, steer_val);
> - xe_mmio_write32(gt, SF_MCR_SELECTOR, steer_val);
> + xe_mmio_write32(>->mmio, MCFG_MCR_SELECTOR, steer_val);
> + xe_mmio_write32(>->mmio, SF_MCR_SELECTOR, steer_val);
what's your threashold on the places that deserve
struct xe_mmio *mmio = >->mmio; ?
3+?
But no strong opinion on anything different. Just curiosity.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> /*
> * For GAM registers, all reads should be directed to instance 1
> * (unicast reads against other instances are not allowed),
> @@ -533,7 +535,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> continue;
>
> for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) {
> - if (xe_mmio_in_range(gt, >->steering[type].ranges[i], reg)) {
> + if (xe_mmio_in_range(>->mmio, >->steering[type].ranges[i], reg)) {
> *group = gt->steering[type].group_target;
> *instance = gt->steering[type].instance_target;
> return true;
> @@ -544,7 +546,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> implicit_ranges = gt->steering[IMPLICIT_STEERING].ranges;
> if (implicit_ranges)
> for (int i = 0; implicit_ranges[i].end > 0; i++)
> - if (xe_mmio_in_range(gt, &implicit_ranges[i], reg))
> + if (xe_mmio_in_range(>->mmio, &implicit_ranges[i], reg))
> return false;
>
> /*
> @@ -579,7 +581,7 @@ static void mcr_lock(struct xe_gt *gt) __acquires(>->mcr_lock)
> * when a read to the relevant register returns 1.
> */
> if (GRAPHICS_VERx100(xe) >= 1270)
> - ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL,
> + ret = xe_mmio_wait32(>->mmio, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL,
> true);
>
> drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);
> @@ -589,7 +591,7 @@ static void mcr_unlock(struct xe_gt *gt) __releases(>->mcr_lock)
> {
> /* Release hardware semaphore - this is done by writing 1 to the register */
> if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270)
> - xe_mmio_write32(gt, STEER_SEMAPHORE, 0x1);
> + xe_mmio_write32(>->mmio, STEER_SEMAPHORE, 0x1);
>
> spin_unlock(>->mcr_lock);
> }
> @@ -603,6 +605,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> u8 rw_flag, int group, int instance, u32 value)
> {
> const struct xe_reg reg = to_xe_reg(reg_mcr);
> + struct xe_mmio *mmio = >->mmio;
> struct xe_reg steer_reg;
> u32 steer_val, val = 0;
>
> @@ -635,12 +638,12 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> if (rw_flag == MCR_OP_READ)
> steer_val |= MCR_MULTICAST;
>
> - xe_mmio_write32(gt, steer_reg, steer_val);
> + xe_mmio_write32(mmio, steer_reg, steer_val);
>
> if (rw_flag == MCR_OP_READ)
> - val = xe_mmio_read32(gt, reg);
> + val = xe_mmio_read32(mmio, reg);
> else
> - xe_mmio_write32(gt, reg, value);
> + xe_mmio_write32(mmio, reg, value);
>
> /*
> * If we turned off the multicast bit (during a write) we're required
> @@ -649,7 +652,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> * operation.
> */
> if (rw_flag == MCR_OP_WRITE)
> - xe_mmio_write32(gt, steer_reg, MCR_MULTICAST);
> + xe_mmio_write32(mmio, steer_reg, MCR_MULTICAST);
>
> return val;
> }
> @@ -684,7 +687,7 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr reg_mcr)
> group, instance, 0);
> mcr_unlock(gt);
> } else {
> - val = xe_mmio_read32(gt, reg);
> + val = xe_mmio_read32(>->mmio, reg);
> }
>
> return val;
> @@ -757,7 +760,7 @@ void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> * to touch the steering register.
> */
> mcr_lock(gt);
> - xe_mmio_write32(gt, reg, value);
> + xe_mmio_write32(>->mmio, reg, value);
> mcr_unlock(gt);
> }
>
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: [PATCH v2 25/43] drm/xe/mcr: Convert register access to use xe_mmio
2024-09-10 18:11 ` Rodrigo Vivi
@ 2024-09-10 18:49 ` Matt Roper
0 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-10 18:49 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe
On Tue, Sep 10, 2024 at 02:11:04PM -0400, Rodrigo Vivi wrote:
> On Fri, Sep 06, 2024 at 05:08:14PM -0700, Matt Roper wrote:
> > Stop using GT pointers for register access.
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_gt_mcr.c | 39 ++++++++++++++++++----------------
> > 1 file changed, 21 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> > index 7d7bd0be6233..2671ce6b1a76 100644
> > --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> > +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> > @@ -239,11 +239,13 @@ static const struct xe_mmio_range xe2lpm_instance0_steering_table[] = {
> >
> > static void init_steering_l3bank(struct xe_gt *gt)
> > {
> > + struct xe_mmio *mmio = >->mmio;
> > +
> > if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
> > u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
> > - xe_mmio_read32(gt, MIRROR_FUSE3));
> > + xe_mmio_read32(mmio, MIRROR_FUSE3));
> > u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,
> > - xe_mmio_read32(gt, XEHP_FUSE4));
> > + xe_mmio_read32(mmio, XEHP_FUSE4));
> >
> > /*
> > * Group selects mslice, instance selects bank within mslice.
> > @@ -254,7 +256,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
> > bank_mask & BIT(0) ? 0 : 2;
> > } else if (gt_to_xe(gt)->info.platform == XE_DG2) {
> > u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
> > - xe_mmio_read32(gt, MIRROR_FUSE3));
> > + xe_mmio_read32(mmio, MIRROR_FUSE3));
> > u32 bank = __ffs(mslice_mask) * 8;
> >
> > /*
> > @@ -266,7 +268,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
> > gt->steering[L3BANK].instance_target = bank & 0x3;
> > } else {
> > u32 fuse = REG_FIELD_GET(L3BANK_MASK,
> > - ~xe_mmio_read32(gt, MIRROR_FUSE3));
> > + ~xe_mmio_read32(mmio, MIRROR_FUSE3));
> >
> > gt->steering[L3BANK].group_target = 0; /* unused */
> > gt->steering[L3BANK].instance_target = __ffs(fuse);
> > @@ -276,7 +278,7 @@ static void init_steering_l3bank(struct xe_gt *gt)
> > static void init_steering_mslice(struct xe_gt *gt)
> > {
> > u32 mask = REG_FIELD_GET(MEML3_EN_MASK,
> > - xe_mmio_read32(gt, MIRROR_FUSE3));
> > + xe_mmio_read32(>->mmio, MIRROR_FUSE3));
> >
> > /*
> > * mslice registers are valid (not terminated) if either the meml3
> > @@ -380,7 +382,7 @@ static void init_steering_oaddrm(struct xe_gt *gt)
> > static void init_steering_sqidi_psmi(struct xe_gt *gt)
> > {
> > u32 mask = REG_FIELD_GET(XE2_NODE_ENABLE_MASK,
> > - xe_mmio_read32(gt, MIRROR_FUSE3));
> > + xe_mmio_read32(>->mmio, MIRROR_FUSE3));
> > u32 select = __ffs(mask);
> >
> > gt->steering[SQIDI_PSMI].group_target = select >> 1;
> > @@ -494,8 +496,8 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
> > u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
> > REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);
> >
> > - xe_mmio_write32(gt, MCFG_MCR_SELECTOR, steer_val);
> > - xe_mmio_write32(gt, SF_MCR_SELECTOR, steer_val);
> > + xe_mmio_write32(>->mmio, MCFG_MCR_SELECTOR, steer_val);
> > + xe_mmio_write32(>->mmio, SF_MCR_SELECTOR, steer_val);
>
> what's your threashold on the places that deserve
> struct xe_mmio *mmio = >->mmio; ?
>
> 3+?
>
> But no strong opinion on anything different. Just curiosity.
Yeah, if there were only 1/2 places to update in a function I accessed
the gt's mmio pointer directly, whereas if there were three or more I
made a dedicated local variable.
Matt
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> > /*
> > * For GAM registers, all reads should be directed to instance 1
> > * (unicast reads against other instances are not allowed),
> > @@ -533,7 +535,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> > continue;
> >
> > for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) {
> > - if (xe_mmio_in_range(gt, >->steering[type].ranges[i], reg)) {
> > + if (xe_mmio_in_range(>->mmio, >->steering[type].ranges[i], reg)) {
> > *group = gt->steering[type].group_target;
> > *instance = gt->steering[type].instance_target;
> > return true;
> > @@ -544,7 +546,7 @@ static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
> > implicit_ranges = gt->steering[IMPLICIT_STEERING].ranges;
> > if (implicit_ranges)
> > for (int i = 0; implicit_ranges[i].end > 0; i++)
> > - if (xe_mmio_in_range(gt, &implicit_ranges[i], reg))
> > + if (xe_mmio_in_range(>->mmio, &implicit_ranges[i], reg))
> > return false;
> >
> > /*
> > @@ -579,7 +581,7 @@ static void mcr_lock(struct xe_gt *gt) __acquires(>->mcr_lock)
> > * when a read to the relevant register returns 1.
> > */
> > if (GRAPHICS_VERx100(xe) >= 1270)
> > - ret = xe_mmio_wait32(gt, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL,
> > + ret = xe_mmio_wait32(>->mmio, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL,
> > true);
> >
> > drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);
> > @@ -589,7 +591,7 @@ static void mcr_unlock(struct xe_gt *gt) __releases(>->mcr_lock)
> > {
> > /* Release hardware semaphore - this is done by writing 1 to the register */
> > if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270)
> > - xe_mmio_write32(gt, STEER_SEMAPHORE, 0x1);
> > + xe_mmio_write32(>->mmio, STEER_SEMAPHORE, 0x1);
> >
> > spin_unlock(>->mcr_lock);
> > }
> > @@ -603,6 +605,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> > u8 rw_flag, int group, int instance, u32 value)
> > {
> > const struct xe_reg reg = to_xe_reg(reg_mcr);
> > + struct xe_mmio *mmio = >->mmio;
> > struct xe_reg steer_reg;
> > u32 steer_val, val = 0;
> >
> > @@ -635,12 +638,12 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> > if (rw_flag == MCR_OP_READ)
> > steer_val |= MCR_MULTICAST;
> >
> > - xe_mmio_write32(gt, steer_reg, steer_val);
> > + xe_mmio_write32(mmio, steer_reg, steer_val);
> >
> > if (rw_flag == MCR_OP_READ)
> > - val = xe_mmio_read32(gt, reg);
> > + val = xe_mmio_read32(mmio, reg);
> > else
> > - xe_mmio_write32(gt, reg, value);
> > + xe_mmio_write32(mmio, reg, value);
> >
> > /*
> > * If we turned off the multicast bit (during a write) we're required
> > @@ -649,7 +652,7 @@ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> > * operation.
> > */
> > if (rw_flag == MCR_OP_WRITE)
> > - xe_mmio_write32(gt, steer_reg, MCR_MULTICAST);
> > + xe_mmio_write32(mmio, steer_reg, MCR_MULTICAST);
> >
> > return val;
> > }
> > @@ -684,7 +687,7 @@ u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr reg_mcr)
> > group, instance, 0);
> > mcr_unlock(gt);
> > } else {
> > - val = xe_mmio_read32(gt, reg);
> > + val = xe_mmio_read32(>->mmio, reg);
> > }
> >
> > return val;
> > @@ -757,7 +760,7 @@ void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
> > * to touch the steering register.
> > */
> > mcr_lock(gt);
> > - xe_mmio_write32(gt, reg, value);
> > + xe_mmio_write32(>->mmio, reg, value);
> > mcr_unlock(gt);
> > }
> >
> > --
> > 2.45.2
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 26/43] drm/xe/mocs: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (24 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 25/43] drm/xe/mcr: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:41 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 27/43] drm/xe/hw_engine: " Matt Roper
` (24 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/tests/xe_mocs.c | 4 ++--
drivers/gpu/drm/xe/xe_mocs.c | 16 ++++++++--------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/xe/tests/xe_mocs.c b/drivers/gpu/drm/xe/tests/xe_mocs.c
index 79be73b4a02b..ea932c051cc7 100644
--- a/drivers/gpu/drm/xe/tests/xe_mocs.c
+++ b/drivers/gpu/drm/xe/tests/xe_mocs.c
@@ -55,7 +55,7 @@ static void read_l3cc_table(struct xe_gt *gt,
if (regs_are_mcr(gt))
reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i >> 1));
else
- reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i >> 1));
+ reg_val = xe_mmio_read32(>->mmio, XELP_LNCFCMOCS(i >> 1));
mocs_dbg(gt, "reg_val=0x%x\n", reg_val);
} else {
@@ -94,7 +94,7 @@ static void read_mocs_table(struct xe_gt *gt,
if (regs_are_mcr(gt))
reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
else
- reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
+ reg_val = xe_mmio_read32(>->mmio, XELP_GLOBAL_MOCS(i));
mocs_expected = get_entry_control(info, i);
mocs = reg_val;
diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index 7ff0ac5b799a..8df41cd12d51 100644
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -278,7 +278,7 @@ static void xelp_lncf_dump(struct xe_mocs_info *info, struct xe_gt *gt, struct d
if (regs_are_mcr(gt))
reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
else
- reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
+ reg_val = xe_mmio_read32(>->mmio, XELP_LNCFCMOCS(i));
drm_printf(p, "LNCFCMOCS[%2d] = [%u, %u, %u] (%#8x)\n",
j++,
@@ -310,7 +310,7 @@ static void xelp_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
if (regs_are_mcr(gt))
reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
else
- reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
+ reg_val = xe_mmio_read32(>->mmio, XELP_GLOBAL_MOCS(i));
drm_printf(p, "GLOB_MOCS[%2d] = [%u, %u, %u, %u, %u, %u, %u, %u, %u, %u ] (%#8x)\n",
i,
@@ -383,7 +383,7 @@ static void xehp_lncf_dump(struct xe_mocs_info *info, unsigned int flags,
if (regs_are_mcr(gt))
reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
else
- reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
+ reg_val = xe_mmio_read32(>->mmio, XELP_LNCFCMOCS(i));
drm_printf(p, "LNCFCMOCS[%2d] = [%u, %u, %u] (%#8x)\n",
j++,
@@ -428,7 +428,7 @@ static void pvc_mocs_dump(struct xe_mocs_info *info, unsigned int flags, struct
if (regs_are_mcr(gt))
reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
else
- reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
+ reg_val = xe_mmio_read32(>->mmio, XELP_LNCFCMOCS(i));
drm_printf(p, "LNCFCMOCS[%2d] = [ %u ] (%#8x)\n",
j++,
@@ -510,7 +510,7 @@ static void mtl_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
if (regs_are_mcr(gt))
reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
else
- reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
+ reg_val = xe_mmio_read32(>->mmio, XELP_GLOBAL_MOCS(i));
drm_printf(p, "GLOB_MOCS[%2d] = [%u, %u] (%#8x)\n",
i,
@@ -553,7 +553,7 @@ static void xe2_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
if (regs_are_mcr(gt))
reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
else
- reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
+ reg_val = xe_mmio_read32(>->mmio, XELP_GLOBAL_MOCS(i));
drm_printf(p, "GLOB_MOCS[%2d] = [%u, %u, %u] (%#8x)\n",
i,
@@ -690,7 +690,7 @@ static void __init_mocs_table(struct xe_gt *gt,
if (regs_are_mcr(gt))
xe_gt_mcr_multicast_write(gt, XEHP_GLOBAL_MOCS(i), mocs);
else
- xe_mmio_write32(gt, XELP_GLOBAL_MOCS(i), mocs);
+ xe_mmio_write32(>->mmio, XELP_GLOBAL_MOCS(i), mocs);
}
}
@@ -730,7 +730,7 @@ static void init_l3cc_table(struct xe_gt *gt,
if (regs_are_mcr(gt))
xe_gt_mcr_multicast_write(gt, XEHP_LNCFCMOCS(i), l3cc);
else
- xe_mmio_write32(gt, XELP_LNCFCMOCS(i), l3cc);
+ xe_mmio_write32(>->mmio, XELP_LNCFCMOCS(i), l3cc);
}
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 26/43] drm/xe/mocs: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 26/43] drm/xe/mocs: " Matt Roper
@ 2024-09-10 18:41 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:41 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:15PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/tests/xe_mocs.c | 4 ++--
> drivers/gpu/drm/xe/xe_mocs.c | 16 ++++++++--------
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/tests/xe_mocs.c b/drivers/gpu/drm/xe/tests/xe_mocs.c
> index 79be73b4a02b..ea932c051cc7 100644
> --- a/drivers/gpu/drm/xe/tests/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/tests/xe_mocs.c
> @@ -55,7 +55,7 @@ static void read_l3cc_table(struct xe_gt *gt,
> if (regs_are_mcr(gt))
> reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i >> 1));
> else
> - reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i >> 1));
> + reg_val = xe_mmio_read32(>->mmio, XELP_LNCFCMOCS(i >> 1));
>
> mocs_dbg(gt, "reg_val=0x%x\n", reg_val);
> } else {
> @@ -94,7 +94,7 @@ static void read_mocs_table(struct xe_gt *gt,
> if (regs_are_mcr(gt))
> reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
> else
> - reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
> + reg_val = xe_mmio_read32(>->mmio, XELP_GLOBAL_MOCS(i));
>
> mocs_expected = get_entry_control(info, i);
> mocs = reg_val;
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index 7ff0ac5b799a..8df41cd12d51 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -278,7 +278,7 @@ static void xelp_lncf_dump(struct xe_mocs_info *info, struct xe_gt *gt, struct d
> if (regs_are_mcr(gt))
> reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
> else
> - reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
> + reg_val = xe_mmio_read32(>->mmio, XELP_LNCFCMOCS(i));
>
> drm_printf(p, "LNCFCMOCS[%2d] = [%u, %u, %u] (%#8x)\n",
> j++,
> @@ -310,7 +310,7 @@ static void xelp_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
> if (regs_are_mcr(gt))
> reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
> else
> - reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
> + reg_val = xe_mmio_read32(>->mmio, XELP_GLOBAL_MOCS(i));
>
> drm_printf(p, "GLOB_MOCS[%2d] = [%u, %u, %u, %u, %u, %u, %u, %u, %u, %u ] (%#8x)\n",
> i,
> @@ -383,7 +383,7 @@ static void xehp_lncf_dump(struct xe_mocs_info *info, unsigned int flags,
> if (regs_are_mcr(gt))
> reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
> else
> - reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
> + reg_val = xe_mmio_read32(>->mmio, XELP_LNCFCMOCS(i));
>
> drm_printf(p, "LNCFCMOCS[%2d] = [%u, %u, %u] (%#8x)\n",
> j++,
> @@ -428,7 +428,7 @@ static void pvc_mocs_dump(struct xe_mocs_info *info, unsigned int flags, struct
> if (regs_are_mcr(gt))
> reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
> else
> - reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
> + reg_val = xe_mmio_read32(>->mmio, XELP_LNCFCMOCS(i));
>
> drm_printf(p, "LNCFCMOCS[%2d] = [ %u ] (%#8x)\n",
> j++,
> @@ -510,7 +510,7 @@ static void mtl_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
> if (regs_are_mcr(gt))
> reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
> else
> - reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
> + reg_val = xe_mmio_read32(>->mmio, XELP_GLOBAL_MOCS(i));
>
> drm_printf(p, "GLOB_MOCS[%2d] = [%u, %u] (%#8x)\n",
> i,
> @@ -553,7 +553,7 @@ static void xe2_mocs_dump(struct xe_mocs_info *info, unsigned int flags,
> if (regs_are_mcr(gt))
> reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
> else
> - reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
> + reg_val = xe_mmio_read32(>->mmio, XELP_GLOBAL_MOCS(i));
>
> drm_printf(p, "GLOB_MOCS[%2d] = [%u, %u, %u] (%#8x)\n",
> i,
> @@ -690,7 +690,7 @@ static void __init_mocs_table(struct xe_gt *gt,
> if (regs_are_mcr(gt))
> xe_gt_mcr_multicast_write(gt, XEHP_GLOBAL_MOCS(i), mocs);
> else
> - xe_mmio_write32(gt, XELP_GLOBAL_MOCS(i), mocs);
> + xe_mmio_write32(>->mmio, XELP_GLOBAL_MOCS(i), mocs);
> }
> }
>
> @@ -730,7 +730,7 @@ static void init_l3cc_table(struct xe_gt *gt,
> if (regs_are_mcr(gt))
> xe_gt_mcr_multicast_write(gt, XEHP_LNCFCMOCS(i), l3cc);
> else
> - xe_mmio_write32(gt, XELP_LNCFCMOCS(i), l3cc);
> + xe_mmio_write32(>->mmio, XELP_LNCFCMOCS(i), l3cc);
> }
> }
>
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 27/43] drm/xe/hw_engine: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (25 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 26/43] drm/xe/mocs: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:42 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 28/43] drm/xe/gt_throttle: " Matt Roper
` (23 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_hw_engine.c | 29 +++++++++++++++--------------
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index c9c3beb3ce8d..0788c2347c84 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -295,7 +295,7 @@ void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe,
reg.addr += hwe->mmio_base;
- xe_mmio_write32(hwe->gt, reg, val);
+ xe_mmio_write32(&hwe->gt->mmio, reg, val);
}
/**
@@ -315,7 +315,7 @@ u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
reg.addr += hwe->mmio_base;
- return xe_mmio_read32(hwe->gt, reg);
+ return xe_mmio_read32(&hwe->gt->mmio, reg);
}
void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
@@ -324,7 +324,7 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
- xe_mmio_write32(hwe->gt, RCU_MODE,
+ xe_mmio_write32(&hwe->gt->mmio, RCU_MODE,
_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
xe_hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);
@@ -354,7 +354,7 @@ static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_gt *gt,
hwe->class != XE_ENGINE_CLASS_RENDER)
return false;
- return xe_mmio_read32(hwe->gt, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
+ return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
}
void
@@ -612,7 +612,7 @@ static void read_media_fuses(struct xe_gt *gt)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE);
+ media_fuse = xe_mmio_read32(>->mmio, GT_VEBOX_VDBOX_DISABLE);
/*
* Pre-Xe_HP platforms had register bits representing absent engines,
@@ -657,7 +657,7 @@ static void read_copy_fuses(struct xe_gt *gt)
xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
- bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3);
+ bcs_mask = xe_mmio_read32(>->mmio, MIRROR_FUSE3);
bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
/* BCS0 is always present; only BCS1-BCS8 may be fused off */
@@ -704,7 +704,7 @@ static void read_compute_fuses_from_reg(struct xe_gt *gt)
struct xe_device *xe = gt_to_xe(gt);
u32 ccs_mask;
- ccs_mask = xe_mmio_read32(gt, XEHP_FUSE4);
+ ccs_mask = xe_mmio_read32(>->mmio, XEHP_FUSE4);
ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask);
for (int i = XE_HW_ENGINE_CCS0, j = 0; i <= XE_HW_ENGINE_CCS3; ++i, ++j) {
@@ -742,8 +742,8 @@ static void check_gsc_availability(struct xe_gt *gt)
gt->info.engine_mask &= ~BIT(XE_HW_ENGINE_GSCCS0);
/* interrupts where previously enabled, so turn them off */
- xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, 0);
- xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~0);
+ xe_mmio_write32(>->mmio, GUNIT_GSC_INTR_ENABLE, 0);
+ xe_mmio_write32(>->mmio, GUNIT_GSC_INTR_MASK, ~0);
drm_info(&xe->drm, "gsccs disabled due to lack of FW\n");
}
@@ -809,6 +809,7 @@ xe_hw_engine_snapshot_instdone_capture(struct xe_hw_engine *hwe,
struct xe_hw_engine_snapshot *snapshot)
{
struct xe_gt *gt = hwe->gt;
+ struct xe_mmio *mmio = >->mmio;
struct xe_device *xe = gt_to_xe(gt);
unsigned int dss;
u16 group, instance;
@@ -820,11 +821,11 @@ xe_hw_engine_snapshot_instdone_capture(struct xe_hw_engine *hwe,
if (is_slice_common_per_gslice(xe) == false) {
snapshot->reg.instdone.slice_common[0] =
- xe_mmio_read32(gt, SC_INSTDONE);
+ xe_mmio_read32(mmio, SC_INSTDONE);
snapshot->reg.instdone.slice_common_extra[0] =
- xe_mmio_read32(gt, SC_INSTDONE_EXTRA);
+ xe_mmio_read32(mmio, SC_INSTDONE_EXTRA);
snapshot->reg.instdone.slice_common_extra2[0] =
- xe_mmio_read32(gt, SC_INSTDONE_EXTRA2);
+ xe_mmio_read32(mmio, SC_INSTDONE_EXTRA2);
} else {
for_each_geometry_dss(dss, gt, group, instance) {
snapshot->reg.instdone.slice_common[dss] =
@@ -959,7 +960,7 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)
xe_hw_engine_snapshot_instdone_capture(hwe, snapshot);
if (snapshot->hwe->class == XE_ENGINE_CLASS_COMPUTE)
- snapshot->reg.rcu_mode = xe_mmio_read32(hwe->gt, RCU_MODE);
+ snapshot->reg.rcu_mode = xe_mmio_read32(&hwe->gt->mmio, RCU_MODE);
return snapshot;
}
@@ -1150,7 +1151,7 @@ const char *xe_hw_engine_class_to_str(enum xe_engine_class class)
u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe)
{
- return xe_mmio_read64_2x32(hwe->gt, RING_TIMESTAMP(hwe->mmio_base));
+ return xe_mmio_read64_2x32(&hwe->gt->mmio, RING_TIMESTAMP(hwe->mmio_base));
}
enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe)
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 27/43] drm/xe/hw_engine: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 27/43] drm/xe/hw_engine: " Matt Roper
@ 2024-09-10 18:42 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:42 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:16PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_hw_engine.c | 29 +++++++++++++++--------------
> 1 file changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index c9c3beb3ce8d..0788c2347c84 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -295,7 +295,7 @@ void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe,
>
> reg.addr += hwe->mmio_base;
>
> - xe_mmio_write32(hwe->gt, reg, val);
> + xe_mmio_write32(&hwe->gt->mmio, reg, val);
> }
>
> /**
> @@ -315,7 +315,7 @@ u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
>
> reg.addr += hwe->mmio_base;
>
> - return xe_mmio_read32(hwe->gt, reg);
> + return xe_mmio_read32(&hwe->gt->mmio, reg);
> }
>
> void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
> @@ -324,7 +324,7 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
> xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
>
> if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
> - xe_mmio_write32(hwe->gt, RCU_MODE,
> + xe_mmio_write32(&hwe->gt->mmio, RCU_MODE,
> _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
>
> xe_hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);
> @@ -354,7 +354,7 @@ static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_gt *gt,
> hwe->class != XE_ENGINE_CLASS_RENDER)
> return false;
>
> - return xe_mmio_read32(hwe->gt, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
> + return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE;
> }
>
> void
> @@ -612,7 +612,7 @@ static void read_media_fuses(struct xe_gt *gt)
>
> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>
> - media_fuse = xe_mmio_read32(gt, GT_VEBOX_VDBOX_DISABLE);
> + media_fuse = xe_mmio_read32(>->mmio, GT_VEBOX_VDBOX_DISABLE);
>
> /*
> * Pre-Xe_HP platforms had register bits representing absent engines,
> @@ -657,7 +657,7 @@ static void read_copy_fuses(struct xe_gt *gt)
>
> xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
>
> - bcs_mask = xe_mmio_read32(gt, MIRROR_FUSE3);
> + bcs_mask = xe_mmio_read32(>->mmio, MIRROR_FUSE3);
> bcs_mask = REG_FIELD_GET(MEML3_EN_MASK, bcs_mask);
>
> /* BCS0 is always present; only BCS1-BCS8 may be fused off */
> @@ -704,7 +704,7 @@ static void read_compute_fuses_from_reg(struct xe_gt *gt)
> struct xe_device *xe = gt_to_xe(gt);
> u32 ccs_mask;
>
> - ccs_mask = xe_mmio_read32(gt, XEHP_FUSE4);
> + ccs_mask = xe_mmio_read32(>->mmio, XEHP_FUSE4);
> ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask);
>
> for (int i = XE_HW_ENGINE_CCS0, j = 0; i <= XE_HW_ENGINE_CCS3; ++i, ++j) {
> @@ -742,8 +742,8 @@ static void check_gsc_availability(struct xe_gt *gt)
> gt->info.engine_mask &= ~BIT(XE_HW_ENGINE_GSCCS0);
>
> /* interrupts where previously enabled, so turn them off */
> - xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, 0);
> - xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~0);
> + xe_mmio_write32(>->mmio, GUNIT_GSC_INTR_ENABLE, 0);
> + xe_mmio_write32(>->mmio, GUNIT_GSC_INTR_MASK, ~0);
>
> drm_info(&xe->drm, "gsccs disabled due to lack of FW\n");
> }
> @@ -809,6 +809,7 @@ xe_hw_engine_snapshot_instdone_capture(struct xe_hw_engine *hwe,
> struct xe_hw_engine_snapshot *snapshot)
> {
> struct xe_gt *gt = hwe->gt;
> + struct xe_mmio *mmio = >->mmio;
> struct xe_device *xe = gt_to_xe(gt);
> unsigned int dss;
> u16 group, instance;
> @@ -820,11 +821,11 @@ xe_hw_engine_snapshot_instdone_capture(struct xe_hw_engine *hwe,
>
> if (is_slice_common_per_gslice(xe) == false) {
> snapshot->reg.instdone.slice_common[0] =
> - xe_mmio_read32(gt, SC_INSTDONE);
> + xe_mmio_read32(mmio, SC_INSTDONE);
> snapshot->reg.instdone.slice_common_extra[0] =
> - xe_mmio_read32(gt, SC_INSTDONE_EXTRA);
> + xe_mmio_read32(mmio, SC_INSTDONE_EXTRA);
> snapshot->reg.instdone.slice_common_extra2[0] =
> - xe_mmio_read32(gt, SC_INSTDONE_EXTRA2);
> + xe_mmio_read32(mmio, SC_INSTDONE_EXTRA2);
> } else {
> for_each_geometry_dss(dss, gt, group, instance) {
> snapshot->reg.instdone.slice_common[dss] =
> @@ -959,7 +960,7 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)
> xe_hw_engine_snapshot_instdone_capture(hwe, snapshot);
>
> if (snapshot->hwe->class == XE_ENGINE_CLASS_COMPUTE)
> - snapshot->reg.rcu_mode = xe_mmio_read32(hwe->gt, RCU_MODE);
> + snapshot->reg.rcu_mode = xe_mmio_read32(&hwe->gt->mmio, RCU_MODE);
>
> return snapshot;
> }
> @@ -1150,7 +1151,7 @@ const char *xe_hw_engine_class_to_str(enum xe_engine_class class)
>
> u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe)
> {
> - return xe_mmio_read64_2x32(hwe->gt, RING_TIMESTAMP(hwe->mmio_base));
> + return xe_mmio_read64_2x32(&hwe->gt->mmio, RING_TIMESTAMP(hwe->mmio_base));
> }
>
> enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe)
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 28/43] drm/xe/gt_throttle: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (26 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 27/43] drm/xe/hw_engine: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:07 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 29/43] drm/xe/pat: " Matt Roper
` (22 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt_throttle.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_throttle.c b/drivers/gpu/drm/xe/xe_gt_throttle.c
index 25963e33a383..03b225364101 100644
--- a/drivers/gpu/drm/xe/xe_gt_throttle.c
+++ b/drivers/gpu/drm/xe/xe_gt_throttle.c
@@ -41,9 +41,9 @@ u32 xe_gt_throttle_get_limit_reasons(struct xe_gt *gt)
xe_pm_runtime_get(gt_to_xe(gt));
if (xe_gt_is_media_type(gt))
- reg = xe_mmio_read32(gt, MTL_MEDIA_PERF_LIMIT_REASONS);
+ reg = xe_mmio_read32(>->mmio, MTL_MEDIA_PERF_LIMIT_REASONS);
else
- reg = xe_mmio_read32(gt, GT0_PERF_LIMIT_REASONS);
+ reg = xe_mmio_read32(>->mmio, GT0_PERF_LIMIT_REASONS);
xe_pm_runtime_put(gt_to_xe(gt));
return reg;
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 28/43] drm/xe/gt_throttle: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 28/43] drm/xe/gt_throttle: " Matt Roper
@ 2024-09-10 18:07 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:07 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:17PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt_throttle.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_throttle.c b/drivers/gpu/drm/xe/xe_gt_throttle.c
> index 25963e33a383..03b225364101 100644
> --- a/drivers/gpu/drm/xe/xe_gt_throttle.c
> +++ b/drivers/gpu/drm/xe/xe_gt_throttle.c
> @@ -41,9 +41,9 @@ u32 xe_gt_throttle_get_limit_reasons(struct xe_gt *gt)
>
> xe_pm_runtime_get(gt_to_xe(gt));
> if (xe_gt_is_media_type(gt))
> - reg = xe_mmio_read32(gt, MTL_MEDIA_PERF_LIMIT_REASONS);
> + reg = xe_mmio_read32(>->mmio, MTL_MEDIA_PERF_LIMIT_REASONS);
> else
> - reg = xe_mmio_read32(gt, GT0_PERF_LIMIT_REASONS);
> + reg = xe_mmio_read32(>->mmio, GT0_PERF_LIMIT_REASONS);
> xe_pm_runtime_put(gt_to_xe(gt));
>
> return reg;
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 29/43] drm/xe/pat: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (27 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 28/43] drm/xe/gt_throttle: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:12 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 30/43] drm/xe/wopcm: " Matt Roper
` (21 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_pat.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 5bf48e99c939..6bd6adfdfc74 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -165,7 +165,7 @@ static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[
for (int i = 0; i < n_entries; i++) {
struct xe_reg reg = XE_REG(_PAT_INDEX(i));
- xe_mmio_write32(gt, reg, table[i].value);
+ xe_mmio_write32(>->mmio, reg, table[i].value);
}
}
@@ -191,7 +191,7 @@ static void xelp_dump(struct xe_gt *gt, struct drm_printer *p)
drm_printf(p, "PAT table:\n");
for (i = 0; i < xe->pat.n_entries; i++) {
- u32 pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i)));
+ u32 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i)));
u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat);
drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i,
@@ -283,7 +283,7 @@ static void xelpg_dump(struct xe_gt *gt, struct drm_printer *p)
u32 pat;
if (xe_gt_is_media_type(gt))
- pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i)));
+ pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i)));
else
pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
@@ -321,10 +321,10 @@ static void xe2lpm_program_pat(struct xe_gt *gt, const struct xe_pat_table_entry
int n_entries)
{
program_pat(gt, table, n_entries);
- xe_mmio_write32(gt, XE_REG(_PAT_ATS), xe2_pat_ats.value);
+ xe_mmio_write32(>->mmio, XE_REG(_PAT_ATS), xe2_pat_ats.value);
if (IS_DGFX(gt_to_xe(gt)))
- xe_mmio_write32(gt, XE_REG(_PAT_PTA), xe2_pat_pta.value);
+ xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe2_pat_pta.value);
}
static void xe2_dump(struct xe_gt *gt, struct drm_printer *p)
@@ -341,7 +341,7 @@ static void xe2_dump(struct xe_gt *gt, struct drm_printer *p)
for (i = 0; i < xe->pat.n_entries; i++) {
if (xe_gt_is_media_type(gt))
- pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i)));
+ pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i)));
else
pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
@@ -360,7 +360,7 @@ static void xe2_dump(struct xe_gt *gt, struct drm_printer *p)
* PPGTT entries.
*/
if (xe_gt_is_media_type(gt))
- pat = xe_mmio_read32(gt, XE_REG(_PAT_PTA));
+ pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_PTA));
else
pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 29/43] drm/xe/pat: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 29/43] drm/xe/pat: " Matt Roper
@ 2024-09-10 18:12 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:12 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:18PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_pat.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 5bf48e99c939..6bd6adfdfc74 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -165,7 +165,7 @@ static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[
> for (int i = 0; i < n_entries; i++) {
> struct xe_reg reg = XE_REG(_PAT_INDEX(i));
>
> - xe_mmio_write32(gt, reg, table[i].value);
> + xe_mmio_write32(>->mmio, reg, table[i].value);
> }
> }
>
> @@ -191,7 +191,7 @@ static void xelp_dump(struct xe_gt *gt, struct drm_printer *p)
> drm_printf(p, "PAT table:\n");
>
> for (i = 0; i < xe->pat.n_entries; i++) {
> - u32 pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i)));
> + u32 pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i)));
> u8 mem_type = REG_FIELD_GET(XELP_MEM_TYPE_MASK, pat);
>
> drm_printf(p, "PAT[%2d] = %s (%#8x)\n", i,
> @@ -283,7 +283,7 @@ static void xelpg_dump(struct xe_gt *gt, struct drm_printer *p)
> u32 pat;
>
> if (xe_gt_is_media_type(gt))
> - pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i)));
> + pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i)));
> else
> pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
>
> @@ -321,10 +321,10 @@ static void xe2lpm_program_pat(struct xe_gt *gt, const struct xe_pat_table_entry
> int n_entries)
> {
> program_pat(gt, table, n_entries);
> - xe_mmio_write32(gt, XE_REG(_PAT_ATS), xe2_pat_ats.value);
> + xe_mmio_write32(>->mmio, XE_REG(_PAT_ATS), xe2_pat_ats.value);
>
> if (IS_DGFX(gt_to_xe(gt)))
> - xe_mmio_write32(gt, XE_REG(_PAT_PTA), xe2_pat_pta.value);
> + xe_mmio_write32(>->mmio, XE_REG(_PAT_PTA), xe2_pat_pta.value);
> }
>
> static void xe2_dump(struct xe_gt *gt, struct drm_printer *p)
> @@ -341,7 +341,7 @@ static void xe2_dump(struct xe_gt *gt, struct drm_printer *p)
>
> for (i = 0; i < xe->pat.n_entries; i++) {
> if (xe_gt_is_media_type(gt))
> - pat = xe_mmio_read32(gt, XE_REG(_PAT_INDEX(i)));
> + pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_INDEX(i)));
> else
> pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_INDEX(i)));
>
> @@ -360,7 +360,7 @@ static void xe2_dump(struct xe_gt *gt, struct drm_printer *p)
> * PPGTT entries.
> */
> if (xe_gt_is_media_type(gt))
> - pat = xe_mmio_read32(gt, XE_REG(_PAT_PTA));
> + pat = xe_mmio_read32(>->mmio, XE_REG(_PAT_PTA));
> else
> pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_PTA));
>
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 30/43] drm/xe/wopcm: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (28 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 29/43] drm/xe/pat: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:12 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 31/43] drm/xe/oa: " Matt Roper
` (20 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_wopcm.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
index d3a99157e523..93c82825d896 100644
--- a/drivers/gpu/drm/xe/xe_wopcm.c
+++ b/drivers/gpu/drm/xe/xe_wopcm.c
@@ -123,8 +123,8 @@ static bool __check_layout(struct xe_device *xe, u32 wopcm_size,
static bool __wopcm_regs_locked(struct xe_gt *gt,
u32 *guc_wopcm_base, u32 *guc_wopcm_size)
{
- u32 reg_base = xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET);
- u32 reg_size = xe_mmio_read32(gt, GUC_WOPCM_SIZE);
+ u32 reg_base = xe_mmio_read32(>->mmio, DMA_GUC_WOPCM_OFFSET);
+ u32 reg_size = xe_mmio_read32(>->mmio, GUC_WOPCM_SIZE);
if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) ||
!(reg_base & GUC_WOPCM_OFFSET_VALID))
@@ -150,13 +150,13 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
XE_WARN_ON(size & ~GUC_WOPCM_SIZE_MASK);
mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
- err = xe_mmio_write32_and_verify(gt, GUC_WOPCM_SIZE, size, mask,
+ err = xe_mmio_write32_and_verify(>->mmio, GUC_WOPCM_SIZE, size, mask,
size | GUC_WOPCM_SIZE_LOCKED);
if (err)
goto err_out;
mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
- err = xe_mmio_write32_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
+ err = xe_mmio_write32_and_verify(>->mmio, DMA_GUC_WOPCM_OFFSET,
base | huc_agent, mask,
base | huc_agent |
GUC_WOPCM_OFFSET_VALID);
@@ -169,10 +169,10 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
drm_notice(&xe->drm, "Failed to init uC WOPCM registers!\n");
drm_notice(&xe->drm, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
DMA_GUC_WOPCM_OFFSET.addr,
- xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET));
+ xe_mmio_read32(>->mmio, DMA_GUC_WOPCM_OFFSET));
drm_notice(&xe->drm, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
GUC_WOPCM_SIZE.addr,
- xe_mmio_read32(gt, GUC_WOPCM_SIZE));
+ xe_mmio_read32(>->mmio, GUC_WOPCM_SIZE));
return err;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 30/43] drm/xe/wopcm: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 30/43] drm/xe/wopcm: " Matt Roper
@ 2024-09-10 18:12 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:12 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:19PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_wopcm.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_wopcm.c b/drivers/gpu/drm/xe/xe_wopcm.c
> index d3a99157e523..93c82825d896 100644
> --- a/drivers/gpu/drm/xe/xe_wopcm.c
> +++ b/drivers/gpu/drm/xe/xe_wopcm.c
> @@ -123,8 +123,8 @@ static bool __check_layout(struct xe_device *xe, u32 wopcm_size,
> static bool __wopcm_regs_locked(struct xe_gt *gt,
> u32 *guc_wopcm_base, u32 *guc_wopcm_size)
> {
> - u32 reg_base = xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET);
> - u32 reg_size = xe_mmio_read32(gt, GUC_WOPCM_SIZE);
> + u32 reg_base = xe_mmio_read32(>->mmio, DMA_GUC_WOPCM_OFFSET);
> + u32 reg_size = xe_mmio_read32(>->mmio, GUC_WOPCM_SIZE);
>
> if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) ||
> !(reg_base & GUC_WOPCM_OFFSET_VALID))
> @@ -150,13 +150,13 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
> XE_WARN_ON(size & ~GUC_WOPCM_SIZE_MASK);
>
> mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED;
> - err = xe_mmio_write32_and_verify(gt, GUC_WOPCM_SIZE, size, mask,
> + err = xe_mmio_write32_and_verify(>->mmio, GUC_WOPCM_SIZE, size, mask,
> size | GUC_WOPCM_SIZE_LOCKED);
> if (err)
> goto err_out;
>
> mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
> - err = xe_mmio_write32_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
> + err = xe_mmio_write32_and_verify(>->mmio, DMA_GUC_WOPCM_OFFSET,
> base | huc_agent, mask,
> base | huc_agent |
> GUC_WOPCM_OFFSET_VALID);
> @@ -169,10 +169,10 @@ static int __wopcm_init_regs(struct xe_device *xe, struct xe_gt *gt,
> drm_notice(&xe->drm, "Failed to init uC WOPCM registers!\n");
> drm_notice(&xe->drm, "%s(%#x)=%#x\n", "DMA_GUC_WOPCM_OFFSET",
> DMA_GUC_WOPCM_OFFSET.addr,
> - xe_mmio_read32(gt, DMA_GUC_WOPCM_OFFSET));
> + xe_mmio_read32(>->mmio, DMA_GUC_WOPCM_OFFSET));
> drm_notice(&xe->drm, "%s(%#x)=%#x\n", "GUC_WOPCM_SIZE",
> GUC_WOPCM_SIZE.addr,
> - xe_mmio_read32(gt, GUC_WOPCM_SIZE));
> + xe_mmio_read32(>->mmio, GUC_WOPCM_SIZE));
>
> return err;
> }
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 31/43] drm/xe/oa: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (29 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 30/43] drm/xe/wopcm: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:34 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 32/43] drm/xe/topology: " Matt Roper
` (19 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_oa.c | 48 +++++++++++++++++++++-----------------
1 file changed, 27 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 63286ed8457f..75c3b587954f 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -176,7 +176,7 @@ static const struct xe_oa_regs *__oa_regs(struct xe_oa_stream *stream)
static u32 xe_oa_hw_tail_read(struct xe_oa_stream *stream)
{
- return xe_mmio_read32(stream->gt, __oa_regs(stream)->oa_tail_ptr) &
+ return xe_mmio_read32(&stream->gt->mmio, __oa_regs(stream)->oa_tail_ptr) &
OAG_OATAILPTR_MASK;
}
@@ -366,7 +366,7 @@ static int xe_oa_append_reports(struct xe_oa_stream *stream, char __user *buf,
struct xe_reg oaheadptr = __oa_regs(stream)->oa_head_ptr;
spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
- xe_mmio_write32(stream->gt, oaheadptr,
+ xe_mmio_write32(&stream->gt->mmio, oaheadptr,
(head + gtt_offset) & OAG_OAHEADPTR_MASK);
stream->oa_buffer.head = head;
spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
@@ -377,22 +377,23 @@ static int xe_oa_append_reports(struct xe_oa_stream *stream, char __user *buf,
static void xe_oa_init_oa_buffer(struct xe_oa_stream *stream)
{
+ struct xe_mmio *mmio = &stream->gt->mmio;
u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
u32 oa_buf = gtt_offset | OABUFFER_SIZE_16M | OAG_OABUFFER_MEMORY_SELECT;
unsigned long flags;
spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
- xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_status, 0);
- xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_head_ptr,
+ xe_mmio_write32(mmio, __oa_regs(stream)->oa_status, 0);
+ xe_mmio_write32(mmio, __oa_regs(stream)->oa_head_ptr,
gtt_offset & OAG_OAHEADPTR_MASK);
stream->oa_buffer.head = 0;
/*
* PRM says: "This MMIO must be set before the OATAILPTR register and after the
* OAHEADPTR register. This is to enable proper functionality of the overflow bit".
*/
- xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_buffer, oa_buf);
- xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_tail_ptr,
+ xe_mmio_write32(mmio, __oa_regs(stream)->oa_buffer, oa_buf);
+ xe_mmio_write32(mmio, __oa_regs(stream)->oa_tail_ptr,
gtt_offset & OAG_OATAILPTR_MASK);
/* Mark that we need updated tail pointer to read from */
@@ -440,21 +441,23 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
- xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
+ xe_mmio_write32(&stream->gt->mmio, regs->oa_ctrl, val);
}
static void xe_oa_disable(struct xe_oa_stream *stream)
{
- xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_ctrl, 0);
- if (xe_mmio_wait32(stream->gt, __oa_regs(stream)->oa_ctrl,
+ struct xe_mmio *mmio = &stream->gt->mmio;
+
+ xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctrl, 0);
+ if (xe_mmio_wait32(mmio, __oa_regs(stream)->oa_ctrl,
OAG_OACONTROL_OA_COUNTER_ENABLE, 0, 50000, NULL, false))
drm_err(&stream->oa->xe->drm,
"wait for OA to be disabled timed out\n");
if (GRAPHICS_VERx100(stream->oa->xe) <= 1270 && GRAPHICS_VERx100(stream->oa->xe) != 1260) {
/* <= XE_METEORLAKE except XE_PVC */
- xe_mmio_write32(stream->gt, OA_TLB_INV_CR, 1);
- if (xe_mmio_wait32(stream->gt, OA_TLB_INV_CR, 1, 0, 50000, NULL, false))
+ xe_mmio_write32(mmio, OA_TLB_INV_CR, 1);
+ if (xe_mmio_wait32(mmio, OA_TLB_INV_CR, 1, 0, 50000, NULL, false))
drm_err(&stream->oa->xe->drm,
"wait for OA tlb invalidate timed out\n");
}
@@ -477,7 +480,7 @@ static int __xe_oa_read(struct xe_oa_stream *stream, char __user *buf,
size_t count, size_t *offset)
{
/* Only clear our bits to avoid side-effects */
- stream->oa_status = xe_mmio_rmw32(stream->gt, __oa_regs(stream)->oa_status,
+ stream->oa_status = xe_mmio_rmw32(&stream->gt->mmio, __oa_regs(stream)->oa_status,
OASTATUS_RELEVANT_BITS, 0);
/*
* Signal to userspace that there is non-zero OA status to read via
@@ -748,7 +751,8 @@ static int xe_oa_configure_oac_context(struct xe_oa_stream *stream, bool enable)
int err;
/* Set ccs select to enable programming of OAC_OACONTROL */
- xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_ctrl, __oa_ccs_select(stream));
+ xe_mmio_write32(&stream->gt->mmio, __oa_regs(stream)->oa_ctrl,
+ __oa_ccs_select(stream));
/* Modify stream hwe context image with regs_context */
err = xe_oa_modify_ctx_image(stream, stream->exec_q->lrc[0],
@@ -784,6 +788,7 @@ static u32 oag_configure_mmio_trigger(const struct xe_oa_stream *stream, bool en
static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
{
+ struct xe_mmio *mmio = &stream->gt->mmio;
u32 sqcnt1;
/*
@@ -797,7 +802,7 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
_MASKED_BIT_DISABLE(DISABLE_DOP_GATING));
}
- xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_debug,
+ xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug,
oag_configure_mmio_trigger(stream, false));
/* disable the context save/restore or OAR counters */
@@ -805,13 +810,13 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
xe_oa_configure_oa_context(stream, false);
/* Make sure we disable noa to save power. */
- xe_mmio_rmw32(stream->gt, RPM_CONFIG1, GT_NOA_ENABLE, 0);
+ xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
sqcnt1 = SQCNT1_PMON_ENABLE |
(HAS_OA_BPC_REPORTING(stream->oa->xe) ? SQCNT1_OABPC : 0);
/* Reset PMON Enable to save power. */
- xe_mmio_rmw32(stream->gt, XELPMP_SQCNT1, sqcnt1, 0);
+ xe_mmio_rmw32(mmio, XELPMP_SQCNT1, sqcnt1, 0);
}
static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
@@ -939,6 +944,7 @@ static u32 oag_report_ctx_switches(const struct xe_oa_stream *stream)
static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
{
+ struct xe_mmio *mmio = &stream->gt->mmio;
u32 oa_debug, sqcnt1;
int ret;
@@ -965,12 +971,12 @@ static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
OAG_OA_DEBUG_DISABLE_START_TRG_2_COUNT_QUAL |
OAG_OA_DEBUG_DISABLE_START_TRG_1_COUNT_QUAL;
- xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_debug,
+ xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug,
_MASKED_BIT_ENABLE(oa_debug) |
oag_report_ctx_switches(stream) |
oag_configure_mmio_trigger(stream, true));
- xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_ctx_ctrl, stream->periodic ?
+ xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctx_ctrl, stream->periodic ?
(OAG_OAGLBCTXCTRL_COUNTER_RESUME |
OAG_OAGLBCTXCTRL_TIMER_ENABLE |
REG_FIELD_PREP(OAG_OAGLBCTXCTRL_TIMER_PERIOD_MASK,
@@ -984,7 +990,7 @@ static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
sqcnt1 = SQCNT1_PMON_ENABLE |
(HAS_OA_BPC_REPORTING(stream->oa->xe) ? SQCNT1_OABPC : 0);
- xe_mmio_rmw32(stream->gt, XELPMP_SQCNT1, 0, sqcnt1);
+ xe_mmio_rmw32(mmio, XELPMP_SQCNT1, 0, sqcnt1);
/* Configure OAR/OAC */
if (stream->exec_q) {
@@ -1533,7 +1539,7 @@ u32 xe_oa_timestamp_frequency(struct xe_gt *gt)
case XE_PVC:
case XE_METEORLAKE:
xe_pm_runtime_get(gt_to_xe(gt));
- reg = xe_mmio_read32(gt, RPM_CONFIG0);
+ reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
xe_pm_runtime_put(gt_to_xe(gt));
shift = REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
@@ -2349,7 +2355,7 @@ static void __xe_oa_init_oa_units(struct xe_gt *gt)
}
/* Ensure MMIO trigger remains disabled till there is a stream */
- xe_mmio_write32(gt, u->regs.oa_debug,
+ xe_mmio_write32(>->mmio, u->regs.oa_debug,
oag_configure_mmio_trigger(NULL, false));
/* Set oa_unit_ids now to ensure ids remain contiguous */
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 31/43] drm/xe/oa: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 31/43] drm/xe/oa: " Matt Roper
@ 2024-09-10 18:34 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:34 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:20PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_oa.c | 48 +++++++++++++++++++++-----------------
> 1 file changed, 27 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
> index 63286ed8457f..75c3b587954f 100644
> --- a/drivers/gpu/drm/xe/xe_oa.c
> +++ b/drivers/gpu/drm/xe/xe_oa.c
> @@ -176,7 +176,7 @@ static const struct xe_oa_regs *__oa_regs(struct xe_oa_stream *stream)
>
> static u32 xe_oa_hw_tail_read(struct xe_oa_stream *stream)
> {
> - return xe_mmio_read32(stream->gt, __oa_regs(stream)->oa_tail_ptr) &
> + return xe_mmio_read32(&stream->gt->mmio, __oa_regs(stream)->oa_tail_ptr) &
> OAG_OATAILPTR_MASK;
> }
>
> @@ -366,7 +366,7 @@ static int xe_oa_append_reports(struct xe_oa_stream *stream, char __user *buf,
> struct xe_reg oaheadptr = __oa_regs(stream)->oa_head_ptr;
>
> spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
> - xe_mmio_write32(stream->gt, oaheadptr,
> + xe_mmio_write32(&stream->gt->mmio, oaheadptr,
> (head + gtt_offset) & OAG_OAHEADPTR_MASK);
> stream->oa_buffer.head = head;
> spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
> @@ -377,22 +377,23 @@ static int xe_oa_append_reports(struct xe_oa_stream *stream, char __user *buf,
>
> static void xe_oa_init_oa_buffer(struct xe_oa_stream *stream)
> {
> + struct xe_mmio *mmio = &stream->gt->mmio;
> u32 gtt_offset = xe_bo_ggtt_addr(stream->oa_buffer.bo);
> u32 oa_buf = gtt_offset | OABUFFER_SIZE_16M | OAG_OABUFFER_MEMORY_SELECT;
> unsigned long flags;
>
> spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
>
> - xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_status, 0);
> - xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_head_ptr,
> + xe_mmio_write32(mmio, __oa_regs(stream)->oa_status, 0);
> + xe_mmio_write32(mmio, __oa_regs(stream)->oa_head_ptr,
> gtt_offset & OAG_OAHEADPTR_MASK);
> stream->oa_buffer.head = 0;
> /*
> * PRM says: "This MMIO must be set before the OATAILPTR register and after the
> * OAHEADPTR register. This is to enable proper functionality of the overflow bit".
> */
> - xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_buffer, oa_buf);
> - xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_tail_ptr,
> + xe_mmio_write32(mmio, __oa_regs(stream)->oa_buffer, oa_buf);
> + xe_mmio_write32(mmio, __oa_regs(stream)->oa_tail_ptr,
> gtt_offset & OAG_OATAILPTR_MASK);
>
> /* Mark that we need updated tail pointer to read from */
> @@ -440,21 +441,23 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
> val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
> __oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
>
> - xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
> + xe_mmio_write32(&stream->gt->mmio, regs->oa_ctrl, val);
> }
>
> static void xe_oa_disable(struct xe_oa_stream *stream)
> {
> - xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_ctrl, 0);
> - if (xe_mmio_wait32(stream->gt, __oa_regs(stream)->oa_ctrl,
> + struct xe_mmio *mmio = &stream->gt->mmio;
> +
> + xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctrl, 0);
> + if (xe_mmio_wait32(mmio, __oa_regs(stream)->oa_ctrl,
> OAG_OACONTROL_OA_COUNTER_ENABLE, 0, 50000, NULL, false))
> drm_err(&stream->oa->xe->drm,
> "wait for OA to be disabled timed out\n");
>
> if (GRAPHICS_VERx100(stream->oa->xe) <= 1270 && GRAPHICS_VERx100(stream->oa->xe) != 1260) {
> /* <= XE_METEORLAKE except XE_PVC */
> - xe_mmio_write32(stream->gt, OA_TLB_INV_CR, 1);
> - if (xe_mmio_wait32(stream->gt, OA_TLB_INV_CR, 1, 0, 50000, NULL, false))
> + xe_mmio_write32(mmio, OA_TLB_INV_CR, 1);
> + if (xe_mmio_wait32(mmio, OA_TLB_INV_CR, 1, 0, 50000, NULL, false))
> drm_err(&stream->oa->xe->drm,
> "wait for OA tlb invalidate timed out\n");
> }
> @@ -477,7 +480,7 @@ static int __xe_oa_read(struct xe_oa_stream *stream, char __user *buf,
> size_t count, size_t *offset)
> {
> /* Only clear our bits to avoid side-effects */
> - stream->oa_status = xe_mmio_rmw32(stream->gt, __oa_regs(stream)->oa_status,
> + stream->oa_status = xe_mmio_rmw32(&stream->gt->mmio, __oa_regs(stream)->oa_status,
> OASTATUS_RELEVANT_BITS, 0);
> /*
> * Signal to userspace that there is non-zero OA status to read via
> @@ -748,7 +751,8 @@ static int xe_oa_configure_oac_context(struct xe_oa_stream *stream, bool enable)
> int err;
>
> /* Set ccs select to enable programming of OAC_OACONTROL */
> - xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_ctrl, __oa_ccs_select(stream));
> + xe_mmio_write32(&stream->gt->mmio, __oa_regs(stream)->oa_ctrl,
> + __oa_ccs_select(stream));
>
> /* Modify stream hwe context image with regs_context */
> err = xe_oa_modify_ctx_image(stream, stream->exec_q->lrc[0],
> @@ -784,6 +788,7 @@ static u32 oag_configure_mmio_trigger(const struct xe_oa_stream *stream, bool en
>
> static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
> {
> + struct xe_mmio *mmio = &stream->gt->mmio;
> u32 sqcnt1;
>
> /*
> @@ -797,7 +802,7 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
> _MASKED_BIT_DISABLE(DISABLE_DOP_GATING));
> }
>
> - xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_debug,
> + xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug,
> oag_configure_mmio_trigger(stream, false));
>
> /* disable the context save/restore or OAR counters */
> @@ -805,13 +810,13 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
> xe_oa_configure_oa_context(stream, false);
>
> /* Make sure we disable noa to save power. */
> - xe_mmio_rmw32(stream->gt, RPM_CONFIG1, GT_NOA_ENABLE, 0);
> + xe_mmio_rmw32(mmio, RPM_CONFIG1, GT_NOA_ENABLE, 0);
>
> sqcnt1 = SQCNT1_PMON_ENABLE |
> (HAS_OA_BPC_REPORTING(stream->oa->xe) ? SQCNT1_OABPC : 0);
>
> /* Reset PMON Enable to save power. */
> - xe_mmio_rmw32(stream->gt, XELPMP_SQCNT1, sqcnt1, 0);
> + xe_mmio_rmw32(mmio, XELPMP_SQCNT1, sqcnt1, 0);
> }
>
> static void xe_oa_stream_destroy(struct xe_oa_stream *stream)
> @@ -939,6 +944,7 @@ static u32 oag_report_ctx_switches(const struct xe_oa_stream *stream)
>
> static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
> {
> + struct xe_mmio *mmio = &stream->gt->mmio;
> u32 oa_debug, sqcnt1;
> int ret;
>
> @@ -965,12 +971,12 @@ static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
> OAG_OA_DEBUG_DISABLE_START_TRG_2_COUNT_QUAL |
> OAG_OA_DEBUG_DISABLE_START_TRG_1_COUNT_QUAL;
>
> - xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_debug,
> + xe_mmio_write32(mmio, __oa_regs(stream)->oa_debug,
> _MASKED_BIT_ENABLE(oa_debug) |
> oag_report_ctx_switches(stream) |
> oag_configure_mmio_trigger(stream, true));
>
> - xe_mmio_write32(stream->gt, __oa_regs(stream)->oa_ctx_ctrl, stream->periodic ?
> + xe_mmio_write32(mmio, __oa_regs(stream)->oa_ctx_ctrl, stream->periodic ?
> (OAG_OAGLBCTXCTRL_COUNTER_RESUME |
> OAG_OAGLBCTXCTRL_TIMER_ENABLE |
> REG_FIELD_PREP(OAG_OAGLBCTXCTRL_TIMER_PERIOD_MASK,
> @@ -984,7 +990,7 @@ static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
> sqcnt1 = SQCNT1_PMON_ENABLE |
> (HAS_OA_BPC_REPORTING(stream->oa->xe) ? SQCNT1_OABPC : 0);
>
> - xe_mmio_rmw32(stream->gt, XELPMP_SQCNT1, 0, sqcnt1);
> + xe_mmio_rmw32(mmio, XELPMP_SQCNT1, 0, sqcnt1);
>
> /* Configure OAR/OAC */
> if (stream->exec_q) {
> @@ -1533,7 +1539,7 @@ u32 xe_oa_timestamp_frequency(struct xe_gt *gt)
> case XE_PVC:
> case XE_METEORLAKE:
> xe_pm_runtime_get(gt_to_xe(gt));
> - reg = xe_mmio_read32(gt, RPM_CONFIG0);
> + reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
> xe_pm_runtime_put(gt_to_xe(gt));
>
> shift = REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
> @@ -2349,7 +2355,7 @@ static void __xe_oa_init_oa_units(struct xe_gt *gt)
> }
>
> /* Ensure MMIO trigger remains disabled till there is a stream */
> - xe_mmio_write32(gt, u->regs.oa_debug,
> + xe_mmio_write32(>->mmio, u->regs.oa_debug,
> oag_configure_mmio_trigger(NULL, false));
>
> /* Set oa_unit_ids now to ensure ids remain contiguous */
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 32/43] drm/xe/topology: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (30 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 31/43] drm/xe/oa: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:11 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 33/43] drm/xe/execlist: " Matt Roper
` (18 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt_topology.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
index 0662f71c6ede..651ba53623e5 100644
--- a/drivers/gpu/drm/xe/xe_gt_topology.c
+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
@@ -25,7 +25,7 @@ load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
va_start(argp, numregs);
for (i = 0; i < numregs; i++)
- fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, struct xe_reg));
+ fuse_val[i] = xe_mmio_read32(>->mmio, va_arg(argp, struct xe_reg));
va_end(argp);
bitmap_from_arr32(mask, fuse_val, numregs * 32);
@@ -35,7 +35,7 @@ static void
load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask, enum xe_gt_eu_type *eu_type)
{
struct xe_device *xe = gt_to_xe(gt);
- u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE);
+ u32 reg_val = xe_mmio_read32(>->mmio, XELP_EU_ENABLE);
u32 val = 0;
int i;
@@ -127,7 +127,7 @@ static void
load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
{
struct xe_device *xe = gt_to_xe(gt);
- u32 fuse3 = xe_mmio_read32(gt, MIRROR_FUSE3);
+ u32 fuse3 = xe_mmio_read32(>->mmio, MIRROR_FUSE3);
if (GRAPHICS_VER(xe) >= 20) {
xe_l3_bank_mask_t per_node = {};
@@ -141,7 +141,7 @@ load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
xe_l3_bank_mask_t per_node = {};
xe_l3_bank_mask_t per_mask_bit = {};
u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3);
- u32 fuse4 = xe_mmio_read32(gt, XEHP_FUSE4);
+ u32 fuse4 = xe_mmio_read32(>->mmio, XEHP_FUSE4);
u32 bank_val = REG_FIELD_GET(GT_L3_EXC_MASK, fuse4);
bitmap_set_value8(per_mask_bit, 0x3, 0);
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 32/43] drm/xe/topology: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 32/43] drm/xe/topology: " Matt Roper
@ 2024-09-10 18:11 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:11 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:21PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt_topology.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
> index 0662f71c6ede..651ba53623e5 100644
> --- a/drivers/gpu/drm/xe/xe_gt_topology.c
> +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
> @@ -25,7 +25,7 @@ load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
>
> va_start(argp, numregs);
> for (i = 0; i < numregs; i++)
> - fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, struct xe_reg));
> + fuse_val[i] = xe_mmio_read32(>->mmio, va_arg(argp, struct xe_reg));
> va_end(argp);
>
> bitmap_from_arr32(mask, fuse_val, numregs * 32);
> @@ -35,7 +35,7 @@ static void
> load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask, enum xe_gt_eu_type *eu_type)
> {
> struct xe_device *xe = gt_to_xe(gt);
> - u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE);
> + u32 reg_val = xe_mmio_read32(>->mmio, XELP_EU_ENABLE);
> u32 val = 0;
> int i;
>
> @@ -127,7 +127,7 @@ static void
> load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
> {
> struct xe_device *xe = gt_to_xe(gt);
> - u32 fuse3 = xe_mmio_read32(gt, MIRROR_FUSE3);
> + u32 fuse3 = xe_mmio_read32(>->mmio, MIRROR_FUSE3);
>
> if (GRAPHICS_VER(xe) >= 20) {
> xe_l3_bank_mask_t per_node = {};
> @@ -141,7 +141,7 @@ load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask)
> xe_l3_bank_mask_t per_node = {};
> xe_l3_bank_mask_t per_mask_bit = {};
> u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3);
> - u32 fuse4 = xe_mmio_read32(gt, XEHP_FUSE4);
> + u32 fuse4 = xe_mmio_read32(>->mmio, XEHP_FUSE4);
> u32 bank_val = REG_FIELD_GET(GT_L3_EXC_MASK, fuse4);
>
> bitmap_set_value8(per_mask_bit, 0x3, 0);
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 33/43] drm/xe/execlist: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (31 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 32/43] drm/xe/topology: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:13 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 34/43] drm/xe/gt_clock: " Matt Roper
` (17 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_execlist.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index 6a59165b9569..f3b71fe7a96d 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -44,6 +44,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
u32 ctx_id)
{
struct xe_gt *gt = hwe->gt;
+ struct xe_mmio *mmio = >->mmio;
struct xe_device *xe = gt_to_xe(gt);
u64 lrc_desc;
@@ -58,7 +59,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
}
if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
- xe_mmio_write32(hwe->gt, RCU_MODE,
+ xe_mmio_write32(mmio, RCU_MODE,
_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
@@ -76,17 +77,17 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
*/
wmb();
- xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base),
+ xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base),
xe_bo_ggtt_addr(hwe->hwsp));
- xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base));
- xe_mmio_write32(gt, RING_MODE(hwe->mmio_base),
+ xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base));
+ xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base),
_MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
- xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
+ xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
lower_32_bits(lrc_desc));
- xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),
+ xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),
upper_32_bits(lrc_desc));
- xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base),
+ xe_mmio_write32(mmio, RING_EXECLIST_CONTROL(hwe->mmio_base),
EL_CTRL_LOAD);
}
@@ -168,8 +169,8 @@ static u64 read_execlist_status(struct xe_hw_engine *hwe)
struct xe_gt *gt = hwe->gt;
u32 hi, lo;
- lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base));
- hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
+ lo = xe_mmio_read32(>->mmio, RING_EXECLIST_STATUS_LO(hwe->mmio_base));
+ hi = xe_mmio_read32(>->mmio, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
return lo | (u64)hi << 32;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 33/43] drm/xe/execlist: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 33/43] drm/xe/execlist: " Matt Roper
@ 2024-09-10 18:13 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:13 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:22PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_execlist.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
> index 6a59165b9569..f3b71fe7a96d 100644
> --- a/drivers/gpu/drm/xe/xe_execlist.c
> +++ b/drivers/gpu/drm/xe/xe_execlist.c
> @@ -44,6 +44,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
> u32 ctx_id)
> {
> struct xe_gt *gt = hwe->gt;
> + struct xe_mmio *mmio = >->mmio;
> struct xe_device *xe = gt_to_xe(gt);
> u64 lrc_desc;
>
> @@ -58,7 +59,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
> }
>
> if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
> - xe_mmio_write32(hwe->gt, RCU_MODE,
> + xe_mmio_write32(mmio, RCU_MODE,
> _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
>
> xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
> @@ -76,17 +77,17 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
> */
> wmb();
>
> - xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base),
> + xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base),
> xe_bo_ggtt_addr(hwe->hwsp));
> - xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base));
> - xe_mmio_write32(gt, RING_MODE(hwe->mmio_base),
> + xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base));
> + xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base),
> _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
>
> - xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
> + xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
> lower_32_bits(lrc_desc));
> - xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),
> + xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),
> upper_32_bits(lrc_desc));
> - xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base),
> + xe_mmio_write32(mmio, RING_EXECLIST_CONTROL(hwe->mmio_base),
> EL_CTRL_LOAD);
> }
>
> @@ -168,8 +169,8 @@ static u64 read_execlist_status(struct xe_hw_engine *hwe)
> struct xe_gt *gt = hwe->gt;
> u32 hi, lo;
>
> - lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base));
> - hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
> + lo = xe_mmio_read32(>->mmio, RING_EXECLIST_STATUS_LO(hwe->mmio_base));
> + hi = xe_mmio_read32(>->mmio, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
>
> return lo | (u64)hi << 32;
> }
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 34/43] drm/xe/gt_clock: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (32 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 33/43] drm/xe/execlist: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:44 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 35/43] drm/xe/reg_sr: " Matt Roper
` (16 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt_clock.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
index 86c2d62b4bdc..cc2ae159298e 100644
--- a/drivers/gpu/drm/xe/xe_gt_clock.c
+++ b/drivers/gpu/drm/xe/xe_gt_clock.c
@@ -17,7 +17,7 @@
static u32 read_reference_ts_freq(struct xe_gt *gt)
{
- u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE);
+ u32 ts_override = xe_mmio_read32(>->mmio, TIMESTAMP_OVERRIDE);
u32 base_freq, frac_freq;
base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK,
@@ -57,7 +57,7 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg)
int xe_gt_clock_init(struct xe_gt *gt)
{
- u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE);
+ u32 ctc_reg = xe_mmio_read32(>->mmio, CTC_MODE);
u32 freq = 0;
/* Assuming gen11+ so assert this assumption is correct */
@@ -66,7 +66,7 @@ int xe_gt_clock_init(struct xe_gt *gt)
if (ctc_reg & CTC_SOURCE_DIVIDE_LOGIC) {
freq = read_reference_ts_freq(gt);
} else {
- u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0);
+ u32 c0 = xe_mmio_read32(>->mmio, RPM_CONFIG0);
freq = get_crystal_clock_freq(c0);
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 34/43] drm/xe/gt_clock: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 34/43] drm/xe/gt_clock: " Matt Roper
@ 2024-09-10 18:44 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:44 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:23PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt_clock.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_clock.c b/drivers/gpu/drm/xe/xe_gt_clock.c
> index 86c2d62b4bdc..cc2ae159298e 100644
> --- a/drivers/gpu/drm/xe/xe_gt_clock.c
> +++ b/drivers/gpu/drm/xe/xe_gt_clock.c
> @@ -17,7 +17,7 @@
>
> static u32 read_reference_ts_freq(struct xe_gt *gt)
> {
> - u32 ts_override = xe_mmio_read32(gt, TIMESTAMP_OVERRIDE);
> + u32 ts_override = xe_mmio_read32(>->mmio, TIMESTAMP_OVERRIDE);
> u32 base_freq, frac_freq;
>
> base_freq = REG_FIELD_GET(TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK,
> @@ -57,7 +57,7 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg)
>
> int xe_gt_clock_init(struct xe_gt *gt)
> {
> - u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE);
> + u32 ctc_reg = xe_mmio_read32(>->mmio, CTC_MODE);
> u32 freq = 0;
>
> /* Assuming gen11+ so assert this assumption is correct */
> @@ -66,7 +66,7 @@ int xe_gt_clock_init(struct xe_gt *gt)
> if (ctc_reg & CTC_SOURCE_DIVIDE_LOGIC) {
> freq = read_reference_ts_freq(gt);
> } else {
> - u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0);
> + u32 c0 = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>
> freq = get_crystal_clock_freq(c0);
>
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 35/43] drm/xe/reg_sr: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (33 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 34/43] drm/xe/gt_clock: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:15 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 36/43] drm/xe/gt: " Matt Roper
` (15 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_reg_sr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index fb209f1e0f1e..191cb4121acd 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -165,7 +165,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
else if (entry->clr_bits + 1)
val = (reg.mcr ?
xe_gt_mcr_unicast_read_any(gt, reg_mcr) :
- xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
+ xe_mmio_read32(>->mmio, reg)) & (~entry->clr_bits);
else
val = 0;
@@ -181,7 +181,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
if (entry->reg.mcr)
xe_gt_mcr_multicast_write(gt, reg_mcr, val);
else
- xe_mmio_write32(gt, reg, val);
+ xe_mmio_write32(>->mmio, reg, val);
}
void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt)
@@ -242,7 +242,7 @@ void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe)
}
xe_reg_whitelist_print_entry(&p, 0, reg, entry);
- xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot),
+ xe_mmio_write32(>->mmio, RING_FORCE_TO_NONPRIV(mmio_base, slot),
reg | entry->set_bits);
slot++;
}
@@ -251,7 +251,7 @@ void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe)
for (; slot < RING_MAX_NONPRIV_SLOTS; slot++) {
u32 addr = RING_NOPID(mmio_base).addr;
- xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
+ xe_mmio_write32(>->mmio, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
}
err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 35/43] drm/xe/reg_sr: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 35/43] drm/xe/reg_sr: " Matt Roper
@ 2024-09-10 18:15 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:15 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:24PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_reg_sr.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
> index fb209f1e0f1e..191cb4121acd 100644
> --- a/drivers/gpu/drm/xe/xe_reg_sr.c
> +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
> @@ -165,7 +165,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
> else if (entry->clr_bits + 1)
> val = (reg.mcr ?
> xe_gt_mcr_unicast_read_any(gt, reg_mcr) :
> - xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
> + xe_mmio_read32(>->mmio, reg)) & (~entry->clr_bits);
> else
> val = 0;
>
> @@ -181,7 +181,7 @@ static void apply_one_mmio(struct xe_gt *gt, struct xe_reg_sr_entry *entry)
> if (entry->reg.mcr)
> xe_gt_mcr_multicast_write(gt, reg_mcr, val);
> else
> - xe_mmio_write32(gt, reg, val);
> + xe_mmio_write32(>->mmio, reg, val);
> }
>
> void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt)
> @@ -242,7 +242,7 @@ void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe)
> }
>
> xe_reg_whitelist_print_entry(&p, 0, reg, entry);
> - xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot),
> + xe_mmio_write32(>->mmio, RING_FORCE_TO_NONPRIV(mmio_base, slot),
> reg | entry->set_bits);
> slot++;
> }
> @@ -251,7 +251,7 @@ void xe_reg_sr_apply_whitelist(struct xe_hw_engine *hwe)
> for (; slot < RING_MAX_NONPRIV_SLOTS; slot++) {
> u32 addr = RING_NOPID(mmio_base).addr;
>
> - xe_mmio_write32(gt, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
> + xe_mmio_write32(>->mmio, RING_FORCE_TO_NONPRIV(mmio_base, slot), addr);
> }
>
> err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 36/43] drm/xe/gt: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (34 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 35/43] drm/xe/reg_sr: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:11 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 37/43] drm/xe/sriov: " Matt Roper
` (14 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index dd96dec95b19..4a768b5f9542 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -110,7 +110,7 @@ static void xe_gt_enable_host_l2_vram(struct xe_gt *gt)
return;
if (!xe_gt_is_media_type(gt)) {
- xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
+ xe_mmio_write32(>->mmio, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
reg |= CG_DIS_CNTLBUS;
xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
@@ -247,7 +247,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
else if (entry->clr_bits + 1)
val = (reg.mcr ?
xe_gt_mcr_unicast_read_any(gt, reg_mcr) :
- xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
+ xe_mmio_read32(>->mmio, reg)) & (~entry->clr_bits);
else
val = 0;
@@ -442,7 +442,7 @@ static int gt_fw_domain_init(struct xe_gt *gt)
* Stash hardware-reported version. Since this register does not exist
* on pre-MTL platforms, reading it there will (correctly) return 0.
*/
- gt->info.gmdid = xe_mmio_read32(gt, GMD_ID);
+ gt->info.gmdid = xe_mmio_read32(>->mmio, GMD_ID);
err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
XE_WARN_ON(err);
@@ -652,8 +652,8 @@ static int do_gt_reset(struct xe_gt *gt)
xe_gsc_wa_14015076503(gt, true);
- xe_mmio_write32(gt, GDRST, GRDOM_FULL);
- err = xe_mmio_wait32(gt, GDRST, GRDOM_FULL, 0, 5000, NULL, false);
+ xe_mmio_write32(>->mmio, GDRST, GRDOM_FULL);
+ err = xe_mmio_wait32(>->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false);
if (err)
xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n",
ERR_PTR(err));
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 36/43] drm/xe/gt: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 36/43] drm/xe/gt: " Matt Roper
@ 2024-09-10 18:11 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:11 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:25PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index dd96dec95b19..4a768b5f9542 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -110,7 +110,7 @@ static void xe_gt_enable_host_l2_vram(struct xe_gt *gt)
> return;
>
> if (!xe_gt_is_media_type(gt)) {
> - xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
> + xe_mmio_write32(>->mmio, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
> reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
> reg |= CG_DIS_CNTLBUS;
> xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
> @@ -247,7 +247,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
> else if (entry->clr_bits + 1)
> val = (reg.mcr ?
> xe_gt_mcr_unicast_read_any(gt, reg_mcr) :
> - xe_mmio_read32(gt, reg)) & (~entry->clr_bits);
> + xe_mmio_read32(>->mmio, reg)) & (~entry->clr_bits);
> else
> val = 0;
>
> @@ -442,7 +442,7 @@ static int gt_fw_domain_init(struct xe_gt *gt)
> * Stash hardware-reported version. Since this register does not exist
> * on pre-MTL platforms, reading it there will (correctly) return 0.
> */
> - gt->info.gmdid = xe_mmio_read32(gt, GMD_ID);
> + gt->info.gmdid = xe_mmio_read32(>->mmio, GMD_ID);
>
> err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> XE_WARN_ON(err);
> @@ -652,8 +652,8 @@ static int do_gt_reset(struct xe_gt *gt)
>
> xe_gsc_wa_14015076503(gt, true);
>
> - xe_mmio_write32(gt, GDRST, GRDOM_FULL);
> - err = xe_mmio_wait32(gt, GDRST, GRDOM_FULL, 0, 5000, NULL, false);
> + xe_mmio_write32(>->mmio, GDRST, GRDOM_FULL);
> + err = xe_mmio_wait32(>->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false);
> if (err)
> xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n",
> ERR_PTR(err));
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 37/43] drm/xe/sriov: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (35 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 36/43] drm/xe/gt: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:47 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 38/43] drm/xe/tlb: " Matt Roper
` (13 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt_sriov_pf.c | 6 +++---
drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c | 6 +++---
drivers/gpu/drm/xe/xe_gt_sriov_vf.c | 4 ++--
drivers/gpu/drm/xe/xe_sriov.c | 2 +-
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
index 919d960165d5..065a9878f8e9 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
@@ -74,7 +74,7 @@ static bool pf_needs_enable_ggtt_guest_update(struct xe_device *xe)
static void pf_enable_ggtt_guest_update(struct xe_gt *gt)
{
- xe_mmio_write32(gt, VIRTUAL_CTRL_REG, GUEST_GTT_UPDATE_EN);
+ xe_mmio_write32(>->mmio, VIRTUAL_CTRL_REG, GUEST_GTT_UPDATE_EN);
}
/**
@@ -116,13 +116,13 @@ static void pf_clear_vf_scratch_regs(struct xe_gt *gt, unsigned int vfid)
count = MED_VF_SW_FLAG_COUNT;
for (n = 0; n < count; n++) {
scratch = xe_reg_vf_to_pf(MED_VF_SW_FLAG(n), vfid, stride);
- xe_mmio_write32(gt, scratch, 0);
+ xe_mmio_write32(>->mmio, scratch, 0);
}
} else {
count = VF_SW_FLAG_COUNT;
for (n = 0; n < count; n++) {
scratch = xe_reg_vf_to_pf(VF_SW_FLAG(n), vfid, stride);
- xe_mmio_write32(gt, scratch, 0);
+ xe_mmio_write32(>->mmio, scratch, 0);
}
}
}
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c
index 0e23b7ea4f3e..924e75b94aec 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c
@@ -237,7 +237,7 @@ static void read_many(struct xe_gt *gt, unsigned int count,
const struct xe_reg *regs, u32 *values)
{
while (count--)
- *values++ = xe_mmio_read32(gt, *regs++);
+ *values++ = xe_mmio_read32(>->mmio, *regs++);
}
static void pf_prepare_runtime_info(struct xe_gt *gt)
@@ -402,7 +402,7 @@ static int pf_service_runtime_query(struct xe_gt *gt, u32 start, u32 limit,
for (i = 0; i < count; ++i, ++data) {
addr = runtime->regs[start + i].addr;
- data->offset = xe_mmio_adjusted_addr(gt, addr);
+ data->offset = xe_mmio_adjusted_addr(>->mmio, addr);
data->value = runtime->values[start + i];
}
@@ -513,7 +513,7 @@ int xe_gt_sriov_pf_service_print_runtime(struct xe_gt *gt, struct drm_printer *p
for (; size--; regs++, values++) {
drm_printf(p, "reg[%#x] = %#x\n",
- xe_mmio_adjusted_addr(gt, regs->addr), *values);
+ xe_mmio_adjusted_addr(>->mmio, regs->addr), *values);
}
return 0;
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
index 4ebc82e607af..d3baba50f085 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
@@ -881,7 +881,7 @@ static struct vf_runtime_reg *vf_lookup_reg(struct xe_gt *gt, u32 addr)
*/
u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg)
{
- u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
+ u32 addr = xe_mmio_adjusted_addr(>->mmio, reg.addr);
struct vf_runtime_reg *rr;
xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
@@ -917,7 +917,7 @@ u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg)
*/
void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val)
{
- u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
+ u32 addr = xe_mmio_adjusted_addr(>->mmio, reg.addr);
xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
xe_gt_assert(gt, !reg.vf);
diff --git a/drivers/gpu/drm/xe/xe_sriov.c b/drivers/gpu/drm/xe/xe_sriov.c
index 5a1d65e4f19f..69a066ef20c0 100644
--- a/drivers/gpu/drm/xe/xe_sriov.c
+++ b/drivers/gpu/drm/xe/xe_sriov.c
@@ -35,7 +35,7 @@ const char *xe_sriov_mode_to_string(enum xe_sriov_mode mode)
static bool test_is_vf(struct xe_device *xe)
{
- u32 value = xe_mmio_read32(xe_root_mmio_gt(xe), VF_CAP_REG);
+ u32 value = xe_mmio_read32(xe_root_tile_mmio(xe), VF_CAP_REG);
return value & VF_CAP;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 37/43] drm/xe/sriov: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 37/43] drm/xe/sriov: " Matt Roper
@ 2024-09-10 18:47 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:47 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:26PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt_sriov_pf.c | 6 +++---
> drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c | 6 +++---
> drivers/gpu/drm/xe/xe_gt_sriov_vf.c | 4 ++--
> drivers/gpu/drm/xe/xe_sriov.c | 2 +-
> 4 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
> index 919d960165d5..065a9878f8e9 100644
> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
> @@ -74,7 +74,7 @@ static bool pf_needs_enable_ggtt_guest_update(struct xe_device *xe)
>
> static void pf_enable_ggtt_guest_update(struct xe_gt *gt)
> {
> - xe_mmio_write32(gt, VIRTUAL_CTRL_REG, GUEST_GTT_UPDATE_EN);
> + xe_mmio_write32(>->mmio, VIRTUAL_CTRL_REG, GUEST_GTT_UPDATE_EN);
> }
>
> /**
> @@ -116,13 +116,13 @@ static void pf_clear_vf_scratch_regs(struct xe_gt *gt, unsigned int vfid)
> count = MED_VF_SW_FLAG_COUNT;
> for (n = 0; n < count; n++) {
> scratch = xe_reg_vf_to_pf(MED_VF_SW_FLAG(n), vfid, stride);
> - xe_mmio_write32(gt, scratch, 0);
> + xe_mmio_write32(>->mmio, scratch, 0);
> }
> } else {
> count = VF_SW_FLAG_COUNT;
> for (n = 0; n < count; n++) {
> scratch = xe_reg_vf_to_pf(VF_SW_FLAG(n), vfid, stride);
> - xe_mmio_write32(gt, scratch, 0);
> + xe_mmio_write32(>->mmio, scratch, 0);
> }
> }
> }
> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c
> index 0e23b7ea4f3e..924e75b94aec 100644
> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c
> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c
> @@ -237,7 +237,7 @@ static void read_many(struct xe_gt *gt, unsigned int count,
> const struct xe_reg *regs, u32 *values)
> {
> while (count--)
> - *values++ = xe_mmio_read32(gt, *regs++);
> + *values++ = xe_mmio_read32(>->mmio, *regs++);
> }
>
> static void pf_prepare_runtime_info(struct xe_gt *gt)
> @@ -402,7 +402,7 @@ static int pf_service_runtime_query(struct xe_gt *gt, u32 start, u32 limit,
>
> for (i = 0; i < count; ++i, ++data) {
> addr = runtime->regs[start + i].addr;
> - data->offset = xe_mmio_adjusted_addr(gt, addr);
> + data->offset = xe_mmio_adjusted_addr(>->mmio, addr);
> data->value = runtime->values[start + i];
> }
>
> @@ -513,7 +513,7 @@ int xe_gt_sriov_pf_service_print_runtime(struct xe_gt *gt, struct drm_printer *p
>
> for (; size--; regs++, values++) {
> drm_printf(p, "reg[%#x] = %#x\n",
> - xe_mmio_adjusted_addr(gt, regs->addr), *values);
> + xe_mmio_adjusted_addr(>->mmio, regs->addr), *values);
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
> index 4ebc82e607af..d3baba50f085 100644
> --- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
> @@ -881,7 +881,7 @@ static struct vf_runtime_reg *vf_lookup_reg(struct xe_gt *gt, u32 addr)
> */
> u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg)
> {
> - u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
> + u32 addr = xe_mmio_adjusted_addr(>->mmio, reg.addr);
> struct vf_runtime_reg *rr;
>
> xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
> @@ -917,7 +917,7 @@ u32 xe_gt_sriov_vf_read32(struct xe_gt *gt, struct xe_reg reg)
> */
> void xe_gt_sriov_vf_write32(struct xe_gt *gt, struct xe_reg reg, u32 val)
> {
> - u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);
> + u32 addr = xe_mmio_adjusted_addr(>->mmio, reg.addr);
>
> xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
> xe_gt_assert(gt, !reg.vf);
> diff --git a/drivers/gpu/drm/xe/xe_sriov.c b/drivers/gpu/drm/xe/xe_sriov.c
> index 5a1d65e4f19f..69a066ef20c0 100644
> --- a/drivers/gpu/drm/xe/xe_sriov.c
> +++ b/drivers/gpu/drm/xe/xe_sriov.c
> @@ -35,7 +35,7 @@ const char *xe_sriov_mode_to_string(enum xe_sriov_mode mode)
>
> static bool test_is_vf(struct xe_device *xe)
> {
> - u32 value = xe_mmio_read32(xe_root_mmio_gt(xe), VF_CAP_REG);
> + u32 value = xe_mmio_read32(xe_root_tile_mmio(xe), VF_CAP_REG);
>
> return value & VF_CAP;
> }
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 38/43] drm/xe/tlb: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (36 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 37/43] drm/xe/sriov: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:45 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 39/43] drm/xe/gt_idle: " Matt Roper
` (12 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
index cca9cf536f76..98616de0c5bb 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
@@ -274,17 +274,19 @@ int xe_gt_tlb_invalidation_ggtt(struct xe_gt *gt)
xe_gt_tlb_invalidation_fence_wait(&fence);
} else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
+ struct xe_mmio *mmio = >->mmio;
+
if (IS_SRIOV_VF(xe))
return 0;
xe_gt_WARN_ON(gt, xe_force_wake_get(gt_to_fw(gt), XE_FW_GT));
if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20) {
- xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1,
+ xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
PVC_GUC_TLB_INV_DESC1_INVALIDATE);
- xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0,
+ xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
PVC_GUC_TLB_INV_DESC0_VALID);
} else {
- xe_mmio_write32(gt, GUC_TLB_INV_CR,
+ xe_mmio_write32(mmio, GUC_TLB_INV_CR,
GUC_TLB_INV_CR_INVALIDATE);
}
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 38/43] drm/xe/tlb: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 38/43] drm/xe/tlb: " Matt Roper
@ 2024-09-10 18:45 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:45 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:27PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
> index cca9cf536f76..98616de0c5bb 100644
> --- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
> +++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
> @@ -274,17 +274,19 @@ int xe_gt_tlb_invalidation_ggtt(struct xe_gt *gt)
>
> xe_gt_tlb_invalidation_fence_wait(&fence);
> } else if (xe_device_uc_enabled(xe) && !xe_device_wedged(xe)) {
> + struct xe_mmio *mmio = >->mmio;
> +
> if (IS_SRIOV_VF(xe))
> return 0;
>
> xe_gt_WARN_ON(gt, xe_force_wake_get(gt_to_fw(gt), XE_FW_GT));
> if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20) {
> - xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1,
> + xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC1,
> PVC_GUC_TLB_INV_DESC1_INVALIDATE);
> - xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0,
> + xe_mmio_write32(mmio, PVC_GUC_TLB_INV_DESC0,
> PVC_GUC_TLB_INV_DESC0_VALID);
> } else {
> - xe_mmio_write32(gt, GUC_TLB_INV_CR,
> + xe_mmio_write32(mmio, GUC_TLB_INV_CR,
> GUC_TLB_INV_CR_INVALIDATE);
> }
> xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 39/43] drm/xe/gt_idle: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (37 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 38/43] drm/xe/tlb: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:12 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 40/43] drm/xe/forcewake: " Matt Roper
` (11 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt_idle.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
index 85a35ed153a3..531924b6c0a1 100644
--- a/drivers/gpu/drm/xe/xe_gt_idle.c
+++ b/drivers/gpu/drm/xe/xe_gt_idle.c
@@ -104,6 +104,7 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
struct xe_gt_idle *gtidle = >->gtidle;
+ struct xe_mmio *mmio = >->mmio;
u32 vcs_mask, vecs_mask;
int i, j;
@@ -137,11 +138,11 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
* GuC sets the hysteresis value when GuC PC is enabled
* else set it to 25 (25 * 1.28us)
*/
- xe_mmio_write32(gt, MEDIA_POWERGATE_IDLE_HYSTERESIS, 25);
- xe_mmio_write32(gt, RENDER_POWERGATE_IDLE_HYSTERESIS, 25);
+ xe_mmio_write32(mmio, MEDIA_POWERGATE_IDLE_HYSTERESIS, 25);
+ xe_mmio_write32(mmio, RENDER_POWERGATE_IDLE_HYSTERESIS, 25);
}
- xe_mmio_write32(gt, POWERGATE_ENABLE, gtidle->powergate_enable);
+ xe_mmio_write32(mmio, POWERGATE_ENABLE, gtidle->powergate_enable);
XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FW_GT));
}
@@ -156,7 +157,7 @@ void xe_gt_idle_disable_pg(struct xe_gt *gt)
gtidle->powergate_enable = 0;
XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FW_GT));
- xe_mmio_write32(gt, POWERGATE_ENABLE, gtidle->powergate_enable);
+ xe_mmio_write32(>->mmio, POWERGATE_ENABLE, gtidle->powergate_enable);
XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FW_GT));
}
@@ -216,8 +217,8 @@ int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p)
if (err)
return err;
- pg_enabled = xe_mmio_read32(gt, POWERGATE_ENABLE);
- pg_status = xe_mmio_read32(gt, POWERGATE_DOMAIN_STATUS);
+ pg_enabled = xe_mmio_read32(>->mmio, POWERGATE_ENABLE);
+ pg_status = xe_mmio_read32(>->mmio, POWERGATE_DOMAIN_STATUS);
XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FW_GT));
}
@@ -361,9 +362,9 @@ void xe_gt_idle_enable_c6(struct xe_gt *gt)
return;
/* Units of 1280 ns for a total of 5s */
- xe_mmio_write32(gt, RC_IDLE_HYSTERSIS, 0x3B9ACA);
+ xe_mmio_write32(>->mmio, RC_IDLE_HYSTERSIS, 0x3B9ACA);
/* Enable RC6 */
- xe_mmio_write32(gt, RC_CONTROL,
+ xe_mmio_write32(>->mmio, RC_CONTROL,
RC_CTL_HW_ENABLE | RC_CTL_TO_MODE | RC_CTL_RC6_ENABLE);
}
@@ -375,6 +376,6 @@ void xe_gt_idle_disable_c6(struct xe_gt *gt)
if (IS_SRIOV_VF(gt_to_xe(gt)))
return;
- xe_mmio_write32(gt, RC_CONTROL, 0);
- xe_mmio_write32(gt, RC_STATE, 0);
+ xe_mmio_write32(>->mmio, RC_CONTROL, 0);
+ xe_mmio_write32(>->mmio, RC_STATE, 0);
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 39/43] drm/xe/gt_idle: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 39/43] drm/xe/gt_idle: " Matt Roper
@ 2024-09-10 18:12 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:12 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:28PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt_idle.c | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
> index 85a35ed153a3..531924b6c0a1 100644
> --- a/drivers/gpu/drm/xe/xe_gt_idle.c
> +++ b/drivers/gpu/drm/xe/xe_gt_idle.c
> @@ -104,6 +104,7 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
> {
> struct xe_device *xe = gt_to_xe(gt);
> struct xe_gt_idle *gtidle = >->gtidle;
> + struct xe_mmio *mmio = >->mmio;
> u32 vcs_mask, vecs_mask;
> int i, j;
>
> @@ -137,11 +138,11 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
> * GuC sets the hysteresis value when GuC PC is enabled
> * else set it to 25 (25 * 1.28us)
> */
> - xe_mmio_write32(gt, MEDIA_POWERGATE_IDLE_HYSTERESIS, 25);
> - xe_mmio_write32(gt, RENDER_POWERGATE_IDLE_HYSTERESIS, 25);
> + xe_mmio_write32(mmio, MEDIA_POWERGATE_IDLE_HYSTERESIS, 25);
> + xe_mmio_write32(mmio, RENDER_POWERGATE_IDLE_HYSTERESIS, 25);
> }
>
> - xe_mmio_write32(gt, POWERGATE_ENABLE, gtidle->powergate_enable);
> + xe_mmio_write32(mmio, POWERGATE_ENABLE, gtidle->powergate_enable);
3+ looks your threashold indeed :)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FW_GT));
> }
>
> @@ -156,7 +157,7 @@ void xe_gt_idle_disable_pg(struct xe_gt *gt)
> gtidle->powergate_enable = 0;
>
> XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FW_GT));
> - xe_mmio_write32(gt, POWERGATE_ENABLE, gtidle->powergate_enable);
> + xe_mmio_write32(>->mmio, POWERGATE_ENABLE, gtidle->powergate_enable);
> XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FW_GT));
> }
>
> @@ -216,8 +217,8 @@ int xe_gt_idle_pg_print(struct xe_gt *gt, struct drm_printer *p)
> if (err)
> return err;
>
> - pg_enabled = xe_mmio_read32(gt, POWERGATE_ENABLE);
> - pg_status = xe_mmio_read32(gt, POWERGATE_DOMAIN_STATUS);
> + pg_enabled = xe_mmio_read32(>->mmio, POWERGATE_ENABLE);
> + pg_status = xe_mmio_read32(>->mmio, POWERGATE_DOMAIN_STATUS);
>
> XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FW_GT));
> }
> @@ -361,9 +362,9 @@ void xe_gt_idle_enable_c6(struct xe_gt *gt)
> return;
>
> /* Units of 1280 ns for a total of 5s */
> - xe_mmio_write32(gt, RC_IDLE_HYSTERSIS, 0x3B9ACA);
> + xe_mmio_write32(>->mmio, RC_IDLE_HYSTERSIS, 0x3B9ACA);
> /* Enable RC6 */
> - xe_mmio_write32(gt, RC_CONTROL,
> + xe_mmio_write32(>->mmio, RC_CONTROL,
> RC_CTL_HW_ENABLE | RC_CTL_TO_MODE | RC_CTL_RC6_ENABLE);
> }
>
> @@ -375,6 +376,6 @@ void xe_gt_idle_disable_c6(struct xe_gt *gt)
> if (IS_SRIOV_VF(gt_to_xe(gt)))
> return;
>
> - xe_mmio_write32(gt, RC_CONTROL, 0);
> - xe_mmio_write32(gt, RC_STATE, 0);
> + xe_mmio_write32(>->mmio, RC_CONTROL, 0);
> + xe_mmio_write32(>->mmio, RC_STATE, 0);
> }
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 40/43] drm/xe/forcewake: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (38 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 39/43] drm/xe/gt_idle: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:42 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 41/43] drm/xe/ggtt: " Matt Roper
` (10 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_force_wake.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
index b263fff15273..a64c14757c84 100644
--- a/drivers/gpu/drm/xe/xe_force_wake.c
+++ b/drivers/gpu/drm/xe/xe_force_wake.c
@@ -100,7 +100,7 @@ static void __domain_ctl(struct xe_gt *gt, struct xe_force_wake_domain *domain,
if (IS_SRIOV_VF(gt_to_xe(gt)))
return;
- xe_mmio_write32(gt, domain->reg_ctl, domain->mask | (wake ? domain->val : 0));
+ xe_mmio_write32(>->mmio, domain->reg_ctl, domain->mask | (wake ? domain->val : 0));
}
static int __domain_wait(struct xe_gt *gt, struct xe_force_wake_domain *domain, bool wake)
@@ -111,7 +111,7 @@ static int __domain_wait(struct xe_gt *gt, struct xe_force_wake_domain *domain,
if (IS_SRIOV_VF(gt_to_xe(gt)))
return 0;
- ret = xe_mmio_wait32(gt, domain->reg_ack, domain->val, wake ? domain->val : 0,
+ ret = xe_mmio_wait32(>->mmio, domain->reg_ack, domain->val, wake ? domain->val : 0,
XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
&value, true);
if (ret)
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 40/43] drm/xe/forcewake: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 40/43] drm/xe/forcewake: " Matt Roper
@ 2024-09-10 18:42 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:42 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:29PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_force_wake.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_force_wake.c b/drivers/gpu/drm/xe/xe_force_wake.c
> index b263fff15273..a64c14757c84 100644
> --- a/drivers/gpu/drm/xe/xe_force_wake.c
> +++ b/drivers/gpu/drm/xe/xe_force_wake.c
> @@ -100,7 +100,7 @@ static void __domain_ctl(struct xe_gt *gt, struct xe_force_wake_domain *domain,
> if (IS_SRIOV_VF(gt_to_xe(gt)))
> return;
>
> - xe_mmio_write32(gt, domain->reg_ctl, domain->mask | (wake ? domain->val : 0));
> + xe_mmio_write32(>->mmio, domain->reg_ctl, domain->mask | (wake ? domain->val : 0));
> }
>
> static int __domain_wait(struct xe_gt *gt, struct xe_force_wake_domain *domain, bool wake)
> @@ -111,7 +111,7 @@ static int __domain_wait(struct xe_gt *gt, struct xe_force_wake_domain *domain,
> if (IS_SRIOV_VF(gt_to_xe(gt)))
> return 0;
>
> - ret = xe_mmio_wait32(gt, domain->reg_ack, domain->val, wake ? domain->val : 0,
> + ret = xe_mmio_wait32(>->mmio, domain->reg_ack, domain->val, wake ? domain->val : 0,
> XE_FORCE_WAKE_ACK_TIMEOUT_MS * USEC_PER_MSEC,
> &value, true);
> if (ret)
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 41/43] drm/xe/ggtt: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (39 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 40/43] drm/xe/forcewake: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:09 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 42/43] drm/xe/ccs_mode: " Matt Roper
` (9 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_ggtt.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index f3fca5565d32..0f4e778a7663 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -107,8 +107,10 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev)
static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
{
- struct xe_gt *gt = XE_WA(ggtt->tile->primary_gt, 22019338487) ? ggtt->tile->primary_gt :
- ggtt->tile->media_gt;
+ struct xe_tile *tile = ggtt->tile;
+ struct xe_gt *affected_gt = XE_WA(tile->primary_gt, 22019338487) ?
+ tile->primary_gt : tile->media_gt;
+ struct xe_mmio *mmio = &affected_gt->mmio;
u32 max_gtt_writes = XE_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63;
/*
* Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit
@@ -118,7 +120,7 @@ static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
lockdep_assert_held(&ggtt->lock);
if ((++ggtt->access_count % max_gtt_writes) == 0) {
- xe_mmio_write32(gt, GMD_ID, 0x0);
+ xe_mmio_write32(mmio, GMD_ID, 0x0);
ggtt->access_count = 0;
}
}
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 41/43] drm/xe/ggtt: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 41/43] drm/xe/ggtt: " Matt Roper
@ 2024-09-10 18:09 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:09 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:30PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_ggtt.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index f3fca5565d32..0f4e778a7663 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -107,8 +107,10 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev)
>
> static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
> {
> - struct xe_gt *gt = XE_WA(ggtt->tile->primary_gt, 22019338487) ? ggtt->tile->primary_gt :
> - ggtt->tile->media_gt;
> + struct xe_tile *tile = ggtt->tile;
> + struct xe_gt *affected_gt = XE_WA(tile->primary_gt, 22019338487) ?
> + tile->primary_gt : tile->media_gt;
> + struct xe_mmio *mmio = &affected_gt->mmio;
> u32 max_gtt_writes = XE_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63;
> /*
> * Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit
> @@ -118,7 +120,7 @@ static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
> lockdep_assert_held(&ggtt->lock);
>
> if ((++ggtt->access_count % max_gtt_writes) == 0) {
> - xe_mmio_write32(gt, GMD_ID, 0x0);
> + xe_mmio_write32(mmio, GMD_ID, 0x0);
> ggtt->access_count = 0;
> }
> }
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 42/43] drm/xe/ccs_mode: Convert register access to use xe_mmio
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (40 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 41/43] drm/xe/ggtt: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-10 18:46 ` Rodrigo Vivi
2024-09-07 0:08 ` [PATCH v2 43/43] drm/xe/mmio: Drop compatibility macros Matt Roper
` (8 subsequent siblings)
50 siblings, 1 reply; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Stop using GT pointers for register access.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_gt_ccs_mode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
index d2e4dc3aaf61..9360ac4de489 100644
--- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
+++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
@@ -68,7 +68,7 @@ static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)
}
}
- xe_mmio_write32(gt, CCS_MODE, mode);
+ xe_mmio_write32(>->mmio, CCS_MODE, mode);
xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
mode, config, num_engines, num_slices);
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* Re: [PATCH v2 42/43] drm/xe/ccs_mode: Convert register access to use xe_mmio
2024-09-07 0:08 ` [PATCH v2 42/43] drm/xe/ccs_mode: " Matt Roper
@ 2024-09-10 18:46 ` Rodrigo Vivi
0 siblings, 0 replies; 83+ messages in thread
From: Rodrigo Vivi @ 2024-09-10 18:46 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
On Fri, Sep 06, 2024 at 05:08:31PM -0700, Matt Roper wrote:
> Stop using GT pointers for register access.
>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt_ccs_mode.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
> index d2e4dc3aaf61..9360ac4de489 100644
> --- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
> +++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
> @@ -68,7 +68,7 @@ static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)
> }
> }
>
> - xe_mmio_write32(gt, CCS_MODE, mode);
> + xe_mmio_write32(>->mmio, CCS_MODE, mode);
>
> xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
> mode, config, num_engines, num_slices);
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 83+ messages in thread
* [PATCH v2 43/43] drm/xe/mmio: Drop compatibility macros
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (41 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 42/43] drm/xe/ccs_mode: " Matt Roper
@ 2024-09-07 0:08 ` Matt Roper
2024-09-07 3:10 ` ✓ CI.Patch_applied: success for Stop using xe_gt as a register MMIO target (rev2) Patchwork
` (7 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-07 0:08 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper
Now that all parts of the driver have switched over to using xe_mmio for
direct register access, we can drop the compatibility macros that allow
continued xe_gt usage.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_mmio.c | 30 ++++++++++-----------
drivers/gpu/drm/xe/xe_mmio.h | 52 +++++++-----------------------------
2 files changed, 25 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index ccf53a7840d9..160307e3a2a4 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -228,7 +228,7 @@ u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg)
return val;
}
-void __xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val)
+void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val)
{
u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
@@ -240,7 +240,7 @@ void __xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val)
writel(val, mmio->regs + addr);
}
-u32 __xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg)
+u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg)
{
u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
u32 val;
@@ -258,7 +258,7 @@ u32 __xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg)
return val;
}
-u32 __xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set)
+u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set)
{
u32 old, reg_val;
@@ -269,8 +269,8 @@ u32 __xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set)
return old;
}
-int __xe_mmio_write32_and_verify(struct xe_mmio *mmio,
- struct xe_reg reg, u32 val, u32 mask, u32 eval)
+int xe_mmio_write32_and_verify(struct xe_mmio *mmio,
+ struct xe_reg reg, u32 val, u32 mask, u32 eval)
{
u32 reg_val;
@@ -280,9 +280,9 @@ int __xe_mmio_write32_and_verify(struct xe_mmio *mmio,
return (reg_val & mask) != eval ? -EINVAL : 0;
}
-bool __xe_mmio_in_range(const struct xe_mmio *mmio,
- const struct xe_mmio_range *range,
- struct xe_reg reg)
+bool xe_mmio_in_range(const struct xe_mmio *mmio,
+ const struct xe_mmio_range *range,
+ struct xe_reg reg)
{
u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
@@ -311,7 +311,7 @@ bool __xe_mmio_in_range(const struct xe_mmio *mmio,
*
* Returns the value of the 64-bit register.
*/
-u64 __xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg)
+u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg)
{
struct xe_reg reg_udw = { .addr = reg.addr + 0x4 };
u32 ldw, udw, oldudw, retries;
@@ -339,8 +339,8 @@ u64 __xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg)
return (u64)udw << 32 | ldw;
}
-static int ____xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
- u32 *out_val, bool atomic, bool expect_match)
+static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
+ u32 *out_val, bool atomic, bool expect_match)
{
ktime_t cur = ktime_get_raw();
const ktime_t end = ktime_add_us(cur, timeout_us);
@@ -411,10 +411,10 @@ static int ____xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,
* @timeout_us for different reasons, specially in non-atomic contexts. Thus,
* it is possible that this function succeeds even after @timeout_us has passed.
*/
-int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
- u32 *out_val, bool atomic)
+int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
+ u32 *out_val, bool atomic)
{
- return ____xe_mmio_wait32(mmio, reg, mask, val, timeout_us, out_val, atomic, true);
+ return __xe_mmio_wait32(mmio, reg, mask, val, timeout_us, out_val, atomic, true);
}
/**
@@ -433,5 +433,5 @@ int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
u32 *out_val, bool atomic)
{
- return ____xe_mmio_wait32(mmio, reg, mask, val, timeout_us, out_val, atomic, false);
+ return __xe_mmio_wait32(mmio, reg, mask, val, timeout_us, out_val, atomic, false);
}
diff --git a/drivers/gpu/drm/xe/xe_mmio.h b/drivers/gpu/drm/xe/xe_mmio.h
index 2e97dc811d82..8a46f4006a84 100644
--- a/drivers/gpu/drm/xe/xe_mmio.h
+++ b/drivers/gpu/drm/xe/xe_mmio.h
@@ -14,58 +14,26 @@ struct xe_reg;
int xe_mmio_init(struct xe_device *xe);
int xe_mmio_probe_tiles(struct xe_device *xe);
-/*
- * Temporary transition helper for xe_gt -> xe_mmio conversion. Allows
- * continued usage of xe_gt as a parameter to MMIO operations which now
- * take an xe_mmio structure instead. Will be removed once the driver-wide
- * conversion is complete.
- */
-#define __to_xe_mmio(ptr) \
- _Generic(ptr, \
- const struct xe_gt *: (&((const struct xe_gt *)(ptr))->mmio), \
- struct xe_gt *: (&((struct xe_gt *)(ptr))->mmio), \
- const struct xe_mmio *: (ptr), \
- struct xe_mmio *: (ptr))
-
u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);
u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);
-
-void __xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);
-#define xe_mmio_write32(p, reg, val) __xe_mmio_write32(__to_xe_mmio(p), reg, val)
-
-u32 __xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg);
-#define xe_mmio_read32(p, reg) __xe_mmio_read32(__to_xe_mmio(p), reg)
-
-u32 __xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set);
-#define xe_mmio_rmw32(p, reg, clr, set) __xe_mmio_rmw32(__to_xe_mmio(p), reg, clr, set)
-
-int __xe_mmio_write32_and_verify(struct xe_mmio *mmio, struct xe_reg reg,
- u32 val, u32 mask, u32 eval);
-#define xe_mmio_write32_and_verify(p, reg, val, mask, eval) \
- __xe_mmio_write32_and_verify(__to_xe_mmio(p), reg, val, mask, eval)
-
-bool __xe_mmio_in_range(const struct xe_mmio *mmio,
- const struct xe_mmio_range *range, struct xe_reg reg);
-#define xe_mmio_in_range(p, range, reg) __xe_mmio_in_range(__to_xe_mmio(p), range, reg)
-
-u64 __xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg);
-#define xe_mmio_read64_2x32(p, reg) __xe_mmio_read64_2x32(__to_xe_mmio(p), reg)
-
-int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
- u32 timeout_us, u32 *out_val, bool atomic);
-#define xe_mmio_wait32(p, reg, mask, val, timeout_us, out_val, atomic) \
- __xe_mmio_wait32(__to_xe_mmio(p), reg, mask, val, timeout_us, out_val, atomic)
-
+void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);
+u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg);
+u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set);
+int xe_mmio_write32_and_verify(struct xe_mmio *mmio, struct xe_reg reg, u32 val, u32 mask, u32 eval);
+bool xe_mmio_in_range(const struct xe_mmio *mmio, const struct xe_mmio_range *range, struct xe_reg reg);
+
+u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg);
+int xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
+ u32 timeout_us, u32 *out_val, bool atomic);
int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,
u32 val, u32 timeout_us, u32 *out_val, bool atomic);
-static inline u32 __xe_mmio_adjusted_addr(const struct xe_mmio *mmio, u32 addr)
+static inline u32 xe_mmio_adjusted_addr(const struct xe_mmio *mmio, u32 addr)
{
if (addr < mmio->adj_limit)
addr += mmio->adj_offset;
return addr;
}
-#define xe_mmio_adjusted_addr(p, addr) __xe_mmio_adjusted_addr(__to_xe_mmio(p), addr)
static inline struct xe_mmio *xe_root_tile_mmio(struct xe_device *xe)
{
--
2.45.2
^ permalink raw reply related [flat|nested] 83+ messages in thread* ✓ CI.Patch_applied: success for Stop using xe_gt as a register MMIO target (rev2)
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (42 preceding siblings ...)
2024-09-07 0:08 ` [PATCH v2 43/43] drm/xe/mmio: Drop compatibility macros Matt Roper
@ 2024-09-07 3:10 ` Patchwork
2024-09-07 3:11 ` ✗ CI.checkpatch: warning " Patchwork
` (6 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Patchwork @ 2024-09-07 3:10 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Stop using xe_gt as a register MMIO target (rev2)
URL : https://patchwork.freedesktop.org/series/138168/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 217031ad4c96 drm-tip: 2024y-09m-06d-19h-01m-03s UTC integration manifest
=== git am output follows ===
Applying: drm/xe: Move forcewake to 'gt.pm' substructure
Applying: drm/xe: Create dedicated xe_mmio structure
Applying: drm/xe: Clarify size of MMIO region
Applying: drm/xe: Move GSI offset adjustment fields into 'struct xe_mmio'
Applying: drm/xe: Populate GT's mmio iomap from tile during init
Applying: drm/xe: Switch mmio_ext to use 'struct xe_mmio'
Applying: drm/xe: Add xe_tile backpointer to xe_mmio
Applying: drm/xe: Adjust mmio code to pass VF substructure to SRIOV code
Applying: drm/xe: Switch MMIO interface to take xe_mmio instead of xe_gt
Applying: drm/xe/irq: Convert register access to use xe_mmio
Applying: drm/xe/pcode: Convert register access to use xe_mmio
Applying: drm/xe/hwmon: Convert register access to use xe_mmio
Applying: drm/xe/vram: Convert register access to use xe_mmio
Applying: drm/xe/compat-i915: Convert register access to use xe_mmio
Applying: drm/xe/lmtt: Convert register access to use xe_mmio
Applying: drm/xe/stolen: Convert register access to use xe_mmio
Applying: drm/xe/device: Convert register access to use xe_mmio
Applying: drm/xe/pci: Convert register access to use xe_mmio
Applying: drm/xe/wa: Convert register access to use xe_mmio
Applying: drm/xe/uc: Convert register access to use xe_mmio
Applying: drm/xe/guc: Convert register access to use xe_mmio
Applying: drm/xe/huc: Convert register access to use xe_mmio
Applying: drm/xe/gsc: Convert register access to use xe_mmio
Applying: drm/xe/query: Convert register access to use xe_mmio
Applying: drm/xe/mcr: Convert register access to use xe_mmio
Applying: drm/xe/mocs: Convert register access to use xe_mmio
Applying: drm/xe/hw_engine: Convert register access to use xe_mmio
Applying: drm/xe/gt_throttle: Convert register access to use xe_mmio
Applying: drm/xe/pat: Convert register access to use xe_mmio
Applying: drm/xe/wopcm: Convert register access to use xe_mmio
Applying: drm/xe/oa: Convert register access to use xe_mmio
Applying: drm/xe/topology: Convert register access to use xe_mmio
Applying: drm/xe/execlist: Convert register access to use xe_mmio
Applying: drm/xe/gt_clock: Convert register access to use xe_mmio
Applying: drm/xe/reg_sr: Convert register access to use xe_mmio
Applying: drm/xe/gt: Convert register access to use xe_mmio
Applying: drm/xe/sriov: Convert register access to use xe_mmio
Applying: drm/xe/tlb: Convert register access to use xe_mmio
Applying: drm/xe/gt_idle: Convert register access to use xe_mmio
Applying: drm/xe/forcewake: Convert register access to use xe_mmio
Applying: drm/xe/ggtt: Convert register access to use xe_mmio
Applying: drm/xe/ccs_mode: Convert register access to use xe_mmio
Applying: drm/xe/mmio: Drop compatibility macros
^ permalink raw reply [flat|nested] 83+ messages in thread* ✗ CI.checkpatch: warning for Stop using xe_gt as a register MMIO target (rev2)
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (43 preceding siblings ...)
2024-09-07 3:10 ` ✓ CI.Patch_applied: success for Stop using xe_gt as a register MMIO target (rev2) Patchwork
@ 2024-09-07 3:11 ` Patchwork
2024-09-07 3:12 ` ✓ CI.KUnit: success " Patchwork
` (5 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Patchwork @ 2024-09-07 3:11 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Stop using xe_gt as a register MMIO target (rev2)
URL : https://patchwork.freedesktop.org/series/138168/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c62d7e164862503a3662a095da1c6c9014248cb2
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit dc6f3ec49aa87a3dcd1243a98ae162ab6e44bd1f
Author: Matt Roper <matthew.d.roper@intel.com>
Date: Fri Sep 6 17:08:32 2024 -0700
drm/xe/mmio: Drop compatibility macros
Now that all parts of the driver have switched over to using xe_mmio for
direct register access, we can drop the compatibility macros that allow
continued xe_gt usage.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
+ /mt/dim checkpatch 217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a drm-intel
f5943b2e1ec6 drm/xe: Move forcewake to 'gt.pm' substructure
b4acc7906286 drm/xe: Create dedicated xe_mmio structure
f4911fd6b14e drm/xe: Clarify size of MMIO region
e6536b27f2f4 drm/xe: Move GSI offset adjustment fields into 'struct xe_mmio'
0ebcf99c15e1 drm/xe: Populate GT's mmio iomap from tile during init
4003e81bb59e drm/xe: Switch mmio_ext to use 'struct xe_mmio'
aedb4330605a drm/xe: Add xe_tile backpointer to xe_mmio
8c18ef6f292e drm/xe: Adjust mmio code to pass VF substructure to SRIOV code
7cd043adb66e drm/xe: Switch MMIO interface to take xe_mmio instead of xe_gt
-:242: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#242: FILE: drivers/gpu/drm/xe/xe_mmio.c:342:
+static int ____xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
-:335: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ptr' - possible side-effects?
#335: FILE: drivers/gpu/drm/xe/xe_mmio.h:23:
+#define __to_xe_mmio(ptr) \
+ _Generic(ptr, \
+ const struct xe_gt *: (&((const struct xe_gt *)(ptr))->mmio), \
+ struct xe_gt *: (&((struct xe_gt *)(ptr))->mmio), \
+ const struct xe_mmio *: (ptr), \
+ struct xe_mmio *: (ptr))
-:336: CHECK:CAMELCASE: Avoid CamelCase: <_Generic>
#336: FILE: drivers/gpu/drm/xe/xe_mmio.h:24:
+ _Generic(ptr, \
-:337: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#337: FILE: drivers/gpu/drm/xe/xe_mmio.h:25:
+ const struct xe_gt *: (&((const struct xe_gt *)(ptr))->mmio), \
^
-:337: ERROR:SPACING: spaces required around that ':' (ctx:OxW)
#337: FILE: drivers/gpu/drm/xe/xe_mmio.h:25:
+ const struct xe_gt *: (&((const struct xe_gt *)(ptr))->mmio), \
^
-:338: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#338: FILE: drivers/gpu/drm/xe/xe_mmio.h:26:
+ struct xe_gt *: (&((struct xe_gt *)(ptr))->mmio), \
^
-:338: ERROR:SPACING: spaces required around that ':' (ctx:OxW)
#338: FILE: drivers/gpu/drm/xe/xe_mmio.h:26:
+ struct xe_gt *: (&((struct xe_gt *)(ptr))->mmio), \
^
-:339: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#339: FILE: drivers/gpu/drm/xe/xe_mmio.h:27:
+ const struct xe_mmio *: (ptr), \
^
-:339: ERROR:SPACING: spaces required around that ':' (ctx:OxW)
#339: FILE: drivers/gpu/drm/xe/xe_mmio.h:27:
+ const struct xe_mmio *: (ptr), \
^
-:340: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#340: FILE: drivers/gpu/drm/xe/xe_mmio.h:28:
+ struct xe_mmio *: (ptr))
^
-:340: ERROR:SPACING: spaces required around that ':' (ctx:OxW)
#340: FILE: drivers/gpu/drm/xe/xe_mmio.h:28:
+ struct xe_mmio *: (ptr))
^
-:387: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#387: FILE: drivers/gpu/drm/xe/xe_mmio.h:73:
}
+#define xe_mmio_adjusted_addr(p, addr) __xe_mmio_adjusted_addr(__to_xe_mmio(p), addr)
total: 4 errors, 1 warnings, 7 checks, 380 lines checked
eb51ba76caa3 drm/xe/irq: Convert register access to use xe_mmio
700294e56143 drm/xe/pcode: Convert register access to use xe_mmio
e41d3621357f drm/xe/hwmon: Convert register access to use xe_mmio
26f3b723eaa9 drm/xe/vram: Convert register access to use xe_mmio
d5dcc2998be4 drm/xe/compat-i915: Convert register access to use xe_mmio
3d043c7eb7d6 drm/xe/lmtt: Convert register access to use xe_mmio
b9c788acc546 drm/xe/stolen: Convert register access to use xe_mmio
520c1ec26549 drm/xe/device: Convert register access to use xe_mmio
f8f1011cb479 drm/xe/pci: Convert register access to use xe_mmio
64d82a48e5e7 drm/xe/wa: Convert register access to use xe_mmio
ec9a95cd3975 drm/xe/uc: Convert register access to use xe_mmio
abca56bfd30f drm/xe/guc: Convert register access to use xe_mmio
93bda7241eab drm/xe/huc: Convert register access to use xe_mmio
7018a2a6491b drm/xe/gsc: Convert register access to use xe_mmio
e02a50152648 drm/xe/query: Convert register access to use xe_mmio
cf644728a467 drm/xe/mcr: Convert register access to use xe_mmio
1bbb6193d53f drm/xe/mocs: Convert register access to use xe_mmio
32ed396db578 drm/xe/hw_engine: Convert register access to use xe_mmio
0b543d36ed30 drm/xe/gt_throttle: Convert register access to use xe_mmio
cf3c1e738fd9 drm/xe/pat: Convert register access to use xe_mmio
7a562cfc9579 drm/xe/wopcm: Convert register access to use xe_mmio
625fa127d310 drm/xe/oa: Convert register access to use xe_mmio
e81581bbf2df drm/xe/topology: Convert register access to use xe_mmio
03b6fee2be5e drm/xe/execlist: Convert register access to use xe_mmio
53552030ed7a drm/xe/gt_clock: Convert register access to use xe_mmio
40612a14647e drm/xe/reg_sr: Convert register access to use xe_mmio
bba564c07335 drm/xe/gt: Convert register access to use xe_mmio
4de0b4a652ce drm/xe/sriov: Convert register access to use xe_mmio
2bbe34d9df64 drm/xe/tlb: Convert register access to use xe_mmio
436e8eba7a2f drm/xe/gt_idle: Convert register access to use xe_mmio
bf0b68b9d2c2 drm/xe/forcewake: Convert register access to use xe_mmio
2437ed061c01 drm/xe/ggtt: Convert register access to use xe_mmio
4919f3e65796 drm/xe/ccs_mode: Convert register access to use xe_mmio
dc6f3ec49aa8 drm/xe/mmio: Drop compatibility macros
-:82: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#82: FILE: drivers/gpu/drm/xe/xe_mmio.c:342:
+static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
-:161: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#161: FILE: drivers/gpu/drm/xe/xe_mmio.h:22:
+int xe_mmio_write32_and_verify(struct xe_mmio *mmio, struct xe_reg reg, u32 val, u32 mask, u32 eval);
-:162: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#162: FILE: drivers/gpu/drm/xe/xe_mmio.h:23:
+bool xe_mmio_in_range(const struct xe_mmio *mmio, const struct xe_mmio_range *range, struct xe_reg reg);
total: 0 errors, 3 warnings, 0 checks, 151 lines checked
^ permalink raw reply [flat|nested] 83+ messages in thread* ✓ CI.KUnit: success for Stop using xe_gt as a register MMIO target (rev2)
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (44 preceding siblings ...)
2024-09-07 3:11 ` ✗ CI.checkpatch: warning " Patchwork
@ 2024-09-07 3:12 ` Patchwork
2024-09-07 3:26 ` ✓ CI.Build: " Patchwork
` (4 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Patchwork @ 2024-09-07 3:12 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Stop using xe_gt as a register MMIO target (rev2)
URL : https://patchwork.freedesktop.org/series/138168/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[03:11:23] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:11:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
156 | u64 ioread64_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
163 | u64 ioread64_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
170 | u64 ioread64be_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
178 | u64 ioread64be_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
[03:11:53] Starting KUnit Kernel (1/1)...
[03:11:53] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:11:54] =================== guc_dbm (7 subtests) ===================
[03:11:54] [PASSED] test_empty
[03:11:54] [PASSED] test_default
[03:11:54] ======================== test_size ========================
[03:11:54] [PASSED] 4
[03:11:54] [PASSED] 8
[03:11:54] [PASSED] 32
[03:11:54] [PASSED] 256
[03:11:54] ==================== [PASSED] test_size ====================
[03:11:54] ======================= test_reuse ========================
[03:11:54] [PASSED] 4
[03:11:54] [PASSED] 8
[03:11:54] [PASSED] 32
[03:11:54] [PASSED] 256
[03:11:54] =================== [PASSED] test_reuse ====================
[03:11:54] =================== test_range_overlap ====================
[03:11:54] [PASSED] 4
[03:11:54] [PASSED] 8
[03:11:54] [PASSED] 32
[03:11:54] [PASSED] 256
[03:11:54] =============== [PASSED] test_range_overlap ================
[03:11:54] =================== test_range_compact ====================
[03:11:54] [PASSED] 4
[03:11:54] [PASSED] 8
[03:11:54] [PASSED] 32
[03:11:54] [PASSED] 256
[03:11:54] =============== [PASSED] test_range_compact ================
[03:11:54] ==================== test_range_spare =====================
[03:11:54] [PASSED] 4
[03:11:54] [PASSED] 8
[03:11:54] [PASSED] 32
[03:11:54] [PASSED] 256
[03:11:54] ================ [PASSED] test_range_spare =================
[03:11:54] ===================== [PASSED] guc_dbm =====================
[03:11:54] =================== guc_idm (6 subtests) ===================
[03:11:54] [PASSED] bad_init
[03:11:54] [PASSED] no_init
[03:11:54] [PASSED] init_fini
[03:11:54] [PASSED] check_used
[03:11:54] [PASSED] check_quota
[03:11:54] [PASSED] check_all
[03:11:54] ===================== [PASSED] guc_idm =====================
[03:11:54] ================== no_relay (3 subtests) ===================
[03:11:54] [PASSED] xe_drops_guc2pf_if_not_ready
[03:11:54] [PASSED] xe_drops_guc2vf_if_not_ready
[03:11:54] [PASSED] xe_rejects_send_if_not_ready
[03:11:54] ==================== [PASSED] no_relay =====================
[03:11:54] ================== pf_relay (14 subtests) ==================
[03:11:54] [PASSED] pf_rejects_guc2pf_too_short
[03:11:54] [PASSED] pf_rejects_guc2pf_too_long
[03:11:54] [PASSED] pf_rejects_guc2pf_no_payload
[03:11:54] [PASSED] pf_fails_no_payload
[03:11:54] [PASSED] pf_fails_bad_origin
[03:11:54] [PASSED] pf_fails_bad_type
[03:11:54] [PASSED] pf_txn_reports_error
[03:11:54] [PASSED] pf_txn_sends_pf2guc
[03:11:54] [PASSED] pf_sends_pf2guc
[03:11:54] [SKIPPED] pf_loopback_nop
[03:11:54] [SKIPPED] pf_loopback_echo
[03:11:54] [SKIPPED] pf_loopback_fail
[03:11:54] [SKIPPED] pf_loopback_busy
[03:11:54] [SKIPPED] pf_loopback_retry
[03:11:54] ==================== [PASSED] pf_relay =====================
[03:11:54] ================== vf_relay (3 subtests) ===================
[03:11:54] [PASSED] vf_rejects_guc2vf_too_short
[03:11:54] [PASSED] vf_rejects_guc2vf_too_long
[03:11:54] [PASSED] vf_rejects_guc2vf_no_payload
[03:11:54] ==================== [PASSED] vf_relay =====================
[03:11:54] ================= pf_service (11 subtests) =================
[03:11:54] [PASSED] pf_negotiate_any
[03:11:54] [PASSED] pf_negotiate_base_match
[03:11:54] [PASSED] pf_negotiate_base_newer
[03:11:54] [PASSED] pf_negotiate_base_next
[03:11:54] [SKIPPED] pf_negotiate_base_older
[03:11:54] [PASSED] pf_negotiate_base_prev
[03:11:54] [PASSED] pf_negotiate_latest_match
[03:11:54] [PASSED] pf_negotiate_latest_newer
[03:11:54] [PASSED] pf_negotiate_latest_next
[03:11:54] [SKIPPED] pf_negotiate_latest_older
[03:11:54] [SKIPPED] pf_negotiate_latest_prev
[03:11:54] =================== [PASSED] pf_service ====================
[03:11:54] ===================== lmtt (1 subtest) =====================
[03:11:54] ======================== test_ops =========================
[03:11:54] [PASSED] 2-level
[03:11:54] [PASSED] multi-level
[03:11:54] ==================== [PASSED] test_ops =====================
[03:11:54] ====================== [PASSED] lmtt =======================
[03:11:54] =================== xe_mocs (2 subtests) ===================
[03:11:54] ================ xe_live_mocs_kernel_kunit ================
[03:11:54] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[03:11:54] ================ xe_live_mocs_reset_kunit =================
[03:11:54] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[03:11:54] ==================== [SKIPPED] xe_mocs =====================
[03:11:54] ================= xe_migrate (2 subtests) ==================
[03:11:54] ================= xe_migrate_sanity_kunit =================
[03:11:54] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[03:11:54] ================== xe_validate_ccs_kunit ==================
[03:11:54] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[03:11:54] =================== [SKIPPED] xe_migrate ===================
[03:11:54] ================== xe_dma_buf (1 subtest) ==================
[03:11:54] ==================== xe_dma_buf_kunit =====================
[03:11:54] ================ [SKIPPED] xe_dma_buf_kunit ================
[03:11:54] =================== [SKIPPED] xe_dma_buf ===================
[03:11:54] ==================== xe_bo (2 subtests) ====================
[03:11:54] ================== xe_ccs_migrate_kunit ===================
[03:11:54] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[03:11:54] ==================== xe_bo_evict_kunit ====================
[03:11:54] =============== [SKIPPED] xe_bo_evict_kunit ================
[03:11:54] ===================== [SKIPPED] xe_bo ======================
[03:11:54] ==================== args (11 subtests) ====================
[03:11:54] [PASSED] count_args_test
[03:11:54] [PASSED] call_args_example
[03:11:54] [PASSED] call_args_test
[03:11:54] [PASSED] drop_first_arg_example
[03:11:54] [PASSED] drop_first_arg_test
[03:11:54] [PASSED] first_arg_example
[03:11:54] [PASSED] first_arg_test
[03:11:54] [PASSED] last_arg_example
[03:11:54] [PASSED] last_arg_test
[03:11:54] [PASSED] pick_arg_example
[03:11:54] [PASSED] sep_comma_example
[03:11:54] ====================== [PASSED] args =======================
[03:11:54] =================== xe_pci (2 subtests) ====================
stty: 'standard input': Inappropriate ioctl for device
[03:11:54] [PASSED] xe_gmdid_graphics_ip
[03:11:54] [PASSED] xe_gmdid_media_ip
[03:11:54] ===================== [PASSED] xe_pci ======================
[03:11:54] =================== xe_rtp (2 subtests) ====================
[03:11:54] =============== xe_rtp_process_to_sr_tests ================
[03:11:54] [PASSED] coalesce-same-reg
[03:11:54] [PASSED] no-match-no-add
[03:11:54] [PASSED] match-or
[03:11:54] [PASSED] match-or-xfail
[03:11:54] [PASSED] no-match-no-add-multiple-rules
[03:11:54] [PASSED] two-regs-two-entries
[03:11:54] [PASSED] clr-one-set-other
[03:11:54] [PASSED] set-field
[03:11:54] [PASSED] conflict-duplicate
[03:11:54] [PASSED] conflict-not-disjoint
[03:11:54] [PASSED] conflict-reg-type
[03:11:54] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[03:11:54] ================== xe_rtp_process_tests ===================
[03:11:54] [PASSED] active1
[03:11:54] [PASSED] active2
[03:11:54] [PASSED] active-inactive
[03:11:54] [PASSED] inactive-active
[03:11:54] [PASSED] inactive-1st_or_active-inactive
[03:11:54] [PASSED] inactive-2nd_or_active-inactive
[03:11:54] [PASSED] inactive-last_or_active-inactive
[03:11:54] [PASSED] inactive-no_or_active-inactive
[03:11:54] ============== [PASSED] xe_rtp_process_tests ===============
[03:11:54] ===================== [PASSED] xe_rtp ======================
[03:11:54] ==================== xe_wa (1 subtest) =====================
[03:11:54] ======================== xe_wa_gt =========================
[03:11:54] [PASSED] TIGERLAKE (B0)
[03:11:54] [PASSED] DG1 (A0)
[03:11:54] [PASSED] DG1 (B0)
[03:11:54] [PASSED] ALDERLAKE_S (A0)
[03:11:54] [PASSED] ALDERLAKE_S (B0)
[03:11:54] [PASSED] ALDERLAKE_S (C0)
[03:11:54] [PASSED] ALDERLAKE_S (D0)
[03:11:54] [PASSED] ALDERLAKE_P (A0)
[03:11:54] [PASSED] ALDERLAKE_P (B0)
[03:11:54] [PASSED] ALDERLAKE_P (C0)
[03:11:54] [PASSED] ALDERLAKE_S_RPLS (D0)
[03:11:54] [PASSED] ALDERLAKE_P_RPLU (E0)
[03:11:54] [PASSED] DG2_G10 (C0)
[03:11:54] [PASSED] DG2_G11 (B1)
[03:11:54] [PASSED] DG2_G12 (A1)
[03:11:54] [PASSED] METEORLAKE (g:A0, m:A0)
[03:11:54] [PASSED] METEORLAKE (g:A0, m:A0)
[03:11:54] [PASSED] METEORLAKE (g:A0, m:A0)
[03:11:54] [PASSED] LUNARLAKE (g:A0, m:A0)
[03:11:54] [PASSED] LUNARLAKE (g:B0, m:A0)
[03:11:54] [PASSED] BATTLEMAGE (g:A0, m:A1)
[03:11:54] ==================== [PASSED] xe_wa_gt =====================
[03:11:54] ====================== [PASSED] xe_wa ======================
[03:11:54] ============================================================
[03:11:54] Testing complete. Ran 121 tests: passed: 106, skipped: 15
[03:11:54] Elapsed time: 30.388s total, 4.199s configuring, 25.919s building, 0.228s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[03:11:54] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:11:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
156 | u64 ioread64_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
163 | u64 ioread64_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
170 | u64 ioread64be_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
178 | u64 ioread64be_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
[03:12:18] Starting KUnit Kernel (1/1)...
[03:12:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:12:18] ============ drm_test_pick_cmdline (2 subtests) ============
[03:12:18] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[03:12:18] =============== drm_test_pick_cmdline_named ===============
[03:12:18] [PASSED] NTSC
[03:12:18] [PASSED] NTSC-J
[03:12:18] [PASSED] PAL
[03:12:18] [PASSED] PAL-M
[03:12:18] =========== [PASSED] drm_test_pick_cmdline_named ===========
[03:12:18] ============== [PASSED] drm_test_pick_cmdline ==============
[03:12:18] ================== drm_buddy (7 subtests) ==================
[03:12:18] [PASSED] drm_test_buddy_alloc_limit
[03:12:18] [PASSED] drm_test_buddy_alloc_optimistic
[03:12:18] [PASSED] drm_test_buddy_alloc_pessimistic
[03:12:18] [PASSED] drm_test_buddy_alloc_pathological
[03:12:18] [PASSED] drm_test_buddy_alloc_contiguous
[03:12:18] [PASSED] drm_test_buddy_alloc_clear
[03:12:18] [PASSED] drm_test_buddy_alloc_range_bias
[03:12:18] ==================== [PASSED] drm_buddy ====================
[03:12:18] ============= drm_cmdline_parser (40 subtests) =============
[03:12:18] [PASSED] drm_test_cmdline_force_d_only
[03:12:18] [PASSED] drm_test_cmdline_force_D_only_dvi
[03:12:18] [PASSED] drm_test_cmdline_force_D_only_hdmi
[03:12:18] [PASSED] drm_test_cmdline_force_D_only_not_digital
[03:12:18] [PASSED] drm_test_cmdline_force_e_only
[03:12:18] [PASSED] drm_test_cmdline_res
[03:12:18] [PASSED] drm_test_cmdline_res_vesa
[03:12:18] [PASSED] drm_test_cmdline_res_vesa_rblank
[03:12:18] [PASSED] drm_test_cmdline_res_rblank
[03:12:18] [PASSED] drm_test_cmdline_res_bpp
[03:12:18] [PASSED] drm_test_cmdline_res_refresh
[03:12:18] [PASSED] drm_test_cmdline_res_bpp_refresh
[03:12:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[03:12:18] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[03:12:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[03:12:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[03:12:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[03:12:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[03:12:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[03:12:18] [PASSED] drm_test_cmdline_res_margins_force_on
[03:12:18] [PASSED] drm_test_cmdline_res_vesa_margins
[03:12:18] [PASSED] drm_test_cmdline_name
[03:12:18] [PASSED] drm_test_cmdline_name_bpp
[03:12:18] [PASSED] drm_test_cmdline_name_option
[03:12:18] [PASSED] drm_test_cmdline_name_bpp_option
[03:12:18] [PASSED] drm_test_cmdline_rotate_0
[03:12:18] [PASSED] drm_test_cmdline_rotate_90
[03:12:18] [PASSED] drm_test_cmdline_rotate_180
[03:12:18] [PASSED] drm_test_cmdline_rotate_270
[03:12:18] [PASSED] drm_test_cmdline_hmirror
[03:12:18] [PASSED] drm_test_cmdline_vmirror
[03:12:18] [PASSED] drm_test_cmdline_margin_options
[03:12:18] [PASSED] drm_test_cmdline_multiple_options
[03:12:18] [PASSED] drm_test_cmdline_bpp_extra_and_option
[03:12:18] [PASSED] drm_test_cmdline_extra_and_option
[03:12:18] [PASSED] drm_test_cmdline_freestanding_options
[03:12:18] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[03:12:18] [PASSED] drm_test_cmdline_panel_orientation
[03:12:18] ================ drm_test_cmdline_invalid =================
[03:12:18] [PASSED] margin_only
[03:12:18] [PASSED] interlace_only
[03:12:18] [PASSED] res_missing_x
[03:12:18] [PASSED] res_missing_y
[03:12:18] [PASSED] res_bad_y
[03:12:18] [PASSED] res_missing_y_bpp
[03:12:18] [PASSED] res_bad_bpp
[03:12:18] [PASSED] res_bad_refresh
[03:12:18] [PASSED] res_bpp_refresh_force_on_off
[03:12:18] [PASSED] res_invalid_mode
[03:12:18] [PASSED] res_bpp_wrong_place_mode
[03:12:18] [PASSED] name_bpp_refresh
[03:12:18] [PASSED] name_refresh
[03:12:18] [PASSED] name_refresh_wrong_mode
[03:12:18] [PASSED] name_refresh_invalid_mode
[03:12:18] [PASSED] rotate_multiple
[03:12:18] [PASSED] rotate_invalid_val
[03:12:18] [PASSED] rotate_truncated
[03:12:18] [PASSED] invalid_option
[03:12:18] [PASSED] invalid_tv_option
[03:12:18] [PASSED] truncated_tv_option
[03:12:18] ============ [PASSED] drm_test_cmdline_invalid =============
[03:12:18] =============== drm_test_cmdline_tv_options ===============
[03:12:18] [PASSED] NTSC
[03:12:18] [PASSED] NTSC_443
[03:12:18] [PASSED] NTSC_J
[03:12:18] [PASSED] PAL
[03:12:18] [PASSED] PAL_M
[03:12:18] [PASSED] PAL_N
[03:12:18] [PASSED] SECAM
[03:12:18] [PASSED] MONO_525
[03:12:18] [PASSED] MONO_625
[03:12:18] =========== [PASSED] drm_test_cmdline_tv_options ===========
[03:12:18] =============== [PASSED] drm_cmdline_parser ================
[03:12:18] ========== drmm_connector_hdmi_init (19 subtests) ==========
[03:12:18] [PASSED] drm_test_connector_hdmi_init_valid
[03:12:18] [PASSED] drm_test_connector_hdmi_init_bpc_8
[03:12:18] [PASSED] drm_test_connector_hdmi_init_bpc_10
[03:12:18] [PASSED] drm_test_connector_hdmi_init_bpc_12
[03:12:18] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[03:12:18] [PASSED] drm_test_connector_hdmi_init_bpc_null
[03:12:18] [PASSED] drm_test_connector_hdmi_init_formats_empty
[03:12:18] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[03:12:18] [PASSED] drm_test_connector_hdmi_init_null_ddc
[03:12:18] [PASSED] drm_test_connector_hdmi_init_null_product
[03:12:18] [PASSED] drm_test_connector_hdmi_init_null_vendor
[03:12:18] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[03:12:18] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[03:12:18] [PASSED] drm_test_connector_hdmi_init_product_valid
[03:12:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[03:12:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[03:12:18] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[03:12:18] ========= drm_test_connector_hdmi_init_type_valid =========
[03:12:18] [PASSED] HDMI-A
[03:12:18] [PASSED] HDMI-B
[03:12:18] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[03:12:18] ======== drm_test_connector_hdmi_init_type_invalid ========
[03:12:18] [PASSED] Unknown
[03:12:18] [PASSED] VGA
[03:12:18] [PASSED] DVI-I
[03:12:18] [PASSED] DVI-D
[03:12:18] [PASSED] DVI-A
[03:12:18] [PASSED] Composite
[03:12:18] [PASSED] SVIDEO
[03:12:18] [PASSED] LVDS
[03:12:18] [PASSED] Component
[03:12:18] [PASSED] DIN
[03:12:18] [PASSED] DP
[03:12:18] [PASSED] TV
[03:12:18] [PASSED] eDP
[03:12:18] [PASSED] Virtual
[03:12:18] [PASSED] DSI
[03:12:18] [PASSED] DPI
[03:12:18] [PASSED] Writeback
[03:12:18] [PASSED] SPI
[03:12:18] [PASSED] USB
[03:12:18] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[03:12:18] ============ [PASSED] drmm_connector_hdmi_init =============
[03:12:18] ============= drmm_connector_init (3 subtests) =============
[03:12:18] [PASSED] drm_test_drmm_connector_init
[03:12:18] [PASSED] drm_test_drmm_connector_init_null_ddc
[03:12:18] ========= drm_test_drmm_connector_init_type_valid =========
[03:12:18] [PASSED] Unknown
[03:12:18] [PASSED] VGA
[03:12:18] [PASSED] DVI-I
[03:12:18] [PASSED] DVI-D
[03:12:18] [PASSED] DVI-A
[03:12:18] [PASSED] Composite
[03:12:18] [PASSED] SVIDEO
[03:12:18] [PASSED] LVDS
[03:12:18] [PASSED] Component
[03:12:18] [PASSED] DIN
[03:12:18] [PASSED] DP
[03:12:18] [PASSED] HDMI-A
[03:12:18] [PASSED] HDMI-B
[03:12:18] [PASSED] TV
[03:12:18] [PASSED] eDP
[03:12:18] [PASSED] Virtual
[03:12:18] [PASSED] DSI
[03:12:18] [PASSED] DPI
[03:12:18] [PASSED] Writeback
[03:12:18] [PASSED] SPI
[03:12:18] [PASSED] USB
[03:12:18] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[03:12:18] =============== [PASSED] drmm_connector_init ===============
[03:12:18] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[03:12:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[03:12:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[03:12:18] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[03:12:18] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[03:12:18] ========== drm_test_get_tv_mode_from_name_valid ===========
[03:12:18] [PASSED] NTSC
[03:12:18] [PASSED] NTSC-443
[03:12:18] [PASSED] NTSC-J
[03:12:18] [PASSED] PAL
[03:12:18] [PASSED] PAL-M
[03:12:18] [PASSED] PAL-N
[03:12:18] [PASSED] SECAM
[03:12:18] [PASSED] Mono
[03:12:18] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[03:12:18] [PASSED] drm_test_get_tv_mode_from_name_truncated
[03:12:18] ============ [PASSED] drm_get_tv_mode_from_name ============
[03:12:18] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[03:12:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[03:12:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[03:12:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[03:12:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[03:12:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[03:12:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[03:12:18] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[03:12:18] [PASSED] VIC 96
[03:12:18] [PASSED] VIC 97
[03:12:18] [PASSED] VIC 101
[03:12:18] [PASSED] VIC 102
[03:12:18] [PASSED] VIC 106
[03:12:18] [PASSED] VIC 107
[03:12:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[03:12:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[03:12:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[03:12:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[03:12:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[03:12:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[03:12:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[03:12:18] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[03:12:18] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[03:12:18] [PASSED] Automatic
[03:12:18] [PASSED] Full
[03:12:18] [PASSED] Limited 16:235
[03:12:18] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[03:12:18] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[03:12:18] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[03:12:18] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[03:12:18] === drm_test_drm_hdmi_connector_get_output_format_name ====
[03:12:18] [PASSED] RGB
[03:12:18] [PASSED] YUV 4:2:0
[03:12:18] [PASSED] YUV 4:2:2
[03:12:18] [PASSED] YUV 4:4:4
[03:12:18] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[03:12:18] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[03:12:18] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[03:12:18] ============= drm_damage_helper (21 subtests) ==============
[03:12:18] [PASSED] drm_test_damage_iter_no_damage
[03:12:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[03:12:18] [PASSED] drm_test_damage_iter_no_damage_src_moved
[03:12:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[03:12:18] [PASSED] drm_test_damage_iter_no_damage_not_visible
[03:12:18] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[03:12:18] [PASSED] drm_test_damage_iter_no_damage_no_fb
[03:12:18] [PASSED] drm_test_damage_iter_simple_damage
[03:12:18] [PASSED] drm_test_damage_iter_single_damage
[03:12:18] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[03:12:18] [PASSED] drm_test_damage_iter_single_damage_outside_src
[03:12:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[03:12:18] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[03:12:18] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[03:12:18] [PASSED] drm_test_damage_iter_single_damage_src_moved
[03:12:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[03:12:18] [PASSED] drm_test_damage_iter_damage
[03:12:18] [PASSED] drm_test_damage_iter_damage_one_intersect
[03:12:18] [PASSED] drm_test_damage_iter_damage_one_outside
[03:12:18] [PASSED] drm_test_damage_iter_damage_src_moved
[03:12:18] [PASSED] drm_test_damage_iter_damage_not_visible
[03:12:18] ================ [PASSED] drm_damage_helper ================
[03:12:18] ============== drm_dp_mst_helper (3 subtests) ==============
[03:12:18] ============== drm_test_dp_mst_calc_pbn_mode ==============
[03:12:18] [PASSED] Clock 154000 BPP 30 DSC disabled
[03:12:18] [PASSED] Clock 234000 BPP 30 DSC disabled
[03:12:18] [PASSED] Clock 297000 BPP 24 DSC disabled
[03:12:18] [PASSED] Clock 332880 BPP 24 DSC enabled
[03:12:18] [PASSED] Clock 324540 BPP 24 DSC enabled
[03:12:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[03:12:18] ============== drm_test_dp_mst_calc_pbn_div ===============
[03:12:18] [PASSED] Link rate 2000000 lane count 4
[03:12:18] [PASSED] Link rate 2000000 lane count 2
[03:12:18] [PASSED] Link rate 2000000 lane count 1
[03:12:18] [PASSED] Link rate 1350000 lane count 4
[03:12:18] [PASSED] Link rate 1350000 lane count 2
[03:12:18] [PASSED] Link rate 1350000 lane count 1
[03:12:18] [PASSED] Link rate 1000000 lane count 4
[03:12:18] [PASSED] Link rate 1000000 lane count 2
[03:12:18] [PASSED] Link rate 1000000 lane count 1
[03:12:18] [PASSED] Link rate 810000 lane count 4
[03:12:18] [PASSED] Link rate 810000 lane count 2
[03:12:18] [PASSED] Link rate 810000 lane count 1
[03:12:18] [PASSED] Link rate 540000 lane count 4
[03:12:18] [PASSED] Link rate 540000 lane count 2
[03:12:18] [PASSED] Link rate 540000 lane count 1
[03:12:18] [PASSED] Link rate 270000 lane count 4
[03:12:18] [PASSED] Link rate 270000 lane count 2
[03:12:18] [PASSED] Link rate 270000 lane count 1
[03:12:18] [PASSED] Link rate 162000 lane count 4
[03:12:18] [PASSED] Link rate 162000 lane count 2
[03:12:18] [PASSED] Link rate 162000 lane count 1
[03:12:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[03:12:18] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[03:12:18] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[03:12:18] [PASSED] DP_POWER_UP_PHY with port number
[03:12:18] [PASSED] DP_POWER_DOWN_PHY with port number
[03:12:18] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[03:12:18] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[03:12:18] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[03:12:18] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[03:12:18] [PASSED] DP_QUERY_PAYLOAD with port number
[03:12:18] [PASSED] DP_QUERY_PAYLOAD with VCPI
[03:12:18] [PASSED] DP_REMOTE_DPCD_READ with port number
[03:12:18] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[03:12:18] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[03:12:18] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[03:12:18] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[03:12:18] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[03:12:18] [PASSED] DP_REMOTE_I2C_READ with port number
[03:12:18] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[03:12:18] [PASSED] DP_REMOTE_I2C_READ with transactions array
[03:12:18] [PASSED] DP_REMOTE_I2C_WRITE with port number
[03:12:18] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[03:12:18] [PASSED] DP_REMOTE_I2C_WRITE with data array
[03:12:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[03:12:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[03:12:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[03:12:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[03:12:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[03:12:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[03:12:18] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[03:12:18] ================ [PASSED] drm_dp_mst_helper ================
[03:12:18] ================== drm_exec (7 subtests) ===================
[03:12:18] [PASSED] sanitycheck
[03:12:18] [PASSED] test_lock
[03:12:18] [PASSED] test_lock_unlock
[03:12:18] [PASSED] test_duplicates
[03:12:18] [PASSED] test_prepare
[03:12:18] [PASSED] test_prepare_array
[03:12:18] [PASSED] test_multiple_loops
[03:12:18] ==================== [PASSED] drm_exec =====================
[03:12:18] =========== drm_format_helper_test (17 subtests) ===========
[03:12:18] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[03:12:18] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[03:12:18] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[03:12:18] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[03:12:18] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[03:12:18] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[03:12:18] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[03:12:18] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[03:12:18] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[03:12:18] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[03:12:18] ============== drm_test_fb_xrgb8888_to_mono ===============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[03:12:18] ==================== drm_test_fb_swab =====================
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ================ [PASSED] drm_test_fb_swab =================
[03:12:18] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[03:12:18] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[03:12:18] [PASSED] single_pixel_source_buffer
[03:12:18] [PASSED] single_pixel_clip_rectangle
[03:12:18] [PASSED] well_known_colors
[03:12:18] [PASSED] destination_pitch
[03:12:18] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[03:12:18] ================= drm_test_fb_clip_offset =================
[03:12:18] [PASSED] pass through
[03:12:18] [PASSED] horizontal offset
[03:12:18] [PASSED] vertical offset
[03:12:18] [PASSED] horizontal and vertical offset
[03:12:18] [PASSED] horizontal offset (custom pitch)
[03:12:18] [PASSED] vertical offset (custom pitch)
[03:12:18] [PASSED] horizontal and vertical offset (custom pitch)
[03:12:18] ============= [PASSED] drm_test_fb_clip_offset =============
[03:12:18] ============== drm_test_fb_build_fourcc_list ==============
[03:12:18] [PASSED] no native formats
[03:12:18] [PASSED] XRGB8888 as native format
[03:12:18] [PASSED] remove duplicates
[03:12:18] [PASSED] convert alpha formats
[03:12:18] [PASSED] random formats
[03:12:18] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[03:12:18] =================== drm_test_fb_memcpy ====================
[03:12:18] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[03:12:18] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[03:12:18] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[03:12:18] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[03:12:18] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[03:12:18] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[03:12:18] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[03:12:18] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[03:12:18] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[03:12:18] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[03:12:18] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[03:12:18] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[03:12:18] =============== [PASSED] drm_test_fb_memcpy ================
[03:12:18] ============= [PASSED] drm_format_helper_test ==============
[03:12:18] ================= drm_format (18 subtests) =================
[03:12:18] [PASSED] drm_test_format_block_width_invalid
[03:12:18] [PASSED] drm_test_format_block_width_one_plane
[03:12:18] [PASSED] drm_test_format_block_width_two_plane
[03:12:18] [PASSED] drm_test_format_block_width_three_plane
[03:12:18] [PASSED] drm_test_format_block_width_tiled
[03:12:18] [PASSED] drm_test_format_block_height_invalid
[03:12:18] [PASSED] drm_test_format_block_height_one_plane
[03:12:18] [PASSED] drm_test_format_block_height_two_plane
[03:12:18] [PASSED] drm_test_format_block_height_three_plane
[03:12:18] [PASSED] drm_test_format_block_height_tiled
[03:12:18] [PASSED] drm_test_format_min_pitch_invalid
[03:12:18] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[03:12:18] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[03:12:18] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[03:12:18] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[03:12:18] [PASSED] drm_test_format_min_pitch_two_plane
[03:12:18] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[03:12:18] [PASSED] drm_test_format_min_pitch_tiled
[03:12:18] =================== [PASSED] drm_format ====================
[03:12:18] =============== drm_framebuffer (1 subtest) ================
[03:12:18] =============== drm_test_framebuffer_create ===============
[03:12:18] [PASSED] ABGR8888 normal sizes
[03:12:18] [PASSED] ABGR8888 max sizes
[03:12:18] [PASSED] ABGR8888 pitch greater than min required
[03:12:18] [PASSED] ABGR8888 pitch less than min required
[03:12:18] [PASSED] ABGR8888 Invalid width
[03:12:18] [PASSED] ABGR8888 Invalid buffer handle
[03:12:18] [PASSED] No pixel format
[03:12:18] [PASSED] ABGR8888 Width 0
[03:12:18] [PASSED] ABGR8888 Height 0
[03:12:18] [PASSED] ABGR8888 Out of bound height * pitch combination
[03:12:18] [PASSED] ABGR8888 Large buffer offset
[03:12:18] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[03:12:18] [PASSED] ABGR8888 Valid buffer modifier
[03:12:18] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[03:12:18] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[03:12:18] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[03:12:18] [PASSED] NV12 Normal sizes
[03:12:18] [PASSED] NV12 Max sizes
[03:12:18] [PASSED] NV12 Invalid pitch
[03:12:18] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[03:12:18] [PASSED] NV12 different modifier per-plane
[03:12:18] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[03:12:18] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[03:12:18] [PASSED] NV12 Modifier for inexistent plane
[03:12:18] [PASSED] NV12 Handle for inexistent plane
[03:12:18] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[03:12:18] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[03:12:18] [PASSED] YVU420 Normal sizes
[03:12:18] [PASSED] YVU420 Max sizes
[03:12:18] [PASSED] YVU420 Invalid pitch
[03:12:18] [PASSED] YVU420 Different pitches
[03:12:18] [PASSED] YVU420 Different buffer offsets/pitches
[03:12:18] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[03:12:18] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[03:12:18] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[03:12:18] [PASSED] YVU420 Valid modifier
[03:12:18] [PASSED] YVU420 Different modifiers per plane
[03:12:18] [PASSED] YVU420 Modifier for inexistent plane
[03:12:18] [PASSED] X0L2 Normal sizes
[03:12:18] [PASSED] X0L2 Max sizes
[03:12:18] [PASSED] X0L2 Invalid pitch
[03:12:18] [PASSED] X0L2 Pitch greater than minimum required
[03:12:18] [PASSED] X0L2 Handle for inexistent plane
[03:12:18] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[03:12:18] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[03:12:18] [PASSED] X0L2 Valid modifier
[03:12:18] [PASSED] X0L2 Modifier for inexistent plane
[03:12:18] =========== [PASSED] drm_test_framebuffer_create ===========
[03:12:18] ================= [PASSED] drm_framebuffer =================
[03:12:18] ================ drm_gem_shmem (8 subtests) ================
[03:12:18] [PASSED] drm_gem_shmem_test_obj_create
[03:12:18] [PASSED] drm_gem_shmem_test_obj_create_private
[03:12:18] [PASSED] drm_gem_shmem_test_pin_pages
[03:12:18] [PASSED] drm_gem_shmem_test_vmap
[03:12:18] [PASSED] drm_gem_shmem_test_get_pages_sgt
[03:12:18] [PASSED] drm_gem_shmem_test_get_sg_table
[03:12:18] [PASSED] drm_gem_shmem_test_madvise
[03:12:18] [PASSED] drm_gem_shmem_test_purge
[03:12:18] ================== [PASSED] drm_gem_shmem ==================
[03:12:18] === drm_atomic_helper_connector_hdmi_check (22 subtests) ===
[03:12:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[03:12:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[03:12:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[03:12:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[03:12:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[03:12:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[03:12:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[03:12:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[03:12:18] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[03:12:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[03:12:18] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[03:12:18] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[03:12:18] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[03:12:18] [PASSED] drm_test_check_output_bpc_dvi
[03:12:18] [PASSED] drm_test_check_output_bpc_format_vic_1
[03:12:18] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[03:12:18] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[03:12:18] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[03:12:18] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[03:12:18] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[03:12:18] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[03:12:18] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[03:12:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[03:12:18] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[03:12:18] [PASSED] drm_test_check_broadcast_rgb_value
[03:12:18] [PASSED] drm_test_check_bpc_8_value
[03:12:18] [PASSED] drm_test_check_bpc_10_value
[03:12:18] [PASSED] drm_test_check_bpc_12_value
[03:12:18] [PASSED] drm_test_check_format_value
[03:12:18] [PASSED] drm_test_check_tmds_char_value
[03:12:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[03:12:18] ================= drm_managed (2 subtests) =================
[03:12:18] [PASSED] drm_test_managed_release_action
[03:12:18] [PASSED] drm_test_managed_run_action
[03:12:18] =================== [PASSED] drm_managed ===================
[03:12:18] =================== drm_mm (6 subtests) ====================
[03:12:18] [PASSED] drm_test_mm_init
[03:12:18] [PASSED] drm_test_mm_debug
[03:12:18] [PASSED] drm_test_mm_align32
[03:12:18] [PASSED] drm_test_mm_align64
[03:12:18] [PASSED] drm_test_mm_lowest
[03:12:18] [PASSED] drm_test_mm_highest
[03:12:18] ===================== [PASSED] drm_mm ======================
[03:12:18] ============= drm_modes_analog_tv (5 subtests) =============
[03:12:18] [PASSED] drm_test_modes_analog_tv_mono_576i
[03:12:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[03:12:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[03:12:18] [PASSED] drm_test_modes_analog_tv_pal_576i
[03:12:18] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[03:12:18] =============== [PASSED] drm_modes_analog_tv ===============
[03:12:18] ============== drm_plane_helper (2 subtests) ===============
[03:12:18] =============== drm_test_check_plane_state ================
[03:12:18] [PASSED] clipping_simple
[03:12:18] [PASSED] clipping_rotate_reflect
[03:12:18] [PASSED] positioning_simple
[03:12:18] [PASSED] upscaling
[03:12:18] [PASSED] downscaling
[03:12:18] [PASSED] rounding1
[03:12:18] [PASSED] rounding2
[03:12:18] [PASSED] rounding3
[03:12:18] [PASSED] rounding4
[03:12:18] =========== [PASSED] drm_test_check_plane_state ============
[03:12:18] =========== drm_test_check_invalid_plane_state ============
[03:12:18] [PASSED] positioning_invalid
[03:12:18] [PASSED] upscaling_invalid
stty: 'standard input': Inappropriate ioctl for device
[03:12:18] [PASSED] downscaling_invalid
[03:12:18] ======= [PASSED] drm_test_check_invalid_plane_state ========
[03:12:18] ================ [PASSED] drm_plane_helper =================
[03:12:18] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[03:12:18] ====== drm_test_connector_helper_tv_get_modes_check =======
[03:12:18] [PASSED] None
[03:12:18] [PASSED] PAL
[03:12:18] [PASSED] NTSC
[03:12:18] [PASSED] Both, NTSC Default
[03:12:18] [PASSED] Both, PAL Default
[03:12:18] [PASSED] Both, NTSC Default, with PAL on command-line
[03:12:18] [PASSED] Both, PAL Default, with NTSC on command-line
[03:12:18] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[03:12:18] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[03:12:18] ================== drm_rect (9 subtests) ===================
[03:12:18] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[03:12:18] [PASSED] drm_test_rect_clip_scaled_not_clipped
[03:12:18] [PASSED] drm_test_rect_clip_scaled_clipped
[03:12:18] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[03:12:18] ================= drm_test_rect_intersect =================
[03:12:18] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[03:12:18] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[03:12:18] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[03:12:18] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[03:12:18] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[03:12:18] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[03:12:18] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[03:12:18] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[03:12:18] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[03:12:18] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[03:12:18] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[03:12:18] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[03:12:18] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[03:12:18] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[03:12:18] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[03:12:18] ============= [PASSED] drm_test_rect_intersect =============
[03:12:18] ================ drm_test_rect_calc_hscale ================
[03:12:18] [PASSED] normal use
[03:12:18] [PASSED] out of max range
[03:12:18] [PASSED] out of min range
[03:12:18] [PASSED] zero dst
[03:12:18] [PASSED] negative src
[03:12:18] [PASSED] negative dst
[03:12:18] ============ [PASSED] drm_test_rect_calc_hscale ============
[03:12:18] ================ drm_test_rect_calc_vscale ================
[03:12:18] [PASSED] normal use
[03:12:18] [PASSED] out of max range
[03:12:18] [PASSED] out of min range
[03:12:18] [PASSED] zero dst
[03:12:18] [PASSED] negative src
[03:12:18] [PASSED] negative dst
[03:12:18] ============ [PASSED] drm_test_rect_calc_vscale ============
[03:12:18] ================== drm_test_rect_rotate ===================
[03:12:18] [PASSED] reflect-x
[03:12:18] [PASSED] reflect-y
[03:12:18] [PASSED] rotate-0
[03:12:18] [PASSED] rotate-90
[03:12:18] [PASSED] rotate-180
[03:12:18] [PASSED] rotate-270
[03:12:18] ============== [PASSED] drm_test_rect_rotate ===============
[03:12:18] ================ drm_test_rect_rotate_inv =================
[03:12:18] [PASSED] reflect-x
[03:12:18] [PASSED] reflect-y
[03:12:18] [PASSED] rotate-0
[03:12:18] [PASSED] rotate-90
[03:12:18] [PASSED] rotate-180
[03:12:18] [PASSED] rotate-270
[03:12:18] ============ [PASSED] drm_test_rect_rotate_inv =============
[03:12:18] ==================== [PASSED] drm_rect =====================
[03:12:18] ============================================================
[03:12:18] Testing complete. Ran 515 tests: passed: 515
[03:12:18] Elapsed time: 23.919s total, 1.768s configuring, 21.931s building, 0.206s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[03:12:18] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[03:12:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[03:12:28] Starting KUnit Kernel (1/1)...
[03:12:28] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[03:12:29] ================= ttm_device (5 subtests) ==================
[03:12:29] [PASSED] ttm_device_init_basic
[03:12:29] [PASSED] ttm_device_init_multiple
[03:12:29] [PASSED] ttm_device_fini_basic
[03:12:29] [PASSED] ttm_device_init_no_vma_man
[03:12:29] ================== ttm_device_init_pools ==================
[03:12:29] [PASSED] No DMA allocations, no DMA32 required
[03:12:29] [PASSED] DMA allocations, DMA32 required
[03:12:29] [PASSED] No DMA allocations, DMA32 required
[03:12:29] [PASSED] DMA allocations, no DMA32 required
[03:12:29] ============== [PASSED] ttm_device_init_pools ==============
[03:12:29] =================== [PASSED] ttm_device ====================
[03:12:29] ================== ttm_pool (8 subtests) ===================
[03:12:29] ================== ttm_pool_alloc_basic ===================
[03:12:29] [PASSED] One page
[03:12:29] [PASSED] More than one page
[03:12:29] [PASSED] Above the allocation limit
[03:12:29] [PASSED] One page, with coherent DMA mappings enabled
[03:12:29] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[03:12:29] ============== [PASSED] ttm_pool_alloc_basic ===============
[03:12:29] ============== ttm_pool_alloc_basic_dma_addr ==============
[03:12:29] [PASSED] One page
[03:12:29] [PASSED] More than one page
[03:12:29] [PASSED] Above the allocation limit
[03:12:29] [PASSED] One page, with coherent DMA mappings enabled
[03:12:29] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[03:12:29] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[03:12:29] [PASSED] ttm_pool_alloc_order_caching_match
[03:12:29] [PASSED] ttm_pool_alloc_caching_mismatch
[03:12:29] [PASSED] ttm_pool_alloc_order_mismatch
[03:12:29] [PASSED] ttm_pool_free_dma_alloc
[03:12:29] [PASSED] ttm_pool_free_no_dma_alloc
[03:12:29] [PASSED] ttm_pool_fini_basic
[03:12:29] ==================== [PASSED] ttm_pool =====================
[03:12:29] ================ ttm_resource (8 subtests) =================
[03:12:29] ================= ttm_resource_init_basic =================
[03:12:29] [PASSED] Init resource in TTM_PL_SYSTEM
[03:12:29] [PASSED] Init resource in TTM_PL_VRAM
[03:12:29] [PASSED] Init resource in a private placement
[03:12:29] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[03:12:29] ============= [PASSED] ttm_resource_init_basic =============
[03:12:29] [PASSED] ttm_resource_init_pinned
[03:12:29] [PASSED] ttm_resource_fini_basic
[03:12:29] [PASSED] ttm_resource_manager_init_basic
[03:12:29] [PASSED] ttm_resource_manager_usage_basic
[03:12:29] [PASSED] ttm_resource_manager_set_used_basic
[03:12:29] [PASSED] ttm_sys_man_alloc_basic
[03:12:29] [PASSED] ttm_sys_man_free_basic
[03:12:29] ================== [PASSED] ttm_resource ===================
[03:12:29] =================== ttm_tt (15 subtests) ===================
[03:12:29] ==================== ttm_tt_init_basic ====================
[03:12:29] [PASSED] Page-aligned size
[03:12:29] [PASSED] Extra pages requested
[03:12:29] ================ [PASSED] ttm_tt_init_basic ================
[03:12:29] [PASSED] ttm_tt_init_misaligned
[03:12:29] [PASSED] ttm_tt_fini_basic
[03:12:29] [PASSED] ttm_tt_fini_sg
[03:12:29] [PASSED] ttm_tt_fini_shmem
[03:12:29] [PASSED] ttm_tt_create_basic
[03:12:29] [PASSED] ttm_tt_create_invalid_bo_type
[03:12:29] [PASSED] ttm_tt_create_ttm_exists
[03:12:29] [PASSED] ttm_tt_create_failed
[03:12:29] [PASSED] ttm_tt_destroy_basic
[03:12:29] [PASSED] ttm_tt_populate_null_ttm
[03:12:29] [PASSED] ttm_tt_populate_populated_ttm
[03:12:29] [PASSED] ttm_tt_unpopulate_basic
[03:12:29] [PASSED] ttm_tt_unpopulate_empty_ttm
[03:12:29] [PASSED] ttm_tt_swapin_basic
[03:12:29] ===================== [PASSED] ttm_tt ======================
[03:12:29] =================== ttm_bo (14 subtests) ===================
[03:12:29] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[03:12:29] [PASSED] Cannot be interrupted and sleeps
[03:12:29] [PASSED] Cannot be interrupted, locks straight away
[03:12:29] [PASSED] Can be interrupted, sleeps
[03:12:29] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[03:12:29] [PASSED] ttm_bo_reserve_locked_no_sleep
[03:12:29] [PASSED] ttm_bo_reserve_no_wait_ticket
[03:12:29] [PASSED] ttm_bo_reserve_double_resv
[03:12:29] [PASSED] ttm_bo_reserve_interrupted
[03:12:29] [PASSED] ttm_bo_reserve_deadlock
[03:12:29] [PASSED] ttm_bo_unreserve_basic
[03:12:29] [PASSED] ttm_bo_unreserve_pinned
[03:12:29] [PASSED] ttm_bo_unreserve_bulk
[03:12:29] [PASSED] ttm_bo_put_basic
[03:12:29] [PASSED] ttm_bo_put_shared_resv
[03:12:29] [PASSED] ttm_bo_pin_basic
[03:12:29] [PASSED] ttm_bo_pin_unpin_resource
[03:12:29] [PASSED] ttm_bo_multiple_pin_one_unpin
[03:12:29] ===================== [PASSED] ttm_bo ======================
[03:12:29] ============== ttm_bo_validate (22 subtests) ===============
[03:12:29] ============== ttm_bo_init_reserved_sys_man ===============
[03:12:29] [PASSED] Buffer object for userspace
[03:12:29] [PASSED] Kernel buffer object
[03:12:29] [PASSED] Shared buffer object
[03:12:29] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[03:12:29] ============== ttm_bo_init_reserved_mock_man ==============
[03:12:29] [PASSED] Buffer object for userspace
[03:12:29] [PASSED] Kernel buffer object
[03:12:29] [PASSED] Shared buffer object
[03:12:29] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[03:12:29] [PASSED] ttm_bo_init_reserved_resv
[03:12:29] ================== ttm_bo_validate_basic ==================
[03:12:29] [PASSED] Buffer object for userspace
[03:12:29] [PASSED] Kernel buffer object
[03:12:29] [PASSED] Shared buffer object
[03:12:29] ============== [PASSED] ttm_bo_validate_basic ==============
[03:12:29] [PASSED] ttm_bo_validate_invalid_placement
[03:12:29] ============= ttm_bo_validate_same_placement ==============
[03:12:29] [PASSED] System manager
[03:12:29] [PASSED] VRAM manager
[03:12:29] ========= [PASSED] ttm_bo_validate_same_placement ==========
[03:12:29] [PASSED] ttm_bo_validate_failed_alloc
[03:12:29] [PASSED] ttm_bo_validate_pinned
[03:12:29] [PASSED] ttm_bo_validate_busy_placement
[03:12:29] ================ ttm_bo_validate_multihop =================
[03:12:29] [PASSED] Buffer object for userspace
[03:12:29] [PASSED] Kernel buffer object
[03:12:29] [PASSED] Shared buffer object
[03:12:29] ============ [PASSED] ttm_bo_validate_multihop =============
[03:12:29] ========== ttm_bo_validate_no_placement_signaled ==========
[03:12:29] [PASSED] Buffer object in system domain, no page vector
[03:12:29] [PASSED] Buffer object in system domain with an existing page vector
[03:12:29] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[03:12:29] ======== ttm_bo_validate_no_placement_not_signaled ========
[03:12:29] [PASSED] Buffer object for userspace
[03:12:29] [PASSED] Kernel buffer object
[03:12:29] [PASSED] Shared buffer object
[03:12:29] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[03:12:29] [PASSED] ttm_bo_validate_move_fence_signaled
[03:12:29] ========= ttm_bo_validate_move_fence_not_signaled =========
[03:12:29] [PASSED] Waits for GPU
[03:12:29] [PASSED] Tries to lock straight away
[03:12:29] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[03:12:29] [PASSED] ttm_bo_validate_swapout
[03:12:29] [PASSED] ttm_bo_validate_happy_evict
[03:12:29] [PASSED] ttm_bo_validate_all_pinned_evict
[03:12:29] [PASSED] ttm_bo_validate_allowed_only_evict
[03:12:29] [PASSED] ttm_bo_validate_deleted_evict
[03:12:29] [PASSED] ttm_bo_validate_busy_domain_evict
[03:12:29] [PASSED] ttm_bo_validate_evict_gutting
[03:12:29] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[03:12:29] ================= [PASSED] ttm_bo_validate =================
[03:12:29] ============================================================
[03:12:29] Testing complete. Ran 102 tests: passed: 102
[03:12:29] Elapsed time: 11.250s total, 1.732s configuring, 8.847s building, 0.558s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 83+ messages in thread* ✓ CI.Build: success for Stop using xe_gt as a register MMIO target (rev2)
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (45 preceding siblings ...)
2024-09-07 3:12 ` ✓ CI.KUnit: success " Patchwork
@ 2024-09-07 3:26 ` Patchwork
2024-09-07 3:31 ` ✗ CI.Hooks: failure " Patchwork
` (3 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Patchwork @ 2024-09-07 3:26 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Stop using xe_gt as a register MMIO target (rev2)
URL : https://patchwork.freedesktop.org/series/138168/
State : success
== Summary ==
lib/modules/6.11.0-rc6-xe/kernel/sound/core/seq/
lib/modules/6.11.0-rc6-xe/kernel/sound/core/seq/snd-seq.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-seq-device.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-hwdep.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-pcm.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-compress.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-timer.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soundcore.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/snd-soc-sst-atom-hifi2-platform.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/sst/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-acpi.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-core.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/common/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/common/snd-soc-acpi-intel-match.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/amd/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/amd/snd-acp-config.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-tgl.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-mlink.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-cnl.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-lnl.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-common.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-generic.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-mtl.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/amd/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/amd/snd-sof-amd-renoir.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/amd/snd-sof-amd-acp.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/snd-sof-utils.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/snd-sof-pci.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/snd-sof.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/snd-sof-probes.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/xtensa/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/xtensa/snd-sof-xtensa-dsp.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/snd-soc-core.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/snd-soc-acpi.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/codecs/
lib/modules/6.11.0-rc6-xe/kernel/sound/soc/codecs/snd-soc-hdac-hda.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/hda/
lib/modules/6.11.0-rc6-xe/kernel/sound/hda/snd-intel-sdw-acpi.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/hda/ext/
lib/modules/6.11.0-rc6-xe/kernel/sound/hda/ext/snd-hda-ext-core.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/hda/snd-intel-dspcfg.ko
lib/modules/6.11.0-rc6-xe/kernel/sound/hda/snd-hda-core.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kernel/
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kernel/msr.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kernel/cpuid.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/sha512-ssse3.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/crct10dif-pclmul.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/ghash-clmulni-intel.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/sha1-ssse3.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/crc32-pclmul.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/sha256-ssse3.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/aesni-intel.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/polyval-clmulni.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/events/
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/events/intel/
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/events/intel/intel-cstate.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/events/rapl.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kvm/
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kvm/kvm.ko
lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kvm/kvm-intel.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/
lib/modules/6.11.0-rc6-xe/kernel/crypto/crypto_simd.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/cmac.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/ccm.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/cryptd.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/polyval-generic.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/
lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.11.0-rc6-xe/build
lib/modules/6.11.0-rc6-xe/modules.alias.bin
lib/modules/6.11.0-rc6-xe/modules.builtin
lib/modules/6.11.0-rc6-xe/modules.softdep
lib/modules/6.11.0-rc6-xe/modules.alias
lib/modules/6.11.0-rc6-xe/modules.order
lib/modules/6.11.0-rc6-xe/modules.symbols
lib/modules/6.11.0-rc6-xe/modules.dep.bin
+ mv kernel-nodebug.tar.gz ..
+ cd ..
+ rm -rf archive
++ date +%s
+ echo -e '\e[0Ksection_end:1725679455:package_x86_64_nodebug\r\e[0K'
+ sync
^[[0Ksection_end:1725679455:package_x86_64_nodebug
^[[0K
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 83+ messages in thread* ✗ CI.Hooks: failure for Stop using xe_gt as a register MMIO target (rev2)
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (46 preceding siblings ...)
2024-09-07 3:26 ` ✓ CI.Build: " Patchwork
@ 2024-09-07 3:31 ` Patchwork
2024-09-07 3:34 ` ✓ CI.checksparse: success " Patchwork
` (2 subsequent siblings)
50 siblings, 0 replies; 83+ messages in thread
From: Patchwork @ 2024-09-07 3:31 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Stop using xe_gt as a register MMIO target (rev2)
URL : https://patchwork.freedesktop.org/series/138168/
State : failure
== Summary ==
run-parts: executing /workspace/ci/hooks/00-showenv
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ cd /workspace/kernel
++ nproc
+ make -j48 O=/workspace/kernel/build64-default modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-default'
GEN Makefile
UPD include/generated/compile.h
UPD include/config/kernel.release
mkdir -p /workspace/kernel/build64-default/tools/objtool && make O=/workspace/kernel/build64-default subdir=tools/objtool --no-print-directory -C objtool
UPD include/generated/utsrelease.h
CALL ../scripts/checksyscalls.sh
HOSTCC /workspace/kernel/build64-default/tools/objtool/fixdep.o
HOSTLD /workspace/kernel/build64-default/tools/objtool/fixdep-in.o
LINK /workspace/kernel/build64-default/tools/objtool/fixdep
INSTALL libsubcmd_headers
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
LD /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
AR /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
CC /workspace/kernel/build64-default/tools/objtool/weak.o
CC /workspace/kernel/build64-default/tools/objtool/check.o
CC /workspace/kernel/build64-default/tools/objtool/special.o
CC /workspace/kernel/build64-default/tools/objtool/builtin-check.o
CC /workspace/kernel/build64-default/tools/objtool/elf.o
CC /workspace/kernel/build64-default/tools/objtool/objtool.o
CC /workspace/kernel/build64-default/tools/objtool/orc_gen.o
CC /workspace/kernel/build64-default/tools/objtool/orc_dump.o
CC /workspace/kernel/build64-default/tools/objtool/libstring.o
CC /workspace/kernel/build64-default/tools/objtool/libctype.o
CC /workspace/kernel/build64-default/tools/objtool/str_error_r.o
CC /workspace/kernel/build64-default/tools/objtool/librbtree.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/orc.o
LD /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
LD /workspace/kernel/build64-default/tools/objtool/objtool-in.o
LINK /workspace/kernel/build64-default/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-default'
++ nproc
+ make -j48 O=/workspace/kernel/build64-default W=1 drivers/gpu/drm/xe
make[1]: Entering directory '/workspace/kernel/build64-default'
make[2]: Nothing to be done for 'drivers/gpu/drm/xe'.
make[1]: Leaving directory '/workspace/kernel/build64-default'
run-parts: executing /workspace/ci/hooks/11-build-32b
+++ realpath /workspace/ci/hooks/11-build-32b
++ dirname /workspace/ci/hooks/11-build-32b
+ THIS_SCRIPT_DIR=/workspace/ci/hooks
+ SRC_DIR=/workspace/kernel
+ TOOLS_SRC_DIR=/workspace/ci
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ BUILD_DIR=/workspace/kernel/build64-default/build32
+ cd /workspace/kernel
+ mkdir -p /workspace/kernel/build64-default/build32
++ nproc
+ make -j48 ARCH=i386 O=/workspace/kernel/build64-default/build32 defconfig
make[1]: Entering directory '/workspace/kernel/build64-default/build32'
GEN Makefile
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/confdata.o
HOSTCC scripts/kconfig/expr.o
LEX scripts/kconfig/lexer.lex.c
YACC scripts/kconfig/parser.tab.[ch]
HOSTCC scripts/kconfig/preprocess.o
HOSTCC scripts/kconfig/menu.o
HOSTCC scripts/kconfig/symbol.o
HOSTCC scripts/kconfig/util.o
HOSTCC scripts/kconfig/lexer.lex.o
HOSTCC scripts/kconfig/parser.tab.o
HOSTLD scripts/kconfig/conf
*** Default configuration is based on 'i386_defconfig'
#
# configuration written to .config
#
make[1]: Leaving directory '/workspace/kernel/build64-default/build32'
+ cd /workspace/kernel/build64-default/build32
+ /workspace/kernel/scripts/kconfig/merge_config.sh .config /workspace/ci/kernel/10-xe.fragment
Using .config as base
Merging /workspace/ci/kernel/10-xe.fragment
Value of CONFIG_DRM_XE is redefined by fragment /workspace/ci/kernel/10-xe.fragment:
Previous value: # CONFIG_DRM_XE is not set
New value: CONFIG_DRM_XE=m
Value of CONFIG_SND_DEBUG is redefined by fragment /workspace/ci/kernel/10-xe.fragment:
Previous value: # CONFIG_SND_DEBUG is not set
New value: CONFIG_SND_DEBUG=y
Value of CONFIG_SND_HDA_INTEL is redefined by fragment /workspace/ci/kernel/10-xe.fragment:
Previous value: CONFIG_SND_HDA_INTEL=y
New value: CONFIG_SND_HDA_INTEL=m
Value of CONFIG_SND_HDA_CODEC_HDMI is redefined by fragment /workspace/ci/kernel/10-xe.fragment:
Previous value: # CONFIG_SND_HDA_CODEC_HDMI is not set
New value: CONFIG_SND_HDA_CODEC_HDMI=m
GEN Makefile
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
#
# configuration written to .config
#
Value requested for CONFIG_HAVE_UID16 not in final .config
Requested value: CONFIG_HAVE_UID16=y
Actual value:
Value requested for CONFIG_UID16 not in final .config
Requested value: CONFIG_UID16=y
Actual value:
Value requested for CONFIG_X86_32 not in final .config
Requested value: CONFIG_X86_32=y
Actual value:
Value requested for CONFIG_OUTPUT_FORMAT not in final .config
Requested value: CONFIG_OUTPUT_FORMAT="elf32-i386"
Actual value: CONFIG_OUTPUT_FORMAT="elf64-x86-64"
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MIN not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MIN=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MIN=28
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MAX not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MAX=16
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MAX=32
Value requested for CONFIG_PGTABLE_LEVELS not in final .config
Requested value: CONFIG_PGTABLE_LEVELS=2
Actual value: CONFIG_PGTABLE_LEVELS=5
Value requested for CONFIG_X86_BIGSMP not in final .config
Requested value: # CONFIG_X86_BIGSMP is not set
Actual value:
Value requested for CONFIG_X86_INTEL_QUARK not in final .config
Requested value: # CONFIG_X86_INTEL_QUARK is not set
Actual value:
Value requested for CONFIG_X86_RDC321X not in final .config
Requested value: # CONFIG_X86_RDC321X is not set
Actual value:
Value requested for CONFIG_X86_32_NON_STANDARD not in final .config
Requested value: # CONFIG_X86_32_NON_STANDARD is not set
Actual value:
Value requested for CONFIG_X86_32_IRIS not in final .config
Requested value: # CONFIG_X86_32_IRIS is not set
Actual value:
Value requested for CONFIG_M486SX not in final .config
Requested value: # CONFIG_M486SX is not set
Actual value:
Value requested for CONFIG_M486 not in final .config
Requested value: # CONFIG_M486 is not set
Actual value:
Value requested for CONFIG_M586 not in final .config
Requested value: # CONFIG_M586 is not set
Actual value:
Value requested for CONFIG_M586TSC not in final .config
Requested value: # CONFIG_M586TSC is not set
Actual value:
Value requested for CONFIG_M586MMX not in final .config
Requested value: # CONFIG_M586MMX is not set
Actual value:
Value requested for CONFIG_M686 not in final .config
Requested value: CONFIG_M686=y
Actual value:
Value requested for CONFIG_MPENTIUMII not in final .config
Requested value: # CONFIG_MPENTIUMII is not set
Actual value:
Value requested for CONFIG_MPENTIUMIII not in final .config
Requested value: # CONFIG_MPENTIUMIII is not set
Actual value:
Value requested for CONFIG_MPENTIUMM not in final .config
Requested value: # CONFIG_MPENTIUMM is not set
Actual value:
Value requested for CONFIG_MPENTIUM4 not in final .config
Requested value: # CONFIG_MPENTIUM4 is not set
Actual value:
Value requested for CONFIG_MK6 not in final .config
Requested value: # CONFIG_MK6 is not set
Actual value:
Value requested for CONFIG_MK7 not in final .config
Requested value: # CONFIG_MK7 is not set
Actual value:
Value requested for CONFIG_MCRUSOE not in final .config
Requested value: # CONFIG_MCRUSOE is not set
Actual value:
Value requested for CONFIG_MEFFICEON not in final .config
Requested value: # CONFIG_MEFFICEON is not set
Actual value:
Value requested for CONFIG_MWINCHIPC6 not in final .config
Requested value: # CONFIG_MWINCHIPC6 is not set
Actual value:
Value requested for CONFIG_MWINCHIP3D not in final .config
Requested value: # CONFIG_MWINCHIP3D is not set
Actual value:
Value requested for CONFIG_MELAN not in final .config
Requested value: # CONFIG_MELAN is not set
Actual value:
Value requested for CONFIG_MGEODEGX1 not in final .config
Requested value: # CONFIG_MGEODEGX1 is not set
Actual value:
Value requested for CONFIG_MGEODE_LX not in final .config
Requested value: # CONFIG_MGEODE_LX is not set
Actual value:
Value requested for CONFIG_MCYRIXIII not in final .config
Requested value: # CONFIG_MCYRIXIII is not set
Actual value:
Value requested for CONFIG_MVIAC3_2 not in final .config
Requested value: # CONFIG_MVIAC3_2 is not set
Actual value:
Value requested for CONFIG_MVIAC7 not in final .config
Requested value: # CONFIG_MVIAC7 is not set
Actual value:
Value requested for CONFIG_X86_GENERIC not in final .config
Requested value: # CONFIG_X86_GENERIC is not set
Actual value:
Value requested for CONFIG_X86_INTERNODE_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_INTERNODE_CACHE_SHIFT=5
Actual value: CONFIG_X86_INTERNODE_CACHE_SHIFT=6
Value requested for CONFIG_X86_L1_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_L1_CACHE_SHIFT=5
Actual value: CONFIG_X86_L1_CACHE_SHIFT=6
Value requested for CONFIG_X86_USE_PPRO_CHECKSUM not in final .config
Requested value: CONFIG_X86_USE_PPRO_CHECKSUM=y
Actual value:
Value requested for CONFIG_X86_MINIMUM_CPU_FAMILY not in final .config
Requested value: CONFIG_X86_MINIMUM_CPU_FAMILY=6
Actual value: CONFIG_X86_MINIMUM_CPU_FAMILY=64
Value requested for CONFIG_CPU_SUP_TRANSMETA_32 not in final .config
Requested value: CONFIG_CPU_SUP_TRANSMETA_32=y
Actual value:
Value requested for CONFIG_CPU_SUP_VORTEX_32 not in final .config
Requested value: CONFIG_CPU_SUP_VORTEX_32=y
Actual value:
Value requested for CONFIG_HPET_TIMER not in final .config
Requested value: # CONFIG_HPET_TIMER is not set
Actual value: CONFIG_HPET_TIMER=y
Value requested for CONFIG_NR_CPUS_RANGE_END not in final .config
Requested value: CONFIG_NR_CPUS_RANGE_END=8
Actual value: CONFIG_NR_CPUS_RANGE_END=512
Value requested for CONFIG_NR_CPUS_DEFAULT not in final .config
Requested value: CONFIG_NR_CPUS_DEFAULT=8
Actual value: CONFIG_NR_CPUS_DEFAULT=64
Value requested for CONFIG_X86_ANCIENT_MCE not in final .config
Requested value: # CONFIG_X86_ANCIENT_MCE is not set
Actual value:
Value requested for CONFIG_X86_LEGACY_VM86 not in final .config
Requested value: # CONFIG_X86_LEGACY_VM86 is not set
Actual value:
Value requested for CONFIG_X86_ESPFIX32 not in final .config
Requested value: CONFIG_X86_ESPFIX32=y
Actual value:
Value requested for CONFIG_TOSHIBA not in final .config
Requested value: # CONFIG_TOSHIBA is not set
Actual value:
Value requested for CONFIG_X86_REBOOTFIXUPS not in final .config
Requested value: # CONFIG_X86_REBOOTFIXUPS is not set
Actual value:
Value requested for CONFIG_MICROCODE_INITRD32 not in final .config
Requested value: CONFIG_MICROCODE_INITRD32=y
Actual value:
Value requested for CONFIG_NOHIGHMEM not in final .config
Requested value: # CONFIG_NOHIGHMEM is not set
Actual value:
Value requested for CONFIG_HIGHMEM4G not in final .config
Requested value: CONFIG_HIGHMEM4G=y
Actual value:
Value requested for CONFIG_HIGHMEM64G not in final .config
Requested value: # CONFIG_HIGHMEM64G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_3G not in final .config
Requested value: CONFIG_VMSPLIT_3G=y
Actual value:
Value requested for CONFIG_VMSPLIT_3G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_3G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G not in final .config
Requested value: # CONFIG_VMSPLIT_2G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_2G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_1G not in final .config
Requested value: # CONFIG_VMSPLIT_1G is not set
Actual value:
Value requested for CONFIG_PAGE_OFFSET not in final .config
Requested value: CONFIG_PAGE_OFFSET=0xC0000000
Actual value:
Value requested for CONFIG_HIGHMEM not in final .config
Requested value: CONFIG_HIGHMEM=y
Actual value:
Value requested for CONFIG_X86_PAE not in final .config
Requested value: # CONFIG_X86_PAE is not set
Actual value:
Value requested for CONFIG_ARCH_FLATMEM_ENABLE not in final .config
Requested value: CONFIG_ARCH_FLATMEM_ENABLE=y
Actual value:
Value requested for CONFIG_ARCH_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_ARCH_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_ILLEGAL_POINTER_VALUE not in final .config
Requested value: CONFIG_ILLEGAL_POINTER_VALUE=0
Actual value: CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
Value requested for CONFIG_HIGHPTE not in final .config
Requested value: # CONFIG_HIGHPTE is not set
Actual value:
Value requested for CONFIG_COMPAT_VDSO not in final .config
Requested value: # CONFIG_COMPAT_VDSO is not set
Actual value:
Value requested for CONFIG_FUNCTION_PADDING_CFI not in final .config
Requested value: CONFIG_FUNCTION_PADDING_CFI=0
Actual value: CONFIG_FUNCTION_PADDING_CFI=11
Value requested for CONFIG_FUNCTION_PADDING_BYTES not in final .config
Requested value: CONFIG_FUNCTION_PADDING_BYTES=4
Actual value: CONFIG_FUNCTION_PADDING_BYTES=16
Value requested for CONFIG_APM not in final .config
Requested value: # CONFIG_APM is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K6 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K6 is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K7 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K7 is not set
Actual value:
Value requested for CONFIG_X86_GX_SUSPMOD not in final .config
Requested value: # CONFIG_X86_GX_SUSPMOD is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_ICH not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_ICH is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_SMI not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_SMI is not set
Actual value:
Value requested for CONFIG_X86_CPUFREQ_NFORCE2 not in final .config
Requested value: # CONFIG_X86_CPUFREQ_NFORCE2 is not set
Actual value:
Value requested for CONFIG_X86_LONGRUN not in final .config
Requested value: # CONFIG_X86_LONGRUN is not set
Actual value:
Value requested for CONFIG_X86_LONGHAUL not in final .config
Requested value: # CONFIG_X86_LONGHAUL is not set
Actual value:
Value requested for CONFIG_X86_E_POWERSAVER not in final .config
Requested value: # CONFIG_X86_E_POWERSAVER is not set
Actual value:
Value requested for CONFIG_PCI_GOBIOS not in final .config
Requested value: # CONFIG_PCI_GOBIOS is not set
Actual value:
Value requested for CONFIG_PCI_GOMMCONFIG not in final .config
Requested value: # CONFIG_PCI_GOMMCONFIG is not set
Actual value:
Value requested for CONFIG_PCI_GODIRECT not in final .config
Requested value: # CONFIG_PCI_GODIRECT is not set
Actual value:
Value requested for CONFIG_PCI_GOANY not in final .config
Requested value: CONFIG_PCI_GOANY=y
Actual value:
Value requested for CONFIG_PCI_BIOS not in final .config
Requested value: CONFIG_PCI_BIOS=y
Actual value:
Value requested for CONFIG_ISA not in final .config
Requested value: # CONFIG_ISA is not set
Actual value:
Value requested for CONFIG_SCx200 not in final .config
Requested value: # CONFIG_SCx200 is not set
Actual value:
Value requested for CONFIG_OLPC not in final .config
Requested value: # CONFIG_OLPC is not set
Actual value:
Value requested for CONFIG_ALIX not in final .config
Requested value: # CONFIG_ALIX is not set
Actual value:
Value requested for CONFIG_NET5501 not in final .config
Requested value: # CONFIG_NET5501 is not set
Actual value:
Value requested for CONFIG_GEOS not in final .config
Requested value: # CONFIG_GEOS is not set
Actual value:
Value requested for CONFIG_COMPAT_32 not in final .config
Requested value: CONFIG_COMPAT_32=y
Actual value:
Value requested for CONFIG_HAVE_ATOMIC_IOMAP not in final .config
Requested value: CONFIG_HAVE_ATOMIC_IOMAP=y
Actual value:
Value requested for CONFIG_ARCH_32BIT_OFF_T not in final .config
Requested value: CONFIG_ARCH_32BIT_OFF_T=y
Actual value:
Value requested for CONFIG_ARCH_WANT_IPC_PARSE_VERSION not in final .config
Requested value: CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
Actual value:
Value requested for CONFIG_MODULES_USE_ELF_REL not in final .config
Requested value: CONFIG_MODULES_USE_ELF_REL=y
Actual value:
Value requested for CONFIG_ARCH_MMAP_RND_BITS not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS=28
Value requested for CONFIG_CLONE_BACKWARDS not in final .config
Requested value: CONFIG_CLONE_BACKWARDS=y
Actual value:
Value requested for CONFIG_OLD_SIGSUSPEND3 not in final .config
Requested value: CONFIG_OLD_SIGSUSPEND3=y
Actual value:
Value requested for CONFIG_OLD_SIGACTION not in final .config
Requested value: CONFIG_OLD_SIGACTION=y
Actual value:
Value requested for CONFIG_ARCH_SPLIT_ARG64 not in final .config
Requested value: CONFIG_ARCH_SPLIT_ARG64=y
Actual value:
Value requested for CONFIG_FUNCTION_ALIGNMENT not in final .config
Requested value: CONFIG_FUNCTION_ALIGNMENT=4
Actual value: CONFIG_FUNCTION_ALIGNMENT=16
Value requested for CONFIG_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_FLATMEM_MANUAL not in final .config
Requested value: CONFIG_FLATMEM_MANUAL=y
Actual value:
Value requested for CONFIG_SPARSEMEM_MANUAL not in final .config
Requested value: # CONFIG_SPARSEMEM_MANUAL is not set
Actual value:
Value requested for CONFIG_FLATMEM not in final .config
Requested value: CONFIG_FLATMEM=y
Actual value:
Value requested for CONFIG_SPARSEMEM_STATIC not in final .config
Requested value: CONFIG_SPARSEMEM_STATIC=y
Actual value:
Value requested for CONFIG_BOUNCE not in final .config
Requested value: CONFIG_BOUNCE=y
Actual value:
Value requested for CONFIG_KMAP_LOCAL not in final .config
Requested value: CONFIG_KMAP_LOCAL=y
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_COMPAQ not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_COMPAQ is not set
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_IBM not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_IBM is not set
Actual value:
Value requested for CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH not in final .config
Requested value: CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
Actual value:
Value requested for CONFIG_PCH_PHUB not in final .config
Requested value: # CONFIG_PCH_PHUB is not set
Actual value:
Value requested for CONFIG_SCSI_NSP32 not in final .config
Requested value: # CONFIG_SCSI_NSP32 is not set
Actual value:
Value requested for CONFIG_PATA_CS5520 not in final .config
Requested value: # CONFIG_PATA_CS5520 is not set
Actual value:
Value requested for CONFIG_PATA_CS5530 not in final .config
Requested value: # CONFIG_PATA_CS5530 is not set
Actual value:
Value requested for CONFIG_PATA_CS5535 not in final .config
Requested value: # CONFIG_PATA_CS5535 is not set
Actual value:
Value requested for CONFIG_PATA_CS5536 not in final .config
Requested value: # CONFIG_PATA_CS5536 is not set
Actual value:
Value requested for CONFIG_PATA_SC1200 not in final .config
Requested value: # CONFIG_PATA_SC1200 is not set
Actual value:
Value requested for CONFIG_PCH_GBE not in final .config
Requested value: # CONFIG_PCH_GBE is not set
Actual value:
Value requested for CONFIG_INPUT_WISTRON_BTNS not in final .config
Requested value: # CONFIG_INPUT_WISTRON_BTNS is not set
Actual value:
Value requested for CONFIG_SERIAL_TIMBERDALE not in final .config
Requested value: # CONFIG_SERIAL_TIMBERDALE is not set
Actual value:
Value requested for CONFIG_SERIAL_PCH_UART not in final .config
Requested value: # CONFIG_SERIAL_PCH_UART is not set
Actual value:
Value requested for CONFIG_HW_RANDOM_GEODE not in final .config
Requested value: CONFIG_HW_RANDOM_GEODE=y
Actual value:
Value requested for CONFIG_SONYPI not in final .config
Requested value: # CONFIG_SONYPI is not set
Actual value:
Value requested for CONFIG_PC8736x_GPIO not in final .config
Requested value: # CONFIG_PC8736x_GPIO is not set
Actual value:
Value requested for CONFIG_NSC_GPIO not in final .config
Requested value: # CONFIG_NSC_GPIO is not set
Actual value:
Value requested for CONFIG_I2C_EG20T not in final .config
Requested value: # CONFIG_I2C_EG20T is not set
Actual value:
Value requested for CONFIG_SCx200_ACB not in final .config
Requested value: # CONFIG_SCx200_ACB is not set
Actual value:
Value requested for CONFIG_PTP_1588_CLOCK_PCH not in final .config
Requested value: # CONFIG_PTP_1588_CLOCK_PCH is not set
Actual value:
Value requested for CONFIG_SBC8360_WDT not in final .config
Requested value: # CONFIG_SBC8360_WDT is not set
Actual value:
Value requested for CONFIG_SBC7240_WDT not in final .config
Requested value: # CONFIG_SBC7240_WDT is not set
Actual value:
Value requested for CONFIG_MFD_CS5535 not in final .config
Requested value: # CONFIG_MFD_CS5535 is not set
Actual value:
Value requested for CONFIG_AGP_ALI not in final .config
Requested value: # CONFIG_AGP_ALI is not set
Actual value:
Value requested for CONFIG_AGP_ATI not in final .config
Requested value: # CONFIG_AGP_ATI is not set
Actual value:
Value requested for CONFIG_AGP_AMD not in final .config
Requested value: # CONFIG_AGP_AMD is not set
Actual value:
Value requested for CONFIG_AGP_NVIDIA not in final .config
Requested value: # CONFIG_AGP_NVIDIA is not set
Actual value:
Value requested for CONFIG_AGP_SWORKS not in final .config
Requested value: # CONFIG_AGP_SWORKS is not set
Actual value:
Value requested for CONFIG_AGP_EFFICEON not in final .config
Requested value: # CONFIG_AGP_EFFICEON is not set
Actual value:
Value requested for CONFIG_SND_PCM not in final .config
Requested value: CONFIG_SND_PCM=y
Actual value: CONFIG_SND_PCM=m
Value requested for CONFIG_SND_HWDEP not in final .config
Requested value: CONFIG_SND_HWDEP=y
Actual value: CONFIG_SND_HWDEP=m
Value requested for CONFIG_SND_DYNAMIC_MINORS not in final .config
Requested value: # CONFIG_SND_DYNAMIC_MINORS is not set
Actual value: CONFIG_SND_DYNAMIC_MINORS=y
Value requested for CONFIG_SND_CS5530 not in final .config
Requested value: # CONFIG_SND_CS5530 is not set
Actual value:
Value requested for CONFIG_SND_CS5535AUDIO not in final .config
Requested value: # CONFIG_SND_CS5535AUDIO is not set
Actual value:
Value requested for CONFIG_SND_SIS7019 not in final .config
Requested value: # CONFIG_SND_SIS7019 is not set
Actual value:
Value requested for CONFIG_SND_HDA not in final .config
Requested value: CONFIG_SND_HDA=y
Actual value: CONFIG_SND_HDA=m
Value requested for CONFIG_SND_HDA_CORE not in final .config
Requested value: CONFIG_SND_HDA_CORE=y
Actual value: CONFIG_SND_HDA_CORE=m
Value requested for CONFIG_SND_INTEL_DSP_CONFIG not in final .config
Requested value: CONFIG_SND_INTEL_DSP_CONFIG=y
Actual value: CONFIG_SND_INTEL_DSP_CONFIG=m
Value requested for CONFIG_SND_INTEL_SOUNDWIRE_ACPI not in final .config
Requested value: CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
Actual value: CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
Value requested for CONFIG_LEDS_OT200 not in final .config
Requested value: # CONFIG_LEDS_OT200 is not set
Actual value:
Value requested for CONFIG_PCH_DMA not in final .config
Requested value: # CONFIG_PCH_DMA is not set
Actual value:
Value requested for CONFIG_CLKSRC_I8253 not in final .config
Requested value: CONFIG_CLKSRC_I8253=y
Actual value:
Value requested for CONFIG_MAILBOX not in final .config
Requested value: # CONFIG_MAILBOX is not set
Actual value: CONFIG_MAILBOX=y
Value requested for CONFIG_CRYPTO_SERPENT_SSE2_586 not in final .config
Requested value: # CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_TWOFISH_586 not in final .config
Requested value: # CONFIG_CRYPTO_TWOFISH_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_GEODE not in final .config
Requested value: # CONFIG_CRYPTO_DEV_GEODE is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_HIFN_795X not in final .config
Requested value: # CONFIG_CRYPTO_DEV_HIFN_795X is not set
Actual value:
Value requested for CONFIG_CRYPTO_LIB_POLY1305_RSIZE not in final .config
Requested value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
Actual value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
Value requested for CONFIG_AUDIT_GENERIC not in final .config
Requested value: CONFIG_AUDIT_GENERIC=y
Actual value:
Value requested for CONFIG_GENERIC_VDSO_32 not in final .config
Requested value: CONFIG_GENERIC_VDSO_32=y
Actual value:
Value requested for CONFIG_DEBUG_KMAP_LOCAL not in final .config
Requested value: # CONFIG_DEBUG_KMAP_LOCAL is not set
Actual value:
Value requested for CONFIG_DEBUG_HIGHMEM not in final .config
Requested value: # CONFIG_DEBUG_HIGHMEM is not set
Actual value:
Value requested for CONFIG_HAVE_DEBUG_STACKOVERFLOW not in final .config
Requested value: CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
Actual value:
Value requested for CONFIG_DEBUG_STACKOVERFLOW not in final .config
Requested value: # CONFIG_DEBUG_STACKOVERFLOW is not set
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_TRACER not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_RETVAL not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y
Actual value:
Value requested for CONFIG_DRM_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_KUNIT_TEST=m
Actual value:
Value requested for CONFIG_DRM_XE_WERROR not in final .config
Requested value: CONFIG_DRM_XE_WERROR=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG not in final .config
Requested value: CONFIG_DRM_XE_DEBUG=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG_MEM not in final .config
Requested value: CONFIG_DRM_XE_DEBUG_MEM=y
Actual value:
Value requested for CONFIG_DRM_XE_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_XE_KUNIT_TEST=m
Actual value:
++ nproc
+ make -j48 ARCH=i386 olddefconfig
GEN Makefile
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
#
# configuration written to .config
#
++ nproc
+ make -j48 ARCH=i386
SYNC include/config/auto.conf.cmd
GEN Makefile
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
GEN Makefile
UPD include/generated/uapi/linux/version.h
WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h
WRAP arch/x86/include/generated/uapi/asm/errno.h
WRAP arch/x86/include/generated/uapi/asm/fcntl.h
WRAP arch/x86/include/generated/uapi/asm/ioctl.h
WRAP arch/x86/include/generated/uapi/asm/ioctls.h
WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h
WRAP arch/x86/include/generated/uapi/asm/param.h
WRAP arch/x86/include/generated/uapi/asm/poll.h
WRAP arch/x86/include/generated/uapi/asm/resource.h
WRAP arch/x86/include/generated/uapi/asm/socket.h
WRAP arch/x86/include/generated/uapi/asm/sockios.h
WRAP arch/x86/include/generated/uapi/asm/termbits.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h
WRAP arch/x86/include/generated/uapi/asm/termios.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h
WRAP arch/x86/include/generated/uapi/asm/types.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h
SYSTBL arch/x86/include/generated/asm/syscalls_32.h
UPD include/generated/compile.h
WRAP arch/x86/include/generated/asm/mcs_spinlock.h
HOSTCC arch/x86/tools/relocs_32.o
WRAP arch/x86/include/generated/asm/early_ioremap.h
WRAP arch/x86/include/generated/asm/irq_regs.h
HOSTCC arch/x86/tools/relocs_64.o
WRAP arch/x86/include/generated/asm/kmap_size.h
HOSTCC arch/x86/tools/relocs_common.o
WRAP arch/x86/include/generated/asm/local64.h
WRAP arch/x86/include/generated/asm/mmiowb.h
WRAP arch/x86/include/generated/asm/module.lds.h
WRAP arch/x86/include/generated/asm/rwonce.h
WRAP arch/x86/include/generated/asm/unaligned.h
HOSTCC scripts/kallsyms
HOSTCC scripts/sorttable
HOSTCC scripts/asn1_compiler
HOSTCC scripts/selinux/genheaders/genheaders
HOSTCC scripts/selinux/mdp/mdp
HOSTLD arch/x86/tools/relocs
UPD include/config/kernel.release
UPD include/generated/utsrelease.h
CC scripts/mod/empty.o
HOSTCC scripts/mod/mk_elfconfig
CC scripts/mod/devicetable-offsets.s
UPD scripts/mod/devicetable-offsets.h
MKELF scripts/mod/elfconfig.h
HOSTCC scripts/mod/modpost.o
HOSTCC scripts/mod/file2alias.o
HOSTCC scripts/mod/sumversion.o
HOSTCC scripts/mod/symsearch.o
HOSTLD scripts/mod/modpost
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-arch-fallback.h
CC kernel/bounds.s
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-instrumented.h
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-long.h
UPD include/generated/timeconst.h
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
UPD include/generated/asm-offsets.h
CALL /workspace/kernel/scripts/checksyscalls.sh
LDS scripts/module.lds
CC security/commoncap.o
CC security/lsm_syscalls.o
HOSTCC usr/gen_init_cpio
CC init/main.o
CC security/min_addr.o
CC init/do_mounts.o
CC security/security.o
CC ipc/util.o
AS arch/x86/lib/atomic64_cx8_32.o
CC certs/system_keyring.o
AS arch/x86/lib/checksum_32.o
CC security/lsm_audit.o
CC init/do_mounts_initrd.o
UPD init/utsversion-tmp.h
CC security/device_cgroup.o
CC arch/x86/power/cpu.o
CC arch/x86/lib/cmdline.o
AS arch/x86/lib/cmpxchg8b_emu.o
CC ipc/msgutil.o
CC init/initramfs.o
CC mm/filemap.o
GEN security/selinux/flask.h security/selinux/av_permissions.h
CC arch/x86/video/video-common.o
CC io_uring/io_uring.o
CC arch/x86/pci/i386.o
CC security/integrity/iint.o
AR net/802/built-in.a
CC security/keys/gc.o
CC lib/math/div64.o
AR arch/x86/crypto/built-in.a
AR drivers/cache/built-in.a
CC net/ethernet/eth.o
AR virt/lib/built-in.a
CC net/sched/sch_generic.o
CC net/netlink/af_netlink.o
CC block/partitions/core.o
CC arch/x86/realmode/init.o
AR net/bpf/built-in.a
CC net/core/sock.o
CC security/selinux/avc.o
CC net/ethtool/ioctl.o
CC security/selinux/hooks.o
CC arch/x86/mm/pat/set_memory.o
CC arch/x86/events/amd/core.o
CC arch/x86/mm/pat/memtype.o
CC arch/x86/kernel/fpu/init.o
AR arch/x86/platform/atom/built-in.a
AR arch/x86/platform/ce4100/built-in.a
CC fs/notify/dnotify/dnotify.o
CC sound/core/seq/seq.o
AR drivers/irqchip/built-in.a
CC sound/core/seq/seq_lock.o
AR virt/built-in.a
CC init/calibrate.o
AR drivers/bus/mhi/built-in.a
CC arch/x86/entry/vdso/vma.o
CC arch/x86/platform/efi/memmap.o
AR sound/i2c/other/built-in.a
AR sound/drivers/opl3/built-in.a
AR drivers/bus/built-in.a
AR sound/drivers/opl4/built-in.a
AR sound/i2c/built-in.a
CC arch/x86/power/hibernate_32.o
CC kernel/sched/core.o
AR sound/drivers/mpu401/built-in.a
AR drivers/pwm/built-in.a
AS arch/x86/realmode/rm/header.o
CC crypto/asymmetric_keys/asymmetric_type.o
AR sound/drivers/vx/built-in.a
CC arch/x86/lib/cpu.o
CC drivers/pci/msi/pcidev_msi.o
AR sound/drivers/pcsp/built-in.a
AS arch/x86/realmode/rm/trampoline_32.o
CC lib/math/gcd.o
AR sound/drivers/built-in.a
AS arch/x86/realmode/rm/stack.o
CC crypto/api.o
AS arch/x86/realmode/rm/reboot.o
CC lib/math/lcm.o
AS arch/x86/realmode/rm/wakeup_asm.o
CC arch/x86/realmode/rm/wakemain.o
CC lib/math/int_log.o
CC arch/x86/kernel/fpu/bugs.o
GEN usr/initramfs_data.cpio
COPY usr/initramfs_inc_data
AS usr/initramfs_data.o
CC security/keys/key.o
AR usr/built-in.a
CC init/init_task.o
CC arch/x86/realmode/rm/video-mode.o
CC lib/math/int_pow.o
HOSTCC certs/extract-cert
CC arch/x86/kernel/fpu/core.o
CC arch/x86/mm/pat/memtype_interval.o
CC lib/math/int_sqrt.o
AS arch/x86/realmode/rm/copy.o
CC arch/x86/lib/delay.o
AS arch/x86/realmode/rm/bioscall.o
AR arch/x86/video/built-in.a
CC lib/math/reciprocal_div.o
CC arch/x86/realmode/rm/regs.o
CC lib/math/rational.o
CC arch/x86/kernel/fpu/regset.o
CC sound/core/seq/seq_clientmgr.o
CC arch/x86/realmode/rm/video-vga.o
CC security/integrity/integrity_audit.o
CC kernel/locking/mutex.o
CC crypto/cipher.o
CC block/bdev.o
CC arch/x86/pci/init.o
CERT certs/x509_certificate_list
CERT certs/signing_key.x509
AS certs/system_certificates.o
CC kernel/locking/semaphore.o
AR certs/built-in.a
CC arch/x86/realmode/rm/video-vesa.o
AS arch/x86/power/hibernate_asm_32.o
CC drivers/pci/msi/api.o
CC block/fops.o
CC crypto/asymmetric_keys/restrict.o
CC drivers/video/console/dummycon.o
CC arch/x86/entry/vdso/extable.o
CC arch/x86/platform/efi/quirks.o
LDS arch/x86/entry/vdso/vdso32/vdso32.lds
AS arch/x86/lib/getuser.o
CC arch/x86/power/hibernate.o
CC drivers/video/console/vgacon.o
AR fs/notify/dnotify/built-in.a
GEN arch/x86/lib/inat-tables.c
CC arch/x86/realmode/rm/video-bios.o
CC block/bio.o
CC fs/notify/inotify/inotify_fsnotify.o
CC block/partitions/msdos.o
CC arch/x86/lib/insn-eval.o
CC fs/notify/inotify/inotify_user.o
PASYMS arch/x86/realmode/rm/pasyms.h
AR lib/math/built-in.a
CC init/version.o
LDS arch/x86/realmode/rm/realmode.lds
LD arch/x86/realmode/rm/realmode.elf
RELOCS arch/x86/realmode/rm/realmode.relocs
CC lib/crypto/mpi/generic_mpih-lshift.o
OBJCOPY arch/x86/realmode/rm/realmode.bin
AS arch/x86/realmode/rmpiggy.o
CC crypto/compress.o
AR arch/x86/realmode/built-in.a
CC crypto/asymmetric_keys/signature.o
CC ipc/msg.o
CC kernel/power/qos.o
CC ipc/sem.o
CC ipc/shm.o
CC ipc/syscall.o
CC arch/x86/lib/insn.o
CC crypto/algapi.o
CC arch/x86/events/amd/lbr.o
CC crypto/scatterwalk.o
CC arch/x86/lib/kaslr.o
CC security/selinux/selinuxfs.o
AR net/ethernet/built-in.a
CC arch/x86/pci/pcbios.o
CC drivers/pci/msi/msi.o
CC security/keys/keyring.o
AR security/integrity/built-in.a
CC security/keys/keyctl.o
CC kernel/locking/rwsem.o
CC lib/crypto/mpi/generic_mpih-mul1.o
AR arch/x86/mm/pat/built-in.a
CC kernel/locking/percpu-rwsem.o
CC arch/x86/mm/init.o
CC security/keys/permission.o
AR init/built-in.a
CC drivers/video/backlight/backlight.o
CC drivers/pci/pcie/portdrv.o
CC net/core/request_sock.o
CC net/core/skbuff.o
AR arch/x86/power/built-in.a
AS arch/x86/entry/vdso/vdso32/note.o
CC crypto/asymmetric_keys/public_key.o
CC arch/x86/lib/memcpy_32.o
ASN.1 crypto/asymmetric_keys/x509.asn1.[ch]
CC net/netlink/genetlink.o
AS arch/x86/entry/vdso/vdso32/system_call.o
CC drivers/pci/pcie/rcec.o
AS arch/x86/entry/vdso/vdso32/sigreturn.o
CC arch/x86/kernel/fpu/signal.o
CC kernel/power/main.o
CC net/netlink/policy.o
CC arch/x86/entry/vdso/vdso32/vclock_gettime.o
CC arch/x86/platform/efi/efi.o
CC block/partitions/efi.o
AS arch/x86/lib/memmove_32.o
CC arch/x86/lib/misc.o
CC block/elevator.o
AR drivers/video/console/built-in.a
CC ipc/ipc_sysctl.o
CC sound/core/seq/seq_memory.o
CC arch/x86/lib/pc-conf-reg.o
CC block/blk-core.o
AR drivers/video/fbdev/core/built-in.a
CC crypto/proc.o
AR drivers/video/fbdev/omap/built-in.a
AR fs/notify/inotify/built-in.a
CC net/sched/sch_mq.o
CC crypto/aead.o
AR fs/notify/fanotify/built-in.a
CC fs/notify/fsnotify.o
AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a
CC lib/crypto/mpi/generic_mpih-mul2.o
AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a
AR drivers/video/fbdev/omap2/omapfb/built-in.a
AR drivers/video/fbdev/omap2/built-in.a
AR drivers/video/fbdev/built-in.a
CC lib/zlib_inflate/inffast.o
CC lib/zlib_deflate/deflate.o
CC arch/x86/pci/mmconfig_32.o
AS arch/x86/lib/putuser.o
AS arch/x86/lib/retpoline.o
CC arch/x86/mm/init_32.o
CC arch/x86/lib/string_32.o
CC arch/x86/events/amd/ibs.o
ASN.1 crypto/asymmetric_keys/x509_akid.asn1.[ch]
CC crypto/asymmetric_keys/x509_loader.o
CC lib/lzo/lzo1x_compress.o
CC lib/zlib_inflate/inflate.o
CC kernel/locking/spinlock.o
CC arch/x86/lib/strstr_32.o
CC lib/lzo/lzo1x_decompress_safe.o
AR drivers/pci/pwrctl/built-in.a
CC arch/x86/lib/usercopy.o
CC security/keys/process_keys.o
CC drivers/pci/pcie/aspm.o
CC ipc/mqueue.o
CC drivers/pci/msi/irqdomain.o
CC drivers/video/aperture.o
CC kernel/locking/osq_lock.o
CC lib/lz4/lz4_decompress.o
CC arch/x86/entry/vdso/vdso32/vgetcpu.o
CC kernel/locking/qspinlock.o
CC crypto/asymmetric_keys/x509_public_key.o
AR drivers/video/backlight/built-in.a
CC fs/nfs_common/nfsacl.o
HOSTCC arch/x86/entry/vdso/vdso2c
CC fs/nfs_common/grace.o
CC arch/x86/kernel/fpu/xstate.o
CC lib/zlib_deflate/deftree.o
CC arch/x86/platform/efi/efi_32.o
CC crypto/geniv.o
CC lib/zlib_inflate/infutil.o
CC lib/crypto/mpi/generic_mpih-mul3.o
CC arch/x86/lib/usercopy_32.o
CC lib/zlib_inflate/inftrees.o
CC net/ethtool/common.o
CC net/sched/sch_frag.o
CC sound/core/seq/seq_queue.o
CC lib/crypto/memneq.o
AR block/partitions/built-in.a
CC net/sched/sch_api.o
CC kernel/power/console.o
CC net/sched/sch_blackhole.o
CC sound/core/seq/seq_fifo.o
CC lib/crypto/utils.o
CC arch/x86/pci/direct.o
AR lib/lzo/built-in.a
AS arch/x86/platform/efi/efi_stub_32.o
CC lib/zstd/zstd_decompress_module.o
CC lib/xz/xz_dec_syms.o
CC crypto/lskcipher.o
CC security/selinux/netlink.o
CC fs/notify/notification.o
CC security/selinux/nlmsgtab.o
CC arch/x86/entry/vdso/vdso32-setup.o
CC arch/x86/lib/msr-smp.o
CC lib/zlib_inflate/inflate_syms.o
CC arch/x86/platform/efi/runtime-map.o
CC arch/x86/lib/cache-smp.o
CC mm/mempool.o
CC kernel/locking/rtmutex_api.o
CC kernel/printk/printk.o
CC security/selinux/netif.o
CC arch/x86/lib/msr.o
ASN.1 crypto/asymmetric_keys/pkcs7.asn1.[ch]
CC crypto/asymmetric_keys/pkcs7_trust.o
CC arch/x86/mm/fault.o
AS arch/x86/lib/msr-reg.o
CC lib/zlib_deflate/deflate_syms.o
CC kernel/printk/printk_safe.o
CC arch/x86/lib/msr-reg-export.o
CC lib/crypto/mpi/generic_mpih-rshift.o
AR drivers/pci/msi/built-in.a
CC lib/crypto/chacha.o
CC lib/xz/xz_dec_stream.o
CC crypto/skcipher.o
AR net/netlink/built-in.a
CC kernel/printk/nbcon.o
CC drivers/pci/hotplug/pci_hotplug_core.o
VDSO arch/x86/entry/vdso/vdso32.so.dbg
CC lib/zstd/decompress/huf_decompress.o
CC kernel/printk/printk_ringbuffer.o
CC drivers/video/cmdline.o
OBJCOPY arch/x86/entry/vdso/vdso32.so
VDSO2C arch/x86/entry/vdso/vdso-image-32.c
CC arch/x86/entry/vdso/vdso-image-32.o
AR lib/zlib_inflate/built-in.a
CC kernel/locking/qrwlock.o
CC lib/crypto/mpi/generic_mpih-sub1.o
AR fs/nfs_common/built-in.a
CC block/blk-sysfs.o
CC net/netfilter/core.o
CC lib/crypto/aes.o
CC drivers/pci/pcie/pme.o
CC security/keys/request_key.o
CC kernel/power/process.o
CC drivers/pci/hotplug/acpi_pcihp.o
CC arch/x86/events/amd/uncore.o
CC crypto/asymmetric_keys/pkcs7_verify.o
AR lib/zlib_deflate/built-in.a
CC kernel/power/suspend.o
CC sound/core/seq/seq_prioq.o
AR arch/x86/entry/vdso/built-in.a
CC arch/x86/pci/mmconfig-shared.o
AR arch/x86/entry/vsyscall/built-in.a
CC fs/notify/group.o
AS arch/x86/entry/entry.o
AS arch/x86/entry/entry_32.o
CC sound/core/sound.o
CC security/keys/request_key_auth.o
CC net/ethtool/netlink.o
CC arch/x86/entry/syscall_32.o
AR lib/lz4/built-in.a
CC fs/notify/mark.o
CC crypto/seqiv.o
AR arch/x86/platform/efi/built-in.a
AR arch/x86/kernel/fpu/built-in.a
CC lib/xz/xz_dec_lzma2.o
CC fs/notify/fdinfo.o
AR arch/x86/platform/geode/built-in.a
AR arch/x86/platform/iris/built-in.a
CC security/selinux/netnode.o
CC arch/x86/kernel/cpu/mce/core.o
CC crypto/echainiv.o
CC mm/oom_kill.o
CC kernel/sched/fair.o
CC security/selinux/netport.o
CC arch/x86/platform/intel/iosf_mbi.o
CC lib/crypto/mpi/generic_mpih-add1.o
CC lib/crypto/arc4.o
CC arch/x86/kernel/cpu/mtrr/mtrr.o
CC arch/x86/kernel/cpu/microcode/core.o
CC io_uring/opdef.o
CC arch/x86/kernel/cpu/microcode/intel.o
CC ipc/namespace.o
CC arch/x86/kernel/cpu/microcode/amd.o
CC crypto/asymmetric_keys/x509.asn1.o
CC crypto/asymmetric_keys/x509_akid.asn1.o
CC drivers/video/nomodeset.o
AR kernel/locking/built-in.a
CC io_uring/kbuf.o
CC io_uring/rsrc.o
AS arch/x86/lib/hweight.o
CC crypto/asymmetric_keys/x509_cert_parser.o
CC arch/x86/lib/iomem.o
CC net/core/datagram.o
CC sound/core/seq/seq_timer.o
AR drivers/pci/pcie/built-in.a
AR drivers/pci/hotplug/built-in.a
AR drivers/idle/built-in.a
AR drivers/pci/controller/dwc/built-in.a
AR drivers/pci/controller/mobiveil/built-in.a
CC crypto/asymmetric_keys/pkcs7.asn1.o
CC ipc/mq_sysctl.o
AR drivers/pci/controller/plda/built-in.a
AR drivers/pci/controller/built-in.a
AR sound/isa/ad1816a/built-in.a
AR sound/isa/ad1848/built-in.a
AR sound/isa/cs423x/built-in.a
CC crypto/asymmetric_keys/pkcs7_parser.o
CC block/blk-flush.o
AR drivers/pci/switch/built-in.a
CC lib/xz/xz_dec_bcj.o
CC security/keys/user_defined.o
CC drivers/pci/access.o
AR sound/isa/es1688/built-in.a
CC arch/x86/kernel/cpu/mce/severity.o
AR sound/isa/galaxy/built-in.a
AR sound/isa/gus/built-in.a
CC block/blk-settings.o
CC arch/x86/kernel/cpu/mce/genpool.o
AR sound/isa/msnd/built-in.a
CC arch/x86/kernel/acpi/boot.o
AR sound/isa/opti9xx/built-in.a
CC sound/core/seq/seq_system.o
CC drivers/video/hdmi.o
CC lib/crypto/mpi/ec.o
CC lib/zstd/decompress/zstd_ddict.o
CC lib/zstd/decompress/zstd_decompress.o
AR sound/isa/sb/built-in.a
AR sound/isa/wavefront/built-in.a
CC arch/x86/lib/atomic64_32.o
AR arch/x86/platform/intel/built-in.a
AR sound/isa/wss/built-in.a
AR sound/isa/built-in.a
CC lib/crypto/mpi/mpicoder.o
CC arch/x86/pci/fixup.o
AR arch/x86/platform/intel-mid/built-in.a
AR arch/x86/platform/intel-quark/built-in.a
CC block/blk-ioc.o
CC arch/x86/mm/ioremap.o
AR arch/x86/platform/olpc/built-in.a
CC arch/x86/lib/inat.o
CC kernel/irq/irqdesc.o
AR arch/x86/events/amd/built-in.a
AR sound/pci/ac97/built-in.a
CC lib/crypto/gf128mul.o
AR arch/x86/platform/scx200/built-in.a
AR fs/notify/built-in.a
AR sound/pci/ali5451/built-in.a
CC arch/x86/kernel/cpu/mtrr/if.o
CC arch/x86/kernel/cpu/mtrr/generic.o
AR arch/x86/platform/ts5500/built-in.a
CC arch/x86/events/intel/core.o
AR sound/pci/asihpi/built-in.a
CC fs/iomap/trace.o
AR ipc/built-in.a
AR arch/x86/platform/uv/built-in.a
CC lib/crypto/blake2s.o
AR sound/pci/au88x0/built-in.a
AR arch/x86/platform/built-in.a
CC net/sched/cls_api.o
CC kernel/irq/handle.o
CC kernel/power/hibernate.o
AR sound/pci/aw2/built-in.a
AR sound/pci/ctxfi/built-in.a
CC kernel/power/snapshot.o
AR sound/pci/ca0106/built-in.a
AR lib/xz/built-in.a
CC arch/x86/kernel/cpu/mtrr/cleanup.o
CC kernel/rcu/update.o
CC arch/x86/kernel/cpu/mtrr/amd.o
AR sound/pci/cs46xx/built-in.a
CC sound/core/init.o
AR arch/x86/lib/built-in.a
CC net/netfilter/nf_log.o
AR sound/pci/cs5535audio/built-in.a
AR arch/x86/lib/lib.a
AR sound/pci/lola/built-in.a
AR sound/pci/lx6464es/built-in.a
AR arch/x86/kernel/cpu/microcode/built-in.a
CC io_uring/notif.o
AR crypto/asymmetric_keys/built-in.a
AR sound/pci/echoaudio/built-in.a
CC crypto/ahash.o
AR sound/pci/emu10k1/built-in.a
CC fs/iomap/iter.o
AR sound/pci/hda/built-in.a
CC [M] sound/pci/hda/hda_bind.o
CC lib/crypto/mpi/mpi-add.o
CC security/keys/proc.o
CC arch/x86/kernel/cpu/cacheinfo.o
CC security/selinux/status.o
CC net/ethtool/bitset.o
CC arch/x86/entry/common.o
CC sound/core/seq/seq_ports.o
CC block/blk-map.o
CC kernel/printk/sysctl.o
CC mm/fadvise.o
CC arch/x86/events/intel/bts.o
CC lib/crypto/mpi/mpi-bit.o
CC drivers/pci/bus.o
CC lib/dim/dim.o
CC lib/zstd/decompress/zstd_decompress_block.o
CC lib/dim/net_dim.o
CC kernel/irq/manage.o
AR drivers/video/built-in.a
CC kernel/irq/spurious.o
AR drivers/char/ipmi/built-in.a
AR kernel/printk/built-in.a
CC kernel/irq/resend.o
CC lib/dim/rdma_dim.o
CC net/sched/act_api.o
AR kernel/livepatch/built-in.a
CC arch/x86/kernel/cpu/mtrr/cyrix.o
CC arch/x86/pci/acpi.o
CC block/blk-merge.o
CC kernel/irq/chip.o
CC block/blk-timeout.o
CC kernel/sched/build_policy.o
CC arch/x86/mm/extable.o
CC arch/x86/kernel/cpu/mtrr/centaur.o
CC arch/x86/kernel/acpi/sleep.o
CC arch/x86/kernel/cpu/mce/intel.o
CC kernel/irq/dummychip.o
CC lib/fonts/fonts.o
CC arch/x86/events/intel/ds.o
CC security/keys/sysctl.o
CC [M] sound/pci/hda/hda_codec.o
CC lib/fonts/font_8x16.o
AR sound/pci/ice1712/built-in.a
AS arch/x86/kernel/acpi/wakeup_32.o
CC io_uring/tctx.o
CC lib/crypto/mpi/mpi-cmp.o
CC drivers/pci/probe.o
CC fs/iomap/buffered-io.o
CC sound/core/seq/seq_info.o
CC kernel/irq/devres.o
CC net/sched/sch_fifo.o
CC kernel/irq/autoprobe.o
AS arch/x86/entry/thunk.o
CC crypto/shash.o
CC lib/crypto/mpi/mpi-sub-ui.o
CC mm/maccess.o
AR arch/x86/entry/built-in.a
CC arch/x86/kernel/cpu/mtrr/legacy.o
CC arch/x86/kernel/cpu/scattered.o
AR arch/x86/net/built-in.a
CC net/netfilter/nf_queue.o
CC arch/x86/kernel/cpu/topology_common.o
CC io_uring/filetable.o
CC lib/crypto/mpi/mpi-div.o
CC kernel/dma/mapping.o
CC crypto/akcipher.o
CC kernel/dma/direct.o
CC net/sched/cls_cgroup.o
AR lib/fonts/built-in.a
CC kernel/irq/irqdomain.o
CC kernel/dma/ops_helpers.o
CC sound/core/memory.o
CC arch/x86/pci/legacy.o
CC lib/argv_split.o
CC security/selinux/ss/ebitmap.o
CC arch/x86/pci/irq.o
CC security/keys/keyctl_pkey.o
CC arch/x86/kernel/cpu/mce/amd.o
AR lib/dim/built-in.a
CC lib/bug.o
CC arch/x86/kernel/acpi/cstate.o
CC net/ethtool/strset.o
CC mm/page-writeback.o
CC sound/core/seq/seq_dummy.o
AR arch/x86/kernel/cpu/mtrr/built-in.a
CC arch/x86/mm/mmap.o
CC net/core/stream.o
CC arch/x86/pci/common.o
CC kernel/power/swap.o
CC net/core/scm.o
CC net/core/gen_stats.o
CC net/core/gen_estimator.o
CC arch/x86/kernel/cpu/mce/threshold.o
CC [M] sound/pci/hda/hda_jack.o
CC arch/x86/kernel/cpu/topology_ext.o
CC lib/crypto/mpi/mpi-inv.o
AR sound/pci/korg1212/built-in.a
AR sound/pci/mixart/built-in.a
AR sound/pci/nm256/built-in.a
AR sound/pci/oxygen/built-in.a
AR sound/pci/pcxhr/built-in.a
CC fs/quota/dquot.o
CC lib/crypto/mpi/mpi-mod.o
CC fs/proc/task_mmu.o
CC sound/core/control.o
CC fs/proc/inode.o
CC kernel/entry/common.o
CC fs/proc/root.o
CC crypto/sig.o
AR security/keys/built-in.a
CC crypto/kpp.o
AR arch/x86/kernel/acpi/built-in.a
CC net/core/net_namespace.o
CC kernel/rcu/sync.o
CC kernel/module/main.o
AR sound/core/seq/built-in.a
CC fs/proc/base.o
CC kernel/module/strict_rwx.o
CC io_uring/rw.o
CC kernel/module/kmod.o
CC arch/x86/mm/pgtable.o
CC sound/core/misc.o
CC block/blk-lib.o
CC kernel/dma/dummy.o
CC kernel/rcu/srcutree.o
CC arch/x86/kernel/apic/apic.o
CC arch/x86/kernel/apic/apic_common.o
CC block/blk-mq.o
CC net/netfilter/nf_sockopt.o
CC arch/x86/kernel/apic/apic_noop.o
CC lib/zstd/zstd_common_module.o
CC arch/x86/kernel/apic/ipi.o
CC lib/crypto/mpi/mpi-mul.o
CC arch/x86/pci/early.o
CC security/selinux/ss/hashtab.o
CC arch/x86/events/intel/knc.o
CC kernel/irq/proc.o
CC drivers/pci/host-bridge.o
CC net/core/secure_seq.o
CC arch/x86/events/zhaoxin/core.o
CC net/ethtool/linkinfo.o
CC net/sched/ematch.o
CC fs/proc/generic.o
CC arch/x86/mm/physaddr.o
CC sound/core/device.o
CC net/netfilter/utils.o
ASN.1 crypto/rsapubkey.asn1.[ch]
CC fs/proc/array.o
CC kernel/power/user.o
CC block/blk-mq-tag.o
ASN.1 crypto/rsaprivkey.asn1.[ch]
CC arch/x86/events/intel/lbr.o
CC kernel/power/poweroff.o
CC crypto/rsa.o
CC [M] sound/pci/hda/hda_auto_parser.o
CC kernel/dma/remap.o
CC sound/core/info.o
CC net/core/flow_dissector.o
CC fs/kernfs/mount.o
CC lib/zstd/common/debug.o
CC security/selinux/ss/symtab.o
CC lib/zstd/common/entropy_common.o
CC arch/x86/kernel/apic/vector.o
CC drivers/pci/remove.o
CC kernel/entry/syscall_user_dispatch.o
AR arch/x86/kernel/cpu/mce/built-in.a
CC arch/x86/kernel/cpu/topology_amd.o
CC drivers/pci/pci.o
CC arch/x86/kernel/apic/init.o
CC fs/iomap/direct-io.o
CC lib/crypto/mpi/mpih-cmp.o
CC fs/kernfs/inode.o
CC lib/zstd/common/error_private.o
CC arch/x86/pci/bus_numa.o
CC arch/x86/events/intel/p4.o
CC lib/crypto/mpi/mpih-div.o
CC lib/zstd/common/fse_decompress.o
CC security/selinux/ss/sidtab.o
CC sound/core/isadma.o
CC arch/x86/mm/tlb.o
CC drivers/pci/pci-driver.o
CC kernel/irq/migration.o
CC fs/sysfs/file.o
CC net/netfilter/nfnetlink.o
CC fs/sysfs/dir.o
CC kernel/rcu/tree.o
CC arch/x86/events/intel/p6.o
CC arch/x86/kernel/cpu/common.o
CC arch/x86/kernel/cpu/rdrand.o
CC mm/folio-compat.o
AR kernel/dma/built-in.a
CC crypto/rsa_helper.o
CC io_uring/net.o
CC fs/proc/fd.o
CC fs/sysfs/symlink.o
AR arch/x86/events/zhaoxin/built-in.a
CC arch/x86/events/core.o
AR kernel/power/built-in.a
AR kernel/entry/built-in.a
CC arch/x86/events/probe.o
CC io_uring/poll.o
CC kernel/rcu/rcu_segcblist.o
CC net/core/sysctl_net_core.o
CC drivers/pci/search.o
CC crypto/rsa-pkcs1pad.o
CC net/ethtool/linkmodes.o
CC mm/readahead.o
CC fs/iomap/fiemap.o
CC net/ethtool/rss.o
CC lib/zstd/common/zstd_common.o
AR net/sched/built-in.a
CC fs/proc/proc_tty.o
CC kernel/module/tree_lookup.o
CC kernel/irq/cpuhotplug.o
CC arch/x86/pci/amd_bus.o
AR lib/zstd/built-in.a
CC arch/x86/mm/cpu_entry_area.o
CC sound/core/vmaster.o
CC [M] sound/pci/hda/hda_sysfs.o
CC fs/quota/quota_v2.o
CC sound/core/ctljack.o
CC fs/kernfs/dir.o
CC fs/proc/cmdline.o
CC lib/crypto/mpi/mpih-mul.o
CC lib/crypto/mpi/mpi-pow.o
CC lib/crypto/mpi/mpiutil.o
CC arch/x86/mm/maccess.o
CC net/ethtool/linkstate.o
CC mm/swap.o
CC fs/kernfs/file.o
CC arch/x86/events/utils.o
CC arch/x86/events/rapl.o
CC kernel/module/kallsyms.o
CC net/netfilter/nfnetlink_log.o
CC lib/buildid.o
CC lib/crypto/blake2s-generic.o
CC fs/kernfs/symlink.o
CC fs/sysfs/mount.o
CC io_uring/eventfd.o
CC arch/x86/events/intel/pt.o
CC net/core/dev.o
CC kernel/sched/build_utility.o
CC fs/iomap/seek.o
CC drivers/pci/rom.o
CC security/selinux/ss/avtab.o
AR sound/pci/riptide/built-in.a
AR sound/pci/rme9652/built-in.a
CC crypto/acompress.o
AR sound/pci/trident/built-in.a
AR sound/pci/ymfpci/built-in.a
CC sound/core/jack.o
CC sound/core/timer.o
AR sound/pci/vx222/built-in.a
CC arch/x86/mm/pgprot.o
CC sound/core/hrtimer.o
CC fs/proc/consoles.o
CC fs/iomap/swapfile.o
AR arch/x86/pci/built-in.a
CC arch/x86/mm/pgtable_32.o
CC arch/x86/kernel/apic/hw_nmi.o
CC fs/quota/quota_tree.o
CC kernel/irq/pm.o
CC arch/x86/mm/iomap_32.o
CC [M] sound/pci/hda/hda_controller.o
CC net/core/dev_addr_lists.o
CC net/ethtool/debug.o
CC net/ethtool/wol.o
CC net/core/dst.o
AR sound/ppc/built-in.a
CC net/core/netevent.o
CC arch/x86/mm/hugetlbpage.o
AR lib/crypto/mpi/built-in.a
CC lib/crypto/sha1.o
CC fs/proc/cpuinfo.o
CC kernel/module/procfs.o
CC net/core/neighbour.o
CC arch/x86/kernel/apic/io_apic.o
CC io_uring/uring_cmd.o
CC arch/x86/mm/dump_pagetables.o
CC sound/core/seq_device.o
CC fs/proc/devices.o
CC arch/x86/kernel/cpu/match.o
CC fs/sysfs/group.o
CC kernel/time/time.o
CC kernel/futex/core.o
CC [M] sound/core/hwdep.o
CC kernel/futex/syscalls.o
CC drivers/pci/setup-res.o
CC crypto/scompress.o
AR fs/kernfs/built-in.a
CC drivers/pci/irq.o
CC fs/devpts/inode.o
CC arch/x86/kernel/cpu/bugs.o
CC net/ethtool/features.o
CC [M] sound/core/pcm.o
CC arch/x86/mm/highmem_32.o
CC lib/crypto/sha256.o
AR fs/iomap/built-in.a
CC [M] sound/core/pcm_native.o
CC fs/netfs/buffered_read.o
CC net/ethtool/privflags.o
CC fs/netfs/buffered_write.o
CC kernel/irq/msi.o
CC kernel/irq/affinity.o
CC fs/quota/quota.o
CC arch/x86/kernel/cpu/aperfmperf.o
CC mm/truncate.o
CC kernel/module/sysfs.o
CC arch/x86/kernel/cpu/cpuid-deps.o
CC [M] sound/core/pcm_lib.o
CC security/selinux/ss/policydb.o
CC lib/clz_tab.o
CC kernel/futex/pi.o
CC fs/proc/interrupts.o
CC arch/x86/events/intel/uncore.o
CC arch/x86/events/intel/uncore_nhmex.o
CC block/blk-stat.o
CC kernel/cgroup/cgroup.o
CC kernel/trace/trace_clock.o
CC lib/cmdline.o
CC net/netfilter/nf_conntrack_core.o
CC kernel/cgroup/rstat.o
CC kernel/trace/ring_buffer.o
AR fs/sysfs/built-in.a
CC arch/x86/events/msr.o
CC kernel/bpf/core.o
CC kernel/irq/matrix.o
CC net/core/rtnetlink.o
CC fs/proc/loadavg.o
CC net/ethtool/rings.o
AR lib/crypto/built-in.a
CC crypto/algboss.o
CC lib/cpumask.o
CC drivers/pci/vpd.o
AR fs/devpts/built-in.a
CC kernel/futex/requeue.o
CC kernel/futex/waitwake.o
CC arch/x86/kernel/cpu/umwait.o
CC fs/ext4/balloc.o
CC drivers/pci/setup-bus.o
CC fs/ext4/bitmap.o
AR arch/x86/mm/built-in.a
CC kernel/time/timer.o
CC fs/ext4/block_validity.o
CC fs/jbd2/transaction.o
CC mm/vmscan.o
CC fs/jbd2/commit.o
CC kernel/trace/trace.o
CC [M] sound/pci/hda/hda_proc.o
CC fs/jbd2/recovery.o
CC io_uring/openclose.o
AR kernel/module/built-in.a
CC kernel/events/core.o
CC kernel/fork.o
CC kernel/events/ring_buffer.o
CC fs/proc/meminfo.o
CC block/blk-mq-sysfs.o
CC kernel/events/callchain.o
CC net/ethtool/channels.o
CC lib/ctype.o
CC fs/quota/kqid.o
CC lib/dec_and_lock.o
CC fs/ext4/dir.o
CC fs/netfs/direct_read.o
CC arch/x86/kernel/apic/msi.o
CC lib/decompress.o
CC [M] sound/core/pcm_misc.o
CC crypto/testmgr.o
AR kernel/futex/built-in.a
CC net/netfilter/nf_conntrack_standalone.o
CC mm/shrinker.o
CC lib/decompress_bunzip2.o
CC drivers/pci/vc.o
CC fs/quota/netlink.o
CC arch/x86/kernel/apic/probe_32.o
MKCAP arch/x86/kernel/cpu/capflags.c
CC arch/x86/events/intel/uncore_snb.o
CC fs/netfs/direct_write.o
CC lib/decompress_inflate.o
CC kernel/cgroup/namespace.o
CC mm/shmem.o
AR kernel/irq/built-in.a
CC net/ethtool/coalesce.o
CC drivers/acpi/acpica/dsargs.o
CC net/ethtool/pause.o
CC fs/proc/stat.o
CC block/blk-mq-cpumap.o
CC [M] sound/pci/hda/hda_hwdep.o
CC drivers/acpi/acpica/dscontrol.o
CC drivers/acpi/acpica/dsdebug.o
CC crypto/cmac.o
CC io_uring/sqpoll.o
CC arch/x86/events/intel/uncore_snbep.o
CC arch/x86/events/intel/uncore_discovery.o
AR kernel/rcu/built-in.a
AR arch/x86/kernel/apic/built-in.a
CC [M] sound/core/pcm_memory.o
CC arch/x86/kernel/kprobes/core.o
CC [M] sound/core/memalloc.o
CC [M] sound/core/pcm_timer.o
LD [M] sound/core/snd-hwdep.o
CC arch/x86/events/intel/cstate.o
CC fs/proc/uptime.o
CC net/core/utils.o
CC arch/x86/kernel/kprobes/opt.o
CC net/core/link_watch.o
CC lib/decompress_unlz4.o
CC lib/decompress_unlzma.o
CC drivers/pci/mmap.o
CC io_uring/xattr.o
CC fs/jbd2/checkpoint.o
AR fs/quota/built-in.a
CC drivers/acpi/acpica/dsfield.o
CC drivers/acpi/acpica/dsinit.o
CC fs/ramfs/inode.o
CC fs/hugetlbfs/inode.o
CC crypto/hmac.o
CC fs/ramfs/file-mmu.o
CC fs/proc/util.o
CC net/core/filter.o
CC fs/proc/version.o
CC net/core/sock_diag.o
CC [M] sound/pci/hda/patch_hdmi.o
CC fs/netfs/io.o
CC block/blk-mq-sched.o
CC net/netfilter/nf_conntrack_expect.o
CC kernel/time/hrtimer.o
AR kernel/sched/built-in.a
CC kernel/time/timekeeping.o
CC lib/decompress_unlzo.o
CC crypto/crypto_null.o
CC security/selinux/ss/services.o
CC fs/netfs/iterator.o
CC security/selinux/ss/conditional.o
CC fs/ext4/ext4_jbd2.o
CC kernel/trace/trace_output.o
CC drivers/acpi/acpica/dsmethod.o
CC kernel/trace/trace_seq.o
CC fs/netfs/locking.o
CC drivers/pci/devres.o
CC fs/netfs/main.o
AR sound/core/built-in.a
LD [M] sound/core/snd-pcm.o
CC lib/decompress_unxz.o
AR arch/x86/virt/svm/built-in.a
AR arch/x86/kernel/kprobes/built-in.a
AR arch/x86/virt/vmx/built-in.a
CC fs/fat/cache.o
AR arch/x86/virt/built-in.a
LDS arch/x86/kernel/vmlinux.lds
CC net/ethtool/eee.o
AR sound/arm/built-in.a
AS arch/x86/kernel/head_32.o
AR sound/sh/built-in.a
CC fs/proc/softirqs.o
CC arch/x86/kernel/head32.o
AR sound/synth/emux/built-in.a
CC arch/x86/kernel/ebda.o
AR sound/synth/built-in.a
AR fs/ramfs/built-in.a
CC net/ethtool/tsinfo.o
CC net/ethtool/cabletest.o
CC fs/isofs/namei.o
CC net/ipv4/route.o
CC net/ipv4/netfilter/nf_defrag_ipv4.o
CC net/ipv4/inetpeer.o
CC net/ipv4/protocol.o
CC drivers/acpi/acpica/dsmthdat.o
AR kernel/bpf/built-in.a
CC fs/isofs/inode.o
CC net/core/dev_ioctl.o
CC crypto/md5.o
CC fs/jbd2/revoke.o
CC crypto/sha256_generic.o
CC kernel/exec_domain.o
CC fs/netfs/misc.o
CC io_uring/nop.o
CC lib/decompress_unzstd.o
AR fs/hugetlbfs/built-in.a
CC security/selinux/ss/mls.o
CC fs/proc/namespaces.o
CC block/ioctl.o
CC drivers/pci/proc.o
CC [M] sound/pci/hda/hda_eld.o
CC drivers/acpi/acpica/dsobject.o
CC crypto/sha512_generic.o
CC fs/jbd2/journal.o
CC net/ipv4/netfilter/nf_reject_ipv4.o
CC fs/netfs/objects.o
CC drivers/pnp/pnpacpi/core.o
CC fs/fat/dir.o
CC fs/proc/self.o
CC fs/isofs/dir.o
CC mm/util.o
CC lib/dump_stack.o
CC net/netfilter/nf_conntrack_helper.o
CC fs/proc/thread_self.o
CC security/selinux/ss/context.o
CC crypto/sha3_generic.o
CC arch/x86/kernel/cpu/powerflags.o
CC drivers/pnp/pnpacpi/rsparser.o
CC fs/netfs/write_collect.o
CC kernel/panic.o
CC fs/netfs/write_issue.o
CC kernel/time/ntp.o
CC kernel/cgroup/cgroup-v1.o
CC drivers/acpi/acpica/dsopcode.o
CC kernel/cpu.o
CC lib/earlycpio.o
CC net/ipv4/ip_input.o
AR arch/x86/events/intel/built-in.a
CC crypto/ecb.o
AR arch/x86/events/built-in.a
CC kernel/trace/trace_stat.o
CC kernel/trace/trace_printk.o
CC net/ethtool/tunnels.o
CC crypto/cbc.o
AR drivers/acpi/pmic/built-in.a
CC net/ipv4/netfilter/ip_tables.o
CC kernel/exit.o
CC io_uring/fs.o
CC net/ipv4/ip_fragment.o
CC fs/proc/proc_sysctl.o
CC net/ipv4/ip_forward.o
CC kernel/softirq.o
CC net/xfrm/xfrm_policy.o
CC net/unix/af_unix.o
CC drivers/pci/pci-sysfs.o
CC net/ipv6/af_inet6.o
CC net/ipv6/netfilter/ip6_tables.o
CC block/genhd.o
CC block/ioprio.o
CC net/ipv6/netfilter/ip6table_filter.o
CC lib/extable.o
CC fs/isofs/util.o
CC lib/flex_proportions.o
CC [M] sound/pci/hda/hda_intel.o
CC drivers/acpi/acpica/dspkginit.o
CC drivers/acpi/acpica/dsutils.o
CC crypto/ctr.o
CC crypto/gcm.o
CC io_uring/splice.o
CC fs/ext4/extents.o
CC kernel/time/clocksource.o
CC security/selinux/netlabel.o
CC drivers/pnp/core.o
AR drivers/pnp/pnpacpi/built-in.a
CC drivers/pnp/card.o
CC kernel/resource.o
CC mm/mmzone.o
CC lib/idr.o
CC drivers/acpi/acpica/dswexec.o
CC net/ipv4/ip_options.o
CC net/ipv4/ip_output.o
CC kernel/trace/pid_list.o
CC net/unix/garbage.o
CC drivers/acpi/acpica/dswload.o
CC net/netfilter/nf_conntrack_proto.o
CC net/netfilter/nf_conntrack_proto_generic.o
CC fs/isofs/rock.o
CC arch/x86/kernel/cpu/topology.o
CC arch/x86/kernel/cpu/proc.o
CC fs/fat/fatent.o
CC net/ipv4/netfilter/iptable_filter.o
CC net/ethtool/fec.o
AR fs/netfs/built-in.a
LD [M] sound/pci/hda/snd-hda-codec.o
CC fs/ext4/extents_status.o
CC lib/irq_regs.o
CC net/ipv6/anycast.o
CC mm/vmstat.o
CC net/xfrm/xfrm_state.o
CC drivers/acpi/acpica/dswload2.o
CC kernel/cgroup/freezer.o
CC arch/x86/kernel/cpu/feat_ctl.o
CC net/core/tso.o
CC drivers/pci/slot.o
CC net/xfrm/xfrm_hash.o
CC drivers/pci/pci-acpi.o
CC io_uring/sync.o
CC block/badblocks.o
CC lib/is_single_threaded.o
CC drivers/pnp/driver.o
CC net/ipv6/netfilter/ip6table_mangle.o
CC kernel/cgroup/legacy_freezer.o
CC net/ethtool/eeprom.o
CC crypto/ccm.o
CC crypto/aes_generic.o
CC kernel/time/jiffies.o
CC crypto/crc32c_generic.o
CC kernel/trace/trace_sched_switch.o
CC fs/proc/proc_net.o
CC net/ethtool/stats.o
CC kernel/sysctl.o
CC kernel/trace/trace_nop.o
LD [M] sound/pci/hda/snd-hda-codec-hdmi.o
CC kernel/trace/blktrace.o
LD [M] sound/pci/hda/snd-hda-intel.o
CC fs/isofs/export.o
AR sound/pci/built-in.a
CC lib/klist.o
CC net/ipv4/ip_sockglue.o
CC drivers/acpi/acpica/dswscope.o
AR sound/usb/misc/built-in.a
AR sound/usb/usx2y/built-in.a
AR sound/usb/caiaq/built-in.a
AR sound/usb/6fire/built-in.a
AR sound/usb/hiface/built-in.a
CC net/netfilter/nf_conntrack_proto_tcp.o
AR sound/usb/bcd2000/built-in.a
AR sound/usb/built-in.a
AR security/selinux/built-in.a
CC net/netfilter/nf_conntrack_proto_udp.o
AR security/built-in.a
CC crypto/authenc.o
CC drivers/pnp/resource.o
AR sound/firewire/built-in.a
CC kernel/time/timer_list.o
CC kernel/time/timeconv.o
AR sound/sparc/built-in.a
CC drivers/acpi/acpica/dswstate.o
CC kernel/capability.o
AR sound/spi/built-in.a
AR sound/parisc/built-in.a
CC kernel/ptrace.o
AR sound/pcmcia/vx/built-in.a
AR fs/jbd2/built-in.a
AR sound/pcmcia/pdaudiocf/built-in.a
AR sound/pcmcia/built-in.a
CC fs/nfs/client.o
CC fs/exportfs/expfs.o
CC fs/nfs/dir.o
AR sound/mips/built-in.a
CC net/ipv4/netfilter/iptable_mangle.o
AR sound/soc/built-in.a
CC lib/kobject.o
AR sound/atmel/built-in.a
CC fs/fat/file.o
AR sound/hda/built-in.a
CC [M] sound/hda/hda_bus_type.o
CC fs/fat/inode.o
CC fs/isofs/joliet.o
CC kernel/user.o
CC fs/isofs/compress.o
CC io_uring/msg_ring.o
CC kernel/cgroup/pids.o
CC net/ethtool/phc_vclocks.o
CC block/blk-rq-qos.o
CC kernel/cgroup/rdma.o
CC fs/proc/kcore.o
CC kernel/events/hw_breakpoint.o
CC kernel/time/timecounter.o
CC drivers/acpi/dptf/int340x_thermal.o
CC fs/lockd/clntlock.o
CC drivers/pci/iomap.o
CC drivers/acpi/acpica/evevent.o
AR drivers/amba/built-in.a
CC kernel/trace/trace_events.o
CC drivers/pci/quirks.o
CC kernel/trace/trace_export.o
CC net/unix/sysctl_net_unix.o
CC kernel/trace/trace_event_perf.o
CC mm/backing-dev.o
CC fs/fat/misc.o
CC net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
CC kernel/time/alarmtimer.o
AR fs/exportfs/built-in.a
CC net/core/sock_reuseport.o
CC net/ethtool/mm.o
CC lib/kobject_uevent.o
CC net/ipv4/inet_hashtables.o
CC fs/fat/nfs.o
CC kernel/trace/trace_events_filter.o
CC kernel/trace/trace_events_trigger.o
CC drivers/acpi/acpica/evgpe.o
CC [M] sound/hda/hdac_bus.o
AR drivers/acpi/dptf/built-in.a
CC fs/ext4/file.o
CC crypto/authencesn.o
CC kernel/cgroup/cpuset.o
CC drivers/pnp/manager.o
CC fs/lockd/clntproc.o
AR fs/isofs/built-in.a
CC fs/lockd/clntxdr.o
CC block/disk-events.o
CC fs/lockd/host.o
CC net/ipv4/netfilter/ipt_REJECT.o
CC net/netfilter/nf_conntrack_proto_icmp.o
CC arch/x86/kernel/cpu/intel.o
CC drivers/acpi/tables.o
CC drivers/acpi/x86/apple.o
CC arch/x86/kernel/cpu/tsx.o
CC net/ipv6/netfilter/nf_conntrack_reasm.o
CC fs/proc/vmcore.o
CC kernel/trace/trace_eprobe.o
CC io_uring/advise.o
CC drivers/acpi/acpica/evgpeblk.o
CC drivers/pnp/support.o
CC net/xfrm/xfrm_input.o
CC net/ipv6/netfilter/nf_reject_ipv6.o
CC fs/fat/namei_vfat.o
AR net/unix/built-in.a
CC net/ipv4/inet_timewait_sock.o
CC net/packet/af_packet.o
CC net/ipv4/inet_connection_sock.o
CC kernel/events/uprobes.o
CC fs/lockd/svc.o
CC net/xfrm/xfrm_output.o
CC kernel/trace/trace_kprobe.o
CC fs/lockd/svclock.o
CC fs/ext4/fsmap.o
CC [M] sound/hda/hdac_device.o
CC fs/nfs/file.o
CC net/xfrm/xfrm_sysctl.o
CC drivers/acpi/x86/cmos_rtc.o
CC kernel/time/posix-timers.o
CC net/ethtool/module.o
CC lib/logic_pio.o
CC drivers/acpi/acpica/evgpeinit.o
CC drivers/pnp/interface.o
CC block/blk-ia-ranges.o
CC mm/mm_init.o
CC crypto/lzo.o
CC fs/ext4/fsync.o
CC block/early-lookup.o
CC kernel/trace/error_report-traces.o
CC [M] net/ipv4/netfilter/iptable_nat.o
CC [M] sound/hda/hdac_sysfs.o
CC drivers/acpi/osi.o
CC drivers/acpi/osl.o
CC io_uring/epoll.o
CC [M] sound/hda/hdac_regmap.o
CC fs/proc/kmsg.o
CC net/xfrm/xfrm_replay.o
CC drivers/acpi/acpica/evgpeutil.o
CC arch/x86/kernel/cpu/intel_epb.o
CC kernel/trace/power-traces.o
CC net/netfilter/nf_conntrack_extend.o
CC drivers/acpi/x86/lpss.o
CC mm/percpu.o
CC lib/maple_tree.o
CC drivers/pnp/quirks.o
CC drivers/pci/pci-label.o
CC fs/ext4/hash.o
CC kernel/trace/rpm-traces.o
CC crypto/lzo-rle.o
CC [M] sound/hda/hdac_controller.o
CC fs/fat/namei_msdos.o
CC drivers/acpi/x86/s2idle.o
CC drivers/acpi/acpica/evglock.o
CC net/ipv6/netfilter/ip6t_ipv6header.o
CC drivers/acpi/utils.o
CC drivers/acpi/x86/utils.o
CC block/bounce.o
CC mm/slab_common.o
CC drivers/acpi/acpica/evhandler.o
CC arch/x86/kernel/cpu/amd.o
CC fs/proc/page.o
CC mm/compaction.o
CC mm/show_mem.o
CC drivers/acpi/reboot.o
CC drivers/acpi/nvs.o
CC net/core/fib_notifier.o
CC fs/lockd/svcshare.o
CC kernel/time/posix-cpu-timers.o
CC io_uring/statx.o
CC arch/x86/kernel/cpu/hygon.o
CC net/ethtool/cmis_fw_update.o
CC fs/ext4/ialloc.o
CC block/bsg.o
CC block/blk-cgroup.o
CC block/blk-ioprio.o
CC kernel/cgroup/misc.o
CC arch/x86/kernel/cpu/centaur.o
CC kernel/cgroup/debug.o
CC drivers/acpi/acpica/evmisc.o
AR net/ipv4/netfilter/built-in.a
CC fs/nfs/getroot.o
CC drivers/pci/vgaarb.o
CC net/ipv4/tcp.o
AR kernel/events/built-in.a
CC io_uring/timeout.o
CC crypto/rng.o
CC [M] sound/hda/hdac_stream.o
CC arch/x86/kernel/cpu/transmeta.o
CC drivers/pnp/system.o
CC net/ipv6/netfilter/ip6t_REJECT.o
CC net/xfrm/xfrm_device.o
CC drivers/acpi/wakeup.o
CC arch/x86/kernel/cpu/zhaoxin.o
CC drivers/acpi/acpica/evregion.o
CC net/netfilter/nf_conntrack_acct.o
CC net/xfrm/xfrm_nat_keepalive.o
CC drivers/acpi/x86/blacklist.o
CC fs/ext4/indirect.o
AR drivers/clk/actions/built-in.a
AR drivers/clk/analogbits/built-in.a
AR net/dsa/built-in.a
AR fs/proc/built-in.a
CC net/ipv4/tcp_input.o
AR drivers/clk/bcm/built-in.a
AR drivers/clk/imgtec/built-in.a
AR drivers/clk/imx/built-in.a
CC fs/nfs/inode.o
CC drivers/acpi/sleep.o
CC kernel/signal.o
AR drivers/clk/ingenic/built-in.a
CC fs/nls/nls_base.o
AR drivers/clk/mediatek/built-in.a
CC fs/nls/nls_cp437.o
AR drivers/clk/microchip/built-in.a
AR drivers/clk/mstar/built-in.a
CC net/sunrpc/auth_gss/auth_gss.o
AR drivers/clk/mvebu/built-in.a
AR drivers/clk/ralink/built-in.a
AR fs/fat/built-in.a
CC block/blk-iolatency.o
AR drivers/clk/renesas/built-in.a
CC net/sunrpc/auth_gss/gss_generic_token.o
AR drivers/clk/socfpga/built-in.a
AR drivers/clk/sophgo/built-in.a
CC net/sunrpc/auth_gss/gss_mech_switch.o
CC fs/ext4/inline.o
AR drivers/clk/sprd/built-in.a
AR drivers/clk/starfive/built-in.a
AR drivers/pnp/built-in.a
CC block/blk-iocost.o
AR drivers/clk/sunxi-ng/built-in.a
CC net/sunrpc/auth_gss/svcauth_gss.o
CC drivers/dma/dw/core.o
CC net/core/xdp.o
AR drivers/clk/ti/built-in.a
CC crypto/drbg.o
AR drivers/clk/versatile/built-in.a
CC drivers/dma/dw/dw.o
CC io_uring/fdinfo.o
AR drivers/soc/apple/built-in.a
AR drivers/clk/xilinx/built-in.a
AR kernel/cgroup/built-in.a
AR drivers/clk/built-in.a
CC io_uring/cancel.o
AR drivers/soc/aspeed/built-in.a
CC arch/x86/kernel/cpu/vortex.o
CC fs/lockd/svcproc.o
AR drivers/soc/bcm/built-in.a
CC arch/x86/kernel/cpu/perfctr-watchdog.o
AR drivers/soc/fsl/built-in.a
AR drivers/soc/fujitsu/built-in.a
CC kernel/sys.o
CC drivers/acpi/acpica/evrgnini.o
AR drivers/soc/hisilicon/built-in.a
AR drivers/acpi/x86/built-in.a
CC net/ethtool/cmis_cdb.o
CC io_uring/waitid.o
CC net/sunrpc/clnt.o
AR drivers/soc/imx/built-in.a
AR drivers/soc/ixp4xx/built-in.a
CC drivers/dma/dw/idma32.o
AR drivers/soc/loongson/built-in.a
AR drivers/soc/mediatek/built-in.a
AR drivers/soc/microchip/built-in.a
CC fs/nls/nls_ascii.o
AR drivers/soc/nuvoton/built-in.a
CC kernel/time/posix-clock.o
CC kernel/trace/trace_dynevent.o
AR drivers/soc/pxa/built-in.a
AR drivers/soc/amlogic/built-in.a
CC crypto/jitterentropy.o
AR drivers/soc/qcom/built-in.a
AR drivers/soc/renesas/built-in.a
AR drivers/pci/built-in.a
AR drivers/soc/rockchip/built-in.a
CC io_uring/register.o
CC io_uring/truncate.o
AR drivers/soc/sunxi/built-in.a
CC crypto/jitterentropy-kcapi.o
AR drivers/soc/ti/built-in.a
CC net/core/flow_offload.o
AR drivers/soc/xilinx/built-in.a
CC [M] sound/hda/array.o
AR drivers/soc/built-in.a
CC arch/x86/kernel/cpu/vmware.o
CC arch/x86/kernel/cpu/hypervisor.o
CC drivers/acpi/acpica/evsci.o
CC mm/shmem_quota.o
CC net/xfrm/xfrm_algo.o
CC net/sunrpc/auth_gss/gss_rpc_upcall.o
AR net/packet/built-in.a
CC fs/nls/nls_iso8859-1.o
AR net/ipv6/netfilter/built-in.a
AR net/wireless/tests/built-in.a
CC net/xfrm/xfrm_user.o
CC net/ipv6/ip6_output.o
CC drivers/dma/dw/acpi.o
CC net/netfilter/nf_conntrack_seqadj.o
CC net/wireless/core.o
CC block/mq-deadline.o
CC kernel/umh.o
CC fs/nls/nls_utf8.o
CC kernel/workqueue.o
CC crypto/ghash-generic.o
CC drivers/acpi/acpica/evxface.o
AR fs/unicode/built-in.a
CC fs/autofs/init.o
CC crypto/hash_info.o
CC io_uring/memmap.o
CC drivers/dma/hsu/hsu.o
CC io_uring/io-wq.o
CC net/sunrpc/xprt.o
CC drivers/acpi/acpica/evxfevnt.o
CC kernel/time/itimer.o
CC kernel/time/clockevents.o
CC [M] sound/hda/hdmi_chmap.o
CC [M] sound/hda/trace.o
CC arch/x86/kernel/cpu/mshyperv.o
CC fs/lockd/svcsubs.o
AR fs/nls/built-in.a
CC kernel/trace/trace_probe.o
CC kernel/pid.o
CC mm/interval_tree.o
CC net/ethtool/pse-pd.o
CC block/kyber-iosched.o
CC crypto/rsapubkey.asn1.o
CC fs/9p/vfs_super.o
AR drivers/dma/dw/built-in.a
CC crypto/rsaprivkey.asn1.o
AR fs/hostfs/built-in.a
CC fs/9p/vfs_inode.o
AR drivers/dma/idxd/built-in.a
AR crypto/built-in.a
CC drivers/acpi/acpica/evxfgpe.o
CC drivers/acpi/acpica/evxfregn.o
CC block/blk-mq-pci.o
CC fs/debugfs/inode.o
CC block/blk-mq-virtio.o
CC drivers/acpi/acpica/exconcat.o
CC mm/list_lru.o
CC fs/autofs/inode.o
CC net/core/gro.o
CC fs/autofs/root.o
AR net/mac80211/tests/built-in.a
CC net/netlabel/netlabel_user.o
CC kernel/task_work.o
CC net/mac80211/main.o
CC fs/debugfs/file.o
CC net/netlabel/netlabel_kapi.o
AR drivers/dma/hsu/built-in.a
AR drivers/dma/mediatek/built-in.a
AR drivers/dma/qcom/built-in.a
CC net/netlabel/netlabel_domainhash.o
CC fs/ext4/inode.o
AR drivers/dma/stm32/built-in.a
CC net/ipv6/ip6_input.o
AR drivers/dma/ti/built-in.a
AR drivers/dma/xilinx/built-in.a
CC net/netfilter/nf_conntrack_proto_icmpv6.o
CC drivers/dma/dmaengine.o
CC net/rfkill/core.o
CC fs/autofs/symlink.o
CC drivers/acpi/acpica/exconfig.o
CC net/ipv6/addrconf.o
CC drivers/acpi/acpica/exconvrt.o
CC fs/9p/vfs_inode_dotl.o
CC kernel/time/tick-common.o
CC net/mac80211/status.o
CC net/sunrpc/auth_gss/gss_rpc_xdr.o
CC [M] sound/hda/hdac_component.o
CC kernel/extable.o
CC net/sunrpc/socklib.o
CC arch/x86/kernel/cpu/debugfs.o
CC kernel/params.o
CC net/netfilter/nf_conntrack_netlink.o
CC mm/workingset.o
CC fs/lockd/mon.o
CC arch/x86/kernel/cpu/capflags.o
CC net/ethtool/plca.o
CC net/ipv4/tcp_output.o
CC kernel/kthread.o
CC net/netlabel/netlabel_addrlist.o
CC mm/debug.o
CC block/blk-mq-debugfs.o
CC drivers/acpi/acpica/excreate.o
CC io_uring/futex.o
CC kernel/time/tick-broadcast.o
CC net/ipv6/addrlabel.o
CC fs/autofs/waitq.o
CC kernel/trace/trace_uprobe.o
CC drivers/dma/virt-dma.o
CC fs/autofs/expire.o
CC net/mac80211/driver-ops.o
AR arch/x86/kernel/cpu/built-in.a
CC arch/x86/kernel/platform-quirks.o
CC fs/nfs/super.o
CC [M] sound/hda/hdac_i915.o
CC drivers/acpi/acpica/exdebug.o
AR fs/debugfs/built-in.a
CC net/rfkill/input.o
CC fs/tracefs/inode.o
CC fs/9p/vfs_addr.o
CC fs/tracefs/event_inode.o
CC kernel/sys_ni.o
CC net/ipv6/route.o
AR sound/x86/built-in.a
CC net/netlabel/netlabel_mgmt.o
AR sound/xen/built-in.a
AR sound/virtio/built-in.a
CC arch/x86/kernel/process_32.o
CC sound/sound_core.o
CC io_uring/napi.o
CC mm/gup.o
CC [M] fs/efivarfs/inode.o
CC fs/open.o
CC net/sunrpc/xprtsock.o
CC fs/read_write.o
AR net/xfrm/built-in.a
CC net/sunrpc/auth_gss/trace.o
CC mm/mmap_lock.o
CC drivers/acpi/acpica/exdump.o
CC kernel/time/tick-broadcast-hrtimer.o
CC sound/last.o
CC net/core/netdev-genl.o
CC drivers/dma/acpi-dma.o
CC net/netlabel/netlabel_unlabeled.o
AR net/ethtool/built-in.a
CC fs/autofs/dev-ioctl.o
CC block/blk-pm.o
CC fs/nfs/io.o
CC kernel/nsproxy.o
CC net/ipv6/ip6_fib.o
CC net/9p/mod.o
CC fs/lockd/trace.o
CC [M] sound/hda/intel-dsp-config.o
CC [M] fs/efivarfs/file.o
CC fs/file_table.o
CC drivers/acpi/acpica/exfield.o
AR net/rfkill/built-in.a
CC net/9p/client.o
CC lib/memcat_p.o
CC net/ipv4/tcp_timer.o
CC net/ipv6/ipv6_sockglue.o
CC net/sunrpc/auth_gss/gss_krb5_mech.o
CC kernel/time/tick-oneshot.o
CC [M] fs/efivarfs/super.o
CC fs/9p/vfs_file.o
CC fs/super.o
CC [M] sound/hda/intel-nhlt.o
CC kernel/notifier.o
CC net/sunrpc/sched.o
CC kernel/time/tick-sched.o
CC lib/nmi_backtrace.o
CC drivers/acpi/acpica/exfldio.o
AR fs/tracefs/built-in.a
CC kernel/time/timer_migration.o
CC arch/x86/kernel/signal.o
CC net/netfilter/nf_conntrack_ftp.o
AR drivers/dma/built-in.a
CC net/wireless/sysfs.o
CC block/holder.o
CC [M] fs/efivarfs/vars.o
CC net/sunrpc/auth_gss/gss_krb5_seal.o
CC mm/highmem.o
CC fs/nfs/direct.o
AR fs/autofs/built-in.a
CC fs/char_dev.o
CC net/mac80211/sta_info.o
CC fs/9p/vfs_dir.o
CC kernel/trace/rethook.o
CC net/dns_resolver/dns_key.o
CC kernel/ksysfs.o
CC net/dns_resolver/dns_query.o
CC fs/stat.o
CC [M] sound/hda/intel-sdw-acpi.o
CC drivers/acpi/acpica/exmisc.o
CC drivers/acpi/acpica/exmutex.o
CC fs/9p/vfs_dentry.o
CC fs/lockd/xdr.o
CC fs/9p/v9fs.o
AR io_uring/built-in.a
CC lib/objpool.o
CC lib/plist.o
CC net/handshake/alert.o
CC lib/radix-tree.o
CC net/core/netdev-genl-gen.o
CC net/mac80211/wep.o
CC net/netlabel/netlabel_cipso_v4.o
AR block/built-in.a
CC net/mac80211/aead_api.o
CC net/sunrpc/auth_gss/gss_krb5_unseal.o
CC net/9p/error.o
CC fs/nfs/pagelist.o
CC arch/x86/kernel/signal_32.o
CC kernel/time/vsyscall.o
LD [M] fs/efivarfs/efivarfs.o
CC mm/memory.o
CC net/netlabel/netlabel_calipso.o
CC kernel/time/timekeeping_debug.o
CC net/handshake/genl.o
CC fs/nfs/read.o
CC drivers/acpi/acpica/exnames.o
CC fs/exec.o
LD [M] sound/hda/snd-hda-core.o
AR kernel/trace/built-in.a
CC drivers/acpi/acpica/exoparg1.o
LD [M] sound/hda/snd-intel-dspcfg.o
LD [M] sound/hda/snd-intel-sdw-acpi.o
CC net/handshake/netlink.o
AR sound/built-in.a
CC net/handshake/request.o
CC kernel/cred.o
CC net/mac80211/wpa.o
CC fs/nfs/symlink.o
CC kernel/reboot.o
CC kernel/async.o
AR net/dns_resolver/built-in.a
CC net/ipv4/tcp_ipv4.o
CC fs/9p/fid.o
CC net/handshake/tlshd.o
CC net/sunrpc/auth_gss/gss_krb5_wrap.o
CC net/9p/protocol.o
CC mm/mincore.o
CC fs/nfs/unlink.o
CC arch/x86/kernel/traps.o
CC net/netfilter/nf_conntrack_irc.o
CC kernel/range.o
CC drivers/acpi/acpica/exoparg2.o
CC drivers/acpi/acpica/exoparg3.o
CC net/sunrpc/auth.o
CC net/sunrpc/auth_gss/gss_krb5_crypto.o
CC kernel/smpboot.o
CC drivers/acpi/device_sysfs.o
CC net/ipv6/ndisc.o
CC net/core/gso.o
CC net/mac80211/scan.o
CC lib/ratelimit.o
CC net/sunrpc/auth_gss/gss_krb5_keys.o
CC kernel/ucount.o
CC kernel/time/namespace.o
CC net/core/net-sysfs.o
CC arch/x86/kernel/idt.o
CC net/handshake/trace.o
CC fs/lockd/clnt4xdr.o
CC lib/rbtree.o
CC arch/x86/kernel/irq.o
CC net/mac80211/offchannel.o
CC net/ipv6/udp.o
CC drivers/acpi/acpica/exoparg6.o
CC kernel/regset.o
CC fs/9p/xattr.o
CC fs/pipe.o
CC fs/namei.o
AR net/netlabel/built-in.a
CC net/core/hotdata.o
CC net/netfilter/nf_conntrack_sip.o
CC lib/seq_buf.o
CC net/9p/trans_common.o
CC fs/fcntl.o
CC net/core/net-procfs.o
CC fs/ext4/ioctl.o
CC mm/mlock.o
CC net/mac80211/ht.o
CC fs/ioctl.o
CC drivers/acpi/acpica/exprep.o
CC arch/x86/kernel/irq_32.o
CC kernel/ksyms_common.o
CC drivers/acpi/acpica/exregion.o
AR kernel/time/built-in.a
CC kernel/groups.o
CC kernel/kcmp.o
CC arch/x86/kernel/dumpstack_32.o
CC net/netfilter/nf_nat_core.o
CC net/wireless/radiotap.o
CC net/9p/trans_fd.o
CC fs/nfs/write.o
CC net/mac80211/agg-tx.o
CC net/mac80211/agg-rx.o
AR net/sunrpc/auth_gss/built-in.a
CC net/sunrpc/auth_null.o
CC drivers/acpi/acpica/exresnte.o
CC drivers/acpi/device_pm.o
CC lib/siphash.o
AR fs/9p/built-in.a
CC fs/readdir.o
CC fs/select.o
CC drivers/virtio/virtio.o
CC net/sunrpc/auth_tls.o
CC fs/dcache.o
CC fs/lockd/xdr4.o
CC net/ipv4/tcp_minisocks.o
CC fs/nfs/namespace.o
CC kernel/freezer.o
CC drivers/virtio/virtio_ring.o
CC drivers/acpi/acpica/exresolv.o
CC net/wireless/util.o
CC net/9p/trans_virtio.o
CC net/ipv6/udplite.o
CC arch/x86/kernel/time.o
CC net/netfilter/nf_nat_proto.o
CC kernel/profile.o
CC arch/x86/kernel/ioport.o
CC fs/inode.o
CC lib/string.o
CC arch/x86/kernel/dumpstack.o
AR net/handshake/built-in.a
CC net/ipv4/tcp_cong.o
CC fs/attr.o
CC net/netfilter/nf_nat_helper.o
CC net/core/netpoll.o
CC net/wireless/reg.o
CC lib/timerqueue.o
CC drivers/acpi/acpica/exresop.o
CC mm/mmap.o
CC net/ipv4/tcp_metrics.o
CC net/devres.o
CC arch/x86/kernel/nmi.o
CC fs/bad_inode.o
CC fs/nfs/mount_clnt.o
CC lib/vsprintf.o
CC drivers/acpi/proc.o
CC net/ipv6/raw.o
CC net/ipv6/icmp.o
CC mm/mmu_gather.o
CC fs/lockd/svc4proc.o
CC kernel/stacktrace.o
CC net/netfilter/nf_nat_masquerade.o
CC kernel/dma.o
CC arch/x86/kernel/ldt.o
CC net/sunrpc/auth_unix.o
CC drivers/acpi/acpica/exserial.o
CC net/netfilter/nf_nat_ftp.o
CC drivers/acpi/bus.o
CC fs/file.o
CC fs/lockd/procfs.o
CC net/socket.o
CC fs/filesystems.o
CC drivers/virtio/virtio_anchor.o
CC fs/nfs/nfstrace.o
CC net/core/fib_rules.o
CC fs/namespace.o
AR net/9p/built-in.a
CC net/sysctl_net.o
CC drivers/acpi/acpica/exstore.o
CC kernel/smp.o
CC mm/mprotect.o
CC drivers/acpi/glue.o
CC net/mac80211/vht.o
CC drivers/virtio/virtio_pci_modern_dev.o
CC kernel/uid16.o
CC net/mac80211/he.o
CC net/ipv4/tcp_fastopen.o
CC net/ipv4/tcp_rate.o
CC drivers/acpi/scan.o
CC fs/ext4/mballoc.o
CC net/sunrpc/svc.o
CC net/mac80211/s1g.o
CC net/netfilter/nf_nat_irc.o
CC fs/seq_file.o
CC drivers/acpi/acpica/exstoren.o
CC drivers/tty/vt/vt_ioctl.o
CC drivers/tty/vt/vc_screen.o
CC net/netfilter/nf_nat_sip.o
CC arch/x86/kernel/setup.o
CC drivers/tty/vt/selection.o
CC net/core/net-traces.o
CC fs/xattr.o
CC net/core/selftests.o
CC fs/libfs.o
AR fs/lockd/built-in.a
CC drivers/char/hw_random/core.o
CC drivers/char/agp/backend.o
AR drivers/iommu/amd/built-in.a
AR drivers/iommu/intel/built-in.a
AR drivers/iommu/arm/arm-smmu/built-in.a
AR drivers/iommu/arm/arm-smmu-v3/built-in.a
AR drivers/iommu/iommufd/built-in.a
AR drivers/iommu/arm/built-in.a
CC drivers/iommu/iommu.o
CC drivers/char/mem.o
CC drivers/iommu/iommu-traces.o
CC net/sunrpc/svcsock.o
CC drivers/tty/hvc/hvc_console.o
CC drivers/acpi/acpica/exstorob.o
CC drivers/acpi/mipi-disco-img.o
CC net/ipv4/tcp_recovery.o
CC drivers/virtio/virtio_pci_legacy_dev.o
CC net/mac80211/ibss.o
CC fs/ext4/migrate.o
CC net/ipv6/mcast.o
CC drivers/char/hw_random/intel-rng.o
CC mm/mremap.o
CC net/mac80211/iface.o
CC kernel/kallsyms.o
CC drivers/char/hw_random/amd-rng.o
CC drivers/acpi/acpica/exsystem.o
CC net/core/ptp_classifier.o
CC drivers/tty/vt/keyboard.o
CC drivers/tty/vt/vt.o
COPY drivers/tty/vt/defkeymap.c
AR drivers/gpu/host1x/built-in.a
CC drivers/acpi/acpica/extrace.o
CC mm/msync.o
AR drivers/gpu/vga/built-in.a
CC drivers/char/hw_random/geode-rng.o
CC drivers/tty/vt/consolemap.o
CC drivers/char/hw_random/via-rng.o
CC drivers/char/agp/generic.o
CC net/netfilter/x_tables.o
CC net/ipv4/tcp_ulp.o
CC lib/win_minmax.o
CC drivers/acpi/resource.o
CC drivers/virtio/virtio_pci_modern.o
CC net/netfilter/xt_tcpudp.o
AR drivers/gpu/drm/tests/built-in.a
CC arch/x86/kernel/x86_init.o
AR drivers/gpu/drm/arm/built-in.a
CC net/netfilter/xt_CONNSECMARK.o
CC drivers/gpu/drm/display/drm_display_helper_mod.o
CC net/netfilter/xt_NFLOG.o
AR drivers/tty/hvc/built-in.a
CC mm/page_vma_mapped.o
CC drivers/char/agp/isoch.o
CC drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
CC drivers/acpi/acpica/exutils.o
CC net/netfilter/xt_SECMARK.o
CC net/core/netprio_cgroup.o
CC drivers/gpu/drm/ttm/ttm_tt.o
CC fs/fs-writeback.o
CC lib/xarray.o
CC drivers/gpu/drm/ttm/ttm_bo.o
CC drivers/gpu/drm/i915/i915_config.o
CC net/wireless/scan.o
CC drivers/gpu/drm/i915/i915_driver.o
CC net/netfilter/xt_TCPMSS.o
CC drivers/gpu/drm/i915/i915_drm_client.o
AR drivers/char/hw_random/built-in.a
CC net/netfilter/xt_conntrack.o
CC drivers/char/random.o
CC mm/pagewalk.o
CC drivers/acpi/acpica/hwacpi.o
AR drivers/gpu/drm/renesas/rcar-du/built-in.a
AR drivers/gpu/drm/renesas/rz-du/built-in.a
AR drivers/gpu/drm/renesas/built-in.a
AR drivers/gpu/drm/omapdrm/built-in.a
CC drivers/gpu/drm/i915/i915_getparam.o
CC lib/lockref.o
CC mm/pgtable-generic.o
CC net/sunrpc/svcauth.o
CC arch/x86/kernel/i8259.o
CC kernel/acct.o
CC net/core/netclassid_cgroup.o
CC drivers/gpu/drm/ttm/ttm_bo_util.o
CC drivers/virtio/virtio_pci_common.o
CC drivers/char/agp/amd64-agp.o
CC lib/bcd.o
CC drivers/iommu/iommu-sysfs.o
CC net/netfilter/xt_policy.o
CC lib/sort.o
CC lib/parser.o
CC drivers/connector/cn_queue.o
CC drivers/acpi/acpica/hwesleep.o
CC drivers/connector/connector.o
CC drivers/gpu/drm/display/drm_dp_helper.o
CC drivers/connector/cn_proc.o
CC net/ipv4/tcp_offload.o
CC net/netfilter/xt_state.o
CC net/sunrpc/svcauth_unix.o
CC drivers/char/agp/intel-agp.o
CC net/mac80211/link.o
CC drivers/char/agp/intel-gtt.o
CC net/mac80211/rate.o
CC net/wireless/nl80211.o
HOSTCC drivers/tty/vt/conmakehash
CC drivers/tty/serial/8250/8250_core.o
CC arch/x86/kernel/irqinit.o
AR drivers/tty/ipwireless/built-in.a
CC drivers/acpi/acpica/hwgpe.o
CC drivers/tty/tty_io.o
CC lib/debug_locks.o
CC drivers/tty/serial/8250/8250_platform.o
CC net/sunrpc/addr.o
CC mm/rmap.o
CC drivers/iommu/dma-iommu.o
CC drivers/iommu/iova.o
CC drivers/gpu/drm/ttm/ttm_bo_vm.o
CC lib/random32.o
CC drivers/gpu/drm/ttm/ttm_module.o
CC lib/bust_spinlocks.o
CC net/core/dst_cache.o
CC drivers/tty/n_tty.o
CC drivers/gpu/drm/i915/i915_ioctl.o
CC kernel/vmcore_info.o
CC drivers/virtio/virtio_pci_legacy.o
CC drivers/base/power/sysfs.o
CC [M] net/netfilter/nf_log_syslog.o
CC drivers/base/firmware_loader/builtin/main.o
CC drivers/base/regmap/regmap.o
CC drivers/gpu/drm/ttm/ttm_execbuf_util.o
CC drivers/acpi/acpica/hwregs.o
CC drivers/virtio/virtio_pci_admin_legacy_io.o
CC mm/vmalloc.o
CC net/wireless/mlme.o
CC drivers/tty/tty_ioctl.o
AR drivers/connector/built-in.a
CC [M] net/netfilter/xt_mark.o
CC drivers/block/loop.o
CC net/wireless/ibss.o
CC [M] net/netfilter/xt_nat.o
AR drivers/base/firmware_loader/builtin/built-in.a
CC drivers/base/firmware_loader/main.o
CC drivers/tty/vt/defkeymap.o
CC [M] net/netfilter/xt_LOG.o
AR drivers/char/agp/built-in.a
CC arch/x86/kernel/jump_label.o
CC drivers/char/misc.o
CC drivers/gpu/drm/ttm/ttm_range_manager.o
CC net/ipv6/reassembly.o
CC lib/kasprintf.o
CC drivers/gpu/drm/ttm/ttm_resource.o
CC drivers/tty/serial/8250/8250_pnp.o
CC drivers/acpi/acpica/hwsleep.o
CC net/mac80211/michael.o
CC drivers/base/power/generic_ops.o
CONMK drivers/tty/vt/consolemap_deftbl.c
CC drivers/tty/vt/consolemap_deftbl.o
CC net/core/gro_cells.o
CC kernel/elfcorehdr.o
CC fs/nfs/export.o
CC net/core/failover.o
AR drivers/tty/vt/built-in.a
CC arch/x86/kernel/irq_work.o
CC net/ipv4/tcp_plb.o
CC net/ipv6/tcp_ipv6.o
AR drivers/base/test/built-in.a
CC drivers/virtio/virtio_input.o
CC drivers/char/virtio_console.o
CC lib/bitmap.o
CC drivers/virtio/virtio_dma_buf.o
CC drivers/gpu/drm/i915/i915_irq.o
CC drivers/base/component.o
CC drivers/acpi/acpica/hwvalid.o
CC drivers/gpu/drm/display/drm_dp_mst_topology.o
CC mm/process_vm_access.o
CC drivers/base/power/common.o
CC drivers/gpu/drm/display/drm_dsc_helper.o
CC drivers/tty/serial/8250/8250_rsa.o
CC drivers/char/hpet.o
CC drivers/char/nvram.o
AR drivers/iommu/built-in.a
CC fs/pnode.o
CC fs/splice.o
CC [M] net/netfilter/xt_MASQUERADE.o
CC kernel/crash_reserve.o
CC kernel/kexec_core.o
CC net/mac80211/tkip.o
CC net/sunrpc/rpcb_clnt.o
AR drivers/base/firmware_loader/built-in.a
CC mm/page_alloc.o
CC drivers/tty/tty_ldisc.o
CC drivers/acpi/acpica/hwxface.o
CC lib/scatterlist.o
CC drivers/gpu/drm/i915/i915_mitigations.o
CC drivers/gpu/drm/ttm/ttm_pool.o
CC net/mac80211/aes_cmac.o
CC fs/ext4/mmp.o
AR drivers/virtio/built-in.a
CC fs/ext4/move_extent.o
CC drivers/gpu/drm/ttm/ttm_device.o
CC drivers/tty/tty_buffer.o
CC lib/list_sort.o
CC drivers/base/power/qos.o
CC drivers/base/power/runtime.o
CC drivers/base/core.o
CC drivers/gpu/drm/ttm/ttm_sys_manager.o
CC drivers/gpu/drm/i915/i915_module.o
AR net/core/built-in.a
CC drivers/base/power/wakeirq.o
CC drivers/base/power/main.o
CC arch/x86/kernel/probe_roms.o
CC drivers/block/virtio_blk.o
CC lib/uuid.o
CC drivers/acpi/acpica/hwxfsleep.o
CC net/sunrpc/timer.o
CC drivers/tty/serial/8250/8250_port.o
CC drivers/tty/serial/8250/8250_dma.o
CC lib/iov_iter.o
CC lib/clz_ctz.o
CC net/ipv4/datagram.o
CC net/sunrpc/xdr.o
CC net/ipv6/ping.o
CC net/ipv6/exthdrs.o
CC drivers/gpu/drm/display/drm_hdcp_helper.o
CC drivers/gpu/drm/i915/i915_params.o
CC drivers/gpu/drm/i915/i915_pci.o
CC kernel/crash_core.o
CC fs/sync.o
CC drivers/tty/tty_port.o
AR drivers/char/built-in.a
CC lib/bsearch.o
CC drivers/acpi/acpica/hwpci.o
CC drivers/gpu/drm/i915/i915_scatterlist.o
CC drivers/gpu/drm/ttm/ttm_agp_backend.o
CC kernel/kexec.o
CC fs/ext4/namei.o
CC kernel/utsname.o
CC [M] net/netfilter/xt_addrtype.o
CC lib/find_bit.o
CC drivers/gpu/drm/i915/i915_suspend.o
CC fs/nfs/sysfs.o
CC fs/ext4/page-io.o
CC arch/x86/kernel/sys_ia32.o
CC fs/utimes.o
CC net/wireless/sme.o
CC net/mac80211/aes_gmac.o
CC lib/llist.o
CC drivers/base/regmap/regcache.o
CC drivers/acpi/acpica/nsaccess.o
CC drivers/tty/serial/8250/8250_dwlib.o
CC drivers/base/power/wakeup.o
CC drivers/gpu/drm/i915/i915_switcheroo.o
CC fs/ext4/readpage.o
CC kernel/pid_namespace.o
CC drivers/tty/tty_mutex.o
CC drivers/base/regmap/regcache-rbtree.o
CC drivers/gpu/drm/i915/i915_sysfs.o
CC arch/x86/kernel/ksysfs.o
CC net/mac80211/fils_aead.o
CC kernel/stop_machine.o
CC drivers/acpi/acpica/nsalloc.o
AR drivers/gpu/drm/ttm/built-in.a
CC drivers/tty/tty_ldsem.o
AR drivers/gpu/drm/tilcdc/built-in.a
CC drivers/gpu/drm/virtio/virtgpu_drv.o
AR drivers/block/built-in.a
CC drivers/gpu/drm/virtio/virtgpu_kms.o
CC lib/lwq.o
CC drivers/gpu/drm/i915/i915_utils.o
CC drivers/gpu/drm/virtio/virtgpu_gem.o
CC net/ipv4/raw.o
CC drivers/gpu/drm/i915/intel_clock_gating.o
AR drivers/misc/eeprom/built-in.a
AR drivers/mfd/built-in.a
CC drivers/gpu/drm/i915/intel_device_info.o
AR drivers/misc/cb710/built-in.a
AR drivers/nfc/built-in.a
CC drivers/acpi/acpica/nsarguments.o
AR drivers/misc/ti-st/built-in.a
CC drivers/acpi/acpica/nsconvert.o
AR drivers/misc/lis3lv02d/built-in.a
CC mm/init-mm.o
AR drivers/misc/cardreader/built-in.a
CC mm/memblock.o
AR drivers/misc/keba/built-in.a
CC fs/nfs/fs_context.o
AR drivers/misc/built-in.a
AR drivers/dax/hmem/built-in.a
AR drivers/dax/built-in.a
CC net/ipv4/udp.o
CC fs/nfs/nfsroot.o
CC drivers/dma-buf/dma-buf.o
CC net/ipv4/udplite.o
CC fs/nfs/sysctl.o
CC mm/slub.o
CC drivers/gpu/drm/display/drm_hdmi_helper.o
CC net/sunrpc/sunrpc_syms.o
CC fs/nfs/nfs3super.o
CC drivers/tty/serial/8250/8250_pcilib.o
CC arch/x86/kernel/bootflag.o
CC drivers/dma-buf/dma-fence.o
CC drivers/acpi/acpica/nsdump.o
AR net/netfilter/built-in.a
CC drivers/acpi/acpica/nseval.o
CC net/ipv4/udp_offload.o
CC drivers/acpi/acpica/nsinit.o
CC drivers/tty/tty_baudrate.o
CC net/ipv6/datagram.o
CC net/mac80211/cfg.o
CC net/wireless/chan.o
CC drivers/base/regmap/regcache-flat.o
CC drivers/gpu/drm/i915/intel_memory_region.o
CC fs/ext4/resize.o
CC drivers/tty/tty_jobctrl.o
CC lib/memweight.o
CC kernel/audit.o
CC drivers/gpu/drm/display/drm_scdc_helper.o
CC drivers/gpu/drm/virtio/virtgpu_vram.o
CC drivers/tty/n_null.o
CC drivers/gpu/drm/i915/intel_pcode.o
CC arch/x86/kernel/e820.o
CC net/mac80211/ethtool.o
CC lib/kfifo.o
CC lib/percpu-refcount.o
CC net/wireless/ethtool.o
CC drivers/gpu/drm/i915/intel_region_ttm.o
CC drivers/acpi/acpica/nsload.o
CC net/sunrpc/cache.o
CC drivers/base/power/wakeup_stats.o
AR drivers/gpu/drm/imx/built-in.a
AR drivers/gpu/drm/i2c/built-in.a
AR drivers/gpu/drm/panel/built-in.a
AR drivers/gpu/drm/bridge/analogix/built-in.a
CC net/mac80211/rx.o
AR drivers/gpu/drm/bridge/cadence/built-in.a
CC drivers/tty/serial/8250/8250_early.o
AR drivers/gpu/drm/bridge/imx/built-in.a
CC net/mac80211/spectmgmt.o
AR drivers/gpu/drm/bridge/synopsys/built-in.a
CC net/mac80211/tx.o
AR drivers/gpu/drm/bridge/built-in.a
CC net/sunrpc/rpc_pipe.o
CC drivers/base/power/trace.o
CC drivers/gpu/drm/virtio/virtgpu_display.o
CC drivers/tty/pty.o
CC drivers/base/regmap/regcache-maple.o
CC lib/rhashtable.o
CC net/ipv4/arp.o
AR drivers/cxl/core/built-in.a
CC drivers/tty/tty_audit.o
AR drivers/cxl/built-in.a
CC fs/nfs/nfs3client.o
CC drivers/gpu/drm/i915/intel_runtime_pm.o
CC drivers/base/regmap/regmap-debugfs.o
CC drivers/macintosh/mac_hid.o
CC drivers/acpi/acpica/nsnames.o
CC lib/base64.o
CC fs/d_path.o
CC lib/once.o
CC fs/nfs/nfs3proc.o
CC mm/madvise.o
CC drivers/tty/sysrq.o
CC drivers/gpu/drm/virtio/virtgpu_vq.o
CC drivers/base/bus.o
CC lib/refcount.o
AR drivers/gpu/drm/display/built-in.a
CC drivers/dma-buf/dma-fence-array.o
AR drivers/gpu/drm/hisilicon/built-in.a
AR drivers/gpu/drm/mxsfb/built-in.a
AR drivers/gpu/drm/tiny/built-in.a
CC drivers/gpu/drm/i915/intel_sbi.o
AR drivers/gpu/drm/xlnx/built-in.a
AR drivers/gpu/drm/gud/built-in.a
AR drivers/gpu/drm/solomon/built-in.a
CC net/mac80211/key.o
CC drivers/tty/serial/8250/8250_exar.o
CC [M] drivers/gpu/drm/scheduler/sched_main.o
CC mm/page_io.o
CC drivers/gpu/drm/i915/intel_step.o
CC drivers/gpu/drm/i915/intel_uncore.o
CC net/sunrpc/sysfs.o
CC lib/rcuref.o
CC drivers/acpi/acpica/nsobject.o
CC arch/x86/kernel/pci-dma.o
CC drivers/gpu/drm/virtio/virtgpu_fence.o
AR drivers/macintosh/built-in.a
AR drivers/base/power/built-in.a
CC fs/stack.o
AR drivers/scsi/pcmcia/built-in.a
AR drivers/nvme/common/built-in.a
CC drivers/scsi/scsi.o
AR drivers/nvme/host/built-in.a
CC drivers/scsi/hosts.o
AR drivers/nvme/target/built-in.a
CC drivers/scsi/scsi_ioctl.o
AR drivers/nvme/built-in.a
CC fs/fs_struct.o
CC net/ipv6/ip6_flowlabel.o
CC fs/statfs.o
AR drivers/base/regmap/built-in.a
CC arch/x86/kernel/quirks.o
CC fs/nfs/nfs3xdr.o
CC drivers/dma-buf/dma-fence-chain.o
CC net/mac80211/util.o
CC lib/usercopy.o
CC drivers/acpi/acpica/nsparse.o
CC kernel/auditfilter.o
CC fs/nfs/nfs3acl.o
CC drivers/base/dd.o
CC net/sunrpc/svc_xprt.o
CC fs/fs_pin.o
CC drivers/gpu/drm/i915/intel_wakeref.o
CC lib/errseq.o
HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob
CC drivers/gpu/drm/i915/vlv_sideband.o
CC lib/bucket_locks.o
CC net/sunrpc/xprtmultipath.o
CC fs/nfs/nfs4proc.o
CC lib/generic-radix-tree.o
CC arch/x86/kernel/kdebugfs.o
CC drivers/acpi/acpica/nspredef.o
CC drivers/tty/serial/8250/8250_lpss.o
CC drivers/dma-buf/dma-fence-unwrap.o
CC drivers/dma-buf/dma-resv.o
GEN xe_wa_oob.c xe_wa_oob.h
CC arch/x86/kernel/alternative.o
CC [M] drivers/gpu/drm/xe/xe_bb.o
CC drivers/gpu/drm/virtio/virtgpu_object.o
CC drivers/acpi/acpi_processor.o
CC drivers/gpu/drm/i915/vlv_suspend.o
CC kernel/auditsc.o
CC kernel/audit_watch.o
CC fs/nfs/nfs4xdr.o
CC kernel/audit_fsnotify.o
CC fs/ext4/super.o
CC mm/swap_state.o
CC drivers/gpu/drm/i915/soc/intel_dram.o
CC drivers/gpu/drm/drm_aperture.o
CC arch/x86/kernel/i8253.o
CC drivers/tty/serial/8250/8250_mid.o
CC drivers/scsi/scsicam.o
CC [M] drivers/gpu/drm/scheduler/sched_fence.o
CC drivers/acpi/acpica/nsprepkg.o
CC drivers/scsi/scsi_error.o
CC lib/bitmap-str.o
CC drivers/dma-buf/sync_file.o
CC drivers/tty/serial/serial_core.o
CC drivers/acpi/processor_core.o
CC net/ipv4/icmp.o
CC drivers/scsi/scsi_lib.o
CC mm/swapfile.o
CC drivers/base/syscore.o
CC net/ipv6/inet6_connection_sock.o
CC lib/string_helpers.o
CC net/wireless/mesh.o
CC drivers/gpu/drm/virtio/virtgpu_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_bo.o
CC drivers/acpi/acpica/nsrepair.o
CC drivers/gpu/drm/virtio/virtgpu_plane.o
CC [M] drivers/gpu/drm/scheduler/sched_entity.o
CC mm/swap_slots.o
CC drivers/gpu/drm/virtio/virtgpu_ioctl.o
CC drivers/gpu/drm/virtio/virtgpu_prime.o
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
CC drivers/gpu/drm/drm_atomic.o
CC fs/nsfs.o
CC kernel/audit_tree.o
CC drivers/tty/serial/8250/8250_pci.o
CC lib/hexdump.o
CC net/sunrpc/stats.o
CC drivers/gpu/drm/i915/soc/intel_gmch.o
CC lib/kstrtox.o
CC arch/x86/kernel/hw_breakpoint.o
AR drivers/dma-buf/built-in.a
CC [M] drivers/gpu/drm/xe/xe_devcoredump.o
CC drivers/tty/serial/8250/8250_pericom.o
CC mm/dmapool.o
CC net/sunrpc/sysctl.o
CC lib/iomap.o
CC drivers/acpi/acpica/nsrepair2.o
CC mm/hugetlb.o
CC drivers/gpu/drm/i915/soc/intel_pch.o
CC mm/mmu_notifier.o
CC drivers/gpu/drm/i915/i915_memcpy.o
CC drivers/gpu/drm/i915/i915_mm.o
CC drivers/gpu/drm/virtio/virtgpu_trace_points.o
LD [M] drivers/gpu/drm/scheduler/gpu-sched.o
CC [M] drivers/gpu/drm/xe/xe_device.o
CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o
CC lib/iomap_copy.o
CC drivers/acpi/processor_pdc.o
CC drivers/gpu/drm/i915/i915_sw_fence.o
CC fs/nfs/nfs4state.o
CC net/ipv4/devinet.o
CC drivers/base/driver.o
CC mm/migrate.o
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC drivers/acpi/acpica/nssearch.o
CC fs/fs_types.o
CC drivers/gpu/drm/virtio/virtgpu_submit.o
CC drivers/base/class.o
CC mm/page_counter.o
CC net/mac80211/parse.o
CC fs/nfs/nfs4renewd.o
CC drivers/acpi/ec.o
CC lib/devres.o
CC drivers/gpu/drm/i915/i915_sw_fence_work.o
CC net/ipv6/udp_offload.o
CC net/ipv6/seg6.o
CC drivers/tty/serial/serial_base_bus.o
CC drivers/gpu/drm/i915/i915_syncmap.o
CC arch/x86/kernel/tsc.o
CC drivers/acpi/dock.o
CC drivers/acpi/acpica/nsutils.o
CC drivers/acpi/acpica/nswalk.o
CC kernel/kprobes.o
CC arch/x86/kernel/tsc_msr.o
CC drivers/acpi/acpica/nsxfeval.o
CC mm/hugetlb_cgroup.o
CC drivers/gpu/drm/drm_atomic_uapi.o
CC drivers/acpi/pci_root.o
CC drivers/gpu/drm/drm_auth.o
CC drivers/base/platform.o
AR drivers/tty/serial/8250/built-in.a
CC drivers/tty/serial/serial_ctrl.o
CC net/ipv4/af_inet.o
CC drivers/gpu/drm/i915/i915_user_extensions.o
CC drivers/scsi/constants.o
CC drivers/gpu/drm/i915/i915_debugfs.o
CC drivers/acpi/pci_link.o
CC lib/check_signature.o
CC drivers/gpu/drm/drm_blend.o
CC net/ipv4/igmp.o
CC net/ipv4/fib_frontend.o
CC drivers/scsi/scsi_lib_dma.o
CC drivers/tty/serial/serial_port.o
CC fs/fs_context.o
CC fs/fs_parser.o
CC kernel/seccomp.o
CC drivers/acpi/acpica/nsxfname.o
CC lib/interval_tree.o
CC drivers/base/cpu.o
AR drivers/gpu/drm/virtio/built-in.a
CC drivers/gpu/drm/drm_bridge.o
CC drivers/base/firmware.o
CC fs/fsopen.o
CC [M] drivers/gpu/drm/xe/xe_drm_client.o
CC net/wireless/ap.o
CC drivers/gpu/drm/i915/i915_debugfs_params.o
CC net/ipv4/fib_semantics.o
CC lib/assoc_array.o
CC drivers/tty/serial/earlycon.o
CC kernel/relay.o
CC fs/nfs/nfs4super.o
CC drivers/acpi/acpica/nsxfobj.o
CC drivers/base/init.o
CC kernel/utsname_sysctl.o
CC lib/bitrev.o
CC drivers/acpi/pci_irq.o
CC arch/x86/kernel/io_delay.o
CC drivers/scsi/scsi_scan.o
GEN drivers/scsi/scsi_devinfo_tbl.c
CC arch/x86/kernel/rtc.o
CC net/ipv6/fib6_notifier.o
CC arch/x86/kernel/resource.o
CC drivers/gpu/drm/drm_cache.o
CC net/ipv6/rpl.o
AS arch/x86/kernel/irqflags.o
CC drivers/acpi/acpi_apd.o
CC lib/crc-ccitt.o
CC drivers/base/map.o
CC drivers/gpu/drm/drm_client.o
CC drivers/scsi/scsi_devinfo.o
CC lib/crc16.o
CC drivers/gpu/drm/drm_client_modeset.o
CC drivers/acpi/acpi_platform.o
CC drivers/acpi/acpica/psargs.o
CC drivers/acpi/acpica/psloop.o
HOSTCC lib/gen_crc32table
CC arch/x86/kernel/static_call.o
CC fs/init.o
CC mm/early_ioremap.o
CC drivers/gpu/drm/drm_color_mgmt.o
AR net/sunrpc/built-in.a
CC net/ipv6/ioam6.o
CC drivers/acpi/acpi_pnp.o
CC fs/nfs/nfs4file.o
CC mm/secretmem.o
CC drivers/gpu/drm/i915/i915_pmu.o
CC [M] drivers/gpu/drm/xe/xe_exec.o
AR drivers/tty/serial/built-in.a
AR drivers/tty/built-in.a
CC lib/xxhash.o
CC lib/genalloc.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
CC lib/percpu_counter.o
CC drivers/ata/libata-core.o
CC net/ipv4/fib_trie.o
CC drivers/ata/libata-scsi.o
CC net/mac80211/wme.o
CC drivers/ata/libata-eh.o
CC drivers/base/devres.o
CC mm/hmm.o
CC drivers/scsi/scsi_sysctl.o
CC net/wireless/trace.o
CC fs/nfs/delegation.o
CC arch/x86/kernel/process.o
CC drivers/acpi/power.o
CC drivers/acpi/event.o
CC drivers/acpi/acpica/psobject.o
CC drivers/gpu/drm/i915/gt/gen2_engine_cs.o
CC drivers/acpi/evged.o
CC net/mac80211/chan.o
CC drivers/acpi/sysfs.o
CC kernel/delayacct.o
CC kernel/taskstats.o
CC arch/x86/kernel/ptrace.o
CC drivers/scsi/scsi_proc.o
CC fs/nfs/nfs4idmap.o
CC drivers/scsi/scsi_debugfs.o
CC net/ipv4/fib_notifier.o
CC [M] drivers/gpu/drm/xe/xe_exec_queue.o
CC net/mac80211/trace.o
CC fs/nfs/callback.o
CC net/ipv6/sysctl_net_ipv6.o
AR drivers/net/phy/qcom/built-in.a
CC net/ipv4/inet_fragment.o
CC net/ipv6/xfrm6_policy.o
CC net/mac80211/mlme.o
CC drivers/net/phy/mdio-boardinfo.o
CC drivers/gpu/drm/drm_connector.o
CC lib/audit.o
CC drivers/acpi/acpica/psopcode.o
AR drivers/net/pse-pd/built-in.a
CC net/ipv6/xfrm6_state.o
CC fs/nfs/callback_xdr.o
CC drivers/base/attribute_container.o
CC drivers/acpi/property.o
CC drivers/acpi/debugfs.o
CC drivers/firewire/init_ohci1394_dma.o
CC mm/memfd.o
CC kernel/tsacct.o
CC drivers/gpu/drm/drm_crtc.o
CC net/ipv4/ping.o
CC drivers/acpi/acpica/psopinfo.o
CC drivers/acpi/acpi_lpat.o
CC net/ipv4/ip_tunnel_core.o
CC fs/nfs/callback_proc.o
CC drivers/scsi/scsi_trace.o
CC drivers/scsi/scsi_logging.o
CC lib/syscall.o
CC net/wireless/ocb.o
CC fs/kernel_read_file.o
CC drivers/base/transport_class.o
CC drivers/gpu/drm/i915/gt/gen6_engine_cs.o
CC drivers/base/topology.o
CC drivers/base/container.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
CC drivers/acpi/acpica/psparse.o
CC drivers/net/phy/stubs.o
CC net/ipv4/gre_offload.o
CC drivers/net/phy/mdio_devres.o
CC arch/x86/kernel/tls.o
CC net/ipv4/metrics.o
AR drivers/firewire/built-in.a
CC drivers/gpu/drm/drm_displayid.o
CC net/ipv6/xfrm6_input.o
CC kernel/tracepoint.o
CC drivers/gpu/drm/i915/gt/gen6_ppgtt.o
CC net/mac80211/tdls.o
CC fs/nfs/nfs4namespace.o
CC drivers/acpi/acpi_pcc.o
CC drivers/cdrom/cdrom.o
CC net/ipv6/xfrm6_output.o
CC drivers/gpu/drm/drm_drv.o
CC lib/errname.o
CC net/ipv4/netlink.o
CC net/ipv4/nexthop.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
CC lib/nlattr.o
CC mm/ptdump.o
CC drivers/acpi/acpica/psscope.o
CC mm/execmem.o
CC drivers/acpi/acpica/pstree.o
CC drivers/base/property.o
CC drivers/gpu/drm/drm_dumb_buffers.o
CC drivers/gpu/drm/drm_edid.o
CC drivers/acpi/ac.o
CC lib/cpu_rmap.o
CC net/wireless/pmsr.o
CC drivers/scsi/scsi_pm.o
CC net/ipv4/udp_tunnel_stub.o
CC net/ipv4/ip_tunnel.o
CC drivers/net/phy/phy.o
CC net/ipv6/xfrm6_protocol.o
CC net/ipv6/netfilter.o
CC drivers/base/cacheinfo.o
AR drivers/auxdisplay/built-in.a
CC net/ipv6/proc.o
CC drivers/acpi/acpica/psutils.o
CC drivers/acpi/acpica/pswalk.o
CC arch/x86/kernel/step.o
CC kernel/irq_work.o
CC fs/mnt_idmapping.o
CC drivers/net/mdio/acpi_mdio.o
CC net/ipv6/syncookies.o
AR mm/built-in.a
CC drivers/net/phy/phy-c45.o
CC fs/nfs/nfs4getroot.o
CC drivers/net/phy/phy-core.o
CC drivers/gpu/drm/i915/gt/gen7_renderclear.o
CC drivers/acpi/acpica/psxface.o
AR drivers/net/pcs/built-in.a
CC drivers/acpi/button.o
CC arch/x86/kernel/i8237.o
CC net/ipv6/calipso.o
CC net/ipv4/sysctl_net_ipv4.o
AR drivers/net/wireless/admtek/built-in.a
AR drivers/net/ethernet/3com/built-in.a
AR drivers/net/wireless/ath/built-in.a
CC drivers/ata/libata-transport.o
CC drivers/net/ethernet/8390/ne2k-pci.o
CC drivers/ata/libata-trace.o
AR drivers/net/wireless/atmel/built-in.a
AR drivers/net/wireless/broadcom/built-in.a
AR drivers/net/wireless/intel/built-in.a
AR drivers/net/wireless/intersil/built-in.a
CC drivers/net/ethernet/8390/8390.o
AR drivers/net/wireless/marvell/built-in.a
AR drivers/net/wireless/mediatek/built-in.a
AR drivers/net/ethernet/adaptec/built-in.a
AR drivers/net/wireless/microchip/built-in.a
CC drivers/scsi/scsi_bsg.o
CC fs/nfs/nfs4client.o
AR drivers/net/wireless/purelifi/built-in.a
CC fs/nfs/nfs4session.o
AR drivers/net/wireless/quantenna/built-in.a
CC net/ipv6/ah6.o
CC drivers/net/mdio/fwnode_mdio.o
AR drivers/net/wireless/ralink/built-in.a
CC kernel/static_call.o
CC [M] drivers/gpu/drm/xe/xe_gpu_scheduler.o
AR drivers/net/wireless/realtek/built-in.a
AR drivers/net/wireless/rsi/built-in.a
CC drivers/acpi/acpica/rsaddr.o
CC drivers/gpu/drm/i915/gt/gen8_engine_cs.o
AR drivers/net/wireless/silabs/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gsc.o
AR drivers/net/wireless/st/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gsc_debugfs.o
AR drivers/net/wireless/ti/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gsc_proxy.o
AR drivers/net/wireless/zydas/built-in.a
AR drivers/net/wireless/virtual/built-in.a
CC arch/x86/kernel/stacktrace.o
CC [M] drivers/gpu/drm/xe/xe_gsc_submit.o
AR drivers/net/wireless/built-in.a
CC lib/dynamic_queue_limits.o
CC fs/remap_range.o
CC arch/x86/kernel/reboot.o
CC drivers/base/swnode.o
CC kernel/padata.o
CC kernel/jump_label.o
CC [M] drivers/gpu/drm/xe/xe_gt.o
CC drivers/acpi/acpica/rscalc.o
AR drivers/net/usb/built-in.a
CC drivers/acpi/fan_core.o
CC drivers/scsi/scsi_common.o
CC drivers/gpu/drm/i915/gt/gen8_ppgtt.o
CC net/ipv6/esp6.o
AR drivers/cdrom/built-in.a
CC drivers/scsi/scsi_transport_spi.o
CC drivers/acpi/acpica/rscreate.o
CC [M] drivers/gpu/drm/xe/xe_gt_ccs_mode.o
CC net/ipv6/sit.o
CC net/ipv4/proc.o
CC drivers/net/phy/phy_device.o
CC drivers/base/auxiliary.o
CC drivers/acpi/acpica/rsdumpinfo.o
CC arch/x86/kernel/msr.o
CC net/ipv6/addrconf_core.o
CC drivers/ata/libata-sata.o
CC drivers/scsi/virtio_scsi.o
CC fs/nfs/dns_resolve.o
CC net/ipv6/exthdrs_core.o
CC drivers/base/devtmpfs.o
AR drivers/net/mdio/built-in.a
CC drivers/net/mii.o
GEN net/wireless/shipped-certs.c
CC drivers/net/loopback.o
CC arch/x86/kernel/cpuid.o
AR drivers/net/ethernet/agere/built-in.a
CC drivers/gpu/drm/drm_eld.o
CC drivers/net/netconsole.o
AR drivers/net/ethernet/8390/built-in.a
AR drivers/net/ethernet/alacritech/built-in.a
CC drivers/acpi/fan_attr.o
CC lib/glob.o
CC drivers/acpi/fan_hwmon.o
CC lib/strncpy_from_user.o
AR drivers/net/ethernet/alteon/built-in.a
AR drivers/net/ethernet/amazon/built-in.a
CC drivers/acpi/acpica/rsinfo.o
AR drivers/net/ethernet/amd/built-in.a
CC drivers/acpi/acpica/rsio.o
CC drivers/pcmcia/cs.o
AR drivers/net/ethernet/aquantia/built-in.a
CC drivers/acpi/acpica/rsirq.o
AR drivers/net/ethernet/arc/built-in.a
CC fs/nfs/nfs4trace.o
CC drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
AR drivers/net/ethernet/asix/built-in.a
CC net/ipv4/fib_rules.o
AR drivers/net/ethernet/atheros/built-in.a
CC kernel/context_tracking.o
CC drivers/acpi/acpica/rslist.o
AR drivers/net/ethernet/cadence/built-in.a
CC drivers/net/ethernet/broadcom/bnx2.o
CC drivers/ata/libata-sff.o
CC drivers/net/ethernet/broadcom/tg3.o
CC drivers/gpu/drm/drm_encoder.o
AR drivers/net/ethernet/brocade/built-in.a
CC fs/nfs/nfs4sysctl.o
AR drivers/net/ethernet/cavium/common/built-in.a
AR drivers/net/ethernet/cavium/thunder/built-in.a
AR drivers/net/ethernet/cavium/liquidio/built-in.a
AR drivers/net/ethernet/cavium/octeon/built-in.a
AR drivers/net/ethernet/cavium/built-in.a
AR drivers/net/ethernet/chelsio/built-in.a
CC net/ipv4/ipmr.o
CC lib/strnlen_user.o
CC drivers/net/phy/linkmode.o
CC net/ipv4/ipmr_base.o
CC net/wireless/shipped-certs.o
CC drivers/ata/libata-pmp.o
CC arch/x86/kernel/early-quirks.o
CC drivers/acpi/acpi_video.o
CC drivers/acpi/video_detect.o
CC drivers/acpi/acpica/rsmemory.o
CC drivers/gpu/drm/i915/gt/intel_context.o
CC drivers/acpi/acpica/rsmisc.o
AR drivers/net/ethernet/cisco/built-in.a
CC drivers/acpi/acpica/rsserial.o
CC arch/x86/kernel/smp.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
CC arch/x86/kernel/smpboot.o
CC net/mac80211/ocb.o
CC drivers/base/module.o
CC drivers/gpu/drm/drm_file.o
CC arch/x86/kernel/tsc_sync.o
CC fs/ext4/symlink.o
CC net/ipv6/ip6_checksum.o
CC net/ipv4/syncookies.o
CC net/ipv4/tunnel4.o
CC net/ipv6/ip6_icmp.o
CC drivers/ata/libata-acpi.o
CC drivers/pcmcia/socket_sysfs.o
CC drivers/net/virtio_net.o
CC lib/net_utils.o
CC drivers/gpu/drm/drm_fourcc.o
CC net/ipv4/ipconfig.o
CC drivers/scsi/sd.o
CC drivers/base/auxiliary_sysfs.o
CC drivers/pcmcia/cardbus.o
CC kernel/iomem.o
CC drivers/acpi/acpica/rsutils.o
CC drivers/pcmcia/ds.o
CC lib/sg_pool.o
CC fs/ext4/sysfs.o
CC drivers/base/devcoredump.o
CC net/ipv6/output_core.o
CC net/ipv6/protocol.o
CC arch/x86/kernel/setup_percpu.o
CC drivers/gpu/drm/drm_framebuffer.o
CC net/ipv4/netfilter.o
CC drivers/gpu/drm/drm_gem.o
CC fs/ext4/xattr.o
CC lib/stackdepot.o
CC [M] drivers/gpu/drm/xe/xe_gt_freq.o
CC drivers/gpu/drm/i915/gt/intel_context_sseu.o
CC kernel/rseq.o
CC net/ipv6/ip6_offload.o
CC drivers/net/phy/mdio_bus.o
CC drivers/pcmcia/pcmcia_resource.o
CC drivers/ata/libata-pata-timings.o
CC drivers/acpi/acpica/rsxface.o
CC drivers/gpu/drm/i915/gt/intel_engine_cs.o
CC arch/x86/kernel/mpparse.o
CC lib/asn1_decoder.o
CC [M] drivers/gpu/drm/xe/xe_gt_idle.o
CC drivers/net/phy/mdio_device.o
CC drivers/acpi/acpica/tbdata.o
CC drivers/acpi/processor_driver.o
CC net/mac80211/airtime.o
CC net/ipv6/tcpv6_offload.o
CC drivers/gpu/drm/drm_ioctl.o
CC net/ipv6/exthdrs_offload.o
CC drivers/net/phy/swphy.o
CC drivers/pcmcia/cistpl.o
CC drivers/base/platform-msi.o
CC fs/ext4/xattr_hurd.o
GEN lib/oid_registry_data.c
CC drivers/ata/ahci.o
CC drivers/ata/libahci.o
CC drivers/acpi/acpica/tbfadt.o
CC lib/ucs2_string.o
CC drivers/base/physical_location.o
CC drivers/net/net_failover.o
CC lib/sbitmap.o
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
CC lib/group_cpus.o
CC drivers/acpi/acpica/tbfind.o
CC arch/x86/kernel/trace_clock.o
CC drivers/base/trace.o
CC net/ipv4/tcp_cubic.o
CC net/ipv6/inet6_hashtables.o
CC arch/x86/kernel/trace.o
CC drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
CC drivers/net/phy/fixed_phy.o
CC arch/x86/kernel/rethook.o
CC net/ipv4/tcp_sigpool.o
AR kernel/built-in.a
CC net/mac80211/eht.o
CC arch/x86/kernel/vmcore_info_32.o
CC arch/x86/kernel/machine_kexec_32.o
AS arch/x86/kernel/relocate_kernel_32.o
CC drivers/acpi/acpica/tbinstal.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
CC drivers/gpu/drm/drm_lease.o
CC drivers/gpu/drm/i915/gt/intel_engine_pm.o
CC drivers/gpu/drm/i915/gt/intel_engine_user.o
CC arch/x86/kernel/crash_dump_32.o
CC [M] drivers/gpu/drm/xe/xe_gt_throttle.o
CC fs/ext4/xattr_trusted.o
CC drivers/gpu/drm/drm_managed.o
CC drivers/net/phy/realtek.o
CC drivers/pcmcia/pcmcia_cis.o
CC drivers/gpu/drm/drm_mm.o
CC arch/x86/kernel/crash.o
CC net/mac80211/led.o
CC arch/x86/kernel/module.o
CC net/mac80211/pm.o
CC drivers/acpi/acpica/tbprint.o
CC net/mac80211/rc80211_minstrel_ht.o
CC arch/x86/kernel/doublefault_32.o
CC drivers/acpi/processor_thermal.o
CC drivers/acpi/processor_idle.o
AR drivers/base/built-in.a
AR drivers/net/ethernet/cortina/built-in.a
CC lib/fw_table.o
AR drivers/net/ethernet/dec/tulip/built-in.a
CC drivers/usb/common/common.o
AR drivers/net/ethernet/dec/built-in.a
CC drivers/usb/common/debug.o
CC net/mac80211/wbrf.o
CC arch/x86/kernel/early_printk.o
CC net/ipv4/cipso_ipv4.o
CC drivers/scsi/sr.o
CC drivers/ata/ata_piix.o
CC arch/x86/kernel/hpet.o
AR drivers/net/ethernet/dlink/built-in.a
AR drivers/net/ethernet/emulex/built-in.a
CC arch/x86/kernel/amd_nb.o
AR drivers/net/ethernet/ezchip/built-in.a
AR drivers/net/ethernet/engleder/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
AR drivers/net/ethernet/fujitsu/built-in.a
CC arch/x86/kernel/kvm.o
AR drivers/net/ethernet/fungible/built-in.a
AR drivers/net/ethernet/google/built-in.a
CC arch/x86/kernel/kvmclock.o
AR drivers/net/ethernet/huawei/built-in.a
CC drivers/ata/pata_amd.o
CC drivers/acpi/acpica/tbutils.o
CC drivers/usb/core/usb.o
CC drivers/acpi/acpica/tbxface.o
CC drivers/usb/core/hub.o
CC drivers/acpi/acpica/tbxfload.o
AR drivers/usb/phy/built-in.a
CC fs/ext4/xattr_user.o
CC fs/ext4/fast_commit.o
CC drivers/usb/mon/mon_main.o
AR fs/nfs/built-in.a
CC drivers/ata/pata_oldpiix.o
CC net/ipv4/xfrm4_policy.o
CC drivers/gpu/drm/drm_mode_config.o
CC drivers/usb/mon/mon_stat.o
CC drivers/ata/pata_sch.o
CC net/ipv4/xfrm4_state.o
CC fs/ext4/orphan.o
CC fs/pidfs.o
CC drivers/usb/host/pci-quirks.o
AR lib/lib.a
CC drivers/pcmcia/rsrc_mgr.o
CC drivers/usb/host/ehci-hcd.o
GEN lib/crc32table.h
CC lib/oid_registry.o
CC drivers/acpi/processor_throttling.o
CC arch/x86/kernel/paravirt.o
CC net/ipv6/mcast_snoop.o
CC drivers/acpi/processor_perflib.o
CC drivers/gpu/drm/drm_mode_object.o
CC drivers/usb/core/hcd.o
CC drivers/usb/class/usblp.o
CC drivers/acpi/acpica/tbxfroot.o
AR drivers/usb/common/built-in.a
CC drivers/gpu/drm/i915/gt/intel_execlists_submission.o
CC drivers/usb/mon/mon_text.o
AR drivers/net/phy/built-in.a
CC fs/buffer.o
CC drivers/net/ethernet/intel/e1000/e1000_main.o
CC drivers/net/ethernet/intel/e1000e/82571.o
CC drivers/net/ethernet/intel/e100.o
CC drivers/net/ethernet/intel/e1000e/ich8lan.o
CC drivers/usb/mon/mon_bin.o
CC lib/crc32.o
CC drivers/net/ethernet/intel/e1000/e1000_hw.o
AR drivers/net/ethernet/i825xx/built-in.a
AR drivers/net/ethernet/microsoft/built-in.a
CC drivers/acpi/container.o
CC net/ipv4/xfrm4_input.o
CC drivers/net/ethernet/intel/e1000e/80003es2lan.o
CC drivers/scsi/sr_ioctl.o
CC drivers/usb/storage/scsiglue.o
CC drivers/acpi/acpica/utaddress.o
CC drivers/usb/storage/protocol.o
CC drivers/acpi/acpica/utalloc.o
CC drivers/usb/storage/transport.o
CC drivers/pcmcia/rsrc_nonstatic.o
CC fs/mpage.o
CC drivers/scsi/sr_vendor.o
CC drivers/ata/pata_mpiix.o
CC fs/proc_namespace.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
CC fs/direct-io.o
CC arch/x86/kernel/pvclock.o
CC arch/x86/kernel/pcspeaker.o
CC drivers/net/ethernet/intel/e1000/e1000_ethtool.o
CC drivers/scsi/sg.o
CC [M] drivers/gpu/drm/xe/xe_guc.o
CC fs/eventpoll.o
CC net/ipv4/xfrm4_output.o
CC drivers/usb/core/urb.o
CC drivers/acpi/thermal_lib.o
CC drivers/usb/core/message.o
AR lib/built-in.a
CC drivers/acpi/thermal.o
CC drivers/gpu/drm/drm_modes.o
CC fs/ext4/acl.o
CC drivers/acpi/acpica/utascii.o
AR drivers/usb/class/built-in.a
CC drivers/gpu/drm/drm_modeset_lock.o
AR drivers/usb/misc/built-in.a
CC drivers/usb/early/ehci-dbgp.o
CC drivers/gpu/drm/drm_plane.o
CC drivers/usb/core/driver.o
AR net/ipv6/built-in.a
CC drivers/usb/core/config.o
CC drivers/acpi/nhlt.o
CC arch/x86/kernel/check.o
CC drivers/scsi/scsi_sysfs.o
CC drivers/usb/core/file.o
CC fs/ext4/xattr_security.o
CC drivers/acpi/acpica/utbuffer.o
AR drivers/usb/mon/built-in.a
CC drivers/usb/core/buffer.o
CC drivers/usb/core/sysfs.o
CC drivers/gpu/drm/i915/gt/intel_ggtt.o
CC drivers/ata/ata_generic.o
CC drivers/pcmcia/yenta_socket.o
CC fs/anon_inodes.o
CC drivers/usb/core/endpoint.o
CC drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
CC drivers/usb/storage/usb.o
AR drivers/net/ethernet/litex/built-in.a
CC drivers/acpi/acpica/utcksum.o
CC drivers/usb/host/ehci-pci.o
CC drivers/net/ethernet/intel/e1000e/mac.o
CC drivers/acpi/acpica/utcopy.o
CC drivers/gpu/drm/i915/gt/intel_gt.o
CC drivers/net/ethernet/intel/e1000/e1000_param.o
CC drivers/acpi/acpi_memhotplug.o
CC drivers/gpu/drm/drm_prime.o
CC drivers/net/ethernet/intel/e1000e/manage.o
CC drivers/usb/core/devio.o
CC drivers/usb/core/notify.o
CC net/ipv4/xfrm4_protocol.o
CC arch/x86/kernel/uprobes.o
CC fs/signalfd.o
AR drivers/usb/early/built-in.a
CC drivers/gpu/drm/drm_print.o
CC drivers/usb/core/generic.o
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
CC drivers/acpi/acpica/utexcep.o
CC drivers/acpi/acpica/utdebug.o
CC drivers/acpi/acpica/utdecode.o
CC drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
CC drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.o
CC drivers/usb/core/quirks.o
CC drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
CC drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
CC fs/timerfd.o
CC fs/eventfd.o
CC drivers/usb/core/devices.o
AR drivers/ata/built-in.a
CC drivers/gpu/drm/drm_property.o
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
CC drivers/usb/host/ohci-hcd.o
CC drivers/usb/core/phy.o
CC drivers/usb/host/ohci-pci.o
AR net/mac80211/built-in.a
CC arch/x86/kernel/perf_regs.o
CC drivers/net/ethernet/intel/e1000e/nvm.o
AR fs/ext4/built-in.a
CC arch/x86/kernel/tracepoint.o
CC drivers/usb/core/port.o
CC [M] drivers/gpu/drm/xe/xe_guc_db_mgr.o
CC drivers/usb/core/hcd-pci.o
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
AR drivers/net/ethernet/marvell/octeon_ep/built-in.a
AR drivers/net/ethernet/marvell/octeon_ep_vf/built-in.a
CC drivers/gpu/drm/drm_syncobj.o
AR drivers/scsi/built-in.a
CC drivers/gpu/drm/drm_sysfs.o
AR drivers/net/ethernet/marvell/octeontx2/built-in.a
CC drivers/gpu/drm/drm_trace_points.o
AR drivers/net/ethernet/marvell/prestera/built-in.a
CC drivers/acpi/ioapic.o
CC drivers/net/ethernet/marvell/sky2.o
CC drivers/acpi/acpica/utdelete.o
CC drivers/usb/core/usb-acpi.o
CC drivers/gpu/drm/drm_vblank.o
CC drivers/input/serio/serio.o
CC drivers/usb/storage/initializers.o
CC drivers/input/serio/i8042.o
CC drivers/net/ethernet/intel/e1000e/phy.o
AR drivers/pcmcia/built-in.a
CC fs/aio.o
CC drivers/usb/storage/sierra_ms.o
CC drivers/input/keyboard/atkbd.o
CC drivers/input/mouse/psmouse-base.o
CC drivers/rtc/lib.o
AR drivers/input/joystick/built-in.a
AR drivers/input/tablet/built-in.a
AR net/wireless/built-in.a
CC drivers/i2c/algos/i2c-algo-bit.o
CC drivers/i2c/busses/i2c-i801.o
AR drivers/i2c/muxes/built-in.a
AR drivers/input/touchscreen/built-in.a
CC drivers/rtc/class.o
CC drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
AR drivers/input/misc/built-in.a
CC drivers/i2c/i2c-boardinfo.o
CC drivers/i2c/i2c-core-base.o
CC drivers/usb/host/uhci-hcd.o
CC fs/locks.o
CC drivers/acpi/acpica/uterror.o
AR drivers/net/ethernet/intel/e1000/built-in.a
CC drivers/usb/storage/option_ms.o
CC drivers/usb/storage/usual-tables.o
AR net/ipv4/built-in.a
AR net/built-in.a
CC fs/binfmt_misc.o
CC arch/x86/kernel/itmt.o
CC drivers/gpu/drm/i915/gt/intel_gt_irq.o
AR drivers/net/ethernet/mellanox/built-in.a
CC drivers/acpi/acpica/uteval.o
CC drivers/acpi/acpica/utglobal.o
CC arch/x86/kernel/umip.o
CC drivers/input/serio/serport.o
CC drivers/input/mouse/synaptics.o
CC [M] drivers/gpu/drm/xe/xe_guc_id_mgr.o
CC drivers/rtc/interface.o
CC drivers/input/input.o
CC [M] drivers/gpu/drm/xe/xe_guc_klv_helpers.o
CC drivers/net/ethernet/intel/e1000e/param.o
CC drivers/gpu/drm/drm_vblank_work.o
CC arch/x86/kernel/unwind_frame.o
AR drivers/i3c/built-in.a
CC drivers/rtc/nvmem.o
AR drivers/media/i2c/built-in.a
CC drivers/gpu/drm/drm_vma_manager.o
CC drivers/gpu/drm/i915/gt/intel_gt_mcr.o
AR drivers/media/tuners/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gt_pm.o
AR drivers/media/rc/keymaps/built-in.a
AR drivers/media/rc/built-in.a
CC drivers/gpu/drm/drm_writeback.o
CC drivers/acpi/acpica/uthex.o
AR drivers/media/common/b2c2/built-in.a
AR drivers/media/platform/allegro-dvt/built-in.a
AR drivers/media/common/saa7146/built-in.a
AR drivers/media/platform/amlogic/meson-ge2d/built-in.a
AR drivers/media/platform/amlogic/built-in.a
AR drivers/media/common/siano/built-in.a
AR drivers/media/usb/b2c2/built-in.a
AR drivers/media/pci/ttpci/built-in.a
AR drivers/media/pci/b2c2/built-in.a
AR drivers/media/usb/dvb-usb/built-in.a
AR drivers/media/platform/amphion/built-in.a
AR drivers/media/common/v4l2-tpg/built-in.a
AR drivers/media/usb/dvb-usb-v2/built-in.a
AR drivers/media/pci/pluto2/built-in.a
AR drivers/media/platform/aspeed/built-in.a
AR drivers/media/common/videobuf2/built-in.a
AR drivers/media/usb/s2255/built-in.a
AR drivers/media/pci/dm1105/built-in.a
AR drivers/media/common/built-in.a
AR drivers/media/platform/atmel/built-in.a
CC drivers/acpi/acpica/utids.o
AR drivers/media/usb/siano/built-in.a
AR drivers/media/platform/broadcom/built-in.a
AR drivers/media/pci/pt1/built-in.a
AR drivers/media/usb/ttusb-budget/built-in.a
AR drivers/media/pci/pt3/built-in.a
AR drivers/media/usb/ttusb-dec/built-in.a
AR drivers/media/platform/cadence/built-in.a
CC drivers/input/serio/libps2.o
AR drivers/media/usb/built-in.a
AR drivers/media/pci/mantis/built-in.a
AR drivers/media/pci/ddbridge/built-in.a
AR drivers/media/pci/ngene/built-in.a
AR drivers/media/platform/chips-media/coda/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
AR drivers/pps/clients/built-in.a
CC fs/binfmt_script.o
CC drivers/ptp/ptp_clock.o
AR drivers/pps/generators/built-in.a
AR drivers/media/pci/saa7146/built-in.a
AR drivers/media/platform/chips-media/wave5/built-in.a
CC drivers/power/supply/power_supply_core.o
AR drivers/media/platform/chips-media/built-in.a
CC drivers/pps/pps.o
AR drivers/media/pci/smipcie/built-in.a
CC drivers/power/supply/power_supply_sysfs.o
CC drivers/power/supply/power_supply_leds.o
AR drivers/media/platform/imagination/built-in.a
AR drivers/media/pci/netup_unidvb/built-in.a
AR drivers/media/platform/intel/built-in.a
AR drivers/media/pci/intel/ipu3/built-in.a
AR drivers/media/platform/marvell/built-in.a
CC drivers/power/supply/power_supply_hwmon.o
AR drivers/media/pci/intel/ivsc/built-in.a
AR drivers/media/platform/mediatek/jpeg/built-in.a
AR drivers/media/pci/intel/built-in.a
AR drivers/usb/core/built-in.a
AR drivers/media/platform/mediatek/mdp/built-in.a
AR drivers/media/pci/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
AR drivers/media/platform/mediatek/vcodec/common/built-in.a
AR drivers/input/keyboard/built-in.a
AR drivers/usb/storage/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
AR drivers/media/platform/mediatek/vpu/built-in.a
AR drivers/media/platform/mediatek/vcodec/encoder/built-in.a
AR drivers/i2c/algos/built-in.a
CC drivers/input/input-compat.o
CC drivers/gpu/drm/i915/gt/intel_gt_requests.o
CC drivers/rtc/dev.o
CC drivers/ptp/ptp_chardev.o
AR drivers/media/platform/mediatek/vcodec/decoder/built-in.a
AR drivers/media/platform/mediatek/mdp3/built-in.a
AR drivers/media/platform/mediatek/vcodec/built-in.a
CC drivers/gpu/drm/drm_panel.o
CC drivers/rtc/proc.o
CC drivers/i2c/i2c-core-smbus.o
AR drivers/media/platform/mediatek/built-in.a
AR drivers/media/platform/microchip/built-in.a
CC drivers/i2c/i2c-core-acpi.o
CC drivers/pps/kapi.o
AR drivers/media/platform/nuvoton/built-in.a
CC drivers/rtc/sysfs.o
AR drivers/media/platform/nvidia/tegra-vde/built-in.a
AR drivers/media/platform/nxp/dw100/built-in.a
AR drivers/media/platform/nvidia/built-in.a
AR drivers/media/platform/nxp/imx-jpeg/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_pc.o
AR drivers/media/platform/nxp/imx8-isi/built-in.a
AR drivers/i2c/busses/built-in.a
AR drivers/net/ethernet/meta/built-in.a
AR drivers/media/platform/nxp/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_submit.o
CC drivers/gpu/drm/drm_pci.o
CC [M] drivers/gpu/drm/xe/xe_heci_gsc.o
AR arch/x86/kernel/built-in.a
AR drivers/media/platform/qcom/camss/built-in.a
CC drivers/acpi/acpica/utinit.o
AR drivers/media/platform/qcom/venus/built-in.a
AR drivers/media/platform/qcom/built-in.a
AR arch/x86/built-in.a
CC [M] drivers/gpu/drm/xe/xe_hw_engine.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
AR drivers/media/platform/raspberrypi/pisp_be/built-in.a
AR drivers/media/platform/raspberrypi/built-in.a
AR drivers/net/ethernet/micrel/built-in.a
CC drivers/input/input-mt.o
CC drivers/input/input-poller.o
CC drivers/rtc/rtc-mc146818-lib.o
CC drivers/gpu/drm/drm_debugfs.o
AR drivers/media/platform/renesas/rcar-vin/built-in.a
AR drivers/media/platform/renesas/rzg2l-cru/built-in.a
CC drivers/ptp/ptp_sysfs.o
AR drivers/media/platform/renesas/vsp1/built-in.a
AR drivers/media/platform/renesas/built-in.a
CC drivers/ptp/ptp_vclock.o
CC fs/binfmt_elf.o
CC drivers/net/ethernet/intel/e1000e/ethtool.o
AR drivers/media/platform/rockchip/rga/built-in.a
AR drivers/media/platform/samsung/exynos-gsc/built-in.a
AR drivers/media/platform/rockchip/rkisp1/built-in.a
AR drivers/media/platform/samsung/exynos4-is/built-in.a
AR drivers/media/platform/rockchip/built-in.a
AR drivers/media/platform/samsung/s3c-camif/built-in.a
AR drivers/input/serio/built-in.a
AR drivers/media/platform/samsung/s5p-g2d/built-in.a
AR drivers/media/platform/samsung/s5p-jpeg/built-in.a
CC drivers/usb/host/xhci.o
AR drivers/net/ethernet/microchip/built-in.a
AR drivers/media/platform/st/sti/bdisp/built-in.a
CC drivers/pps/sysfs.o
AR drivers/media/platform/samsung/s5p-mfc/built-in.a
AR drivers/media/platform/samsung/built-in.a
AR drivers/media/platform/st/sti/c8sectpfe/built-in.a
CC fs/mbcache.o
CC drivers/usb/host/xhci-mem.o
AR drivers/media/platform/st/sti/delta/built-in.a
CC fs/posix_acl.o
CC drivers/input/mouse/focaltech.o
AR drivers/media/platform/st/sti/hva/built-in.a
CC drivers/hwmon/hwmon.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine_group.o
AR drivers/media/platform/st/stm32/built-in.a
AR drivers/media/platform/sunxi/sun4i-csi/built-in.a
AR drivers/media/platform/st/built-in.a
CC drivers/acpi/acpica/utlock.o
AR drivers/media/platform/sunxi/sun6i-csi/built-in.a
CC [M] drivers/gpu/drm/xe/xe_hw_fence.o
AR drivers/net/ethernet/myricom/built-in.a
AR drivers/net/ethernet/mscc/built-in.a
AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
CC drivers/input/ff-core.o
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
AR drivers/media/platform/sunxi/sun8i-di/built-in.a
AR drivers/power/supply/built-in.a
AR drivers/power/built-in.a
CC drivers/input/touchscreen.o
AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a
AR drivers/media/platform/sunxi/built-in.a
CC drivers/rtc/rtc-cmos.o
CC drivers/gpu/drm/drm_debugfs_crc.o
AR drivers/media/platform/ti/am437x/built-in.a
AR drivers/media/platform/ti/cal/built-in.a
CC drivers/input/ff-memless.o
AR drivers/media/platform/ti/vpe/built-in.a
CC drivers/ptp/ptp_kvm_x86.o
AR drivers/media/platform/ti/davinci/built-in.a
CC drivers/usb/host/xhci-ext-caps.o
AR drivers/media/platform/ti/j721e-csi2rx/built-in.a
AR drivers/media/platform/ti/omap/built-in.a
AR drivers/media/platform/ti/omap3isp/built-in.a
CC drivers/input/sparse-keymap.o
AR drivers/media/platform/ti/built-in.a
CC drivers/ptp/ptp_kvm_common.o
CC drivers/input/mouse/alps.o
CC drivers/acpi/battery.o
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
CC drivers/gpu/drm/drm_panel_orientation_quirks.o
CC drivers/gpu/drm/drm_buddy.o
AR drivers/media/platform/verisilicon/built-in.a
AR drivers/pps/built-in.a
AR drivers/media/platform/via/built-in.a
AR drivers/thermal/broadcom/built-in.a
AR drivers/media/platform/xilinx/built-in.a
AR drivers/watchdog/built-in.a
AR drivers/media/platform/built-in.a
AR drivers/thermal/renesas/built-in.a
CC drivers/md/md.o
CC drivers/cpufreq/cpufreq.o
CC [M] drivers/gpu/drm/xe/xe_huc.o
AR drivers/thermal/samsung/built-in.a
CC drivers/md/md-bitmap.o
CC drivers/thermal/intel/intel_tcc.o
CC drivers/acpi/acpica/utmath.o
AR drivers/thermal/st/built-in.a
AR drivers/thermal/qcom/built-in.a
CC drivers/i2c/i2c-smbus.o
AR drivers/media/firewire/built-in.a
AR drivers/media/mmc/siano/built-in.a
AR drivers/media/mmc/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gtt.o
CC drivers/input/vivaldi-fmap.o
AR drivers/media/spi/built-in.a
AR drivers/media/test-drivers/built-in.a
CC drivers/gpu/drm/i915/gt/intel_llc.o
AR drivers/media/built-in.a
AR drivers/thermal/tegra/built-in.a
CC drivers/thermal/thermal_core.o
AR drivers/thermal/mediatek/built-in.a
CC [M] drivers/gpu/drm/xe/xe_irq.o
CC drivers/acpi/acpica/utmisc.o
CC drivers/cpufreq/freq_table.o
CC drivers/gpu/drm/i915/gt/intel_lrc.o
CC drivers/thermal/intel/therm_throt.o
CC drivers/gpu/drm/i915/gt/intel_migrate.o
CC fs/coredump.o
CC drivers/cpufreq/cpufreq_performance.o
CC drivers/input/input-leds.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o
CC drivers/input/evdev.o
CC drivers/net/ethernet/intel/e1000e/netdev.o
AR drivers/net/ethernet/broadcom/built-in.a
AR drivers/net/ethernet/natsemi/built-in.a
AR drivers/net/ethernet/neterion/built-in.a
CC drivers/acpi/bgrt.o
CC drivers/usb/host/xhci-ring.o
AR drivers/net/ethernet/netronome/built-in.a
AR drivers/net/ethernet/ni/built-in.a
CC [M] drivers/gpu/drm/xe/xe_lrc.o
CC drivers/usb/host/xhci-hub.o
CC drivers/net/ethernet/nvidia/forcedeth.o
AR drivers/net/ethernet/oki-semi/built-in.a
CC [M] drivers/gpu/drm/xe/xe_migrate.o
CC drivers/cpufreq/cpufreq_userspace.o
CC drivers/cpufreq/cpufreq_ondemand.o
CC drivers/gpu/drm/i915/gt/intel_mocs.o
CC drivers/acpi/acpica/utmutex.o
CC drivers/input/mouse/byd.o
AR drivers/net/ethernet/marvell/built-in.a
CC drivers/usb/host/xhci-dbg.o
CC drivers/gpu/drm/i915/gt/intel_ppgtt.o
AR drivers/ptp/built-in.a
CC drivers/input/mouse/logips2pp.o
CC drivers/input/mouse/lifebook.o
CC drivers/cpuidle/governors/menu.o
CC drivers/cpuidle/cpuidle.o
CC drivers/cpufreq/cpufreq_governor.o
CC fs/drop_caches.o
CC fs/sysctls.o
AR drivers/rtc/built-in.a
CC drivers/input/mouse/trackpoint.o
CC [M] drivers/gpu/drm/xe/xe_mmio.o
CC [M] drivers/gpu/drm/xe/xe_mocs.o
AR drivers/i2c/built-in.a
CC drivers/gpu/drm/drm_gem_shmem_helper.o
AR drivers/mmc/built-in.a
CC drivers/md/md-autodetect.o
CC drivers/acpi/acpica/utnonansi.o
AR drivers/ufs/built-in.a
CC drivers/input/mouse/cypress_ps2.o
AR drivers/hwmon/built-in.a
CC drivers/acpi/acpica/utobject.o
AR drivers/net/ethernet/packetengines/built-in.a
CC drivers/acpi/acpica/utosi.o
CC drivers/cpufreq/cpufreq_governor_attr_set.o
CC drivers/acpi/acpica/utownerid.o
CC drivers/md/dm.o
AR drivers/leds/trigger/built-in.a
AR drivers/leds/blink/built-in.a
AR drivers/leds/simple/built-in.a
CC drivers/leds/led-core.o
CC drivers/net/ethernet/intel/e1000e/ptp.o
CC drivers/input/mouse/psmouse-smbus.o
CC drivers/md/dm-table.o
CC drivers/gpu/drm/i915/gt/intel_rc6.o
CC drivers/cpuidle/governors/haltpoll.o
CC [M] drivers/gpu/drm/xe/xe_module.o
CC drivers/usb/host/xhci-trace.o
CC drivers/gpu/drm/i915/gt/intel_region_lmem.o
CC drivers/cpufreq/acpi-cpufreq.o
CC drivers/usb/host/xhci-debugfs.o
CC drivers/acpi/acpica/utpredef.o
CC drivers/gpu/drm/drm_atomic_helper.o
AR drivers/thermal/intel/built-in.a
CC drivers/md/dm-target.o
CC drivers/thermal/thermal_sysfs.o
CC drivers/acpi/spcr.o
CC drivers/acpi/acpica/utresdecode.o
CC drivers/cpufreq/amd-pstate.o
CC drivers/acpi/acpica/utresrc.o
CC drivers/gpu/drm/drm_atomic_state_helper.o
CC drivers/gpu/drm/drm_crtc_helper.o
CC drivers/cpufreq/amd-pstate-trace.o
CC drivers/md/dm-linear.o
CC drivers/cpuidle/driver.o
AR drivers/firmware/arm_ffa/built-in.a
AR drivers/crypto/stm32/built-in.a
AR drivers/firmware/arm_scmi/built-in.a
AR drivers/crypto/xilinx/built-in.a
AR drivers/crypto/hisilicon/built-in.a
AR drivers/firmware/broadcom/built-in.a
CC drivers/md/dm-stripe.o
AR drivers/firmware/cirrus/built-in.a
AR drivers/crypto/intel/keembay/built-in.a
AR drivers/firmware/meson/built-in.a
CC drivers/leds/led-class.o
AR drivers/crypto/intel/ixp4xx/built-in.a
AR drivers/firmware/microchip/built-in.a
AR drivers/crypto/starfive/built-in.a
AR drivers/crypto/intel/built-in.a
CC drivers/usb/host/xhci-pci.o
CC drivers/clocksource/acpi_pm.o
CC drivers/clocksource/i8253.o
AR drivers/crypto/built-in.a
CC drivers/gpu/drm/i915/gt/intel_renderstate.o
CC drivers/acpi/acpica/utstate.o
CC drivers/gpu/drm/i915/gt/intel_reset.o
CC drivers/firmware/efi/efi-bgrt.o
CC fs/fhandle.o
CC drivers/firmware/efi/efi.o
CC drivers/firmware/efi/libstub/efi-stub-helper.o
CC drivers/firmware/efi/libstub/gop.o
CC drivers/gpu/drm/i915/gt/intel_ring.o
CC drivers/cpuidle/governor.o
AR drivers/input/mouse/built-in.a
AR drivers/input/built-in.a
CC drivers/hid/usbhid/hid-core.o
CC drivers/gpu/drm/i915/gt/intel_ring_submission.o
CC drivers/hid/usbhid/hiddev.o
CC drivers/cpuidle/sysfs.o
CC drivers/thermal/thermal_trip.o
CC drivers/cpuidle/poll_state.o
CC drivers/cpuidle/cpuidle-haltpoll.o
CC [M] drivers/gpu/drm/xe/xe_oa.o
CC [M] drivers/gpu/drm/xe/xe_observation.o
CC drivers/acpi/acpica/utstring.o
CC drivers/cpufreq/intel_pstate.o
CC drivers/md/dm-ioctl.o
CC drivers/leds/led-triggers.o
AR drivers/firmware/imx/built-in.a
CC drivers/md/dm-io.o
AR drivers/cpuidle/governors/built-in.a
AR drivers/platform/x86/amd/built-in.a
AR drivers/platform/surface/built-in.a
CC drivers/platform/x86/wmi.o
AR drivers/platform/x86/intel/built-in.a
CC drivers/firmware/efi/libstub/secureboot.o
AR drivers/firmware/psci/built-in.a
CC drivers/firmware/efi/libstub/tpm.o
CC drivers/firmware/efi/libstub/file.o
CC drivers/firmware/efi/libstub/mem.o
CC drivers/firmware/efi/libstub/random.o
CC drivers/platform/x86/wmi-bmof.o
CC drivers/firmware/efi/libstub/randomalloc.o
CC drivers/firmware/efi/libstub/pci.o
CC [M] drivers/gpu/drm/xe/xe_pat.o
CC [M] drivers/gpu/drm/xe/xe_pci.o
AR drivers/clocksource/built-in.a
CC drivers/mailbox/mailbox.o
CC [M] drivers/gpu/drm/xe/xe_pcode.o
CC drivers/mailbox/pcc.o
AR drivers/perf/built-in.a
CC drivers/thermal/thermal_helpers.o
AR drivers/hwtracing/intel_th/built-in.a
AR drivers/android/built-in.a
CC drivers/gpu/drm/drm_damage_helper.o
CC drivers/acpi/acpica/utstrsuppt.o
CC drivers/acpi/acpica/utstrtoul64.o
CC drivers/gpu/drm/i915/gt/intel_rps.o
CC [M] drivers/gpu/drm/xe/xe_pm.o
CC drivers/hid/usbhid/hid-pidff.o
AR drivers/cpuidle/built-in.a
AR drivers/net/ethernet/qlogic/built-in.a
CC drivers/net/ethernet/realtek/8139too.o
AR drivers/net/ethernet/renesas/built-in.a
AR drivers/net/ethernet/qualcomm/emac/built-in.a
AR fs/built-in.a
CC drivers/firmware/efi/libstub/skip_spaces.o
AR drivers/net/ethernet/qualcomm/built-in.a
AR drivers/net/ethernet/rdc/built-in.a
AR drivers/net/ethernet/rocker/built-in.a
AR drivers/net/ethernet/samsung/built-in.a
AR drivers/net/ethernet/seeq/built-in.a
CC drivers/net/ethernet/realtek/r8169_main.o
AR drivers/net/ethernet/silan/built-in.a
CC drivers/gpu/drm/drm_encoder_slave.o
CC drivers/thermal/thermal_hwmon.o
AR drivers/net/ethernet/sis/built-in.a
AR drivers/net/ethernet/sfc/built-in.a
CC drivers/firmware/efi/libstub/lib-cmdline.o
CC drivers/net/ethernet/realtek/r8169_firmware.o
CC drivers/acpi/acpica/utxface.o
CC drivers/gpu/drm/i915/gt/intel_sa_media.o
CC drivers/md/dm-kcopyd.o
CC drivers/md/dm-sysfs.o
CC drivers/md/dm-stats.o
AR drivers/leds/built-in.a
CC drivers/platform/x86/eeepc-laptop.o
CC drivers/acpi/acpica/utxfinit.o
AR drivers/nvmem/layouts/built-in.a
CC drivers/firmware/efi/libstub/lib-ctype.o
CC drivers/nvmem/core.o
CC drivers/acpi/acpica/utxferror.o
CC drivers/gpu/drm/i915/gt/intel_sseu.o
CC drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
CC drivers/firmware/efi/libstub/alignedmem.o
CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o
CC drivers/gpu/drm/i915/gt/intel_timeline.o
CC drivers/md/dm-rq.o
CC drivers/thermal/gov_step_wise.o
AR drivers/net/ethernet/smsc/built-in.a
CC drivers/firmware/efi/libstub/relocate.o
CC drivers/hid/hid-core.o
AR drivers/mailbox/built-in.a
CC drivers/gpu/drm/i915/gt/intel_tlb.o
CC drivers/thermal/gov_user_space.o
CC drivers/gpu/drm/i915/gt/intel_wopcm.o
CC drivers/hid/hid-input.o
CC drivers/hid/hid-quirks.o
CC drivers/net/ethernet/realtek/r8169_phy_config.o
CC drivers/firmware/efi/libstub/printk.o
CC drivers/firmware/efi/libstub/vsprintf.o
CC drivers/gpu/drm/drm_flip_work.o
CC drivers/md/dm-io-rewind.o
CC drivers/md/dm-builtin.o
CC drivers/platform/x86/p2sb.o
CC drivers/acpi/acpica/utxfmutex.o
CC [M] drivers/gpu/drm/xe/xe_pt.o
CC drivers/gpu/drm/i915/gt/intel_workarounds.o
AR drivers/net/ethernet/socionext/built-in.a
AR drivers/net/ethernet/stmicro/built-in.a
AR drivers/net/ethernet/nvidia/built-in.a
CC drivers/md/dm-raid1.o
AR drivers/net/ethernet/sun/built-in.a
AR drivers/net/ethernet/tehuti/built-in.a
AR drivers/net/ethernet/ti/built-in.a
AR drivers/net/ethernet/vertexcom/built-in.a
AR drivers/net/ethernet/via/built-in.a
CC [M] drivers/gpu/drm/xe/xe_pt_walk.o
AR drivers/net/ethernet/wangxun/built-in.a
CC drivers/firmware/efi/vars.o
AR drivers/usb/host/built-in.a
CC drivers/gpu/drm/drm_format_helper.o
AR drivers/usb/built-in.a
CC drivers/gpu/drm/drm_gem_atomic_helper.o
CC [M] drivers/gpu/drm/xe/xe_query.o
CC [M] drivers/gpu/drm/xe/xe_range_fence.o
AR drivers/thermal/built-in.a
CC drivers/gpu/drm/i915/gt/shmem_utils.o
CC [M] drivers/gpu/drm/xe/xe_reg_sr.o
CC drivers/md/dm-log.o
CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o
AR drivers/acpi/acpica/built-in.a
AR drivers/acpi/built-in.a
CC [M] drivers/gpu/drm/xe/xe_rtp.o
CC drivers/hid/hid-debug.o
CC drivers/hid/hidraw.o
CC drivers/firmware/efi/libstub/x86-stub.o
CC drivers/firmware/efi/reboot.o
AR drivers/hid/usbhid/built-in.a
CC drivers/md/dm-region-hash.o
CC drivers/hid/hid-generic.o
CC drivers/gpu/drm/drm_gem_framebuffer_helper.o
CC [M] drivers/gpu/drm/xe/xe_ring_ops.o
CC drivers/firmware/efi/libstub/smbios.o
STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
CC drivers/gpu/drm/drm_kms_helper_common.o
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
CC drivers/md/dm-zero.o
STUBCPY drivers/firmware/efi/libstub/file.stub.o
CC drivers/hid/hid-a4tech.o
CC [M] drivers/gpu/drm/xe/xe_sa.o
STUBCPY drivers/firmware/efi/libstub/gop.stub.o
AR drivers/firmware/qcom/built-in.a
STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
AR drivers/net/ethernet/wiznet/built-in.a
STUBCPY drivers/firmware/efi/libstub/mem.stub.o
AR drivers/platform/x86/built-in.a
AR drivers/firmware/smccc/built-in.a
STUBCPY drivers/firmware/efi/libstub/pci.stub.o
STUBCPY drivers/firmware/efi/libstub/printk.stub.o
CC [M] drivers/gpu/drm/xe/xe_sched_job.o
AR drivers/platform/built-in.a
AR drivers/nvmem/built-in.a
STUBCPY drivers/firmware/efi/libstub/random.stub.o
CC drivers/hid/hid-apple.o
AR drivers/net/ethernet/xilinx/built-in.a
AR drivers/net/ethernet/xircom/built-in.a
CC drivers/gpu/drm/drm_modeset_helper.o
CC drivers/hid/hid-belkin.o
CC drivers/firmware/efi/memattr.o
AR drivers/net/ethernet/synopsys/built-in.a
AR drivers/firmware/tegra/built-in.a
CC drivers/hid/hid-cherry.o
CC drivers/firmware/dmi_scan.o
AR drivers/firmware/xilinx/built-in.a
AR drivers/net/ethernet/pensando/built-in.a
STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
CC drivers/hid/hid-chicony.o
AR drivers/cpufreq/built-in.a
CC drivers/hid/hid-cypress.o
CC drivers/gpu/drm/drm_plane_helper.o
CC drivers/hid/hid-ezkey.o
CC drivers/firmware/efi/tpm.o
STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
CC [M] drivers/gpu/drm/xe/xe_step.o
STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
CC [M] drivers/gpu/drm/xe/xe_sync.o
CC drivers/firmware/efi/memmap.o
AR drivers/net/ethernet/intel/e1000e/built-in.a
AR drivers/net/ethernet/intel/built-in.a
CC drivers/hid/hid-gyration.o
CC drivers/hid/hid-ite.o
CC drivers/hid/hid-kensington.o
CC drivers/firmware/efi/capsule.o
CC drivers/gpu/drm/drm_probe_helper.o
CC drivers/firmware/efi/esrt.o
CC drivers/gpu/drm/drm_rect.o
CC [M] drivers/gpu/drm/xe/xe_tile.o
CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o
CC drivers/hid/hid-lg.o
CC [M] drivers/gpu/drm/xe/xe_trace.o
CC [M] drivers/gpu/drm/xe/xe_trace_bo.o
CC [M] drivers/gpu/drm/xe/xe_trace_guc.o
STUBCPY drivers/firmware/efi/libstub/smbios.stub.o
CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
CC drivers/hid/hid-lgff.o
CC drivers/hid/hid-lg4ff.o
CC drivers/firmware/dmi-id.o
CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
CC drivers/gpu/drm/drm_self_refresh_helper.o
CC drivers/gpu/drm/drm_simple_kms_helper.o
STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
CC drivers/gpu/drm/i915/gt/sysfs_engines.o
AR drivers/firmware/efi/libstub/lib.a
CC drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
CC drivers/firmware/efi/runtime-wrappers.o
CC drivers/hid/hid-lg-g15.o
CC drivers/firmware/efi/capsule-loader.o
CC drivers/hid/hid-microsoft.o
CC drivers/hid/hid-monterey.o
CC drivers/hid/hid-ntrig.o
CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
CC drivers/gpu/drm/bridge/panel.o
CC drivers/firmware/memmap.o
CC drivers/hid/hid-pl.o
CC drivers/gpu/drm/drm_mipi_dsi.o
CC drivers/hid/hid-petalynx.o
CC [M] drivers/gpu/drm/drm_exec.o
CC drivers/gpu/drm/i915/gt/gen6_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_tuning.o
CC drivers/firmware/efi/earlycon.o
CC drivers/hid/hid-redragon.o
CC [M] drivers/gpu/drm/drm_gpuvm.o
CC drivers/hid/hid-samsung.o
CC drivers/hid/hid-sony.o
CC drivers/hid/hid-sunplus.o
CC [M] drivers/gpu/drm/drm_suballoc.o
CC [M] drivers/gpu/drm/xe/xe_uc.o
CC drivers/hid/hid-topseed.o
CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o
CC [M] drivers/gpu/drm/xe/xe_uc_fw.o
CC [M] drivers/gpu/drm/xe/xe_vm.o
CC [M] drivers/gpu/drm/xe/xe_vram.o
CC [M] drivers/gpu/drm/xe/xe_vram_freq.o
CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o
CC [M] drivers/gpu/drm/xe/xe_wa.o
CC [M] drivers/gpu/drm/xe/xe_wopcm.o
CC drivers/gpu/drm/i915/gt/gen7_renderstate.o
CC drivers/gpu/drm/i915/gt/gen8_renderstate.o
AR drivers/md/built-in.a
CC drivers/gpu/drm/i915/gt/gen9_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_hmm.o
CC [M] drivers/gpu/drm/xe/xe_hwmon.o
AR drivers/net/ethernet/realtek/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf.o
AR drivers/net/ethernet/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_relay.o
CC [M] drivers/gpu/drm/xe/xe_memirq.o
CC [M] drivers/gpu/drm/xe/xe_sriov.o
AR drivers/net/built-in.a
CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_utils.o
CC drivers/gpu/drm/i915/gem/i915_gem_busy.o
CC [M] drivers/gpu/drm/xe/display/intel_fb_bo.o
CC drivers/gpu/drm/i915/gem/i915_gem_clflush.o
CC [M] drivers/gpu/drm/xe/display/intel_fbdev_fb.o
CC [M] drivers/gpu/drm/xe/display/xe_display.o
CC [M] drivers/gpu/drm/xe/display/xe_display_misc.o
CC drivers/gpu/drm/i915/gem/i915_gem_context.o
CC drivers/gpu/drm/i915/gem/i915_gem_create.o
LD [M] drivers/gpu/drm/drm_suballoc_helper.o
CC drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o
CC drivers/gpu/drm/i915/gem/i915_gem_domain.o
CC drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
CC [M] drivers/gpu/drm/xe/display/xe_display_wa.o
CC [M] drivers/gpu/drm/xe/display/xe_dsb_buffer.o
CC drivers/gpu/drm/i915/gem/i915_gem_internal.o
CC drivers/gpu/drm/i915/gem/i915_gem_lmem.o
CC drivers/gpu/drm/i915/gem/i915_gem_mman.o
AR drivers/firmware/efi/built-in.a
CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o
CC drivers/gpu/drm/i915/gem/i915_gem_object.o
CC drivers/gpu/drm/i915/gem/i915_gem_pages.o
CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
AR drivers/firmware/built-in.a
CC drivers/gpu/drm/i915/gem/i915_gem_phys.o
CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o
LD [M] drivers/gpu/drm/drm_ttm_helper.o
CC drivers/gpu/drm/i915/gem/i915_gem_pm.o
CC [M] drivers/gpu/drm/xe/display/xe_tdf.o
CC drivers/gpu/drm/i915/gem/i915_gem_region.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_dram.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_pch.o
CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o
CC drivers/gpu/drm/i915/gem/i915_gem_shmem.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_alpm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o
AR drivers/hid/built-in.a
CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o
CC drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o
CC drivers/gpu/drm/i915/gem/i915_gem_stolen.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o
CC drivers/gpu/drm/i915/gem/i915_gem_throttle.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_device.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_driver.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_params.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o
CC drivers/gpu/drm/i915/gem/i915_gem_tiling.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o
CC drivers/gpu/drm/i915/gem/i915_gem_userptr.o
CC drivers/gpu/drm/i915/gem/i915_gem_wait.o
CC drivers/gpu/drm/i915/gem/i915_gemfs.o
CC drivers/gpu/drm/i915/i915_active.o
CC drivers/gpu/drm/i915/i915_cmd_parser.o
CC drivers/gpu/drm/i915/i915_deps.o
CC drivers/gpu/drm/i915/i915_gem.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_wa.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o
CC drivers/gpu/drm/i915/i915_gem_evict.o
CC drivers/gpu/drm/i915/i915_gem_gtt.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o
CC drivers/gpu/drm/i915/i915_gem_ww.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt_common.o
CC drivers/gpu/drm/i915/i915_query.o
CC drivers/gpu/drm/i915/i915_request.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o
CC drivers/gpu/drm/i915/i915_scheduler.o
CC drivers/gpu/drm/i915/i915_trace_points.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_encoder.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o
CC drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o
CC drivers/gpu/drm/i915/i915_vma.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o
CC drivers/gpu/drm/i915/i915_vma_resource.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp_gsc_message.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_link_bw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pmdemand.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc_wl.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o
CC [M] drivers/gpu/drm/xe/xe_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_stats.o
CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
CC drivers/gpu/drm/i915/gt/intel_gsc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o
CC drivers/gpu/drm/i915/i915_hwmon.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs_params.o
CC drivers/gpu/drm/i915/display/hsw_ips.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o
CC drivers/gpu/drm/i915/display/i9xx_plane.o
CC drivers/gpu/drm/i915/display/i9xx_wm.o
CC drivers/gpu/drm/i915/display/intel_alpm.o
CC drivers/gpu/drm/i915/display/intel_atomic.o
CC drivers/gpu/drm/i915/display/intel_atomic_plane.o
CC drivers/gpu/drm/i915/display/intel_audio.o
CC drivers/gpu/drm/i915/display/intel_bios.o
CC drivers/gpu/drm/i915/display/intel_bw.o
CC drivers/gpu/drm/i915/display/intel_cdclk.o
CC drivers/gpu/drm/i915/display/intel_color.o
CC drivers/gpu/drm/i915/display/intel_combo_phy.o
CC drivers/gpu/drm/i915/display/intel_connector.o
CC drivers/gpu/drm/i915/display/intel_crtc.o
CC drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
CC drivers/gpu/drm/i915/display/intel_cursor.o
CC drivers/gpu/drm/i915/display/intel_display.o
CC drivers/gpu/drm/i915/display/intel_display_driver.o
CC drivers/gpu/drm/i915/display/intel_display_irq.o
CC drivers/gpu/drm/i915/display/intel_display_params.o
CC drivers/gpu/drm/i915/display/intel_display_power.o
CC drivers/gpu/drm/i915/display/intel_display_power_map.o
CC drivers/gpu/drm/i915/display/intel_display_power_well.o
CC drivers/gpu/drm/i915/display/intel_display_reset.o
CC drivers/gpu/drm/i915/display/intel_display_rps.o
CC drivers/gpu/drm/i915/display/intel_display_wa.o
CC drivers/gpu/drm/i915/display/intel_dmc.o
CC drivers/gpu/drm/i915/display/intel_dmc_wl.o
CC drivers/gpu/drm/i915/display/intel_dpio_phy.o
CC drivers/gpu/drm/i915/display/intel_dpll.o
CC drivers/gpu/drm/i915/display/intel_dpll_mgr.o
CC drivers/gpu/drm/i915/display/intel_dpt.o
CC drivers/gpu/drm/i915/display/intel_dpt_common.o
CC drivers/gpu/drm/i915/display/intel_drrs.o
CC drivers/gpu/drm/i915/display/intel_dsb.o
CC drivers/gpu/drm/i915/display/intel_dsb_buffer.o
CC drivers/gpu/drm/i915/display/intel_fb.o
CC drivers/gpu/drm/i915/display/intel_fb_bo.o
CC drivers/gpu/drm/i915/display/intel_fb_pin.o
CC drivers/gpu/drm/i915/display/intel_fbc.o
CC drivers/gpu/drm/i915/display/intel_fdi.o
CC drivers/gpu/drm/i915/display/intel_fifo_underrun.o
CC drivers/gpu/drm/i915/display/intel_frontbuffer.o
CC drivers/gpu/drm/i915/display/intel_global_state.o
CC drivers/gpu/drm/i915/display/intel_hdcp.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.o
CC drivers/gpu/drm/i915/display/intel_hotplug.o
CC drivers/gpu/drm/i915/display/intel_hotplug_irq.o
CC drivers/gpu/drm/i915/display/intel_hti.o
CC drivers/gpu/drm/i915/display/intel_link_bw.o
CC drivers/gpu/drm/i915/display/intel_load_detect.o
CC drivers/gpu/drm/i915/display/intel_lpe_audio.o
CC drivers/gpu/drm/i915/display/intel_modeset_lock.o
CC drivers/gpu/drm/i915/display/intel_modeset_setup.o
CC drivers/gpu/drm/i915/display/intel_modeset_verify.o
CC drivers/gpu/drm/i915/display/intel_overlay.o
CC drivers/gpu/drm/i915/display/intel_pch_display.o
CC drivers/gpu/drm/i915/display/intel_pch_refclk.o
CC drivers/gpu/drm/i915/display/intel_plane_initial.o
CC drivers/gpu/drm/i915/display/intel_pmdemand.o
CC drivers/gpu/drm/i915/display/intel_psr.o
CC drivers/gpu/drm/i915/display/intel_quirks.o
CC drivers/gpu/drm/i915/display/intel_sprite.o
CC drivers/gpu/drm/i915/display/intel_sprite_uapi.o
CC drivers/gpu/drm/i915/display/intel_tc.o
CC drivers/gpu/drm/i915/display/intel_vblank.o
CC drivers/gpu/drm/i915/display/intel_vga.o
CC drivers/gpu/drm/i915/display/intel_wm.o
CC drivers/gpu/drm/i915/display/skl_scaler.o
CC drivers/gpu/drm/i915/display/skl_universal_plane.o
CC drivers/gpu/drm/i915/display/skl_watermark.o
CC drivers/gpu/drm/i915/display/intel_acpi.o
CC drivers/gpu/drm/i915/display/intel_opregion.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs_params.o
CC drivers/gpu/drm/i915/display/intel_pipe_crc.o
CC drivers/gpu/drm/i915/display/dvo_ch7017.o
LD [M] drivers/gpu/drm/xe/xe.o
CC drivers/gpu/drm/i915/display/dvo_ch7xxx.o
CC drivers/gpu/drm/i915/display/dvo_ivch.o
CC drivers/gpu/drm/i915/display/dvo_ns2501.o
CC drivers/gpu/drm/i915/display/dvo_sil164.o
CC drivers/gpu/drm/i915/display/dvo_tfp410.o
CC drivers/gpu/drm/i915/display/g4x_dp.o
CC drivers/gpu/drm/i915/display/g4x_hdmi.o
CC drivers/gpu/drm/i915/display/icl_dsi.o
CC drivers/gpu/drm/i915/display/intel_backlight.o
CC drivers/gpu/drm/i915/display/intel_crt.o
CC drivers/gpu/drm/i915/display/intel_cx0_phy.o
CC drivers/gpu/drm/i915/display/intel_ddi.o
CC drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
CC drivers/gpu/drm/i915/display/intel_display_device.o
CC drivers/gpu/drm/i915/display/intel_display_trace.o
CC drivers/gpu/drm/i915/display/intel_dkl_phy.o
CC drivers/gpu/drm/i915/display/intel_dp.o
CC drivers/gpu/drm/i915/display/intel_dp_aux.o
CC drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
CC drivers/gpu/drm/i915/display/intel_dp_hdcp.o
CC drivers/gpu/drm/i915/display/intel_dp_link_training.o
CC drivers/gpu/drm/i915/display/intel_dp_mst.o
CC drivers/gpu/drm/i915/display/intel_dsi.o
CC drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
CC drivers/gpu/drm/i915/display/intel_dsi_vbt.o
CC drivers/gpu/drm/i915/display/intel_dvo.o
CC drivers/gpu/drm/i915/display/intel_encoder.o
CC drivers/gpu/drm/i915/display/intel_gmbus.o
CC drivers/gpu/drm/i915/display/intel_hdmi.o
CC drivers/gpu/drm/i915/display/intel_lspcon.o
CC drivers/gpu/drm/i915/display/intel_lvds.o
CC drivers/gpu/drm/i915/display/intel_panel.o
CC drivers/gpu/drm/i915/display/intel_pps.o
CC drivers/gpu/drm/i915/display/intel_qp_tables.o
CC drivers/gpu/drm/i915/display/intel_sdvo.o
CC drivers/gpu/drm/i915/display/intel_snps_phy.o
CC drivers/gpu/drm/i915/display/intel_tv.o
CC drivers/gpu/drm/i915/display/intel_vdsc.o
CC drivers/gpu/drm/i915/display/intel_vrr.o
CC drivers/gpu/drm/i915/display/vlv_dsi.o
CC drivers/gpu/drm/i915/display/vlv_dsi_pll.o
CC drivers/gpu/drm/i915/i915_perf.o
CC drivers/gpu/drm/i915/pxp/intel_pxp.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
CC drivers/gpu/drm/i915/i915_gpu_error.o
CC drivers/gpu/drm/i915/i915_vgpu.o
AR drivers/gpu/drm/i915/built-in.a
AR drivers/gpu/drm/built-in.a
AR drivers/gpu/built-in.a
AR drivers/built-in.a
AR built-in.a
AR vmlinux.a
LD vmlinux.o
OBJCOPY modules.builtin.modinfo
GEN modules.builtin
MODPOST Module.symvers
CC .vmlinux.export.o
CC [M] fs/efivarfs/efivarfs.mod.o
CC [M] drivers/gpu/drm/drm_exec.mod.o
CC [M] drivers/gpu/drm/drm_gpuvm.mod.o
CC [M] drivers/gpu/drm/drm_suballoc_helper.mod.o
CC [M] drivers/gpu/drm/drm_ttm_helper.mod.o
CC [M] drivers/gpu/drm/scheduler/gpu-sched.mod.o
CC [M] drivers/gpu/drm/xe/xe.mod.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.mod.o
CC [M] sound/core/snd-hwdep.mod.o
CC [M] sound/core/snd-pcm.mod.o
CC [M] sound/pci/hda/snd-hda-codec.mod.o
CC [M] sound/pci/hda/snd-hda-codec-hdmi.mod.o
CC [M] sound/pci/hda/snd-hda-intel.mod.o
CC [M] sound/hda/snd-hda-core.mod.o
CC [M] sound/hda/snd-intel-dspcfg.mod.o
CC [M] sound/hda/snd-intel-sdw-acpi.mod.o
CC [M] net/netfilter/nf_log_syslog.mod.o
CC [M] net/netfilter/xt_mark.mod.o
CC [M] net/netfilter/xt_nat.mod.o
CC [M] net/netfilter/xt_LOG.mod.o
CC [M] net/netfilter/xt_MASQUERADE.mod.o
CC [M] net/netfilter/xt_addrtype.mod.o
CC [M] net/ipv4/netfilter/iptable_nat.mod.o
LD [M] fs/efivarfs/efivarfs.ko
LD [M] net/netfilter/xt_mark.ko
LD [M] net/netfilter/nf_log_syslog.ko
LD [M] drivers/gpu/drm/drm_suballoc_helper.ko
LD [M] sound/core/snd-hwdep.ko
LD [M] sound/hda/snd-intel-dspcfg.ko
LD [M] net/netfilter/xt_nat.ko
LD [M] sound/pci/hda/snd-hda-intel.ko
LD [M] drivers/thermal/intel/x86_pkg_temp_thermal.ko
LD [M] net/netfilter/xt_LOG.ko
LD [M] sound/core/snd-pcm.ko
LD [M] sound/hda/snd-intel-sdw-acpi.ko
LD [M] sound/hda/snd-hda-core.ko
LD [M] net/netfilter/xt_MASQUERADE.ko
LD [M] sound/pci/hda/snd-hda-codec-hdmi.ko
LD [M] drivers/gpu/drm/drm_gpuvm.ko
LD [M] drivers/gpu/drm/drm_exec.ko
LD [M] drivers/gpu/drm/xe/xe.ko
LD [M] net/ipv4/netfilter/iptable_nat.ko
LD [M] drivers/gpu/drm/drm_ttm_helper.ko
LD [M] drivers/gpu/drm/scheduler/gpu-sched.ko
LD [M] sound/pci/hda/snd-hda-codec.ko
LD [M] net/netfilter/xt_addrtype.ko
UPD include/generated/utsversion.h
CC init/version-timestamp.o
KSYMS .tmp_vmlinux0.kallsyms.S
AS .tmp_vmlinux0.kallsyms.o
LD .tmp_vmlinux1
NM .tmp_vmlinux1.syms
KSYMS .tmp_vmlinux1.kallsyms.S
AS .tmp_vmlinux1.kallsyms.o
LD .tmp_vmlinux2
NM .tmp_vmlinux2.syms
KSYMS .tmp_vmlinux2.kallsyms.S
AS .tmp_vmlinux2.kallsyms.o
LD vmlinux
NM System.map
SORTTAB vmlinux
RELOCS arch/x86/boot/compressed/vmlinux.relocs
RSTRIP vmlinux
CC arch/x86/boot/a20.o
AS arch/x86/boot/bioscall.o
CC arch/x86/boot/cmdline.o
AS arch/x86/boot/copy.o
HOSTCC arch/x86/boot/mkcpustr
CC arch/x86/boot/cpuflags.o
CC arch/x86/boot/cpucheck.o
CC arch/x86/boot/early_serial_console.o
CC arch/x86/boot/edd.o
CC arch/x86/boot/main.o
CC arch/x86/boot/memory.o
CC arch/x86/boot/pm.o
AS arch/x86/boot/pmjump.o
CC arch/x86/boot/printf.o
CC arch/x86/boot/regs.o
CC arch/x86/boot/string.o
CC arch/x86/boot/tty.o
CC arch/x86/boot/video.o
CC arch/x86/boot/video-mode.o
CC arch/x86/boot/version.o
CC arch/x86/boot/video-vga.o
CC arch/x86/boot/video-vesa.o
CC arch/x86/boot/video-bios.o
HOSTCC arch/x86/boot/tools/build
CPUSTR arch/x86/boot/cpustr.h
CC arch/x86/boot/cpu.o
LDS arch/x86/boot/compressed/vmlinux.lds
AS arch/x86/boot/compressed/kernel_info.o
AS arch/x86/boot/compressed/head_32.o
VOFFSET arch/x86/boot/compressed/../voffset.h
CC arch/x86/boot/compressed/string.o
CC arch/x86/boot/compressed/cmdline.o
CC arch/x86/boot/compressed/error.o
OBJCOPY arch/x86/boot/compressed/vmlinux.bin
HOSTCC arch/x86/boot/compressed/mkpiggy
CC arch/x86/boot/compressed/cpuflags.o
CC arch/x86/boot/compressed/early_serial_console.o
CC arch/x86/boot/compressed/kaslr.o
CC arch/x86/boot/compressed/acpi.o
CC arch/x86/boot/compressed/efi.o
GZIP arch/x86/boot/compressed/vmlinux.bin.gz
CC arch/x86/boot/compressed/misc.o
MKPIGGY arch/x86/boot/compressed/piggy.S
AS arch/x86/boot/compressed/piggy.o
LD arch/x86/boot/compressed/vmlinux
ZOFFSET arch/x86/boot/zoffset.h
OBJCOPY arch/x86/boot/vmlinux.bin
AS arch/x86/boot/header.o
LD arch/x86/boot/setup.elf
OBJCOPY arch/x86/boot/setup.bin
BUILD arch/x86/boot/bzImage
Kernel: arch/x86/boot/bzImage is ready (#1)
run-parts: executing /workspace/ci/hooks/20-kernel-doc
+ SRC_DIR=/workspace/kernel
+ cd /workspace/kernel
+ find drivers/gpu/drm/xe/ -name '*.[ch]' -not -path 'drivers/gpu/drm/xe/display/*'
+ xargs ./scripts/kernel-doc -Werror -none include/uapi/drm/xe_drm.h
drivers/gpu/drm/xe/xe_device_types.h:147: warning: Function parameter or struct member 'adj_limit' not described in 'xe_mmio'
1 warnings as Errors
run-parts: /workspace/ci/hooks/20-kernel-doc exited with return code 123
^ permalink raw reply [flat|nested] 83+ messages in thread* ✓ CI.checksparse: success for Stop using xe_gt as a register MMIO target (rev2)
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (47 preceding siblings ...)
2024-09-07 3:31 ` ✗ CI.Hooks: failure " Patchwork
@ 2024-09-07 3:34 ` Patchwork
2024-09-07 4:22 ` ✗ CI.BAT: failure " Patchwork
2024-09-09 16:59 ` ✓ CI.FULL: success " Patchwork
50 siblings, 0 replies; 83+ messages in thread
From: Patchwork @ 2024-09-07 3:34 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
== Series Details ==
Series: Stop using xe_gt as a register MMIO target (rev2)
URL : https://patchwork.freedesktop.org/series/138168/
State : success
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a
Sparse version: 0.6.1 (Ubuntu: 0.6.1-2build1)
Fast mode used, each commit won't be checked separately.
Okay!
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 83+ messages in thread* ✗ CI.BAT: failure for Stop using xe_gt as a register MMIO target (rev2)
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (48 preceding siblings ...)
2024-09-07 3:34 ` ✓ CI.checksparse: success " Patchwork
@ 2024-09-07 4:22 ` Patchwork
2024-09-09 17:04 ` Matt Roper
2024-09-09 16:59 ` ✓ CI.FULL: success " Patchwork
50 siblings, 1 reply; 83+ messages in thread
From: Patchwork @ 2024-09-07 4:22 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1531 bytes --]
== Series Details ==
Series: Stop using xe_gt as a register MMIO target (rev2)
URL : https://patchwork.freedesktop.org/series/138168/
State : failure
== Summary ==
CI Bug Log - changes from xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a_BAT -> xe-pw-138168v2_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-138168v2_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-138168v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (8 -> 0)
------------------------------
ERROR: It appears as if the changes made in xe-pw-138168v2_BAT prevented too many machines from booting.
Missing (8): bat-bmg-1 bat-lnl-2 bat-adlp-vf bat-lnl-1 bat-dg2-oem2 bat-atsm-2 bat-bmg-2 bat-adlp-7
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_8008 -> IGT_8010
* Linux: xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a -> xe-pw-138168v2
IGT_8008: 91925eef7a79b1402b9422758311a4d693825362 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8010: 8010
xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a: 217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a
xe-pw-138168v2: 138168v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/index.html
[-- Attachment #2: Type: text/html, Size: 2117 bytes --]
^ permalink raw reply [flat|nested] 83+ messages in thread* Re: ✗ CI.BAT: failure for Stop using xe_gt as a register MMIO target (rev2)
2024-09-07 4:22 ` ✗ CI.BAT: failure " Patchwork
@ 2024-09-09 17:04 ` Matt Roper
0 siblings, 0 replies; 83+ messages in thread
From: Matt Roper @ 2024-09-09 17:04 UTC (permalink / raw)
To: intel-xe
On Sat, Sep 07, 2024 at 04:22:34AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: Stop using xe_gt as a register MMIO target (rev2)
> URL : https://patchwork.freedesktop.org/series/138168/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a_BAT -> xe-pw-138168v2_BAT
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with xe-pw-138168v2_BAT absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in xe-pw-138168v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (8 -> 0)
> ------------------------------
>
> ERROR: It appears as if the changes made in xe-pw-138168v2_BAT prevented too many machines from booting.
>
> Missing (8): bat-bmg-1 bat-lnl-2 bat-adlp-vf bat-lnl-1 bat-dg2-oem2 bat-atsm-2 bat-bmg-2 bat-adlp-7
I don't see any issues locally, and despite this error being reported,
CI.FULL still ran successfully on all of these platforms (and passed).
So this BAT report might have been a CI infrastructure glitch I guess?
Matt
>
>
> Changes
> -------
>
> No changes found
>
>
> Build changes
> -------------
>
> * IGT: IGT_8008 -> IGT_8010
> * Linux: xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a -> xe-pw-138168v2
>
> IGT_8008: 91925eef7a79b1402b9422758311a4d693825362 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> IGT_8010: 8010
> xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a: 217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a
> xe-pw-138168v2: 138168v2
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/index.html
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 83+ messages in thread
* ✓ CI.FULL: success for Stop using xe_gt as a register MMIO target (rev2)
2024-09-07 0:07 [PATCH v2 00/43] Stop using xe_gt as a register MMIO target Matt Roper
` (49 preceding siblings ...)
2024-09-07 4:22 ` ✗ CI.BAT: failure " Patchwork
@ 2024-09-09 16:59 ` Patchwork
50 siblings, 0 replies; 83+ messages in thread
From: Patchwork @ 2024-09-09 16:59 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 111598 bytes --]
== Series Details ==
Series: Stop using xe_gt as a register MMIO target (rev2)
URL : https://patchwork.freedesktop.org/series/138168/
State : success
== Summary ==
CI Bug Log - changes from xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a_full -> xe-pw-138168v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-138168v2_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_crc@cursor-random-256x256@pipe-d-dp-2:
- {shard-bmg}: [PASS][1] -> [INCOMPLETE][2] +5 other tests incomplete
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-bmg-8/igt@kms_cursor_crc@cursor-random-256x256@pipe-d-dp-2.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-bmg-4/igt@kms_cursor_crc@cursor-random-256x256@pipe-d-dp-2.html
Known issues
------------
Here are the changes found in xe-pw-138168v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_hwmon@hwmon-write:
- shard-lnl: NOTRUN -> [SKIP][3] ([Intel XE#1125])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@intel_hwmon@hwmon-write.html
* igt@kms_3d:
- shard-lnl: NOTRUN -> [SKIP][4] ([Intel XE#1465])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_3d.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][5] ([Intel XE#1201] / [Intel XE#801]) +23 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-6-4-mc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-x:
- shard-adlp: [PASS][6] -> [DMESG-WARN][7] ([Intel XE#1033]) +1 other test dmesg-warn
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-x.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-x.html
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
- shard-lnl: [PASS][8] -> [FAIL][9] ([Intel XE#1701]) +1 other test fail
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-1/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-4/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-lnl: [PASS][10] -> [FAIL][11] ([Intel XE#1426]) +1 other test fail
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition:
- shard-adlp: [PASS][12] -> [FAIL][13] ([Intel XE#1426]) +3 other tests fail
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-1/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-adlp: NOTRUN -> [SKIP][14] ([Intel XE#1124] / [Intel XE#1201]) +2 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-lnl: NOTRUN -> [SKIP][15] ([Intel XE#1407])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-lnl: [PASS][16] -> [FAIL][17] ([Intel XE#1659]) +1 other test fail
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@linear-64bpp-rotate-0:
- shard-lnl: NOTRUN -> [DMESG-WARN][18] ([Intel XE#1725])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_big_fb@linear-64bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-dg2-set2: NOTRUN -> [SKIP][19] ([Intel XE#1201] / [Intel XE#316])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: [PASS][20] -> [FAIL][21] ([Intel XE#1204])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-adlp: NOTRUN -> [FAIL][22] ([Intel XE#1874])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-adlp: NOTRUN -> [FAIL][23] ([Intel XE#1231])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-adlp: NOTRUN -> [SKIP][24] ([Intel XE#1201] / [Intel XE#316])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-lnl: NOTRUN -> [SKIP][25] ([Intel XE#1428])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-7/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#1124] / [Intel XE#1201])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-lnl: NOTRUN -> [SKIP][27] ([Intel XE#1124]) +2 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-5/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
- shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#2191]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-8/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#1201] / [Intel XE#367])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
- shard-adlp: NOTRUN -> [SKIP][30] ([Intel XE#1201] / [Intel XE#2191]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-6/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-4-displays-2560x1440p:
- shard-adlp: NOTRUN -> [SKIP][31] ([Intel XE#1201] / [Intel XE#367]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][32] ([Intel XE#1399]) +6 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-2/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][33] ([Intel XE#787]) +13 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-b-dp-4.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
- shard-adlp: NOTRUN -> [SKIP][34] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +7 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][35] ([Intel XE#1201] / [Intel XE#787]) +11 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-1.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][36] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +12 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][37] ([Intel XE#1201] / [Intel XE#1252])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-adlp: NOTRUN -> [SKIP][38] ([Intel XE#1201] / [Intel XE#1252])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][39] ([Intel XE#1201] / [Intel XE#787]) +90 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-4.html
* igt@kms_cdclk@mode-transition@pipe-a-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][41] ([Intel XE#1201] / [Intel XE#314]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_cdclk@mode-transition@pipe-a-hdmi-a-1.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][42] ([Intel XE#1201] / [Intel XE#314] / [Intel XE#455]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_color@ctm-green-to-red:
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#306])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-7/igt@kms_chamelium_color@ctm-green-to-red.html
* igt@kms_chamelium_color@ctm-max:
- shard-adlp: NOTRUN -> [SKIP][44] ([Intel XE#1201] / [Intel XE#306]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-6/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-dg2-set2: NOTRUN -> [SKIP][45] ([Intel XE#1201] / [Intel XE#373])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_frames@hdmi-aspect-ratio:
- shard-lnl: NOTRUN -> [SKIP][46] ([Intel XE#373]) +3 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-8/igt@kms_chamelium_frames@hdmi-aspect-ratio.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-adlp: NOTRUN -> [SKIP][47] ([Intel XE#1201] / [Intel XE#373]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-adlp: NOTRUN -> [SKIP][48] ([Intel XE#1201] / [Intel XE#307])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2-set2: NOTRUN -> [SKIP][49] ([Intel XE#307])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_cursor_crc@cursor-offscreen-256x85:
- shard-lnl: NOTRUN -> [SKIP][50] ([Intel XE#1424])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-5/igt@kms_cursor_crc@cursor-offscreen-256x85.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-adlp: NOTRUN -> [SKIP][51] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-lnl: NOTRUN -> [SKIP][52] ([Intel XE#1413])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-7/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-lnl: NOTRUN -> [SKIP][53] ([Intel XE#309]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#323])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-adlp: NOTRUN -> [SKIP][55] ([Intel XE#1201] / [Intel XE#309]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-lnl: NOTRUN -> [SKIP][56] ([Intel XE#599]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-5/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
- shard-lnl: NOTRUN -> [SKIP][57] ([Intel XE#1421]) +3 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-7/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-adlp: NOTRUN -> [SKIP][58] ([Intel XE#1201] / [Intel XE#310]) +3 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-4/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip@wf_vblank-ts-check@a-edp1:
- shard-lnl: [PASS][59] -> [FAIL][60] ([Intel XE#886]) +1 other test fail
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-7/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-5/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-lnl: NOTRUN -> [SKIP][61] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][62] ([Intel XE#1201] / [Intel XE#455]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][63] ([Intel XE#1401]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
- shard-adlp: NOTRUN -> [DMESG-FAIL][64] ([Intel XE#324]) +1 other test dmesg-fail
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][65] ([Intel XE#1201] / [Intel XE#651]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-pgflip-blt:
- shard-adlp: NOTRUN -> [SKIP][66] ([Intel XE#1201] / [Intel XE#651]) +6 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][67] ([Intel XE#1201] / [Intel XE#656]) +12 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
- shard-adlp: NOTRUN -> [FAIL][68] ([Intel XE#1861]) +1 other test fail
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][69] ([Intel XE#656]) +17 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][70] ([Intel XE#651]) +4 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][71] ([Intel XE#1201] / [Intel XE#653]) +2 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-adlp: NOTRUN -> [SKIP][72] ([Intel XE#1201] / [Intel XE#653]) +5 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-adlp: NOTRUN -> [SKIP][73] ([Intel XE#1201] / [Intel XE#356])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@plane-position-covered:
- shard-lnl: [PASS][74] -> [DMESG-WARN][75] ([Intel XE#324]) +5 other tests dmesg-warn
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-8/igt@kms_plane@plane-position-covered.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-4/igt@kms_plane@plane-position-covered.html
* igt@kms_plane_lowres@tiling-x@pipe-b-hdmi-a-1:
- shard-adlp: [PASS][76] -> [FAIL][77] ([Intel XE#1874]) +2 other tests fail
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-1/igt@kms_plane_lowres@tiling-x@pipe-b-hdmi-a-1.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-4/igt@kms_plane_lowres@tiling-x@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][78] ([Intel XE#498]) +2 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][79] ([Intel XE#455] / [Intel XE#498])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d-hdmi-a-6.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][80] ([Intel XE#1201] / [Intel XE#2318]) +2 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-6.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][81] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-6.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][82] ([Intel XE#1201] / [Intel XE#2318]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][83] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-adlp: NOTRUN -> [SKIP][84] ([Intel XE#1201] / [Intel XE#870])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc5-psr:
- shard-lnl: NOTRUN -> [FAIL][85] ([Intel XE#718])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-6/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_dc@dc6-dpms:
- shard-adlp: [PASS][86] -> [FAIL][87] ([Intel XE#718])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-8/igt@kms_pm_dc@dc6-dpms.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-6/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-lnl: [PASS][88] -> [FAIL][89] ([Intel XE#1430]) +1 other test fail
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-3/igt@kms_pm_dc@dc6-psr.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-2/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-adlp: NOTRUN -> [SKIP][90] ([Intel XE#1201] / [Intel XE#836])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-adlp: NOTRUN -> [SKIP][91] ([Intel XE#1201]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr@pr-basic:
- shard-lnl: NOTRUN -> [SKIP][92] ([Intel XE#1406]) +3 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-3/igt@kms_psr@pr-basic.html
* igt@kms_psr@psr-basic:
- shard-adlp: NOTRUN -> [SKIP][93] ([Intel XE#1201] / [Intel XE#929]) +6 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-9/igt@kms_psr@psr-basic.html
* igt@kms_psr@psr2-sprite-plane-onoff:
- shard-lnl: [PASS][94] -> [FAIL][95] ([Intel XE#1649]) +3 other tests fail
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-6/igt@kms_psr@psr2-sprite-plane-onoff.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_psr@psr2-sprite-plane-onoff.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-adlp: NOTRUN -> [SKIP][96] ([Intel XE#1127] / [Intel XE#1201])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-lnl: NOTRUN -> [SKIP][97] ([Intel XE#1437]) +1 other test skip
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-adlp: NOTRUN -> [SKIP][98] ([Intel XE#1201] / [Intel XE#327])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-lnl: NOTRUN -> [SKIP][99] ([Intel XE#1435])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-8/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_vrr@flip-basic:
- shard-lnl: [PASS][100] -> [FAIL][101] ([Intel XE#2443]) +5 other tests fail
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-3/igt@kms_vrr@flip-basic.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-8/igt@kms_vrr@flip-basic.html
* igt@xe_ccs@block-copy-compressed:
- shard-adlp: NOTRUN -> [SKIP][102] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#488])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@xe_ccs@block-copy-compressed.html
* igt@xe_compute_preempt@compute-preempt:
- shard-adlp: NOTRUN -> [SKIP][103] ([Intel XE#1201] / [Intel XE#455]) +6 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-9/igt@xe_compute_preempt@compute-preempt.html
* igt@xe_compute_preempt@compute-preempt@engine-drm_xe_engine_class_compute:
- shard-dg2-set2: NOTRUN -> [SKIP][104] ([Intel XE#1280] / [Intel XE#455])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_compute_preempt@compute-preempt@engine-drm_xe_engine_class_compute.html
* igt@xe_copy_basic@mem-copy-linear-0x3fff:
- shard-adlp: NOTRUN -> [SKIP][105] ([Intel XE#1123] / [Intel XE#1201])
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@xe_copy_basic@mem-copy-linear-0x3fff.html
* igt@xe_evict@evict-beng-mixed-many-threads-large:
- shard-dg2-set2: [PASS][106] -> [TIMEOUT][107] ([Intel XE#1473]) +1 other test timeout
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-463/igt@xe_evict@evict-beng-mixed-many-threads-large.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-large.html
* igt@xe_evict@evict-beng-mixed-threads-large-multi-vm:
- shard-adlp: NOTRUN -> [SKIP][108] ([Intel XE#1201] / [Intel XE#261])
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-4/igt@xe_evict@evict-beng-mixed-threads-large-multi-vm.html
* igt@xe_evict@evict-mixed-threads-large-multi-vm:
- shard-lnl: NOTRUN -> [SKIP][109] ([Intel XE#688]) +5 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-3/igt@xe_evict@evict-mixed-threads-large-multi-vm.html
* igt@xe_evict@evict-small-external-cm:
- shard-adlp: NOTRUN -> [SKIP][110] ([Intel XE#1201] / [Intel XE#261] / [Intel XE#688]) +2 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@xe_evict@evict-small-external-cm.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind:
- shard-lnl: NOTRUN -> [SKIP][111] ([Intel XE#1392]) +2 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-5/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-rebind.html
* igt@xe_exec_basic@multigpu-once-userptr-invalidate-race:
- shard-adlp: NOTRUN -> [SKIP][112] ([Intel XE#1201] / [Intel XE#1392]) +1 other test skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@xe_exec_basic@multigpu-once-userptr-invalidate-race.html
* igt@xe_exec_basic@twice-rebind:
- shard-adlp: [PASS][113] -> [INCOMPLETE][114] ([Intel XE#1195])
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-4/igt@xe_exec_basic@twice-rebind.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-6/igt@xe_exec_basic@twice-rebind.html
* igt@xe_exec_compute_mode@twice-userptr-invalidate-race:
- shard-dg2-set2: [PASS][115] -> [FAIL][116] ([Intel XE#1069])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-466/igt@xe_exec_compute_mode@twice-userptr-invalidate-race.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@xe_exec_compute_mode@twice-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@many-basic-prefetch:
- shard-dg2-set2: NOTRUN -> [SKIP][117] ([Intel XE#1201] / [Intel XE#288]) +2 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@xe_exec_fault_mode@many-basic-prefetch.html
* igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate:
- shard-adlp: NOTRUN -> [SKIP][118] ([Intel XE#1201] / [Intel XE#288]) +10 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-4/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate.html
* igt@xe_live_ktest@xe_bo:
- shard-lnl: [PASS][119] -> [SKIP][120] ([Intel XE#1192])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-6/igt@xe_live_ktest@xe_bo.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-8/igt@xe_live_ktest@xe_bo.html
* igt@xe_module_load@force-load:
- shard-adlp: NOTRUN -> [SKIP][121] ([Intel XE#1201] / [Intel XE#378])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@xe_module_load@force-load.html
* igt@xe_oa@invalid-oa-format-id:
- shard-adlp: NOTRUN -> [SKIP][122] ([Intel XE#1201] / [Intel XE#2541]) +2 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@xe_oa@invalid-oa-format-id.html
* igt@xe_oa@oa-regs-whitelisted:
- shard-lnl: [PASS][123] -> [FAIL][124] ([Intel XE#2514]) +1 other test fail
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-8/igt@xe_oa@oa-regs-whitelisted.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-5/igt@xe_oa@oa-regs-whitelisted.html
* igt@xe_pat@pat-index-xehpc:
- shard-lnl: NOTRUN -> [SKIP][125] ([Intel XE#1420])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-7/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pm@d3cold-basic:
- shard-lnl: NOTRUN -> [SKIP][126] ([Intel XE#2284] / [Intel XE#366])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-2/igt@xe_pm@d3cold-basic.html
* igt@xe_pm@s3-basic-exec:
- shard-adlp: [PASS][127] -> [FAIL][128] ([Intel XE#2028])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-9/igt@xe_pm@s3-basic-exec.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@xe_pm@s3-basic-exec.html
* igt@xe_pm@s4-basic:
- shard-lnl: [PASS][129] -> [ABORT][130] ([Intel XE#1358] / [Intel XE#1607])
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-7/igt@xe_pm@s4-basic.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-2/igt@xe_pm@s4-basic.html
* igt@xe_query@multigpu-query-topology-l3-bank-mask:
- shard-adlp: NOTRUN -> [SKIP][131] ([Intel XE#1201] / [Intel XE#944])
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-4/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
* igt@xe_wedged@wedged-at-any-timeout:
- shard-dg2-set2: [PASS][132] -> [SKIP][133] ([Intel XE#1130] / [Intel XE#1201])
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@xe_wedged@wedged-at-any-timeout.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@xe_wedged@wedged-at-any-timeout.html
#### Possible fixes ####
* igt@core_getversion@basic:
- shard-dg2-set2: [FAIL][134] ([Intel XE#2452]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@core_getversion@basic.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@core_getversion@basic.html
* igt@core_hotunplug@unbind-rebind:
- shard-dg2-set2: [SKIP][136] ([Intel XE#1201] / [Intel XE#1885]) -> [PASS][137] +2 other tests pass
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@core_hotunplug@unbind-rebind.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@core_hotunplug@unbind-rebind.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-x:
- shard-adlp: [DMESG-WARN][138] ([Intel XE#1033]) -> [PASS][139] +1 other test pass
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-x.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-x.html
* igt@kms_atomic@plane-invalid-params-fence:
- shard-dg2-set2: [SKIP][140] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [PASS][141] +81 other tests pass
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_atomic@plane-invalid-params-fence.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_atomic@plane-invalid-params-fence.html
* igt@kms_atomic_transition@modeset-transition-nonblocking:
- shard-lnl: [FAIL][142] ([Intel XE#1701]) -> [PASS][143] +1 other test pass
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-4/igt@kms_atomic_transition@modeset-transition-nonblocking.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-5/igt@kms_atomic_transition@modeset-transition-nonblocking.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-lnl: [FAIL][144] ([Intel XE#1659]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-dg2-set2: [SKIP][146] ([Intel XE#1201]) -> [PASS][147] +20 other tests pass
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-434/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-adlp: [FAIL][148] ([Intel XE#1231]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: [FAIL][150] ([Intel XE#1204]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling:
- shard-dg2-set2: [SKIP][152] ([Intel XE#1201] / [Intel XE#2351]) -> [PASS][153] +10 other tests pass
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-3-linear-to-linear:
- {shard-bmg}: [DMESG-WARN][154] ([Intel XE#877]) -> [PASS][155] +7 other tests pass
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-bmg-4/igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-3-linear-to-linear.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-bmg-1/igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-3-linear-to-linear.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y:
- shard-adlp: [FAIL][156] ([Intel XE#1874]) -> [PASS][157] +7 other tests pass
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-6/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-4/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-adlp: [FAIL][158] ([Intel XE#1861]) -> [PASS][159] +1 other test pass
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: [SKIP][160] ([Intel XE#1201] / [Intel XE#455]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@kms_hdr@invalid-hdr.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
- {shard-bmg}: [SKIP][162] ([Intel XE#1503]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-bmg-3/igt@kms_hdr@invalid-hdr.html
* igt@kms_plane@plane-position-hole@pipe-b-plane-1:
- shard-lnl: [DMESG-WARN][164] ([Intel XE#324]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-6/igt@kms_plane@plane-position-hole@pipe-b-plane-1.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-4/igt@kms_plane@plane-position-hole@pipe-b-plane-1.html
* igt@kms_plane_lowres@tiling-4@pipe-c-dp-2:
- {shard-bmg}: [INCOMPLETE][166] -> [PASS][167] +1 other test pass
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-bmg-5/igt@kms_plane_lowres@tiling-4@pipe-c-dp-2.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-bmg-5/igt@kms_plane_lowres@tiling-4@pipe-c-dp-2.html
* igt@kms_pm_dc@dc5-dpms:
- shard-lnl: [FAIL][168] ([Intel XE#718]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-5/igt@kms_pm_dc@dc5-dpms.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-2/igt@kms_pm_dc@dc5-dpms.html
* igt@kms_pm_rpm@legacy-planes:
- shard-dg2-set2: [SKIP][170] ([Intel XE#1201] / [Intel XE#2446]) -> [PASS][171] +2 other tests pass
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_pm_rpm@legacy-planes.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_pm_rpm@legacy-planes.html
* igt@kms_pm_rpm@universal-planes:
- shard-lnl: [DMESG-WARN][172] ([Intel XE#2042]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-5/igt@kms_pm_rpm@universal-planes.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_pm_rpm@universal-planes.html
* igt@kms_pm_rpm@universal-planes@plane-32:
- shard-lnl: [DMESG-WARN][174] -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-5/igt@kms_pm_rpm@universal-planes@plane-32.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-1/igt@kms_pm_rpm@universal-planes@plane-32.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-adlp: [FAIL][176] ([Intel XE#771] / [Intel XE#899]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-6/igt@kms_universal_plane@cursor-fb-leak.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@kms_universal_plane@cursor-fb-leak.html
- {shard-bmg}: [FAIL][178] ([Intel XE#899]) -> [PASS][179] +1 other test pass
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-bmg-8/igt@kms_universal_plane@cursor-fb-leak.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-bmg-3/igt@kms_universal_plane@cursor-fb-leak.html
- shard-dg2-set2: [FAIL][180] ([Intel XE#771] / [Intel XE#899]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_universal_plane@cursor-fb-leak.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-adlp: [FAIL][182] ([Intel XE#899]) -> [PASS][183] +1 other test pass
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-6/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6:
- shard-dg2-set2: [FAIL][184] ([Intel XE#899]) -> [PASS][185] +1 other test pass
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-6.html
* igt@kms_vrr@max-min:
- shard-lnl: [FAIL][186] ([Intel XE#2443]) -> [PASS][187] +1 other test pass
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-6/igt@kms_vrr@max-min.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-6/igt@kms_vrr@max-min.html
* igt@xe_ccs@suspend-resume:
- shard-lnl: [INCOMPLETE][188] -> [PASS][189] +1 other test pass
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-7/igt@xe_ccs@suspend-resume.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-7/igt@xe_ccs@suspend-resume.html
* igt@xe_exec_balancer@twice-virtual-basic:
- shard-dg2-set2: [SKIP][190] ([Intel XE#1130] / [Intel XE#1201]) -> [PASS][191] +140 other tests pass
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_exec_balancer@twice-virtual-basic.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_exec_balancer@twice-virtual-basic.html
* igt@xe_module_load@reload:
- shard-dg2-set2: [FAIL][192] ([Intel XE#2136]) -> [PASS][193]
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_module_load@reload.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@xe_module_load@reload.html
* igt@xe_pm@s2idle-d3hot-basic-exec:
- {shard-bmg}: [INCOMPLETE][194] ([Intel XE#1616]) -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-bmg-2/igt@xe_pm@s2idle-d3hot-basic-exec.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-bmg-1/igt@xe_pm@s2idle-d3hot-basic-exec.html
- shard-dg2-set2: [INCOMPLETE][196] ([Intel XE#1195] / [Intel XE#1358]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-435/igt@xe_pm@s2idle-d3hot-basic-exec.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@xe_pm@s2idle-d3hot-basic-exec.html
* igt@xe_pm@s4-d3hot-basic-exec:
- shard-adlp: [ABORT][198] ([Intel XE#1358] / [Intel XE#1607]) -> [PASS][199]
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-9/igt@xe_pm@s4-d3hot-basic-exec.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-8/igt@xe_pm@s4-d3hot-basic-exec.html
* igt@xe_pm@s4-vm-bind-prefetch:
- shard-lnl: [ABORT][200] ([Intel XE#1607] / [Intel XE#1794]) -> [PASS][201]
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-lnl-2/igt@xe_pm@s4-vm-bind-prefetch.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-lnl-8/igt@xe_pm@s4-vm-bind-prefetch.html
#### Warnings ####
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-dg2-set2: [SKIP][202] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][203] ([Intel XE#316]) +1 other test skip
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-dg2-set2: [SKIP][204] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][205] ([Intel XE#1201] / [Intel XE#316])
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-dg2-set2: [SKIP][206] ([Intel XE#316]) -> [SKIP][207] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-270.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-dg2-set2: [SKIP][208] ([Intel XE#1201]) -> [SKIP][209] ([Intel XE#316])
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_big_fb@linear-8bpp-rotate-270.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-adlp: [FAIL][210] ([Intel XE#1204]) -> [DMESG-FAIL][211] ([Intel XE#324])
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-90:
- shard-dg2-set2: [SKIP][212] ([Intel XE#1201]) -> [SKIP][213] ([Intel XE#1124] / [Intel XE#1201]) +2 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-dg2-set2: [SKIP][214] ([Intel XE#1201] / [Intel XE#619]) -> [SKIP][215] ([Intel XE#619])
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@kms_big_fb@y-tiled-addfb.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-adlp: [FAIL][216] ([Intel XE#1231]) -> [DMESG-FAIL][217] ([Intel XE#324])
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180:
- shard-dg2-set2: [SKIP][218] ([Intel XE#1201]) -> [SKIP][219] ([Intel XE#1124])
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-adlp: [DMESG-FAIL][220] ([Intel XE#324]) -> [FAIL][221] ([Intel XE#1231])
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-adlp-9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-dg2-set2: [SKIP][222] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][223] ([Intel XE#1124] / [Intel XE#1201]) +3 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-dg2-set2: [SKIP][224] ([Intel XE#1124]) -> [SKIP][225] ([Intel XE#1124] / [Intel XE#1201]) +5 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-dg2-set2: [SKIP][226] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][227] ([Intel XE#1124]) +3 other tests skip
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_joiner@basic:
- shard-dg2-set2: [SKIP][228] ([Intel XE#1201]) -> [SKIP][229] ([Intel XE#1201] / [Intel XE#346])
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_big_joiner@basic.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-434/igt@kms_big_joiner@basic.html
* igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p:
- shard-dg2-set2: [SKIP][230] ([Intel XE#367]) -> [SKIP][231] ([Intel XE#1201] / [Intel XE#367]) +2 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html
* igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
- shard-dg2-set2: [SKIP][232] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][233] ([Intel XE#1201] / [Intel XE#2191])
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
- shard-dg2-set2: [SKIP][234] ([Intel XE#1201] / [Intel XE#2191]) -> [SKIP][235] ([Intel XE#2191])
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-433/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-3-displays-2160x1440p:
- shard-dg2-set2: [SKIP][236] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][237] ([Intel XE#1201] / [Intel XE#367]) +3 other tests skip
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-3-displays-2560x1440p:
- shard-dg2-set2: [SKIP][238] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][239] ([Intel XE#367])
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-433/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html
* igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
- shard-dg2-set2: [SKIP][240] ([Intel XE#1201]) -> [SKIP][241] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +9 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
* igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-4:
- shard-dg2-set2: [SKIP][242] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][243] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +17 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-4.html
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-4.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
- shard-dg2-set2: [SKIP][244] ([Intel XE#1201] / [Intel XE#1252]) -> [SKIP][245] ([Intel XE#1252])
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-466/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc:
- shard-dg2-set2: [SKIP][246] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][247] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +2 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc.html
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-c-dp-4:
- shard-dg2-set2: [SKIP][248] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][249] ([Intel XE#787]) +41 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-435/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-c-dp-4.html
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-c-dp-4.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
- shard-dg2-set2: [SKIP][250] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][251] ([Intel XE#455] / [Intel XE#787]) +11 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-435/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html
* igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4:
- shard-dg2-set2: [SKIP][252] ([Intel XE#787]) -> [SKIP][253] ([Intel XE#1201] / [Intel XE#787]) +62 other tests skip
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-dg2-set2: [SKIP][254] ([Intel XE#1201]) -> [SKIP][255] ([Intel XE#1201] / [Intel XE#1252])
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs:
- shard-dg2-set2: [SKIP][256] ([Intel XE#1201]) -> [SKIP][257] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
* igt@kms_chamelium_color@ctm-max:
- shard-dg2-set2: [SKIP][258] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][259] ([Intel XE#1201] / [Intel XE#306])
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_chamelium_color@ctm-max.html
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-434/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-dg2-set2: [SKIP][260] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][261] ([Intel XE#306]) +1 other test skip
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_chamelium_color@ctm-red-to-blue.html
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_color@degamma:
- shard-dg2-set2: [SKIP][262] ([Intel XE#306]) -> [SKIP][263] ([Intel XE#1201] / [Intel XE#306]) +1 other test skip
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_chamelium_color@degamma.html
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
- shard-dg2-set2: [SKIP][264] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][265] ([Intel XE#1201] / [Intel XE#373]) +5 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-dg2-set2: [SKIP][266] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][267] ([Intel XE#373]) +1 other test skip
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
- shard-dg2-set2: [SKIP][268] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][269] ([Intel XE#373]) +5 other tests skip
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-435/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-dg2-set2: [SKIP][270] ([Intel XE#373]) -> [SKIP][271] ([Intel XE#1201] / [Intel XE#373]) +5 other tests skip
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-434/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2-set2: [SKIP][272] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][273] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_cursor_crc@cursor-onscreen-512x170.html
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-dg2-set2: [SKIP][274] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][275] ([Intel XE#1201] / [Intel XE#455]) +8 other tests skip
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_cursor_crc@cursor-random-max-size.html
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-434/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg2-set2: [SKIP][276] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][277] ([Intel XE#308])
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@kms_cursor_crc@cursor-sliding-512x512.html
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2-set2: [SKIP][278] ([Intel XE#1201] / [Intel XE#323]) -> [SKIP][279] ([Intel XE#323]) +1 other test skip
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-435/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2-set2: [SKIP][280] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][281] ([Intel XE#1201] / [Intel XE#323])
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6:
- shard-dg2-set2: [SKIP][282] ([i915#3804]) -> [SKIP][283] ([Intel XE#1201] / [i915#3804])
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-6.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg2-set2: [SKIP][284] ([Intel XE#1201]) -> [SKIP][285] ([Intel XE#1201] / [Intel XE#455]) +1 other test skip
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_dsc@dsc-with-bpc.html
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-434/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-dg2-set2: [SKIP][286] ([Intel XE#1201]) -> [SKIP][287] ([Intel XE#455])
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_dsc@dsc-with-output-formats.html
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-dg2-set2: [SKIP][288] ([Intel XE#776]) -> [SKIP][289] ([Intel XE#1201] / [Intel XE#776])
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_fbcon_fbt@psr-suspend.html
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2-set2: [SKIP][290] ([Intel XE#1201] / [Intel XE#701]) -> [SKIP][291] ([Intel XE#701])
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-466/igt@kms_feature_discovery@chamelium.html
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2-set2: [SKIP][292] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][293] ([Intel XE#1201] / [Intel XE#703])
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_feature_discovery@display-3x.html
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@psr2:
- shard-dg2-set2: [SKIP][294] ([Intel XE#1135] / [Intel XE#1201]) -> [SKIP][295] ([Intel XE#1135])
[294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-463/igt@kms_feature_discovery@psr2.html
[295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_feature_discovery@psr2.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-dg2-set2: [SKIP][296] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][297] ([Intel XE#455]) +5 other tests skip
[296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
[297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-dg2-set2: [SKIP][298] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][299] ([Intel XE#1201] / [Intel XE#455])
[298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
[299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-wc:
- shard-dg2-set2: [SKIP][300] ([Intel XE#1201]) -> [SKIP][301] ([Intel XE#651])
[300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-wc.html
[301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][302] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][303] ([Intel XE#651]) +18 other tests skip
[302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html
[303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@drrs-suspend:
- shard-dg2-set2: [SKIP][304] ([Intel XE#651]) -> [SKIP][305] ([Intel XE#1201] / [Intel XE#651]) +18 other tests skip
[304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-suspend.html
[305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-suspend.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
- shard-dg2-set2: [SKIP][306] ([Intel XE#1201]) -> [SKIP][307] ([Intel XE#1201] / [Intel XE#651]) +22 other tests skip
[306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
[307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff:
- shard-dg2-set2: [SKIP][308] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][309] ([Intel XE#1201] / [Intel XE#651]) +5 other tests skip
[308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff.html
[309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][310] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][311] ([Intel XE#651])
[310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff.html
[311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2-set2: [SKIP][312] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][313] ([Intel XE#653]) +15 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
[313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move:
- shard-dg2-set2: [SKIP][314] ([Intel XE#653]) -> [SKIP][315] ([Intel XE#1201] / [Intel XE#653]) +15 other tests skip
[314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html
[315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
- shard-dg2-set2: [SKIP][316] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][317] ([Intel XE#653]) +2 other tests skip
[316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html
[317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2-set2: [SKIP][318] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][319] ([Intel XE#1201] / [Intel XE#653]) +7 other tests skip
[318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
[319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt:
- shard-dg2-set2: [SKIP][320] ([Intel XE#1201]) -> [SKIP][321] ([Intel XE#1201] / [Intel XE#653]) +18 other tests skip
[320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
[321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2-set2: [SKIP][322] ([Intel XE#1201] / [Intel XE#605]) -> [SKIP][323] ([Intel XE#605])
[322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_getfb@getfb-reject-ccs.html
[323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
- shard-dg2-set2: [SKIP][324] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][325] ([Intel XE#455] / [Intel XE#498])
[324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html
[325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-dg2-set2: [SKIP][326] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][327] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455])
[326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
[327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling:
- shard-dg2-set2: [SKIP][328] ([Intel XE#1201] / [Intel XE#2318] / [Intel XE#455]) -> [SKIP][329] ([Intel XE#2318] / [Intel XE#455]) +1 other test skip
[328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html
[329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6:
- shard-dg2-set2: [SKIP][330] ([Intel XE#1201] / [Intel XE#2318]) -> [SKIP][331] ([Intel XE#2318]) +2 other tests skip
[330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6.html
[331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a-hdmi-a-6.html
* igt@kms_pm_backlight@fade:
- shard-dg2-set2: [SKIP][332] ([Intel XE#1201] / [Intel XE#870]) -> [SKIP][333] ([Intel XE#870])
[332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@kms_pm_backlight@fade.html
[333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_pm_backlight@fade.html
* igt@kms_pm_backlight@fade-with-suspend:
- shard-dg2-set2: [SKIP][334] ([Intel XE#1201]) -> [SKIP][335] ([Intel XE#1201] / [Intel XE#870]) +1 other test skip
[334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_pm_backlight@fade-with-suspend.html
[335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_pm_backlight@fade-with-suspend.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-dg2-set2: [SKIP][336] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][337] ([Intel XE#1122] / [Intel XE#1201])
[336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_pm_dc@dc3co-vpb-simulation.html
[337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area:
- shard-dg2-set2: [SKIP][338] ([Intel XE#1201]) -> [SKIP][339] ([Intel XE#1201] / [Intel XE#1489]) +2 other tests skip
[338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area.html
[339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-dg2-set2: [SKIP][340] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][341] ([Intel XE#1201] / [Intel XE#1489])
[340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
[341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-dg2-set2: [SKIP][342] ([Intel XE#1489]) -> [SKIP][343] ([Intel XE#1201] / [Intel XE#1489]) +2 other tests skip
[342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-dg2-set2: [SKIP][344] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][345] ([Intel XE#1489]) +1 other test skip
[344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-466/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@fbc-pr-cursor-plane-move:
- shard-dg2-set2: [SKIP][346] ([Intel XE#1201]) -> [SKIP][347] ([Intel XE#1201] / [Intel XE#929]) +7 other tests skip
[346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_psr@fbc-pr-cursor-plane-move.html
[347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@kms_psr@fbc-pr-cursor-plane-move.html
* igt@kms_psr@fbc-pr-dpms:
- shard-dg2-set2: [SKIP][348] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][349] ([Intel XE#929]) +4 other tests skip
[348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@kms_psr@fbc-pr-dpms.html
[349]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_psr@fbc-pr-dpms.html
* igt@kms_psr@fbc-pr-no-drrs:
- shard-dg2-set2: [SKIP][350] ([Intel XE#1201] / [Intel XE#2351]) -> [SKIP][351] ([Intel XE#1201] / [Intel XE#929]) +1 other test skip
[350]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_psr@fbc-pr-no-drrs.html
[351]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_psr@fbc-pr-no-drrs.html
* igt@kms_psr@fbc-psr2-sprite-plane-move:
- shard-dg2-set2: [SKIP][352] ([Intel XE#1201]) -> [SKIP][353] ([Intel XE#929]) +3 other tests skip
[352]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_psr@fbc-psr2-sprite-plane-move.html
[353]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_psr@fbc-psr2-sprite-plane-move.html
* igt@kms_psr@pr-sprite-blt:
- shard-dg2-set2: [SKIP][354] ([Intel XE#929]) -> [SKIP][355] ([Intel XE#1201] / [Intel XE#929]) +9 other tests skip
[354]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_psr@pr-sprite-blt.html
[355]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_psr@pr-sprite-blt.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-dg2-set2: [SKIP][356] ([Intel XE#327]) -> [SKIP][357] ([Intel XE#1201] / [Intel XE#327]) +1 other test skip
[356]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_rotation_crc@bad-pixel-format.html
[357]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-dg2-set2: [SKIP][358] ([Intel XE#1127] / [Intel XE#1201]) -> [SKIP][359] ([Intel XE#1127])
[358]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-433/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
[359]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-dg2-set2: [SKIP][360] ([Intel XE#1127]) -> [SKIP][361] ([Intel XE#1127] / [Intel XE#1201])
[360]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
[361]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-dg2-set2: [SKIP][362] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][363] ([Intel XE#1201] / [Intel XE#327]) +1 other test skip
[362]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
[363]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2-set2: [SKIP][364] ([Intel XE#1201] / [Intel XE#362]) -> [FAIL][365] ([Intel XE#1729])
[364]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
[365]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][366] ([Intel XE#1201] / [Intel XE#1500]) -> [SKIP][367] ([Intel XE#1201] / [Intel XE#362])
[366]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[367]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@flip-dpms:
- shard-dg2-set2: [SKIP][368] ([Intel XE#455]) -> [SKIP][369] ([Intel XE#1201] / [Intel XE#455]) +7 other tests skip
[368]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@kms_vrr@flip-dpms.html
[369]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-434/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg2-set2: [SKIP][370] ([Intel XE#1201] / [Intel XE#2423] / [i915#2575]) -> [SKIP][371] ([Intel XE#1201] / [Intel XE#756])
[370]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
[371]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg2-set2: [SKIP][372] ([Intel XE#1201] / [Intel XE#756]) -> [SKIP][373] ([Intel XE#756])
[372]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@kms_writeback@writeback-invalid-parameters.html
[373]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@kms_writeback@writeback-invalid-parameters.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-dg2-set2: [SKIP][374] ([Intel XE#1091] / [Intel XE#1201]) -> [SKIP][375] ([Intel XE#1091])
[374]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-435/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
[375]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
* igt@xe_compute_preempt@compute-preempt:
- shard-dg2-set2: [SKIP][376] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][377] ([Intel XE#1280] / [Intel XE#455])
[376]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_compute_preempt@compute-preempt.html
[377]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_compute_preempt@compute-preempt.html
* igt@xe_copy_basic@mem-set-linear-0xfd:
- shard-dg2-set2: [SKIP][378] ([Intel XE#1126]) -> [SKIP][379] ([Intel XE#1126] / [Intel XE#1201])
[378]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@xe_copy_basic@mem-set-linear-0xfd.html
[379]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@xe_copy_basic@mem-set-linear-0xfd.html
* igt@xe_evict@evict-large-multi-vm-cm:
- shard-dg2-set2: [SKIP][380] ([Intel XE#1130] / [Intel XE#1201]) -> [FAIL][381] ([Intel XE#1600])
[380]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_evict@evict-large-multi-vm-cm.html
[381]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_evict@evict-large-multi-vm-cm.html
* igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-imm:
- shard-dg2-set2: [SKIP][382] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][383] ([Intel XE#288]) +4 other tests skip
[382]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-imm.html
[383]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-rebind-imm.html
* igt@xe_exec_fault_mode@many-execqueues-userptr-imm:
- shard-dg2-set2: [SKIP][384] ([Intel XE#288]) -> [SKIP][385] ([Intel XE#1201] / [Intel XE#288]) +15 other tests skip
[384]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@xe_exec_fault_mode@many-execqueues-userptr-imm.html
[385]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@xe_exec_fault_mode@many-execqueues-userptr-imm.html
* igt@xe_exec_fault_mode@once-invalid-userptr-fault:
- shard-dg2-set2: [SKIP][386] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][387] ([Intel XE#288]) +11 other tests skip
[386]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-435/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html
[387]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html
* igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch:
- shard-dg2-set2: [SKIP][388] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][389] ([Intel XE#1201] / [Intel XE#288]) +18 other tests skip
[388]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html
[389]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html
* igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
- shard-dg2-set2: [SKIP][390] ([Intel XE#2360]) -> [SKIP][391] ([Intel XE#1201] / [Intel XE#2360])
[390]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html
[391]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html
* igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
- shard-dg2-set2: [SKIP][392] ([Intel XE#1201] / [Intel XE#2360]) -> [SKIP][393] ([Intel XE#2360])
[392]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-435/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
[393]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
* igt@xe_oa@invalid-oa-metric-set-id:
- shard-dg2-set2: [SKIP][394] ([Intel XE#1201] / [Intel XE#2541]) -> [SKIP][395] ([Intel XE#2541]) +2 other tests skip
[394]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_oa@invalid-oa-metric-set-id.html
[395]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_oa@invalid-oa-metric-set-id.html
* igt@xe_oa@mi-rpc:
- shard-dg2-set2: [SKIP][396] ([Intel XE#2541]) -> [SKIP][397] ([Intel XE#1201] / [Intel XE#2541]) +2 other tests skip
[396]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@xe_oa@mi-rpc.html
[397]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-466/igt@xe_oa@mi-rpc.html
* igt@xe_oa@non-privileged-map-oa-buffer:
- shard-dg2-set2: [SKIP][398] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][399] ([Intel XE#1201] / [Intel XE#2541]) +3 other tests skip
[398]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_oa@non-privileged-map-oa-buffer.html
[399]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-433/igt@xe_oa@non-privileged-map-oa-buffer.html
* igt@xe_oa@oa-regs-whitelisted:
- shard-dg2-set2: [SKIP][400] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][401] ([Intel XE#2541]) +1 other test skip
[400]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_oa@oa-regs-whitelisted.html
[401]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_oa@oa-regs-whitelisted.html
* igt@xe_pat@pat-index-xe2:
- shard-dg2-set2: [SKIP][402] ([Intel XE#1201] / [Intel XE#977]) -> [SKIP][403] ([Intel XE#977])
[402]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-466/igt@xe_pat@pat-index-xe2.html
[403]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_pat@pat-index-xe2.html
* igt@xe_pat@pat-index-xehpc:
- shard-dg2-set2: [SKIP][404] ([Intel XE#1201] / [Intel XE#979]) -> [SKIP][405] ([Intel XE#979])
[404]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-434/igt@xe_pat@pat-index-xehpc.html
[405]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pm@d3cold-basic:
- shard-dg2-set2: [SKIP][406] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][407] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366])
[406]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@xe_pm@d3cold-basic.html
[407]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@xe_pm@d3cold-basic.html
* igt@xe_pm@d3cold-mmap-vram:
- shard-dg2-set2: [SKIP][408] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) -> [SKIP][409] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
[408]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-463/igt@xe_pm@d3cold-mmap-vram.html
[409]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_pm@d3cold-mmap-vram.html
* igt@xe_pm@d3cold-mocs:
- shard-dg2-set2: [SKIP][410] ([Intel XE#2284]) -> [SKIP][411] ([Intel XE#1201] / [Intel XE#2284])
[410]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@xe_pm@d3cold-mocs.html
[411]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-436/igt@xe_pm@d3cold-mocs.html
* igt@xe_query@multigpu-query-gt-list:
- shard-dg2-set2: [SKIP][412] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][413] ([Intel XE#944])
[412]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-466/igt@xe_query@multigpu-query-gt-list.html
[413]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-432/igt@xe_query@multigpu-query-gt-list.html
* igt@xe_query@multigpu-query-invalid-extension:
- shard-dg2-set2: [SKIP][414] ([Intel XE#944]) -> [SKIP][415] ([Intel XE#1201] / [Intel XE#944])
[414]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-432/igt@xe_query@multigpu-query-invalid-extension.html
[415]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-463/igt@xe_query@multigpu-query-invalid-extension.html
* igt@xe_query@multigpu-query-uc-fw-version-guc:
- shard-dg2-set2: [SKIP][416] ([Intel XE#1130] / [Intel XE#1201]) -> [SKIP][417] ([Intel XE#1201] / [Intel XE#944]) +2 other tests skip
[416]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a/shard-dg2-436/igt@xe_query@multigpu-query-uc-fw-version-guc.html
[417]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/shard-dg2-435/igt@xe_query@multigpu-query-uc-fw-version-guc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033
[Intel XE#1069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1069
[Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
[Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
[Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
[Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
[Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
[Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
[Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201
[Intel XE#1204]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1204
[Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
[Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252
[Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
[Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1413
[Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426
[Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
[Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1437
[Intel XE#1465]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1465
[Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600
[Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
[Intel XE#1616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1616
[Intel XE#1649]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1649
[Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659
[Intel XE#1701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1701
[Intel XE#1725]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1725
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#1861]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1861
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#1885]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1885
[Intel XE#2028]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2028
[Intel XE#2042]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2042
[Intel XE#2105]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2105
[Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2251
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2318
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
[Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
[Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
[Intel XE#2436]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2436
[Intel XE#2443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2443
[Intel XE#2446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2446
[Intel XE#2452]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2452
[Intel XE#2472]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2472
[Intel XE#2514]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2514
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2635]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2635
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324
[Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/356
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
[Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498
[Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
[Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605
[Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
[Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
[Intel XE#771]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/771
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#801]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/801
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
[Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
Build changes
-------------
* IGT: IGT_8008 -> IGT_8010
* Linux: xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a -> xe-pw-138168v2
IGT_8008: 91925eef7a79b1402b9422758311a4d693825362 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8010: 8010
xe-1909-217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a: 217031ad4c962ee8b1b7ac4b30323b4e2ac6d12a
xe-pw-138168v2: 138168v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138168v2/index.html
[-- Attachment #2: Type: text/html, Size: 149154 bytes --]
^ permalink raw reply [flat|nested] 83+ messages in thread