* [PATCH 1/9] drm/i915: Add helper to compute link M/N ratio for reuse
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
@ 2025-07-21 9:15 ` Ankit Nautiyal
2025-07-21 9:15 ` [PATCH 2/9] drm/i915/dp: Limit m/n ratio to 10 for DP SST Ankit Nautiyal
` (12 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-07-21 9:15 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: jani.nikula, uma.shankar, ville.syrjala, Ankit Nautiyal
Introduce `intel_display_get_link_m_n()` to compute the link M/N ratio
based on pixel clock and link clock. This logic was previously embedded
within `intel_link_compute_m_n()`.
The new helper allows reuse of link M/N computation in other contexts
without requiring the full data M/N calculation.
No functional changes intended.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 456fc4b04cda..671491a2a3b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2506,13 +2506,24 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
intel_reduce_m_n_ratio(ret_m, ret_n);
}
+static
+void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
+ u32 pixel_clock,
+ u32 link_clock)
+{
+ u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
+
+ compute_m_n(link_m, link_n,
+ pixel_clock, link_symbol_clock,
+ 0x80000);
+}
+
void
intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
int pixel_clock, int link_clock,
int bw_overhead,
struct intel_link_m_n *m_n)
{
- u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock);
u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16,
bw_overhead);
u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes);
@@ -2529,9 +2540,8 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
data_m, data_n,
0x8000000);
- compute_m_n(&m_n->link_m, &m_n->link_n,
- pixel_clock, link_symbol_clock,
- 0x80000);
+ intel_display_get_link_m_n(&m_n->link_m, &m_n->link_n,
+ pixel_clock, link_clock);
}
void intel_panel_sanitize_ssc(struct intel_display *display)
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 2/9] drm/i915/dp: Limit m/n ratio to 10 for DP SST
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
2025-07-21 9:15 ` [PATCH 1/9] drm/i915: Add helper to compute link M/N ratio for reuse Ankit Nautiyal
@ 2025-07-21 9:15 ` Ankit Nautiyal
2025-07-21 11:41 ` Imre Deak
2025-07-21 9:15 ` [PATCH 3/9] drm/i915/dp_mst: Limit m/n ratio to 10 for MST Ankit Nautiyal
` (11 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Ankit Nautiyal @ 2025-07-21 9:15 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: jani.nikula, uma.shankar, ville.syrjala, Ankit Nautiyal
The hardware cannot support DisplayPort configurations where the
ceiling of the Link M/Link N ratio exceeds 10. This limitation has
always existed, but it typically wasn't encountered without the use of
joiners and DSC.
With higher resolutions and combinations involving joiners and DSC,
this constraint can now be hit in certain scenarios.
Introduce a check during link rate configuration to ensure
the computed M/N ratio does not exceed the hardware limit. If no valid
link rate satisfies this constraint, the mode will be rejected.
Note: This change applies the check only for SST. Support for MST will
be added in a subsequent commit.
v2:
-Move the M/N ratio check to the link rate configuration phase instead
of during M/N computation. (Ville)
-Prune modes that cannot be supported even with highest link rate due to
M/N ratio restriction.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
drivers/gpu/drm/i915/display/intel_display.h | 3 ++
drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++-
3 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 671491a2a3b6..f32a4956c926 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2506,7 +2506,6 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
intel_reduce_m_n_ratio(ret_m, ret_n);
}
-static
void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
u32 pixel_clock,
u32 link_clock)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 37e2ab301a80..bfa3db219b9c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -559,5 +559,8 @@ bool assert_port_valid(struct intel_display *display, enum port port);
bool intel_scanout_needs_vtd_wa(struct intel_display *display);
int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
+void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
+ u32 pixel_clock,
+ u32 link_clock);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 54d88f24b689..4245dd65b2af 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1407,6 +1407,28 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
return true;
}
+static int
+intel_dp_get_max_m_n_ratio(void)
+{
+ return 10;
+}
+
+static bool
+intel_dp_can_support_m_n(int pixel_clock,
+ int link_rate)
+{
+ int max_m_n_ratio = intel_dp_get_max_m_n_ratio();
+ u32 link_m, link_n;
+ int m_n_ratio;
+
+ intel_display_get_link_m_n(&link_m, &link_n,
+ pixel_clock, link_rate);
+
+ m_n_ratio = DIV_ROUND_UP(link_m, link_n);
+
+ return m_n_ratio <= max_m_n_ratio;
+}
+
static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector *_connector,
const struct drm_display_mode *mode)
@@ -1518,6 +1540,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (status != MODE_OK)
return status;
+ if (!intel_dp_can_support_m_n(target_clock, max_rate))
+ return MODE_CLOCK_HIGH;
+
return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
}
@@ -1789,6 +1814,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
link_rate > limits->max_rate)
continue;
+ if (!intel_dp_can_support_m_n(clock, link_rate))
+ continue;
+
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
@@ -1796,7 +1824,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
link_rate,
lane_count);
-
if (mode_rate <= link_avail) {
pipe_config->lane_count = lane_count;
pipe_config->pipe_bpp = bpp;
@@ -1983,6 +2010,10 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
if (link_rate < limits->min_rate || link_rate > limits->max_rate)
continue;
+ if (!intel_dp_can_support_m_n(adjusted_mode->clock,
+ link_rate))
+ continue;
+
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 2/9] drm/i915/dp: Limit m/n ratio to 10 for DP SST
2025-07-21 9:15 ` [PATCH 2/9] drm/i915/dp: Limit m/n ratio to 10 for DP SST Ankit Nautiyal
@ 2025-07-21 11:41 ` Imre Deak
2025-07-22 5:55 ` Nautiyal, Ankit K
0 siblings, 1 reply; 21+ messages in thread
From: Imre Deak @ 2025-07-21 11:41 UTC (permalink / raw)
To: Ankit Nautiyal
Cc: intel-gfx, intel-xe, jani.nikula, uma.shankar, ville.syrjala
On Mon, Jul 21, 2025 at 02:45:22PM +0530, Ankit Nautiyal wrote:
> The hardware cannot support DisplayPort configurations where the
> ceiling of the Link M/Link N ratio exceeds 10. This limitation has
> always existed, but it typically wasn't encountered without the use of
> joiners and DSC.
>
> With higher resolutions and combinations involving joiners and DSC,
> this constraint can now be hit in certain scenarios.
>
> Introduce a check during link rate configuration to ensure
> the computed M/N ratio does not exceed the hardware limit. If no valid
> link rate satisfies this constraint, the mode will be rejected.
>
> Note: This change applies the check only for SST. Support for MST will
> be added in a subsequent commit.
>
> v2:
> -Move the M/N ratio check to the link rate configuration phase instead
> of during M/N computation. (Ville)
> -Prune modes that cannot be supported even with highest link rate due to
> M/N ratio restriction.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 -
> drivers/gpu/drm/i915/display/intel_display.h | 3 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++-
> 3 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 671491a2a3b6..f32a4956c926 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2506,7 +2506,6 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
> intel_reduce_m_n_ratio(ret_m, ret_n);
> }
>
> -static
> void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
> u32 pixel_clock,
> u32 link_clock)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 37e2ab301a80..bfa3db219b9c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -559,5 +559,8 @@ bool assert_port_valid(struct intel_display *display, enum port port);
>
> bool intel_scanout_needs_vtd_wa(struct intel_display *display);
> int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
> +void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
> + u32 pixel_clock,
> + u32 link_clock);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 54d88f24b689..4245dd65b2af 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1407,6 +1407,28 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
> return true;
> }
>
> +static int
> +intel_dp_get_max_m_n_ratio(void)
> +{
> + return 10;
> +}
> +
> +static bool
> +intel_dp_can_support_m_n(int pixel_clock,
> + int link_rate)
> +{
> + int max_m_n_ratio = intel_dp_get_max_m_n_ratio();
> + u32 link_m, link_n;
> + int m_n_ratio;
> +
> + intel_display_get_link_m_n(&link_m, &link_n,
> + pixel_clock, link_rate);
> +
> + m_n_ratio = DIV_ROUND_UP(link_m, link_n);
> +
> + return m_n_ratio <= max_m_n_ratio;
> +}
> +
> static enum drm_mode_status
> intel_dp_mode_valid(struct drm_connector *_connector,
> const struct drm_display_mode *mode)
> @@ -1518,6 +1540,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> if (status != MODE_OK)
> return status;
>
> + if (!intel_dp_can_support_m_n(target_clock, max_rate))
> + return MODE_CLOCK_HIGH;
> +
> return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
> }
>
> @@ -1789,6 +1814,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> link_rate > limits->max_rate)
> continue;
>
> + if (!intel_dp_can_support_m_n(clock, link_rate))
> + continue;
Could this limit be set in limits->min_rate, computed already in
intel_dp_compute_config_limits()? (And fail already there if this is
bigger than limits->max_rate.)
> +
> for (lane_count = limits->min_lane_count;
> lane_count <= limits->max_lane_count;
> lane_count <<= 1) {
> @@ -1796,7 +1824,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> link_rate,
> lane_count);
>
> -
> if (mode_rate <= link_avail) {
> pipe_config->lane_count = lane_count;
> pipe_config->pipe_bpp = bpp;
> @@ -1983,6 +2010,10 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
> if (link_rate < limits->min_rate || link_rate > limits->max_rate)
> continue;
>
> + if (!intel_dp_can_support_m_n(adjusted_mode->clock,
> + link_rate))
> + continue;
> +
> for (lane_count = limits->min_lane_count;
> lane_count <= limits->max_lane_count;
> lane_count <<= 1) {
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 2/9] drm/i915/dp: Limit m/n ratio to 10 for DP SST
2025-07-21 11:41 ` Imre Deak
@ 2025-07-22 5:55 ` Nautiyal, Ankit K
2025-07-22 9:22 ` Imre Deak
0 siblings, 1 reply; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-07-22 5:55 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx, intel-xe, jani.nikula, uma.shankar, ville.syrjala
On 7/21/2025 5:11 PM, Imre Deak wrote:
> On Mon, Jul 21, 2025 at 02:45:22PM +0530, Ankit Nautiyal wrote:
>> The hardware cannot support DisplayPort configurations where the
>> ceiling of the Link M/Link N ratio exceeds 10. This limitation has
>> always existed, but it typically wasn't encountered without the use of
>> joiners and DSC.
>>
>> With higher resolutions and combinations involving joiners and DSC,
>> this constraint can now be hit in certain scenarios.
>>
>> Introduce a check during link rate configuration to ensure
>> the computed M/N ratio does not exceed the hardware limit. If no valid
>> link rate satisfies this constraint, the mode will be rejected.
>>
>> Note: This change applies the check only for SST. Support for MST will
>> be added in a subsequent commit.
>>
>> v2:
>> -Move the M/N ratio check to the link rate configuration phase instead
>> of during M/N computation. (Ville)
>> -Prune modes that cannot be supported even with highest link rate due to
>> M/N ratio restriction.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 1 -
>> drivers/gpu/drm/i915/display/intel_display.h | 3 ++
>> drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++-
>> 3 files changed, 35 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 671491a2a3b6..f32a4956c926 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -2506,7 +2506,6 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
>> intel_reduce_m_n_ratio(ret_m, ret_n);
>> }
>>
>> -static
>> void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
>> u32 pixel_clock,
>> u32 link_clock)
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> index 37e2ab301a80..bfa3db219b9c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> @@ -559,5 +559,8 @@ bool assert_port_valid(struct intel_display *display, enum port port);
>>
>> bool intel_scanout_needs_vtd_wa(struct intel_display *display);
>> int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
>> +void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
>> + u32 pixel_clock,
>> + u32 link_clock);
>>
>> #endif
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 54d88f24b689..4245dd65b2af 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1407,6 +1407,28 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
>> return true;
>> }
>>
>> +static int
>> +intel_dp_get_max_m_n_ratio(void)
>> +{
>> + return 10;
>> +}
>> +
>> +static bool
>> +intel_dp_can_support_m_n(int pixel_clock,
>> + int link_rate)
>> +{
>> + int max_m_n_ratio = intel_dp_get_max_m_n_ratio();
>> + u32 link_m, link_n;
>> + int m_n_ratio;
>> +
>> + intel_display_get_link_m_n(&link_m, &link_n,
>> + pixel_clock, link_rate);
>> +
>> + m_n_ratio = DIV_ROUND_UP(link_m, link_n);
>> +
>> + return m_n_ratio <= max_m_n_ratio;
>> +}
>> +
>> static enum drm_mode_status
>> intel_dp_mode_valid(struct drm_connector *_connector,
>> const struct drm_display_mode *mode)
>> @@ -1518,6 +1540,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>> if (status != MODE_OK)
>> return status;
>>
>> + if (!intel_dp_can_support_m_n(target_clock, max_rate))
>> + return MODE_CLOCK_HIGH;
>> +
>> return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
>> }
>>
>> @@ -1789,6 +1814,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>> link_rate > limits->max_rate)
>> continue;
>>
>> + if (!intel_dp_can_support_m_n(clock, link_rate))
>> + continue;
> Could this limit be set in limits->min_rate, computed already in
> intel_dp_compute_config_limits()? (And fail already there if this is
> bigger than limits->max_rate.)
Yes right this can be done in intel_dp_compute_config_limit.
We can iterate over the array of common_rates and find the rate for
which the ratio is within limits and bail out early if we cant find such
a link rate.
Or otherwise instead of iterating over rates, I guess theoretically we
can calculate the minimum link rate for given pixelclock and ratio and
set it to limits->min_rate and bail out early if this is more than the
limits->max_rate.
However this might be bit tricky as symbol size is different for uhbr.
I will check this out, and move this in intel_dp_compute_config_limits.
Thanks & Regards,
Ankit
>
>> +
>> for (lane_count = limits->min_lane_count;
>> lane_count <= limits->max_lane_count;
>> lane_count <<= 1) {
>> @@ -1796,7 +1824,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>> link_rate,
>> lane_count);
>>
>> -
>> if (mode_rate <= link_avail) {
>> pipe_config->lane_count = lane_count;
>> pipe_config->pipe_bpp = bpp;
>> @@ -1983,6 +2010,10 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
>> if (link_rate < limits->min_rate || link_rate > limits->max_rate)
>> continue;
>>
>> + if (!intel_dp_can_support_m_n(adjusted_mode->clock,
>> + link_rate))
>> + continue;
>> +
>> for (lane_count = limits->min_lane_count;
>> lane_count <= limits->max_lane_count;
>> lane_count <<= 1) {
>> --
>> 2.45.2
>>
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 2/9] drm/i915/dp: Limit m/n ratio to 10 for DP SST
2025-07-22 5:55 ` Nautiyal, Ankit K
@ 2025-07-22 9:22 ` Imre Deak
2025-07-22 15:15 ` Nautiyal, Ankit K
0 siblings, 1 reply; 21+ messages in thread
From: Imre Deak @ 2025-07-22 9:22 UTC (permalink / raw)
To: Nautiyal, Ankit K
Cc: intel-gfx, intel-xe, jani.nikula, uma.shankar, ville.syrjala
On Tue, Jul 22, 2025 at 11:25:32AM +0530, Nautiyal, Ankit K wrote:
>
> On 7/21/2025 5:11 PM, Imre Deak wrote:
> > On Mon, Jul 21, 2025 at 02:45:22PM +0530, Ankit Nautiyal wrote:
> > > The hardware cannot support DisplayPort configurations where the
> > > ceiling of the Link M/Link N ratio exceeds 10. This limitation has
> > > always existed, but it typically wasn't encountered without the use of
> > > joiners and DSC.
> > >
> > > With higher resolutions and combinations involving joiners and DSC,
> > > this constraint can now be hit in certain scenarios.
> > >
> > > Introduce a check during link rate configuration to ensure
> > > the computed M/N ratio does not exceed the hardware limit. If no valid
> > > link rate satisfies this constraint, the mode will be rejected.
> > >
> > > Note: This change applies the check only for SST. Support for MST will
> > > be added in a subsequent commit.
> > >
> > > v2:
> > > -Move the M/N ratio check to the link rate configuration phase instead
> > > of during M/N computation. (Ville)
> > > -Prune modes that cannot be supported even with highest link rate due to
> > > M/N ratio restriction.
> > >
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 1 -
> > > drivers/gpu/drm/i915/display/intel_display.h | 3 ++
> > > drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++-
> > > 3 files changed, 35 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 671491a2a3b6..f32a4956c926 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -2506,7 +2506,6 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
> > > intel_reduce_m_n_ratio(ret_m, ret_n);
> > > }
> > > -static
> > > void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
> > > u32 pixel_clock,
> > > u32 link_clock)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > > index 37e2ab301a80..bfa3db219b9c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > > @@ -559,5 +559,8 @@ bool assert_port_valid(struct intel_display *display, enum port port);
> > > bool intel_scanout_needs_vtd_wa(struct intel_display *display);
> > > int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
> > > +void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
> > > + u32 pixel_clock,
> > > + u32 link_clock);
> > > #endif
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 54d88f24b689..4245dd65b2af 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1407,6 +1407,28 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
> > > return true;
> > > }
> > > +static int
> > > +intel_dp_get_max_m_n_ratio(void)
> > > +{
> > > + return 10;
> > > +}
> > > +
> > > +static bool
> > > +intel_dp_can_support_m_n(int pixel_clock,
> > > + int link_rate)
> > > +{
> > > + int max_m_n_ratio = intel_dp_get_max_m_n_ratio();
> > > + u32 link_m, link_n;
> > > + int m_n_ratio;
> > > +
> > > + intel_display_get_link_m_n(&link_m, &link_n,
> > > + pixel_clock, link_rate);
> > > +
> > > + m_n_ratio = DIV_ROUND_UP(link_m, link_n);
> > > +
> > > + return m_n_ratio <= max_m_n_ratio;
> > > +}
> > > +
> > > static enum drm_mode_status
> > > intel_dp_mode_valid(struct drm_connector *_connector,
> > > const struct drm_display_mode *mode)
> > > @@ -1518,6 +1540,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
> > > if (status != MODE_OK)
> > > return status;
> > > + if (!intel_dp_can_support_m_n(target_clock, max_rate))
> > > + return MODE_CLOCK_HIGH;
> > > +
> > > return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
> > > }
> > > @@ -1789,6 +1814,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> > > link_rate > limits->max_rate)
> > > continue;
> > > + if (!intel_dp_can_support_m_n(clock, link_rate))
> > > + continue;
> > Could this limit be set in limits->min_rate, computed already in
> > intel_dp_compute_config_limits()? (And fail already there if this is
> > bigger than limits->max_rate.)
>
> Yes right this can be done in intel_dp_compute_config_limit.
>
> We can iterate over the array of common_rates and find the rate for which
> the ratio is within limits and bail out early if we cant find such a link
> rate.
>
> Or otherwise instead of iterating over rates, I guess theoretically we can
> calculate the minimum link rate for given pixelclock and ratio and set it to
> limits->min_rate and bail out early if this is more than the
> limits->max_rate.
Right, the first option to just iterate over common_rates sounds better.
limits->min_rate should be set to a validate rate, so it will need to be
looked up from common_rates anyway. There's also
intel_dp_rate_limit_len()/intel_dp_common_rate(), but the former returns
the index for a rate which is <= than the limit passed to it (while >=
would be needed here), so can't be used as-is.
I noticed that the mode's pixel clock is adjusted later based on the MSO
link count (in intel_dp_compute_config()) and the number of joined pipes
(in intel_joiner_adjust_timings()), but I suppose this doesn't matter,
since the link m/n values are calculated with the unadjusted pixel
clock. Could you confirm this nevertheless?
> However this might be bit tricky as symbol size is different for uhbr.
>
> I will check this out, and move this in intel_dp_compute_config_limits.
>
> Thanks & Regards,
>
> Ankit
>
>
> >
> > > +
> > > for (lane_count = limits->min_lane_count;
> > > lane_count <= limits->max_lane_count;
> > > lane_count <<= 1) {
> > > @@ -1796,7 +1824,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
> > > link_rate,
> > > lane_count);
> > > -
> > > if (mode_rate <= link_avail) {
> > > pipe_config->lane_count = lane_count;
> > > pipe_config->pipe_bpp = bpp;
> > > @@ -1983,6 +2010,10 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
> > > if (link_rate < limits->min_rate || link_rate > limits->max_rate)
> > > continue;
> > > + if (!intel_dp_can_support_m_n(adjusted_mode->clock,
> > > + link_rate))
> > > + continue;
> > > +
> > > for (lane_count = limits->min_lane_count;
> > > lane_count <= limits->max_lane_count;
> > > lane_count <<= 1) {
> > > --
> > > 2.45.2
> > >
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 2/9] drm/i915/dp: Limit m/n ratio to 10 for DP SST
2025-07-22 9:22 ` Imre Deak
@ 2025-07-22 15:15 ` Nautiyal, Ankit K
0 siblings, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-07-22 15:15 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx, intel-xe, jani.nikula, uma.shankar, ville.syrjala
On 7/22/2025 2:52 PM, Imre Deak wrote:
> On Tue, Jul 22, 2025 at 11:25:32AM +0530, Nautiyal, Ankit K wrote:
>> On 7/21/2025 5:11 PM, Imre Deak wrote:
>>> On Mon, Jul 21, 2025 at 02:45:22PM +0530, Ankit Nautiyal wrote:
>>>> The hardware cannot support DisplayPort configurations where the
>>>> ceiling of the Link M/Link N ratio exceeds 10. This limitation has
>>>> always existed, but it typically wasn't encountered without the use of
>>>> joiners and DSC.
>>>>
>>>> With higher resolutions and combinations involving joiners and DSC,
>>>> this constraint can now be hit in certain scenarios.
>>>>
>>>> Introduce a check during link rate configuration to ensure
>>>> the computed M/N ratio does not exceed the hardware limit. If no valid
>>>> link rate satisfies this constraint, the mode will be rejected.
>>>>
>>>> Note: This change applies the check only for SST. Support for MST will
>>>> be added in a subsequent commit.
>>>>
>>>> v2:
>>>> -Move the M/N ratio check to the link rate configuration phase instead
>>>> of during M/N computation. (Ville)
>>>> -Prune modes that cannot be supported even with highest link rate due to
>>>> M/N ratio restriction.
>>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_display.c | 1 -
>>>> drivers/gpu/drm/i915/display/intel_display.h | 3 ++
>>>> drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++-
>>>> 3 files changed, 35 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>>> index 671491a2a3b6..f32a4956c926 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>> @@ -2506,7 +2506,6 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
>>>> intel_reduce_m_n_ratio(ret_m, ret_n);
>>>> }
>>>> -static
>>>> void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
>>>> u32 pixel_clock,
>>>> u32 link_clock)
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>>>> index 37e2ab301a80..bfa3db219b9c 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>>>> @@ -559,5 +559,8 @@ bool assert_port_valid(struct intel_display *display, enum port port);
>>>> bool intel_scanout_needs_vtd_wa(struct intel_display *display);
>>>> int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
>>>> +void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
>>>> + u32 pixel_clock,
>>>> + u32 link_clock);
>>>> #endif
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index 54d88f24b689..4245dd65b2af 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -1407,6 +1407,28 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
>>>> return true;
>>>> }
>>>> +static int
>>>> +intel_dp_get_max_m_n_ratio(void)
>>>> +{
>>>> + return 10;
>>>> +}
>>>> +
>>>> +static bool
>>>> +intel_dp_can_support_m_n(int pixel_clock,
>>>> + int link_rate)
>>>> +{
>>>> + int max_m_n_ratio = intel_dp_get_max_m_n_ratio();
>>>> + u32 link_m, link_n;
>>>> + int m_n_ratio;
>>>> +
>>>> + intel_display_get_link_m_n(&link_m, &link_n,
>>>> + pixel_clock, link_rate);
>>>> +
>>>> + m_n_ratio = DIV_ROUND_UP(link_m, link_n);
>>>> +
>>>> + return m_n_ratio <= max_m_n_ratio;
>>>> +}
>>>> +
>>>> static enum drm_mode_status
>>>> intel_dp_mode_valid(struct drm_connector *_connector,
>>>> const struct drm_display_mode *mode)
>>>> @@ -1518,6 +1540,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>>>> if (status != MODE_OK)
>>>> return status;
>>>> + if (!intel_dp_can_support_m_n(target_clock, max_rate))
>>>> + return MODE_CLOCK_HIGH;
>>>> +
>>>> return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
>>>> }
>>>> @@ -1789,6 +1814,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>>>> link_rate > limits->max_rate)
>>>> continue;
>>>> + if (!intel_dp_can_support_m_n(clock, link_rate))
>>>> + continue;
>>> Could this limit be set in limits->min_rate, computed already in
>>> intel_dp_compute_config_limits()? (And fail already there if this is
>>> bigger than limits->max_rate.)
>> Yes right this can be done in intel_dp_compute_config_limit.
>>
>> We can iterate over the array of common_rates and find the rate for which
>> the ratio is within limits and bail out early if we cant find such a link
>> rate.
>>
>> Or otherwise instead of iterating over rates, I guess theoretically we can
>> calculate the minimum link rate for given pixelclock and ratio and set it to
>> limits->min_rate and bail out early if this is more than the
>> limits->max_rate.
> Right, the first option to just iterate over common_rates sounds better.
>
> limits->min_rate should be set to a validate rate, so it will need to be
> looked up from common_rates anyway. There's also
> intel_dp_rate_limit_len()/intel_dp_common_rate(), but the former returns
> the index for a rate which is <= than the limit passed to it (while >=
> would be needed here), so can't be used as-is.
>
> I noticed that the mode's pixel clock is adjusted later based on the MSO
> link count (in intel_dp_compute_config()) and the number of joined pipes
> (in intel_joiner_adjust_timings()), but I suppose this doesn't matter,
> since the link m/n values are calculated with the unadjusted pixel
> clock. Could you confirm this nevertheless?
Yes this should be unadjusted pixel clock. I did not realize this
earlier, will need to fix patch#4.
Also realized from Wa_14014191401 this need to be only for UHBR rates
and also for DG2 the ratio is 4.
Regards,
Ankit
>
>> However this might be bit tricky as symbol size is different for uhbr.
>>
>> I will check this out, and move this in intel_dp_compute_config_limits.
>>
>> Thanks & Regards,
>>
>> Ankit
>>
>>
>>>> +
>>>> for (lane_count = limits->min_lane_count;
>>>> lane_count <= limits->max_lane_count;
>>>> lane_count <<= 1) {
>>>> @@ -1796,7 +1824,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>>>> link_rate,
>>>> lane_count);
>>>> -
>>>> if (mode_rate <= link_avail) {
>>>> pipe_config->lane_count = lane_count;
>>>> pipe_config->pipe_bpp = bpp;
>>>> @@ -1983,6 +2010,10 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
>>>> if (link_rate < limits->min_rate || link_rate > limits->max_rate)
>>>> continue;
>>>> + if (!intel_dp_can_support_m_n(adjusted_mode->clock,
>>>> + link_rate))
>>>> + continue;
>>>> +
>>>> for (lane_count = limits->min_lane_count;
>>>> lane_count <= limits->max_lane_count;
>>>> lane_count <<= 1) {
>>>> --
>>>> 2.45.2
>>>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 3/9] drm/i915/dp_mst: Limit m/n ratio to 10 for MST
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
2025-07-21 9:15 ` [PATCH 1/9] drm/i915: Add helper to compute link M/N ratio for reuse Ankit Nautiyal
2025-07-21 9:15 ` [PATCH 2/9] drm/i915/dp: Limit m/n ratio to 10 for DP SST Ankit Nautiyal
@ 2025-07-21 9:15 ` Ankit Nautiyal
2025-07-21 9:15 ` [PATCH 4/9] drm/i915/dp: Add M/N ratio check with warning for DP link config Ankit Nautiyal
` (10 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-07-21 9:15 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: jani.nikula, uma.shankar, ville.syrjala, Ankit Nautiyal
The hardware does not support DisplayPort configurations where the ceiling
of the Link M/Link N ratio exceeds 10. Enforce this constraint for MST
as well.
Add a check to reject mode for which where the M/N ratio exceeds the
supported limit. For MST, in compute config phase currently we use the
maximum link rate so just check if the M/N ratio is with in limit,
and bail out.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.h | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 ++++++++++++++++----
3 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4245dd65b2af..a1077a7ba7da 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1413,7 +1413,7 @@ intel_dp_get_max_m_n_ratio(void)
return 10;
}
-static bool
+bool
intel_dp_can_support_m_n(int pixel_clock,
int link_rate)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0657f5681196..16555a9c53c4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -214,5 +214,6 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
+bool intel_dp_can_support_m_n(int pixel_clock, int link_rate);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 74497c9a0554..62da0cb70607 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -202,10 +202,10 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
}
-static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
- int overhead,
- int bpp_x16,
- struct intel_link_m_n *m_n)
+static int intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
+ int overhead,
+ int bpp_x16,
+ struct intel_link_m_n *m_n)
{
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
@@ -218,6 +218,8 @@ static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
m_n);
m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
+
+ return 0;
}
static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead)
@@ -445,6 +447,11 @@ static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
{
crtc_state->lane_count = limits->max_lane_count;
crtc_state->port_clock = limits->max_rate;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+ if (!intel_dp_can_support_m_n(adjusted_mode->clock, crtc_state->port_clock))
+ return -EINVAL;
/*
* FIXME: allocate the BW according to link_bpp, which in the case of
@@ -1551,6 +1558,11 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
return 0;
}
+ if (!intel_dp_can_support_m_n(mode->clock, max_rate)) {
+ *status = MODE_CLOCK_HIGH;
+ return 0;
+ }
+
*status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
return 0;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 4/9] drm/i915/dp: Add M/N ratio check with warning for DP link config
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (2 preceding siblings ...)
2025-07-21 9:15 ` [PATCH 3/9] drm/i915/dp_mst: Limit m/n ratio to 10 for MST Ankit Nautiyal
@ 2025-07-21 9:15 ` Ankit Nautiyal
2025-07-21 9:15 ` [PATCH 5/9] drm/i915/display: Add bits for link_n_exended for DISPLAY >= 14 Ankit Nautiyal
` (9 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-07-21 9:15 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: jani.nikula, uma.shankar, ville.syrjala, Ankit Nautiyal
Introduce intel_dp_check_m_n_ratio() to validate the computed link
M/N ratio against the maximum allowed value. If the ratio exceeds the
limit, a warning is issued via drm_WARN().
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
drivers/gpu/drm/i915/display/intel_fdi.c | 2 ++
4 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a1077a7ba7da..a1114d1059dd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3001,6 +3001,23 @@ static bool can_enable_drrs(struct intel_connector *connector,
intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
}
+void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
+ struct intel_link_m_n *m_n)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ int m_n_ratio;
+
+ if (!m_n || !m_n->link_n)
+ return;
+
+ m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+ if (m_n_ratio > intel_dp_get_max_m_n_ratio())
+ drm_WARN(display->drm, 1,
+ "Link M/N ratio (%d) exceeds max allowed (%d)\n",
+ m_n_ratio, intel_dp_get_max_m_n_ratio());
+}
+
static void
intel_dp_drrs_compute_config(struct intel_connector *connector,
struct intel_crtc_state *pipe_config,
@@ -3039,6 +3056,8 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
intel_dp_bw_fec_overhead(pipe_config->fec_enable),
&pipe_config->dp_m2_n2);
+ intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m2_n2);
+
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
@@ -3316,6 +3335,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
pipe_config->port_clock,
intel_dp_bw_fec_overhead(pipe_config->fec_enable),
&pipe_config->dp_m_n);
+
+ intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m_n);
}
ret = intel_dp_compute_min_hblank(pipe_config, conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 16555a9c53c4..a197eb0a7fc6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -22,6 +22,7 @@ struct intel_digital_port;
struct intel_display;
struct intel_dp;
struct intel_encoder;
+struct intel_link_m_n;
struct link_config_limits {
int min_rate, max_rate;
@@ -215,5 +216,7 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
bool intel_dp_can_support_m_n(int pixel_clock, int link_rate);
+void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
+ struct intel_link_m_n *m_n);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 62da0cb70607..45b72a2c8588 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -347,6 +347,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
link_bpp_x16,
&crtc_state->dp_m_n);
+ intel_dp_check_m_n_ratio(crtc_state, &crtc_state->dp_m_n);
+
if (is_mst) {
int remote_bw_overhead;
int remote_tu;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 8039a84671cc..d8e9d6e108e8 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -349,6 +349,8 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
intel_dp_bw_fec_overhead(false),
&pipe_config->fdi_m_n);
+ intel_dp_check_m_n_ratio(pipe_config, &pipe_config->dp_m_n);
+
return 0;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 5/9] drm/i915/display: Add bits for link_n_exended for DISPLAY >= 14
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (3 preceding siblings ...)
2025-07-21 9:15 ` [PATCH 4/9] drm/i915/dp: Add M/N ratio check with warning for DP link config Ankit Nautiyal
@ 2025-07-21 9:15 ` Ankit Nautiyal
2025-07-29 11:08 ` Jani Nikula
2025-07-21 9:15 ` [PATCH 6/9] drm/i915/display_wa: Add support for Wa_14021768792 Ankit Nautiyal
` (8 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Ankit Nautiyal @ 2025-07-21 9:15 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: jani.nikula, uma.shankar, ville.syrjala, Ankit Nautiyal
LINK_N register has bits 31:24 for extended link N value used for
HDMI2.1 and for an alternate mode of operation of DP TG DDA
(Bspec:50488).
Add support for these extra bits.
For displays with version 14 or higher, the `PIPE_LINK_N1_EXTENDED_MASK`
(bits 31:24) is used to handle the extended link N bits.
For older platforms, the `DATA_LINK_M_N_MASK` (bits 23:0) is used to
handle the standard link N bits. This distinction ensures clarity and
maintains the semantics for platforms that support the extended bits.
In subsequent changes the logic is updated to conditionally apply the
extended link N bits.
v2: Drop extra link_n_ext member. (Jani)
v3: Avoid link_n_ext in set_m_n helper. (Jani)
v4: Rebase, and update commit message.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++--
.../gpu/drm/i915/display/intel_display_regs.h | 2 ++
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f32a4956c926..5232478613aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2578,14 +2578,22 @@ void intel_set_m_n(struct intel_display *display,
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
i915_reg_t link_m_reg, i915_reg_t link_n_reg)
{
+ u32 link_n = m_n->link_n;
+
intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
intel_de_write(display, data_n_reg, m_n->data_n);
intel_de_write(display, link_m_reg, m_n->link_m);
+
+ if (DISPLAY_VER(display) >= 14)
+ link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+ else
+ link_n &= DATA_LINK_M_N_MASK;
+
/*
* On BDW+ writing LINK_N arms the double buffered update
* of all the M/N registers, so it must be written last.
*/
- intel_de_write(display, link_n_reg, m_n->link_n);
+ intel_de_write(display, link_n_reg, link_n);
}
bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
@@ -3321,7 +3329,13 @@ void intel_get_m_n(struct intel_display *display,
i915_reg_t link_m_reg, i915_reg_t link_n_reg)
{
m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
- m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
+ m_n->link_n = intel_de_read(display, link_n_reg);
+
+ if (DISPLAY_VER(display) >= 14)
+ m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
+ else
+ m_n->link_n &= DATA_LINK_M_N_MASK;
+
m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 7bd09d981cd2..9248561aec5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1027,6 +1027,8 @@
#define _PIPEA_LINK_N1 0x60044
#define _PIPEB_LINK_N1 0x61044
+#define PIPE_LINK_N1_EXTENDED_MASK REG_GENMASK(31, 24)
+#define PIPE_LINK_N1_EXTENDED(val) REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
#define _PIPEA_LINK_M2 0x60048
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 5/9] drm/i915/display: Add bits for link_n_exended for DISPLAY >= 14
2025-07-21 9:15 ` [PATCH 5/9] drm/i915/display: Add bits for link_n_exended for DISPLAY >= 14 Ankit Nautiyal
@ 2025-07-29 11:08 ` Jani Nikula
0 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2025-07-29 11:08 UTC (permalink / raw)
To: Ankit Nautiyal, intel-gfx, intel-xe
Cc: uma.shankar, ville.syrjala, Ankit Nautiyal
On Mon, 21 Jul 2025, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> LINK_N register has bits 31:24 for extended link N value used for
> HDMI2.1 and for an alternate mode of operation of DP TG DDA
> (Bspec:50488).
>
> Add support for these extra bits.
>
> For displays with version 14 or higher, the `PIPE_LINK_N1_EXTENDED_MASK`
> (bits 31:24) is used to handle the extended link N bits.
> For older platforms, the `DATA_LINK_M_N_MASK` (bits 23:0) is used to
> handle the standard link N bits. This distinction ensures clarity and
> maintains the semantics for platforms that support the extended bits.
> In subsequent changes the logic is updated to conditionally apply the
> extended link N bits.
>
> v2: Drop extra link_n_ext member. (Jani)
> v3: Avoid link_n_ext in set_m_n helper. (Jani)
> v4: Rebase, and update commit message.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++--
> .../gpu/drm/i915/display/intel_display_regs.h | 2 ++
> 2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f32a4956c926..5232478613aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2578,14 +2578,22 @@ void intel_set_m_n(struct intel_display *display,
> i915_reg_t data_m_reg, i915_reg_t data_n_reg,
> i915_reg_t link_m_reg, i915_reg_t link_n_reg)
> {
> + u32 link_n = m_n->link_n;
> +
> intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
> intel_de_write(display, data_n_reg, m_n->data_n);
> intel_de_write(display, link_m_reg, m_n->link_m);
> +
> + if (DISPLAY_VER(display) >= 14)
> + link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
> + else
> + link_n &= DATA_LINK_M_N_MASK;
> +
> /*
> * On BDW+ writing LINK_N arms the double buffered update
> * of all the M/N registers, so it must be written last.
> */
> - intel_de_write(display, link_n_reg, m_n->link_n);
> + intel_de_write(display, link_n_reg, link_n);
> }
>
> bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
> @@ -3321,7 +3329,13 @@ void intel_get_m_n(struct intel_display *display,
> i915_reg_t link_m_reg, i915_reg_t link_n_reg)
> {
> m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
> - m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK;
> + m_n->link_n = intel_de_read(display, link_n_reg);
> +
> + if (DISPLAY_VER(display) >= 14)
> + m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
> + else
> + m_n->link_n &= DATA_LINK_M_N_MASK;
> +
> m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
> m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
> m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 7bd09d981cd2..9248561aec5f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1027,6 +1027,8 @@
>
> #define _PIPEA_LINK_N1 0x60044
> #define _PIPEB_LINK_N1 0x61044
> +#define PIPE_LINK_N1_EXTENDED_MASK REG_GENMASK(31, 24)
> +#define PIPE_LINK_N1_EXTENDED(val) REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
Please read the comment near the top of i915_reg.h, and send patches to
amend the comment if there's something unclear.
BR,
Jani.
> #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
>
> #define _PIPEA_LINK_M2 0x60048
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 6/9] drm/i915/display_wa: Add support for Wa_14021768792
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (4 preceding siblings ...)
2025-07-21 9:15 ` [PATCH 5/9] drm/i915/display: Add bits for link_n_exended for DISPLAY >= 14 Ankit Nautiyal
@ 2025-07-21 9:15 ` Ankit Nautiyal
2025-07-29 11:10 ` Jani Nikula
2025-07-21 9:15 ` [PATCH 7/9] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10 Ankit Nautiyal
` (7 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Ankit Nautiyal @ 2025-07-21 9:15 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: jani.nikula, uma.shankar, ville.syrjala, Ankit Nautiyal
Some BMG ultrajoiner configurations require support for Link M/N ratios
between 10.0 and 15.0. This range is not natively supported and requires
a workaround.
Wa_14021768792 enables this support by utilizing HDMI_EMP_DATA,
CHICKEN_BITs, and extended bits in the LINK_N registers.
Add the necessary logic to enable the workaround on applicable platforms.
Bspec: 49266
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
.../gpu/drm/i915/display/intel_display_wa.c | 18 ++++++++++++++++++
.../gpu/drm/i915/display/intel_display_wa.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 399c08902413..541967168e97 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -5,11 +5,13 @@
#include <drm/drm_print.h>
+#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_core.h"
#include "intel_display_regs.h"
#include "intel_display_wa.h"
+#include "intel_step.h"
static void gen11_display_wa_apply(struct intel_display *display)
{
@@ -52,6 +54,20 @@ static bool intel_display_needs_wa_16025573575(struct intel_display *display)
return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002;
}
+/*
+ * Wa_14021768792:
+ * Fixes: Limitation of Link M/N ratio > 10 for specific Xe2HPD platforms.
+ * Workaround: Use HDMI_EMP_DATA, CHICKEN_BITs and extended bits in LINK_N registers to support
+ * LINK M/N ratios from > 10 but < 15.
+ */
+static bool intel_display_needs_wa_14021768792(struct intel_display *display)
+{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
+ return (DISPLAY_VER(display) == 14 && IS_DGFX(i915) &&
+ IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER));
+}
+
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name)
{
switch (wa) {
@@ -59,6 +75,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
return intel_display_needs_wa_16023588340(display);
case INTEL_DISPLAY_WA_16025573575:
return intel_display_needs_wa_16025573575(display);
+ case INTEL_DISPLAY_WA_14021768792:
+ return intel_display_needs_wa_14021768792(display);
default:
drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);
break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index aedea4cfa3ce..8470f4ceea1a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -24,6 +24,7 @@ bool intel_display_needs_wa_16023588340(struct intel_display *display);
enum intel_display_wa {
INTEL_DISPLAY_WA_16023588340,
INTEL_DISPLAY_WA_16025573575,
+ INTEL_DISPLAY_WA_14021768792,
};
bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 6/9] drm/i915/display_wa: Add support for Wa_14021768792
2025-07-21 9:15 ` [PATCH 6/9] drm/i915/display_wa: Add support for Wa_14021768792 Ankit Nautiyal
@ 2025-07-29 11:10 ` Jani Nikula
0 siblings, 0 replies; 21+ messages in thread
From: Jani Nikula @ 2025-07-29 11:10 UTC (permalink / raw)
To: Ankit Nautiyal, intel-gfx, intel-xe
Cc: uma.shankar, ville.syrjala, Ankit Nautiyal
On Mon, 21 Jul 2025, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Some BMG ultrajoiner configurations require support for Link M/N ratios
> between 10.0 and 15.0. This range is not natively supported and requires
> a workaround.
>
> Wa_14021768792 enables this support by utilizing HDMI_EMP_DATA,
> CHICKEN_BITs, and extended bits in the LINK_N registers.
>
> Add the necessary logic to enable the workaround on applicable platforms.
>
> Bspec: 49266
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_wa.c | 18 ++++++++++++++++++
> .../gpu/drm/i915/display/intel_display_wa.h | 1 +
> 2 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index 399c08902413..541967168e97 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -5,11 +5,13 @@
>
> #include <drm/drm_print.h>
>
> +#include "i915_drv.h"
Please do not add new includes of i915_drv.h in display/.
> #include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_core.h"
> #include "intel_display_regs.h"
> #include "intel_display_wa.h"
> +#include "intel_step.h"
>
> static void gen11_display_wa_apply(struct intel_display *display)
> {
> @@ -52,6 +54,20 @@ static bool intel_display_needs_wa_16025573575(struct intel_display *display)
> return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002;
> }
>
> +/*
> + * Wa_14021768792:
> + * Fixes: Limitation of Link M/N ratio > 10 for specific Xe2HPD platforms.
> + * Workaround: Use HDMI_EMP_DATA, CHICKEN_BITs and extended bits in LINK_N registers to support
> + * LINK M/N ratios from > 10 but < 15.
> + */
> +static bool intel_display_needs_wa_14021768792(struct intel_display *display)
> +{
> + struct drm_i915_private *i915 = to_i915(display->drm);
Please do not add new uses of struct drm_i915_private under display/.
> +
> + return (DISPLAY_VER(display) == 14 && IS_DGFX(i915) &&
s/IS_DGFX(i915)/display->platform.dgfx/
> + IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER));
> +}
> +
> bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name)
> {
> switch (wa) {
> @@ -59,6 +75,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
> return intel_display_needs_wa_16023588340(display);
> case INTEL_DISPLAY_WA_16025573575:
> return intel_display_needs_wa_16025573575(display);
> + case INTEL_DISPLAY_WA_14021768792:
> + return intel_display_needs_wa_14021768792(display);
> default:
> drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);
> break;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
> index aedea4cfa3ce..8470f4ceea1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> @@ -24,6 +24,7 @@ bool intel_display_needs_wa_16023588340(struct intel_display *display);
> enum intel_display_wa {
> INTEL_DISPLAY_WA_16023588340,
> INTEL_DISPLAY_WA_16025573575,
> + INTEL_DISPLAY_WA_14021768792,
> };
>
> bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 7/9] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (5 preceding siblings ...)
2025-07-21 9:15 ` [PATCH 6/9] drm/i915/display_wa: Add support for Wa_14021768792 Ankit Nautiyal
@ 2025-07-21 9:15 ` Ankit Nautiyal
2025-07-21 9:15 ` [PATCH 8/9] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n " Ankit Nautiyal
` (6 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-07-21 9:15 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: jani.nikula, uma.shankar, ville.syrjala, Ankit Nautiyal
To support Link M/N ratio between 10.0 and 15.0, for some BMG ultrajoiner
cases we need Wa_14021768792.
To bypass the hardware limitation within the Timing Generator DDA (TGDDA),
we need to program the LINKM and LINKN registers as defined in
the WA. Along with this we also need relvant bits in HDMI_EMP_DATA and
CHICKEN_TRANS regs.
Add the bits for the WA and a new member 'bmg_bypass_m_n_ratio_limit' to
track if we need to bypass the Link M/N ratio limit in intel_link_m_n
structure.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 115 +++++++++++++++++-
.../gpu/drm/i915/display/intel_display_regs.h | 5 +
.../drm/i915/display/intel_display_types.h | 2 +
3 files changed, 116 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5232478613aa..bb50928762f6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -76,6 +76,7 @@
#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
+#include "intel_display_wa.h"
#include "intel_dmc.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
@@ -2573,6 +2574,20 @@ void intel_zero_m_n(struct intel_link_m_n *m_n)
m_n->tu = 1;
}
+static
+u8 bmg_get_link_n_ext(const struct intel_link_m_n *m_n)
+{
+ int m_n_ratio, m_n_frac;
+
+ if (!m_n->link_n)
+ return 0;
+
+ m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+ m_n_frac = m_n->link_m % m_n->link_n;
+
+ return m_n_ratio + (m_n_frac > 0 ? 1 : 0);
+}
+
void intel_set_m_n(struct intel_display *display,
const struct intel_link_m_n *m_n,
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
@@ -2584,7 +2599,9 @@ void intel_set_m_n(struct intel_display *display,
intel_de_write(display, data_n_reg, m_n->data_n);
intel_de_write(display, link_m_reg, m_n->link_m);
- if (DISPLAY_VER(display) >= 14)
+ if (DISPLAY_VER(display) >= 14 && m_n->bypass_m_n_ratio_limit)
+ link_n |= PIPE_LINK_N1_EXTENDED(bmg_get_link_n_ext(m_n));
+ else if (DISPLAY_VER(display) >= 14)
link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
else
link_n &= DATA_LINK_M_N_MASK;
@@ -2605,6 +2622,24 @@ bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
}
+static
+void bmg_bypass_m_n_limit_write(struct intel_crtc *crtc,
+ enum transcoder transcoder,
+ const struct intel_link_m_n *m_n)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ int m_n_frac;
+ enum pipe pipe = crtc->pipe;
+
+ if (!m_n->link_n)
+ return;
+
+ m_n_frac = m_n->link_m % m_n->link_n;
+
+ intel_de_rmw(display, CHICKEN_TRANS(display, transcoder), 0, BMG_DP_BYPASS_M_N_LIMIT);
+ intel_de_write(display, HDMI_EMP_DATA(pipe), m_n_frac);
+}
+
void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
enum transcoder transcoder,
const struct intel_link_m_n *m_n)
@@ -2622,6 +2657,9 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
intel_set_m_n(display, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
+
+ if (m_n->bypass_m_n_ratio_limit)
+ bmg_bypass_m_n_limit_write(crtc, transcoder, m_n);
}
void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
@@ -2638,6 +2676,9 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
PIPE_DATA_N2(display, transcoder),
PIPE_LINK_M2(display, transcoder),
PIPE_LINK_N2(display, transcoder));
+
+ if (m_n->bypass_m_n_ratio_limit)
+ bmg_bypass_m_n_limit_write(crtc, transcoder, m_n);
}
static bool
@@ -3331,22 +3372,64 @@ void intel_get_m_n(struct intel_display *display,
m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK;
m_n->link_n = intel_de_read(display, link_n_reg);
- if (DISPLAY_VER(display) >= 14)
+ if (DISPLAY_VER(display) >= 14) {
+ u8 link_n_ext = REG_FIELD_GET(PIPE_LINK_N1_EXTENDED_MASK, m_n->link_n);
+
m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
- else
+ drm_WARN_ON(display->drm, link_n_ext && link_n_ext != bmg_get_link_n_ext(m_n));
+ } else {
m_n->link_n &= DATA_LINK_M_N_MASK;
+ }
m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK;
m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK;
m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
}
+static
+void bmg_bypass_m_n_limit_read(struct intel_crtc *crtc,
+ enum transcoder transcoder,
+ struct intel_link_m_n *m_n)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+ u32 chicken_trans, m_n_frac;
+
+ chicken_trans = intel_de_read(display, CHICKEN_TRANS(display, transcoder));
+ m_n_frac = intel_de_read(display, HDMI_EMP_DATA(pipe));
+
+ if (!m_n->link_n)
+ return;
+
+ if ((chicken_trans & BMG_DP_BYPASS_M_N_LIMIT) &&
+ m_n_frac == (m_n->link_m % m_n->link_n))
+ m_n->bypass_m_n_ratio_limit = true;
+}
+
+static
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+ int m_n_ratio,
+ enum pipe pipe)
+{
+ if (m_n_ratio > 15)
+ return false;
+
+ if (pipe != PIPE_A)
+ return false;
+
+ if (!intel_display_wa(display, 14021768792))
+ return false;
+
+ return true;
+}
+
void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
enum transcoder transcoder,
struct intel_link_m_n *m_n)
{
struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
+ int m_n_ratio;
if (DISPLAY_VER(display) >= 5)
intel_get_m_n(display, m_n,
@@ -3358,6 +3441,14 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
intel_get_m_n(display, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
+ if (!m_n->link_n)
+ return;
+
+ m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+ if (intel_display_can_bypass_m_n_limit(display, m_n_ratio, pipe))
+ bmg_bypass_m_n_limit_read(crtc, transcoder, m_n);
+
}
void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
@@ -3365,6 +3456,8 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+ int m_n_ratio;
if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
return;
@@ -3374,6 +3467,14 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
PIPE_DATA_N2(display, transcoder),
PIPE_LINK_M2(display, transcoder),
PIPE_LINK_N2(display, transcoder));
+
+ if (!m_n->link_n)
+ return;
+
+ m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+ if (intel_display_can_bypass_m_n_limit(display, m_n_ratio, pipe))
+ bmg_bypass_m_n_limit_read(crtc, transcoder, m_n);
}
static bool ilk_get_pipe_config(struct intel_crtc *crtc,
@@ -5106,18 +5207,20 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
if (!intel_compare_link_m_n(¤t_config->name, \
&pipe_config->name)) { \
pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
- "(expected tu %i data %i/%i link %i/%i, " \
- "found tu %i, data %i/%i link %i/%i)", \
+ "(expected tu %i data %i/%i link %i/%i bypass_m_n_ratio_limit %s, " \
+ "found tu %i, data %i/%i link %i/%i bypass_m_n_ratio_limit %s)", \
current_config->name.tu, \
current_config->name.data_m, \
current_config->name.data_n, \
current_config->name.link_m, \
current_config->name.link_n, \
+ str_yes_no(current_config->name.bypass_m_n_ratio_limit), \
pipe_config->name.tu, \
pipe_config->name.data_m, \
pipe_config->name.data_n, \
pipe_config->name.link_m, \
- pipe_config->name.link_n); \
+ pipe_config->name.link_n, \
+ str_yes_no(pipe_config->name.bypass_m_n_ratio_limit)); \
ret = false; \
} \
} while (0)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9248561aec5f..ee7eb19920b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -411,6 +411,10 @@
#define _TRANS_MULT_B 0x6102c
#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
+#define _HDMI_EMP_DATA_A 0x600d8
+#define _HDMI_EMP_DATA_B 0x610d8
+#define HDMI_EMP_DATA(pipe) _MMIO_PIPE(pipe, _HDMI_EMP_DATA_A, _HDMI_EMP_DATA_B)
+
/* Hotplug control (945+ only) */
#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
#define PORTB_HOTPLUG_INT_EN (1 << 29)
@@ -1483,6 +1487,7 @@
#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
#define DP_FEC_BS_JITTER_WA REG_BIT(15)
#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
+#define BMG_DP_BYPASS_M_N_LIMIT REG_BIT(11)
#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8f8019d40d77..55e0e8065af3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -935,6 +935,8 @@ struct intel_link_m_n {
u32 data_n;
u32 link_m;
u32 link_n;
+ /* Wa_14021768792 for linkm/n ratio > 10 */
+ bool bypass_m_n_ratio_limit;
};
struct intel_csc_matrix {
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 8/9] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (6 preceding siblings ...)
2025-07-21 9:15 ` [PATCH 7/9] drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10 Ankit Nautiyal
@ 2025-07-21 9:15 ` Ankit Nautiyal
2025-07-21 9:15 ` [PATCH 9/9] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass Ankit Nautiyal
` (5 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-07-21 9:15 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: jani.nikula, uma.shankar, ville.syrjala, Ankit Nautiyal
Handle the bypass logic for the M/N ratio limit for DP.
Calculate the M/N ratio, check if it can bypass the limit, and set the
appropriate flags for the workaround.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
drivers/gpu/drm/i915/display/intel_display.h | 2 ++
drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bb50928762f6..ee15289221d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3406,7 +3406,6 @@ void bmg_bypass_m_n_limit_read(struct intel_crtc *crtc,
m_n->bypass_m_n_ratio_limit = true;
}
-static
bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
int m_n_ratio,
enum pipe pipe)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index bfa3db219b9c..a7134dd15687 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -562,5 +562,7 @@ int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state);
void intel_display_get_link_m_n(u32 *link_m, u32 *link_n,
u32 pixel_clock,
u32 link_clock);
+bool intel_display_can_bypass_m_n_limit(struct intel_display *display,
+ int m_n_ratio, enum pipe pipe);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a1114d1059dd..a5ab7d694dbe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3012,10 +3012,19 @@ void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
- if (m_n_ratio > intel_dp_get_max_m_n_ratio())
+ if (m_n_ratio > intel_dp_get_max_m_n_ratio()) {
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+
+ if (intel_display_can_bypass_m_n_limit(display, m_n_ratio, pipe)) {
+ m_n->bypass_m_n_ratio_limit = true;
+ drm_dbg_kms(display->drm, "Bypassing Link_m/Link_n ratio limit\n");
+ return;
+ }
drm_WARN(display->drm, 1,
"Link M/N ratio (%d) exceeds max allowed (%d)\n",
m_n_ratio, intel_dp_get_max_m_n_ratio());
+ }
}
static void
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH 9/9] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (7 preceding siblings ...)
2025-07-21 9:15 ` [PATCH 8/9] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n " Ankit Nautiyal
@ 2025-07-21 9:15 ` Ankit Nautiyal
2025-07-21 9:34 ` ✗ CI.checkpatch: warning for Implement Wa_14021768792 to bypass m_n ratio limit (rev5) Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Ankit Nautiyal @ 2025-07-21 9:15 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: jani.nikula, uma.shankar, ville.syrjala, Ankit Nautiyal
On BMG platforms, the standard M/N ratio limit of 10 can be bypassed
under specific conditions, as permitted by hardware capabilities.
Modify the helper intel_dp_can_support_m_n() to account for this by
checking whether the platform supports bypassing the limit.
During mode_valid phase, the check assumes that PIPE_A will be used to
allow the mode, where M/N ratio is with int the limits for the workaround.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp.h | 4 ++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++--
3 files changed, 32 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a5ab7d694dbe..fde373a3606a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1414,10 +1414,13 @@ intel_dp_get_max_m_n_ratio(void)
}
bool
-intel_dp_can_support_m_n(int pixel_clock,
- int link_rate)
+intel_dp_can_support_m_n(struct intel_display *display,
+ struct intel_crtc_state *crtc_state,
+ int pixel_clock, int link_rate)
{
+ struct intel_crtc *crtc;
int max_m_n_ratio = intel_dp_get_max_m_n_ratio();
+ enum pipe pipe;
u32 link_m, link_n;
int m_n_ratio;
@@ -1426,7 +1429,20 @@ intel_dp_can_support_m_n(int pixel_clock,
m_n_ratio = DIV_ROUND_UP(link_m, link_n);
- return m_n_ratio <= max_m_n_ratio;
+ if (m_n_ratio <= max_m_n_ratio)
+ return true;
+
+ if (crtc_state) {
+ crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ pipe = crtc->pipe;
+ } else {
+ pipe = PIPE_A;
+ }
+
+ if (intel_display_can_bypass_m_n_limit(display, m_n_ratio, pipe))
+ return true;
+
+ return false;
}
static enum drm_mode_status
@@ -1540,7 +1556,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
if (status != MODE_OK)
return status;
- if (!intel_dp_can_support_m_n(target_clock, max_rate))
+ if (!intel_dp_can_support_m_n(display, NULL, target_clock, max_rate))
return MODE_CLOCK_HIGH;
return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
@@ -1798,6 +1814,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
const struct drm_connector_state *conn_state,
const struct link_config_limits *limits)
{
+ struct intel_display *display = to_intel_display(pipe_config);
int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
int mode_rate, link_rate, link_avail;
@@ -1814,7 +1831,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
link_rate > limits->max_rate)
continue;
- if (!intel_dp_can_support_m_n(clock, link_rate))
+ if (!intel_dp_can_support_m_n(display, pipe_config, clock, link_rate))
continue;
for (lane_count = limits->min_lane_count;
@@ -2001,6 +2018,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
int dsc_bpp_x16,
int timeslots)
{
+ struct intel_display *display = to_intel_display(pipe_config);
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
int link_rate, lane_count;
int i;
@@ -2010,7 +2028,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
if (link_rate < limits->min_rate || link_rate > limits->max_rate)
continue;
- if (!intel_dp_can_support_m_n(adjusted_mode->clock,
+ if (!intel_dp_can_support_m_n(display, pipe_config,
+ adjusted_mode->clock,
link_rate))
continue;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index a197eb0a7fc6..7b7b950aeb61 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -215,7 +215,9 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
-bool intel_dp_can_support_m_n(int pixel_clock, int link_rate);
+bool intel_dp_can_support_m_n(struct intel_display *display,
+ struct intel_crtc_state *crtc_state,
+ int pixel_clock, int link_rate);
void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
struct intel_link_m_n *m_n);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 45b72a2c8588..a06901ad7a9f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -447,12 +447,14 @@ static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
struct drm_connector_state *conn_state,
const struct link_config_limits *limits)
{
+ struct intel_display *display = to_intel_display(crtc_state);
crtc_state->lane_count = limits->max_lane_count;
crtc_state->port_clock = limits->max_rate;
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- if (!intel_dp_can_support_m_n(adjusted_mode->clock, crtc_state->port_clock))
+ if (!intel_dp_can_support_m_n(display, crtc_state, adjusted_mode->clock,
+ crtc_state->port_clock))
return -EINVAL;
/*
@@ -1560,7 +1562,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
return 0;
}
- if (!intel_dp_can_support_m_n(mode->clock, max_rate)) {
+ if (!intel_dp_can_support_m_n(display, NULL, mode->clock, max_rate)) {
*status = MODE_CLOCK_HIGH;
return 0;
}
--
2.45.2
^ permalink raw reply related [flat|nested] 21+ messages in thread* ✗ CI.checkpatch: warning for Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (8 preceding siblings ...)
2025-07-21 9:15 ` [PATCH 9/9] drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass Ankit Nautiyal
@ 2025-07-21 9:34 ` Patchwork
2025-07-21 9:35 ` ✓ CI.KUnit: success " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-07-21 9:34 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
URL : https://patchwork.freedesktop.org/series/138256/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
63535c743231a7497a612c53f6edbb8a7d14412d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit eb191f4ee62393387162b4998fbe8009ee311435
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Date: Mon Jul 21 14:45:29 2025 +0530
drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass
On BMG platforms, the standard M/N ratio limit of 10 can be bypassed
under specific conditions, as permitted by hardware capabilities.
Modify the helper intel_dp_can_support_m_n() to account for this by
checking whether the platform supports bypassing the limit.
During mode_valid phase, the check assumes that PIPE_A will be used to
allow the mode, where M/N ratio is with int the limits for the workaround.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch 62dc6f672f79c0b74acd61dd86936f8e5e6fdb0d drm-intel
72acce8a6eb1 drm/i915: Add helper to compute link M/N ratio for reuse
a9f0a2622ec7 drm/i915/dp: Limit m/n ratio to 10 for DP SST
edf67a68d527 drm/i915/dp_mst: Limit m/n ratio to 10 for MST
6ceb9bf2674f drm/i915/dp: Add M/N ratio check with warning for DP link config
b9b0b06a2be9 drm/i915/display: Add bits for link_n_exended for DISPLAY >= 14
6d47196507ac drm/i915/display_wa: Add support for Wa_14021768792
4c2c735dbc7f drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
-:223: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#223: FILE: drivers/gpu/drm/i915/display/intel_display.c:5211:
+ "found tu %i, data %i/%i link %i/%i bypass_m_n_ratio_limit %s)", \
total: 0 errors, 1 warnings, 0 checks, 229 lines checked
59ea772a0beb drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10
eb191f4ee623 drm/i915/dp: Extend intel_dp_can_support_m_n() for BMG M/N bypass
^ permalink raw reply [flat|nested] 21+ messages in thread* ✓ CI.KUnit: success for Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (9 preceding siblings ...)
2025-07-21 9:34 ` ✗ CI.checkpatch: warning for Implement Wa_14021768792 to bypass m_n ratio limit (rev5) Patchwork
@ 2025-07-21 9:35 ` Patchwork
2025-07-21 9:50 ` ✗ CI.checksparse: warning " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-07-21 9:35 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
URL : https://patchwork.freedesktop.org/series/138256/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[09:34:16] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:34:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:34:47] Starting KUnit Kernel (1/1)...
[09:34:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:34:47] ================== guc_buf (11 subtests) ===================
[09:34:47] [PASSED] test_smallest
[09:34:47] [PASSED] test_largest
[09:34:47] [PASSED] test_granular
[09:34:47] [PASSED] test_unique
[09:34:47] [PASSED] test_overlap
[09:34:47] [PASSED] test_reusable
[09:34:47] [PASSED] test_too_big
[09:34:47] [PASSED] test_flush
[09:34:47] [PASSED] test_lookup
[09:34:47] [PASSED] test_data
[09:34:47] [PASSED] test_class
[09:34:47] ===================== [PASSED] guc_buf =====================
[09:34:47] =================== guc_dbm (7 subtests) ===================
[09:34:47] [PASSED] test_empty
[09:34:47] [PASSED] test_default
[09:34:47] ======================== test_size ========================
[09:34:47] [PASSED] 4
[09:34:47] [PASSED] 8
[09:34:47] [PASSED] 32
[09:34:47] [PASSED] 256
[09:34:47] ==================== [PASSED] test_size ====================
[09:34:47] ======================= test_reuse ========================
[09:34:47] [PASSED] 4
[09:34:47] [PASSED] 8
[09:34:47] [PASSED] 32
[09:34:47] [PASSED] 256
[09:34:47] =================== [PASSED] test_reuse ====================
[09:34:47] =================== test_range_overlap ====================
[09:34:47] [PASSED] 4
[09:34:47] [PASSED] 8
[09:34:47] [PASSED] 32
[09:34:47] [PASSED] 256
[09:34:47] =============== [PASSED] test_range_overlap ================
[09:34:47] =================== test_range_compact ====================
[09:34:47] [PASSED] 4
[09:34:47] [PASSED] 8
[09:34:47] [PASSED] 32
[09:34:47] [PASSED] 256
[09:34:47] =============== [PASSED] test_range_compact ================
[09:34:47] ==================== test_range_spare =====================
[09:34:47] [PASSED] 4
[09:34:47] [PASSED] 8
[09:34:47] [PASSED] 32
[09:34:47] [PASSED] 256
[09:34:47] ================ [PASSED] test_range_spare =================
[09:34:47] ===================== [PASSED] guc_dbm =====================
[09:34:47] =================== guc_idm (6 subtests) ===================
[09:34:47] [PASSED] bad_init
[09:34:47] [PASSED] no_init
[09:34:47] [PASSED] init_fini
[09:34:47] [PASSED] check_used
[09:34:47] [PASSED] check_quota
[09:34:47] [PASSED] check_all
[09:34:47] ===================== [PASSED] guc_idm =====================
[09:34:47] ================== no_relay (3 subtests) ===================
[09:34:47] [PASSED] xe_drops_guc2pf_if_not_ready
[09:34:47] [PASSED] xe_drops_guc2vf_if_not_ready
[09:34:47] [PASSED] xe_rejects_send_if_not_ready
[09:34:47] ==================== [PASSED] no_relay =====================
[09:34:47] ================== pf_relay (14 subtests) ==================
[09:34:47] [PASSED] pf_rejects_guc2pf_too_short
[09:34:47] [PASSED] pf_rejects_guc2pf_too_long
[09:34:47] [PASSED] pf_rejects_guc2pf_no_payload
[09:34:47] [PASSED] pf_fails_no_payload
[09:34:47] [PASSED] pf_fails_bad_origin
[09:34:47] [PASSED] pf_fails_bad_type
[09:34:47] [PASSED] pf_txn_reports_error
[09:34:47] [PASSED] pf_txn_sends_pf2guc
[09:34:47] [PASSED] pf_sends_pf2guc
[09:34:47] [SKIPPED] pf_loopback_nop
[09:34:47] [SKIPPED] pf_loopback_echo
[09:34:47] [SKIPPED] pf_loopback_fail
[09:34:47] [SKIPPED] pf_loopback_busy
[09:34:47] [SKIPPED] pf_loopback_retry
[09:34:47] ==================== [PASSED] pf_relay =====================
[09:34:47] ================== vf_relay (3 subtests) ===================
[09:34:47] [PASSED] vf_rejects_guc2vf_too_short
[09:34:47] [PASSED] vf_rejects_guc2vf_too_long
[09:34:47] [PASSED] vf_rejects_guc2vf_no_payload
[09:34:47] ==================== [PASSED] vf_relay =====================
[09:34:47] ===================== lmtt (1 subtest) =====================
[09:34:47] ======================== test_ops =========================
[09:34:47] [PASSED] 2-level
[09:34:47] [PASSED] multi-level
[09:34:47] ==================== [PASSED] test_ops =====================
[09:34:47] ====================== [PASSED] lmtt =======================
[09:34:47] ================= pf_service (11 subtests) =================
[09:34:47] [PASSED] pf_negotiate_any
[09:34:47] [PASSED] pf_negotiate_base_match
[09:34:47] [PASSED] pf_negotiate_base_newer
[09:34:47] [PASSED] pf_negotiate_base_next
[09:34:47] [SKIPPED] pf_negotiate_base_older
[09:34:47] [PASSED] pf_negotiate_base_prev
[09:34:47] [PASSED] pf_negotiate_latest_match
[09:34:47] [PASSED] pf_negotiate_latest_newer
[09:34:47] [PASSED] pf_negotiate_latest_next
[09:34:47] [SKIPPED] pf_negotiate_latest_older
[09:34:47] [SKIPPED] pf_negotiate_latest_prev
[09:34:47] =================== [PASSED] pf_service ====================
[09:34:47] =================== xe_mocs (2 subtests) ===================
[09:34:47] ================ xe_live_mocs_kernel_kunit ================
[09:34:47] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[09:34:47] ================ xe_live_mocs_reset_kunit =================
[09:34:47] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[09:34:47] ==================== [SKIPPED] xe_mocs =====================
[09:34:47] ================= xe_migrate (2 subtests) ==================
[09:34:47] ================= xe_migrate_sanity_kunit =================
[09:34:47] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[09:34:47] ================== xe_validate_ccs_kunit ==================
[09:34:47] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[09:34:47] =================== [SKIPPED] xe_migrate ===================
[09:34:47] ================== xe_dma_buf (1 subtest) ==================
[09:34:47] ==================== xe_dma_buf_kunit =====================
[09:34:47] ================ [SKIPPED] xe_dma_buf_kunit ================
[09:34:47] =================== [SKIPPED] xe_dma_buf ===================
[09:34:47] ================= xe_bo_shrink (1 subtest) =================
[09:34:47] =================== xe_bo_shrink_kunit ====================
[09:34:47] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[09:34:47] ================== [SKIPPED] xe_bo_shrink ==================
[09:34:47] ==================== xe_bo (2 subtests) ====================
[09:34:47] ================== xe_ccs_migrate_kunit ===================
[09:34:47] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[09:34:47] ==================== xe_bo_evict_kunit ====================
[09:34:47] =============== [SKIPPED] xe_bo_evict_kunit ================
[09:34:47] ===================== [SKIPPED] xe_bo ======================
[09:34:47] ==================== args (11 subtests) ====================
[09:34:47] [PASSED] count_args_test
[09:34:47] [PASSED] call_args_example
[09:34:47] [PASSED] call_args_test
[09:34:47] [PASSED] drop_first_arg_example
[09:34:47] [PASSED] drop_first_arg_test
[09:34:47] [PASSED] first_arg_example
[09:34:47] [PASSED] first_arg_test
[09:34:47] [PASSED] last_arg_example
[09:34:47] [PASSED] last_arg_test
[09:34:47] [PASSED] pick_arg_example
[09:34:47] [PASSED] sep_comma_example
[09:34:47] ====================== [PASSED] args =======================
[09:34:47] =================== xe_pci (3 subtests) ====================
[09:34:47] ==================== check_graphics_ip ====================
[09:34:47] [PASSED] 12.70 Xe_LPG
[09:34:47] [PASSED] 12.71 Xe_LPG
[09:34:47] [PASSED] 12.74 Xe_LPG+
[09:34:47] [PASSED] 20.01 Xe2_HPG
[09:34:47] [PASSED] 20.02 Xe2_HPG
[09:34:47] [PASSED] 20.04 Xe2_LPG
[09:34:47] [PASSED] 30.00 Xe3_LPG
[09:34:47] [PASSED] 30.01 Xe3_LPG
[09:34:47] [PASSED] 30.03 Xe3_LPG
[09:34:47] ================ [PASSED] check_graphics_ip ================
[09:34:47] ===================== check_media_ip ======================
[09:34:47] [PASSED] 13.00 Xe_LPM+
[09:34:47] [PASSED] 13.01 Xe2_HPM
[09:34:47] [PASSED] 20.00 Xe2_LPM
[09:34:47] [PASSED] 30.00 Xe3_LPM
[09:34:47] [PASSED] 30.02 Xe3_LPM
[09:34:47] ================= [PASSED] check_media_ip ==================
[09:34:47] ================= check_platform_gt_count =================
[09:34:47] [PASSED] 0x9A60 (TIGERLAKE)
[09:34:47] [PASSED] 0x9A68 (TIGERLAKE)
[09:34:47] [PASSED] 0x9A70 (TIGERLAKE)
[09:34:47] [PASSED] 0x9A40 (TIGERLAKE)
[09:34:47] [PASSED] 0x9A49 (TIGERLAKE)
[09:34:47] [PASSED] 0x9A59 (TIGERLAKE)
[09:34:47] [PASSED] 0x9A78 (TIGERLAKE)
[09:34:47] [PASSED] 0x9AC0 (TIGERLAKE)
[09:34:47] [PASSED] 0x9AC9 (TIGERLAKE)
[09:34:47] [PASSED] 0x9AD9 (TIGERLAKE)
[09:34:47] [PASSED] 0x9AF8 (TIGERLAKE)
[09:34:47] [PASSED] 0x4C80 (ROCKETLAKE)
[09:34:47] [PASSED] 0x4C8A (ROCKETLAKE)
[09:34:47] [PASSED] 0x4C8B (ROCKETLAKE)
[09:34:47] [PASSED] 0x4C8C (ROCKETLAKE)
[09:34:47] [PASSED] 0x4C90 (ROCKETLAKE)
[09:34:47] [PASSED] 0x4C9A (ROCKETLAKE)
[09:34:47] [PASSED] 0x4680 (ALDERLAKE_S)
[09:34:47] [PASSED] 0x4682 (ALDERLAKE_S)
[09:34:47] [PASSED] 0x4688 (ALDERLAKE_S)
[09:34:47] [PASSED] 0x468A (ALDERLAKE_S)
[09:34:47] [PASSED] 0x468B (ALDERLAKE_S)
[09:34:47] [PASSED] 0x4690 (ALDERLAKE_S)
[09:34:47] [PASSED] 0x4692 (ALDERLAKE_S)
[09:34:47] [PASSED] 0x4693 (ALDERLAKE_S)
[09:34:47] [PASSED] 0x46A0 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46A1 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46A2 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46A3 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46A6 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46A8 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46AA (ALDERLAKE_P)
[09:34:47] [PASSED] 0x462A (ALDERLAKE_P)
[09:34:47] [PASSED] 0x4626 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x4628 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46B0 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46B1 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46B2 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46B3 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46C0 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46C1 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46C2 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46C3 (ALDERLAKE_P)
[09:34:47] [PASSED] 0x46D0 (ALDERLAKE_N)
[09:34:47] [PASSED] 0x46D1 (ALDERLAKE_N)
[09:34:47] [PASSED] 0x46D2 (ALDERLAKE_N)
[09:34:47] [PASSED] 0x46D3 (ALDERLAKE_N)
[09:34:47] [PASSED] 0x46D4 (ALDERLAKE_N)
[09:34:47] [PASSED] 0xA721 (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA7A1 (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA7A9 (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA7AC (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA7AD (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA720 (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA7A0 (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA7A8 (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA7AA (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA7AB (ALDERLAKE_P)
[09:34:47] [PASSED] 0xA780 (ALDERLAKE_S)
[09:34:47] [PASSED] 0xA781 (ALDERLAKE_S)
[09:34:47] [PASSED] 0xA782 (ALDERLAKE_S)
[09:34:47] [PASSED] 0xA783 (ALDERLAKE_S)
[09:34:47] [PASSED] 0xA788 (ALDERLAKE_S)
[09:34:47] [PASSED] 0xA789 (ALDERLAKE_S)
[09:34:47] [PASSED] 0xA78A (ALDERLAKE_S)
[09:34:47] [PASSED] 0xA78B (ALDERLAKE_S)
[09:34:47] [PASSED] 0x4905 (DG1)
[09:34:47] [PASSED] 0x4906 (DG1)
[09:34:47] [PASSED] 0x4907 (DG1)
[09:34:47] [PASSED] 0x4908 (DG1)
[09:34:47] [PASSED] 0x4909 (DG1)
[09:34:47] [PASSED] 0x56C0 (DG2)
[09:34:47] [PASSED] 0x56C2 (DG2)
[09:34:47] [PASSED] 0x56C1 (DG2)
[09:34:47] [PASSED] 0x7D51 (METEORLAKE)
[09:34:47] [PASSED] 0x7DD1 (METEORLAKE)
[09:34:47] [PASSED] 0x7D41 (METEORLAKE)
[09:34:47] [PASSED] 0x7D67 (METEORLAKE)
[09:34:47] [PASSED] 0xB640 (METEORLAKE)
[09:34:47] [PASSED] 0x56A0 (DG2)
[09:34:47] [PASSED] 0x56A1 (DG2)
[09:34:47] [PASSED] 0x56A2 (DG2)
[09:34:47] [PASSED] 0x56BE (DG2)
[09:34:47] [PASSED] 0x56BF (DG2)
[09:34:47] [PASSED] 0x5690 (DG2)
[09:34:47] [PASSED] 0x5691 (DG2)
[09:34:47] [PASSED] 0x5692 (DG2)
[09:34:47] [PASSED] 0x56A5 (DG2)
[09:34:47] [PASSED] 0x56A6 (DG2)
[09:34:47] [PASSED] 0x56B0 (DG2)
[09:34:47] [PASSED] 0x56B1 (DG2)
[09:34:47] [PASSED] 0x56BA (DG2)
[09:34:47] [PASSED] 0x56BB (DG2)
[09:34:47] [PASSED] 0x56BC (DG2)
[09:34:47] [PASSED] 0x56BD (DG2)
[09:34:47] [PASSED] 0x5693 (DG2)
[09:34:47] [PASSED] 0x5694 (DG2)
[09:34:47] [PASSED] 0x5695 (DG2)
[09:34:47] [PASSED] 0x56A3 (DG2)
[09:34:47] [PASSED] 0x56A4 (DG2)
[09:34:47] [PASSED] 0x56B2 (DG2)
[09:34:47] [PASSED] 0x56B3 (DG2)
[09:34:47] [PASSED] 0x5696 (DG2)
[09:34:47] [PASSED] 0x5697 (DG2)
[09:34:47] [PASSED] 0xB69 (PVC)
[09:34:47] [PASSED] 0xB6E (PVC)
[09:34:47] [PASSED] 0xBD4 (PVC)
[09:34:47] [PASSED] 0xBD5 (PVC)
[09:34:47] [PASSED] 0xBD6 (PVC)
[09:34:47] [PASSED] 0xBD7 (PVC)
[09:34:47] [PASSED] 0xBD8 (PVC)
[09:34:47] [PASSED] 0xBD9 (PVC)
[09:34:47] [PASSED] 0xBDA (PVC)
[09:34:47] [PASSED] 0xBDB (PVC)
[09:34:47] [PASSED] 0xBE0 (PVC)
[09:34:47] [PASSED] 0xBE1 (PVC)
[09:34:47] [PASSED] 0xBE5 (PVC)
[09:34:47] [PASSED] 0x7D40 (METEORLAKE)
[09:34:47] [PASSED] 0x7D45 (METEORLAKE)
[09:34:47] [PASSED] 0x7D55 (METEORLAKE)
[09:34:47] [PASSED] 0x7D60 (METEORLAKE)
[09:34:47] [PASSED] 0x7DD5 (METEORLAKE)
[09:34:47] [PASSED] 0x6420 (LUNARLAKE)
[09:34:47] [PASSED] 0x64A0 (LUNARLAKE)
[09:34:47] [PASSED] 0x64B0 (LUNARLAKE)
[09:34:47] [PASSED] 0xE202 (BATTLEMAGE)
[09:34:47] [PASSED] 0xE209 (BATTLEMAGE)
[09:34:47] [PASSED] 0xE20B (BATTLEMAGE)
[09:34:47] [PASSED] 0xE20C (BATTLEMAGE)
[09:34:47] [PASSED] 0xE20D (BATTLEMAGE)
[09:34:47] [PASSED] 0xE210 (BATTLEMAGE)
[09:34:47] [PASSED] 0xE211 (BATTLEMAGE)
[09:34:47] [PASSED] 0xE212 (BATTLEMAGE)
[09:34:47] [PASSED] 0xE216 (BATTLEMAGE)
[09:34:47] [PASSED] 0xE220 (BATTLEMAGE)
[09:34:47] [PASSED] 0xE221 (BATTLEMAGE)
[09:34:47] [PASSED] 0xE222 (BATTLEMAGE)
[09:34:47] [PASSED] 0xE223 (BATTLEMAGE)
[09:34:47] [PASSED] 0xB080 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB081 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB082 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB083 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB084 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB085 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB086 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB087 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB08F (PANTHERLAKE)
[09:34:47] [PASSED] 0xB090 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB0A0 (PANTHERLAKE)
[09:34:47] [PASSED] 0xB0B0 (PANTHERLAKE)
[09:34:47] [PASSED] 0xFD80 (PANTHERLAKE)
[09:34:47] [PASSED] 0xFD81 (PANTHERLAKE)
[09:34:47] ============= [PASSED] check_platform_gt_count =============
[09:34:47] ===================== [PASSED] xe_pci ======================
[09:34:47] =================== xe_rtp (2 subtests) ====================
[09:34:47] =============== xe_rtp_process_to_sr_tests ================
[09:34:47] [PASSED] coalesce-same-reg
[09:34:47] [PASSED] no-match-no-add
[09:34:47] [PASSED] match-or
[09:34:47] [PASSED] match-or-xfail
[09:34:47] [PASSED] no-match-no-add-multiple-rules
[09:34:47] [PASSED] two-regs-two-entries
[09:34:47] [PASSED] clr-one-set-other
[09:34:47] [PASSED] set-field
[09:34:47] [PASSED] conflict-duplicate
[09:34:47] [PASSED] conflict-not-disjoint
[09:34:47] [PASSED] conflict-reg-type
[09:34:47] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[09:34:47] ================== xe_rtp_process_tests ===================
[09:34:47] [PASSED] active1
[09:34:47] [PASSED] active2
[09:34:47] [PASSED] active-inactive
[09:34:47] [PASSED] inactive-active
[09:34:47] [PASSED] inactive-1st_or_active-inactive
[09:34:47] [PASSED] inactive-2nd_or_active-inactive
[09:34:47] [PASSED] inactive-last_or_active-inactive
[09:34:47] [PASSED] inactive-no_or_active-inactive
[09:34:47] ============== [PASSED] xe_rtp_process_tests ===============
[09:34:47] ===================== [PASSED] xe_rtp ======================
[09:34:47] ==================== xe_wa (1 subtest) =====================
[09:34:47] ======================== xe_wa_gt =========================
[09:34:47] [PASSED] TIGERLAKE (B0)
[09:34:47] [PASSED] DG1 (A0)
[09:34:47] [PASSED] DG1 (B0)
[09:34:47] [PASSED] ALDERLAKE_S (A0)
[09:34:47] [PASSED] ALDERLAKE_S (B0)
[09:34:47] [PASSED] ALDERLAKE_S (C0)
[09:34:47] [PASSED] ALDERLAKE_S (D0)
[09:34:47] [PASSED] ALDERLAKE_P (A0)
[09:34:47] [PASSED] ALDERLAKE_P (B0)
[09:34:47] [PASSED] ALDERLAKE_P (C0)
[09:34:47] [PASSED] ALDERLAKE_S_RPLS (D0)
[09:34:47] [PASSED] ALDERLAKE_P_RPLU (E0)
[09:34:47] [PASSED] DG2_G10 (C0)
[09:34:47] [PASSED] DG2_G11 (B1)
[09:34:47] [PASSED] DG2_G12 (A1)
[09:34:47] [PASSED] METEORLAKE (g:A0, m:A0)
[09:34:47] [PASSED] METEORLAKE (g:A0, m:A0)
[09:34:47] [PASSED] METEORLAKE (g:A0, m:A0)
[09:34:47] [PASSED] LUNARLAKE (g:A0, m:A0)
[09:34:47] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[09:34:47] [PASSED] BATTLEMAGE (g:A0, m:A1)
[09:34:47] ==================== [PASSED] xe_wa_gt =====================
[09:34:47] ====================== [PASSED] xe_wa ======================
[09:34:47] ============================================================
[09:34:47] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[09:34:47] Elapsed time: 31.745s total, 4.202s configuring, 27.176s building, 0.322s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[09:34:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:34:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:35:11] Starting KUnit Kernel (1/1)...
[09:35:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:35:11] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[09:35:11] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[09:35:11] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[09:35:11] =========== drm_validate_clone_mode (2 subtests) ===========
[09:35:11] ============== drm_test_check_in_clone_mode ===============
[09:35:11] [PASSED] in_clone_mode
[09:35:11] [PASSED] not_in_clone_mode
[09:35:11] ========== [PASSED] drm_test_check_in_clone_mode ===========
[09:35:11] =============== drm_test_check_valid_clones ===============
[09:35:11] [PASSED] not_in_clone_mode
[09:35:11] [PASSED] valid_clone
[09:35:11] [PASSED] invalid_clone
[09:35:11] =========== [PASSED] drm_test_check_valid_clones ===========
[09:35:11] ============= [PASSED] drm_validate_clone_mode =============
[09:35:11] ============= drm_validate_modeset (1 subtest) =============
[09:35:11] [PASSED] drm_test_check_connector_changed_modeset
[09:35:11] ============== [PASSED] drm_validate_modeset ===============
[09:35:11] ====== drm_test_bridge_get_current_state (2 subtests) ======
[09:35:11] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[09:35:11] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[09:35:11] ======== [PASSED] drm_test_bridge_get_current_state ========
[09:35:11] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[09:35:11] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[09:35:11] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[09:35:11] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[09:35:11] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[09:35:11] ============== drm_bridge_alloc (2 subtests) ===============
[09:35:11] [PASSED] drm_test_drm_bridge_alloc_basic
[09:35:11] [PASSED] drm_test_drm_bridge_alloc_get_put
[09:35:11] ================ [PASSED] drm_bridge_alloc =================
[09:35:11] ================== drm_buddy (7 subtests) ==================
[09:35:11] [PASSED] drm_test_buddy_alloc_limit
[09:35:11] [PASSED] drm_test_buddy_alloc_optimistic
[09:35:11] [PASSED] drm_test_buddy_alloc_pessimistic
[09:35:11] [PASSED] drm_test_buddy_alloc_pathological
[09:35:11] [PASSED] drm_test_buddy_alloc_contiguous
[09:35:11] [PASSED] drm_test_buddy_alloc_clear
[09:35:11] [PASSED] drm_test_buddy_alloc_range_bias
[09:35:11] ==================== [PASSED] drm_buddy ====================
[09:35:11] ============= drm_cmdline_parser (40 subtests) =============
[09:35:11] [PASSED] drm_test_cmdline_force_d_only
[09:35:11] [PASSED] drm_test_cmdline_force_D_only_dvi
[09:35:11] [PASSED] drm_test_cmdline_force_D_only_hdmi
[09:35:11] [PASSED] drm_test_cmdline_force_D_only_not_digital
[09:35:11] [PASSED] drm_test_cmdline_force_e_only
[09:35:11] [PASSED] drm_test_cmdline_res
[09:35:11] [PASSED] drm_test_cmdline_res_vesa
[09:35:11] [PASSED] drm_test_cmdline_res_vesa_rblank
[09:35:11] [PASSED] drm_test_cmdline_res_rblank
[09:35:11] [PASSED] drm_test_cmdline_res_bpp
[09:35:11] [PASSED] drm_test_cmdline_res_refresh
[09:35:11] [PASSED] drm_test_cmdline_res_bpp_refresh
[09:35:11] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[09:35:11] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[09:35:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[09:35:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[09:35:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[09:35:11] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[09:35:11] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[09:35:11] [PASSED] drm_test_cmdline_res_margins_force_on
[09:35:11] [PASSED] drm_test_cmdline_res_vesa_margins
[09:35:11] [PASSED] drm_test_cmdline_name
[09:35:11] [PASSED] drm_test_cmdline_name_bpp
[09:35:11] [PASSED] drm_test_cmdline_name_option
[09:35:11] [PASSED] drm_test_cmdline_name_bpp_option
[09:35:11] [PASSED] drm_test_cmdline_rotate_0
[09:35:11] [PASSED] drm_test_cmdline_rotate_90
[09:35:11] [PASSED] drm_test_cmdline_rotate_180
[09:35:11] [PASSED] drm_test_cmdline_rotate_270
[09:35:11] [PASSED] drm_test_cmdline_hmirror
[09:35:11] [PASSED] drm_test_cmdline_vmirror
[09:35:11] [PASSED] drm_test_cmdline_margin_options
[09:35:11] [PASSED] drm_test_cmdline_multiple_options
[09:35:11] [PASSED] drm_test_cmdline_bpp_extra_and_option
[09:35:11] [PASSED] drm_test_cmdline_extra_and_option
[09:35:11] [PASSED] drm_test_cmdline_freestanding_options
[09:35:11] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[09:35:11] [PASSED] drm_test_cmdline_panel_orientation
[09:35:11] ================ drm_test_cmdline_invalid =================
[09:35:11] [PASSED] margin_only
[09:35:11] [PASSED] interlace_only
[09:35:11] [PASSED] res_missing_x
[09:35:11] [PASSED] res_missing_y
[09:35:11] [PASSED] res_bad_y
[09:35:11] [PASSED] res_missing_y_bpp
[09:35:11] [PASSED] res_bad_bpp
[09:35:11] [PASSED] res_bad_refresh
[09:35:11] [PASSED] res_bpp_refresh_force_on_off
[09:35:11] [PASSED] res_invalid_mode
[09:35:11] [PASSED] res_bpp_wrong_place_mode
[09:35:11] [PASSED] name_bpp_refresh
[09:35:11] [PASSED] name_refresh
[09:35:11] [PASSED] name_refresh_wrong_mode
[09:35:11] [PASSED] name_refresh_invalid_mode
[09:35:11] [PASSED] rotate_multiple
[09:35:11] [PASSED] rotate_invalid_val
[09:35:11] [PASSED] rotate_truncated
[09:35:11] [PASSED] invalid_option
[09:35:11] [PASSED] invalid_tv_option
[09:35:11] [PASSED] truncated_tv_option
[09:35:11] ============ [PASSED] drm_test_cmdline_invalid =============
[09:35:11] =============== drm_test_cmdline_tv_options ===============
[09:35:11] [PASSED] NTSC
[09:35:11] [PASSED] NTSC_443
[09:35:11] [PASSED] NTSC_J
[09:35:11] [PASSED] PAL
[09:35:11] [PASSED] PAL_M
[09:35:11] [PASSED] PAL_N
[09:35:11] [PASSED] SECAM
[09:35:11] [PASSED] MONO_525
[09:35:11] [PASSED] MONO_625
[09:35:11] =========== [PASSED] drm_test_cmdline_tv_options ===========
[09:35:11] =============== [PASSED] drm_cmdline_parser ================
[09:35:11] ========== drmm_connector_hdmi_init (20 subtests) ==========
[09:35:11] [PASSED] drm_test_connector_hdmi_init_valid
[09:35:11] [PASSED] drm_test_connector_hdmi_init_bpc_8
[09:35:11] [PASSED] drm_test_connector_hdmi_init_bpc_10
[09:35:11] [PASSED] drm_test_connector_hdmi_init_bpc_12
[09:35:11] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[09:35:11] [PASSED] drm_test_connector_hdmi_init_bpc_null
[09:35:11] [PASSED] drm_test_connector_hdmi_init_formats_empty
[09:35:11] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[09:35:11] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:35:11] [PASSED] supported_formats=0x9 yuv420_allowed=1
[09:35:11] [PASSED] supported_formats=0x9 yuv420_allowed=0
[09:35:11] [PASSED] supported_formats=0x3 yuv420_allowed=1
[09:35:11] [PASSED] supported_formats=0x3 yuv420_allowed=0
[09:35:11] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:35:11] [PASSED] drm_test_connector_hdmi_init_null_ddc
[09:35:11] [PASSED] drm_test_connector_hdmi_init_null_product
[09:35:11] [PASSED] drm_test_connector_hdmi_init_null_vendor
[09:35:11] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[09:35:11] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[09:35:11] [PASSED] drm_test_connector_hdmi_init_product_valid
[09:35:11] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[09:35:11] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[09:35:11] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[09:35:11] ========= drm_test_connector_hdmi_init_type_valid =========
[09:35:11] [PASSED] HDMI-A
[09:35:11] [PASSED] HDMI-B
[09:35:11] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[09:35:11] ======== drm_test_connector_hdmi_init_type_invalid ========
[09:35:11] [PASSED] Unknown
[09:35:11] [PASSED] VGA
[09:35:11] [PASSED] DVI-I
[09:35:11] [PASSED] DVI-D
[09:35:11] [PASSED] DVI-A
[09:35:11] [PASSED] Composite
[09:35:11] [PASSED] SVIDEO
[09:35:11] [PASSED] LVDS
[09:35:11] [PASSED] Component
[09:35:11] [PASSED] DIN
[09:35:11] [PASSED] DP
[09:35:11] [PASSED] TV
[09:35:11] [PASSED] eDP
[09:35:11] [PASSED] Virtual
[09:35:11] [PASSED] DSI
[09:35:11] [PASSED] DPI
[09:35:11] [PASSED] Writeback
[09:35:11] [PASSED] SPI
[09:35:11] [PASSED] USB
[09:35:11] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[09:35:11] ============ [PASSED] drmm_connector_hdmi_init =============
[09:35:11] ============= drmm_connector_init (3 subtests) =============
[09:35:11] [PASSED] drm_test_drmm_connector_init
[09:35:11] [PASSED] drm_test_drmm_connector_init_null_ddc
[09:35:11] ========= drm_test_drmm_connector_init_type_valid =========
[09:35:11] [PASSED] Unknown
[09:35:11] [PASSED] VGA
[09:35:11] [PASSED] DVI-I
[09:35:11] [PASSED] DVI-D
[09:35:11] [PASSED] DVI-A
[09:35:11] [PASSED] Composite
[09:35:11] [PASSED] SVIDEO
[09:35:11] [PASSED] LVDS
[09:35:11] [PASSED] Component
[09:35:11] [PASSED] DIN
[09:35:11] [PASSED] DP
[09:35:11] [PASSED] HDMI-A
[09:35:11] [PASSED] HDMI-B
[09:35:11] [PASSED] TV
[09:35:11] [PASSED] eDP
[09:35:11] [PASSED] Virtual
[09:35:11] [PASSED] DSI
[09:35:11] [PASSED] DPI
[09:35:11] [PASSED] Writeback
[09:35:11] [PASSED] SPI
[09:35:11] [PASSED] USB
[09:35:11] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[09:35:11] =============== [PASSED] drmm_connector_init ===============
[09:35:11] ========= drm_connector_dynamic_init (6 subtests) ==========
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_init
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_init_properties
[09:35:11] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[09:35:11] [PASSED] Unknown
[09:35:11] [PASSED] VGA
[09:35:11] [PASSED] DVI-I
[09:35:11] [PASSED] DVI-D
[09:35:11] [PASSED] DVI-A
[09:35:11] [PASSED] Composite
[09:35:11] [PASSED] SVIDEO
[09:35:11] [PASSED] LVDS
[09:35:11] [PASSED] Component
[09:35:11] [PASSED] DIN
[09:35:11] [PASSED] DP
[09:35:11] [PASSED] HDMI-A
[09:35:11] [PASSED] HDMI-B
[09:35:11] [PASSED] TV
[09:35:11] [PASSED] eDP
[09:35:11] [PASSED] Virtual
[09:35:11] [PASSED] DSI
[09:35:11] [PASSED] DPI
[09:35:11] [PASSED] Writeback
[09:35:11] [PASSED] SPI
[09:35:11] [PASSED] USB
[09:35:11] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[09:35:11] ======== drm_test_drm_connector_dynamic_init_name =========
[09:35:11] [PASSED] Unknown
[09:35:11] [PASSED] VGA
[09:35:11] [PASSED] DVI-I
[09:35:11] [PASSED] DVI-D
[09:35:11] [PASSED] DVI-A
[09:35:11] [PASSED] Composite
[09:35:11] [PASSED] SVIDEO
[09:35:11] [PASSED] LVDS
[09:35:11] [PASSED] Component
[09:35:11] [PASSED] DIN
[09:35:11] [PASSED] DP
[09:35:11] [PASSED] HDMI-A
[09:35:11] [PASSED] HDMI-B
[09:35:11] [PASSED] TV
[09:35:11] [PASSED] eDP
[09:35:11] [PASSED] Virtual
[09:35:11] [PASSED] DSI
[09:35:11] [PASSED] DPI
[09:35:11] [PASSED] Writeback
[09:35:11] [PASSED] SPI
[09:35:11] [PASSED] USB
[09:35:11] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[09:35:11] =========== [PASSED] drm_connector_dynamic_init ============
[09:35:11] ==== drm_connector_dynamic_register_early (4 subtests) =====
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[09:35:11] ====== [PASSED] drm_connector_dynamic_register_early =======
[09:35:11] ======= drm_connector_dynamic_register (7 subtests) ========
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[09:35:11] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[09:35:11] ========= [PASSED] drm_connector_dynamic_register ==========
[09:35:11] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[09:35:11] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[09:35:11] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[09:35:11] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[09:35:11] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[09:35:11] ========== drm_test_get_tv_mode_from_name_valid ===========
[09:35:11] [PASSED] NTSC
[09:35:11] [PASSED] NTSC-443
[09:35:11] [PASSED] NTSC-J
[09:35:11] [PASSED] PAL
[09:35:11] [PASSED] PAL-M
[09:35:11] [PASSED] PAL-N
[09:35:11] [PASSED] SECAM
[09:35:11] [PASSED] Mono
[09:35:11] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[09:35:11] [PASSED] drm_test_get_tv_mode_from_name_truncated
[09:35:11] ============ [PASSED] drm_get_tv_mode_from_name ============
[09:35:11] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[09:35:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[09:35:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[09:35:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[09:35:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[09:35:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[09:35:11] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[09:35:11] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[09:35:11] [PASSED] VIC 96
[09:35:11] [PASSED] VIC 97
[09:35:11] [PASSED] VIC 101
[09:35:11] [PASSED] VIC 102
[09:35:11] [PASSED] VIC 106
[09:35:11] [PASSED] VIC 107
[09:35:11] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[09:35:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[09:35:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[09:35:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[09:35:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[09:35:11] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[09:35:11] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[09:35:11] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[09:35:11] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[09:35:11] [PASSED] Automatic
[09:35:11] [PASSED] Full
[09:35:11] [PASSED] Limited 16:235
[09:35:11] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[09:35:11] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[09:35:11] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[09:35:11] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[09:35:11] === drm_test_drm_hdmi_connector_get_output_format_name ====
[09:35:11] [PASSED] RGB
[09:35:11] [PASSED] YUV 4:2:0
[09:35:11] [PASSED] YUV 4:2:2
[09:35:11] [PASSED] YUV 4:4:4
[09:35:11] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[09:35:11] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[09:35:11] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[09:35:11] ============= drm_damage_helper (21 subtests) ==============
[09:35:11] [PASSED] drm_test_damage_iter_no_damage
[09:35:11] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[09:35:11] [PASSED] drm_test_damage_iter_no_damage_src_moved
[09:35:11] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[09:35:11] [PASSED] drm_test_damage_iter_no_damage_not_visible
[09:35:11] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[09:35:11] [PASSED] drm_test_damage_iter_no_damage_no_fb
[09:35:11] [PASSED] drm_test_damage_iter_simple_damage
[09:35:11] [PASSED] drm_test_damage_iter_single_damage
[09:35:11] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[09:35:11] [PASSED] drm_test_damage_iter_single_damage_outside_src
[09:35:11] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[09:35:11] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[09:35:11] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[09:35:11] [PASSED] drm_test_damage_iter_single_damage_src_moved
[09:35:11] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[09:35:11] [PASSED] drm_test_damage_iter_damage
[09:35:11] [PASSED] drm_test_damage_iter_damage_one_intersect
[09:35:11] [PASSED] drm_test_damage_iter_damage_one_outside
[09:35:11] [PASSED] drm_test_damage_iter_damage_src_moved
[09:35:11] [PASSED] drm_test_damage_iter_damage_not_visible
[09:35:11] ================ [PASSED] drm_damage_helper ================
[09:35:11] ============== drm_dp_mst_helper (3 subtests) ==============
[09:35:11] ============== drm_test_dp_mst_calc_pbn_mode ==============
[09:35:11] [PASSED] Clock 154000 BPP 30 DSC disabled
[09:35:11] [PASSED] Clock 234000 BPP 30 DSC disabled
[09:35:11] [PASSED] Clock 297000 BPP 24 DSC disabled
[09:35:11] [PASSED] Clock 332880 BPP 24 DSC enabled
[09:35:11] [PASSED] Clock 324540 BPP 24 DSC enabled
[09:35:11] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[09:35:11] ============== drm_test_dp_mst_calc_pbn_div ===============
[09:35:11] [PASSED] Link rate 2000000 lane count 4
[09:35:11] [PASSED] Link rate 2000000 lane count 2
[09:35:11] [PASSED] Link rate 2000000 lane count 1
[09:35:11] [PASSED] Link rate 1350000 lane count 4
[09:35:11] [PASSED] Link rate 1350000 lane count 2
[09:35:11] [PASSED] Link rate 1350000 lane count 1
[09:35:11] [PASSED] Link rate 1000000 lane count 4
[09:35:11] [PASSED] Link rate 1000000 lane count 2
[09:35:11] [PASSED] Link rate 1000000 lane count 1
[09:35:11] [PASSED] Link rate 810000 lane count 4
[09:35:11] [PASSED] Link rate 810000 lane count 2
[09:35:11] [PASSED] Link rate 810000 lane count 1
[09:35:11] [PASSED] Link rate 540000 lane count 4
[09:35:11] [PASSED] Link rate 540000 lane count 2
[09:35:11] [PASSED] Link rate 540000 lane count 1
[09:35:11] [PASSED] Link rate 270000 lane count 4
[09:35:11] [PASSED] Link rate 270000 lane count 2
[09:35:11] [PASSED] Link rate 270000 lane count 1
[09:35:11] [PASSED] Link rate 162000 lane count 4
[09:35:11] [PASSED] Link rate 162000 lane count 2
[09:35:11] [PASSED] Link rate 162000 lane count 1
[09:35:11] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[09:35:11] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[09:35:11] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[09:35:11] [PASSED] DP_POWER_UP_PHY with port number
[09:35:11] [PASSED] DP_POWER_DOWN_PHY with port number
[09:35:11] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[09:35:11] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[09:35:11] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[09:35:11] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[09:35:11] [PASSED] DP_QUERY_PAYLOAD with port number
[09:35:11] [PASSED] DP_QUERY_PAYLOAD with VCPI
[09:35:11] [PASSED] DP_REMOTE_DPCD_READ with port number
[09:35:11] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[09:35:11] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[09:35:11] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[09:35:11] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[09:35:11] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[09:35:11] [PASSED] DP_REMOTE_I2C_READ with port number
[09:35:11] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[09:35:11] [PASSED] DP_REMOTE_I2C_READ with transactions array
[09:35:11] [PASSED] DP_REMOTE_I2C_WRITE with port number
[09:35:11] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[09:35:11] [PASSED] DP_REMOTE_I2C_WRITE with data array
[09:35:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[09:35:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[09:35:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[09:35:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[09:35:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[09:35:11] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[09:35:11] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[09:35:11] ================ [PASSED] drm_dp_mst_helper ================
[09:35:11] ================== drm_exec (7 subtests) ===================
[09:35:11] [PASSED] sanitycheck
[09:35:11] [PASSED] test_lock
[09:35:11] [PASSED] test_lock_unlock
[09:35:11] [PASSED] test_duplicates
[09:35:11] [PASSED] test_prepare
[09:35:11] [PASSED] test_prepare_array
[09:35:11] [PASSED] test_multiple_loops
[09:35:11] ==================== [PASSED] drm_exec =====================
[09:35:11] =========== drm_format_helper_test (17 subtests) ===========
[09:35:11] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[09:35:11] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[09:35:11] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[09:35:11] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[09:35:11] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[09:35:11] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[09:35:11] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[09:35:11] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[09:35:11] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[09:35:11] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[09:35:11] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[09:35:11] ============== drm_test_fb_xrgb8888_to_mono ===============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[09:35:11] ==================== drm_test_fb_swab =====================
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ================ [PASSED] drm_test_fb_swab =================
[09:35:11] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[09:35:11] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[09:35:11] [PASSED] single_pixel_source_buffer
[09:35:11] [PASSED] single_pixel_clip_rectangle
[09:35:11] [PASSED] well_known_colors
[09:35:11] [PASSED] destination_pitch
[09:35:11] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[09:35:11] ================= drm_test_fb_clip_offset =================
[09:35:11] [PASSED] pass through
[09:35:11] [PASSED] horizontal offset
[09:35:11] [PASSED] vertical offset
[09:35:11] [PASSED] horizontal and vertical offset
[09:35:11] [PASSED] horizontal offset (custom pitch)
[09:35:11] [PASSED] vertical offset (custom pitch)
[09:35:11] [PASSED] horizontal and vertical offset (custom pitch)
[09:35:11] ============= [PASSED] drm_test_fb_clip_offset =============
[09:35:11] =================== drm_test_fb_memcpy ====================
[09:35:11] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[09:35:11] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[09:35:11] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[09:35:11] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[09:35:11] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[09:35:11] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[09:35:11] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[09:35:11] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[09:35:11] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[09:35:11] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[09:35:11] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[09:35:11] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[09:35:11] =============== [PASSED] drm_test_fb_memcpy ================
[09:35:11] ============= [PASSED] drm_format_helper_test ==============
[09:35:11] ================= drm_format (18 subtests) =================
[09:35:11] [PASSED] drm_test_format_block_width_invalid
[09:35:11] [PASSED] drm_test_format_block_width_one_plane
[09:35:11] [PASSED] drm_test_format_block_width_two_plane
[09:35:11] [PASSED] drm_test_format_block_width_three_plane
[09:35:11] [PASSED] drm_test_format_block_width_tiled
[09:35:11] [PASSED] drm_test_format_block_height_invalid
[09:35:11] [PASSED] drm_test_format_block_height_one_plane
[09:35:11] [PASSED] drm_test_format_block_height_two_plane
[09:35:11] [PASSED] drm_test_format_block_height_three_plane
[09:35:11] [PASSED] drm_test_format_block_height_tiled
[09:35:11] [PASSED] drm_test_format_min_pitch_invalid
[09:35:11] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[09:35:11] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[09:35:11] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[09:35:11] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[09:35:11] [PASSED] drm_test_format_min_pitch_two_plane
[09:35:11] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[09:35:11] [PASSED] drm_test_format_min_pitch_tiled
[09:35:11] =================== [PASSED] drm_format ====================
[09:35:11] ============== drm_framebuffer (10 subtests) ===============
[09:35:11] ========== drm_test_framebuffer_check_src_coords ==========
[09:35:11] [PASSED] Success: source fits into fb
[09:35:11] [PASSED] Fail: overflowing fb with x-axis coordinate
[09:35:11] [PASSED] Fail: overflowing fb with y-axis coordinate
[09:35:11] [PASSED] Fail: overflowing fb with source width
[09:35:11] [PASSED] Fail: overflowing fb with source height
[09:35:11] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[09:35:11] [PASSED] drm_test_framebuffer_cleanup
[09:35:11] =============== drm_test_framebuffer_create ===============
[09:35:11] [PASSED] ABGR8888 normal sizes
[09:35:11] [PASSED] ABGR8888 max sizes
[09:35:11] [PASSED] ABGR8888 pitch greater than min required
[09:35:11] [PASSED] ABGR8888 pitch less than min required
[09:35:11] [PASSED] ABGR8888 Invalid width
[09:35:11] [PASSED] ABGR8888 Invalid buffer handle
[09:35:11] [PASSED] No pixel format
[09:35:11] [PASSED] ABGR8888 Width 0
[09:35:11] [PASSED] ABGR8888 Height 0
[09:35:11] [PASSED] ABGR8888 Out of bound height * pitch combination
[09:35:11] [PASSED] ABGR8888 Large buffer offset
[09:35:11] [PASSED] ABGR8888 Buffer offset for inexistent plane
[09:35:11] [PASSED] ABGR8888 Invalid flag
[09:35:11] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[09:35:11] [PASSED] ABGR8888 Valid buffer modifier
[09:35:11] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[09:35:11] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[09:35:11] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[09:35:11] [PASSED] NV12 Normal sizes
[09:35:11] [PASSED] NV12 Max sizes
[09:35:11] [PASSED] NV12 Invalid pitch
[09:35:11] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[09:35:11] [PASSED] NV12 different modifier per-plane
[09:35:11] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[09:35:11] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[09:35:11] [PASSED] NV12 Modifier for inexistent plane
[09:35:11] [PASSED] NV12 Handle for inexistent plane
[09:35:11] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[09:35:11] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[09:35:11] [PASSED] YVU420 Normal sizes
[09:35:11] [PASSED] YVU420 Max sizes
[09:35:11] [PASSED] YVU420 Invalid pitch
[09:35:11] [PASSED] YVU420 Different pitches
[09:35:11] [PASSED] YVU420 Different buffer offsets/pitches
[09:35:11] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[09:35:11] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[09:35:11] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[09:35:11] [PASSED] YVU420 Valid modifier
[09:35:11] [PASSED] YVU420 Different modifiers per plane
[09:35:11] [PASSED] YVU420 Modifier for inexistent plane
[09:35:11] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[09:35:11] [PASSED] X0L2 Normal sizes
[09:35:11] [PASSED] X0L2 Max sizes
[09:35:11] [PASSED] X0L2 Invalid pitch
[09:35:11] [PASSED] X0L2 Pitch greater than minimum required
[09:35:11] [PASSED] X0L2 Handle for inexistent plane
[09:35:11] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[09:35:11] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[09:35:11] [PASSED] X0L2 Valid modifier
[09:35:11] [PASSED] X0L2 Modifier for inexistent plane
[09:35:11] =========== [PASSED] drm_test_framebuffer_create ===========
[09:35:11] [PASSED] drm_test_framebuffer_free
[09:35:11] [PASSED] drm_test_framebuffer_init
[09:35:11] [PASSED] drm_test_framebuffer_init_bad_format
[09:35:11] [PASSED] drm_test_framebuffer_init_dev_mismatch
[09:35:11] [PASSED] drm_test_framebuffer_lookup
[09:35:11] [PASSED] drm_test_framebuffer_lookup_inexistent
[09:35:11] [PASSED] drm_test_framebuffer_modifiers_not_supported
[09:35:11] ================= [PASSED] drm_framebuffer =================
[09:35:11] ================ drm_gem_shmem (8 subtests) ================
[09:35:11] [PASSED] drm_gem_shmem_test_obj_create
[09:35:11] [PASSED] drm_gem_shmem_test_obj_create_private
[09:35:11] [PASSED] drm_gem_shmem_test_pin_pages
[09:35:11] [PASSED] drm_gem_shmem_test_vmap
[09:35:11] [PASSED] drm_gem_shmem_test_get_pages_sgt
[09:35:11] [PASSED] drm_gem_shmem_test_get_sg_table
[09:35:11] [PASSED] drm_gem_shmem_test_madvise
[09:35:11] [PASSED] drm_gem_shmem_test_purge
[09:35:11] ================== [PASSED] drm_gem_shmem ==================
[09:35:11] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[09:35:11] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[09:35:11] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[09:35:11] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[09:35:11] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[09:35:11] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[09:35:11] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[09:35:11] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[09:35:11] [PASSED] Automatic
[09:35:11] [PASSED] Full
[09:35:11] [PASSED] Limited 16:235
[09:35:11] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[09:35:11] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[09:35:11] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[09:35:11] [PASSED] drm_test_check_disable_connector
[09:35:11] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[09:35:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[09:35:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[09:35:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[09:35:11] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[09:35:11] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[09:35:11] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[09:35:11] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[09:35:11] [PASSED] drm_test_check_output_bpc_dvi
[09:35:11] [PASSED] drm_test_check_output_bpc_format_vic_1
[09:35:11] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[09:35:11] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[09:35:11] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[09:35:11] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[09:35:11] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[09:35:11] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[09:35:11] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[09:35:11] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[09:35:11] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[09:35:11] [PASSED] drm_test_check_broadcast_rgb_value
[09:35:11] [PASSED] drm_test_check_bpc_8_value
[09:35:11] [PASSED] drm_test_check_bpc_10_value
[09:35:11] [PASSED] drm_test_check_bpc_12_value
[09:35:11] [PASSED] drm_test_check_format_value
[09:35:11] [PASSED] drm_test_check_tmds_char_value
[09:35:11] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[09:35:11] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[09:35:11] [PASSED] drm_test_check_mode_valid
[09:35:11] [PASSED] drm_test_check_mode_valid_reject
[09:35:11] [PASSED] drm_test_check_mode_valid_reject_rate
[09:35:11] [PASSED] drm_test_check_mode_valid_reject_max_clock
[09:35:11] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[09:35:11] ================= drm_managed (2 subtests) =================
[09:35:11] [PASSED] drm_test_managed_release_action
[09:35:11] [PASSED] drm_test_managed_run_action
[09:35:11] =================== [PASSED] drm_managed ===================
[09:35:11] =================== drm_mm (6 subtests) ====================
[09:35:11] [PASSED] drm_test_mm_init
[09:35:11] [PASSED] drm_test_mm_debug
[09:35:11] [PASSED] drm_test_mm_align32
[09:35:11] [PASSED] drm_test_mm_align64
[09:35:11] [PASSED] drm_test_mm_lowest
[09:35:11] [PASSED] drm_test_mm_highest
[09:35:11] ===================== [PASSED] drm_mm ======================
[09:35:11] ============= drm_modes_analog_tv (5 subtests) =============
[09:35:11] [PASSED] drm_test_modes_analog_tv_mono_576i
[09:35:11] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[09:35:11] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[09:35:11] [PASSED] drm_test_modes_analog_tv_pal_576i
[09:35:11] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[09:35:11] =============== [PASSED] drm_modes_analog_tv ===============
[09:35:11] ============== drm_plane_helper (2 subtests) ===============
[09:35:11] =============== drm_test_check_plane_state ================
[09:35:11] [PASSED] clipping_simple
[09:35:11] [PASSED] clipping_rotate_reflect
[09:35:11] [PASSED] positioning_simple
[09:35:11] [PASSED] upscaling
[09:35:11] [PASSED] downscaling
[09:35:11] [PASSED] rounding1
[09:35:11] [PASSED] rounding2
[09:35:11] [PASSED] rounding3
[09:35:11] [PASSED] rounding4
[09:35:11] =========== [PASSED] drm_test_check_plane_state ============
[09:35:11] =========== drm_test_check_invalid_plane_state ============
[09:35:11] [PASSED] positioning_invalid
[09:35:11] [PASSED] upscaling_invalid
[09:35:11] [PASSED] downscaling_invalid
[09:35:11] ======= [PASSED] drm_test_check_invalid_plane_state ========
[09:35:11] ================ [PASSED] drm_plane_helper =================
[09:35:11] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[09:35:11] ====== drm_test_connector_helper_tv_get_modes_check =======
[09:35:11] [PASSED] None
[09:35:11] [PASSED] PAL
[09:35:11] [PASSED] NTSC
[09:35:11] [PASSED] Both, NTSC Default
[09:35:11] [PASSED] Both, PAL Default
[09:35:11] [PASSED] Both, NTSC Default, with PAL on command-line
[09:35:11] [PASSED] Both, PAL Default, with NTSC on command-line
[09:35:11] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[09:35:11] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[09:35:11] ================== drm_rect (9 subtests) ===================
[09:35:11] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[09:35:11] [PASSED] drm_test_rect_clip_scaled_not_clipped
[09:35:11] [PASSED] drm_test_rect_clip_scaled_clipped
[09:35:11] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[09:35:11] ================= drm_test_rect_intersect =================
[09:35:11] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[09:35:11] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[09:35:11] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[09:35:11] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[09:35:11] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[09:35:11] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[09:35:11] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[09:35:11] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[09:35:11] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[09:35:11] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[09:35:11] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[09:35:11] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[09:35:11] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[09:35:11] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[09:35:11] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[09:35:11] ============= [PASSED] drm_test_rect_intersect =============
[09:35:11] ================ drm_test_rect_calc_hscale ================
[09:35:11] [PASSED] normal use
[09:35:11] [PASSED] out of max range
[09:35:11] [PASSED] out of min range
[09:35:11] [PASSED] zero dst
[09:35:11] [PASSED] negative src
[09:35:11] [PASSED] negative dst
[09:35:11] ============ [PASSED] drm_test_rect_calc_hscale ============
[09:35:11] ================ drm_test_rect_calc_vscale ================
[09:35:11] [PASSED] normal use
[09:35:11] [PASSED] out of max range
[09:35:11] [PASSED] out of min range
[09:35:11] [PASSED] zero dst
[09:35:11] [PASSED] negative src
[09:35:11] [PASSED] negative dst
[09:35:11] ============ [PASSED] drm_test_rect_calc_vscale ============
[09:35:11] ================== drm_test_rect_rotate ===================
[09:35:11] [PASSED] reflect-x
[09:35:11] [PASSED] reflect-y
[09:35:11] [PASSED] rotate-0
[09:35:11] [PASSED] rotate-90
[09:35:11] [PASSED] rotate-180
[09:35:11] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[09:35:11] ============== [PASSED] drm_test_rect_rotate ===============
[09:35:11] ================ drm_test_rect_rotate_inv =================
[09:35:11] [PASSED] reflect-x
[09:35:11] [PASSED] reflect-y
[09:35:11] [PASSED] rotate-0
[09:35:11] [PASSED] rotate-90
[09:35:11] [PASSED] rotate-180
[09:35:11] [PASSED] rotate-270
[09:35:11] ============ [PASSED] drm_test_rect_rotate_inv =============
[09:35:11] ==================== [PASSED] drm_rect =====================
[09:35:11] ============ drm_sysfb_modeset_test (1 subtest) ============
[09:35:11] ============ drm_test_sysfb_build_fourcc_list =============
[09:35:11] [PASSED] no native formats
[09:35:11] [PASSED] XRGB8888 as native format
[09:35:11] [PASSED] remove duplicates
[09:35:11] [PASSED] convert alpha formats
[09:35:11] [PASSED] random formats
[09:35:11] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[09:35:11] ============= [PASSED] drm_sysfb_modeset_test ==============
[09:35:11] ============================================================
[09:35:11] Testing complete. Ran 616 tests: passed: 616
[09:35:11] Elapsed time: 23.559s total, 1.741s configuring, 21.600s building, 0.187s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[09:35:11] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:35:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:35:20] Starting KUnit Kernel (1/1)...
[09:35:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:35:21] ================= ttm_device (5 subtests) ==================
[09:35:21] [PASSED] ttm_device_init_basic
[09:35:21] [PASSED] ttm_device_init_multiple
[09:35:21] [PASSED] ttm_device_fini_basic
[09:35:21] [PASSED] ttm_device_init_no_vma_man
[09:35:21] ================== ttm_device_init_pools ==================
[09:35:21] [PASSED] No DMA allocations, no DMA32 required
[09:35:21] [PASSED] DMA allocations, DMA32 required
[09:35:21] [PASSED] No DMA allocations, DMA32 required
[09:35:21] [PASSED] DMA allocations, no DMA32 required
[09:35:21] ============== [PASSED] ttm_device_init_pools ==============
[09:35:21] =================== [PASSED] ttm_device ====================
[09:35:21] ================== ttm_pool (8 subtests) ===================
[09:35:21] ================== ttm_pool_alloc_basic ===================
[09:35:21] [PASSED] One page
[09:35:21] [PASSED] More than one page
[09:35:21] [PASSED] Above the allocation limit
[09:35:21] [PASSED] One page, with coherent DMA mappings enabled
[09:35:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:35:21] ============== [PASSED] ttm_pool_alloc_basic ===============
[09:35:21] ============== ttm_pool_alloc_basic_dma_addr ==============
[09:35:21] [PASSED] One page
[09:35:21] [PASSED] More than one page
[09:35:21] [PASSED] Above the allocation limit
[09:35:21] [PASSED] One page, with coherent DMA mappings enabled
[09:35:21] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:35:21] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[09:35:21] [PASSED] ttm_pool_alloc_order_caching_match
[09:35:21] [PASSED] ttm_pool_alloc_caching_mismatch
[09:35:21] [PASSED] ttm_pool_alloc_order_mismatch
[09:35:21] [PASSED] ttm_pool_free_dma_alloc
[09:35:21] [PASSED] ttm_pool_free_no_dma_alloc
[09:35:21] [PASSED] ttm_pool_fini_basic
[09:35:21] ==================== [PASSED] ttm_pool =====================
[09:35:21] ================ ttm_resource (8 subtests) =================
[09:35:21] ================= ttm_resource_init_basic =================
[09:35:21] [PASSED] Init resource in TTM_PL_SYSTEM
[09:35:21] [PASSED] Init resource in TTM_PL_VRAM
[09:35:21] [PASSED] Init resource in a private placement
[09:35:21] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[09:35:21] ============= [PASSED] ttm_resource_init_basic =============
[09:35:21] [PASSED] ttm_resource_init_pinned
[09:35:21] [PASSED] ttm_resource_fini_basic
[09:35:21] [PASSED] ttm_resource_manager_init_basic
[09:35:21] [PASSED] ttm_resource_manager_usage_basic
[09:35:21] [PASSED] ttm_resource_manager_set_used_basic
[09:35:21] [PASSED] ttm_sys_man_alloc_basic
[09:35:21] [PASSED] ttm_sys_man_free_basic
[09:35:21] ================== [PASSED] ttm_resource ===================
[09:35:21] =================== ttm_tt (15 subtests) ===================
[09:35:21] ==================== ttm_tt_init_basic ====================
[09:35:21] [PASSED] Page-aligned size
[09:35:21] [PASSED] Extra pages requested
[09:35:21] ================ [PASSED] ttm_tt_init_basic ================
[09:35:21] [PASSED] ttm_tt_init_misaligned
[09:35:21] [PASSED] ttm_tt_fini_basic
[09:35:21] [PASSED] ttm_tt_fini_sg
[09:35:21] [PASSED] ttm_tt_fini_shmem
[09:35:21] [PASSED] ttm_tt_create_basic
[09:35:21] [PASSED] ttm_tt_create_invalid_bo_type
[09:35:21] [PASSED] ttm_tt_create_ttm_exists
[09:35:21] [PASSED] ttm_tt_create_failed
[09:35:21] [PASSED] ttm_tt_destroy_basic
[09:35:21] [PASSED] ttm_tt_populate_null_ttm
[09:35:21] [PASSED] ttm_tt_populate_populated_ttm
[09:35:21] [PASSED] ttm_tt_unpopulate_basic
[09:35:21] [PASSED] ttm_tt_unpopulate_empty_ttm
[09:35:21] [PASSED] ttm_tt_swapin_basic
[09:35:21] ===================== [PASSED] ttm_tt ======================
[09:35:21] =================== ttm_bo (14 subtests) ===================
[09:35:21] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[09:35:21] [PASSED] Cannot be interrupted and sleeps
[09:35:21] [PASSED] Cannot be interrupted, locks straight away
[09:35:21] [PASSED] Can be interrupted, sleeps
[09:35:21] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[09:35:21] [PASSED] ttm_bo_reserve_locked_no_sleep
[09:35:21] [PASSED] ttm_bo_reserve_no_wait_ticket
[09:35:21] [PASSED] ttm_bo_reserve_double_resv
[09:35:21] [PASSED] ttm_bo_reserve_interrupted
[09:35:21] [PASSED] ttm_bo_reserve_deadlock
[09:35:21] [PASSED] ttm_bo_unreserve_basic
[09:35:21] [PASSED] ttm_bo_unreserve_pinned
[09:35:21] [PASSED] ttm_bo_unreserve_bulk
[09:35:21] [PASSED] ttm_bo_put_basic
[09:35:21] [PASSED] ttm_bo_put_shared_resv
[09:35:21] [PASSED] ttm_bo_pin_basic
[09:35:21] [PASSED] ttm_bo_pin_unpin_resource
[09:35:21] [PASSED] ttm_bo_multiple_pin_one_unpin
[09:35:21] ===================== [PASSED] ttm_bo ======================
[09:35:21] ============== ttm_bo_validate (21 subtests) ===============
[09:35:21] ============== ttm_bo_init_reserved_sys_man ===============
[09:35:21] [PASSED] Buffer object for userspace
[09:35:21] [PASSED] Kernel buffer object
[09:35:21] [PASSED] Shared buffer object
[09:35:21] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[09:35:21] ============== ttm_bo_init_reserved_mock_man ==============
[09:35:21] [PASSED] Buffer object for userspace
[09:35:21] [PASSED] Kernel buffer object
[09:35:21] [PASSED] Shared buffer object
[09:35:21] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[09:35:21] [PASSED] ttm_bo_init_reserved_resv
[09:35:21] ================== ttm_bo_validate_basic ==================
[09:35:21] [PASSED] Buffer object for userspace
[09:35:21] [PASSED] Kernel buffer object
[09:35:21] [PASSED] Shared buffer object
[09:35:21] ============== [PASSED] ttm_bo_validate_basic ==============
[09:35:21] [PASSED] ttm_bo_validate_invalid_placement
[09:35:21] ============= ttm_bo_validate_same_placement ==============
[09:35:21] [PASSED] System manager
[09:35:21] [PASSED] VRAM manager
[09:35:21] ========= [PASSED] ttm_bo_validate_same_placement ==========
[09:35:21] [PASSED] ttm_bo_validate_failed_alloc
[09:35:21] [PASSED] ttm_bo_validate_pinned
[09:35:21] [PASSED] ttm_bo_validate_busy_placement
[09:35:21] ================ ttm_bo_validate_multihop =================
[09:35:21] [PASSED] Buffer object for userspace
[09:35:21] [PASSED] Kernel buffer object
[09:35:21] [PASSED] Shared buffer object
[09:35:21] ============ [PASSED] ttm_bo_validate_multihop =============
[09:35:21] ========== ttm_bo_validate_no_placement_signaled ==========
[09:35:21] [PASSED] Buffer object in system domain, no page vector
[09:35:21] [PASSED] Buffer object in system domain with an existing page vector
[09:35:21] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[09:35:21] ======== ttm_bo_validate_no_placement_not_signaled ========
[09:35:21] [PASSED] Buffer object for userspace
[09:35:21] [PASSED] Kernel buffer object
[09:35:21] [PASSED] Shared buffer object
[09:35:21] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[09:35:21] [PASSED] ttm_bo_validate_move_fence_signaled
[09:35:21] ========= ttm_bo_validate_move_fence_not_signaled =========
[09:35:21] [PASSED] Waits for GPU
[09:35:21] [PASSED] Tries to lock straight away
[09:35:21] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[09:35:21] [PASSED] ttm_bo_validate_happy_evict
[09:35:21] [PASSED] ttm_bo_validate_all_pinned_evict
[09:35:21] [PASSED] ttm_bo_validate_allowed_only_evict
[09:35:21] [PASSED] ttm_bo_validate_deleted_evict
[09:35:21] [PASSED] ttm_bo_validate_busy_domain_evict
[09:35:21] [PASSED] ttm_bo_validate_evict_gutting
[09:35:21] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[09:35:21] ================= [PASSED] ttm_bo_validate =================
[09:35:21] ============================================================
[09:35:21] Testing complete. Ran 101 tests: passed: 101
[09:35:21] Elapsed time: 9.623s total, 1.714s configuring, 7.693s building, 0.183s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 21+ messages in thread* ✗ CI.checksparse: warning for Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (10 preceding siblings ...)
2025-07-21 9:35 ` ✓ CI.KUnit: success " Patchwork
@ 2025-07-21 9:50 ` Patchwork
2025-07-21 17:27 ` ✓ Xe.CI.BAT: success " Patchwork
2025-07-21 18:17 ` ✗ Xe.CI.Full: failure " Patchwork
13 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-07-21 9:50 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
URL : https://patchwork.freedesktop.org/series/138256/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 62dc6f672f79c0b74acd61dd86936f8e5e6fdb0d
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2024:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2024:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2024:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2037:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 21+ messages in thread* ✓ Xe.CI.BAT: success for Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (11 preceding siblings ...)
2025-07-21 9:50 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-07-21 17:27 ` Patchwork
2025-07-21 18:17 ` ✗ Xe.CI.Full: failure " Patchwork
13 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-07-21 17:27 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1477 bytes --]
== Series Details ==
Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
URL : https://patchwork.freedesktop.org/series/138256/
State : success
== Summary ==
CI Bug Log - changes from xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268_BAT -> xe-pw-138256v5_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 7)
------------------------------
Missing (1): bat-adlp-vm
Known issues
------------
Here are the changes found in xe-pw-138256v5_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-plain-flip@b-edp1:
- bat-adlp-7: [PASS][1] -> [DMESG-WARN][2] ([Intel XE#4543]) +1 other test dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
Build changes
-------------
* Linux: xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268 -> xe-pw-138256v5
IGT_8468: 8468
xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268: ab5c1718e3b878411f5fd2c6841db98e4f21f268
xe-pw-138256v5: 138256v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/index.html
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^ permalink raw reply [flat|nested] 21+ messages in thread* ✗ Xe.CI.Full: failure for Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
2025-07-21 9:15 [PATCH 0/4] Implement Wa_14021768792 to bypass m_n ratio limit Ankit Nautiyal
` (12 preceding siblings ...)
2025-07-21 17:27 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-07-21 18:17 ` Patchwork
13 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-07-21 18:17 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
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== Series Details ==
Series: Implement Wa_14021768792 to bypass m_n ratio limit (rev5)
URL : https://patchwork.freedesktop.org/series/138256/
State : failure
== Summary ==
CI Bug Log - changes from xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268_FULL -> xe-pw-138256v5_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-138256v5_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-138256v5_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-138256v5_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@core_getversion@all-cards:
- shard-adlp: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@core_getversion@all-cards.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@core_getversion@all-cards.html
* igt@xe_eu_stall@unprivileged-access:
- shard-dg2-set2: NOTRUN -> [SKIP][3]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_eu_stall@unprivileged-access.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init:
- shard-lnl: NOTRUN -> [ABORT][4]
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-lnl-1/igt@xe_fault_injection@inject-fault-probe-function-xe_uc_fw_init.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_wa_init:
- shard-bmg: NOTRUN -> [ABORT][5]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-3/igt@xe_fault_injection@inject-fault-probe-function-xe_wa_init.html
#### Warnings ####
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-adlp: [SKIP][6] ([Intel XE#836]) -> [ABORT][7]
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-8/igt@kms_pm_rpm@modeset-non-lpsp.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-6/igt@kms_pm_rpm@modeset-non-lpsp.html
Known issues
------------
Here are the changes found in xe-pw-138256v5_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][8] ([Intel XE#316])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-434/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#1124]) +5 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
- shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#2191])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
* igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][11] ([Intel XE#455] / [Intel XE#787]) +30 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-434/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#3442])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][13] ([Intel XE#787]) +160 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][14] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-dg2-set2: NOTRUN -> [SKIP][15] ([Intel XE#373]) +2 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_content_protection@atomic:
- shard-dg2-set2: NOTRUN -> [FAIL][16] ([Intel XE#1178]) +1 other test fail
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#307])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-lnl: NOTRUN -> [SKIP][18] ([Intel XE#3278])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-lnl-1/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][19] ([Intel XE#1178])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-4/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-bmg: [PASS][20] -> [SKIP][21] ([Intel XE#2291])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_draw_crc@fill-fb:
- shard-adlp: [PASS][22] -> [SKIP][23] ([Intel XE#2351] / [Intel XE#4947])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_draw_crc@fill-fb.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_draw_crc@fill-fb.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2-set2: NOTRUN -> [SKIP][24] ([Intel XE#703])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_feature_discovery@display-3x.html
* igt@kms_flip@2x-flip-vs-expired-vblank@cd-hdmi-a6-dp4:
- shard-dg2-set2: [PASS][25] -> [FAIL][26] ([Intel XE#301]) +1 other test fail
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-434/igt@kms_flip@2x-flip-vs-expired-vblank@cd-hdmi-a6-dp4.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@kms_flip@2x-flip-vs-expired-vblank@cd-hdmi-a6-dp4.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-bmg: [PASS][27] -> [FAIL][28] ([Intel XE#5338]) +1 other test fail
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-rmfb:
- shard-adlp: [PASS][29] -> [DMESG-WARN][30] ([Intel XE#5208])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-3/igt@kms_flip@flip-vs-rmfb.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-1/igt@kms_flip@flip-vs-rmfb.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [PASS][31] -> [DMESG-WARN][32] ([Intel XE#4543]) +5 other tests dmesg-warn
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-3/igt@kms_flip@flip-vs-suspend-interruptible.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-adlp: [PASS][33] -> [SKIP][34] ([Intel XE#4947]) +3 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#651])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][36] ([Intel XE#651]) +15 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][37] ([Intel XE#656])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#658])
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][39] ([Intel XE#653]) +10 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#2927])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-adlp: [PASS][41] -> [SKIP][42] ([Intel XE#4962])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_pm_rpm@dpms-lpsp.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@universal-planes-dpms@plane-43:
- shard-adlp: [PASS][43] -> [DMESG-WARN][44] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-3/igt@kms_pm_rpm@universal-planes-dpms@plane-43.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_pm_rpm@universal-planes-dpms@plane-43.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][45] ([Intel XE#1489]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@fbc-psr2-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][46] ([Intel XE#2850] / [Intel XE#929]) +7 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@kms_psr@fbc-psr2-dpms.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-dg2-set2: NOTRUN -> [SKIP][47] ([Intel XE#1127])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2-set2: NOTRUN -> [SKIP][48] ([Intel XE#3414])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-434/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#2426])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vblank@ts-continuation-suspend:
- shard-adlp: [PASS][50] -> [SKIP][51] ([Intel XE#4950]) +18 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_vblank@ts-continuation-suspend.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_vblank@ts-continuation-suspend.html
* igt@kms_vrr@flip-dpms:
- shard-dg2-set2: NOTRUN -> [SKIP][52] ([Intel XE#455]) +11 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@kms_vrr@flip-dpms.html
* igt@xe_copy_basic@mem-set-linear-0x3fff:
- shard-dg2-set2: NOTRUN -> [SKIP][53] ([Intel XE#1126])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_copy_basic@mem-set-linear-0x3fff.html
* igt@xe_eudebug@basic-vm-bind-metadata-discovery:
- shard-dg2-set2: NOTRUN -> [SKIP][54] ([Intel XE#4837]) +5 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
- shard-dg2-set2: [PASS][55] -> [SKIP][56] ([Intel XE#1392]) +2 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-466/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html
* igt@xe_exec_fault_mode@twice-userptr-rebind-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][57] ([Intel XE#288]) +14 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-adlp: [PASS][58] -> [DMESG-WARN][59] ([Intel XE#3876])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-8/igt@xe_exec_reset@parallel-gt-reset.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-6/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_exec_system_allocator@many-large-malloc-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][60] ([Intel XE#4915]) +113 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@xe_exec_system_allocator@many-large-malloc-nomemset.html
* igt@xe_module_load@load:
- shard-dg2-set2: ([PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84]) -> ([PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [SKIP][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110]) ([Intel XE#378])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-432/igt@xe_module_load@load.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-432/igt@xe_module_load@load.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-432/igt@xe_module_load@load.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-435/igt@xe_module_load@load.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-433/igt@xe_module_load@load.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-433/igt@xe_module_load@load.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-464/igt@xe_module_load@load.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-435/igt@xe_module_load@load.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-463/igt@xe_module_load@load.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-463/igt@xe_module_load@load.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-463/igt@xe_module_load@load.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-434/igt@xe_module_load@load.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-435/igt@xe_module_load@load.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-435/igt@xe_module_load@load.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-466/igt@xe_module_load@load.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-466/igt@xe_module_load@load.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-464/igt@xe_module_load@load.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-432/igt@xe_module_load@load.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-434/igt@xe_module_load@load.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-434/igt@xe_module_load@load.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-436/igt@xe_module_load@load.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-436/igt@xe_module_load@load.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-436/igt@xe_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-434/igt@xe_module_load@load.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@xe_module_load@load.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-436/igt@xe_module_load@load.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-436/igt@xe_module_load@load.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@xe_module_load@load.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-432/igt@xe_module_load@load.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-432/igt@xe_module_load@load.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-432/igt@xe_module_load@load.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_module_load@load.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-436/igt@xe_module_load@load.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-434/igt@xe_module_load@load.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-463/igt@xe_module_load@load.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-463/igt@xe_module_load@load.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-463/igt@xe_module_load@load.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-436/igt@xe_module_load@load.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_module_load@load.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-434/igt@xe_module_load@load.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-435/igt@xe_module_load@load.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-435/igt@xe_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-464/igt@xe_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-463/igt@xe_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-435/igt@xe_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-464/igt@xe_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-464/igt@xe_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@xe_module_load@load.html
* igt@xe_oa@non-privileged-map-oa-buffer:
- shard-dg2-set2: NOTRUN -> [SKIP][111] ([Intel XE#3573]) +3 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@xe_oa@non-privileged-map-oa-buffer.html
* igt@xe_pat@pat-index-xehpc:
- shard-lnl: NOTRUN -> [SKIP][112] ([Intel XE#1420] / [Intel XE#2838])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-lnl-1/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pm@d3cold-basic-exec:
- shard-dg2-set2: NOTRUN -> [SKIP][113] ([Intel XE#2284] / [Intel XE#366])
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_pm@d3cold-basic-exec.html
* igt@xe_pxp@pxp-stale-queue-post-suspend:
- shard-bmg: NOTRUN -> [SKIP][114] ([Intel XE#4733])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-3/igt@xe_pxp@pxp-stale-queue-post-suspend.html
* igt@xe_query@multigpu-query-topology:
- shard-dg2-set2: NOTRUN -> [SKIP][115] ([Intel XE#944])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_query@multigpu-query-topology.html
* igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
- shard-adlp: [PASS][116] -> [SKIP][117] ([Intel XE#4945]) +31 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
* igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs:
- shard-dg2-set2: NOTRUN -> [SKIP][118] ([Intel XE#4130])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-433/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs.html
* igt@xe_sriov_flr@flr-twice:
- shard-dg2-set2: NOTRUN -> [SKIP][119] ([Intel XE#4273])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-466/igt@xe_sriov_flr@flr-twice.html
#### Possible fixes ####
* igt@kms_atomic_transition@modeset-transition:
- shard-adlp: [DMESG-WARN][120] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][121] +7 other tests pass
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-8/igt@kms_atomic_transition@modeset-transition.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-4/igt@kms_atomic_transition@modeset-transition.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: [INCOMPLETE][122] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][124] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-dp-4:
- shard-dg2-set2: [INCOMPLETE][126] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-dp-4.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-d-dp-4.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-bmg: [SKIP][128] ([Intel XE#2316]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-6/igt@kms_flip@2x-absolute-wf_vblank.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-2/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-bmg: [INCOMPLETE][130] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][131] +1 other test pass
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-7/igt@kms_flip@flip-vs-suspend-interruptible.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][132] ([Intel XE#4543]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-3/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-3/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2:
- shard-bmg: [FAIL][134] ([Intel XE#3098]) -> [PASS][135] +1 other test pass
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-4/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-7/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2.html
* igt@kms_pm_dc@dc6-dpms:
- shard-adlp: [FAIL][136] ([Intel XE#718]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-1/igt@kms_pm_dc@dc6-dpms.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-8/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_setmode@basic:
- shard-bmg: [FAIL][138] ([Intel XE#2883]) -> [PASS][139] +6 other tests pass
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-4/igt@kms_setmode@basic.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-4/igt@kms_setmode@basic.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
- shard-dg2-set2: [SKIP][140] ([Intel XE#1392]) -> [PASS][141] +4 other tests pass
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-dg2-436/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
- shard-lnl: [FAIL][142] ([Intel XE#5018]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
#### Warnings ####
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-adlp: [SKIP][144] ([Intel XE#607]) -> [SKIP][145] ([Intel XE#4947])
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
- shard-adlp: [DMESG-FAIL][146] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543]) -> [DMESG-FAIL][147] ([Intel XE#4543])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-adlp: [SKIP][148] ([Intel XE#1124]) -> [SKIP][149] ([Intel XE#2351] / [Intel XE#4947])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-adlp: [SKIP][150] ([Intel XE#1124]) -> [SKIP][151] ([Intel XE#4947])
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
- shard-adlp: [SKIP][152] ([Intel XE#2191]) -> [SKIP][153] ([Intel XE#4950])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-3-displays-2560x1440p:
- shard-adlp: [SKIP][154] ([Intel XE#367]) -> [SKIP][155] ([Intel XE#4950])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
- shard-adlp: [SKIP][156] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][157] ([Intel XE#4947]) +3 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-adlp: [SKIP][158] ([Intel XE#373]) -> [SKIP][159] ([Intel XE#4950]) +1 other test skip
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_chamelium_frames@vga-frame-dump.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_content_protection@lic-type-0:
- shard-bmg: [SKIP][160] ([Intel XE#2341]) -> [FAIL][161] ([Intel XE#1178])
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-6/igt@kms_content_protection@lic-type-0.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-4/igt@kms_content_protection@lic-type-0.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-adlp: [SKIP][162] ([Intel XE#308]) -> [SKIP][163] ([Intel XE#4950])
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_cursor_crc@cursor-onscreen-512x512.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-adlp: [SKIP][164] ([Intel XE#309]) -> [SKIP][165] ([Intel XE#4950])
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_dsc@dsc-basic:
- shard-adlp: [SKIP][166] ([Intel XE#455]) -> [SKIP][167] ([Intel XE#2351] / [Intel XE#4947])
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_dsc@dsc-basic.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_dsc@dsc-basic.html
* igt@kms_feature_discovery@display-2x:
- shard-adlp: [SKIP][168] ([Intel XE#702]) -> [SKIP][169] ([Intel XE#4950])
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_feature_discovery@display-2x.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-adlp: [SKIP][170] ([Intel XE#310]) -> [SKIP][171] ([Intel XE#4950]) +2 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
- shard-adlp: [SKIP][172] ([Intel XE#455]) -> [SKIP][173] ([Intel XE#4947])
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render:
- shard-adlp: [SKIP][174] ([Intel XE#651]) -> [SKIP][175] ([Intel XE#4947]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][176] ([Intel XE#2312]) -> [SKIP][177] ([Intel XE#2311]) +4 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][178] ([Intel XE#2311]) -> [SKIP][179] ([Intel XE#2312]) +2 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][180] ([Intel XE#2312]) -> [SKIP][181] ([Intel XE#5390])
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
- shard-bmg: [SKIP][182] ([Intel XE#5390]) -> [SKIP][183] ([Intel XE#2312])
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt:
- shard-adlp: [SKIP][184] ([Intel XE#651]) -> [SKIP][185] ([Intel XE#2351] / [Intel XE#4947]) +1 other test skip
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-adlp: [SKIP][186] ([Intel XE#653]) -> [SKIP][187] ([Intel XE#4947]) +1 other test skip
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
- shard-bmg: [SKIP][188] ([Intel XE#2312]) -> [SKIP][189] ([Intel XE#2313]) +5 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][190] ([Intel XE#2313]) -> [SKIP][191] ([Intel XE#2312]) +1 other test skip
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-render.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-adlp: [SKIP][192] ([Intel XE#656]) -> [SKIP][193] ([Intel XE#4947]) +6 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-adlp: [SKIP][194] ([Intel XE#346]) -> [SKIP][195] ([Intel XE#4947])
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_joiner@invalid-modeset-big-joiner.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_pm_dc@dc9-dpms:
- shard-adlp: [FAIL][196] ([Intel XE#3325]) -> [SKIP][197] ([Intel XE#734])
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-8/igt@kms_pm_dc@dc9-dpms.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-3/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
- shard-adlp: [SKIP][198] ([Intel XE#1489]) -> [SKIP][199] ([Intel XE#4947])
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@fbc-pr-no-drrs:
- shard-adlp: [SKIP][200] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][201] ([Intel XE#4947])
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_psr@fbc-pr-no-drrs.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_psr@fbc-pr-no-drrs.html
* igt@kms_psr@psr-cursor-plane-move:
- shard-adlp: [SKIP][202] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][203] ([Intel XE#2351] / [Intel XE#4947]) +2 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_psr@psr-cursor-plane-move.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_psr@psr-cursor-plane-move.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-adlp: [SKIP][204] ([Intel XE#362]) -> [SKIP][205] ([Intel XE#4950])
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_ccs@large-ctrl-surf-copy:
- shard-adlp: [SKIP][206] ([Intel XE#3576]) -> [SKIP][207] ([Intel XE#4945])
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_ccs@large-ctrl-surf-copy.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_ccs@large-ctrl-surf-copy.html
* igt@xe_eu_stall@blocking-re-enable:
- shard-adlp: [SKIP][208] -> [SKIP][209] ([Intel XE#4945])
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_eu_stall@blocking-re-enable.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_eu_stall@blocking-re-enable.html
* igt@xe_evict@evict-beng-small-external:
- shard-adlp: [SKIP][210] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688]) -> [SKIP][211] ([Intel XE#4945])
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_evict@evict-beng-small-external.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_evict@evict-beng-small-external.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap:
- shard-adlp: [SKIP][212] ([Intel XE#1392] / [Intel XE#5575]) -> [SKIP][213] ([Intel XE#4945]) +1 other test skip
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-mmap.html
* igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm:
- shard-adlp: [SKIP][214] ([Intel XE#288] / [Intel XE#5561]) -> [SKIP][215] ([Intel XE#4945]) +6 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm.html
* igt@xe_exec_sip_eudebug@breakpoint-waitsip-heavy:
- shard-adlp: [SKIP][216] ([Intel XE#4837] / [Intel XE#5565]) -> [SKIP][217] ([Intel XE#4945]) +1 other test skip
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_exec_sip_eudebug@breakpoint-waitsip-heavy.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_exec_sip_eudebug@breakpoint-waitsip-heavy.html
* igt@xe_exec_system_allocator@many-stride-free:
- shard-adlp: [SKIP][218] ([Intel XE#4915] / [Intel XE#5560]) -> [SKIP][219] ([Intel XE#4945]) +57 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_exec_system_allocator@many-stride-free.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_exec_system_allocator@many-stride-free.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-adlp: [ABORT][220] ([Intel XE#4917] / [Intel XE#5530]) -> [ABORT][221] ([Intel XE#5530])
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
* igt@xe_oa@invalid-remove-userspace-config:
- shard-adlp: [SKIP][222] ([Intel XE#3573]) -> [SKIP][223] ([Intel XE#4945]) +1 other test skip
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_oa@invalid-remove-userspace-config.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_oa@invalid-remove-userspace-config.html
* igt@xe_pxp@pxp-stale-bo-exec-post-suspend:
- shard-adlp: [SKIP][224] ([Intel XE#4733] / [Intel XE#5594]) -> [SKIP][225] ([Intel XE#4945])
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_pxp@pxp-stale-bo-exec-post-suspend.html
* igt@xe_query@multigpu-query-pxp-status:
- shard-adlp: [SKIP][226] ([Intel XE#944]) -> [SKIP][227] ([Intel XE#4945])
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268/shard-adlp-6/igt@xe_query@multigpu-query-pxp-status.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/shard-adlp-9/igt@xe_query@multigpu-query-pxp-status.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
[Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
[Intel XE#3325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3325
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#3576]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3576
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#4945]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4945
[Intel XE#4947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4947
[Intel XE#4950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4950
[Intel XE#4962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4962
[Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
[Intel XE#5338]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5338
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
[Intel XE#5560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5560
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
[Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
[Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
[Intel XE#734]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/734
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268 -> xe-pw-138256v5
IGT_8468: 8468
xe-3446-ab5c1718e3b878411f5fd2c6841db98e4f21f268: ab5c1718e3b878411f5fd2c6841db98e4f21f268
xe-pw-138256v5: 138256v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138256v5/index.html
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