[PATCH 0/7] drm/i915/dp: DP stuff

[PATCH 0/7] drm/i915/dp: DP stuff

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A few DP related things:
- Fix 2.7 Gbps link training on g4x
- Adjust the idle pattern handling (most of this was part
  of my POST_LT_ADJ_REQ series earlier, but I reordered
  things to leave the actual POST_LT_ADJ_REQ support for
  later)
- shuffle the link training code a bit (again prep stuff
  for the POST_LT_ADJ_REQ support)

Ville Syrjälä (7):
  drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x
  drm/i915/dp: Don't switch to idle pattern before disable on pre-hsw
  drm/i915/dp: Clear DPCD training pattern before transmitting the idle
    pattern
  drm/i915/dp: Have intel_dp_get_adjust_train() tell us if anything
    changed
  drm/i915/dp: Move intel_dp_training_pattern()
  drm/i915/dp: Implement .set_idle_link_train() for everyone
  drm/i915/dp: Make .set_idle_link_train() mandatory

 drivers/gpu/drm/i915/display/g4x_dp.c         |  44 ++++--
 drivers/gpu/drm/i915/display/intel_dp.c       |   6 +
 .../drm/i915/display/intel_dp_link_training.c | 137 +++++++++---------
 .../drm/i915/display/intel_dp_link_training.h |   2 +-
 4 files changed, 110 insertions(+), 79 deletions(-)

-- 
2.49.0

[PATCH 1/7] drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On g4x we currently use the 96MHz non-SSC refclk, which can't actually
generate an exact 2.7 Gbps link rate. In practice we end up with 2.688
Gbps which seems to be close enough to actually work, but link training
is currently failing due to miscalculating the DP_LINK_BW value (we
calcualte it directly from port_clock which reflects the actual PLL
outpout frequency).

Ideas how to fix this:
- nudge port_clock back up to 270000 during PLL computation/readout
- track port_clock and the nominal link rate separately so they might
  differ a bit
- switch to the 100MHz refclk, but that one should be SSC so perhaps
  not something we want

While we ponder about a better solution apply some band aid to the
immediate issue of miscalculated DP_LINK_BW value. With this
I can again use 2.7 Gbps link rate on g4x.

Cc: stable@vger.kernel.org
Fixes: 665a7b04092c ("drm/i915: Feed the DPLL output freq back into crtc_state")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f48912f308df..7976fec88606 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1606,6 +1606,12 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 			   u8 *link_bw, u8 *rate_select)
 {
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	/* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */
+	if (display->platform.g4x && port_clock == 268800)
+		port_clock = 270000;
+
 	/* eDP 1.4 rate select method. */
 	if (intel_dp->use_rate_select) {
 		*link_bw = 0;
-- 
2.49.0

[PATCH 2/7] drm/i915/dp: Don't switch to idle pattern before disable on pre-hsw

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For some reason we are switching over to the idle pattern before
disabling the DP port on pre-hsw. AFAICS this has never been part
of the documented sequence (and on hsw+ the spec explicitly says
not to do this). Get rid of it.

The code goes all the way back to commit 5eb08b69f510 ("drm/i915: enable
DisplayPort support on IGDNG"), and it was accompanied by a 17ms delay
which got changed to vbl wait in commit ab527efc2fea ("drm/i915: use
wait_for_vblank instead of msleep(17)"), and was later completely removed
in  commit 93c9c19b3d25 ("drm/i915: remove unexplained vblank wait in
the DP off code").

Smoke tested on g4x/snb/chv.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 87f6b9602b16..b54edf0d1c23 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -424,17 +424,6 @@ intel_dp_link_down(struct intel_encoder *encoder,
 
 	drm_dbg_kms(display->drm, "\n");
 
-	if ((display->platform.ivybridge && port == PORT_A) ||
-	    (HAS_PCH_CPT(display) && port != PORT_A)) {
-		intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
-		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
-	} else {
-		intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
-		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
-	}
-	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
-	intel_de_posting_read(display, intel_dp->output_reg);
-
 	intel_dp->DP &= ~DP_PORT_EN;
 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
 	intel_de_posting_read(display, intel_dp->output_reg);
-- 
2.49.0

[PATCH 3/7] drm/i915/dp: Clear DPCD training pattern before transmitting the idle pattern

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We are supposed to switch off the training pattern in DPCD before
we start transmitting the idle pattern. For LTTPRs we do that
correctly, but for the sink DPRX we only do this correctly
for some platforms.

On pre-HSW (where we don't implement the .set_idle_link_train()
hook), we directly switch from transmitting the training pattern
to normal pixel transmission (the hardware should hopefully
guarantee that the minimum number of required idle patters will
be transmitted during this transition). The DPCD write correctly
precedes the actual switch away from the training pattern.

For HSW+ we start transmitting the idle pattern earlier, and only
switch off the DPCD training pattern after we switch from the idle
pattern to normal pixel transmission. Adjust the code to disable
the DPCD training pattern before we start transmitting the idle
pattern.

v2: Tweak the commit message a bit

Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a479b63112ea..322a26c1910c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1130,7 +1130,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
 
 	intel_dp->link.active = true;
 
-	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
+	if (!intel_dp->set_idle_link_train)
+		intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
+
 	intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
 					       DP_TRAINING_PATTERN_DISABLE);
 
@@ -1371,8 +1373,10 @@ intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
 	if (ret)
 		ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
 
-	if (intel_dp->set_idle_link_train)
+	if (intel_dp->set_idle_link_train) {
+		intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
 		intel_dp->set_idle_link_train(intel_dp, crtc_state);
+	}
 
 	return ret;
 }
-- 
2.49.0

[PATCH 4/7] drm/i915/dp: Have intel_dp_get_adjust_train() tell us if anything changed

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In order to implement the POST_LT_ADJ_REQ sequence we need to
know whether the sink actually requested a changed to the
vswing/pre-emph values.

Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_dp_link_training.c  | 18 +++++++++++++-----
 .../drm/i915/display/intel_dp_link_training.h  |  2 +-
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 322a26c1910c..57b9dc52a98d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -478,12 +478,13 @@ static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
 	_TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
 
-void
+bool
 intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			  const struct intel_crtc_state *crtc_state,
 			  enum drm_dp_phy dp_phy,
 			  const u8 link_status[DP_LINK_STATUS_SIZE])
 {
+	bool changed = false;
 	int lane;
 
 	if (intel_dp_is_uhbr(crtc_state)) {
@@ -502,10 +503,17 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 		       TRAIN_REQ_PREEMPH_ARGS(link_status));
 	}
 
-	for (lane = 0; lane < 4; lane++)
-		intel_dp->train_set[lane] =
-			intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
-						       dp_phy, link_status, lane);
+	for (lane = 0; lane < 4; lane++) {
+		u8 new = intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
+							dp_phy, link_status, lane);
+		if (intel_dp->train_set[lane] == new)
+			continue;
+
+		intel_dp->train_set[lane] = new;
+		changed = true;
+	}
+
+	return changed;
 }
 
 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 46614124569f..1ba22ed6db08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -23,7 +23,7 @@ void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 				   int link_bw, int rate_select, int lane_count,
 				   bool enhanced_framing);
 
-void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+bool intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state,
 			       enum drm_dp_phy dp_phy,
 			       const u8 link_status[DP_LINK_STATUS_SIZE]);
-- 
2.49.0

[PATCH 5/7] drm/i915/dp: Move intel_dp_training_pattern()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move intel_dp_training_pattern() upwards to avoid the forward
declaration for the POST_LT_ADJ_REQ stuff.

Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_dp_link_training.c | 114 +++++++++---------
 1 file changed, 57 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 57b9dc52a98d..cb3870427f3f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -766,6 +766,63 @@ void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 	}
 }
 
+/*
+ * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
+ * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
+ * 1.2 devices that support it, TPS2 otherwise.
+ */
+static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state,
+				     enum drm_dp_phy dp_phy)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
+
+	/* UHBR+ use separate 128b/132b TPS2 */
+	if (intel_dp_is_uhbr(crtc_state))
+		return DP_TRAINING_PATTERN_2;
+
+	/*
+	 * TPS4 support is mandatory for all downstream devices that
+	 * support HBR3. There are no known eDP panels that support
+	 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
+	 * LTTPRs must support TPS4.
+	 */
+	source_tps4 = intel_dp_source_supports_tps4(display);
+	sink_tps4 = dp_phy != DP_PHY_DPRX ||
+		    drm_dp_tps4_supported(intel_dp->dpcd);
+	if (source_tps4 && sink_tps4) {
+		return DP_TRAINING_PATTERN_4;
+	} else if (crtc_state->port_clock == 810000) {
+		if (!source_tps4)
+			lt_dbg(intel_dp, dp_phy,
+			       "8.1 Gbps link rate without source TPS4 support\n");
+		if (!sink_tps4)
+			lt_dbg(intel_dp, dp_phy,
+			       "8.1 Gbps link rate without sink TPS4 support\n");
+	}
+
+	/*
+	 * TPS3 support is mandatory for downstream devices that
+	 * support HBR2. However, not all sinks follow the spec.
+	 */
+	source_tps3 = intel_dp_source_supports_tps3(display);
+	sink_tps3 = dp_phy != DP_PHY_DPRX ||
+		    drm_dp_tps3_supported(intel_dp->dpcd);
+	if (source_tps3 && sink_tps3) {
+		return  DP_TRAINING_PATTERN_3;
+	} else if (crtc_state->port_clock >= 540000) {
+		if (!source_tps3)
+			lt_dbg(intel_dp, dp_phy,
+			       ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
+		if (!sink_tps3)
+			lt_dbg(intel_dp, dp_phy,
+			       ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
+	}
+
+	return DP_TRAINING_PATTERN_2;
+}
+
 static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
 					const struct intel_crtc_state *crtc_state,
 					u8 link_bw, u8 rate_select)
@@ -957,63 +1014,6 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 	return false;
 }
 
-/*
- * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
- * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
- * 1.2 devices that support it, TPS2 otherwise.
- */
-static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
-				     const struct intel_crtc_state *crtc_state,
-				     enum drm_dp_phy dp_phy)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
-
-	/* UHBR+ use separate 128b/132b TPS2 */
-	if (intel_dp_is_uhbr(crtc_state))
-		return DP_TRAINING_PATTERN_2;
-
-	/*
-	 * TPS4 support is mandatory for all downstream devices that
-	 * support HBR3. There are no known eDP panels that support
-	 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
-	 * LTTPRs must support TPS4.
-	 */
-	source_tps4 = intel_dp_source_supports_tps4(display);
-	sink_tps4 = dp_phy != DP_PHY_DPRX ||
-		    drm_dp_tps4_supported(intel_dp->dpcd);
-	if (source_tps4 && sink_tps4) {
-		return DP_TRAINING_PATTERN_4;
-	} else if (crtc_state->port_clock == 810000) {
-		if (!source_tps4)
-			lt_dbg(intel_dp, dp_phy,
-			       "8.1 Gbps link rate without source TPS4 support\n");
-		if (!sink_tps4)
-			lt_dbg(intel_dp, dp_phy,
-			       "8.1 Gbps link rate without sink TPS4 support\n");
-	}
-
-	/*
-	 * TPS3 support is mandatory for downstream devices that
-	 * support HBR2. However, not all sinks follow the spec.
-	 */
-	source_tps3 = intel_dp_source_supports_tps3(display);
-	sink_tps3 = dp_phy != DP_PHY_DPRX ||
-		    drm_dp_tps3_supported(intel_dp->dpcd);
-	if (source_tps3 && sink_tps3) {
-		return  DP_TRAINING_PATTERN_3;
-	} else if (crtc_state->port_clock >= 540000) {
-		if (!source_tps3)
-			lt_dbg(intel_dp, dp_phy,
-			       ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
-		if (!sink_tps3)
-			lt_dbg(intel_dp, dp_phy,
-			       ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
-	}
-
-	return DP_TRAINING_PATTERN_2;
-}
-
 /*
  * Perform the link training channel equalization phase on the given DP PHY
  * using one of training pattern 2, 3 or 4 depending on the source and
-- 
2.49.0

[PATCH 6/7] drm/i915/dp: Implement .set_idle_link_train() for everyone

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All platforms are capable of explicitly transmitting the idle
pattern. Implement it for everyone (so far it as implemented
only for HSW+).

The immediate benefit is that we gain the possibility of
implementing the POST_LT_ADJ_REQ sequence for all platforms.

Another potential future use would be a pseudo port sync mode on
pre-BDW where we attempt to sync up multiple ports/pipes by trying
to turn on the transcoders at the same time, and switching the
links to normal pixel transmission at the same time.

I'm not 100% sure the hardware is guaranteed to transmit the
required number of idle patterns (5) when switching away from
training pattern (either via explicit idle pattern, or straight
to the normal pixel output). Would be nice to confirm that at
some point, but for now let's assume it happens correctly in
both cases.

v2: Elaborate a bit more on the min required idle patterns

Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c | 33 +++++++++++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index b54edf0d1c23..846dbd8ae931 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -600,6 +600,19 @@ cpt_set_link_train(struct intel_dp *intel_dp,
 	intel_de_posting_read(display, intel_dp->output_reg);
 }
 
+static void
+cpt_set_idle_link_train(struct intel_dp *intel_dp,
+			const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
+	intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
+
+	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
+	intel_de_posting_read(display, intel_dp->output_reg);
+}
+
 static void
 g4x_set_link_train(struct intel_dp *intel_dp,
 		   const struct intel_crtc_state *crtc_state,
@@ -628,6 +641,19 @@ g4x_set_link_train(struct intel_dp *intel_dp,
 	intel_de_posting_read(display, intel_dp->output_reg);
 }
 
+static void
+g4x_set_idle_link_train(struct intel_dp *intel_dp,
+			const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
+	intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
+
+	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
+	intel_de_posting_read(display, intel_dp->output_reg);
+}
+
 static void intel_dp_enable_port(struct intel_dp *intel_dp,
 				 const struct intel_crtc_state *crtc_state)
 {
@@ -1331,10 +1357,13 @@ bool g4x_dp_init(struct intel_display *display,
 	intel_encoder->audio_disable = g4x_dp_audio_disable;
 
 	if ((display->platform.ivybridge && port == PORT_A) ||
-	    (HAS_PCH_CPT(display) && port != PORT_A))
+	    (HAS_PCH_CPT(display) && port != PORT_A)) {
 		dig_port->dp.set_link_train = cpt_set_link_train;
-	else
+		dig_port->dp.set_idle_link_train = cpt_set_idle_link_train;
+	} else {
 		dig_port->dp.set_link_train = g4x_set_link_train;
+		dig_port->dp.set_idle_link_train = g4x_set_idle_link_train;
+	}
 
 	if (display->platform.cherryview)
 		intel_encoder->set_signal_levels = chv_set_signal_levels;
-- 
2.49.0

[PATCH 7/7] drm/i915/dp: Make .set_idle_link_train() mandatory

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Everyone implements the .set_idle_link_train() hook now.
Just make it mandatory.

Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index cb3870427f3f..344b74109a83 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1138,9 +1138,6 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp,
 
 	intel_dp->link.active = true;
 
-	if (!intel_dp->set_idle_link_train)
-		intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
-
 	intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
 					       DP_TRAINING_PATTERN_DISABLE);
 
@@ -1381,10 +1378,8 @@ intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
 	if (ret)
 		ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
 
-	if (intel_dp->set_idle_link_train) {
-		intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
-		intel_dp->set_idle_link_train(intel_dp, crtc_state);
-	}
+	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
+	intel_dp->set_idle_link_train(intel_dp, crtc_state);
 
 	return ret;
 }
-- 
2.49.0

✓ CI.KUnit: success for drm/i915/dp: DP stuff

[Patchwork]

== Series Details ==

Series: drm/i915/dp: DP stuff
URL   : https://patchwork.freedesktop.org/series/151464/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:53:48] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:53:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:54:19] Starting KUnit Kernel (1/1)...
[20:54:19] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:54:20] ================== guc_buf (11 subtests) ===================
[20:54:20] [PASSED] test_smallest
[20:54:20] [PASSED] test_largest
[20:54:20] [PASSED] test_granular
[20:54:20] [PASSED] test_unique
[20:54:20] [PASSED] test_overlap
[20:54:20] [PASSED] test_reusable
[20:54:20] [PASSED] test_too_big
[20:54:20] [PASSED] test_flush
[20:54:20] [PASSED] test_lookup
[20:54:20] [PASSED] test_data
[20:54:20] [PASSED] test_class
[20:54:20] ===================== [PASSED] guc_buf =====================
[20:54:20] =================== guc_dbm (7 subtests) ===================
[20:54:20] [PASSED] test_empty
[20:54:20] [PASSED] test_default
[20:54:20] ======================== test_size  ========================
[20:54:20] [PASSED] 4
[20:54:20] [PASSED] 8
[20:54:20] [PASSED] 32
[20:54:20] [PASSED] 256
[20:54:20] ==================== [PASSED] test_size ====================
[20:54:20] ======================= test_reuse  ========================
[20:54:20] [PASSED] 4
[20:54:20] [PASSED] 8
[20:54:20] [PASSED] 32
[20:54:20] [PASSED] 256
[20:54:20] =================== [PASSED] test_reuse ====================
[20:54:20] =================== test_range_overlap  ====================
[20:54:20] [PASSED] 4
[20:54:20] [PASSED] 8
[20:54:20] [PASSED] 32
[20:54:20] [PASSED] 256
[20:54:20] =============== [PASSED] test_range_overlap ================
[20:54:20] =================== test_range_compact  ====================
[20:54:20] [PASSED] 4
[20:54:20] [PASSED] 8
[20:54:20] [PASSED] 32
[20:54:20] [PASSED] 256
[20:54:20] =============== [PASSED] test_range_compact ================
[20:54:20] ==================== test_range_spare  =====================
[20:54:20] [PASSED] 4
[20:54:20] [PASSED] 8
[20:54:20] [PASSED] 32
[20:54:20] [PASSED] 256
[20:54:20] ================ [PASSED] test_range_spare =================
[20:54:20] ===================== [PASSED] guc_dbm =====================
[20:54:20] =================== guc_idm (6 subtests) ===================
[20:54:20] [PASSED] bad_init
[20:54:20] [PASSED] no_init
[20:54:20] [PASSED] init_fini
[20:54:20] [PASSED] check_used
[20:54:20] [PASSED] check_quota
[20:54:20] [PASSED] check_all
[20:54:20] ===================== [PASSED] guc_idm =====================
[20:54:20] ================== no_relay (3 subtests) ===================
[20:54:20] [PASSED] xe_drops_guc2pf_if_not_ready
[20:54:20] [PASSED] xe_drops_guc2vf_if_not_ready
[20:54:20] [PASSED] xe_rejects_send_if_not_ready
[20:54:20] ==================== [PASSED] no_relay =====================
[20:54:20] ================== pf_relay (14 subtests) ==================
[20:54:20] [PASSED] pf_rejects_guc2pf_too_short
[20:54:20] [PASSED] pf_rejects_guc2pf_too_long
[20:54:20] [PASSED] pf_rejects_guc2pf_no_payload
[20:54:20] [PASSED] pf_fails_no_payload
[20:54:20] [PASSED] pf_fails_bad_origin
[20:54:20] [PASSED] pf_fails_bad_type
[20:54:20] [PASSED] pf_txn_reports_error
[20:54:20] [PASSED] pf_txn_sends_pf2guc
[20:54:20] [PASSED] pf_sends_pf2guc
[20:54:20] [SKIPPED] pf_loopback_nop
[20:54:20] [SKIPPED] pf_loopback_echo
[20:54:20] [SKIPPED] pf_loopback_fail
[20:54:20] [SKIPPED] pf_loopback_busy
[20:54:20] [SKIPPED] pf_loopback_retry
[20:54:20] ==================== [PASSED] pf_relay =====================
[20:54:20] ================== vf_relay (3 subtests) ===================
[20:54:20] [PASSED] vf_rejects_guc2vf_too_short
[20:54:20] [PASSED] vf_rejects_guc2vf_too_long
[20:54:20] [PASSED] vf_rejects_guc2vf_no_payload
[20:54:20] ==================== [PASSED] vf_relay =====================
[20:54:20] ================= pf_service (11 subtests) =================
[20:54:20] [PASSED] pf_negotiate_any
[20:54:20] [PASSED] pf_negotiate_base_match
[20:54:20] [PASSED] pf_negotiate_base_newer
[20:54:20] [PASSED] pf_negotiate_base_next
[20:54:20] [SKIPPED] pf_negotiate_base_older
[20:54:20] [PASSED] pf_negotiate_base_prev
[20:54:20] [PASSED] pf_negotiate_latest_match
[20:54:20] [PASSED] pf_negotiate_latest_newer
[20:54:20] [PASSED] pf_negotiate_latest_next
[20:54:20] [SKIPPED] pf_negotiate_latest_older
[20:54:20] [SKIPPED] pf_negotiate_latest_prev
[20:54:20] =================== [PASSED] pf_service ====================
[20:54:20] ===================== lmtt (1 subtest) =====================
[20:54:20] ======================== test_ops  =========================
[20:54:20] [PASSED] 2-level
[20:54:20] [PASSED] multi-level
[20:54:20] ==================== [PASSED] test_ops =====================
[20:54:20] ====================== [PASSED] lmtt =======================
[20:54:20] =================== xe_mocs (2 subtests) ===================
[20:54:20] ================ xe_live_mocs_kernel_kunit  ================
[20:54:20] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:54:20] ================ xe_live_mocs_reset_kunit  =================
[20:54:20] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:54:20] ==================== [SKIPPED] xe_mocs =====================
[20:54:20] ================= xe_migrate (2 subtests) ==================
[20:54:20] ================= xe_migrate_sanity_kunit  =================
[20:54:20] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:54:20] ================== xe_validate_ccs_kunit  ==================
[20:54:20] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:54:20] =================== [SKIPPED] xe_migrate ===================
[20:54:20] ================== xe_dma_buf (1 subtest) ==================
[20:54:20] ==================== xe_dma_buf_kunit  =====================
[20:54:20] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:54:20] =================== [SKIPPED] xe_dma_buf ===================
[20:54:20] ================= xe_bo_shrink (1 subtest) =================
[20:54:20] =================== xe_bo_shrink_kunit  ====================
[20:54:20] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:54:20] ================== [SKIPPED] xe_bo_shrink ==================
[20:54:20] ==================== xe_bo (2 subtests) ====================
[20:54:20] ================== xe_ccs_migrate_kunit  ===================
[20:54:20] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:54:20] ==================== xe_bo_evict_kunit  ====================
[20:54:20] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:54:20] ===================== [SKIPPED] xe_bo ======================
[20:54:20] ==================== args (11 subtests) ====================
[20:54:20] [PASSED] count_args_test
[20:54:20] [PASSED] call_args_example
[20:54:20] [PASSED] call_args_test
[20:54:20] [PASSED] drop_first_arg_example
[20:54:20] [PASSED] drop_first_arg_test
[20:54:20] [PASSED] first_arg_example
[20:54:20] [PASSED] first_arg_test
[20:54:20] [PASSED] last_arg_example
[20:54:20] [PASSED] last_arg_test
[20:54:20] [PASSED] pick_arg_example
[20:54:20] [PASSED] sep_comma_example
[20:54:20] ====================== [PASSED] args =======================
[20:54:20] =================== xe_pci (3 subtests) ====================
[20:54:20] ==================== check_graphics_ip  ====================
[20:54:20] [PASSED] 12.70 Xe_LPG
[20:54:20] [PASSED] 12.71 Xe_LPG
[20:54:20] [PASSED] 12.74 Xe_LPG+
[20:54:20] [PASSED] 20.01 Xe2_HPG
[20:54:20] [PASSED] 20.02 Xe2_HPG
[20:54:20] [PASSED] 20.04 Xe2_LPG
[20:54:20] [PASSED] 30.00 Xe3_LPG
[20:54:20] [PASSED] 30.01 Xe3_LPG
[20:54:20] [PASSED] 30.03 Xe3_LPG
[20:54:20] ================ [PASSED] check_graphics_ip ================
[20:54:20] ===================== check_media_ip  ======================
[20:54:20] [PASSED] 13.00 Xe_LPM+
[20:54:20] [PASSED] 13.01 Xe2_HPM
[20:54:20] [PASSED] 20.00 Xe2_LPM
[20:54:20] [PASSED] 30.00 Xe3_LPM
[20:54:20] [PASSED] 30.02 Xe3_LPM
[20:54:20] ================= [PASSED] check_media_ip ==================
[20:54:20] ================= check_platform_gt_count  =================
[20:54:20] [PASSED] 0x9A60 (TIGERLAKE)
[20:54:20] [PASSED] 0x9A68 (TIGERLAKE)
[20:54:20] [PASSED] 0x9A70 (TIGERLAKE)
[20:54:20] [PASSED] 0x9A40 (TIGERLAKE)
[20:54:20] [PASSED] 0x9A49 (TIGERLAKE)
[20:54:20] [PASSED] 0x9A59 (TIGERLAKE)
[20:54:20] [PASSED] 0x9A78 (TIGERLAKE)
[20:54:20] [PASSED] 0x9AC0 (TIGERLAKE)
[20:54:20] [PASSED] 0x9AC9 (TIGERLAKE)
[20:54:20] [PASSED] 0x9AD9 (TIGERLAKE)
[20:54:20] [PASSED] 0x9AF8 (TIGERLAKE)
[20:54:20] [PASSED] 0x4C80 (ROCKETLAKE)
[20:54:20] [PASSED] 0x4C8A (ROCKETLAKE)
[20:54:20] [PASSED] 0x4C8B (ROCKETLAKE)
[20:54:20] [PASSED] 0x4C8C (ROCKETLAKE)
[20:54:20] [PASSED] 0x4C90 (ROCKETLAKE)
[20:54:20] [PASSED] 0x4C9A (ROCKETLAKE)
[20:54:20] [PASSED] 0x4680 (ALDERLAKE_S)
[20:54:20] [PASSED] 0x4682 (ALDERLAKE_S)
[20:54:20] [PASSED] 0x4688 (ALDERLAKE_S)
[20:54:20] [PASSED] 0x468A (ALDERLAKE_S)
[20:54:20] [PASSED] 0x468B (ALDERLAKE_S)
[20:54:20] [PASSED] 0x4690 (ALDERLAKE_S)
[20:54:20] [PASSED] 0x4692 (ALDERLAKE_S)
[20:54:20] [PASSED] 0x4693 (ALDERLAKE_S)
[20:54:20] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46AA (ALDERLAKE_P)
[20:54:20] [PASSED] 0x462A (ALDERLAKE_P)
[20:54:20] [PASSED] 0x4626 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x4628 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:54:20] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:54:20] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:54:20] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:54:20] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:54:20] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:54:20] [PASSED] 0xA721 (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA720 (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:54:20] [PASSED] 0xA780 (ALDERLAKE_S)
[20:54:20] [PASSED] 0xA781 (ALDERLAKE_S)
[20:54:20] [PASSED] 0xA782 (ALDERLAKE_S)
[20:54:20] [PASSED] 0xA783 (ALDERLAKE_S)
[20:54:20] [PASSED] 0xA788 (ALDERLAKE_S)
[20:54:20] [PASSED] 0xA789 (ALDERLAKE_S)
[20:54:20] [PASSED] 0xA78A (ALDERLAKE_S)
[20:54:20] [PASSED] 0xA78B (ALDERLAKE_S)
[20:54:20] [PASSED] 0x4905 (DG1)
[20:54:20] [PASSED] 0x4906 (DG1)
[20:54:20] [PASSED] 0x4907 (DG1)
[20:54:20] [PASSED] 0x4908 (DG1)
[20:54:20] [PASSED] 0x4909 (DG1)
[20:54:20] [PASSED] 0x56C0 (DG2)
[20:54:20] [PASSED] 0x56C2 (DG2)
[20:54:20] [PASSED] 0x56C1 (DG2)
[20:54:20] [PASSED] 0x7D51 (METEORLAKE)
[20:54:20] [PASSED] 0x7DD1 (METEORLAKE)
[20:54:20] [PASSED] 0x7D41 (METEORLAKE)
[20:54:20] [PASSED] 0x7D67 (METEORLAKE)
[20:54:20] [PASSED] 0xB640 (METEORLAKE)
[20:54:20] [PASSED] 0x56A0 (DG2)
[20:54:20] [PASSED] 0x56A1 (DG2)
[20:54:20] [PASSED] 0x56A2 (DG2)
[20:54:20] [PASSED] 0x56BE (DG2)
[20:54:20] [PASSED] 0x56BF (DG2)
[20:54:20] [PASSED] 0x5690 (DG2)
[20:54:20] [PASSED] 0x5691 (DG2)
[20:54:20] [PASSED] 0x5692 (DG2)
[20:54:20] [PASSED] 0x56A5 (DG2)
[20:54:20] [PASSED] 0x56A6 (DG2)
[20:54:20] [PASSED] 0x56B0 (DG2)
[20:54:20] [PASSED] 0x56B1 (DG2)
[20:54:20] [PASSED] 0x56BA (DG2)
[20:54:20] [PASSED] 0x56BB (DG2)
[20:54:20] [PASSED] 0x56BC (DG2)
[20:54:20] [PASSED] 0x56BD (DG2)
[20:54:20] [PASSED] 0x5693 (DG2)
[20:54:20] [PASSED] 0x5694 (DG2)
[20:54:20] [PASSED] 0x5695 (DG2)
[20:54:20] [PASSED] 0x56A3 (DG2)
[20:54:20] [PASSED] 0x56A4 (DG2)
[20:54:20] [PASSED] 0x56B2 (DG2)
[20:54:20] [PASSED] 0x56B3 (DG2)
[20:54:20] [PASSED] 0x5696 (DG2)
[20:54:20] [PASSED] 0x5697 (DG2)
[20:54:20] [PASSED] 0xB69 (PVC)
[20:54:20] [PASSED] 0xB6E (PVC)
[20:54:20] [PASSED] 0xBD4 (PVC)
[20:54:20] [PASSED] 0xBD5 (PVC)
[20:54:20] [PASSED] 0xBD6 (PVC)
[20:54:20] [PASSED] 0xBD7 (PVC)
[20:54:20] [PASSED] 0xBD8 (PVC)
[20:54:20] [PASSED] 0xBD9 (PVC)
[20:54:20] [PASSED] 0xBDA (PVC)
[20:54:20] [PASSED] 0xBDB (PVC)
[20:54:20] [PASSED] 0xBE0 (PVC)
[20:54:20] [PASSED] 0xBE1 (PVC)
[20:54:20] [PASSED] 0xBE5 (PVC)
[20:54:20] [PASSED] 0x7D40 (METEORLAKE)
[20:54:20] [PASSED] 0x7D45 (METEORLAKE)
[20:54:20] [PASSED] 0x7D55 (METEORLAKE)
[20:54:20] [PASSED] 0x7D60 (METEORLAKE)
[20:54:20] [PASSED] 0x7DD5 (METEORLAKE)
[20:54:20] [PASSED] 0x6420 (LUNARLAKE)
[20:54:20] [PASSED] 0x64A0 (LUNARLAKE)
[20:54:20] [PASSED] 0x64B0 (LUNARLAKE)
[20:54:20] [PASSED] 0xE202 (BATTLEMAGE)
[20:54:20] [PASSED] 0xE209 (BATTLEMAGE)
[20:54:20] [PASSED] 0xE20B (BATTLEMAGE)
[20:54:20] [PASSED] 0xE20C (BATTLEMAGE)
[20:54:20] [PASSED] 0xE20D (BATTLEMAGE)
[20:54:20] [PASSED] 0xE210 (BATTLEMAGE)
[20:54:20] [PASSED] 0xE211 (BATTLEMAGE)
[20:54:20] [PASSED] 0xE212 (BATTLEMAGE)
[20:54:20] [PASSED] 0xE216 (BATTLEMAGE)
[20:54:20] [PASSED] 0xE220 (BATTLEMAGE)
[20:54:20] [PASSED] 0xE221 (BATTLEMAGE)
[20:54:20] [PASSED] 0xE222 (BATTLEMAGE)
[20:54:20] [PASSED] 0xE223 (BATTLEMAGE)
[20:54:20] [PASSED] 0xB080 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB081 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB082 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB083 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB084 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB085 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB086 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB087 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB08F (PANTHERLAKE)
[20:54:20] [PASSED] 0xB090 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:54:20] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:54:20] [PASSED] 0xFD80 (PANTHERLAKE)
[20:54:20] [PASSED] 0xFD81 (PANTHERLAKE)
[20:54:20] ============= [PASSED] check_platform_gt_count =============
[20:54:20] ===================== [PASSED] xe_pci ======================
[20:54:20] =================== xe_rtp (2 subtests) ====================
[20:54:20] =============== xe_rtp_process_to_sr_tests  ================
[20:54:20] [PASSED] coalesce-same-reg
[20:54:20] [PASSED] no-match-no-add
[20:54:20] [PASSED] match-or
[20:54:20] [PASSED] match-or-xfail
[20:54:20] [PASSED] no-match-no-add-multiple-rules
[20:54:20] [PASSED] two-regs-two-entries
[20:54:20] [PASSED] clr-one-set-other
[20:54:20] [PASSED] set-field
[20:54:20] [PASSED] conflict-duplicate
[20:54:20] [PASSED] conflict-not-disjoint
[20:54:20] [PASSED] conflict-reg-type
[20:54:20] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:54:20] ================== xe_rtp_process_tests  ===================
[20:54:20] [PASSED] active1
[20:54:20] [PASSED] active2
[20:54:20] [PASSED] active-inactive
[20:54:20] [PASSED] inactive-active
[20:54:20] [PASSED] inactive-1st_or_active-inactive
[20:54:20] [PASSED] inactive-2nd_or_active-inactive
[20:54:20] [PASSED] inactive-last_or_active-inactive
[20:54:20] [PASSED] inactive-no_or_active-inactive
[20:54:20] ============== [PASSED] xe_rtp_process_tests ===============
[20:54:20] ===================== [PASSED] xe_rtp ======================
[20:54:20] ==================== xe_wa (1 subtest) =====================
[20:54:20] ======================== xe_wa_gt  =========================
[20:54:20] [PASSED] TIGERLAKE (B0)
[20:54:20] [PASSED] DG1 (A0)
[20:54:20] [PASSED] DG1 (B0)
[20:54:20] [PASSED] ALDERLAKE_S (A0)
[20:54:20] [PASSED] ALDERLAKE_S (B0)
[20:54:20] [PASSED] ALDERLAKE_S (C0)
[20:54:20] [PASSED] ALDERLAKE_S (D0)
[20:54:20] [PASSED] ALDERLAKE_P (A0)
[20:54:20] [PASSED] ALDERLAKE_P (B0)
[20:54:20] [PASSED] ALDERLAKE_P (C0)
[20:54:20] [PASSED] ALDERLAKE_S_RPLS (D0)
[20:54:20] [PASSED] ALDERLAKE_P_RPLU (E0)
[20:54:20] [PASSED] DG2_G10 (C0)
[20:54:20] [PASSED] DG2_G11 (B1)
[20:54:20] [PASSED] DG2_G12 (A1)
[20:54:20] [PASSED] METEORLAKE (g:A0, m:A0)
[20:54:20] [PASSED] METEORLAKE (g:A0, m:A0)
[20:54:20] [PASSED] METEORLAKE (g:A0, m:A0)
[20:54:20] [PASSED] LUNARLAKE (g:A0, m:A0)
[20:54:20] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[20:54:20] [PASSED] BATTLEMAGE (g:A0, m:A1)
[20:54:20] ==================== [PASSED] xe_wa_gt =====================
[20:54:20] ====================== [PASSED] xe_wa ======================
[20:54:20] ============================================================
[20:54:20] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[20:54:20] Elapsed time: 31.536s total, 4.259s configuring, 26.958s building, 0.303s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:54:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:54:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:54:43] Starting KUnit Kernel (1/1)...
[20:54:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:54:43] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:54:43] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:54:43] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:54:43] =========== drm_validate_clone_mode (2 subtests) ===========
[20:54:43] ============== drm_test_check_in_clone_mode  ===============
[20:54:43] [PASSED] in_clone_mode
[20:54:43] [PASSED] not_in_clone_mode
[20:54:43] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:54:43] =============== drm_test_check_valid_clones  ===============
[20:54:43] [PASSED] not_in_clone_mode
[20:54:43] [PASSED] valid_clone
[20:54:43] [PASSED] invalid_clone
[20:54:43] =========== [PASSED] drm_test_check_valid_clones ===========
[20:54:43] ============= [PASSED] drm_validate_clone_mode =============
[20:54:43] ============= drm_validate_modeset (1 subtest) =============
[20:54:43] [PASSED] drm_test_check_connector_changed_modeset
[20:54:43] ============== [PASSED] drm_validate_modeset ===============
[20:54:43] ====== drm_test_bridge_get_current_state (2 subtests) ======
[20:54:43] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:54:43] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[20:54:43] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:54:43] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:54:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:54:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:54:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[20:54:43] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:54:43] ============== drm_bridge_alloc (2 subtests) ===============
[20:54:43] [PASSED] drm_test_drm_bridge_alloc_basic
[20:54:43] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:54:43] ================ [PASSED] drm_bridge_alloc =================
[20:54:43] ================== drm_buddy (7 subtests) ==================
[20:54:43] [PASSED] drm_test_buddy_alloc_limit
[20:54:43] [PASSED] drm_test_buddy_alloc_optimistic
[20:54:43] [PASSED] drm_test_buddy_alloc_pessimistic
[20:54:43] [PASSED] drm_test_buddy_alloc_pathological
[20:54:43] [PASSED] drm_test_buddy_alloc_contiguous
[20:54:43] [PASSED] drm_test_buddy_alloc_clear
[20:54:43] [PASSED] drm_test_buddy_alloc_range_bias
[20:54:43] ==================== [PASSED] drm_buddy ====================
[20:54:43] ============= drm_cmdline_parser (40 subtests) =============
[20:54:43] [PASSED] drm_test_cmdline_force_d_only
[20:54:43] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:54:43] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:54:43] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:54:43] [PASSED] drm_test_cmdline_force_e_only
[20:54:43] [PASSED] drm_test_cmdline_res
[20:54:43] [PASSED] drm_test_cmdline_res_vesa
[20:54:43] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:54:43] [PASSED] drm_test_cmdline_res_rblank
[20:54:43] [PASSED] drm_test_cmdline_res_bpp
[20:54:43] [PASSED] drm_test_cmdline_res_refresh
[20:54:43] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:54:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:54:43] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:54:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:54:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:54:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:54:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:54:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:54:43] [PASSED] drm_test_cmdline_res_margins_force_on
[20:54:43] [PASSED] drm_test_cmdline_res_vesa_margins
[20:54:43] [PASSED] drm_test_cmdline_name
[20:54:43] [PASSED] drm_test_cmdline_name_bpp
[20:54:43] [PASSED] drm_test_cmdline_name_option
[20:54:43] [PASSED] drm_test_cmdline_name_bpp_option
[20:54:43] [PASSED] drm_test_cmdline_rotate_0
[20:54:43] [PASSED] drm_test_cmdline_rotate_90
[20:54:43] [PASSED] drm_test_cmdline_rotate_180
[20:54:43] [PASSED] drm_test_cmdline_rotate_270
[20:54:43] [PASSED] drm_test_cmdline_hmirror
[20:54:43] [PASSED] drm_test_cmdline_vmirror
[20:54:43] [PASSED] drm_test_cmdline_margin_options
[20:54:43] [PASSED] drm_test_cmdline_multiple_options
[20:54:43] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:54:43] [PASSED] drm_test_cmdline_extra_and_option
[20:54:43] [PASSED] drm_test_cmdline_freestanding_options
[20:54:43] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:54:43] [PASSED] drm_test_cmdline_panel_orientation
[20:54:43] ================ drm_test_cmdline_invalid  =================
[20:54:43] [PASSED] margin_only
[20:54:43] [PASSED] interlace_only
[20:54:43] [PASSED] res_missing_x
[20:54:43] [PASSED] res_missing_y
[20:54:43] [PASSED] res_bad_y
[20:54:43] [PASSED] res_missing_y_bpp
[20:54:43] [PASSED] res_bad_bpp
[20:54:43] [PASSED] res_bad_refresh
[20:54:43] [PASSED] res_bpp_refresh_force_on_off
[20:54:43] [PASSED] res_invalid_mode
[20:54:43] [PASSED] res_bpp_wrong_place_mode
[20:54:43] [PASSED] name_bpp_refresh
[20:54:43] [PASSED] name_refresh
[20:54:43] [PASSED] name_refresh_wrong_mode
[20:54:43] [PASSED] name_refresh_invalid_mode
[20:54:43] [PASSED] rotate_multiple
[20:54:43] [PASSED] rotate_invalid_val
[20:54:43] [PASSED] rotate_truncated
[20:54:43] [PASSED] invalid_option
[20:54:43] [PASSED] invalid_tv_option
[20:54:43] [PASSED] truncated_tv_option
[20:54:43] ============ [PASSED] drm_test_cmdline_invalid =============
[20:54:43] =============== drm_test_cmdline_tv_options  ===============
[20:54:43] [PASSED] NTSC
[20:54:43] [PASSED] NTSC_443
[20:54:43] [PASSED] NTSC_J
[20:54:43] [PASSED] PAL
[20:54:43] [PASSED] PAL_M
[20:54:43] [PASSED] PAL_N
[20:54:43] [PASSED] SECAM
[20:54:43] [PASSED] MONO_525
[20:54:43] [PASSED] MONO_625
[20:54:43] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:54:43] =============== [PASSED] drm_cmdline_parser ================
[20:54:43] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:54:43] [PASSED] drm_test_connector_hdmi_init_valid
[20:54:43] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:54:43] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:54:43] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:54:43] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:54:43] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:54:43] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:54:43] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:54:43] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[20:54:43] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:54:43] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:54:43] [PASSED] supported_formats=0x3 yuv420_allowed=1
[20:54:43] [PASSED] supported_formats=0x3 yuv420_allowed=0
[20:54:43] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:54:43] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:54:43] [PASSED] drm_test_connector_hdmi_init_null_product
[20:54:43] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:54:43] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:54:43] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:54:43] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:54:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:54:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:54:43] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:54:43] ========= drm_test_connector_hdmi_init_type_valid  =========
[20:54:43] [PASSED] HDMI-A
[20:54:43] [PASSED] HDMI-B
[20:54:43] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:54:43] ======== drm_test_connector_hdmi_init_type_invalid  ========
[20:54:43] [PASSED] Unknown
[20:54:43] [PASSED] VGA
[20:54:43] [PASSED] DVI-I
[20:54:43] [PASSED] DVI-D
[20:54:43] [PASSED] DVI-A
[20:54:43] [PASSED] Composite
[20:54:43] [PASSED] SVIDEO
[20:54:43] [PASSED] LVDS
[20:54:43] [PASSED] Component
[20:54:43] [PASSED] DIN
[20:54:43] [PASSED] DP
[20:54:43] [PASSED] TV
[20:54:43] [PASSED] eDP
[20:54:43] [PASSED] Virtual
[20:54:43] [PASSED] DSI
[20:54:43] [PASSED] DPI
[20:54:43] [PASSED] Writeback
[20:54:43] [PASSED] SPI
[20:54:43] [PASSED] USB
[20:54:43] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:54:43] ============ [PASSED] drmm_connector_hdmi_init =============
[20:54:43] ============= drmm_connector_init (3 subtests) =============
[20:54:43] [PASSED] drm_test_drmm_connector_init
[20:54:43] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:54:43] ========= drm_test_drmm_connector_init_type_valid  =========
[20:54:43] [PASSED] Unknown
[20:54:43] [PASSED] VGA
[20:54:43] [PASSED] DVI-I
[20:54:43] [PASSED] DVI-D
[20:54:43] [PASSED] DVI-A
[20:54:43] [PASSED] Composite
[20:54:43] [PASSED] SVIDEO
[20:54:43] [PASSED] LVDS
[20:54:43] [PASSED] Component
[20:54:43] [PASSED] DIN
[20:54:43] [PASSED] DP
[20:54:43] [PASSED] HDMI-A
[20:54:43] [PASSED] HDMI-B
[20:54:43] [PASSED] TV
[20:54:43] [PASSED] eDP
[20:54:43] [PASSED] Virtual
[20:54:43] [PASSED] DSI
[20:54:43] [PASSED] DPI
[20:54:43] [PASSED] Writeback
[20:54:43] [PASSED] SPI
[20:54:43] [PASSED] USB
[20:54:43] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:54:43] =============== [PASSED] drmm_connector_init ===============
[20:54:43] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_init
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:54:43] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[20:54:43] [PASSED] Unknown
[20:54:43] [PASSED] VGA
[20:54:43] [PASSED] DVI-I
[20:54:43] [PASSED] DVI-D
[20:54:43] [PASSED] DVI-A
[20:54:43] [PASSED] Composite
[20:54:43] [PASSED] SVIDEO
[20:54:43] [PASSED] LVDS
[20:54:43] [PASSED] Component
[20:54:43] [PASSED] DIN
[20:54:43] [PASSED] DP
[20:54:43] [PASSED] HDMI-A
[20:54:43] [PASSED] HDMI-B
[20:54:43] [PASSED] TV
[20:54:43] [PASSED] eDP
[20:54:43] [PASSED] Virtual
[20:54:43] [PASSED] DSI
[20:54:43] [PASSED] DPI
[20:54:43] [PASSED] Writeback
[20:54:43] [PASSED] SPI
[20:54:43] [PASSED] USB
[20:54:43] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:54:43] ======== drm_test_drm_connector_dynamic_init_name  =========
[20:54:43] [PASSED] Unknown
[20:54:43] [PASSED] VGA
[20:54:43] [PASSED] DVI-I
[20:54:43] [PASSED] DVI-D
[20:54:43] [PASSED] DVI-A
[20:54:43] [PASSED] Composite
[20:54:43] [PASSED] SVIDEO
[20:54:43] [PASSED] LVDS
[20:54:43] [PASSED] Component
[20:54:43] [PASSED] DIN
[20:54:43] [PASSED] DP
[20:54:43] [PASSED] HDMI-A
[20:54:43] [PASSED] HDMI-B
[20:54:43] [PASSED] TV
[20:54:43] [PASSED] eDP
[20:54:43] [PASSED] Virtual
[20:54:43] [PASSED] DSI
[20:54:43] [PASSED] DPI
[20:54:43] [PASSED] Writeback
[20:54:43] [PASSED] SPI
[20:54:43] [PASSED] USB
[20:54:43] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:54:43] =========== [PASSED] drm_connector_dynamic_init ============
[20:54:43] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:54:43] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:54:43] ======= drm_connector_dynamic_register (7 subtests) ========
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:54:43] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:54:43] ========= [PASSED] drm_connector_dynamic_register ==========
[20:54:43] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:54:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:54:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:54:43] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:54:43] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:54:43] ========== drm_test_get_tv_mode_from_name_valid  ===========
[20:54:43] [PASSED] NTSC
[20:54:43] [PASSED] NTSC-443
[20:54:43] [PASSED] NTSC-J
[20:54:43] [PASSED] PAL
[20:54:43] [PASSED] PAL-M
[20:54:43] [PASSED] PAL-N
[20:54:43] [PASSED] SECAM
[20:54:43] [PASSED] Mono
[20:54:43] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:54:43] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:54:43] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:54:43] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:54:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:54:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:54:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:54:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:54:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:54:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:54:43] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[20:54:43] [PASSED] VIC 96
[20:54:43] [PASSED] VIC 97
[20:54:43] [PASSED] VIC 101
[20:54:43] [PASSED] VIC 102
[20:54:43] [PASSED] VIC 106
[20:54:43] [PASSED] VIC 107
[20:54:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:54:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:54:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:54:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:54:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:54:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:54:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:54:43] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:54:43] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[20:54:43] [PASSED] Automatic
[20:54:43] [PASSED] Full
[20:54:43] [PASSED] Limited 16:235
[20:54:43] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:54:43] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:54:43] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:54:43] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:54:43] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[20:54:43] [PASSED] RGB
[20:54:43] [PASSED] YUV 4:2:0
[20:54:43] [PASSED] YUV 4:2:2
[20:54:43] [PASSED] YUV 4:4:4
[20:54:43] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:54:43] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:54:43] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:54:43] ============= drm_damage_helper (21 subtests) ==============
[20:54:43] [PASSED] drm_test_damage_iter_no_damage
[20:54:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:54:43] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:54:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:54:43] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:54:43] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:54:43] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:54:43] [PASSED] drm_test_damage_iter_simple_damage
[20:54:43] [PASSED] drm_test_damage_iter_single_damage
[20:54:43] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:54:43] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:54:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:54:43] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:54:43] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:54:43] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:54:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:54:43] [PASSED] drm_test_damage_iter_damage
[20:54:43] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:54:43] [PASSED] drm_test_damage_iter_damage_one_outside
[20:54:43] [PASSED] drm_test_damage_iter_damage_src_moved
[20:54:43] [PASSED] drm_test_damage_iter_damage_not_visible
[20:54:43] ================ [PASSED] drm_damage_helper ================
[20:54:43] ============== drm_dp_mst_helper (3 subtests) ==============
[20:54:43] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[20:54:43] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:54:43] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:54:43] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:54:43] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:54:43] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:54:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:54:43] ============== drm_test_dp_mst_calc_pbn_div  ===============
[20:54:43] [PASSED] Link rate 2000000 lane count 4
[20:54:43] [PASSED] Link rate 2000000 lane count 2
[20:54:43] [PASSED] Link rate 2000000 lane count 1
[20:54:43] [PASSED] Link rate 1350000 lane count 4
[20:54:43] [PASSED] Link rate 1350000 lane count 2
[20:54:43] [PASSED] Link rate 1350000 lane count 1
[20:54:43] [PASSED] Link rate 1000000 lane count 4
[20:54:43] [PASSED] Link rate 1000000 lane count 2
[20:54:43] [PASSED] Link rate 1000000 lane count 1
[20:54:43] [PASSED] Link rate 810000 lane count 4
[20:54:43] [PASSED] Link rate 810000 lane count 2
[20:54:43] [PASSED] Link rate 810000 lane count 1
[20:54:43] [PASSED] Link rate 540000 lane count 4
[20:54:43] [PASSED] Link rate 540000 lane count 2
[20:54:43] [PASSED] Link rate 540000 lane count 1
[20:54:43] [PASSED] Link rate 270000 lane count 4
[20:54:43] [PASSED] Link rate 270000 lane count 2
[20:54:43] [PASSED] Link rate 270000 lane count 1
[20:54:43] [PASSED] Link rate 162000 lane count 4
[20:54:43] [PASSED] Link rate 162000 lane count 2
[20:54:43] [PASSED] Link rate 162000 lane count 1
[20:54:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:54:43] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[20:54:43] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:54:43] [PASSED] DP_POWER_UP_PHY with port number
[20:54:43] [PASSED] DP_POWER_DOWN_PHY with port number
[20:54:43] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:54:43] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:54:43] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:54:43] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:54:43] [PASSED] DP_QUERY_PAYLOAD with port number
[20:54:43] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:54:43] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:54:43] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:54:43] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:54:43] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:54:43] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:54:43] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:54:43] [PASSED] DP_REMOTE_I2C_READ with port number
[20:54:43] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:54:43] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:54:43] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:54:43] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:54:43] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:54:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:54:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:54:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:54:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:54:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:54:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:54:43] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:54:43] ================ [PASSED] drm_dp_mst_helper ================
[20:54:43] ================== drm_exec (7 subtests) ===================
[20:54:43] [PASSED] sanitycheck
[20:54:43] [PASSED] test_lock
[20:54:43] [PASSED] test_lock_unlock
[20:54:43] [PASSED] test_duplicates
[20:54:43] [PASSED] test_prepare
[20:54:43] [PASSED] test_prepare_array
[20:54:43] [PASSED] test_multiple_loops
[20:54:43] ==================== [PASSED] drm_exec =====================
[20:54:43] =========== drm_format_helper_test (17 subtests) ===========
[20:54:43] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:54:43] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:54:43] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:54:43] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:54:43] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:54:43] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:54:43] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:54:43] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:54:43] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:54:43] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:54:43] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:54:43] ============== drm_test_fb_xrgb8888_to_mono  ===============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:54:43] ==================== drm_test_fb_swab  =====================
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ================ [PASSED] drm_test_fb_swab =================
[20:54:43] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:54:43] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[20:54:43] [PASSED] single_pixel_source_buffer
[20:54:43] [PASSED] single_pixel_clip_rectangle
[20:54:43] [PASSED] well_known_colors
[20:54:43] [PASSED] destination_pitch
[20:54:43] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:54:43] ================= drm_test_fb_clip_offset  =================
[20:54:43] [PASSED] pass through
[20:54:43] [PASSED] horizontal offset
[20:54:43] [PASSED] vertical offset
[20:54:43] [PASSED] horizontal and vertical offset
[20:54:43] [PASSED] horizontal offset (custom pitch)
[20:54:43] [PASSED] vertical offset (custom pitch)
[20:54:43] [PASSED] horizontal and vertical offset (custom pitch)
[20:54:43] ============= [PASSED] drm_test_fb_clip_offset =============
[20:54:43] =================== drm_test_fb_memcpy  ====================
[20:54:43] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:54:43] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:54:43] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:54:43] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:54:43] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:54:43] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:54:43] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:54:43] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:54:43] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:54:43] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:54:43] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:54:43] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:54:43] =============== [PASSED] drm_test_fb_memcpy ================
[20:54:43] ============= [PASSED] drm_format_helper_test ==============
[20:54:43] ================= drm_format (18 subtests) =================
[20:54:43] [PASSED] drm_test_format_block_width_invalid
[20:54:43] [PASSED] drm_test_format_block_width_one_plane
[20:54:43] [PASSED] drm_test_format_block_width_two_plane
[20:54:43] [PASSED] drm_test_format_block_width_three_plane
[20:54:43] [PASSED] drm_test_format_block_width_tiled
[20:54:43] [PASSED] drm_test_format_block_height_invalid
[20:54:43] [PASSED] drm_test_format_block_height_one_plane
[20:54:43] [PASSED] drm_test_format_block_height_two_plane
[20:54:43] [PASSED] drm_test_format_block_height_three_plane
[20:54:43] [PASSED] drm_test_format_block_height_tiled
[20:54:43] [PASSED] drm_test_format_min_pitch_invalid
[20:54:43] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:54:43] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:54:43] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:54:43] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:54:43] [PASSED] drm_test_format_min_pitch_two_plane
[20:54:43] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:54:43] [PASSED] drm_test_format_min_pitch_tiled
[20:54:43] =================== [PASSED] drm_format ====================
[20:54:43] ============== drm_framebuffer (10 subtests) ===============
[20:54:43] ========== drm_test_framebuffer_check_src_coords  ==========
[20:54:43] [PASSED] Success: source fits into fb
[20:54:43] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:54:43] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:54:43] [PASSED] Fail: overflowing fb with source width
[20:54:43] [PASSED] Fail: overflowing fb with source height
[20:54:43] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:54:43] [PASSED] drm_test_framebuffer_cleanup
[20:54:43] =============== drm_test_framebuffer_create  ===============
[20:54:43] [PASSED] ABGR8888 normal sizes
[20:54:43] [PASSED] ABGR8888 max sizes
[20:54:43] [PASSED] ABGR8888 pitch greater than min required
[20:54:43] [PASSED] ABGR8888 pitch less than min required
[20:54:43] [PASSED] ABGR8888 Invalid width
[20:54:43] [PASSED] ABGR8888 Invalid buffer handle
[20:54:43] [PASSED] No pixel format
[20:54:43] [PASSED] ABGR8888 Width 0
[20:54:43] [PASSED] ABGR8888 Height 0
[20:54:43] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:54:43] [PASSED] ABGR8888 Large buffer offset
[20:54:43] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:54:43] [PASSED] ABGR8888 Invalid flag
[20:54:43] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:54:43] [PASSED] ABGR8888 Valid buffer modifier
[20:54:43] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:54:43] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:54:43] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:54:43] [PASSED] NV12 Normal sizes
[20:54:43] [PASSED] NV12 Max sizes
[20:54:43] [PASSED] NV12 Invalid pitch
[20:54:43] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:54:43] [PASSED] NV12 different  modifier per-plane
[20:54:43] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:54:43] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:54:43] [PASSED] NV12 Modifier for inexistent plane
[20:54:43] [PASSED] NV12 Handle for inexistent plane
[20:54:43] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:54:43] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:54:43] [PASSED] YVU420 Normal sizes
[20:54:43] [PASSED] YVU420 Max sizes
[20:54:43] [PASSED] YVU420 Invalid pitch
[20:54:43] [PASSED] YVU420 Different pitches
[20:54:43] [PASSED] YVU420 Different buffer offsets/pitches
[20:54:43] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:54:43] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:54:43] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:54:43] [PASSED] YVU420 Valid modifier
[20:54:43] [PASSED] YVU420 Different modifiers per plane
[20:54:43] [PASSED] YVU420 Modifier for inexistent plane
[20:54:43] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:54:43] [PASSED] X0L2 Normal sizes
[20:54:43] [PASSED] X0L2 Max sizes
[20:54:43] [PASSED] X0L2 Invalid pitch
[20:54:43] [PASSED] X0L2 Pitch greater than minimum required
[20:54:43] [PASSED] X0L2 Handle for inexistent plane
[20:54:43] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:54:43] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:54:43] [PASSED] X0L2 Valid modifier
[20:54:43] [PASSED] X0L2 Modifier for inexistent plane
[20:54:43] =========== [PASSED] drm_test_framebuffer_create ===========
[20:54:43] [PASSED] drm_test_framebuffer_free
[20:54:43] [PASSED] drm_test_framebuffer_init
[20:54:43] [PASSED] drm_test_framebuffer_init_bad_format
[20:54:43] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:54:43] [PASSED] drm_test_framebuffer_lookup
[20:54:43] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:54:43] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:54:43] ================= [PASSED] drm_framebuffer =================
[20:54:43] ================ drm_gem_shmem (8 subtests) ================
[20:54:43] [PASSED] drm_gem_shmem_test_obj_create
[20:54:43] [PASSED] drm_gem_shmem_test_obj_create_private
[20:54:43] [PASSED] drm_gem_shmem_test_pin_pages
[20:54:43] [PASSED] drm_gem_shmem_test_vmap
[20:54:43] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:54:43] [PASSED] drm_gem_shmem_test_get_sg_table
[20:54:43] [PASSED] drm_gem_shmem_test_madvise
[20:54:43] [PASSED] drm_gem_shmem_test_purge
[20:54:43] ================== [PASSED] drm_gem_shmem ==================
[20:54:43] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[20:54:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:54:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:54:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:54:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:54:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:54:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:54:43] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[20:54:43] [PASSED] Automatic
[20:54:43] [PASSED] Full
[20:54:43] [PASSED] Limited 16:235
[20:54:43] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:54:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:54:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:54:43] [PASSED] drm_test_check_disable_connector
[20:54:43] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:54:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:54:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:54:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:54:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:54:43] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:54:43] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:54:43] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:54:43] [PASSED] drm_test_check_output_bpc_dvi
[20:54:43] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:54:43] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:54:43] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:54:43] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:54:43] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:54:43] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:54:43] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:54:43] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:54:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:54:43] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:54:43] [PASSED] drm_test_check_broadcast_rgb_value
[20:54:43] [PASSED] drm_test_check_bpc_8_value
[20:54:43] [PASSED] drm_test_check_bpc_10_value
[20:54:43] [PASSED] drm_test_check_bpc_12_value
[20:54:43] [PASSED] drm_test_check_format_value
[20:54:43] [PASSED] drm_test_check_tmds_char_value
[20:54:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:54:43] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[20:54:43] [PASSED] drm_test_check_mode_valid
[20:54:43] [PASSED] drm_test_check_mode_valid_reject
[20:54:43] [PASSED] drm_test_check_mode_valid_reject_rate
[20:54:43] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:54:43] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:54:43] ================= drm_managed (2 subtests) =================
[20:54:43] [PASSED] drm_test_managed_release_action
[20:54:43] [PASSED] drm_test_managed_run_action
[20:54:43] =================== [PASSED] drm_managed ===================
[20:54:43] =================== drm_mm (6 subtests) ====================
[20:54:43] [PASSED] drm_test_mm_init
[20:54:43] [PASSED] drm_test_mm_debug
[20:54:43] [PASSED] drm_test_mm_align32
[20:54:43] [PASSED] drm_test_mm_align64
[20:54:43] [PASSED] drm_test_mm_lowest
[20:54:43] [PASSED] drm_test_mm_highest
[20:54:43] ===================== [PASSED] drm_mm ======================
[20:54:43] ============= drm_modes_analog_tv (5 subtests) =============
[20:54:43] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:54:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:54:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:54:43] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:54:43] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:54:43] =============== [PASSED] drm_modes_analog_tv ===============
[20:54:43] ============== drm_plane_helper (2 subtests) ===============
[20:54:43] =============== drm_test_check_plane_state  ================
[20:54:43] [PASSED] clipping_simple
[20:54:43] [PASSED] clipping_rotate_reflect
[20:54:43] [PASSED] positioning_simple
[20:54:43] [PASSED] upscaling
[20:54:43] [PASSED] downscaling
[20:54:43] [PASSED] rounding1
[20:54:43] [PASSED] rounding2
[20:54:43] [PASSED] rounding3
[20:54:43] [PASSED] rounding4
[20:54:43] =========== [PASSED] drm_test_check_plane_state ============
[20:54:43] =========== drm_test_check_invalid_plane_state  ============
[20:54:43] [PASSED] positioning_invalid
[20:54:43] [PASSED] upscaling_invalid
[20:54:43] [PASSED] downscaling_invalid
[20:54:43] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:54:43] ================ [PASSED] drm_plane_helper =================
[20:54:43] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:54:43] ====== drm_test_connector_helper_tv_get_modes_check  =======
[20:54:43] [PASSED] None
[20:54:43] [PASSED] PAL
[20:54:43] [PASSED] NTSC
[20:54:43] [PASSED] Both, NTSC Default
[20:54:43] [PASSED] Both, PAL Default
[20:54:43] [PASSED] Both, NTSC Default, with PAL on command-line
[20:54:43] [PASSED] Both, PAL Default, with NTSC on command-line
[20:54:43] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:54:43] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:54:43] ================== drm_rect (9 subtests) ===================
[20:54:43] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:54:43] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:54:43] [PASSED] drm_test_rect_clip_scaled_clipped
[20:54:43] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:54:43] ================= drm_test_rect_intersect  =================
[20:54:43] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:54:43] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:54:43] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:54:43] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:54:43] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:54:43] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:54:43] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:54:43] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:54:43] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:54:43] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:54:43] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:54:43] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:54:43] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:54:43] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:54:43] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:54:43] ============= [PASSED] drm_test_rect_intersect =============
[20:54:43] ================ drm_test_rect_calc_hscale  ================
[20:54:43] [PASSED] normal use
[20:54:43] [PASSED] out of max range
[20:54:43] [PASSED] out of min range
[20:54:43] [PASSED] zero dst
[20:54:43] [PASSED] negative src
[20:54:43] [PASSED] negative dst
[20:54:43] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:54:43] ================ drm_test_rect_calc_vscale  ================
[20:54:43] [PASSED] normal use
[20:54:43] [PASSED] out of max range
[20:54:43] [PASSED] out of min range
[20:54:43] [PASSED] zero dst
[20:54:43] [PASSED] negative src
[20:54:43] [PASSED] negative dst
[20:54:43] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:54:43] ================== drm_test_rect_rotate  ===================
[20:54:43] [PASSED] reflect-x
[20:54:43] [PASSED] reflect-y
[20:54:43] [PASSED] rotate-0
[20:54:43] [PASSED] rotate-90
[20:54:43] [PASSED] rotate-180
[20:54:43] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[20:54:43] ============== [PASSED] drm_test_rect_rotate ===============
[20:54:43] ================ drm_test_rect_rotate_inv  =================
[20:54:43] [PASSED] reflect-x
[20:54:43] [PASSED] reflect-y
[20:54:43] [PASSED] rotate-0
[20:54:43] [PASSED] rotate-90
[20:54:43] [PASSED] rotate-180
[20:54:43] [PASSED] rotate-270
[20:54:43] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:54:43] ==================== [PASSED] drm_rect =====================
[20:54:43] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:54:43] ============ drm_test_sysfb_build_fourcc_list  =============
[20:54:43] [PASSED] no native formats
[20:54:43] [PASSED] XRGB8888 as native format
[20:54:43] [PASSED] remove duplicates
[20:54:43] [PASSED] convert alpha formats
[20:54:43] [PASSED] random formats
[20:54:43] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:54:43] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:54:43] ============================================================
[20:54:43] Testing complete. Ran 616 tests: passed: 616
[20:54:43] Elapsed time: 23.419s total, 1.690s configuring, 21.560s building, 0.132s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:54:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:54:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:54:53] Starting KUnit Kernel (1/1)...
[20:54:53] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:54:53] ================= ttm_device (5 subtests) ==================
[20:54:53] [PASSED] ttm_device_init_basic
[20:54:53] [PASSED] ttm_device_init_multiple
[20:54:53] [PASSED] ttm_device_fini_basic
[20:54:53] [PASSED] ttm_device_init_no_vma_man
[20:54:53] ================== ttm_device_init_pools  ==================
[20:54:53] [PASSED] No DMA allocations, no DMA32 required
[20:54:53] [PASSED] DMA allocations, DMA32 required
[20:54:53] [PASSED] No DMA allocations, DMA32 required
[20:54:53] [PASSED] DMA allocations, no DMA32 required
[20:54:53] ============== [PASSED] ttm_device_init_pools ==============
[20:54:53] =================== [PASSED] ttm_device ====================
[20:54:53] ================== ttm_pool (8 subtests) ===================
[20:54:53] ================== ttm_pool_alloc_basic  ===================
[20:54:53] [PASSED] One page
[20:54:53] [PASSED] More than one page
[20:54:53] [PASSED] Above the allocation limit
[20:54:53] [PASSED] One page, with coherent DMA mappings enabled
[20:54:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:54:53] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:54:53] ============== ttm_pool_alloc_basic_dma_addr  ==============
[20:54:53] [PASSED] One page
[20:54:53] [PASSED] More than one page
[20:54:53] [PASSED] Above the allocation limit
[20:54:53] [PASSED] One page, with coherent DMA mappings enabled
[20:54:53] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:54:53] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:54:53] [PASSED] ttm_pool_alloc_order_caching_match
[20:54:53] [PASSED] ttm_pool_alloc_caching_mismatch
[20:54:53] [PASSED] ttm_pool_alloc_order_mismatch
[20:54:53] [PASSED] ttm_pool_free_dma_alloc
[20:54:53] [PASSED] ttm_pool_free_no_dma_alloc
[20:54:53] [PASSED] ttm_pool_fini_basic
[20:54:53] ==================== [PASSED] ttm_pool =====================
[20:54:53] ================ ttm_resource (8 subtests) =================
[20:54:53] ================= ttm_resource_init_basic  =================
[20:54:53] [PASSED] Init resource in TTM_PL_SYSTEM
[20:54:53] [PASSED] Init resource in TTM_PL_VRAM
[20:54:53] [PASSED] Init resource in a private placement
[20:54:53] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:54:53] ============= [PASSED] ttm_resource_init_basic =============
[20:54:53] [PASSED] ttm_resource_init_pinned
[20:54:53] [PASSED] ttm_resource_fini_basic
[20:54:53] [PASSED] ttm_resource_manager_init_basic
[20:54:53] [PASSED] ttm_resource_manager_usage_basic
[20:54:53] [PASSED] ttm_resource_manager_set_used_basic
[20:54:53] [PASSED] ttm_sys_man_alloc_basic
[20:54:53] [PASSED] ttm_sys_man_free_basic
[20:54:53] ================== [PASSED] ttm_resource ===================
[20:54:53] =================== ttm_tt (15 subtests) ===================
[20:54:53] ==================== ttm_tt_init_basic  ====================
[20:54:53] [PASSED] Page-aligned size
[20:54:53] [PASSED] Extra pages requested
[20:54:53] ================ [PASSED] ttm_tt_init_basic ================
[20:54:53] [PASSED] ttm_tt_init_misaligned
[20:54:53] [PASSED] ttm_tt_fini_basic
[20:54:53] [PASSED] ttm_tt_fini_sg
[20:54:53] [PASSED] ttm_tt_fini_shmem
[20:54:53] [PASSED] ttm_tt_create_basic
[20:54:53] [PASSED] ttm_tt_create_invalid_bo_type
[20:54:53] [PASSED] ttm_tt_create_ttm_exists
[20:54:53] [PASSED] ttm_tt_create_failed
[20:54:53] [PASSED] ttm_tt_destroy_basic
[20:54:53] [PASSED] ttm_tt_populate_null_ttm
[20:54:53] [PASSED] ttm_tt_populate_populated_ttm
[20:54:53] [PASSED] ttm_tt_unpopulate_basic
[20:54:53] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:54:53] [PASSED] ttm_tt_swapin_basic
[20:54:53] ===================== [PASSED] ttm_tt ======================
[20:54:53] =================== ttm_bo (14 subtests) ===================
[20:54:53] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[20:54:53] [PASSED] Cannot be interrupted and sleeps
[20:54:53] [PASSED] Cannot be interrupted, locks straight away
[20:54:53] [PASSED] Can be interrupted, sleeps
[20:54:53] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:54:53] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:54:53] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:54:53] [PASSED] ttm_bo_reserve_double_resv
[20:54:53] [PASSED] ttm_bo_reserve_interrupted
[20:54:53] [PASSED] ttm_bo_reserve_deadlock
[20:54:53] [PASSED] ttm_bo_unreserve_basic
[20:54:53] [PASSED] ttm_bo_unreserve_pinned
[20:54:53] [PASSED] ttm_bo_unreserve_bulk
[20:54:53] [PASSED] ttm_bo_put_basic
[20:54:53] [PASSED] ttm_bo_put_shared_resv
[20:54:53] [PASSED] ttm_bo_pin_basic
[20:54:53] [PASSED] ttm_bo_pin_unpin_resource
[20:54:53] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:54:53] ===================== [PASSED] ttm_bo ======================
[20:54:53] ============== ttm_bo_validate (22 subtests) ===============
[20:54:53] ============== ttm_bo_init_reserved_sys_man  ===============
[20:54:53] [PASSED] Buffer object for userspace
[20:54:53] [PASSED] Kernel buffer object
[20:54:53] [PASSED] Shared buffer object
[20:54:53] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:54:53] ============== ttm_bo_init_reserved_mock_man  ==============
[20:54:53] [PASSED] Buffer object for userspace
[20:54:53] [PASSED] Kernel buffer object
[20:54:53] [PASSED] Shared buffer object
[20:54:53] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:54:53] [PASSED] ttm_bo_init_reserved_resv
[20:54:53] ================== ttm_bo_validate_basic  ==================
[20:54:53] [PASSED] Buffer object for userspace
[20:54:53] [PASSED] Kernel buffer object
[20:54:53] [PASSED] Shared buffer object
[20:54:53] ============== [PASSED] ttm_bo_validate_basic ==============
[20:54:53] [PASSED] ttm_bo_validate_invalid_placement
[20:54:53] ============= ttm_bo_validate_same_placement  ==============
[20:54:53] [PASSED] System manager
[20:54:53] [PASSED] VRAM manager
[20:54:53] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:54:53] [PASSED] ttm_bo_validate_failed_alloc
[20:54:53] [PASSED] ttm_bo_validate_pinned
[20:54:53] [PASSED] ttm_bo_validate_busy_placement
[20:54:53] ================ ttm_bo_validate_multihop  =================
[20:54:53] [PASSED] Buffer object for userspace
[20:54:53] [PASSED] Kernel buffer object
[20:54:53] [PASSED] Shared buffer object
[20:54:53] ============ [PASSED] ttm_bo_validate_multihop =============
[20:54:53] ========== ttm_bo_validate_no_placement_signaled  ==========
[20:54:53] [PASSED] Buffer object in system domain, no page vector
[20:54:53] [PASSED] Buffer object in system domain with an existing page vector
[20:54:53] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:54:53] ======== ttm_bo_validate_no_placement_not_signaled  ========
[20:54:53] [PASSED] Buffer object for userspace
[20:54:53] [PASSED] Kernel buffer object
[20:54:53] [PASSED] Shared buffer object
[20:54:53] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:54:53] [PASSED] ttm_bo_validate_move_fence_signaled
[20:54:53] ========= ttm_bo_validate_move_fence_not_signaled  =========
[20:54:53] [PASSED] Waits for GPU
[20:54:53] [PASSED] Tries to lock straight away
[20:54:53] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:54:53] [PASSED] ttm_bo_validate_swapout
[20:54:53] [PASSED] ttm_bo_validate_happy_evict
[20:54:53] [PASSED] ttm_bo_validate_all_pinned_evict
[20:54:53] [PASSED] ttm_bo_validate_allowed_only_evict
[20:54:53] [PASSED] ttm_bo_validate_deleted_evict
[20:54:53] [PASSED] ttm_bo_validate_busy_domain_evict
[20:54:53] [PASSED] ttm_bo_validate_evict_gutting
[20:54:53] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[20:54:53] ================= [PASSED] ttm_bo_validate =================
[20:54:53] ============================================================
[20:54:53] Testing complete. Ran 102 tests: passed: 102
[20:54:53] Elapsed time: 10.076s total, 1.704s configuring, 7.755s building, 0.515s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/i915/dp: DP stuff

[Patchwork]

== Series Details ==

Series: drm/i915/dp: DP stuff
URL   : https://patchwork.freedesktop.org/series/151464/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 0634465b9ad088eec546c342110514e0d2d775d1
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2032:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2032:24: warning: unreplaced symbol '<noident>'

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/dp: DP stuff

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 837 bytes --]

== Series Details ==

Series: drm/i915/dp: DP stuff
URL   : https://patchwork.freedesktop.org/series/151464/
State : success

== Summary ==

CI Bug Log - changes from xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c_BAT -> xe-pw-151464v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 8)
------------------------------

  Missing    (1): bat-adlp-vm 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c -> xe-pw-151464v1

  IGT_8451: 8451
  xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c: 6ee8d9883a49bf8ddaf26b60905f73e8654fd58c
  xe-pw-151464v1: 151464v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/index.html

[-- Attachment #2: Type: text/html, Size: 1385 bytes --]

✗ Xe.CI.Full: failure for drm/i915/dp: DP stuff

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 35329 bytes --]

== Series Details ==

Series: drm/i915/dp: DP stuff
URL   : https://patchwork.freedesktop.org/series/151464/
State : failure

== Summary ==

CI Bug Log - changes from xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c_FULL -> xe-pw-151464v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-151464v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-151464v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-151464v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@core_getversion@all-cards:
    - shard-dg2-set2:     [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-dg2-466/igt@core_getversion@all-cards.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@core_getversion@all-cards.html

  
Known issues
------------

  Here are the changes found in xe-pw-151464v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-dg2-set2:     NOTRUN -> [SKIP][3] ([Intel XE#455]) +4 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][4] ([Intel XE#316]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#1124]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2328])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#1124])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-adlp:         [PASS][9] -> [DMESG-FAIL][10] ([Intel XE#4543])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#2191])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-463/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#367])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-4-displays-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#367])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-7/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-7/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#787]) +132 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][16] -> [INCOMPLETE][17] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
    - shard-dg2-set2:     [PASS][18] -> [INCOMPLETE][19] ([Intel XE#3124])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [PASS][20] -> [DMESG-WARN][21] ([Intel XE#1727] / [Intel XE#3113])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][22] -> [INCOMPLETE][23] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#455] / [Intel XE#787]) +22 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2887]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_hpd@dp-hpd:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2252])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_chamelium_hpd@dp-hpd.html

  * igt@kms_chamelium_hpd@vga-hpd:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#373]) +4 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-463/igt@kms_chamelium_hpd@vga-hpd.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     NOTRUN -> [FAIL][28] ([Intel XE#1178]) +3 other tests fail
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#307])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-463/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][30] -> [SKIP][31] ([Intel XE#2291]) +8 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-bmg:          [PASS][32] -> [SKIP][33] ([Intel XE#1340])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-bmg:          [PASS][34] -> [SKIP][35] ([Intel XE#2316]) +8 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-4/igt@kms_flip@2x-nonexisting-fb.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-6/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-adlp:         [PASS][36] -> [DMESG-WARN][37] ([Intel XE#4543]) +8 other tests dmesg-warn
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-adlp-8/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-adlp-2/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2311]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary:
    - shard-dg2-set2:     NOTRUN -> [SKIP][39] ([Intel XE#651]) +7 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#5390]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2313]) +4 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#5426])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#653]) +7 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_hdr@static-swap:
    - shard-bmg:          [PASS][44] -> [SKIP][45] ([Intel XE#1503]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-8/igt@kms_hdr@static-swap.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-6/igt@kms_hdr@static-swap.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-bmg:          [PASS][46] -> [SKIP][47] ([Intel XE#4596]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-x.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#5021])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#1489]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-466/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#1489]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-7/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-pr-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#2234] / [Intel XE#2850])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_psr@fbc-pr-dpms.html

  * igt@kms_psr@psr2-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#2850] / [Intel XE#929]) +5 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-466/igt@kms_psr@psr2-dpms.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-bmg:          [PASS][53] -> [SKIP][54] ([Intel XE#1435])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-4/igt@kms_setmode@clone-exclusive-crtc.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_vrr@cmrr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#2168])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-463/igt@kms_vrr@cmrr.html

  * igt@xe_eu_stall@invalid-gt-id:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#5419]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@xe_eu_stall@invalid-gt-id.html

  * igt@xe_eudebug@vm-bind-clear-faultable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][57] ([Intel XE#4837]) +5 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-463/igt@xe_eudebug@vm-bind-clear-faultable.html

  * igt@xe_eudebug_online@interrupt-reconnect:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#4837])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-7/igt@xe_eudebug_online@interrupt-reconnect.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
    - shard-dg2-set2:     [PASS][59] -> [SKIP][60] ([Intel XE#1392]) +2 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-dg2-436/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html

  * igt@xe_exec_basic@multigpu-once-null-defer-mmap:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#2322])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@xe_exec_basic@multigpu-once-null-defer-mmap.html

  * igt@xe_exec_fault_mode@many-basic-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#288]) +9 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-463/igt@xe_exec_fault_mode@many-basic-prefetch.html

  * igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#4943]) +7 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-many-mmap-shared-remap-eocheck:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#4915]) +97 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@xe_exec_system_allocator@threads-many-mmap-shared-remap-eocheck.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
    - shard-lnl:          [PASS][65] -> [FAIL][66] ([Intel XE#5018])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-lnl-4/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-lnl-8/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html

  * igt@xe_media_fill@media-fill:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#560])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@xe_media_fill@media-fill.html

  * igt@xe_oa@mmio-triggered-reports:
    - shard-dg2-set2:     NOTRUN -> [SKIP][68] ([Intel XE#2541] / [Intel XE#3573]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@xe_oa@mmio-triggered-reports.html

  * igt@xe_oa@syncs-syncobj-none:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#2541] / [Intel XE#3573] / [Intel XE#4501])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-466/igt@xe_oa@syncs-syncobj-none.html

  * igt@xe_query@multigpu-query-gt-list:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#944])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@xe_query@multigpu-query-gt-list.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-dg2-set2:     NOTRUN -> [SKIP][71] ([Intel XE#944])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-435/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_wedged@basic-wedged:
    - shard-adlp:         [PASS][72] -> [DMESG-WARN][73] ([Intel XE#2953] / [Intel XE#4173]) +5 other tests dmesg-warn
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-adlp-4/igt@xe_wedged@basic-wedged.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-adlp-1/igt@xe_wedged@basic-wedged.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-adlp:         [FAIL][74] ([Intel XE#3908]) -> [PASS][75] +1 other test pass
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-adlp-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-adlp-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][76] ([Intel XE#2291]) -> [PASS][77] +3 other tests pass
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [SKIP][78] ([Intel XE#2316]) -> [PASS][79] +11 other tests pass
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-1/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][80] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [FAIL][82] ([Intel XE#301]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][84] ([Intel XE#4543]) -> [PASS][85] +4 other tests pass
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-adlp-6/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible@b-hdmi-a1.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][86] ([Intel XE#1503]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-7/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [SKIP][88] ([Intel XE#4596]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-4.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_setmode@basic@pipe-b-edp-1:
    - shard-lnl:          [FAIL][90] ([Intel XE#2883]) -> [PASS][91] +2 other tests pass
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-lnl-6/igt@kms_setmode@basic@pipe-b-edp-1.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-lnl-4/igt@kms_setmode@basic@pipe-b-edp-1.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-adlp:         [DMESG-WARN][92] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][93] +2 other tests pass
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-adlp-9/igt@kms_vblank@ts-continuation-suspend.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-adlp-4/igt@kms_vblank@ts-continuation-suspend.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-dg2-set2:     [SKIP][94] ([Intel XE#1392]) -> [PASS][95] +4 other tests pass
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-466/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-dg2-set2:     [DMESG-WARN][96] ([Intel XE#3876]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-dg2-463/igt@xe_exec_reset@parallel-gt-reset.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-466/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_pm@s4-basic:
    - shard-bmg:          [ABORT][98] ([Intel XE#5255]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-6/igt@xe_pm@s4-basic.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-7/igt@xe_pm@s4-basic.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][100] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][101] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          [FAIL][102] ([Intel XE#1178]) -> [SKIP][103] ([Intel XE#2341])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-1/igt@kms_content_protection@legacy.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-5/igt@kms_content_protection@legacy.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-adlp:         [DMESG-WARN][104] ([Intel XE#4543] / [Intel XE#5208]) -> [DMESG-WARN][105] ([Intel XE#5208])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-adlp-6/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][106] ([Intel XE#2312]) -> [SKIP][107] ([Intel XE#2311]) +23 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][108] ([Intel XE#2311]) -> [SKIP][109] ([Intel XE#2312]) +20 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][110] ([Intel XE#5390]) -> [SKIP][111] ([Intel XE#2312]) +11 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][112] ([Intel XE#2312]) -> [SKIP][113] ([Intel XE#5390]) +10 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][114] ([Intel XE#2313]) -> [SKIP][115] ([Intel XE#2312]) +19 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][116] ([Intel XE#2312]) -> [SKIP][117] ([Intel XE#2313]) +22 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][118] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][119] ([Intel XE#3544])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-adlp:         [ABORT][120] ([Intel XE#4917]) -> [ABORT][121] ([Intel XE#2953] / [Intel XE#4917])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c/shard-adlp-6/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/shard-adlp-9/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4501
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5255
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5419
  [Intel XE#5426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5426
  [Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c -> xe-pw-151464v1

  IGT_8451: 8451
  xe-3391-6ee8d9883a49bf8ddaf26b60905f73e8654fd58c: 6ee8d9883a49bf8ddaf26b60905f73e8654fd58c
  xe-pw-151464v1: 151464v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151464v1/index.html

[-- Attachment #2: Type: text/html, Size: 41992 bytes --]

Re: [PATCH 1/7] drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x

[Imre Deak]

On Thu, Jul 10, 2025 at 11:17:12PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On g4x we currently use the 96MHz non-SSC refclk, which can't actually
> generate an exact 2.7 Gbps link rate. In practice we end up with 2.688
> Gbps which seems to be close enough to actually work, but link training
> is currently failing due to miscalculating the DP_LINK_BW value (we
> calcualte it directly from port_clock which reflects the actual PLL
> outpout frequency).
> 
> Ideas how to fix this:
> - nudge port_clock back up to 270000 during PLL computation/readout
> - track port_clock and the nominal link rate separately so they might
>   differ a bit
> - switch to the 100MHz refclk, but that one should be SSC so perhaps
>   not something we want
> 
> While we ponder about a better solution apply some band aid to the
> immediate issue of miscalculated DP_LINK_BW value. With this
> I can again use 2.7 Gbps link rate on g4x.
> 
> Cc: stable@vger.kernel.org
> Fixes: 665a7b04092c ("drm/i915: Feed the DPLL output freq back into crtc_state")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

IIUC, port_clock for g4x is ref * m / n / p, where for DP the fixed
ref=96000 and m/n/p values from g4x_dpll are used.

Ftr, m = 135, n = 6, p = 8 would give port_clock = 270000, but there's
no intel_limit for DP, so can't know if these params are within range.

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f48912f308df..7976fec88606 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1606,6 +1606,12 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
>  void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
>  			   u8 *link_bw, u8 *rate_select)
>  {
> +	struct intel_display *display = to_intel_display(intel_dp);
> +
> +	/* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */
> +	if (display->platform.g4x && port_clock == 268800)
> +		port_clock = 270000;
> +
>  	/* eDP 1.4 rate select method. */
>  	if (intel_dp->use_rate_select) {
>  		*link_bw = 0;
> -- 
> 2.49.0
> 

Re: [PATCH 2/7] drm/i915/dp: Don't switch to idle pattern before disable on pre-hsw

[Imre Deak]

On Thu, Jul 10, 2025 at 11:17:13PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> For some reason we are switching over to the idle pattern before
> disabling the DP port on pre-hsw. AFAICS this has never been part
> of the documented sequence (and on hsw+ the spec explicitly says
> not to do this). Get rid of it.
> 
> The code goes all the way back to commit 5eb08b69f510 ("drm/i915: enable
> DisplayPort support on IGDNG"), and it was accompanied by a 17ms delay
> which got changed to vbl wait in commit ab527efc2fea ("drm/i915: use
> wait_for_vblank instead of msleep(17)"), and was later completely removed
> in  commit 93c9c19b3d25 ("drm/i915: remove unexplained vblank wait in
> the DP off code").
> 
> Smoke tested on g4x/snb/chv.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Matches the spec on SNB/IVB at least, I can't see a requirement to set
idle patterns before the 'Disable port' step there, based on that:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c | 11 -----------
>  1 file changed, 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 87f6b9602b16..b54edf0d1c23 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -424,17 +424,6 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  
>  	drm_dbg_kms(display->drm, "\n");
>  
> -	if ((display->platform.ivybridge && port == PORT_A) ||
> -	    (HAS_PCH_CPT(display) && port != PORT_A)) {
> -		intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
> -		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> -	} else {
> -		intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
> -		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
> -	}
> -	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
> -	intel_de_posting_read(display, intel_dp->output_reg);
> -
>  	intel_dp->DP &= ~DP_PORT_EN;
>  	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
>  	intel_de_posting_read(display, intel_dp->output_reg);
> -- 
> 2.49.0
> 

Re: [PATCH 1/7] drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x

[Ville Syrjälä]

On Wed, Jul 16, 2025 at 04:20:28PM +0300, Imre Deak wrote:
> On Thu, Jul 10, 2025 at 11:17:12PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On g4x we currently use the 96MHz non-SSC refclk, which can't actually
> > generate an exact 2.7 Gbps link rate. In practice we end up with 2.688
> > Gbps which seems to be close enough to actually work, but link training
> > is currently failing due to miscalculating the DP_LINK_BW value (we
> > calcualte it directly from port_clock which reflects the actual PLL
> > outpout frequency).
> > 
> > Ideas how to fix this:
> > - nudge port_clock back up to 270000 during PLL computation/readout
> > - track port_clock and the nominal link rate separately so they might
> >   differ a bit
> > - switch to the 100MHz refclk, but that one should be SSC so perhaps
> >   not something we want
> > 
> > While we ponder about a better solution apply some band aid to the
> > immediate issue of miscalculated DP_LINK_BW value. With this
> > I can again use 2.7 Gbps link rate on g4x.
> > 
> > Cc: stable@vger.kernel.org
> > Fixes: 665a7b04092c ("drm/i915: Feed the DPLL output freq back into crtc_state")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> IIUC, port_clock for g4x is ref * m / n / p, where for DP the fixed
> ref=96000 and m/n/p values from g4x_dpll are used.
> 
> Ftr, m = 135, n = 6, p = 8 would give port_clock = 270000, but there's
> no intel_limit for DP, so can't know if these params are within range.

The P divider can only be some multiple of 5.

> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index f48912f308df..7976fec88606 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1606,6 +1606,12 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
> >  void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> >  			   u8 *link_bw, u8 *rate_select)
> >  {
> > +	struct intel_display *display = to_intel_display(intel_dp);
> > +
> > +	/* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */
> > +	if (display->platform.g4x && port_clock == 268800)
> > +		port_clock = 270000;
> > +
> >  	/* eDP 1.4 rate select method. */
> >  	if (intel_dp->use_rate_select) {
> >  		*link_bw = 0;
> > -- 
> > 2.49.0
> > 

-- 
Ville Syrjälä
Intel

Re: [PATCH 1/7] drm/i915/dp: Fix 2.7 Gbps DP_LINK_BW value on g4x

[Imre Deak]

On Wed, Jul 16, 2025 at 09:40:40PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 16, 2025 at 04:20:28PM +0300, Imre Deak wrote:
> > On Thu, Jul 10, 2025 at 11:17:12PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > On g4x we currently use the 96MHz non-SSC refclk, which can't actually
> > > generate an exact 2.7 Gbps link rate. In practice we end up with 2.688
> > > Gbps which seems to be close enough to actually work, but link training
> > > is currently failing due to miscalculating the DP_LINK_BW value (we
> > > calcualte it directly from port_clock which reflects the actual PLL
> > > outpout frequency).
> > > 
> > > Ideas how to fix this:
> > > - nudge port_clock back up to 270000 during PLL computation/readout
> > > - track port_clock and the nominal link rate separately so they might
> > >   differ a bit
> > > - switch to the 100MHz refclk, but that one should be SSC so perhaps
> > >   not something we want
> > > 
> > > While we ponder about a better solution apply some band aid to the
> > > immediate issue of miscalculated DP_LINK_BW value. With this
> > > I can again use 2.7 Gbps link rate on g4x.
> > > 
> > > Cc: stable@vger.kernel.org
> > > Fixes: 665a7b04092c ("drm/i915: Feed the DPLL output freq back into crtc_state")
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > 
> > IIUC, port_clock for g4x is ref * m / n / p, where for DP the fixed
> > ref=96000 and m/n/p values from g4x_dpll are used.
> > 
> > Ftr, m = 135, n = 6, p = 8 would give port_clock = 270000, but there's
> > no intel_limit for DP, so can't know if these params are within range.
> 
> The P divider can only be some multiple of 5.

Right, missed that, so with this ref clock setting an exact link rate
doesn't seem to be possible indeed (within the VCO range used for all
other output types on g4x).

> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
> > >  1 file changed, 6 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index f48912f308df..7976fec88606 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1606,6 +1606,12 @@ int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
> > >  void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> > >  			   u8 *link_bw, u8 *rate_select)
> > >  {
> > > +	struct intel_display *display = to_intel_display(intel_dp);
> > > +
> > > +	/* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */
> > > +	if (display->platform.g4x && port_clock == 268800)
> > > +		port_clock = 270000;
> > > +
> > >  	/* eDP 1.4 rate select method. */
> > >  	if (intel_dp->use_rate_select) {
> > >  		*link_bw = 0;
> > > -- 
> > > 2.49.0
> > > 
> 
> -- 
> Ville Syrjälä
> Intel