[PATCH v2 0/2] GuC CT memory optimizations

[PATCH v2 0/2] GuC CT memory optimizations

[Matthew Brost]

Profiling has shown that reading from VRAM on BMG is very slow and
introduces significant latency in GuC CT operations. To address this,
CPU-side read buffers (G2H) are moved to system memory, and unnecessary
CPU reads of VRAM in hot paths are removed. This is marked as a fixes
change due to the dramatic improvement in G2H performance, which affects
hot paths such as TLB invalidation fences and fault-storm handling.

We likely have similar issues in hardware fence signaling paths that
currently read from VRAM. A follow-up will move the LRC fence seqno (and
possibly other CPU-side LRC reads) to system memory as well.

v2:
 - Fix devcoredump explosion (Testing)

Matt

Matthew Brost (2):
  drm/xe: Split H2G and G2H into separate buffer objects
  drm/xe: Remove H2G reads in CT send path in non-debug builds

 drivers/gpu/drm/xe/xe_guc_ct.c       | 80 ++++++++++++++++++----------
 drivers/gpu/drm/xe/xe_guc_ct_types.h |  6 ++-
 2 files changed, 55 insertions(+), 31 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] drm/xe: Split H2G and G2H into separate buffer objects

[Matthew Brost]

H2G and G2H buffers have different access patterns (H2G is CPU-write,
GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
benefit from different memory placements: H2G in VRAM and G2H in system
memory. Split the CT buffer into two separate buffers—one for H2G and
one for G2H—and select the optimal placement for each.

This provides a significant performance improvement on the G2H read
path, reducing a single read from ~20 µs to under 1 µs on BMG.

Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ct.c       | 66 ++++++++++++++++++----------
 drivers/gpu/drm/xe/xe_guc_ct_types.h |  6 ++-
 2 files changed, 48 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 8a45573f8812..6a96bea40720 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct g2h_fence *g2h_fence)
 
 #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
 #define CTB_H2G_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
+#define CTB_G2H_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
 #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
 #define CTB_H2G_BUFFER_DWORDS	(CTB_H2G_BUFFER_SIZE / sizeof(u32))
 #define CTB_G2H_BUFFER_SIZE	(SZ_128K)
@@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct xe_guc_ct *ct)
 	return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
 }
 
-static size_t guc_ct_size(void)
+static size_t guc_h2g_size(void)
 {
-	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
-		CTB_G2H_BUFFER_SIZE;
+	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
+}
+
+static size_t guc_g2h_size(void)
+{
+	return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
 }
 
 static void guc_ct_fini(struct drm_device *drm, void *arg)
@@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
 	struct xe_gt *gt = ct_to_gt(ct);
 	int err;
 
-	xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
+	xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
+	xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
 
 	err = drmm_mutex_init(&xe->drm, &ct->lock);
 	if (err)
@@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
 	struct xe_tile *tile = gt_to_tile(gt);
 	struct xe_bo *bo;
 
-	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
+	bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
+					  XE_BO_FLAG_SYSTEM |
+					  XE_BO_FLAG_GGTT |
+					  XE_BO_FLAG_GGTT_INVALIDATE |
+					  XE_BO_FLAG_PINNED_NORESTORE);
+	if (IS_ERR(bo))
+		return PTR_ERR(bo);
+
+	ct->bo_h2g = bo;
+
+	bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
 					  XE_BO_FLAG_SYSTEM |
 					  XE_BO_FLAG_GGTT |
 					  XE_BO_FLAG_GGTT_INVALIDATE |
@@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
 
-	ct->bo = bo;
+	ct->bo_g2h = bo;
 
 	return devm_add_action_or_reset(xe->drm.dev, guc_action_disable_ct, ct);
 }
@@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct)
 	xe_assert(xe, !xe_guc_ct_enabled(ct));
 
 	if (IS_DGFX(xe)) {
-		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo);
+		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo_h2g);
 		if (ret)
 			return ret;
 	}
@@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device *xe, struct guc_ctb *g2h,
 	g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
 	xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
 
-	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET +
-					    CTB_H2G_BUFFER_SIZE);
+	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_G2H_BUFFER_OFFSET);
 }
 
 static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
@@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
 	u32 desc_addr, ctb_addr, size;
 	int err;
 
-	desc_addr = xe_bo_ggtt_addr(ct->bo);
-	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
+	desc_addr = xe_bo_ggtt_addr(ct->bo_h2g);
+	ctb_addr = xe_bo_ggtt_addr(ct->bo_h2g) + CTB_H2G_BUFFER_OFFSET;
 	size = ct->ctbs.h2g.info.size * sizeof(u32);
 
 	err = xe_guc_self_cfg64(guc,
@@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct xe_guc_ct *ct)
 	u32 desc_addr, ctb_addr, size;
 	int err;
 
-	desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
-	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
-		CTB_H2G_BUFFER_SIZE;
+	desc_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_DESC_SIZE;
+	ctb_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_G2H_BUFFER_OFFSET;
 	size = ct->ctbs.g2h.info.size * sizeof(u32);
 
 	err = xe_guc_self_cfg64(guc,
@@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
 	xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
 
 	if (needs_register) {
-		xe_map_memset(xe, &ct->bo->vmap, 0, 0, xe_bo_size(ct->bo));
-		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo->vmap);
-		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo->vmap);
+		xe_map_memset(xe, &ct->bo_h2g->vmap, 0, 0,
+			      xe_bo_size(ct->bo_h2g));
+		xe_map_memset(xe, &ct->bo_g2h->vmap, 0, 0,
+			      xe_bo_size(ct->bo_g2h));
+		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo_h2g->vmap);
+		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo_g2h->vmap);
 
 		err = guc_ct_ctb_h2g_register(ct);
 		if (err)
@@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
 		ct->ctbs.h2g.info.broken = false;
 		ct->ctbs.g2h.info.broken = false;
 		/* Skip everything in H2G buffer */
-		xe_map_memset(xe, &ct->bo->vmap, CTB_H2G_BUFFER_OFFSET, 0,
+		xe_map_memset(xe, &ct->bo_h2g->vmap, CTB_H2G_BUFFER_OFFSET, 0,
 			      CTB_H2G_BUFFER_SIZE);
 	}
 
@@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
 	if (!snapshot)
 		return NULL;
 
-	if (ct->bo && want_ctb) {
-		snapshot->ctb_size = xe_bo_size(ct->bo);
+	if (ct->bo_h2g && ct->bo_g2h && want_ctb) {
+		snapshot->ctb_size = xe_bo_size(ct->bo_h2g) +
+			xe_bo_size(ct->bo_g2h);
 		snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ? GFP_ATOMIC : GFP_KERNEL);
 	}
 
@@ -2012,8 +2030,12 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
 		guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h, &snapshot->g2h);
 	}
 
-	if (ct->bo && snapshot->ctb)
-		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap, 0, snapshot->ctb_size);
+	if (ct->bo_h2g && ct->bo_g2h && snapshot->ctb) {
+		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo_h2g->vmap, 0,
+				   xe_bo_size(ct->bo_h2g));
+		xe_map_memcpy_from(xe, snapshot->ctb + xe_bo_size(ct->bo_h2g),
+				   &ct->bo_g2h->vmap, 0, xe_bo_size(ct->bo_g2h));
+	}
 
 	return snapshot;
 }
diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h
index 09d7ff1ef42a..385a607e4777 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
@@ -126,8 +126,10 @@ struct xe_fast_req_fence {
  * for the H2G and G2H requests sent and received through the buffers.
  */
 struct xe_guc_ct {
-	/** @bo: Xe BO for CT */
-	struct xe_bo *bo;
+	/** @bo_h2g: Xe BO for H2G */
+	struct xe_bo *bo_h2g;
+	/** @bo_g2h: Xe BO for G2H */
+	struct xe_bo *bo_g2h;
 	/** @lock: protects everything in CT layer */
 	struct mutex lock;
 	/** @fast_lock: protects G2H channel and credits */
-- 
2.34.1

Re: [PATCH v2 1/2] drm/xe: Split H2G and G2H into separate buffer objects

[Michal Wajdeczko]

On 2/13/2026 10:16 PM, Matthew Brost wrote:
> H2G and G2H buffers have different access patterns (H2G is CPU-write,
> GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
> benefit from different memory placements: H2G in VRAM and G2H in system
> memory. Split the CT buffer into two separate buffers—one for H2G and
> one for G2H—and select the optimal placement for each.
> 
> This provides a significant performance improvement on the G2H read
> path, reducing a single read from ~20 µs to under 1 µs on BMG.
> 
> Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_ct.c       | 66 ++++++++++++++++++----------
>  drivers/gpu/drm/xe/xe_guc_ct_types.h |  6 ++-
>  2 files changed, 48 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 8a45573f8812..6a96bea40720 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct g2h_fence *g2h_fence)
>  
>  #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
>  #define CTB_H2G_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
> +#define CTB_G2H_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
>  #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
>  #define CTB_H2G_BUFFER_DWORDS	(CTB_H2G_BUFFER_SIZE / sizeof(u32))
>  #define CTB_G2H_BUFFER_SIZE	(SZ_128K)
> @@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct xe_guc_ct *ct)
>  	return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
>  }
>  
> -static size_t guc_ct_size(void)
> +static size_t guc_h2g_size(void)
>  {
> -	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> -		CTB_G2H_BUFFER_SIZE;
> +	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> +}
> +
> +static size_t guc_g2h_size(void)
> +{
> +	return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
>  }
>  
>  static void guc_ct_fini(struct drm_device *drm, void *arg)
> @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
>  	struct xe_gt *gt = ct_to_gt(ct);
>  	int err;
>  
> -	xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> +	xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
> +	xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));

nit: maybe it's time to use SZ_4K here instead of PAGE_SIZE?

>  
>  	err = drmm_mutex_init(&xe->drm, &ct->lock);
>  	if (err)
> @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
>  	struct xe_tile *tile = gt_to_tile(gt);
>  	struct xe_bo *bo;

nit: can we drop this local var and assign bo to ct struct members directly ?

>  
> -	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
> +	bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
> +					  XE_BO_FLAG_SYSTEM |
> +					  XE_BO_FLAG_GGTT |
> +					  XE_BO_FLAG_GGTT_INVALIDATE |
> +					  XE_BO_FLAG_PINNED_NORESTORE);
> +	if (IS_ERR(bo))
> +		return PTR_ERR(bo);
> +
> +	ct->bo_h2g = bo;
> +
> +	bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
>  					  XE_BO_FLAG_SYSTEM |
>  					  XE_BO_FLAG_GGTT |
>  					  XE_BO_FLAG_GGTT_INVALIDATE |
> @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
>  	if (IS_ERR(bo))
>  		return PTR_ERR(bo);
>  
> -	ct->bo = bo;
> +	ct->bo_g2h = bo;
>  
>  	return devm_add_action_or_reset(xe->drm.dev, guc_action_disable_ct, ct);
>  }
> @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct)
>  	xe_assert(xe, !xe_guc_ct_enabled(ct));
>  
>  	if (IS_DGFX(xe)) {
> -		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo);
> +		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo_h2g);
>  		if (ret)
>  			return ret;
>  	}
> @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device *xe, struct guc_ctb *g2h,
>  	g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
>  	xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
>  
> -	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET +
> -					    CTB_H2G_BUFFER_SIZE);
> +	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_G2H_BUFFER_OFFSET);
>  }
>  
>  static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
>  	u32 desc_addr, ctb_addr, size;
>  	int err;
>  
> -	desc_addr = xe_bo_ggtt_addr(ct->bo);
> -	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
> +	desc_addr = xe_bo_ggtt_addr(ct->bo_h2g);
> +	ctb_addr = xe_bo_ggtt_addr(ct->bo_h2g) + CTB_H2G_BUFFER_OFFSET;
>  	size = ct->ctbs.h2g.info.size * sizeof(u32);
>  
>  	err = xe_guc_self_cfg64(guc,
> @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct xe_guc_ct *ct)
>  	u32 desc_addr, ctb_addr, size;
>  	int err;
>  
> -	desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> -	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
> -		CTB_H2G_BUFFER_SIZE;
> +	desc_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_DESC_SIZE;
> +	ctb_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_G2H_BUFFER_OFFSET;
>  	size = ct->ctbs.g2h.info.size * sizeof(u32);
>  
>  	err = xe_guc_self_cfg64(guc,
> @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
>  	xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
>  
>  	if (needs_register) {
> -		xe_map_memset(xe, &ct->bo->vmap, 0, 0, xe_bo_size(ct->bo));
> -		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo->vmap);
> -		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo->vmap);
> +		xe_map_memset(xe, &ct->bo_h2g->vmap, 0, 0,
> +			      xe_bo_size(ct->bo_h2g));
> +		xe_map_memset(xe, &ct->bo_g2h->vmap, 0, 0,
> +			      xe_bo_size(ct->bo_g2h));
> +		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo_h2g->vmap);
> +		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo_g2h->vmap);
>  
>  		err = guc_ct_ctb_h2g_register(ct);
>  		if (err)
> @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
>  		ct->ctbs.h2g.info.broken = false;
>  		ct->ctbs.g2h.info.broken = false;
>  		/* Skip everything in H2G buffer */
> -		xe_map_memset(xe, &ct->bo->vmap, CTB_H2G_BUFFER_OFFSET, 0,
> +		xe_map_memset(xe, &ct->bo_h2g->vmap, CTB_H2G_BUFFER_OFFSET, 0,
>  			      CTB_H2G_BUFFER_SIZE);
>  	}
>  
> @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
>  	if (!snapshot)
>  		return NULL;
>  
> -	if (ct->bo && want_ctb) {
> -		snapshot->ctb_size = xe_bo_size(ct->bo);
> +	if (ct->bo_h2g && ct->bo_g2h && want_ctb) {
> +		snapshot->ctb_size = xe_bo_size(ct->bo_h2g) +
> +			xe_bo_size(ct->bo_g2h);
>  		snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ? GFP_ATOMIC : GFP_KERNEL);
>  	}
>  
> @@ -2012,8 +2030,12 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
>  		guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h, &snapshot->g2h);
>  	}
>  
> -	if (ct->bo && snapshot->ctb)
> -		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap, 0, snapshot->ctb_size);
> +	if (ct->bo_h2g && ct->bo_g2h && snapshot->ctb) {
> +		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo_h2g->vmap, 0,
> +				   xe_bo_size(ct->bo_h2g));
> +		xe_map_memcpy_from(xe, snapshot->ctb + xe_bo_size(ct->bo_h2g),
> +				   &ct->bo_g2h->vmap, 0, xe_bo_size(ct->bo_g2h));
> +	}
>  
>  	return snapshot;
>  }
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> index 09d7ff1ef42a..385a607e4777 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> @@ -126,8 +126,10 @@ struct xe_fast_req_fence {
>   * for the H2G and G2H requests sent and received through the buffers.
>   */
>  struct xe_guc_ct {
> -	/** @bo: Xe BO for CT */
> -	struct xe_bo *bo;
> +	/** @bo_h2g: Xe BO for H2G */
> +	struct xe_bo *bo_h2g;
> +	/** @bo_g2h: Xe BO for G2H */
> +	struct xe_bo *bo_g2h;

since we already have h2g and g2h:

	struct {
		/** @ctbs.send: Host to GuC (H2G, send) channel */
		struct guc_ctb h2g;
		/** @ctbs.recv: GuC to Host (G2H, receive) channel */
		struct guc_ctb g2h;
	} ctbs;

maybe just add .bo member to struct guc_ctb?


>  	/** @lock: protects everything in CT layer */
>  	struct mutex lock;
>  	/** @fast_lock: protects G2H channel and credits */

Re: [PATCH v2 1/2] drm/xe: Split H2G and G2H into separate buffer objects

[Matthew Brost]

On Fri, Feb 13, 2026 at 11:55:14PM +0100, Michal Wajdeczko wrote:
> 
> 
> On 2/13/2026 10:16 PM, Matthew Brost wrote:
> > H2G and G2H buffers have different access patterns (H2G is CPU-write,
> > GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
> > benefit from different memory placements: H2G in VRAM and G2H in system
> > memory. Split the CT buffer into two separate buffers—one for H2G and
> > one for G2H—and select the optimal placement for each.
> > 
> > This provides a significant performance improvement on the G2H read
> > path, reducing a single read from ~20 µs to under 1 µs on BMG.
> > 
> > Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_guc_ct.c       | 66 ++++++++++++++++++----------
> >  drivers/gpu/drm/xe/xe_guc_ct_types.h |  6 ++-
> >  2 files changed, 48 insertions(+), 24 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> > index 8a45573f8812..6a96bea40720 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct g2h_fence *g2h_fence)
> >  
> >  #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
> >  #define CTB_H2G_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
> > +#define CTB_G2H_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
> >  #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
> >  #define CTB_H2G_BUFFER_DWORDS	(CTB_H2G_BUFFER_SIZE / sizeof(u32))
> >  #define CTB_G2H_BUFFER_SIZE	(SZ_128K)
> > @@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct xe_guc_ct *ct)
> >  	return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
> >  }
> >  
> > -static size_t guc_ct_size(void)
> > +static size_t guc_h2g_size(void)
> >  {
> > -	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> > -		CTB_G2H_BUFFER_SIZE;
> > +	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> > +}
> > +
> > +static size_t guc_g2h_size(void)
> > +{
> > +	return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
> >  }
> >  
> >  static void guc_ct_fini(struct drm_device *drm, void *arg)
> > @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
> >  	struct xe_gt *gt = ct_to_gt(ct);
> >  	int err;
> >  
> > -	xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> > +	xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
> > +	xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
> 
> nit: maybe it's time to use SZ_4K here instead of PAGE_SIZE?
> 

Not a nit actually, this is a correctness thing and SZ_4K is correct or
XE_PAGE_SIZE. 

> >  
> >  	err = drmm_mutex_init(&xe->drm, &ct->lock);
> >  	if (err)
> > @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> >  	struct xe_tile *tile = gt_to_tile(gt);
> >  	struct xe_bo *bo;
> 
> nit: can we drop this local var and assign bo to ct struct members directly ?
> 

Yes.

> >  
> > -	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
> > +	bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
> > +					  XE_BO_FLAG_SYSTEM |
> > +					  XE_BO_FLAG_GGTT |
> > +					  XE_BO_FLAG_GGTT_INVALIDATE |
> > +					  XE_BO_FLAG_PINNED_NORESTORE);
> > +	if (IS_ERR(bo))
> > +		return PTR_ERR(bo);
> > +
> > +	ct->bo_h2g = bo;
> > +
> > +	bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
> >  					  XE_BO_FLAG_SYSTEM |
> >  					  XE_BO_FLAG_GGTT |
> >  					  XE_BO_FLAG_GGTT_INVALIDATE |
> > @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> >  	if (IS_ERR(bo))
> >  		return PTR_ERR(bo);
> >  
> > -	ct->bo = bo;
> > +	ct->bo_g2h = bo;
> >  
> >  	return devm_add_action_or_reset(xe->drm.dev, guc_action_disable_ct, ct);
> >  }
> > @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct)
> >  	xe_assert(xe, !xe_guc_ct_enabled(ct));
> >  
> >  	if (IS_DGFX(xe)) {
> > -		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo);
> > +		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo_h2g);
> >  		if (ret)
> >  			return ret;
> >  	}
> > @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device *xe, struct guc_ctb *g2h,
> >  	g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
> >  	xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
> >  
> > -	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET +
> > -					    CTB_H2G_BUFFER_SIZE);
> > +	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_G2H_BUFFER_OFFSET);
> >  }
> >  
> >  static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> > @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> >  	u32 desc_addr, ctb_addr, size;
> >  	int err;
> >  
> > -	desc_addr = xe_bo_ggtt_addr(ct->bo);
> > -	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
> > +	desc_addr = xe_bo_ggtt_addr(ct->bo_h2g);
> > +	ctb_addr = xe_bo_ggtt_addr(ct->bo_h2g) + CTB_H2G_BUFFER_OFFSET;
> >  	size = ct->ctbs.h2g.info.size * sizeof(u32);
> >  
> >  	err = xe_guc_self_cfg64(guc,
> > @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct xe_guc_ct *ct)
> >  	u32 desc_addr, ctb_addr, size;
> >  	int err;
> >  
> > -	desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> > -	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
> > -		CTB_H2G_BUFFER_SIZE;
> > +	desc_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_DESC_SIZE;
> > +	ctb_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_G2H_BUFFER_OFFSET;
> >  	size = ct->ctbs.g2h.info.size * sizeof(u32);
> >  
> >  	err = xe_guc_self_cfg64(guc,
> > @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
> >  	xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
> >  
> >  	if (needs_register) {
> > -		xe_map_memset(xe, &ct->bo->vmap, 0, 0, xe_bo_size(ct->bo));
> > -		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo->vmap);
> > -		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo->vmap);
> > +		xe_map_memset(xe, &ct->bo_h2g->vmap, 0, 0,
> > +			      xe_bo_size(ct->bo_h2g));
> > +		xe_map_memset(xe, &ct->bo_g2h->vmap, 0, 0,
> > +			      xe_bo_size(ct->bo_g2h));
> > +		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo_h2g->vmap);
> > +		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo_g2h->vmap);
> >  
> >  		err = guc_ct_ctb_h2g_register(ct);
> >  		if (err)
> > @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
> >  		ct->ctbs.h2g.info.broken = false;
> >  		ct->ctbs.g2h.info.broken = false;
> >  		/* Skip everything in H2G buffer */
> > -		xe_map_memset(xe, &ct->bo->vmap, CTB_H2G_BUFFER_OFFSET, 0,
> > +		xe_map_memset(xe, &ct->bo_h2g->vmap, CTB_H2G_BUFFER_OFFSET, 0,
> >  			      CTB_H2G_BUFFER_SIZE);
> >  	}
> >  
> > @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
> >  	if (!snapshot)
> >  		return NULL;
> >  
> > -	if (ct->bo && want_ctb) {
> > -		snapshot->ctb_size = xe_bo_size(ct->bo);
> > +	if (ct->bo_h2g && ct->bo_g2h && want_ctb) {
> > +		snapshot->ctb_size = xe_bo_size(ct->bo_h2g) +
> > +			xe_bo_size(ct->bo_g2h);
> >  		snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ? GFP_ATOMIC : GFP_KERNEL);
> >  	}
> >  
> > @@ -2012,8 +2030,12 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
> >  		guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h, &snapshot->g2h);
> >  	}
> >  
> > -	if (ct->bo && snapshot->ctb)
> > -		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap, 0, snapshot->ctb_size);
> > +	if (ct->bo_h2g && ct->bo_g2h && snapshot->ctb) {
> > +		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo_h2g->vmap, 0,
> > +				   xe_bo_size(ct->bo_h2g));
> > +		xe_map_memcpy_from(xe, snapshot->ctb + xe_bo_size(ct->bo_h2g),
> > +				   &ct->bo_g2h->vmap, 0, xe_bo_size(ct->bo_g2h));
> > +	}
> >  
> >  	return snapshot;
> >  }
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > index 09d7ff1ef42a..385a607e4777 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > @@ -126,8 +126,10 @@ struct xe_fast_req_fence {
> >   * for the H2G and G2H requests sent and received through the buffers.
> >   */
> >  struct xe_guc_ct {
> > -	/** @bo: Xe BO for CT */
> > -	struct xe_bo *bo;
> > +	/** @bo_h2g: Xe BO for H2G */
> > +	struct xe_bo *bo_h2g;
> > +	/** @bo_g2h: Xe BO for G2H */
> > +	struct xe_bo *bo_g2h;
> 
> since we already have h2g and g2h:
> 
> 	struct {
> 		/** @ctbs.send: Host to GuC (H2G, send) channel */
> 		struct guc_ctb h2g;
> 		/** @ctbs.recv: GuC to Host (G2H, receive) channel */
> 		struct guc_ctb g2h;
> 	} ctbs;
> 
> maybe just add .bo member to struct guc_ctb?
> 

I thought about this, was trying to keep the diff to minimum for fixes
but moving it there is likely fine.

Matt

> 
> >  	/** @lock: protects everything in CT layer */
> >  	struct mutex lock;
> >  	/** @fast_lock: protects G2H channel and credits */
> 

Re: [PATCH v2 1/2] drm/xe: Split H2G and G2H into separate buffer objects

[Matthew Brost]

On Fri, Feb 13, 2026 at 04:54:45PM -0800, Matthew Brost wrote:
> On Fri, Feb 13, 2026 at 11:55:14PM +0100, Michal Wajdeczko wrote:
> > 
> > 
> > On 2/13/2026 10:16 PM, Matthew Brost wrote:
> > > H2G and G2H buffers have different access patterns (H2G is CPU-write,
> > > GuC-read, while G2H is GPU-write, CPU-read). On dGPU, these patterns
> > > benefit from different memory placements: H2G in VRAM and G2H in system
> > > memory. Split the CT buffer into two separate buffers—one for H2G and
> > > one for G2H—and select the optimal placement for each.
> > > 
> > > This provides a significant performance improvement on the G2H read
> > > path, reducing a single read from ~20 µs to under 1 µs on BMG.
> > > 
> > > Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_guc_ct.c       | 66 ++++++++++++++++++----------
> > >  drivers/gpu/drm/xe/xe_guc_ct_types.h |  6 ++-
> > >  2 files changed, 48 insertions(+), 24 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > index 8a45573f8812..6a96bea40720 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > @@ -255,6 +255,7 @@ static bool g2h_fence_needs_alloc(struct g2h_fence *g2h_fence)
> > >  
> > >  #define CTB_DESC_SIZE		ALIGN(sizeof(struct guc_ct_buffer_desc), SZ_2K)
> > >  #define CTB_H2G_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
> > > +#define CTB_G2H_BUFFER_OFFSET	(CTB_DESC_SIZE * 2)
> > >  #define CTB_H2G_BUFFER_SIZE	(SZ_4K)
> > >  #define CTB_H2G_BUFFER_DWORDS	(CTB_H2G_BUFFER_SIZE / sizeof(u32))
> > >  #define CTB_G2H_BUFFER_SIZE	(SZ_128K)
> > > @@ -279,10 +280,14 @@ long xe_guc_ct_queue_proc_time_jiffies(struct xe_guc_ct *ct)
> > >  	return (CTB_H2G_BUFFER_SIZE / SZ_4K) * HZ;
> > >  }
> > >  
> > > -static size_t guc_ct_size(void)
> > > +static size_t guc_h2g_size(void)
> > >  {
> > > -	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE +
> > > -		CTB_G2H_BUFFER_SIZE;
> > > +	return CTB_H2G_BUFFER_OFFSET + CTB_H2G_BUFFER_SIZE;
> > > +}
> > > +
> > > +static size_t guc_g2h_size(void)
> > > +{
> > > +	return CTB_G2H_BUFFER_OFFSET + CTB_G2H_BUFFER_SIZE;
> > >  }
> > >  
> > >  static void guc_ct_fini(struct drm_device *drm, void *arg)
> > > @@ -311,7 +316,8 @@ int xe_guc_ct_init_noalloc(struct xe_guc_ct *ct)
> > >  	struct xe_gt *gt = ct_to_gt(ct);
> > >  	int err;
> > >  
> > > -	xe_gt_assert(gt, !(guc_ct_size() % PAGE_SIZE));
> > > +	xe_gt_assert(gt, !(guc_h2g_size() % PAGE_SIZE));
> > > +	xe_gt_assert(gt, !(guc_g2h_size() % PAGE_SIZE));
> > 
> > nit: maybe it's time to use SZ_4K here instead of PAGE_SIZE?
> > 
> 
> Not a nit actually, this is a correctness thing and SZ_4K is correct or
> XE_PAGE_SIZE. 
> 

On second thought - PAGE_SIZE is right here as these are CPU mapped.
There is an existing bug here for non-x86 CPUs with non-4k PAGE_SIZE
(currently unsupported). This a seperate issue and as this is a fixes,
I'd like to fix this up in follow up.

Matt 

> > >  
> > >  	err = drmm_mutex_init(&xe->drm, &ct->lock);
> > >  	if (err)
> > > @@ -356,7 +362,17 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > >  	struct xe_tile *tile = gt_to_tile(gt);
> > >  	struct xe_bo *bo;
> > 
> > nit: can we drop this local var and assign bo to ct struct members directly ?
> > 
> 
> Yes.
> 
> > >  
> > > -	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
> > > +	bo = xe_managed_bo_create_pin_map(xe, tile, guc_h2g_size(),
> > > +					  XE_BO_FLAG_SYSTEM |
> > > +					  XE_BO_FLAG_GGTT |
> > > +					  XE_BO_FLAG_GGTT_INVALIDATE |
> > > +					  XE_BO_FLAG_PINNED_NORESTORE);
> > > +	if (IS_ERR(bo))
> > > +		return PTR_ERR(bo);
> > > +
> > > +	ct->bo_h2g = bo;
> > > +
> > > +	bo = xe_managed_bo_create_pin_map(xe, tile, guc_g2h_size(),
> > >  					  XE_BO_FLAG_SYSTEM |
> > >  					  XE_BO_FLAG_GGTT |
> > >  					  XE_BO_FLAG_GGTT_INVALIDATE |
> > > @@ -364,7 +380,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> > >  	if (IS_ERR(bo))
> > >  		return PTR_ERR(bo);
> > >  
> > > -	ct->bo = bo;
> > > +	ct->bo_g2h = bo;
> > >  
> > >  	return devm_add_action_or_reset(xe->drm.dev, guc_action_disable_ct, ct);
> > >  }
> > > @@ -389,7 +405,7 @@ int xe_guc_ct_init_post_hwconfig(struct xe_guc_ct *ct)
> > >  	xe_assert(xe, !xe_guc_ct_enabled(ct));
> > >  
> > >  	if (IS_DGFX(xe)) {
> > > -		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo);
> > > +		ret = xe_managed_bo_reinit_in_vram(xe, tile, &ct->bo_h2g);
> > >  		if (ret)
> > >  			return ret;
> > >  	}
> > > @@ -439,8 +455,7 @@ static void guc_ct_ctb_g2h_init(struct xe_device *xe, struct guc_ctb *g2h,
> > >  	g2h->desc = IOSYS_MAP_INIT_OFFSET(map, CTB_DESC_SIZE);
> > >  	xe_map_memset(xe, &g2h->desc, 0, 0, sizeof(struct guc_ct_buffer_desc));
> > >  
> > > -	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_H2G_BUFFER_OFFSET +
> > > -					    CTB_H2G_BUFFER_SIZE);
> > > +	g2h->cmds = IOSYS_MAP_INIT_OFFSET(map, CTB_G2H_BUFFER_OFFSET);
> > >  }
> > >  
> > >  static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> > > @@ -449,8 +464,8 @@ static int guc_ct_ctb_h2g_register(struct xe_guc_ct *ct)
> > >  	u32 desc_addr, ctb_addr, size;
> > >  	int err;
> > >  
> > > -	desc_addr = xe_bo_ggtt_addr(ct->bo);
> > > -	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET;
> > > +	desc_addr = xe_bo_ggtt_addr(ct->bo_h2g);
> > > +	ctb_addr = xe_bo_ggtt_addr(ct->bo_h2g) + CTB_H2G_BUFFER_OFFSET;
> > >  	size = ct->ctbs.h2g.info.size * sizeof(u32);
> > >  
> > >  	err = xe_guc_self_cfg64(guc,
> > > @@ -476,9 +491,8 @@ static int guc_ct_ctb_g2h_register(struct xe_guc_ct *ct)
> > >  	u32 desc_addr, ctb_addr, size;
> > >  	int err;
> > >  
> > > -	desc_addr = xe_bo_ggtt_addr(ct->bo) + CTB_DESC_SIZE;
> > > -	ctb_addr = xe_bo_ggtt_addr(ct->bo) + CTB_H2G_BUFFER_OFFSET +
> > > -		CTB_H2G_BUFFER_SIZE;
> > > +	desc_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_DESC_SIZE;
> > > +	ctb_addr = xe_bo_ggtt_addr(ct->bo_g2h) + CTB_G2H_BUFFER_OFFSET;
> > >  	size = ct->ctbs.g2h.info.size * sizeof(u32);
> > >  
> > >  	err = xe_guc_self_cfg64(guc,
> > > @@ -605,9 +619,12 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
> > >  	xe_gt_assert(gt, !xe_guc_ct_enabled(ct));
> > >  
> > >  	if (needs_register) {
> > > -		xe_map_memset(xe, &ct->bo->vmap, 0, 0, xe_bo_size(ct->bo));
> > > -		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo->vmap);
> > > -		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo->vmap);
> > > +		xe_map_memset(xe, &ct->bo_h2g->vmap, 0, 0,
> > > +			      xe_bo_size(ct->bo_h2g));
> > > +		xe_map_memset(xe, &ct->bo_g2h->vmap, 0, 0,
> > > +			      xe_bo_size(ct->bo_g2h));
> > > +		guc_ct_ctb_h2g_init(xe, &ct->ctbs.h2g, &ct->bo_h2g->vmap);
> > > +		guc_ct_ctb_g2h_init(xe, &ct->ctbs.g2h, &ct->bo_g2h->vmap);
> > >  
> > >  		err = guc_ct_ctb_h2g_register(ct);
> > >  		if (err)
> > > @@ -624,7 +641,7 @@ static int __xe_guc_ct_start(struct xe_guc_ct *ct, bool needs_register)
> > >  		ct->ctbs.h2g.info.broken = false;
> > >  		ct->ctbs.g2h.info.broken = false;
> > >  		/* Skip everything in H2G buffer */
> > > -		xe_map_memset(xe, &ct->bo->vmap, CTB_H2G_BUFFER_OFFSET, 0,
> > > +		xe_map_memset(xe, &ct->bo_h2g->vmap, CTB_H2G_BUFFER_OFFSET, 0,
> > >  			      CTB_H2G_BUFFER_SIZE);
> > >  	}
> > >  
> > > @@ -1963,8 +1980,9 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bo
> > >  	if (!snapshot)
> > >  		return NULL;
> > >  
> > > -	if (ct->bo && want_ctb) {
> > > -		snapshot->ctb_size = xe_bo_size(ct->bo);
> > > +	if (ct->bo_h2g && ct->bo_g2h && want_ctb) {
> > > +		snapshot->ctb_size = xe_bo_size(ct->bo_h2g) +
> > > +			xe_bo_size(ct->bo_g2h);
> > >  		snapshot->ctb = kmalloc(snapshot->ctb_size, atomic ? GFP_ATOMIC : GFP_KERNEL);
> > >  	}
> > >  
> > > @@ -2012,8 +2030,12 @@ static struct xe_guc_ct_snapshot *guc_ct_snapshot_capture(struct xe_guc_ct *ct,
> > >  		guc_ctb_snapshot_capture(xe, &ct->ctbs.g2h, &snapshot->g2h);
> > >  	}
> > >  
> > > -	if (ct->bo && snapshot->ctb)
> > > -		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo->vmap, 0, snapshot->ctb_size);
> > > +	if (ct->bo_h2g && ct->bo_g2h && snapshot->ctb) {
> > > +		xe_map_memcpy_from(xe, snapshot->ctb, &ct->bo_h2g->vmap, 0,
> > > +				   xe_bo_size(ct->bo_h2g));
> > > +		xe_map_memcpy_from(xe, snapshot->ctb + xe_bo_size(ct->bo_h2g),
> > > +				   &ct->bo_g2h->vmap, 0, xe_bo_size(ct->bo_g2h));
> > > +	}
> > >  
> > >  	return snapshot;
> > >  }
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > index 09d7ff1ef42a..385a607e4777 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
> > > @@ -126,8 +126,10 @@ struct xe_fast_req_fence {
> > >   * for the H2G and G2H requests sent and received through the buffers.
> > >   */
> > >  struct xe_guc_ct {
> > > -	/** @bo: Xe BO for CT */
> > > -	struct xe_bo *bo;
> > > +	/** @bo_h2g: Xe BO for H2G */
> > > +	struct xe_bo *bo_h2g;
> > > +	/** @bo_g2h: Xe BO for G2H */
> > > +	struct xe_bo *bo_g2h;
> > 
> > since we already have h2g and g2h:
> > 
> > 	struct {
> > 		/** @ctbs.send: Host to GuC (H2G, send) channel */
> > 		struct guc_ctb h2g;
> > 		/** @ctbs.recv: GuC to Host (G2H, receive) channel */
> > 		struct guc_ctb g2h;
> > 	} ctbs;
> > 
> > maybe just add .bo member to struct guc_ctb?
> > 
> 
> I thought about this, was trying to keep the diff to minimum for fixes
> but moving it there is likely fine.
> 
> Matt
> 
> > 
> > >  	/** @lock: protects everything in CT layer */
> > >  	struct mutex lock;
> > >  	/** @fast_lock: protects G2H channel and credits */
> > 

[PATCH v2 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds

[Matthew Brost]

A single VRAM read on BMG can take over 1µs. While small, this is a
non-trivial amount of time in a hot path. Remove the descriptor H2G read
(potentially a VRAM access) from non-debug builds, as this
error-checking code is not needed outside of debug configurations.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ct.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 6a96bea40720..f200d3ee9d22 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
 	u32 full_len;
 	struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
 							 tail * sizeof(u32));
-	u32 desc_status;
 
 	full_len = len + GUC_CTB_HDR_LEN;
 
 	lockdep_assert_held(&ct->lock);
 	xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
 
-	desc_status = desc_read(xe, h2g, status);
-	if (desc_status) {
-		xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
-		goto corrupted;
-	}
-
 	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
 		u32 desc_tail = desc_read(xe, h2g, tail);
 		u32 desc_head = desc_read(xe, h2g, head);
+		u32 desc_status;
+
+		desc_status = desc_read(xe, h2g, status);
+		if (desc_status) {
+			xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
+			goto corrupted;
+		}
 
 		if (tail != desc_tail) {
 			desc_write(xe, h2g, status, desc_status | GUC_CTB_STATUS_MISMATCH);
-- 
2.34.1

Re: [PATCH v2 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds

[Francois Dugast]

mOn Fri, Feb 13, 2026 at 01:16:25PM -0800, Matthew Brost wrote:
> A single VRAM read on BMG can take over 1µs. While small, this is a
> non-trivial amount of time in a hot path. Remove the descriptor H2G read
> (potentially a VRAM access) from non-debug builds, as this
> error-checking code is not needed outside of debug configurations.

About the change itself: I understand the performance benefit and this would
make the code consistent with the 2 other reads.

But the existing block under "if (IS_ENABLED(CONFIG_DRM_XE_DEBUG))" seems wrong
because it is not just about optionally printing some debug statements, in case
of error the function actually returns a different value if CONFIG_DRM_XE_DEBUG
is enabled or not (goto), and this return value is used in __guc_ct_send_locked.

Francois

> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_ct.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 6a96bea40720..f200d3ee9d22 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
>  	u32 full_len;
>  	struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
>  							 tail * sizeof(u32));
> -	u32 desc_status;
>  
>  	full_len = len + GUC_CTB_HDR_LEN;
>  
>  	lockdep_assert_held(&ct->lock);
>  	xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
>  
> -	desc_status = desc_read(xe, h2g, status);
> -	if (desc_status) {
> -		xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
> -		goto corrupted;
> -	}
> -
>  	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
>  		u32 desc_tail = desc_read(xe, h2g, tail);
>  		u32 desc_head = desc_read(xe, h2g, head);
> +		u32 desc_status;
> +
> +		desc_status = desc_read(xe, h2g, status);
> +		if (desc_status) {
> +			xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
> +			goto corrupted;
> +		}
>  
>  		if (tail != desc_tail) {
>  			desc_write(xe, h2g, status, desc_status | GUC_CTB_STATUS_MISMATCH);
> -- 
> 2.34.1
> 

Re: [PATCH v2 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds

[Matthew Brost]

On Mon, Feb 16, 2026 at 01:51:57PM +0100, Francois Dugast wrote:
> mOn Fri, Feb 13, 2026 at 01:16:25PM -0800, Matthew Brost wrote:
> > A single VRAM read on BMG can take over 1µs. While small, this is a
> > non-trivial amount of time in a hot path. Remove the descriptor H2G read
> > (potentially a VRAM access) from non-debug builds, as this
> > error-checking code is not needed outside of debug configurations.
> 
> About the change itself: I understand the performance benefit and this would
> make the code consistent with the 2 other reads.
> 

Yes.

> But the existing block under "if (IS_ENABLED(CONFIG_DRM_XE_DEBUG))" seems wrong
> because it is not just about optionally printing some debug statements, in case
> of error the function actually returns a different value if CONFIG_DRM_XE_DEBUG
> is enabled or not (goto), and this return value is used in __guc_ct_send_locked.
> 

I can't realy argue with this logic but I also see the benefits of
verbose checking of GuC state in CI configs. fwiw, this logic was added
here:

git format-patch -1 d2c5a5a926f43

The cost of reads are actually huge here - this patch by itself is
incomplete as a tracepoint below does a desc_read in the argument list
and this is uncoditionally executed even if ftrace is disabled. On BMG H2G
before this patch / fixing ftrace are 3-4us, after ~300ns. So I'd
suggest we move forward with with a couple of fixes patches first, then
in a follow up either:

The cost of reads is actually huge here — this patch by itself is
incomplete, as a tracepoint below performs a desc_read in the argument
list, and that is unconditionally executed even if ftrace is disabled.
On BMG, H2G reads before this patch / fixing ftrace are 3–4-µs; after,
they’re ~300ns. So I’d suggest we move forward with a couple of fixes
patches first, and then in a follow-up:

- Move all really expensive things in GuC CT layer under
  CONFIG_DRM_XE_DEBUG_GUC, enable this Kconfig some CI run
- Perhaps just assert if GuC state is corrupted in the path mentioned
  above

Matt

> Francois
> 
> > 
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_guc_ct.c | 14 +++++++-------
> >  1 file changed, 7 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> > index 6a96bea40720..f200d3ee9d22 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > @@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
> >  	u32 full_len;
> >  	struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
> >  							 tail * sizeof(u32));
> > -	u32 desc_status;
> >  
> >  	full_len = len + GUC_CTB_HDR_LEN;
> >  
> >  	lockdep_assert_held(&ct->lock);
> >  	xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
> >  
> > -	desc_status = desc_read(xe, h2g, status);
> > -	if (desc_status) {
> > -		xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
> > -		goto corrupted;
> > -	}
> > -
> >  	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
> >  		u32 desc_tail = desc_read(xe, h2g, tail);
> >  		u32 desc_head = desc_read(xe, h2g, head);
> > +		u32 desc_status;
> > +
> > +		desc_status = desc_read(xe, h2g, status);
> > +		if (desc_status) {
> > +			xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
> > +			goto corrupted;
> > +		}
> >  
> >  		if (tail != desc_tail) {
> >  			desc_write(xe, h2g, status, desc_status | GUC_CTB_STATUS_MISMATCH);
> > -- 
> > 2.34.1
> > 

Re: [PATCH v2 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds

[Francois Dugast]

On Mon, Feb 16, 2026 at 09:40:19AM -0800, Matthew Brost wrote:
> On Mon, Feb 16, 2026 at 01:51:57PM +0100, Francois Dugast wrote:
> > mOn Fri, Feb 13, 2026 at 01:16:25PM -0800, Matthew Brost wrote:
> > > A single VRAM read on BMG can take over 1µs. While small, this is a
> > > non-trivial amount of time in a hot path. Remove the descriptor H2G read
> > > (potentially a VRAM access) from non-debug builds, as this
> > > error-checking code is not needed outside of debug configurations.
> > 
> > About the change itself: I understand the performance benefit and this would
> > make the code consistent with the 2 other reads.
> > 
> 
> Yes.
> 
> > But the existing block under "if (IS_ENABLED(CONFIG_DRM_XE_DEBUG))" seems wrong
> > because it is not just about optionally printing some debug statements, in case
> > of error the function actually returns a different value if CONFIG_DRM_XE_DEBUG
> > is enabled or not (goto), and this return value is used in __guc_ct_send_locked.
> > 
> 
> I can't realy argue with this logic but I also see the benefits of
> verbose checking of GuC state in CI configs. fwiw, this logic was added
> here:
> 
> git format-patch -1 d2c5a5a926f43
> 
> The cost of reads are actually huge here - this patch by itself is
> incomplete as a tracepoint below does a desc_read in the argument list
> and this is uncoditionally executed even if ftrace is disabled. On BMG H2G
> before this patch / fixing ftrace are 3-4us, after ~300ns. So I'd
> suggest we move forward with with a couple of fixes patches first, then
> in a follow up either:
> 
> The cost of reads is actually huge here — this patch by itself is
> incomplete, as a tracepoint below performs a desc_read in the argument
> list, and that is unconditionally executed even if ftrace is disabled.
> On BMG, H2G reads before this patch / fixing ftrace are 3–4-µs; after,
> they’re ~300ns. So I’d suggest we move forward with a couple of fixes
> patches first, and then in a follow-up:
> 
> - Move all really expensive things in GuC CT layer under
>   CONFIG_DRM_XE_DEBUG_GUC, enable this Kconfig some CI run
> - Perhaps just assert if GuC state is corrupted in the path mentioned
>   above

Sounds good.

> 
> Matt
> 
> > Francois
> > 
> > > 
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_guc_ct.c | 14 +++++++-------
> > >  1 file changed, 7 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > index 6a96bea40720..f200d3ee9d22 100644
> > > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > @@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
> > >  	u32 full_len;
> > >  	struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
> > >  							 tail * sizeof(u32));
> > > -	u32 desc_status;
> > >  
> > >  	full_len = len + GUC_CTB_HDR_LEN;
> > >  
> > >  	lockdep_assert_held(&ct->lock);
> > >  	xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
> > >  
> > > -	desc_status = desc_read(xe, h2g, status);
> > > -	if (desc_status) {
> > > -		xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
> > > -		goto corrupted;
> > > -	}
> > > -
> > >  	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
> > >  		u32 desc_tail = desc_read(xe, h2g, tail);
> > >  		u32 desc_head = desc_read(xe, h2g, head);
> > > +		u32 desc_status;
> > > +
> > > +		desc_status = desc_read(xe, h2g, status);
> > > +		if (desc_status) {
> > > +			xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
> > > +			goto corrupted;
> > > +		}
> > >  
> > >  		if (tail != desc_tail) {
> > >  			desc_write(xe, h2g, status, desc_status | GUC_CTB_STATUS_MISMATCH);
> > > -- 
> > > 2.34.1
> > > 

Re: [PATCH v2 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds

[Summers, Stuart]

On Tue, 2026-02-17 at 12:19 +0100, Francois Dugast wrote:
> On Mon, Feb 16, 2026 at 09:40:19AM -0800, Matthew Brost wrote:
> > On Mon, Feb 16, 2026 at 01:51:57PM +0100, Francois Dugast wrote:
> > > mOn Fri, Feb 13, 2026 at 01:16:25PM -0800, Matthew Brost wrote:
> > > > A single VRAM read on BMG can take over 1µs. While small, this
> > > > is a
> > > > non-trivial amount of time in a hot path. Remove the descriptor
> > > > H2G read
> > > > (potentially a VRAM access) from non-debug builds, as this
> > > > error-checking code is not needed outside of debug
> > > > configurations.
> > > 
> > > About the change itself: I understand the performance benefit and
> > > this would
> > > make the code consistent with the 2 other reads.
> > > 
> > 
> > Yes.
> > 
> > > But the existing block under "if
> > > (IS_ENABLED(CONFIG_DRM_XE_DEBUG))" seems wrong
> > > because it is not just about optionally printing some debug
> > > statements, in case
> > > of error the function actually returns a different value if
> > > CONFIG_DRM_XE_DEBUG
> > > is enabled or not (goto), and this return value is used in
> > > __guc_ct_send_locked.
> > > 
> > 
> > I can't realy argue with this logic but I also see the benefits of
> > verbose checking of GuC state in CI configs. fwiw, this logic was
> > added
> > here:
> > 
> > git format-patch -1 d2c5a5a926f43
> > 
> > The cost of reads are actually huge here - this patch by itself is
> > incomplete as a tracepoint below does a desc_read in the argument
> > list
> > and this is uncoditionally executed even if ftrace is disabled. On
> > BMG H2G
> > before this patch / fixing ftrace are 3-4us, after ~300ns. So I'd
> > suggest we move forward with with a couple of fixes patches first,
> > then
> > in a follow up either:
> > 
> > The cost of reads is actually huge here — this patch by itself is
> > incomplete, as a tracepoint below performs a desc_read in the
> > argument
> > list, and that is unconditionally executed even if ftrace is
> > disabled.
> > On BMG, H2G reads before this patch / fixing ftrace are 3–4-µs;
> > after,
> > they’re ~300ns. So I’d suggest we move forward with a couple of
> > fixes
> > patches first, and then in a follow-up:
> > 
> > - Move all really expensive things in GuC CT layer under
> >   CONFIG_DRM_XE_DEBUG_GUC, enable this Kconfig some CI run
> > - Perhaps just assert if GuC state is corrupted in the path
> > mentioned
> >   above

So is the suggestion here to enable this DEBUG_GUC parameter for all
CI? We do rely on these error messages for baseline debug and sometimes
things coming out of CI (or even a customer) are hard to reproduce. I'm
a little worried removing this will drag out debug for these types of
problems.

-Stuart

> 
> Sounds good.
> 
> > 
> > Matt
> > 
> > > Francois
> > > 
> > > > 
> > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/xe/xe_guc_ct.c | 14 +++++++-------
> > > >  1 file changed, 7 insertions(+), 7 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > index 6a96bea40720..f200d3ee9d22 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > @@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct
> > > > *ct, const u32 *action, u32 len,
> > > >         u32 full_len;
> > > >         struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g-
> > > > >cmds,
> > > >                                                          tail *
> > > > sizeof(u32));
> > > > -       u32 desc_status;
> > > >  
> > > >         full_len = len + GUC_CTB_HDR_LEN;
> > > >  
> > > >         lockdep_assert_held(&ct->lock);
> > > >         xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
> > > >  
> > > > -       desc_status = desc_read(xe, h2g, status);
> > > > -       if (desc_status) {
> > > > -               xe_gt_err(gt, "CT write: non-zero status:
> > > > %u\n", desc_status);
> > > > -               goto corrupted;
> > > > -       }
> > > > -
> > > >         if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
> > > >                 u32 desc_tail = desc_read(xe, h2g, tail);
> > > >                 u32 desc_head = desc_read(xe, h2g, head);
> > > > +               u32 desc_status;
> > > > +
> > > > +               desc_status = desc_read(xe, h2g, status);
> > > > +               if (desc_status) {
> > > > +                       xe_gt_err(gt, "CT write: non-zero
> > > > status: %u\n", desc_status);
> > > > +                       goto corrupted;
> > > > +               }
> > > >  
> > > >                 if (tail != desc_tail) {
> > > >                         desc_write(xe, h2g, status, desc_status
> > > > | GUC_CTB_STATUS_MISMATCH);
> > > > -- 
> > > > 2.34.1
> > > > 

Re: [PATCH v2 2/2] drm/xe: Remove H2G reads in CT send path in non-debug builds

[Matthew Brost]

On Tue, Feb 17, 2026 at 05:24:07PM -0700, Summers, Stuart wrote:
> On Tue, 2026-02-17 at 12:19 +0100, Francois Dugast wrote:
> > On Mon, Feb 16, 2026 at 09:40:19AM -0800, Matthew Brost wrote:
> > > On Mon, Feb 16, 2026 at 01:51:57PM +0100, Francois Dugast wrote:
> > > > mOn Fri, Feb 13, 2026 at 01:16:25PM -0800, Matthew Brost wrote:
> > > > > A single VRAM read on BMG can take over 1µs. While small, this
> > > > > is a
> > > > > non-trivial amount of time in a hot path. Remove the descriptor
> > > > > H2G read
> > > > > (potentially a VRAM access) from non-debug builds, as this
> > > > > error-checking code is not needed outside of debug
> > > > > configurations.
> > > > 
> > > > About the change itself: I understand the performance benefit and
> > > > this would
> > > > make the code consistent with the 2 other reads.
> > > > 
> > > 
> > > Yes.
> > > 
> > > > But the existing block under "if
> > > > (IS_ENABLED(CONFIG_DRM_XE_DEBUG))" seems wrong
> > > > because it is not just about optionally printing some debug
> > > > statements, in case
> > > > of error the function actually returns a different value if
> > > > CONFIG_DRM_XE_DEBUG
> > > > is enabled or not (goto), and this return value is used in
> > > > __guc_ct_send_locked.
> > > > 
> > > 
> > > I can't realy argue with this logic but I also see the benefits of
> > > verbose checking of GuC state in CI configs. fwiw, this logic was
> > > added
> > > here:
> > > 
> > > git format-patch -1 d2c5a5a926f43
> > > 
> > > The cost of reads are actually huge here - this patch by itself is
> > > incomplete as a tracepoint below does a desc_read in the argument
> > > list
> > > and this is uncoditionally executed even if ftrace is disabled. On
> > > BMG H2G
> > > before this patch / fixing ftrace are 3-4us, after ~300ns. So I'd
> > > suggest we move forward with with a couple of fixes patches first,
> > > then
> > > in a follow up either:
> > > 
> > > The cost of reads is actually huge here — this patch by itself is
> > > incomplete, as a tracepoint below performs a desc_read in the
> > > argument
> > > list, and that is unconditionally executed even if ftrace is
> > > disabled.
> > > On BMG, H2G reads before this patch / fixing ftrace are 3–4-µs;
> > > after,
> > > they’re ~300ns. So I’d suggest we move forward with a couple of
> > > fixes
> > > patches first, and then in a follow-up:
> > > 
> > > - Move all really expensive things in GuC CT layer under
> > >   CONFIG_DRM_XE_DEBUG_GUC, enable this Kconfig some CI run
> > > - Perhaps just assert if GuC state is corrupted in the path
> > > mentioned
> > >   above
> 
> So is the suggestion here to enable this DEBUG_GUC parameter for all
> CI? We do rely on these error messages for baseline debug and sometimes
> things coming out of CI (or even a customer) are hard to reproduce. I'm

Customers would never turn this (CONFIG_DRM_XE_DEBUG) on unless we
explicitly ask them to rebuild their kernel and reproduce an issue.

> a little worried removing this will drag out debug for these types of
> problems.

I think we should basically leave this as is for now and focus on
getting the non-debug paths performing optimally in the smallest patch
we can. I’m planning for my next rev (which also fixes the tracepoint)
to be a fixes patch, since that alone gives a 10× speedup in H2G on BMG.
This starts to show up throughout the driver as performance improvements
(e.g., I’m seeing TLB invalidations get faster) because it reduces
contention on the CT locks.

We can debate DEBUG vs. DEBUG_GUC in a follow up, along with any
intended behavior changes tied to the debug knobs. FWIW, I really doubt
this has ever caught anything — this type of failure would be a
catastrophic GuC bug and would surface quickly in other ways.

Matt

> 
> -Stuart
> 
> > 
> > Sounds good.
> > 
> > > 
> > > Matt
> > > 
> > > > Francois
> > > > 
> > > > > 
> > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/xe/xe_guc_ct.c | 14 +++++++-------
> > > > >  1 file changed, 7 insertions(+), 7 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > > b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > > index 6a96bea40720..f200d3ee9d22 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> > > > > @@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct
> > > > > *ct, const u32 *action, u32 len,
> > > > >         u32 full_len;
> > > > >         struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g-
> > > > > >cmds,
> > > > >                                                          tail *
> > > > > sizeof(u32));
> > > > > -       u32 desc_status;
> > > > >  
> > > > >         full_len = len + GUC_CTB_HDR_LEN;
> > > > >  
> > > > >         lockdep_assert_held(&ct->lock);
> > > > >         xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
> > > > >  
> > > > > -       desc_status = desc_read(xe, h2g, status);
> > > > > -       if (desc_status) {
> > > > > -               xe_gt_err(gt, "CT write: non-zero status:
> > > > > %u\n", desc_status);
> > > > > -               goto corrupted;
> > > > > -       }
> > > > > -
> > > > >         if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
> > > > >                 u32 desc_tail = desc_read(xe, h2g, tail);
> > > > >                 u32 desc_head = desc_read(xe, h2g, head);
> > > > > +               u32 desc_status;
> > > > > +
> > > > > +               desc_status = desc_read(xe, h2g, status);
> > > > > +               if (desc_status) {
> > > > > +                       xe_gt_err(gt, "CT write: non-zero
> > > > > status: %u\n", desc_status);
> > > > > +                       goto corrupted;
> > > > > +               }
> > > > >  
> > > > >                 if (tail != desc_tail) {
> > > > >                         desc_write(xe, h2g, status, desc_status
> > > > > | GUC_CTB_STATUS_MISMATCH);
> > > > > -- 
> > > > > 2.34.1
> > > > > 
> 

✓ CI.KUnit: success for GuC CT memory optimizations

[Patchwork]

== Series Details ==

Series: GuC CT memory optimizations
URL   : https://patchwork.freedesktop.org/series/161604/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:58:34] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:58:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:59:10] Starting KUnit Kernel (1/1)...
[21:59:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:59:10] ================== guc_buf (11 subtests) ===================
[21:59:10] [PASSED] test_smallest
[21:59:10] [PASSED] test_largest
[21:59:10] [PASSED] test_granular
[21:59:10] [PASSED] test_unique
[21:59:10] [PASSED] test_overlap
[21:59:10] [PASSED] test_reusable
[21:59:10] [PASSED] test_too_big
[21:59:10] [PASSED] test_flush
[21:59:10] [PASSED] test_lookup
[21:59:10] [PASSED] test_data
[21:59:10] [PASSED] test_class
[21:59:10] ===================== [PASSED] guc_buf =====================
[21:59:10] =================== guc_dbm (7 subtests) ===================
[21:59:10] [PASSED] test_empty
[21:59:10] [PASSED] test_default
[21:59:10] ======================== test_size  ========================
[21:59:10] [PASSED] 4
[21:59:10] [PASSED] 8
[21:59:10] [PASSED] 32
[21:59:10] [PASSED] 256
[21:59:10] ==================== [PASSED] test_size ====================
[21:59:10] ======================= test_reuse  ========================
[21:59:10] [PASSED] 4
[21:59:10] [PASSED] 8
[21:59:10] [PASSED] 32
[21:59:10] [PASSED] 256
[21:59:10] =================== [PASSED] test_reuse ====================
[21:59:10] =================== test_range_overlap  ====================
[21:59:10] [PASSED] 4
[21:59:10] [PASSED] 8
[21:59:10] [PASSED] 32
[21:59:10] [PASSED] 256
[21:59:10] =============== [PASSED] test_range_overlap ================
[21:59:10] =================== test_range_compact  ====================
[21:59:10] [PASSED] 4
[21:59:10] [PASSED] 8
[21:59:10] [PASSED] 32
[21:59:10] [PASSED] 256
[21:59:10] =============== [PASSED] test_range_compact ================
[21:59:10] ==================== test_range_spare  =====================
[21:59:10] [PASSED] 4
[21:59:10] [PASSED] 8
[21:59:10] [PASSED] 32
[21:59:10] [PASSED] 256
[21:59:10] ================ [PASSED] test_range_spare =================
[21:59:10] ===================== [PASSED] guc_dbm =====================
[21:59:10] =================== guc_idm (6 subtests) ===================
[21:59:10] [PASSED] bad_init
[21:59:10] [PASSED] no_init
[21:59:10] [PASSED] init_fini
[21:59:10] [PASSED] check_used
[21:59:10] [PASSED] check_quota
[21:59:10] [PASSED] check_all
[21:59:10] ===================== [PASSED] guc_idm =====================
[21:59:10] ================== no_relay (3 subtests) ===================
[21:59:10] [PASSED] xe_drops_guc2pf_if_not_ready
[21:59:10] [PASSED] xe_drops_guc2vf_if_not_ready
[21:59:10] [PASSED] xe_rejects_send_if_not_ready
[21:59:10] ==================== [PASSED] no_relay =====================
[21:59:10] ================== pf_relay (14 subtests) ==================
[21:59:10] [PASSED] pf_rejects_guc2pf_too_short
[21:59:10] [PASSED] pf_rejects_guc2pf_too_long
[21:59:10] [PASSED] pf_rejects_guc2pf_no_payload
[21:59:10] [PASSED] pf_fails_no_payload
[21:59:10] [PASSED] pf_fails_bad_origin
[21:59:10] [PASSED] pf_fails_bad_type
[21:59:10] [PASSED] pf_txn_reports_error
[21:59:10] [PASSED] pf_txn_sends_pf2guc
[21:59:10] [PASSED] pf_sends_pf2guc
[21:59:10] [SKIPPED] pf_loopback_nop
[21:59:10] [SKIPPED] pf_loopback_echo
[21:59:10] [SKIPPED] pf_loopback_fail
[21:59:10] [SKIPPED] pf_loopback_busy
[21:59:10] [SKIPPED] pf_loopback_retry
[21:59:10] ==================== [PASSED] pf_relay =====================
[21:59:10] ================== vf_relay (3 subtests) ===================
[21:59:10] [PASSED] vf_rejects_guc2vf_too_short
[21:59:10] [PASSED] vf_rejects_guc2vf_too_long
[21:59:10] [PASSED] vf_rejects_guc2vf_no_payload
[21:59:10] ==================== [PASSED] vf_relay =====================
[21:59:10] ================ pf_gt_config (6 subtests) =================
[21:59:10] [PASSED] fair_contexts_1vf
[21:59:10] [PASSED] fair_doorbells_1vf
[21:59:10] [PASSED] fair_ggtt_1vf
[21:59:10] ====================== fair_contexts  ======================
[21:59:10] [PASSED] 1 VF
[21:59:10] [PASSED] 2 VFs
[21:59:10] [PASSED] 3 VFs
[21:59:10] [PASSED] 4 VFs
[21:59:10] [PASSED] 5 VFs
[21:59:10] [PASSED] 6 VFs
[21:59:10] [PASSED] 7 VFs
[21:59:10] [PASSED] 8 VFs
[21:59:10] [PASSED] 9 VFs
[21:59:10] [PASSED] 10 VFs
[21:59:10] [PASSED] 11 VFs
[21:59:10] [PASSED] 12 VFs
[21:59:10] [PASSED] 13 VFs
[21:59:10] [PASSED] 14 VFs
[21:59:10] [PASSED] 15 VFs
[21:59:10] [PASSED] 16 VFs
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[21:59:10] [PASSED] 18 VFs
[21:59:10] [PASSED] 19 VFs
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[21:59:10] [PASSED] 22 VFs
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[21:59:10] [PASSED] 24 VFs
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[21:59:10] [PASSED] 27 VFs
[21:59:10] [PASSED] 28 VFs
[21:59:10] [PASSED] 29 VFs
[21:59:10] [PASSED] 30 VFs
[21:59:10] [PASSED] 31 VFs
[21:59:10] [PASSED] 32 VFs
[21:59:10] [PASSED] 33 VFs
[21:59:10] [PASSED] 34 VFs
[21:59:10] [PASSED] 35 VFs
[21:59:10] [PASSED] 36 VFs
[21:59:10] [PASSED] 37 VFs
[21:59:10] [PASSED] 38 VFs
[21:59:10] [PASSED] 39 VFs
[21:59:10] [PASSED] 40 VFs
[21:59:10] [PASSED] 41 VFs
[21:59:10] [PASSED] 42 VFs
[21:59:10] [PASSED] 43 VFs
[21:59:10] [PASSED] 44 VFs
[21:59:10] [PASSED] 45 VFs
[21:59:10] [PASSED] 46 VFs
[21:59:10] [PASSED] 47 VFs
[21:59:10] [PASSED] 48 VFs
[21:59:10] [PASSED] 49 VFs
[21:59:10] [PASSED] 50 VFs
[21:59:10] [PASSED] 51 VFs
[21:59:10] [PASSED] 52 VFs
[21:59:10] [PASSED] 53 VFs
[21:59:10] [PASSED] 54 VFs
[21:59:10] [PASSED] 55 VFs
[21:59:10] [PASSED] 56 VFs
[21:59:10] [PASSED] 57 VFs
[21:59:10] [PASSED] 58 VFs
[21:59:10] [PASSED] 59 VFs
[21:59:10] [PASSED] 60 VFs
[21:59:10] [PASSED] 61 VFs
[21:59:10] [PASSED] 62 VFs
[21:59:10] [PASSED] 63 VFs
[21:59:10] ================== [PASSED] fair_contexts ==================
[21:59:10] ===================== fair_doorbells  ======================
[21:59:10] [PASSED] 1 VF
[21:59:10] [PASSED] 2 VFs
[21:59:10] [PASSED] 3 VFs
[21:59:10] [PASSED] 4 VFs
[21:59:10] [PASSED] 5 VFs
[21:59:10] [PASSED] 6 VFs
[21:59:10] [PASSED] 7 VFs
[21:59:10] [PASSED] 8 VFs
[21:59:10] [PASSED] 9 VFs
[21:59:10] [PASSED] 10 VFs
[21:59:10] [PASSED] 11 VFs
[21:59:10] [PASSED] 12 VFs
[21:59:10] [PASSED] 13 VFs
[21:59:10] [PASSED] 14 VFs
[21:59:10] [PASSED] 15 VFs
[21:59:10] [PASSED] 16 VFs
[21:59:10] [PASSED] 17 VFs
[21:59:10] [PASSED] 18 VFs
[21:59:10] [PASSED] 19 VFs
[21:59:10] [PASSED] 20 VFs
[21:59:10] [PASSED] 21 VFs
[21:59:10] [PASSED] 22 VFs
[21:59:10] [PASSED] 23 VFs
[21:59:10] [PASSED] 24 VFs
[21:59:10] [PASSED] 25 VFs
[21:59:10] [PASSED] 26 VFs
[21:59:10] [PASSED] 27 VFs
[21:59:10] [PASSED] 28 VFs
[21:59:10] [PASSED] 29 VFs
[21:59:10] [PASSED] 30 VFs
[21:59:10] [PASSED] 31 VFs
[21:59:10] [PASSED] 32 VFs
[21:59:10] [PASSED] 33 VFs
[21:59:10] [PASSED] 34 VFs
[21:59:10] [PASSED] 35 VFs
[21:59:10] [PASSED] 36 VFs
[21:59:10] [PASSED] 37 VFs
[21:59:10] [PASSED] 38 VFs
[21:59:10] [PASSED] 39 VFs
[21:59:10] [PASSED] 40 VFs
[21:59:10] [PASSED] 41 VFs
[21:59:10] [PASSED] 42 VFs
[21:59:10] [PASSED] 43 VFs
[21:59:11] [PASSED] 44 VFs
[21:59:11] [PASSED] 45 VFs
[21:59:11] [PASSED] 46 VFs
[21:59:11] [PASSED] 47 VFs
[21:59:11] [PASSED] 48 VFs
[21:59:11] [PASSED] 49 VFs
[21:59:11] [PASSED] 50 VFs
[21:59:11] [PASSED] 51 VFs
[21:59:11] [PASSED] 52 VFs
[21:59:11] [PASSED] 53 VFs
[21:59:11] [PASSED] 54 VFs
[21:59:11] [PASSED] 55 VFs
[21:59:11] [PASSED] 56 VFs
[21:59:11] [PASSED] 57 VFs
[21:59:11] [PASSED] 58 VFs
[21:59:11] [PASSED] 59 VFs
[21:59:11] [PASSED] 60 VFs
[21:59:11] [PASSED] 61 VFs
[21:59:11] [PASSED] 62 VFs
[21:59:11] [PASSED] 63 VFs
[21:59:11] ================= [PASSED] fair_doorbells ==================
[21:59:11] ======================== fair_ggtt  ========================
[21:59:11] [PASSED] 1 VF
[21:59:11] [PASSED] 2 VFs
[21:59:11] [PASSED] 3 VFs
[21:59:11] [PASSED] 4 VFs
[21:59:11] [PASSED] 5 VFs
[21:59:11] [PASSED] 6 VFs
[21:59:11] [PASSED] 7 VFs
[21:59:11] [PASSED] 8 VFs
[21:59:11] [PASSED] 9 VFs
[21:59:11] [PASSED] 10 VFs
[21:59:11] [PASSED] 11 VFs
[21:59:11] [PASSED] 12 VFs
[21:59:11] [PASSED] 13 VFs
[21:59:11] [PASSED] 14 VFs
[21:59:11] [PASSED] 15 VFs
[21:59:11] [PASSED] 16 VFs
[21:59:11] [PASSED] 17 VFs
[21:59:11] [PASSED] 18 VFs
[21:59:11] [PASSED] 19 VFs
[21:59:11] [PASSED] 20 VFs
[21:59:11] [PASSED] 21 VFs
[21:59:11] [PASSED] 22 VFs
[21:59:11] [PASSED] 23 VFs
[21:59:11] [PASSED] 24 VFs
[21:59:11] [PASSED] 25 VFs
[21:59:11] [PASSED] 26 VFs
[21:59:11] [PASSED] 27 VFs
[21:59:11] [PASSED] 28 VFs
[21:59:11] [PASSED] 29 VFs
[21:59:11] [PASSED] 30 VFs
[21:59:11] [PASSED] 31 VFs
[21:59:11] [PASSED] 32 VFs
[21:59:11] [PASSED] 33 VFs
[21:59:11] [PASSED] 34 VFs
[21:59:11] [PASSED] 35 VFs
[21:59:11] [PASSED] 36 VFs
[21:59:11] [PASSED] 37 VFs
[21:59:11] [PASSED] 38 VFs
[21:59:11] [PASSED] 39 VFs
[21:59:11] [PASSED] 40 VFs
[21:59:11] [PASSED] 41 VFs
[21:59:11] [PASSED] 42 VFs
[21:59:11] [PASSED] 43 VFs
[21:59:11] [PASSED] 44 VFs
[21:59:11] [PASSED] 45 VFs
[21:59:11] [PASSED] 46 VFs
[21:59:11] [PASSED] 47 VFs
[21:59:11] [PASSED] 48 VFs
[21:59:11] [PASSED] 49 VFs
[21:59:11] [PASSED] 50 VFs
[21:59:11] [PASSED] 51 VFs
[21:59:11] [PASSED] 52 VFs
[21:59:11] [PASSED] 53 VFs
[21:59:11] [PASSED] 54 VFs
[21:59:11] [PASSED] 55 VFs
[21:59:11] [PASSED] 56 VFs
[21:59:11] [PASSED] 57 VFs
[21:59:11] [PASSED] 58 VFs
[21:59:11] [PASSED] 59 VFs
[21:59:11] [PASSED] 60 VFs
[21:59:11] [PASSED] 61 VFs
[21:59:11] [PASSED] 62 VFs
[21:59:11] [PASSED] 63 VFs
[21:59:11] ==================== [PASSED] fair_ggtt ====================
[21:59:11] ================== [PASSED] pf_gt_config ===================
[21:59:11] ===================== lmtt (1 subtest) =====================
[21:59:11] ======================== test_ops  =========================
[21:59:11] [PASSED] 2-level
[21:59:11] [PASSED] multi-level
[21:59:11] ==================== [PASSED] test_ops =====================
[21:59:11] ====================== [PASSED] lmtt =======================
[21:59:11] ================= pf_service (11 subtests) =================
[21:59:11] [PASSED] pf_negotiate_any
[21:59:11] [PASSED] pf_negotiate_base_match
[21:59:11] [PASSED] pf_negotiate_base_newer
[21:59:11] [PASSED] pf_negotiate_base_next
[21:59:11] [SKIPPED] pf_negotiate_base_older
[21:59:11] [PASSED] pf_negotiate_base_prev
[21:59:11] [PASSED] pf_negotiate_latest_match
[21:59:11] [PASSED] pf_negotiate_latest_newer
[21:59:11] [PASSED] pf_negotiate_latest_next
[21:59:11] [SKIPPED] pf_negotiate_latest_older
[21:59:11] [SKIPPED] pf_negotiate_latest_prev
[21:59:11] =================== [PASSED] pf_service ====================
[21:59:11] ================= xe_guc_g2g (2 subtests) ==================
[21:59:11] ============== xe_live_guc_g2g_kunit_default  ==============
[21:59:11] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:59:11] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:59:11] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:59:11] =================== [SKIPPED] xe_guc_g2g ===================
[21:59:11] =================== xe_mocs (2 subtests) ===================
[21:59:11] ================ xe_live_mocs_kernel_kunit  ================
[21:59:11] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:59:11] ================ xe_live_mocs_reset_kunit  =================
[21:59:11] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:59:11] ==================== [SKIPPED] xe_mocs =====================
[21:59:11] ================= xe_migrate (2 subtests) ==================
[21:59:11] ================= xe_migrate_sanity_kunit  =================
[21:59:11] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:59:11] ================== xe_validate_ccs_kunit  ==================
[21:59:11] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:59:11] =================== [SKIPPED] xe_migrate ===================
[21:59:11] ================== xe_dma_buf (1 subtest) ==================
[21:59:11] ==================== xe_dma_buf_kunit  =====================
[21:59:11] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:59:11] =================== [SKIPPED] xe_dma_buf ===================
[21:59:11] ================= xe_bo_shrink (1 subtest) =================
[21:59:11] =================== xe_bo_shrink_kunit  ====================
[21:59:11] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:59:11] ================== [SKIPPED] xe_bo_shrink ==================
[21:59:11] ==================== xe_bo (2 subtests) ====================
[21:59:11] ================== xe_ccs_migrate_kunit  ===================
[21:59:11] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:59:11] ==================== xe_bo_evict_kunit  ====================
[21:59:11] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:59:11] ===================== [SKIPPED] xe_bo ======================
[21:59:11] ==================== args (13 subtests) ====================
[21:59:11] [PASSED] count_args_test
[21:59:11] [PASSED] call_args_example
[21:59:11] [PASSED] call_args_test
[21:59:11] [PASSED] drop_first_arg_example
[21:59:11] [PASSED] drop_first_arg_test
[21:59:11] [PASSED] first_arg_example
[21:59:11] [PASSED] first_arg_test
[21:59:11] [PASSED] last_arg_example
[21:59:11] [PASSED] last_arg_test
[21:59:11] [PASSED] pick_arg_example
[21:59:11] [PASSED] if_args_example
[21:59:11] [PASSED] if_args_test
[21:59:11] [PASSED] sep_comma_example
[21:59:11] ====================== [PASSED] args =======================
[21:59:11] =================== xe_pci (3 subtests) ====================
[21:59:11] ==================== check_graphics_ip  ====================
[21:59:11] [PASSED] 12.00 Xe_LP
[21:59:11] [PASSED] 12.10 Xe_LP+
[21:59:11] [PASSED] 12.55 Xe_HPG
[21:59:11] [PASSED] 12.60 Xe_HPC
[21:59:11] [PASSED] 12.70 Xe_LPG
[21:59:11] [PASSED] 12.71 Xe_LPG
[21:59:11] [PASSED] 12.74 Xe_LPG+
[21:59:11] [PASSED] 20.01 Xe2_HPG
[21:59:11] [PASSED] 20.02 Xe2_HPG
[21:59:11] [PASSED] 20.04 Xe2_LPG
[21:59:11] [PASSED] 30.00 Xe3_LPG
[21:59:11] [PASSED] 30.01 Xe3_LPG
[21:59:11] [PASSED] 30.03 Xe3_LPG
[21:59:11] [PASSED] 30.04 Xe3_LPG
[21:59:11] [PASSED] 30.05 Xe3_LPG
[21:59:11] [PASSED] 35.10 Xe3p_LPG
[21:59:11] [PASSED] 35.11 Xe3p_XPC
[21:59:11] ================ [PASSED] check_graphics_ip ================
[21:59:11] ===================== check_media_ip  ======================
[21:59:11] [PASSED] 12.00 Xe_M
[21:59:11] [PASSED] 12.55 Xe_HPM
[21:59:11] [PASSED] 13.00 Xe_LPM+
[21:59:11] [PASSED] 13.01 Xe2_HPM
[21:59:11] [PASSED] 20.00 Xe2_LPM
[21:59:11] [PASSED] 30.00 Xe3_LPM
[21:59:11] [PASSED] 30.02 Xe3_LPM
[21:59:11] [PASSED] 35.00 Xe3p_LPM
[21:59:11] [PASSED] 35.03 Xe3p_HPM
[21:59:11] ================= [PASSED] check_media_ip ==================
[21:59:11] =================== check_platform_desc  ===================
[21:59:11] [PASSED] 0x9A60 (TIGERLAKE)
[21:59:11] [PASSED] 0x9A68 (TIGERLAKE)
[21:59:11] [PASSED] 0x9A70 (TIGERLAKE)
[21:59:11] [PASSED] 0x9A40 (TIGERLAKE)
[21:59:11] [PASSED] 0x9A49 (TIGERLAKE)
[21:59:11] [PASSED] 0x9A59 (TIGERLAKE)
[21:59:11] [PASSED] 0x9A78 (TIGERLAKE)
[21:59:11] [PASSED] 0x9AC0 (TIGERLAKE)
[21:59:11] [PASSED] 0x9AC9 (TIGERLAKE)
[21:59:11] [PASSED] 0x9AD9 (TIGERLAKE)
[21:59:11] [PASSED] 0x9AF8 (TIGERLAKE)
[21:59:11] [PASSED] 0x4C80 (ROCKETLAKE)
[21:59:11] [PASSED] 0x4C8A (ROCKETLAKE)
[21:59:11] [PASSED] 0x4C8B (ROCKETLAKE)
[21:59:11] [PASSED] 0x4C8C (ROCKETLAKE)
[21:59:11] [PASSED] 0x4C90 (ROCKETLAKE)
[21:59:11] [PASSED] 0x4C9A (ROCKETLAKE)
[21:59:11] [PASSED] 0x4680 (ALDERLAKE_S)
[21:59:11] [PASSED] 0x4682 (ALDERLAKE_S)
[21:59:11] [PASSED] 0x4688 (ALDERLAKE_S)
[21:59:11] [PASSED] 0x468A (ALDERLAKE_S)
[21:59:11] [PASSED] 0x468B (ALDERLAKE_S)
[21:59:11] [PASSED] 0x4690 (ALDERLAKE_S)
[21:59:11] [PASSED] 0x4692 (ALDERLAKE_S)
[21:59:11] [PASSED] 0x4693 (ALDERLAKE_S)
[21:59:11] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46AA (ALDERLAKE_P)
[21:59:11] [PASSED] 0x462A (ALDERLAKE_P)
[21:59:11] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[21:59:11] [PASSED] 0x4628 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:59:11] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:59:11] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:59:11] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:59:11] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:59:11] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:59:11] [PASSED] 0xA721 (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA720 (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:59:11] [PASSED] 0xA780 (ALDERLAKE_S)
[21:59:11] [PASSED] 0xA781 (ALDERLAKE_S)
[21:59:11] [PASSED] 0xA782 (ALDERLAKE_S)
[21:59:11] [PASSED] 0xA783 (ALDERLAKE_S)
[21:59:11] [PASSED] 0xA788 (ALDERLAKE_S)
[21:59:11] [PASSED] 0xA789 (ALDERLAKE_S)
[21:59:11] [PASSED] 0xA78A (ALDERLAKE_S)
[21:59:11] [PASSED] 0xA78B (ALDERLAKE_S)
[21:59:11] [PASSED] 0x4905 (DG1)
[21:59:11] [PASSED] 0x4906 (DG1)
[21:59:11] [PASSED] 0x4907 (DG1)
[21:59:11] [PASSED] 0x4908 (DG1)
[21:59:11] [PASSED] 0x4909 (DG1)
[21:59:11] [PASSED] 0x56C0 (DG2)
[21:59:11] [PASSED] 0x56C2 (DG2)
[21:59:11] [PASSED] 0x56C1 (DG2)
[21:59:11] [PASSED] 0x7D51 (METEORLAKE)
[21:59:11] [PASSED] 0x7DD1 (METEORLAKE)
[21:59:11] [PASSED] 0x7D41 (METEORLAKE)
[21:59:11] [PASSED] 0x7D67 (METEORLAKE)
[21:59:11] [PASSED] 0xB640 (METEORLAKE)
[21:59:11] [PASSED] 0x56A0 (DG2)
[21:59:11] [PASSED] 0x56A1 (DG2)
[21:59:11] [PASSED] 0x56A2 (DG2)
[21:59:11] [PASSED] 0x56BE (DG2)
[21:59:11] [PASSED] 0x56BF (DG2)
[21:59:11] [PASSED] 0x5690 (DG2)
[21:59:11] [PASSED] 0x5691 (DG2)
[21:59:11] [PASSED] 0x5692 (DG2)
[21:59:11] [PASSED] 0x56A5 (DG2)
[21:59:11] [PASSED] 0x56A6 (DG2)
[21:59:11] [PASSED] 0x56B0 (DG2)
[21:59:11] [PASSED] 0x56B1 (DG2)
[21:59:11] [PASSED] 0x56BA (DG2)
[21:59:11] [PASSED] 0x56BB (DG2)
[21:59:11] [PASSED] 0x56BC (DG2)
[21:59:11] [PASSED] 0x56BD (DG2)
[21:59:11] [PASSED] 0x5693 (DG2)
[21:59:11] [PASSED] 0x5694 (DG2)
[21:59:11] [PASSED] 0x5695 (DG2)
[21:59:11] [PASSED] 0x56A3 (DG2)
[21:59:11] [PASSED] 0x56A4 (DG2)
[21:59:11] [PASSED] 0x56B2 (DG2)
[21:59:11] [PASSED] 0x56B3 (DG2)
[21:59:11] [PASSED] 0x5696 (DG2)
[21:59:11] [PASSED] 0x5697 (DG2)
[21:59:11] [PASSED] 0xB69 (PVC)
[21:59:11] [PASSED] 0xB6E (PVC)
[21:59:11] [PASSED] 0xBD4 (PVC)
[21:59:11] [PASSED] 0xBD5 (PVC)
[21:59:11] [PASSED] 0xBD6 (PVC)
[21:59:11] [PASSED] 0xBD7 (PVC)
[21:59:11] [PASSED] 0xBD8 (PVC)
[21:59:11] [PASSED] 0xBD9 (PVC)
[21:59:11] [PASSED] 0xBDA (PVC)
[21:59:11] [PASSED] 0xBDB (PVC)
[21:59:11] [PASSED] 0xBE0 (PVC)
[21:59:11] [PASSED] 0xBE1 (PVC)
[21:59:11] [PASSED] 0xBE5 (PVC)
[21:59:11] [PASSED] 0x7D40 (METEORLAKE)
[21:59:11] [PASSED] 0x7D45 (METEORLAKE)
[21:59:11] [PASSED] 0x7D55 (METEORLAKE)
[21:59:11] [PASSED] 0x7D60 (METEORLAKE)
[21:59:11] [PASSED] 0x7DD5 (METEORLAKE)
[21:59:11] [PASSED] 0x6420 (LUNARLAKE)
[21:59:11] [PASSED] 0x64A0 (LUNARLAKE)
[21:59:11] [PASSED] 0x64B0 (LUNARLAKE)
[21:59:11] [PASSED] 0xE202 (BATTLEMAGE)
[21:59:11] [PASSED] 0xE209 (BATTLEMAGE)
[21:59:11] [PASSED] 0xE20B (BATTLEMAGE)
[21:59:11] [PASSED] 0xE20C (BATTLEMAGE)
[21:59:11] [PASSED] 0xE20D (BATTLEMAGE)
[21:59:11] [PASSED] 0xE210 (BATTLEMAGE)
[21:59:11] [PASSED] 0xE211 (BATTLEMAGE)
[21:59:11] [PASSED] 0xE212 (BATTLEMAGE)
[21:59:11] [PASSED] 0xE216 (BATTLEMAGE)
[21:59:11] [PASSED] 0xE220 (BATTLEMAGE)
[21:59:11] [PASSED] 0xE221 (BATTLEMAGE)
[21:59:11] [PASSED] 0xE222 (BATTLEMAGE)
[21:59:11] [PASSED] 0xE223 (BATTLEMAGE)
[21:59:11] [PASSED] 0xB080 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB081 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB082 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB083 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB084 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB085 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB086 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB087 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB08F (PANTHERLAKE)
[21:59:11] [PASSED] 0xB090 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:59:11] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:59:11] [PASSED] 0xFD80 (PANTHERLAKE)
[21:59:11] [PASSED] 0xFD81 (PANTHERLAKE)
[21:59:11] [PASSED] 0xD740 (NOVALAKE_S)
[21:59:11] [PASSED] 0xD741 (NOVALAKE_S)
[21:59:11] [PASSED] 0xD742 (NOVALAKE_S)
[21:59:11] [PASSED] 0xD743 (NOVALAKE_S)
[21:59:11] [PASSED] 0xD744 (NOVALAKE_S)
[21:59:11] [PASSED] 0xD745 (NOVALAKE_S)
[21:59:11] [PASSED] 0x674C (CRESCENTISLAND)
[21:59:11] [PASSED] 0xD750 (NOVALAKE_P)
[21:59:11] [PASSED] 0xD751 (NOVALAKE_P)
[21:59:11] [PASSED] 0xD752 (NOVALAKE_P)
[21:59:11] [PASSED] 0xD753 (NOVALAKE_P)
[21:59:11] [PASSED] 0xD754 (NOVALAKE_P)
[21:59:11] [PASSED] 0xD755 (NOVALAKE_P)
[21:59:11] [PASSED] 0xD756 (NOVALAKE_P)
[21:59:11] [PASSED] 0xD757 (NOVALAKE_P)
[21:59:11] [PASSED] 0xD75F (NOVALAKE_P)
[21:59:11] =============== [PASSED] check_platform_desc ===============
[21:59:11] ===================== [PASSED] xe_pci ======================
[21:59:11] =================== xe_rtp (2 subtests) ====================
[21:59:11] =============== xe_rtp_process_to_sr_tests  ================
[21:59:11] [PASSED] coalesce-same-reg
[21:59:11] [PASSED] no-match-no-add
[21:59:11] [PASSED] match-or
[21:59:11] [PASSED] match-or-xfail
[21:59:11] [PASSED] no-match-no-add-multiple-rules
[21:59:11] [PASSED] two-regs-two-entries
[21:59:11] [PASSED] clr-one-set-other
[21:59:11] [PASSED] set-field
[21:59:11] [PASSED] conflict-duplicate
[21:59:11] [PASSED] conflict-not-disjoint
[21:59:11] [PASSED] conflict-reg-type
[21:59:11] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:59:11] ================== xe_rtp_process_tests  ===================
[21:59:11] [PASSED] active1
[21:59:11] [PASSED] active2
[21:59:11] [PASSED] active-inactive
[21:59:11] [PASSED] inactive-active
[21:59:11] [PASSED] inactive-1st_or_active-inactive
[21:59:11] [PASSED] inactive-2nd_or_active-inactive
[21:59:11] [PASSED] inactive-last_or_active-inactive
[21:59:11] [PASSED] inactive-no_or_active-inactive
[21:59:11] ============== [PASSED] xe_rtp_process_tests ===============
[21:59:11] ===================== [PASSED] xe_rtp ======================
[21:59:11] ==================== xe_wa (1 subtest) =====================
[21:59:11] ======================== xe_wa_gt  =========================
[21:59:11] [PASSED] TIGERLAKE B0
[21:59:11] [PASSED] DG1 A0
[21:59:11] [PASSED] DG1 B0
[21:59:11] [PASSED] ALDERLAKE_S A0
[21:59:11] [PASSED] ALDERLAKE_S B0
[21:59:11] [PASSED] ALDERLAKE_S C0
[21:59:11] [PASSED] ALDERLAKE_S D0
[21:59:11] [PASSED] ALDERLAKE_P A0
[21:59:11] [PASSED] ALDERLAKE_P B0
[21:59:11] [PASSED] ALDERLAKE_P C0
[21:59:11] [PASSED] ALDERLAKE_S RPLS D0
[21:59:11] [PASSED] ALDERLAKE_P RPLU E0
[21:59:11] [PASSED] DG2 G10 C0
[21:59:11] [PASSED] DG2 G11 B1
[21:59:11] [PASSED] DG2 G12 A1
[21:59:11] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:59:11] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:59:11] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:59:11] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:59:11] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:59:11] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:59:11] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:59:11] ==================== [PASSED] xe_wa_gt =====================
[21:59:11] ====================== [PASSED] xe_wa ======================
[21:59:11] ============================================================
[21:59:11] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[21:59:11] Elapsed time: 36.424s total, 4.206s configuring, 31.701s building, 0.476s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:59:11] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:59:12] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:59:38] Starting KUnit Kernel (1/1)...
[21:59:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:59:38] ============ drm_test_pick_cmdline (2 subtests) ============
[21:59:38] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:59:38] =============== drm_test_pick_cmdline_named  ===============
[21:59:38] [PASSED] NTSC
[21:59:38] [PASSED] NTSC-J
[21:59:38] [PASSED] PAL
[21:59:38] [PASSED] PAL-M
[21:59:38] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:59:38] ============== [PASSED] drm_test_pick_cmdline ==============
[21:59:38] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:59:38] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:59:38] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:59:38] =========== drm_validate_clone_mode (2 subtests) ===========
[21:59:38] ============== drm_test_check_in_clone_mode  ===============
[21:59:38] [PASSED] in_clone_mode
[21:59:38] [PASSED] not_in_clone_mode
[21:59:38] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:59:38] =============== drm_test_check_valid_clones  ===============
[21:59:38] [PASSED] not_in_clone_mode
[21:59:38] [PASSED] valid_clone
[21:59:38] [PASSED] invalid_clone
[21:59:38] =========== [PASSED] drm_test_check_valid_clones ===========
[21:59:38] ============= [PASSED] drm_validate_clone_mode =============
[21:59:38] ============= drm_validate_modeset (1 subtest) =============
[21:59:38] [PASSED] drm_test_check_connector_changed_modeset
[21:59:38] ============== [PASSED] drm_validate_modeset ===============
[21:59:38] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:59:38] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:59:38] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:59:38] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:59:38] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:59:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:59:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:59:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:59:38] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:59:38] ============== drm_bridge_alloc (2 subtests) ===============
[21:59:38] [PASSED] drm_test_drm_bridge_alloc_basic
[21:59:38] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:59:38] ================ [PASSED] drm_bridge_alloc =================
[21:59:38] ============= drm_cmdline_parser (40 subtests) =============
[21:59:38] [PASSED] drm_test_cmdline_force_d_only
[21:59:38] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:59:38] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:59:38] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:59:38] [PASSED] drm_test_cmdline_force_e_only
[21:59:38] [PASSED] drm_test_cmdline_res
[21:59:38] [PASSED] drm_test_cmdline_res_vesa
[21:59:38] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:59:38] [PASSED] drm_test_cmdline_res_rblank
[21:59:38] [PASSED] drm_test_cmdline_res_bpp
[21:59:38] [PASSED] drm_test_cmdline_res_refresh
[21:59:38] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:59:38] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:59:38] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:59:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:59:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:59:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:59:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:59:38] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:59:38] [PASSED] drm_test_cmdline_res_margins_force_on
[21:59:38] [PASSED] drm_test_cmdline_res_vesa_margins
[21:59:38] [PASSED] drm_test_cmdline_name
[21:59:38] [PASSED] drm_test_cmdline_name_bpp
[21:59:38] [PASSED] drm_test_cmdline_name_option
[21:59:38] [PASSED] drm_test_cmdline_name_bpp_option
[21:59:38] [PASSED] drm_test_cmdline_rotate_0
[21:59:38] [PASSED] drm_test_cmdline_rotate_90
[21:59:38] [PASSED] drm_test_cmdline_rotate_180
[21:59:38] [PASSED] drm_test_cmdline_rotate_270
[21:59:38] [PASSED] drm_test_cmdline_hmirror
[21:59:38] [PASSED] drm_test_cmdline_vmirror
[21:59:38] [PASSED] drm_test_cmdline_margin_options
[21:59:38] [PASSED] drm_test_cmdline_multiple_options
[21:59:38] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:59:38] [PASSED] drm_test_cmdline_extra_and_option
[21:59:38] [PASSED] drm_test_cmdline_freestanding_options
[21:59:38] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:59:38] [PASSED] drm_test_cmdline_panel_orientation
[21:59:38] ================ drm_test_cmdline_invalid  =================
[21:59:38] [PASSED] margin_only
[21:59:38] [PASSED] interlace_only
[21:59:38] [PASSED] res_missing_x
[21:59:38] [PASSED] res_missing_y
[21:59:38] [PASSED] res_bad_y
[21:59:38] [PASSED] res_missing_y_bpp
[21:59:38] [PASSED] res_bad_bpp
[21:59:38] [PASSED] res_bad_refresh
[21:59:38] [PASSED] res_bpp_refresh_force_on_off
[21:59:38] [PASSED] res_invalid_mode
[21:59:38] [PASSED] res_bpp_wrong_place_mode
[21:59:38] [PASSED] name_bpp_refresh
[21:59:38] [PASSED] name_refresh
[21:59:38] [PASSED] name_refresh_wrong_mode
[21:59:38] [PASSED] name_refresh_invalid_mode
[21:59:38] [PASSED] rotate_multiple
[21:59:38] [PASSED] rotate_invalid_val
[21:59:38] [PASSED] rotate_truncated
[21:59:38] [PASSED] invalid_option
[21:59:38] [PASSED] invalid_tv_option
[21:59:38] [PASSED] truncated_tv_option
[21:59:38] ============ [PASSED] drm_test_cmdline_invalid =============
[21:59:38] =============== drm_test_cmdline_tv_options  ===============
[21:59:38] [PASSED] NTSC
[21:59:38] [PASSED] NTSC_443
[21:59:38] [PASSED] NTSC_J
[21:59:38] [PASSED] PAL
[21:59:38] [PASSED] PAL_M
[21:59:38] [PASSED] PAL_N
[21:59:38] [PASSED] SECAM
[21:59:38] [PASSED] MONO_525
[21:59:38] [PASSED] MONO_625
[21:59:38] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:59:38] =============== [PASSED] drm_cmdline_parser ================
[21:59:38] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:59:38] [PASSED] drm_test_connector_hdmi_init_valid
[21:59:38] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:59:38] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:59:38] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:59:38] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:59:38] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:59:38] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:59:38] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:59:38] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:59:38] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:59:38] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:59:38] [PASSED] supported_formats=0x3 yuv420_allowed=1
[21:59:38] [PASSED] supported_formats=0x3 yuv420_allowed=0
[21:59:38] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:59:38] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:59:38] [PASSED] drm_test_connector_hdmi_init_null_product
[21:59:38] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:59:38] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:59:38] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:59:38] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:59:38] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:59:38] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:59:38] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:59:38] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:59:38] [PASSED] HDMI-A
[21:59:38] [PASSED] HDMI-B
[21:59:38] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:59:38] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:59:38] [PASSED] Unknown
[21:59:38] [PASSED] VGA
[21:59:38] [PASSED] DVI-I
[21:59:38] [PASSED] DVI-D
[21:59:38] [PASSED] DVI-A
[21:59:38] [PASSED] Composite
[21:59:38] [PASSED] SVIDEO
[21:59:38] [PASSED] LVDS
[21:59:38] [PASSED] Component
[21:59:38] [PASSED] DIN
[21:59:38] [PASSED] DP
[21:59:38] [PASSED] TV
[21:59:38] [PASSED] eDP
[21:59:38] [PASSED] Virtual
[21:59:38] [PASSED] DSI
[21:59:38] [PASSED] DPI
[21:59:38] [PASSED] Writeback
[21:59:38] [PASSED] SPI
[21:59:38] [PASSED] USB
[21:59:38] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:59:38] ============ [PASSED] drmm_connector_hdmi_init =============
[21:59:38] ============= drmm_connector_init (3 subtests) =============
[21:59:38] [PASSED] drm_test_drmm_connector_init
[21:59:38] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:59:38] ========= drm_test_drmm_connector_init_type_valid  =========
[21:59:38] [PASSED] Unknown
[21:59:38] [PASSED] VGA
[21:59:38] [PASSED] DVI-I
[21:59:38] [PASSED] DVI-D
[21:59:38] [PASSED] DVI-A
[21:59:38] [PASSED] Composite
[21:59:38] [PASSED] SVIDEO
[21:59:38] [PASSED] LVDS
[21:59:38] [PASSED] Component
[21:59:38] [PASSED] DIN
[21:59:38] [PASSED] DP
[21:59:38] [PASSED] HDMI-A
[21:59:38] [PASSED] HDMI-B
[21:59:38] [PASSED] TV
[21:59:38] [PASSED] eDP
[21:59:38] [PASSED] Virtual
[21:59:38] [PASSED] DSI
[21:59:38] [PASSED] DPI
[21:59:38] [PASSED] Writeback
[21:59:38] [PASSED] SPI
[21:59:38] [PASSED] USB
[21:59:38] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:59:38] =============== [PASSED] drmm_connector_init ===============
[21:59:38] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_init
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:59:38] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:59:38] [PASSED] Unknown
[21:59:38] [PASSED] VGA
[21:59:38] [PASSED] DVI-I
[21:59:38] [PASSED] DVI-D
[21:59:38] [PASSED] DVI-A
[21:59:38] [PASSED] Composite
[21:59:38] [PASSED] SVIDEO
[21:59:38] [PASSED] LVDS
[21:59:38] [PASSED] Component
[21:59:38] [PASSED] DIN
[21:59:38] [PASSED] DP
[21:59:38] [PASSED] HDMI-A
[21:59:38] [PASSED] HDMI-B
[21:59:38] [PASSED] TV
[21:59:38] [PASSED] eDP
[21:59:38] [PASSED] Virtual
[21:59:38] [PASSED] DSI
[21:59:38] [PASSED] DPI
[21:59:38] [PASSED] Writeback
[21:59:38] [PASSED] SPI
[21:59:38] [PASSED] USB
[21:59:38] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:59:38] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:59:38] [PASSED] Unknown
[21:59:38] [PASSED] VGA
[21:59:38] [PASSED] DVI-I
[21:59:38] [PASSED] DVI-D
[21:59:38] [PASSED] DVI-A
[21:59:38] [PASSED] Composite
[21:59:38] [PASSED] SVIDEO
[21:59:38] [PASSED] LVDS
[21:59:38] [PASSED] Component
[21:59:38] [PASSED] DIN
[21:59:38] [PASSED] DP
[21:59:38] [PASSED] HDMI-A
[21:59:38] [PASSED] HDMI-B
[21:59:38] [PASSED] TV
[21:59:38] [PASSED] eDP
[21:59:38] [PASSED] Virtual
[21:59:38] [PASSED] DSI
[21:59:38] [PASSED] DPI
[21:59:38] [PASSED] Writeback
[21:59:38] [PASSED] SPI
[21:59:38] [PASSED] USB
[21:59:38] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:59:38] =========== [PASSED] drm_connector_dynamic_init ============
[21:59:38] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:59:38] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:59:38] ======= drm_connector_dynamic_register (7 subtests) ========
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:59:38] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:59:38] ========= [PASSED] drm_connector_dynamic_register ==========
[21:59:38] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:59:38] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:59:38] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:59:38] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:59:38] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:59:38] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:59:38] [PASSED] NTSC
[21:59:38] [PASSED] NTSC-443
[21:59:38] [PASSED] NTSC-J
[21:59:38] [PASSED] PAL
[21:59:38] [PASSED] PAL-M
[21:59:38] [PASSED] PAL-N
[21:59:38] [PASSED] SECAM
[21:59:38] [PASSED] Mono
[21:59:38] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:59:38] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:59:38] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:59:38] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:59:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:59:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:59:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:59:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:59:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:59:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:59:38] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:59:38] [PASSED] VIC 96
[21:59:38] [PASSED] VIC 97
[21:59:38] [PASSED] VIC 101
[21:59:38] [PASSED] VIC 102
[21:59:38] [PASSED] VIC 106
[21:59:38] [PASSED] VIC 107
[21:59:38] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:59:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:59:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:59:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:59:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:59:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:59:38] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:59:38] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:59:38] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:59:38] [PASSED] Automatic
[21:59:38] [PASSED] Full
[21:59:38] [PASSED] Limited 16:235
[21:59:38] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:59:38] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:59:38] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:59:38] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:59:38] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:59:38] [PASSED] RGB
[21:59:38] [PASSED] YUV 4:2:0
[21:59:38] [PASSED] YUV 4:2:2
[21:59:38] [PASSED] YUV 4:4:4
[21:59:38] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:59:38] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:59:38] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:59:38] ============= drm_damage_helper (21 subtests) ==============
[21:59:38] [PASSED] drm_test_damage_iter_no_damage
[21:59:38] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:59:38] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:59:38] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:59:38] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:59:38] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:59:38] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:59:38] [PASSED] drm_test_damage_iter_simple_damage
[21:59:38] [PASSED] drm_test_damage_iter_single_damage
[21:59:38] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:59:38] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:59:38] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:59:38] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:59:38] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:59:38] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:59:38] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:59:38] [PASSED] drm_test_damage_iter_damage
[21:59:38] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:59:38] [PASSED] drm_test_damage_iter_damage_one_outside
[21:59:38] [PASSED] drm_test_damage_iter_damage_src_moved
[21:59:38] [PASSED] drm_test_damage_iter_damage_not_visible
[21:59:38] ================ [PASSED] drm_damage_helper ================
[21:59:38] ============== drm_dp_mst_helper (3 subtests) ==============
[21:59:38] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:59:38] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:59:38] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:59:38] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:59:38] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:59:38] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:59:38] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:59:38] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:59:38] [PASSED] Link rate 2000000 lane count 4
[21:59:38] [PASSED] Link rate 2000000 lane count 2
[21:59:38] [PASSED] Link rate 2000000 lane count 1
[21:59:38] [PASSED] Link rate 1350000 lane count 4
[21:59:38] [PASSED] Link rate 1350000 lane count 2
[21:59:38] [PASSED] Link rate 1350000 lane count 1
[21:59:38] [PASSED] Link rate 1000000 lane count 4
[21:59:38] [PASSED] Link rate 1000000 lane count 2
[21:59:38] [PASSED] Link rate 1000000 lane count 1
[21:59:38] [PASSED] Link rate 810000 lane count 4
[21:59:38] [PASSED] Link rate 810000 lane count 2
[21:59:38] [PASSED] Link rate 810000 lane count 1
[21:59:38] [PASSED] Link rate 540000 lane count 4
[21:59:38] [PASSED] Link rate 540000 lane count 2
[21:59:38] [PASSED] Link rate 540000 lane count 1
[21:59:38] [PASSED] Link rate 270000 lane count 4
[21:59:38] [PASSED] Link rate 270000 lane count 2
[21:59:38] [PASSED] Link rate 270000 lane count 1
[21:59:38] [PASSED] Link rate 162000 lane count 4
[21:59:38] [PASSED] Link rate 162000 lane count 2
[21:59:38] [PASSED] Link rate 162000 lane count 1
[21:59:38] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:59:38] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:59:38] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:59:38] [PASSED] DP_POWER_UP_PHY with port number
[21:59:38] [PASSED] DP_POWER_DOWN_PHY with port number
[21:59:38] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:59:38] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:59:38] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:59:38] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:59:38] [PASSED] DP_QUERY_PAYLOAD with port number
[21:59:38] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:59:38] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:59:38] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:59:38] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:59:38] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:59:38] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:59:38] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:59:38] [PASSED] DP_REMOTE_I2C_READ with port number
[21:59:38] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:59:38] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:59:38] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:59:38] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:59:38] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:59:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:59:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:59:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:59:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:59:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:59:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:59:38] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:59:38] ================ [PASSED] drm_dp_mst_helper ================
[21:59:38] ================== drm_exec (7 subtests) ===================
[21:59:38] [PASSED] sanitycheck
[21:59:38] [PASSED] test_lock
[21:59:38] [PASSED] test_lock_unlock
[21:59:38] [PASSED] test_duplicates
[21:59:38] [PASSED] test_prepare
[21:59:38] [PASSED] test_prepare_array
[21:59:38] [PASSED] test_multiple_loops
[21:59:38] ==================== [PASSED] drm_exec =====================
[21:59:38] =========== drm_format_helper_test (17 subtests) ===========
[21:59:38] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:59:38] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:59:38] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:59:38] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:59:38] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:59:38] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:59:38] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:59:38] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:59:38] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:59:38] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:59:38] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:59:38] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:59:38] ==================== drm_test_fb_swab  =====================
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ================ [PASSED] drm_test_fb_swab =================
[21:59:38] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:59:38] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:59:38] [PASSED] single_pixel_source_buffer
[21:59:38] [PASSED] single_pixel_clip_rectangle
[21:59:38] [PASSED] well_known_colors
[21:59:38] [PASSED] destination_pitch
[21:59:38] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:59:38] ================= drm_test_fb_clip_offset  =================
[21:59:38] [PASSED] pass through
[21:59:38] [PASSED] horizontal offset
[21:59:38] [PASSED] vertical offset
[21:59:38] [PASSED] horizontal and vertical offset
[21:59:38] [PASSED] horizontal offset (custom pitch)
[21:59:38] [PASSED] vertical offset (custom pitch)
[21:59:38] [PASSED] horizontal and vertical offset (custom pitch)
[21:59:38] ============= [PASSED] drm_test_fb_clip_offset =============
[21:59:38] =================== drm_test_fb_memcpy  ====================
[21:59:38] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:59:38] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:59:38] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:59:38] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:59:38] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:59:38] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:59:38] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:59:38] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:59:38] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:59:38] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:59:38] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:59:38] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:59:38] =============== [PASSED] drm_test_fb_memcpy ================
[21:59:38] ============= [PASSED] drm_format_helper_test ==============
[21:59:38] ================= drm_format (18 subtests) =================
[21:59:38] [PASSED] drm_test_format_block_width_invalid
[21:59:38] [PASSED] drm_test_format_block_width_one_plane
[21:59:38] [PASSED] drm_test_format_block_width_two_plane
[21:59:38] [PASSED] drm_test_format_block_width_three_plane
[21:59:38] [PASSED] drm_test_format_block_width_tiled
[21:59:38] [PASSED] drm_test_format_block_height_invalid
[21:59:38] [PASSED] drm_test_format_block_height_one_plane
[21:59:38] [PASSED] drm_test_format_block_height_two_plane
[21:59:38] [PASSED] drm_test_format_block_height_three_plane
[21:59:38] [PASSED] drm_test_format_block_height_tiled
[21:59:38] [PASSED] drm_test_format_min_pitch_invalid
[21:59:38] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:59:38] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:59:38] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:59:38] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:59:38] [PASSED] drm_test_format_min_pitch_two_plane
[21:59:38] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:59:38] [PASSED] drm_test_format_min_pitch_tiled
[21:59:38] =================== [PASSED] drm_format ====================
[21:59:38] ============== drm_framebuffer (10 subtests) ===============
[21:59:38] ========== drm_test_framebuffer_check_src_coords  ==========
[21:59:38] [PASSED] Success: source fits into fb
[21:59:38] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:59:38] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:59:38] [PASSED] Fail: overflowing fb with source width
[21:59:38] [PASSED] Fail: overflowing fb with source height
[21:59:38] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:59:38] [PASSED] drm_test_framebuffer_cleanup
[21:59:38] =============== drm_test_framebuffer_create  ===============
[21:59:38] [PASSED] ABGR8888 normal sizes
[21:59:38] [PASSED] ABGR8888 max sizes
[21:59:38] [PASSED] ABGR8888 pitch greater than min required
[21:59:38] [PASSED] ABGR8888 pitch less than min required
[21:59:38] [PASSED] ABGR8888 Invalid width
[21:59:38] [PASSED] ABGR8888 Invalid buffer handle
[21:59:38] [PASSED] No pixel format
[21:59:38] [PASSED] ABGR8888 Width 0
[21:59:38] [PASSED] ABGR8888 Height 0
[21:59:38] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:59:38] [PASSED] ABGR8888 Large buffer offset
[21:59:38] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:59:38] [PASSED] ABGR8888 Invalid flag
[21:59:38] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:59:38] [PASSED] ABGR8888 Valid buffer modifier
[21:59:38] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:59:38] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:59:38] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:59:38] [PASSED] NV12 Normal sizes
[21:59:38] [PASSED] NV12 Max sizes
[21:59:38] [PASSED] NV12 Invalid pitch
[21:59:38] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:59:38] [PASSED] NV12 different  modifier per-plane
[21:59:38] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:59:38] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:59:38] [PASSED] NV12 Modifier for inexistent plane
[21:59:38] [PASSED] NV12 Handle for inexistent plane
[21:59:38] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:59:38] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:59:38] [PASSED] YVU420 Normal sizes
[21:59:38] [PASSED] YVU420 Max sizes
[21:59:38] [PASSED] YVU420 Invalid pitch
[21:59:38] [PASSED] YVU420 Different pitches
[21:59:38] [PASSED] YVU420 Different buffer offsets/pitches
[21:59:38] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:59:38] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:59:38] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:59:38] [PASSED] YVU420 Valid modifier
[21:59:38] [PASSED] YVU420 Different modifiers per plane
[21:59:38] [PASSED] YVU420 Modifier for inexistent plane
[21:59:38] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:59:38] [PASSED] X0L2 Normal sizes
[21:59:38] [PASSED] X0L2 Max sizes
[21:59:38] [PASSED] X0L2 Invalid pitch
[21:59:38] [PASSED] X0L2 Pitch greater than minimum required
[21:59:38] [PASSED] X0L2 Handle for inexistent plane
[21:59:38] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:59:38] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:59:38] [PASSED] X0L2 Valid modifier
[21:59:38] [PASSED] X0L2 Modifier for inexistent plane
[21:59:38] =========== [PASSED] drm_test_framebuffer_create ===========
[21:59:38] [PASSED] drm_test_framebuffer_free
[21:59:38] [PASSED] drm_test_framebuffer_init
[21:59:38] [PASSED] drm_test_framebuffer_init_bad_format
[21:59:38] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:59:38] [PASSED] drm_test_framebuffer_lookup
[21:59:38] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:59:38] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:59:38] ================= [PASSED] drm_framebuffer =================
[21:59:38] ================ drm_gem_shmem (8 subtests) ================
[21:59:38] [PASSED] drm_gem_shmem_test_obj_create
[21:59:38] [PASSED] drm_gem_shmem_test_obj_create_private
[21:59:38] [PASSED] drm_gem_shmem_test_pin_pages
[21:59:38] [PASSED] drm_gem_shmem_test_vmap
[21:59:38] [PASSED] drm_gem_shmem_test_get_sg_table
[21:59:38] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:59:38] [PASSED] drm_gem_shmem_test_madvise
[21:59:38] [PASSED] drm_gem_shmem_test_purge
[21:59:38] ================== [PASSED] drm_gem_shmem ==================
[21:59:38] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:59:38] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:59:38] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:59:38] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:59:38] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:59:38] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:59:38] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:59:38] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:59:38] [PASSED] Automatic
[21:59:38] [PASSED] Full
[21:59:38] [PASSED] Limited 16:235
[21:59:38] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:59:38] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:59:38] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:59:38] [PASSED] drm_test_check_disable_connector
[21:59:38] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:59:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:59:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:59:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:59:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:59:38] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:59:38] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:59:38] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:59:38] [PASSED] drm_test_check_output_bpc_dvi
[21:59:38] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:59:38] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:59:38] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:59:38] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:59:38] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:59:38] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:59:38] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:59:38] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:59:38] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:59:38] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:59:38] [PASSED] drm_test_check_broadcast_rgb_value
[21:59:38] [PASSED] drm_test_check_bpc_8_value
[21:59:38] [PASSED] drm_test_check_bpc_10_value
[21:59:38] [PASSED] drm_test_check_bpc_12_value
[21:59:38] [PASSED] drm_test_check_format_value
[21:59:38] [PASSED] drm_test_check_tmds_char_value
[21:59:38] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:59:38] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:59:38] [PASSED] drm_test_check_mode_valid
[21:59:38] [PASSED] drm_test_check_mode_valid_reject
[21:59:38] [PASSED] drm_test_check_mode_valid_reject_rate
[21:59:38] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:59:38] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:59:38] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[21:59:38] [PASSED] drm_test_check_infoframes
[21:59:38] [PASSED] drm_test_check_reject_avi_infoframe
[21:59:38] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[21:59:38] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[21:59:38] [PASSED] drm_test_check_reject_audio_infoframe
[21:59:38] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[21:59:38] ================= drm_managed (2 subtests) =================
[21:59:38] [PASSED] drm_test_managed_release_action
[21:59:38] [PASSED] drm_test_managed_run_action
[21:59:38] =================== [PASSED] drm_managed ===================
[21:59:38] =================== drm_mm (6 subtests) ====================
[21:59:38] [PASSED] drm_test_mm_init
[21:59:38] [PASSED] drm_test_mm_debug
[21:59:38] [PASSED] drm_test_mm_align32
[21:59:38] [PASSED] drm_test_mm_align64
[21:59:38] [PASSED] drm_test_mm_lowest
[21:59:38] [PASSED] drm_test_mm_highest
[21:59:38] ===================== [PASSED] drm_mm ======================
[21:59:38] ============= drm_modes_analog_tv (5 subtests) =============
[21:59:38] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:59:38] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:59:38] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:59:38] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:59:38] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:59:38] =============== [PASSED] drm_modes_analog_tv ===============
[21:59:38] ============== drm_plane_helper (2 subtests) ===============
[21:59:38] =============== drm_test_check_plane_state  ================
[21:59:38] [PASSED] clipping_simple
[21:59:38] [PASSED] clipping_rotate_reflect
[21:59:38] [PASSED] positioning_simple
[21:59:38] [PASSED] upscaling
[21:59:38] [PASSED] downscaling
[21:59:38] [PASSED] rounding1
[21:59:38] [PASSED] rounding2
[21:59:38] [PASSED] rounding3
[21:59:38] [PASSED] rounding4
[21:59:38] =========== [PASSED] drm_test_check_plane_state ============
[21:59:38] =========== drm_test_check_invalid_plane_state  ============
[21:59:38] [PASSED] positioning_invalid
[21:59:38] [PASSED] upscaling_invalid
[21:59:38] [PASSED] downscaling_invalid
[21:59:38] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:59:38] ================ [PASSED] drm_plane_helper =================
[21:59:38] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:59:38] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:59:38] [PASSED] None
[21:59:38] [PASSED] PAL
[21:59:38] [PASSED] NTSC
[21:59:38] [PASSED] Both, NTSC Default
[21:59:38] [PASSED] Both, PAL Default
[21:59:38] [PASSED] Both, NTSC Default, with PAL on command-line
[21:59:38] [PASSED] Both, PAL Default, with NTSC on command-line
[21:59:38] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:59:38] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:59:38] ================== drm_rect (9 subtests) ===================
[21:59:38] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:59:38] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:59:38] [PASSED] drm_test_rect_clip_scaled_clipped
[21:59:38] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:59:38] ================= drm_test_rect_intersect  =================
[21:59:38] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:59:38] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:59:38] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:59:38] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:59:38] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:59:38] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:59:38] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:59:38] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:59:38] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:59:38] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:59:38] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:59:38] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:59:38] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:59:38] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:59:38] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:59:38] ============= [PASSED] drm_test_rect_intersect =============
[21:59:38] ================ drm_test_rect_calc_hscale  ================
[21:59:38] [PASSED] normal use
[21:59:38] [PASSED] out of max range
[21:59:38] [PASSED] out of min range
[21:59:38] [PASSED] zero dst
[21:59:38] [PASSED] negative src
[21:59:38] [PASSED] negative dst
[21:59:38] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:59:38] ================ drm_test_rect_calc_vscale  ================
[21:59:38] [PASSED] normal use
[21:59:38] [PASSED] out of max range
[21:59:38] [PASSED] out of min range
[21:59:38] [PASSED] zero dst
[21:59:38] [PASSED] negative src
[21:59:38] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[21:59:38] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:59:38] ================== drm_test_rect_rotate  ===================
[21:59:38] [PASSED] reflect-x
[21:59:38] [PASSED] reflect-y
[21:59:38] [PASSED] rotate-0
[21:59:38] [PASSED] rotate-90
[21:59:38] [PASSED] rotate-180
[21:59:38] [PASSED] rotate-270
[21:59:38] ============== [PASSED] drm_test_rect_rotate ===============
[21:59:38] ================ drm_test_rect_rotate_inv  =================
[21:59:38] [PASSED] reflect-x
[21:59:38] [PASSED] reflect-y
[21:59:38] [PASSED] rotate-0
[21:59:38] [PASSED] rotate-90
[21:59:38] [PASSED] rotate-180
[21:59:38] [PASSED] rotate-270
[21:59:38] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:59:38] ==================== [PASSED] drm_rect =====================
[21:59:38] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:59:38] ============ drm_test_sysfb_build_fourcc_list  =============
[21:59:38] [PASSED] no native formats
[21:59:38] [PASSED] XRGB8888 as native format
[21:59:38] [PASSED] remove duplicates
[21:59:38] [PASSED] convert alpha formats
[21:59:38] [PASSED] random formats
[21:59:38] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:59:38] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:59:38] ================== drm_fixp (2 subtests) ===================
[21:59:38] [PASSED] drm_test_int2fixp
[21:59:38] [PASSED] drm_test_sm2fixp
[21:59:38] ==================== [PASSED] drm_fixp =====================
[21:59:38] ============================================================
[21:59:38] Testing complete. Ran 621 tests: passed: 621
[21:59:38] Elapsed time: 27.340s total, 1.646s configuring, 25.523s building, 0.138s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:59:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:59:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:59:49] Starting KUnit Kernel (1/1)...
[21:59:49] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:59:50] ================= ttm_device (5 subtests) ==================
[21:59:50] [PASSED] ttm_device_init_basic
[21:59:50] [PASSED] ttm_device_init_multiple
[21:59:50] [PASSED] ttm_device_fini_basic
[21:59:50] [PASSED] ttm_device_init_no_vma_man
[21:59:50] ================== ttm_device_init_pools  ==================
[21:59:50] [PASSED] No DMA allocations, no DMA32 required
[21:59:50] [PASSED] DMA allocations, DMA32 required
[21:59:50] [PASSED] No DMA allocations, DMA32 required
[21:59:50] [PASSED] DMA allocations, no DMA32 required
[21:59:50] ============== [PASSED] ttm_device_init_pools ==============
[21:59:50] =================== [PASSED] ttm_device ====================
[21:59:50] ================== ttm_pool (8 subtests) ===================
[21:59:50] ================== ttm_pool_alloc_basic  ===================
[21:59:50] [PASSED] One page
[21:59:50] [PASSED] More than one page
[21:59:50] [PASSED] Above the allocation limit
[21:59:50] [PASSED] One page, with coherent DMA mappings enabled
[21:59:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:59:50] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:59:50] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:59:50] [PASSED] One page
[21:59:50] [PASSED] More than one page
[21:59:50] [PASSED] Above the allocation limit
[21:59:50] [PASSED] One page, with coherent DMA mappings enabled
[21:59:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:59:50] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:59:50] [PASSED] ttm_pool_alloc_order_caching_match
[21:59:50] [PASSED] ttm_pool_alloc_caching_mismatch
[21:59:50] [PASSED] ttm_pool_alloc_order_mismatch
[21:59:50] [PASSED] ttm_pool_free_dma_alloc
[21:59:50] [PASSED] ttm_pool_free_no_dma_alloc
[21:59:50] [PASSED] ttm_pool_fini_basic
[21:59:50] ==================== [PASSED] ttm_pool =====================
[21:59:50] ================ ttm_resource (8 subtests) =================
[21:59:50] ================= ttm_resource_init_basic  =================
[21:59:50] [PASSED] Init resource in TTM_PL_SYSTEM
[21:59:50] [PASSED] Init resource in TTM_PL_VRAM
[21:59:50] [PASSED] Init resource in a private placement
[21:59:50] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:59:50] ============= [PASSED] ttm_resource_init_basic =============
[21:59:50] [PASSED] ttm_resource_init_pinned
[21:59:50] [PASSED] ttm_resource_fini_basic
[21:59:50] [PASSED] ttm_resource_manager_init_basic
[21:59:50] [PASSED] ttm_resource_manager_usage_basic
[21:59:50] [PASSED] ttm_resource_manager_set_used_basic
[21:59:50] [PASSED] ttm_sys_man_alloc_basic
[21:59:50] [PASSED] ttm_sys_man_free_basic
[21:59:50] ================== [PASSED] ttm_resource ===================
[21:59:50] =================== ttm_tt (15 subtests) ===================
[21:59:50] ==================== ttm_tt_init_basic  ====================
[21:59:50] [PASSED] Page-aligned size
[21:59:50] [PASSED] Extra pages requested
[21:59:50] ================ [PASSED] ttm_tt_init_basic ================
[21:59:50] [PASSED] ttm_tt_init_misaligned
[21:59:50] [PASSED] ttm_tt_fini_basic
[21:59:50] [PASSED] ttm_tt_fini_sg
[21:59:50] [PASSED] ttm_tt_fini_shmem
[21:59:50] [PASSED] ttm_tt_create_basic
[21:59:50] [PASSED] ttm_tt_create_invalid_bo_type
[21:59:50] [PASSED] ttm_tt_create_ttm_exists
[21:59:50] [PASSED] ttm_tt_create_failed
[21:59:50] [PASSED] ttm_tt_destroy_basic
[21:59:50] [PASSED] ttm_tt_populate_null_ttm
[21:59:50] [PASSED] ttm_tt_populate_populated_ttm
[21:59:50] [PASSED] ttm_tt_unpopulate_basic
[21:59:50] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:59:50] [PASSED] ttm_tt_swapin_basic
[21:59:50] ===================== [PASSED] ttm_tt ======================
[21:59:50] =================== ttm_bo (14 subtests) ===================
[21:59:50] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:59:50] [PASSED] Cannot be interrupted and sleeps
[21:59:50] [PASSED] Cannot be interrupted, locks straight away
[21:59:50] [PASSED] Can be interrupted, sleeps
[21:59:50] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:59:50] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:59:50] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:59:50] [PASSED] ttm_bo_reserve_double_resv
[21:59:50] [PASSED] ttm_bo_reserve_interrupted
[21:59:50] [PASSED] ttm_bo_reserve_deadlock
[21:59:50] [PASSED] ttm_bo_unreserve_basic
[21:59:50] [PASSED] ttm_bo_unreserve_pinned
[21:59:50] [PASSED] ttm_bo_unreserve_bulk
[21:59:50] [PASSED] ttm_bo_fini_basic
[21:59:50] [PASSED] ttm_bo_fini_shared_resv
[21:59:50] [PASSED] ttm_bo_pin_basic
[21:59:50] [PASSED] ttm_bo_pin_unpin_resource
[21:59:50] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:59:50] ===================== [PASSED] ttm_bo ======================
[21:59:50] ============== ttm_bo_validate (21 subtests) ===============
[21:59:50] ============== ttm_bo_init_reserved_sys_man  ===============
[21:59:50] [PASSED] Buffer object for userspace
[21:59:50] [PASSED] Kernel buffer object
[21:59:50] [PASSED] Shared buffer object
[21:59:50] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:59:50] ============== ttm_bo_init_reserved_mock_man  ==============
[21:59:50] [PASSED] Buffer object for userspace
[21:59:50] [PASSED] Kernel buffer object
[21:59:50] [PASSED] Shared buffer object
[21:59:50] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:59:50] [PASSED] ttm_bo_init_reserved_resv
[21:59:50] ================== ttm_bo_validate_basic  ==================
[21:59:50] [PASSED] Buffer object for userspace
[21:59:50] [PASSED] Kernel buffer object
[21:59:50] [PASSED] Shared buffer object
[21:59:50] ============== [PASSED] ttm_bo_validate_basic ==============
[21:59:50] [PASSED] ttm_bo_validate_invalid_placement
[21:59:50] ============= ttm_bo_validate_same_placement  ==============
[21:59:50] [PASSED] System manager
[21:59:50] [PASSED] VRAM manager
[21:59:50] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:59:50] [PASSED] ttm_bo_validate_failed_alloc
[21:59:50] [PASSED] ttm_bo_validate_pinned
[21:59:50] [PASSED] ttm_bo_validate_busy_placement
[21:59:50] ================ ttm_bo_validate_multihop  =================
[21:59:50] [PASSED] Buffer object for userspace
[21:59:50] [PASSED] Kernel buffer object
[21:59:50] [PASSED] Shared buffer object
[21:59:50] ============ [PASSED] ttm_bo_validate_multihop =============
[21:59:50] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:59:50] [PASSED] Buffer object in system domain, no page vector
[21:59:50] [PASSED] Buffer object in system domain with an existing page vector
[21:59:50] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:59:50] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:59:50] [PASSED] Buffer object for userspace
[21:59:50] [PASSED] Kernel buffer object
[21:59:50] [PASSED] Shared buffer object
[21:59:50] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:59:50] [PASSED] ttm_bo_validate_move_fence_signaled
[21:59:50] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:59:50] [PASSED] Waits for GPU
[21:59:50] [PASSED] Tries to lock straight away
[21:59:50] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:59:50] [PASSED] ttm_bo_validate_happy_evict
[21:59:50] [PASSED] ttm_bo_validate_all_pinned_evict
[21:59:50] [PASSED] ttm_bo_validate_allowed_only_evict
[21:59:50] [PASSED] ttm_bo_validate_deleted_evict
[21:59:50] [PASSED] ttm_bo_validate_busy_domain_evict
[21:59:50] [PASSED] ttm_bo_validate_evict_gutting
[21:59:50] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:59:50] ================= [PASSED] ttm_bo_validate =================
[21:59:50] ============================================================
[21:59:50] Testing complete. Ran 101 tests: passed: 101
[21:59:50] Elapsed time: 11.485s total, 1.668s configuring, 9.600s building, 0.173s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for GuC CT memory optimizations

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 850 bytes --]

== Series Details ==

Series: GuC CT memory optimizations
URL   : https://patchwork.freedesktop.org/series/161604/
State : success

== Summary ==

CI Bug Log - changes from xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288_BAT -> xe-pw-161604v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288 -> xe-pw-161604v1

  IGT_8753: 8753
  xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288: 69686d26e229ebcd8068fd86b7c39bc0832e8288
  xe-pw-161604v1: 161604v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/index.html

[-- Attachment #2: Type: text/html, Size: 1398 bytes --]

✗ Xe.CI.FULL: failure for GuC CT memory optimizations

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 27296 bytes --]

== Series Details ==

Series: GuC CT memory optimizations
URL   : https://patchwork.freedesktop.org/series/161604/
State : failure

== Summary ==

CI Bug Log - changes from xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288_FULL -> xe-pw-161604v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-161604v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-161604v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-161604v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-d-dp-2.html

  * igt@xe_module_load@many-reload:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][2]
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_module_load@many-reload.html

  
Known issues
------------

  Here are the changes found in xe-pw-161604v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2370])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#7059])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2328]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html

  * igt@kms_bw@linear-tiling-1-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#367]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][9] -> [INCOMPLETE][10] ([Intel XE#7084])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#3432])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2887]) +7 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2252]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][14] ([Intel XE#3304])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2321]) +1 other test skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2320])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2286])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [PASS][18] -> [FAIL][19] ([Intel XE#301] / [Intel XE#3149])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [PASS][20] -> [INCOMPLETE][21] ([Intel XE#2049] / [Intel XE#2597]) +2 other tests incomplete
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7178]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7179])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@kms_flip_scaled_crc@flip-32bpp-yuv-linear-to-32bpp-yuv-linear-reflect-x.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2311]) +14 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#4141]) +5 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2313]) +12 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7061]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][28] -> [SKIP][29] ([Intel XE#1503])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-6/igt@kms_hdr@invalid-hdr.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#7111]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier.html

  * igt@kms_plane_cursor@viewport:
    - shard-bmg:          [PASS][31] -> [DMESG-FAIL][32] ([Intel XE#5545]) +1 other test dmesg-fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@kms_plane_cursor@viewport.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_plane_cursor@viewport.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#3309])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#1406] / [Intel XE#2387])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#1406] / [Intel XE#6703])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_psr@fbc-psr2-no-drrs.html

  * igt@kms_psr@pr-sprite-render:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_psr@pr-sprite-render.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#1406] / [Intel XE#2234])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@kms_psr@psr2-primary-render.html

  * igt@kms_sharpness_filter@filter-toggle:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#6503])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_sharpness_filter@filter-toggle.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2450])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][41] -> [FAIL][42] ([Intel XE#2142]) +1 other test fail
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-lnl-6/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_eudebug@multigpu-basic-client:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#4837]) +3 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@xe_eudebug@multigpu-basic-client.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@xe_eudebug_online@single-step.html

  * igt@xe_evict@evict-small-external-multi-queue-cm:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#7140]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@xe_evict@evict-small-external-multi-queue-cm.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2322]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#6703]) +56 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#7136]) +5 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#6874]) +13 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_system_allocator@many-stride-new-prefetch:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][50] ([Intel XE#7098])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@xe_exec_system_allocator@many-stride-new-prefetch.html

  * igt@xe_exec_system_allocator@threads-many-execqueues-mmap-file-mlock:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#6557] / [Intel XE#6703])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-execqueues-mmap-file-mlock.html

  * igt@xe_exec_system_allocator@threads-shared-alloc-many-stride-malloc:
    - shard-bmg:          [PASS][52] -> [SKIP][53] ([Intel XE#6703]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@xe_exec_system_allocator@threads-shared-alloc-many-stride-malloc.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-alloc-many-stride-malloc.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#7138]) +2 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr-invalidate-race.html

  * igt@xe_multigpu_svm@mgpu-concurrent-access-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#6964]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@xe_multigpu_svm@mgpu-concurrent-access-prefetch.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#2284])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#4733])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html

  * igt@xe_query@multigpu-query-invalid-query:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#944]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@xe_query@multigpu-query-invalid-query.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - shard-bmg:          [ABORT][59] ([Intel XE#7249]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-8/igt@core_hotunplug@unbind-rebind.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-1/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_atomic_interruptible@universal-setplane-primary@pipe-a-dp-2:
    - shard-bmg:          [ABORT][61] ([Intel XE#5545]) -> [PASS][62] +1 other test pass
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-2/igt@kms_atomic_interruptible@universal-setplane-primary@pipe-a-dp-2.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-8/igt@kms_atomic_interruptible@universal-setplane-primary@pipe-a-dp-2.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-bmg:          [SKIP][63] ([Intel XE#367]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-9/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][65] ([Intel XE#301]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_plane@pixel-format-linear-modifier-source-clamping@pipe-a-plane-0:
    - shard-lnl:          [FAIL][67] -> [PASS][68] +1 other test pass
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-4/igt@kms_plane@pixel-format-linear-modifier-source-clamping@pipe-a-plane-0.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-lnl-7/igt@kms_plane@pixel-format-linear-modifier-source-clamping@pipe-a-plane-0.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][69] ([Intel XE#6321]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html

  
#### Warnings ####

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-bmg:          [SKIP][71] ([Intel XE#1124]) -> [SKIP][72] ([Intel XE#6703])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_content_protection@lic-type-1:
    - shard-bmg:          [SKIP][73] ([Intel XE#2341]) -> [SKIP][74] ([Intel XE#6703])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@kms_content_protection@lic-type-1.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@kms_content_protection@lic-type-1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][75] ([Intel XE#301]) -> [FAIL][76] ([Intel XE#301] / [Intel XE#3149])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [DMESG-WARN][77] ([Intel XE#5208]) -> [INCOMPLETE][78] ([Intel XE#2049] / [Intel XE#2597])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@kms_flip@flip-vs-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-5/igt@kms_flip@flip-vs-suspend.html

  * igt@xe_configfs@ctx-restore-mid-bb-invalid:
    - shard-bmg:          [ABORT][79] -> [SKIP][80] ([Intel XE#6703])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@xe_configfs@ctx-restore-mid-bb-invalid.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_configfs@ctx-restore-mid-bb-invalid.html

  * igt@xe_eudebug_online@debugger-reopen:
    - shard-bmg:          [SKIP][81] ([Intel XE#4837] / [Intel XE#6665]) -> [SKIP][82] ([Intel XE#6703])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@xe_eudebug_online@debugger-reopen.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_eudebug_online@debugger-reopen.html

  * igt@xe_exec_multi_queue@many-queues-basic-smem:
    - shard-bmg:          [SKIP][83] ([Intel XE#6874]) -> [SKIP][84] ([Intel XE#6703]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@xe_exec_multi_queue@many-queues-basic-smem.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-basic-smem.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-invalidate-race:
    - shard-bmg:          [SKIP][85] ([Intel XE#7138]) -> [SKIP][86] ([Intel XE#6703])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-invalidate-race.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-shared-vm-userptr-invalidate-race.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-bmg:          [ABORT][87] ([Intel XE#5466]) -> [ABORT][88] ([Intel XE#5466] / [Intel XE#6652])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288/shard-bmg-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/shard-bmg-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7098
  [Intel XE#7111]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7111
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7179]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7179
  [Intel XE#7249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7249
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288 -> xe-pw-161604v1

  IGT_8753: 8753
  xe-4556-69686d26e229ebcd8068fd86b7c39bc0832e8288: 69686d26e229ebcd8068fd86b7c39bc0832e8288
  xe-pw-161604v1: 161604v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161604v1/index.html

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