[PATCH 00/14] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[PATCH 00/14] Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[Ankit Nautiyal]

Enable Adaptive Sync SDP for Panel replay + auxless ALPM.
First few patches are fixes in existing AS SDP enablement.
Later patches add the support to send AS SDP for Panel replay with Link
ON and with auxless ALPM (Link-Off). 

This series is in continuation from discussions in [1] [2] and more
recent [3]:

Apart from few patches from [3] new changes include:
- Add AS SDP version and PR and VRR specific bits in drm_dp.h.
- Modify AS SDP compute config to accomodate PR with Link On and Link
  Off.
- Program Downspread Ctrl DPCD bits.
- Make way for T1 and T2 AS SDP transmission timing/position.

Note:
Currently I have enabled AS SDP for either VRR or Panel Replay. However
in view of the optimized guardband, perhaps we should always enable AS
SDP whenever supported. That way we will always take the AS SDP constraints
into account while computing the optimized guardband.

[1] https://lore.kernel.org/all/1b8c6c6de1e5fe0db83e6ae942dfee7e6f950767.camel@intel.com/
[2] https://lore.kernel.org/all/aPtqdAxDwiuQZbrn@intel.com/
[3] https://lore.kernel.org/intel-gfx/7c2d6f4e-69e6-452a-89cc-5fd4254430bd@intel.com/T/#m6e8beab2cc3b6ff9d61f740f107d83a2f4e08114

Ankit Nautiyal (14):
  drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP
  drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink
  drm/i915/dp: Add a helper to decide if AS SDP is needed
  drm/i915/dp: Update the helper intel_dp_needs_as_sdp() for CMRR
  include/drm/display/dp: Add field for storing AS SDP version
  drm/i915/dp: Use version field of AS SDP data structure
  drm/i915/dp: Compute AS SDP after PSR and LOBF
  drm/i915/dp: Add AS SDP support for PR with link ON
  drm/i915/psr: Add helper to check if PR is with link OFF
  drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless
    ALPM
  drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off
  include/drm/display/dp: Add DPCD registers for configuring Panel
    Replay + VRR
  drm/i915/display: Add member to store AS SDP transmission time
  drm/i915/dp: Account for AS_SDP guardband only when enabled

 drivers/gpu/drm/display/drm_dp_helper.c       |  1 +
 drivers/gpu/drm/i915/display/intel_alpm.c     | 21 +++++++-
 drivers/gpu/drm/i915/display/intel_display.c  |  3 +-
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 48 ++++++++++++++-----
 .../drm/i915/display/intel_dp_link_training.c | 10 +++-
 .../drm/i915/display/intel_dp_link_training.h |  3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 13 +++++
 drivers/gpu/drm/i915/display/intel_psr.h      |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 10 ++++
 include/drm/display/drm_dp.h                  |  9 ++++
 include/drm/display/drm_dp_helper.h           |  1 +
 13 files changed, 105 insertions(+), 18 deletions(-)

-- 
2.45.2

[PATCH 01/14] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP

[Ankit Nautiyal]

Correct the bit-shift logic to properly readback the 10 bit target_rr from
DB3 and DB4.

v2: Align the style with readback for vtotal. (Ville)

Fixes: 12ea89291603 ("drm/i915/dp: Add Read/Write support for Adaptive Sync SDP")
Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 025e906b63a9..b999d8c085c7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5187,7 +5187,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
 	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
-	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
 
 	return 0;
-- 
2.45.2

[PATCH 02/14] drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink

[Ankit Nautiyal]

Currently we do not support VRR with HDMI so skip vrr compute
config step for all DP branch devices.

v2: Restrict VRR on all DP branch devices instead for checking only for
    HDMI. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 00ca76dbdd6c..c1d8b32ef42f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,6 +55,16 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 		if (connector->mst.dp)
 			return false;
 		intel_dp = intel_attached_dp(connector);
+		/*
+		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
+		 * via a PCON could support VRR. However, supporting VRR through a
+		 * PCON requires non-trivial changes that are not implemented yet.
+		 * Until that support exists, avoid VRR on all DP branch devices.
+		 *
+		 * TODO: Add support for VRR for DP->HDMI 2.1 PCON.
+		 */
+		if (drm_dp_is_branch(intel_dp->dpcd))
+			return false;
 
 		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
 			return false;
-- 
2.45.2

Re: [PATCH 02/14] drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink

[Ville Syrjälä]

On Mon, Feb 23, 2026 at 07:14:19PM +0530, Ankit Nautiyal wrote:
> Currently we do not support VRR with HDMI so skip vrr compute
> config step for all DP branch devices.
> 
> v2: Restrict VRR on all DP branch devices instead for checking only for
>     HDMI. (Ville)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 00ca76dbdd6c..c1d8b32ef42f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -55,6 +55,16 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
>  		if (connector->mst.dp)
>  			return false;
>  		intel_dp = intel_attached_dp(connector);
> +		/*
> +		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
> +		 * via a PCON could support VRR. However, supporting VRR through a
> +		 * PCON requires non-trivial changes that are not implemented yet.
> +		 * Until that support exists, avoid VRR on all DP branch devices.
> +		 *
> +		 * TODO: Add support for VRR for DP->HDMI 2.1 PCON.
> +		 */
> +		if (drm_dp_is_branch(intel_dp->dpcd))
> +			return false;
>  
>  		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
>  			return false;
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

[PATCH 03/14] drm/i915/dp: Add a helper to decide if AS SDP is needed

[Ankit Nautiyal]

Add a helper to check if AS SDP is needed. Currently AS SDP is only
required when VRR is enabled. However, there are other use cases, along
with the missing case of CMRR, dealt in subsequent changes.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b999d8c085c7..65764ab0bb9b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3111,6 +3111,12 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
 }
 
+static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
+				  struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->vrr.enable;
+}
+
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -3118,7 +3124,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 
-	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
+	if (!intel_dp->as_sdp_supported)
+		return;
+
+	if (!intel_dp_needs_as_sdp(intel_dp, crtc_state))
 		return;
 
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
-- 
2.45.2

Re: [PATCH 03/14] drm/i915/dp: Add a helper to decide if AS SDP is needed

[Ville Syrjälä]

On Mon, Feb 23, 2026 at 07:14:20PM +0530, Ankit Nautiyal wrote:
> Add a helper to check if AS SDP is needed. Currently AS SDP is only
> required when VRR is enabled. However, there are other use cases, along
> with the missing case of CMRR, dealt in subsequent changes.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index b999d8c085c7..65764ab0bb9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3111,6 +3111,12 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>  	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
>  }
>  
> +static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
> +				  struct intel_crtc_state *crtc_state)
> +{
> +	return crtc_state->vrr.enable;

Since we don't support VRR+PCON I don't think we actually
need the AS SDP for VRR.

And I don't think we even have a fastset path for this stuff
(or where is it?) so isn't this already causing fastset
failures for VRR enable/disable? Or maybe we don't have
displays with both VRR and AS SDP support anywhere?

> +}
> +
>  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  				    struct intel_crtc_state *crtc_state)
>  {
> @@ -3118,7 +3124,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
>  
> -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
> +	if (!intel_dp->as_sdp_supported)
> +		return;
> +
> +	if (!intel_dp_needs_as_sdp(intel_dp, crtc_state))
>  		return;
>  
>  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 03/14] drm/i915/dp: Add a helper to decide if AS SDP is needed

[Ville Syrjälä]

On Thu, Feb 26, 2026 at 05:29:48PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 23, 2026 at 07:14:20PM +0530, Ankit Nautiyal wrote:
> > Add a helper to check if AS SDP is needed. Currently AS SDP is only
> > required when VRR is enabled. However, there are other use cases, along
> > with the missing case of CMRR, dealt in subsequent changes.
> > 
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index b999d8c085c7..65764ab0bb9b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3111,6 +3111,12 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> >  	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
> >  }
> >  
> > +static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
> > +				  struct intel_crtc_state *crtc_state)
> > +{
> > +	return crtc_state->vrr.enable;
> 
> Since we don't support VRR+PCON I don't think we actually
> need the AS SDP for VRR.

Hmm. DP 2.1a does say
"When the plugged DP device has DPCD 02214h[0] = 1, a DP Source
 device shall transmit an Adaptive-Sync SDP before enabling an
 Adaptive-Sync video transmission."

So maybe we do need to transmit it whenever the DP device
supports it. In that case someone will probably need to figure
out the fastset stuff.

> 
> And I don't think we even have a fastset path for this stuff
> (or where is it?) so isn't this already causing fastset
> failures for VRR enable/disable? Or maybe we don't have
> displays with both VRR and AS SDP support anywhere?
> 
> > +}
> > +
> >  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> >  				    struct intel_crtc_state *crtc_state)
> >  {
> > @@ -3118,7 +3124,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> >  	const struct drm_display_mode *adjusted_mode =
> >  		&crtc_state->hw.adjusted_mode;
> >  
> > -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
> > +	if (!intel_dp->as_sdp_supported)
> > +		return;
> > +
> > +	if (!intel_dp_needs_as_sdp(intel_dp, crtc_state))
> >  		return;
> >  
> >  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> > -- 
> > 2.45.2
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 03/14] drm/i915/dp: Add a helper to decide if AS SDP is needed

[Nautiyal, Ankit K]

On 2/26/2026 9:31 PM, Ville Syrjälä wrote:
> On Thu, Feb 26, 2026 at 05:29:48PM +0200, Ville Syrjälä wrote:
>> On Mon, Feb 23, 2026 at 07:14:20PM +0530, Ankit Nautiyal wrote:
>>> Add a helper to check if AS SDP is needed. Currently AS SDP is only
>>> required when VRR is enabled. However, there are other use cases, along
>>> with the missing case of CMRR, dealt in subsequent changes.
>>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++++-
>>>   1 file changed, 10 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index b999d8c085c7..65764ab0bb9b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -3111,6 +3111,12 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>>>   	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
>>>   }
>>>   
>>> +static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>>> +				  struct intel_crtc_state *crtc_state)
>>> +{
>>> +	return crtc_state->vrr.enable;
>> Since we don't support VRR+PCON I don't think we actually
>> need the AS SDP for VRR.
> Hmm. DP 2.1a does say
> "When the plugged DP device has DPCD 02214h[0] = 1, a DP Source
>   device shall transmit an Adaptive-Sync SDP before enabling an
>   Adaptive-Sync video transmission."
>
> So maybe we do need to transmit it whenever the DP device
> supports it.

Yeah I think that will be a better way.


> In that case someone will probably need to figure
> out the fastset stuff.

Hmm.. currently we are avoiding checking of AS SDP during fastset.

The fields will change as VRR will get enabled/disabled on the fly, so 
we are avoiding check for fastset.


>
>> And I don't think we even have a fastset path for this stuff
>> (or where is it?) so isn't this already causing fastset
>> failures for VRR enable/disable? Or maybe we don't have
>> displays with both VRR and AS SDP support anywhere?

VRR with AS SDP supported panels are there, (not in CI, but some resume 
machines have them). Till now we didnt see any specific issues.

There is a test kms_vrr@flip-basic-fastset, I will re-check this on such 
a panel.


Regards,

Ankit

>>
>>> +}
>>> +
>>>   static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>>   				    struct intel_crtc_state *crtc_state)
>>>   {
>>> @@ -3118,7 +3124,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>>   	const struct drm_display_mode *adjusted_mode =
>>>   		&crtc_state->hw.adjusted_mode;
>>>   
>>> -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
>>> +	if (!intel_dp->as_sdp_supported)
>>> +		return;
>>> +
>>> +	if (!intel_dp_needs_as_sdp(intel_dp, crtc_state))
>>>   		return;
>>>   
>>>   	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
>>> -- 
>>> 2.45.2
>> -- 
>> Ville Syrjälä
>> Intel

[PATCH 04/14] drm/i915/dp: Update the helper intel_dp_needs_as_sdp() for CMRR

[Ankit Nautiyal]

AS SDP is supported for both VRR (AVT) and CMRR (FAVT). Update the check
to return true when either VRR or CMRR is enabled.

CMRR is currently disabled in i915, so this change has no functional
impact as of now, but it keeps the logic complete and ready for when CMRR
is enabled.

Subsequent changes will handle AS SDP requirements for Panel Replay.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 65764ab0bb9b..5abb56fb26f7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3114,7 +3114,8 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 				  struct intel_crtc_state *crtc_state)
 {
-	return crtc_state->vrr.enable;
+	return crtc_state->vrr.enable ||
+	       crtc_state->cmrr.enable;
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-- 
2.45.2

[PATCH 05/14] include/drm/display/dp: Add field for storing AS SDP version

[Ankit Nautiyal]

Add a new member to store Adaptive Sync SDP version and include it in AS
SDP logs.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 1 +
 include/drm/display/drm_dp_helper.h     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index a697cc227e28..9469943d8194 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -3507,6 +3507,7 @@ void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp
 {
 	drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
 		   as_sdp->revision, as_sdp->length);
+	drm_printf(p, "    version: %d\n", as_sdp->version);
 	drm_printf(p, "    vtotal: %d\n", as_sdp->vtotal);
 	drm_printf(p, "    target_rr: %d\n", as_sdp->target_rr);
 	drm_printf(p, "    duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 1d0acd58f486..c71787fc31c1 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -120,6 +120,7 @@ struct drm_dp_as_sdp {
 	unsigned char sdp_type;
 	unsigned char revision;
 	unsigned char length;
+	int version;
 	int vtotal;
 	int target_rr;
 	int duration_incr_ms;
-- 
2.45.2

Re: [PATCH 05/14] include/drm/display/dp: Add field for storing AS SDP version

[Ville Syrjälä]

On Mon, Feb 23, 2026 at 07:14:22PM +0530, Ankit Nautiyal wrote:
> Add a new member to store Adaptive Sync SDP version and include it in AS
> SDP logs.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/display/drm_dp_helper.c | 1 +
>  include/drm/display/drm_dp_helper.h     | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index a697cc227e28..9469943d8194 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -3507,6 +3507,7 @@ void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp
>  {
>  	drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
>  		   as_sdp->revision, as_sdp->length);
> +	drm_printf(p, "    version: %d\n", as_sdp->version);
>  	drm_printf(p, "    vtotal: %d\n", as_sdp->vtotal);
>  	drm_printf(p, "    target_rr: %d\n", as_sdp->target_rr);
>  	drm_printf(p, "    duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index 1d0acd58f486..c71787fc31c1 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -120,6 +120,7 @@ struct drm_dp_as_sdp {
>  	unsigned char sdp_type;
>  	unsigned char revision;
                      ^^^^^^^^

Isn't that already the thing you're trying to add here?

>  	unsigned char length;
> +	int version;
>  	int vtotal;
>  	int target_rr;
>  	int duration_incr_ms;
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 05/14] include/drm/display/dp: Add field for storing AS SDP version

[Nautiyal, Ankit K]

On 2/26/2026 9:04 PM, Ville Syrjälä wrote:
> On Mon, Feb 23, 2026 at 07:14:22PM +0530, Ankit Nautiyal wrote:
>> Add a new member to store Adaptive Sync SDP version and include it in AS
>> SDP logs.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/display/drm_dp_helper.c | 1 +
>>   include/drm/display/drm_dp_helper.h     | 1 +
>>   2 files changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
>> index a697cc227e28..9469943d8194 100644
>> --- a/drivers/gpu/drm/display/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
>> @@ -3507,6 +3507,7 @@ void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp
>>   {
>>   	drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
>>   		   as_sdp->revision, as_sdp->length);
>> +	drm_printf(p, "    version: %d\n", as_sdp->version);
>>   	drm_printf(p, "    vtotal: %d\n", as_sdp->vtotal);
>>   	drm_printf(p, "    target_rr: %d\n", as_sdp->target_rr);
>>   	drm_printf(p, "    duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
>> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
>> index 1d0acd58f486..c71787fc31c1 100644
>> --- a/include/drm/display/drm_dp_helper.h
>> +++ b/include/drm/display/drm_dp_helper.h
>> @@ -120,6 +120,7 @@ struct drm_dp_as_sdp {
>>   	unsigned char sdp_type;
>>   	unsigned char revision;
>                        ^^^^^^^^
>
> Isn't that already the thing you're trying to add here?

Indeed (face palm). We seem to be not using it.

I will drop this patch and use the existing thing.


Regards,

Ankit


>
>>   	unsigned char length;
>> +	int version;
>>   	int vtotal;
>>   	int target_rr;
>>   	int duration_incr_ms;
>> -- 
>> 2.45.2

[PATCH 06/14] drm/i915/dp: Use version field of AS SDP data structure

[Ankit Nautiyal]

Use the newly added version field of struct drm_dp_as_sdp instead of
current hardcoding.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 drivers/gpu/drm/i915/display/intel_dp.c      | 7 +++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 33821cc2948b..309e28b15198 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4902,7 +4902,8 @@ static bool
 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
 			const struct drm_dp_as_sdp *b)
 {
-	return a->vtotal == b->vtotal &&
+	return a->version == b->version &&
+		a->vtotal == b->vtotal &&
 		a->target_rr == b->target_rr &&
 		a->duration_incr_ms == b->duration_incr_ms &&
 		a->duration_decr_ms == b->duration_decr_ms &&
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5abb56fb26f7..5d173553a646 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3136,6 +3136,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
 	as_sdp->length = 0x9;
 	as_sdp->duration_incr_ms = 0;
+	as_sdp->version = 0x2;
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
 	if (crtc_state->cmrr.enable) {
@@ -5001,7 +5002,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	/* Prepare AS (Adaptive Sync) SDP Header */
 	sdp->sdp_header.HB0 = 0;
 	sdp->sdp_header.HB1 = as_sdp->sdp_type;
-	sdp->sdp_header.HB2 = 0x02;
+	sdp->sdp_header.HB2 = as_sdp->version;
 	sdp->sdp_header.HB3 = as_sdp->length;
 
 	/* Fill AS (Adaptive Sync) SDP Payload */
@@ -5188,13 +5189,11 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
 		return -EINVAL;
 
-	if (sdp->sdp_header.HB2 != 0x02)
-		return -EINVAL;
-
 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
 		return -EINVAL;
 
 	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
+	as_sdp->version = sdp->sdp_header.HB2;
 	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = ((sdp->db[4] & 0x3) << 8) | sdp->db[3];
-- 
2.45.2

[PATCH 07/14] drm/i915/dp: Compute AS SDP after PSR and LOBF

[Ankit Nautiyal]

To enable AS SDP support for Panel Replay (PR) with Link ON and
Auxless-ALPM, we need to compute AS SDP after
intel_{psr, alpm_lobf}_compute_config().

Move call for intel_dp_compute_as_sdp() after the above two helpers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5d173553a646..d08db4938638 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3608,9 +3608,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
 
 	intel_vrr_compute_config(pipe_config, conn_state);
-	intel_dp_compute_as_sdp(intel_dp, pipe_config);
 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
 	intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_as_sdp(intel_dp, pipe_config);
 	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
-- 
2.45.2

[PATCH 08/14] drm/i915/dp: Add AS SDP support for PR with link ON

[Ankit Nautiyal]

Adaptive Sync SDP (AS SDP) is also used for Panel Replay (PR).
For PR with Link ON, the AS SDP version V1 is used. When using
AS SDP Version 1, AS SDP payload and parity bytes are all set to zeroes.

Bspec: 75639
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d08db4938638..5952db6197cf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3115,7 +3115,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 				  struct intel_crtc_state *crtc_state)
 {
 	return crtc_state->vrr.enable ||
-	       crtc_state->cmrr.enable;
+	       crtc_state->cmrr.enable ||
+	       crtc_state->has_panel_replay;
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
@@ -3137,6 +3138,16 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->length = 0x9;
 	as_sdp->duration_incr_ms = 0;
 	as_sdp->version = 0x2;
+
+	if (crtc_state->vrr.enable)
+		as_sdp->version = 0x2;
+	else
+		as_sdp->version = 0x1;
+
+	/* No payload data bytes for Version 1 */
+	if (as_sdp->version == 0x1)
+		return;
+
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
 	if (crtc_state->cmrr.enable) {
@@ -5005,6 +5016,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	sdp->sdp_header.HB2 = as_sdp->version;
 	sdp->sdp_header.HB3 = as_sdp->length;
 
+	/* No Payload Data bytes for Version 1 */
+	if (as_sdp->version == 0x1)
+		return length;
+
 	/* Fill AS (Adaptive Sync) SDP Payload */
 	sdp->db[0] = as_sdp->mode;
 	sdp->db[1] = as_sdp->vtotal & 0xFF;
-- 
2.45.2

Re: [PATCH 08/14] drm/i915/dp: Add AS SDP support for PR with link ON

[Ville Syrjälä]

On Mon, Feb 23, 2026 at 07:14:25PM +0530, Ankit Nautiyal wrote:
> Adaptive Sync SDP (AS SDP) is also used for Panel Replay (PR).
> For PR with Link ON, the AS SDP version V1 is used. When using
> AS SDP Version 1, AS SDP payload and parity bytes are all set to zeroes.

I don't think we should need to transmit any AS SDP in link ON mode.

> 
> Bspec: 75639
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index d08db4938638..5952db6197cf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3115,7 +3115,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>  				  struct intel_crtc_state *crtc_state)
>  {
>  	return crtc_state->vrr.enable ||
> -	       crtc_state->cmrr.enable;
> +	       crtc_state->cmrr.enable ||
> +	       crtc_state->has_panel_replay;
>  }
>  
>  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> @@ -3137,6 +3138,16 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  	as_sdp->length = 0x9;
>  	as_sdp->duration_incr_ms = 0;
>  	as_sdp->version = 0x2;
> +
> +	if (crtc_state->vrr.enable)
> +		as_sdp->version = 0x2;

I think we rather need some versions checks or something to
make sure the device actually supports v2. VRR itself shouldn't
need v2 since the v1 was originally added exactly for VRR+PCON
use cases. PR+ALPM definitely does need v2, but not sure anything
else actually needs it.

> +	else
> +		as_sdp->version = 0x1;
> +
> +	/* No payload data bytes for Version 1 */
> +	if (as_sdp->version == 0x1)
> +		return;
> +
>  	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>  
>  	if (crtc_state->cmrr.enable) {
> @@ -5005,6 +5016,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
>  	sdp->sdp_header.HB2 = as_sdp->version;
>  	sdp->sdp_header.HB3 = as_sdp->length;
>  
> +	/* No Payload Data bytes for Version 1 */
> +	if (as_sdp->version == 0x1)
> +		return length;
> +
>  	/* Fill AS (Adaptive Sync) SDP Payload */
>  	sdp->db[0] = as_sdp->mode;
>  	sdp->db[1] = as_sdp->vtotal & 0xFF;
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 08/14] drm/i915/dp: Add AS SDP support for PR with link ON

[Ville Syrjälä]

On Thu, Feb 26, 2026 at 06:10:34PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 23, 2026 at 07:14:25PM +0530, Ankit Nautiyal wrote:
> > Adaptive Sync SDP (AS SDP) is also used for Panel Replay (PR).
> > For PR with Link ON, the AS SDP version V1 is used. When using
> > AS SDP Version 1, AS SDP payload and parity bytes are all set to zeroes.
> 
> I don't think we should need to transmit any AS SDP in link ON mode.

Hmm, maybe we do. While the DP spec is is extremely confusing here
(mostly just talking about the ALPM+AS SDP combo and ignoring the
link ON case), I think what it might be hinting at is that the sink
tells us whether it needs the AS SDP, via
ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR.

> 
> > 
> > Bspec: 75639
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++++++++++-
> >  1 file changed, 16 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index d08db4938638..5952db6197cf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3115,7 +3115,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
> >  				  struct intel_crtc_state *crtc_state)
> >  {
> >  	return crtc_state->vrr.enable ||
> > -	       crtc_state->cmrr.enable;
> > +	       crtc_state->cmrr.enable ||
> > +	       crtc_state->has_panel_replay;
> >  }
> >  
> >  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> > @@ -3137,6 +3138,16 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> >  	as_sdp->length = 0x9;
> >  	as_sdp->duration_incr_ms = 0;
> >  	as_sdp->version = 0x2;
> > +
> > +	if (crtc_state->vrr.enable)
> > +		as_sdp->version = 0x2;
> 
> I think we rather need some versions checks or something to
> make sure the device actually supports v2. VRR itself shouldn't
> need v2 since the v1 was originally added exactly for VRR+PCON
> use cases. PR+ALPM definitely does need v2, but not sure anything
> else actually needs it.
> 
> > +	else
> > +		as_sdp->version = 0x1;
> > +
> > +	/* No payload data bytes for Version 1 */
> > +	if (as_sdp->version == 0x1)
> > +		return;
> > +
> >  	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
> >  
> >  	if (crtc_state->cmrr.enable) {
> > @@ -5005,6 +5016,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
> >  	sdp->sdp_header.HB2 = as_sdp->version;
> >  	sdp->sdp_header.HB3 = as_sdp->length;
> >  
> > +	/* No Payload Data bytes for Version 1 */
> > +	if (as_sdp->version == 0x1)
> > +		return length;
> > +
> >  	/* Fill AS (Adaptive Sync) SDP Payload */
> >  	sdp->db[0] = as_sdp->mode;
> >  	sdp->db[1] = as_sdp->vtotal & 0xFF;
> > -- 
> > 2.45.2
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 08/14] drm/i915/dp: Add AS SDP support for PR with link ON

[Hogander, Jouni]

On Fri, 2026-02-27 at 06:37 +0200, Ville Syrjälä wrote:
> On Thu, Feb 26, 2026 at 06:10:34PM +0200, Ville Syrjälä wrote:
> > On Mon, Feb 23, 2026 at 07:14:25PM +0530, Ankit Nautiyal wrote:
> > > Adaptive Sync SDP (AS SDP) is also used for Panel Replay (PR).
> > > For PR with Link ON, the AS SDP version V1 is used. When using
> > > AS SDP Version 1, AS SDP payload and parity bytes are all set to
> > > zeroes.
> > 
> > I don't think we should need to transmit any AS SDP in link ON
> > mode.
> 
> Hmm, maybe we do. While the DP spec is is extremely confusing here
> (mostly just talking about the ALPM+AS SDP combo and ignoring the
> link ON case), I think what it might be hinting at is that the sink
> tells us whether it needs the AS SDP, via
> ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR.

This sounds reasonable. It seems I have been reading only the mention
"Source device may choose to disable Adaptive-Sync SDP transmission
during a PR Active state." There is also a note saying in case of eDP
this should be 0 always.

Maybe instead of just checking Panel Replay we could add a helper
checking this bit and use that as a enabler for AS SDP? Unless we are
enabling AS SDP always when supported.

BR,
Jouni Högander

> 
> > 
> > > 
> > > Bspec: 75639
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++++++++++-
> > >  1 file changed, 16 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index d08db4938638..5952db6197cf 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -3115,7 +3115,8 @@ static bool intel_dp_needs_as_sdp(struct
> > > intel_dp *intel_dp,
> > >  				  struct intel_crtc_state
> > > *crtc_state)
> > >  {
> > >  	return crtc_state->vrr.enable ||
> > > -	       crtc_state->cmrr.enable;
> > > +	       crtc_state->cmrr.enable ||
> > > +	       crtc_state->has_panel_replay;
> > >  }
> > >  
> > >  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> > > @@ -3137,6 +3138,16 @@ static void intel_dp_compute_as_sdp(struct
> > > intel_dp *intel_dp,
> > >  	as_sdp->length = 0x9;
> > >  	as_sdp->duration_incr_ms = 0;
> > >  	as_sdp->version = 0x2;
> > > +
> > > +	if (crtc_state->vrr.enable)
> > > +		as_sdp->version = 0x2;
> > 
> > I think we rather need some versions checks or something to
> > make sure the device actually supports v2. VRR itself shouldn't
> > need v2 since the v1 was originally added exactly for VRR+PCON
> > use cases. PR+ALPM definitely does need v2, but not sure anything
> > else actually needs it.
> > 
> > > +	else
> > > +		as_sdp->version = 0x1;
> > > +
> > > +	/* No payload data bytes for Version 1 */
> > > +	if (as_sdp->version == 0x1)
> > > +		return;
> > > +
> > >  	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
> > >  
> > >  	if (crtc_state->cmrr.enable) {
> > > @@ -5005,6 +5016,10 @@ static ssize_t intel_dp_as_sdp_pack(const
> > > struct drm_dp_as_sdp *as_sdp,
> > >  	sdp->sdp_header.HB2 = as_sdp->version;
> > >  	sdp->sdp_header.HB3 = as_sdp->length;
> > >  
> > > +	/* No Payload Data bytes for Version 1 */
> > > +	if (as_sdp->version == 0x1)
> > > +		return length;
> > > +
> > >  	/* Fill AS (Adaptive Sync) SDP Payload */
> > >  	sdp->db[0] = as_sdp->mode;
> > >  	sdp->db[1] = as_sdp->vtotal & 0xFF;
> > > -- 
> > > 2.45.2
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 

Re: [PATCH 08/14] drm/i915/dp: Add AS SDP support for PR with link ON

[Ville Syrjälä]

On Fri, Feb 27, 2026 at 06:37:37AM +0200, Ville Syrjälä wrote:
> On Thu, Feb 26, 2026 at 06:10:34PM +0200, Ville Syrjälä wrote:
> > On Mon, Feb 23, 2026 at 07:14:25PM +0530, Ankit Nautiyal wrote:
> > > Adaptive Sync SDP (AS SDP) is also used for Panel Replay (PR).
> > > For PR with Link ON, the AS SDP version V1 is used. When using
> > > AS SDP Version 1, AS SDP payload and parity bytes are all set to zeroes.
> > 
> > I don't think we should need to transmit any AS SDP in link ON mode.
> 
> Hmm, maybe we do. While the DP spec is is extremely confusing here
> (mostly just talking about the ALPM+AS SDP combo and ignoring the
> link ON case), I think what it might be hinting at is that the sink
> tells us whether it needs the AS SDP, via
> ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR.

Actually no. It looks to me like with the link ON, the source is still
transmitting the BS/BE at the expected locations so the sink remains
synced to the source video timings, and thus the AS SDP is not needed
for that.

> 
> > 
> > > 
> > > Bspec: 75639
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++++++++++-
> > >  1 file changed, 16 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index d08db4938638..5952db6197cf 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -3115,7 +3115,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
> > >  				  struct intel_crtc_state *crtc_state)
> > >  {
> > >  	return crtc_state->vrr.enable ||
> > > -	       crtc_state->cmrr.enable;
> > > +	       crtc_state->cmrr.enable ||
> > > +	       crtc_state->has_panel_replay;
> > >  }
> > >  
> > >  static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> > > @@ -3137,6 +3138,16 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> > >  	as_sdp->length = 0x9;
> > >  	as_sdp->duration_incr_ms = 0;
> > >  	as_sdp->version = 0x2;
> > > +
> > > +	if (crtc_state->vrr.enable)
> > > +		as_sdp->version = 0x2;
> > 
> > I think we rather need some versions checks or something to
> > make sure the device actually supports v2. VRR itself shouldn't
> > need v2 since the v1 was originally added exactly for VRR+PCON
> > use cases. PR+ALPM definitely does need v2, but not sure anything
> > else actually needs it.
> > 
> > > +	else
> > > +		as_sdp->version = 0x1;
> > > +
> > > +	/* No payload data bytes for Version 1 */
> > > +	if (as_sdp->version == 0x1)
> > > +		return;
> > > +
> > >  	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
> > >  
> > >  	if (crtc_state->cmrr.enable) {
> > > @@ -5005,6 +5016,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
> > >  	sdp->sdp_header.HB2 = as_sdp->version;
> > >  	sdp->sdp_header.HB3 = as_sdp->length;
> > >  
> > > +	/* No Payload Data bytes for Version 1 */
> > > +	if (as_sdp->version == 0x1)
> > > +		return length;
> > > +
> > >  	/* Fill AS (Adaptive Sync) SDP Payload */
> > >  	sdp->db[0] = as_sdp->mode;
> > >  	sdp->db[1] = as_sdp->vtotal & 0xFF;
> > > -- 
> > > 2.45.2
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> -- 
> Ville Syrjälä
> Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 08/14] drm/i915/dp: Add AS SDP support for PR with link ON

[Nautiyal, Ankit K]

On 2/27/2026 11:19 AM, Ville Syrjälä wrote:
> On Fri, Feb 27, 2026 at 06:37:37AM +0200, Ville Syrjälä wrote:
>> On Thu, Feb 26, 2026 at 06:10:34PM +0200, Ville Syrjälä wrote:
>>> On Mon, Feb 23, 2026 at 07:14:25PM +0530, Ankit Nautiyal wrote:
>>>> Adaptive Sync SDP (AS SDP) is also used for Panel Replay (PR).
>>>> For PR with Link ON, the AS SDP version V1 is used. When using
>>>> AS SDP Version 1, AS SDP payload and parity bytes are all set to zeroes.
>>> I don't think we should need to transmit any AS SDP in link ON mode.
>> Hmm, maybe we do. While the DP spec is is extremely confusing here
>> (mostly just talking about the ALPM+AS SDP combo and ignoring the
>> link ON case), I think what it might be hinting at is that the sink
>> tells us whether it needs the AS SDP, via
>> ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR.
> Actually no. It looks to me like with the link ON, the source is still
> transmitting the BS/BE at the expected locations so the sink remains
> synced to the source video timings, and thus the AS SDP is not needed
> for that.

Yeah the spec does not say if its needed for PR with Link ON.

What I gather from different portions of the spec is that we can send 
the AS SDP with PR with Link ON.

The version 1 thing :  This is coming from Bspec: 75639

Whole thing is a bit confusing. As I have also mentioned in the 
cover-letter, I am inclined to always send AS SDP if its supported from 
both source and sink.

That way while computing optimized the guardband we will account for the 
Transmission Line conditions (for AS SDP) wrt the guardband.

Without this, if there is VRR enabled in between, we need to enable it 
and account it on the fly which will trigger full modeset.

So in all, I mean:

Always enable AS SDP if supported.

For PR with Link ON -> use version 1 (as per Bspec 75639)

For PR with Auxless ALPM -> use version 2. ( For disabling AS SDP during 
PR active, there are provisions to write into PR_ALPM_CTL[AS SDP 
Transmission in Active Disable])


Regards,

Ankit

>>>> Bspec: 75639
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++++++++++-
>>>>   1 file changed, 16 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index d08db4938638..5952db6197cf 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -3115,7 +3115,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>>>>   				  struct intel_crtc_state *crtc_state)
>>>>   {
>>>>   	return crtc_state->vrr.enable ||
>>>> -	       crtc_state->cmrr.enable;
>>>> +	       crtc_state->cmrr.enable ||
>>>> +	       crtc_state->has_panel_replay;
>>>>   }
>>>>   
>>>>   static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>>> @@ -3137,6 +3138,16 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>>>   	as_sdp->length = 0x9;
>>>>   	as_sdp->duration_incr_ms = 0;
>>>>   	as_sdp->version = 0x2;
>>>> +
>>>> +	if (crtc_state->vrr.enable)
>>>> +		as_sdp->version = 0x2;
>>> I think we rather need some versions checks or something to
>>> make sure the device actually supports v2. VRR itself shouldn't
>>> need v2 since the v1 was originally added exactly for VRR+PCON
>>> use cases. PR+ALPM definitely does need v2, but not sure anything
>>> else actually needs it.
>>>
>>>> +	else
>>>> +		as_sdp->version = 0x1;
>>>> +
>>>> +	/* No payload data bytes for Version 1 */
>>>> +	if (as_sdp->version == 0x1)
>>>> +		return;
>>>> +
>>>>   	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
>>>>   
>>>>   	if (crtc_state->cmrr.enable) {
>>>> @@ -5005,6 +5016,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
>>>>   	sdp->sdp_header.HB2 = as_sdp->version;
>>>>   	sdp->sdp_header.HB3 = as_sdp->length;
>>>>   
>>>> +	/* No Payload Data bytes for Version 1 */
>>>> +	if (as_sdp->version == 0x1)
>>>> +		return length;
>>>> +
>>>>   	/* Fill AS (Adaptive Sync) SDP Payload */
>>>>   	sdp->db[0] = as_sdp->mode;
>>>>   	sdp->db[1] = as_sdp->vtotal & 0xFF;
>>>> -- 
>>>> 2.45.2
>>> -- 
>>> Ville Syrjälä
>>> Intel
>> -- 
>> Ville Syrjälä
>> Intel

[PATCH 09/14] drm/i915/psr: Add helper to check if PR is with link OFF

[Ankit Nautiyal]

Introduce a helper intel_psr_is_pr_with_link_off() to check if the Panel
Replay feature needs to be enabled with link off.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
 drivers/gpu/drm/i915/display/intel_psr.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5bea2eda744b..e0e6ddbfaa2d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4575,3 +4575,9 @@ bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state)
 
 	return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr;
 }
+
+bool intel_psr_is_pr_with_link_off(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->has_panel_replay &&
+		crtc_state->link_off_after_as_sdp_when_pr_active;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 394b641840b3..6764bcb13f9b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -86,5 +86,6 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *crtc_state);
 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
 bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state);
+bool intel_psr_is_pr_with_link_off(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.45.2

Re: [PATCH 09/14] drm/i915/psr: Add helper to check if PR is with link OFF

[Ville Syrjälä]

On Mon, Feb 23, 2026 at 07:14:26PM +0530, Ankit Nautiyal wrote:
> Introduce a helper intel_psr_is_pr_with_link_off() to check if the Panel
> Replay feature needs to be enabled with link off.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
>  drivers/gpu/drm/i915/display/intel_psr.h | 1 +
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5bea2eda744b..e0e6ddbfaa2d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -4575,3 +4575,9 @@ bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state)
>  
>  	return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr;
>  }
> +
> +bool intel_psr_is_pr_with_link_off(const struct intel_crtc_state *crtc_state)
> +{
> +	return crtc_state->has_panel_replay &&
> +		crtc_state->link_off_after_as_sdp_when_pr_active;

I don't think that flag has anything to do with what you're
trying to determine here.

> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 394b641840b3..6764bcb13f9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -86,5 +86,6 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>  				   struct intel_crtc_state *crtc_state);
>  int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
>  bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state);
> +bool intel_psr_is_pr_with_link_off(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_PSR_H__ */
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 09/14] drm/i915/psr: Add helper to check if PR is with link OFF

[Nautiyal, Ankit K]

On 2/26/2026 9:42 PM, Ville Syrjälä wrote:
> On Mon, Feb 23, 2026 at 07:14:26PM +0530, Ankit Nautiyal wrote:
>> Introduce a helper intel_psr_is_pr_with_link_off() to check if the Panel
>> Replay feature needs to be enabled with link off.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
>>   drivers/gpu/drm/i915/display/intel_psr.h | 1 +
>>   2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 5bea2eda744b..e0e6ddbfaa2d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -4575,3 +4575,9 @@ bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state)
>>   
>>   	return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr;
>>   }
>> +
>> +bool intel_psr_is_pr_with_link_off(const struct intel_crtc_state *crtc_state)
>> +{
>> +	return crtc_state->has_panel_replay &&
>> +		crtc_state->link_off_after_as_sdp_when_pr_active;
> I don't think that flag has anything to do with what you're
> trying to determine here.

You are right this is not the thing I wanted.

The source can use Auxless ALPM to turn off main link without this bit.

I am still looking for flag that can help to determine Auxless ALPM with 
Link Off.


Regards,

Ankit

>
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
>> index 394b641840b3..6764bcb13f9b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>> @@ -86,5 +86,6 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>>   				   struct intel_crtc_state *crtc_state);
>>   int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
>>   bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state);
>> +bool intel_psr_is_pr_with_link_off(const struct intel_crtc_state *crtc_state);
>>   
>>   #endif /* __INTEL_PSR_H__ */
>> -- 
>> 2.45.2

[PATCH 10/14] drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPM

[Ankit Nautiyal]

To support Panel Replay with Auxless-ALPM, the source must transmit
Adaptive-Sync SDPs for video timing synchronization while PR is active.
As per the DP spec v2.1, this requires setting DPCD 0x0107[6]
(FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether VRR is enabled
(AVT/FAVT) or fixed-timing mode is used.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 ++++++++--
 drivers/gpu/drm/i915/display/intel_dp_link_training.h |  3 ++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c           |  2 +-
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 54c585c59b90..e494e005cc0f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -36,6 +36,7 @@
 #include "intel_encoder.h"
 #include "intel_hotplug.h"
 #include "intel_panel.h"
+#include "intel_psr.h"
 
 #define LT_MSG_PREFIX			"[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] "
 #define LT_MSG_ARGS(_intel_dp, _dp_phy)	(_intel_dp)->attached_connector->base.base.id, \
@@ -710,11 +711,14 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
 	return true;
 }
 
-void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
+void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate,
+				     bool is_vrr,
+				     bool is_pr_with_link_off)
 {
 	u8 link_config[2];
 
 	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
+	link_config[0] |= is_pr_with_link_off ? DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE : 0;
 	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
 			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
@@ -737,7 +741,9 @@ static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 	  * especially on the first real commit when clearing the inherited flag.
 	  */
 	intel_dp_link_training_set_mode(intel_dp,
-					crtc_state->port_clock, crtc_state->vrr.in_range);
+					crtc_state->port_clock,
+					crtc_state->vrr.in_range,
+					intel_psr_is_pr_with_link_off(crtc_state));
 }
 
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 1ba22ed6db08..3591210f8ee6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -18,7 +18,8 @@ int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
 bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp);
 
 void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
-				     int link_rate, bool is_vrr);
+				     int link_rate, bool is_vrr,
+				     bool is_pr_with_link_off);
 void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 				   int link_bw, int rate_select, int lane_count,
 				   bool enhanced_framing);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index fb5396a46d1b..3b4256b8e030 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -2139,7 +2139,7 @@ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
 
 	intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select);
 
-	intel_dp_link_training_set_mode(intel_dp, link_rate, false);
+	intel_dp_link_training_set_mode(intel_dp, link_rate, false, false);
 	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count,
 				      drm_dp_enhanced_frame_cap(intel_dp->dpcd));
 
-- 
2.45.2

[PATCH 11/14] drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off

[Ankit Nautiyal]

For Panel Replay with AUX-less ALPM (link-off PR), the source must send
Adaptive-Sync SDP v2. Program DB[1:0] per DP spec v2.1:
- VRR AVT: 00b (variable VTotal)
- VRR FAVT: 10b/11b (TRR not reached/reached)
- Fixed timing with PR link-off (VRR off): 01b (AS disabled; VTotal fixed)

Select SDP version v2 whenever PR link-off or VRR is active, otherwise v1,
and program the AS SDP DB[1:0] bits.

Also, drop the redundant target_rr assignment.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5952db6197cf..ad2aceb526ff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3139,7 +3139,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->duration_incr_ms = 0;
 	as_sdp->version = 0x2;
 
-	if (crtc_state->vrr.enable)
+	if (crtc_state->vrr.enable || intel_psr_is_pr_with_link_off(crtc_state))
 		as_sdp->version = 0x2;
 	else
 		as_sdp->version = 0x1;
@@ -3154,9 +3154,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 		as_sdp->target_rr_divider = true;
-	} else {
+	} else if (crtc_state->vrr.enable) {
 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-		as_sdp->target_rr = 0;
+	} else if (intel_psr_is_pr_with_link_off(crtc_state)) {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
 	}
 }
 
-- 
2.45.2

Re: [PATCH 11/14] drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off

[Ville Syrjälä]

On Mon, Feb 23, 2026 at 07:14:28PM +0530, Ankit Nautiyal wrote:
> For Panel Replay with AUX-less ALPM (link-off PR), the source must send
> Adaptive-Sync SDP v2. Program DB[1:0] per DP spec v2.1:
> - VRR AVT: 00b (variable VTotal)
> - VRR FAVT: 10b/11b (TRR not reached/reached)
> - Fixed timing with PR link-off (VRR off): 01b (AS disabled; VTotal fixed)
> 
> Select SDP version v2 whenever PR link-off or VRR is active, otherwise v1,
> and program the AS SDP DB[1:0] bits.
> 
> Also, drop the redundant target_rr assignment.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5952db6197cf..ad2aceb526ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3139,7 +3139,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  	as_sdp->duration_incr_ms = 0;
>  	as_sdp->version = 0x2;
>  
> -	if (crtc_state->vrr.enable)
> +	if (crtc_state->vrr.enable || intel_psr_is_pr_with_link_off(crtc_state))
>  		as_sdp->version = 0x2;
>  	else
>  		as_sdp->version = 0x1;
> @@ -3154,9 +3154,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>  		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>  		as_sdp->target_rr_divider = true;
> -	} else {
> +	} else if (crtc_state->vrr.enable) {
>  		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
> -		as_sdp->target_rr = 0;
> +	} else if (intel_psr_is_pr_with_link_off(crtc_state)) {
> +		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>  	}
 else {
  what now?
 }
>  }
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/14] drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off

[Nautiyal, Ankit K]

On 2/26/2026 9:44 PM, Ville Syrjälä wrote:
> On Mon, Feb 23, 2026 at 07:14:28PM +0530, Ankit Nautiyal wrote:
>> For Panel Replay with AUX-less ALPM (link-off PR), the source must send
>> Adaptive-Sync SDP v2. Program DB[1:0] per DP spec v2.1:
>> - VRR AVT: 00b (variable VTotal)
>> - VRR FAVT: 10b/11b (TRR not reached/reached)
>> - Fixed timing with PR link-off (VRR off): 01b (AS disabled; VTotal fixed)
>>
>> Select SDP version v2 whenever PR link-off or VRR is active, otherwise v1,
>> and program the AS SDP DB[1:0] bits.
>>
>> Also, drop the redundant target_rr assignment.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
>>   1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 5952db6197cf..ad2aceb526ff 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -3139,7 +3139,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>   	as_sdp->duration_incr_ms = 0;
>>   	as_sdp->version = 0x2;
>>   
>> -	if (crtc_state->vrr.enable)
>> +	if (crtc_state->vrr.enable || intel_psr_is_pr_with_link_off(crtc_state))
>>   		as_sdp->version = 0x2;
>>   	else
>>   		as_sdp->version = 0x1;
>> @@ -3154,9 +3154,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>   		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>>   		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>>   		as_sdp->target_rr_divider = true;
>> -	} else {
>> +	} else if (crtc_state->vrr.enable) {
>>   		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
>> -		as_sdp->target_rr = 0;
>> +	} else if (intel_psr_is_pr_with_link_off(crtc_state)) {
>> +		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>>   	}
>   else {
>    what now?
>   }

Hmm I think with always enable AS SDP the else part would naturally become:

as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;


Regards,
Ankit


>>   }
>>   
>> -- 
>> 2.45.2

[PATCH 12/14] include/drm/display/dp: Add DPCD registers for configuring Panel Replay + VRR

[Ankit Nautiyal]

Add additional DPCDs required to be configured to support VRR with Panel
Replay. These DPCDs are specifically required for configuring Adaptive Sync
SDP and are introduced in DP v2.1.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e4eebabab975..e63705415647 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -773,6 +773,15 @@
 # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
 # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
 
+#define PANEL_REPLAY_CONFIG3				0x11a	/* DP 2.1 */
+# define AS_SDP_SETUP_TIME_MASK				(3 << 6)
+# define AS_SDP_SETUP_TIME_T1				0
+# define AS_SDP_SETUP_TIME_DYNAMIC			1	/* uses Table 2-227 */
+# define AS_SDP_SETUP_TIME_T2				2
+
+#define AS_SDP_TRANSMISSION_TIMIING_CONFIG	0x11b	/* DP 2.1 */
+# define AS_SDP_ONE_LINE_EARLIER_ENABLE		BIT(7)
+
 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
-- 
2.45.2

Re: [PATCH 12/14] include/drm/display/dp: Add DPCD registers for configuring Panel Replay + VRR

[Ville Syrjälä]

On Mon, Feb 23, 2026 at 07:14:29PM +0530, Ankit Nautiyal wrote:
> Add additional DPCDs required to be configured to support VRR with Panel
> Replay. These DPCDs are specifically required for configuring Adaptive Sync
> SDP and are introduced in DP v2.1.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  include/drm/display/drm_dp.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index e4eebabab975..e63705415647 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -773,6 +773,15 @@
>  # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)
>  # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)
>  
> +#define PANEL_REPLAY_CONFIG3				0x11a	/* DP 2.1 */
> +# define AS_SDP_SETUP_TIME_MASK				(3 << 6)
> +# define AS_SDP_SETUP_TIME_T1				0
> +# define AS_SDP_SETUP_TIME_DYNAMIC			1	/* uses Table 2-227 */
                                                                        ^^^^^^^^^^^

That reference is likely very DP spec version specific.

> +# define AS_SDP_SETUP_TIME_T2				2

Missing the shift on the values.

> +
> +#define AS_SDP_TRANSMISSION_TIMIING_CONFIG	0x11b	/* DP 2.1 */
> +# define AS_SDP_ONE_LINE_EARLIER_ENABLE		BIT(7)
> +
>  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

[PATCH 13/14] drm/i915/display: Add member to store AS SDP transmission time

[Ankit Nautiyal]

AS SDP can be sent at two different positions T1 and T2.
These depend on the Panel Replay configuration and Adaptive Sync SDP
modes as per DP v2.1.
Currently we have configurations where SDP needs to be sent at T1 only.
However, to make way for supporting more PR and AS SDP configurations,
add a new member to store AS SDP transmission time in crtc_state.

This is filled with T1 for now during panel_replay_compute_config() and
is used to set the MMIO register PR_ALPM and DPCD Panel_Replay_Config3
DPCD offsets.

readout for this new member needs to be added along with other related
members.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 21 ++++++++++++++++++-
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  7 +++++++
 3 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index b3334bc4d0f9..6eecd5ce4fad 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -365,6 +365,25 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	crtc_state->has_lobf = true;
 }
 
+static int get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	switch (crtc_state->pr_as_sdp_transmission) {
+	case AS_SDP_SETUP_TIME_T1:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+	case AS_SDP_SETUP_TIME_DYNAMIC:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
+	case AS_SDP_SETUP_TIME_T2:
+		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
+	default:
+		drm_dbg_kms(display->drm,
+			    "Missing case %d for AS SDP Position, going with T1 by default\n",
+			    crtc_state->pr_as_sdp_transmission);
+		return AS_SDP_SETUP_TIME_T1;
+	}
+}
+
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			       const struct intel_crtc_state *crtc_state)
 {
@@ -388,7 +407,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
 
 		if (intel_dp->as_sdp_supported) {
-			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
+			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
 
 			if (crtc_state->link_off_after_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e8e4af03a6a6..9065bf8bd6a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1181,6 +1181,7 @@ struct intel_crtc_state {
 	bool has_panel_replay;
 	bool link_off_after_as_sdp_when_pr_active;
 	bool disable_as_sdp_when_pr_active;
+	int pr_as_sdp_transmission;
 	bool wm_level_disabled;
 	bool pkg_c_latency_used;
 	/* Only used for state verification. */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e0e6ddbfaa2d..74242c93db87 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -779,6 +779,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
 		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
 	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
+	u8 panel_replay_config3 = crtc_state->pr_as_sdp_transmission;
 
 	if (crtc_state->has_sel_update)
 		val |= DP_PANEL_REPLAY_SU_ENABLE;
@@ -794,6 +795,9 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
 
 	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
 			   panel_replay_config2);
+
+	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3,
+			   panel_replay_config3);
 }
 
 static void _psr_enable_sink(struct intel_dp *intel_dp,
@@ -1771,6 +1775,9 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
 	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
 	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
 
+	/* For now we use T1 as the transmission time */
+	crtc_state->pr_as_sdp_transmission = AS_SDP_SETUP_TIME_T1;
+
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
 
-- 
2.45.2

Re: [PATCH 13/14] drm/i915/display: Add member to store AS SDP transmission time

[Ville Syrjälä]

On Mon, Feb 23, 2026 at 07:14:30PM +0530, Ankit Nautiyal wrote:
> AS SDP can be sent at two different positions T1 and T2.
> These depend on the Panel Replay configuration and Adaptive Sync SDP
> modes as per DP v2.1.
> Currently we have configurations where SDP needs to be sent at T1 only.
> However, to make way for supporting more PR and AS SDP configurations,
> add a new member to store AS SDP transmission time in crtc_state.
> 
> This is filled with T1 for now during panel_replay_compute_config() and
> is used to set the MMIO register PR_ALPM and DPCD Panel_Replay_Config3
> DPCD offsets.
> 
> readout for this new member needs to be added along with other related
> members.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     | 21 ++++++++++++++++++-
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      |  7 +++++++
>  3 files changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index b3334bc4d0f9..6eecd5ce4fad 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -365,6 +365,25 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
>  	crtc_state->has_lobf = true;
>  }
>  
> +static int get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	switch (crtc_state->pr_as_sdp_transmission) {
> +	case AS_SDP_SETUP_TIME_T1:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +	case AS_SDP_SETUP_TIME_DYNAMIC:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
> +	case AS_SDP_SETUP_TIME_T2:
> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
> +	default:
> +		drm_dbg_kms(display->drm,
> +			    "Missing case %d for AS SDP Position, going with T1 by default\n",
> +			    crtc_state->pr_as_sdp_transmission);

MISSING_CASE()

There's no point in adding eloquent debug messages/etc into dead code.

> +		return AS_SDP_SETUP_TIME_T1;
> +	}
> +}
> +
>  static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			       const struct intel_crtc_state *crtc_state)
>  {
> @@ -388,7 +407,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>  
>  		if (intel_dp->as_sdp_supported) {
> -			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
> +			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
>  
>  			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>  				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e8e4af03a6a6..9065bf8bd6a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1181,6 +1181,7 @@ struct intel_crtc_state {
>  	bool has_panel_replay;
>  	bool link_off_after_as_sdp_when_pr_active;
>  	bool disable_as_sdp_when_pr_active;
> +	int pr_as_sdp_transmission;

I don't see much point of adding that if you only ever set
it to one fixed value. Though I suppose the point was to make
sure the DPCD and PR_ALPM_CTL register values stay in sync.
We could also achieve that by replacing that crtc_state member
with eg. just a simple function.

>  	bool wm_level_disabled;
>  	bool pkg_c_latency_used;
>  	/* Only used for state verification. */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index e0e6ddbfaa2d..74242c93db87 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -779,6 +779,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>  		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
>  		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
>  	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
> +	u8 panel_replay_config3 = crtc_state->pr_as_sdp_transmission;
>  
>  	if (crtc_state->has_sel_update)
>  		val |= DP_PANEL_REPLAY_SU_ENABLE;
> @@ -794,6 +795,9 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>  
>  	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
>  			   panel_replay_config2);
> +
> +	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3,
> +			   panel_replay_config3);

This is starting to look like someone should make this a burst write.

>  }
>  
>  static void _psr_enable_sink(struct intel_dp *intel_dp,
> @@ -1771,6 +1775,9 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
>  	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
>  	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
>  
> +	/* For now we use T1 as the transmission time */
> +	crtc_state->pr_as_sdp_transmission = AS_SDP_SETUP_TIME_T1;
> +
>  	if (!intel_dp_is_edp(intel_dp))
>  		return true;
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 13/14] drm/i915/display: Add member to store AS SDP transmission time

[Nautiyal, Ankit K]

On 2/26/2026 10:30 PM, Ville Syrjälä wrote:
> On Mon, Feb 23, 2026 at 07:14:30PM +0530, Ankit Nautiyal wrote:
>> AS SDP can be sent at two different positions T1 and T2.
>> These depend on the Panel Replay configuration and Adaptive Sync SDP
>> modes as per DP v2.1.
>> Currently we have configurations where SDP needs to be sent at T1 only.
>> However, to make way for supporting more PR and AS SDP configurations,
>> add a new member to store AS SDP transmission time in crtc_state.
>>
>> This is filled with T1 for now during panel_replay_compute_config() and
>> is used to set the MMIO register PR_ALPM and DPCD Panel_Replay_Config3
>> DPCD offsets.
>>
>> readout for this new member needs to be added along with other related
>> members.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_alpm.c     | 21 ++++++++++++++++++-
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_psr.c      |  7 +++++++
>>   3 files changed, 28 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
>> index b3334bc4d0f9..6eecd5ce4fad 100644
>> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
>> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
>> @@ -365,6 +365,25 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
>>   	crtc_state->has_lobf = true;
>>   }
>>   
>> +static int get_pr_alpm_as_sdp_transmission_time(const struct intel_crtc_state *crtc_state)
>> +{
>> +	struct intel_display *display = to_intel_display(crtc_state);
>> +
>> +	switch (crtc_state->pr_as_sdp_transmission) {
>> +	case AS_SDP_SETUP_TIME_T1:
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>> +	case AS_SDP_SETUP_TIME_DYNAMIC:
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2;
>> +	case AS_SDP_SETUP_TIME_T2:
>> +		return PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2;
>> +	default:
>> +		drm_dbg_kms(display->drm,
>> +			    "Missing case %d for AS SDP Position, going with T1 by default\n",
>> +			    crtc_state->pr_as_sdp_transmission);
> MISSING_CASE()
>
> There's no point in adding eloquent debug messages/etc into dead code.

Roger that. I think we were avoiding MISSING_CASE() some time back 
during transitioning to struct display, but that was long back.

Will use MISSING_CASE() here.


>
>> +		return AS_SDP_SETUP_TIME_T1;
>> +	}
>> +}
>> +
>>   static void lnl_alpm_configure(struct intel_dp *intel_dp,
>>   			       const struct intel_crtc_state *crtc_state)
>>   {
>> @@ -388,7 +407,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>>   			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
>>   
>>   		if (intel_dp->as_sdp_supported) {
>> -			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;
>> +			u32 pr_alpm_ctl = get_pr_alpm_as_sdp_transmission_time(crtc_state);
>>   
>>   			if (crtc_state->link_off_after_as_sdp_when_pr_active)
>>   				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index e8e4af03a6a6..9065bf8bd6a5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1181,6 +1181,7 @@ struct intel_crtc_state {
>>   	bool has_panel_replay;
>>   	bool link_off_after_as_sdp_when_pr_active;
>>   	bool disable_as_sdp_when_pr_active;
>> +	int pr_as_sdp_transmission;
> I don't see much point of adding that if you only ever set
> it to one fixed value. Though I suppose the point was to make
> sure the DPCD and PR_ALPM_CTL register values stay in sync.
> We could also achieve that by replacing that crtc_state member
> with eg. just a simple function.

The idea was to get this computed in compute_config phase. Currently 
this is a fixed value T1, but if we ever want to change (e.g. 
dynamically change to t2) we might need to store it and perhaps will be 
used to configure other things.

But all this is premature optimization and as you said, we could just 
have a simple function.

>
>>   	bool wm_level_disabled;
>>   	bool pkg_c_latency_used;
>>   	/* Only used for state verification. */
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index e0e6ddbfaa2d..74242c93db87 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -779,6 +779,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>>   		DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
>>   		DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
>>   	u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
>> +	u8 panel_replay_config3 = crtc_state->pr_as_sdp_transmission;
>>   
>>   	if (crtc_state->has_sel_update)
>>   		val |= DP_PANEL_REPLAY_SU_ENABLE;
>> @@ -794,6 +795,9 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
>>   
>>   	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
>>   			   panel_replay_config2);
>> +
>> +	drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3,
>> +			   panel_replay_config3);
> This is starting to look like someone should make this a burst write.

I can send a separate patch for this.


Regards,

Ankit

>
>>   }
>>   
>>   static void _psr_enable_sink(struct intel_dp *intel_dp,
>> @@ -1771,6 +1775,9 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
>>   	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
>>   	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
>>   
>> +	/* For now we use T1 as the transmission time */
>> +	crtc_state->pr_as_sdp_transmission = AS_SDP_SETUP_TIME_T1;
>> +
>>   	if (!intel_dp_is_edp(intel_dp))
>>   		return true;
>>   
>> -- 
>> 2.45.2

[PATCH 14/14] drm/i915/dp: Account for AS_SDP guardband only when enabled

[Ankit Nautiyal]

Currently the intel_dp_sdp_min_guardband() accounts for AS_SDP for all
platforms that support adaptive sync SDP even for configurations where
it cannot be enabled. Instead account for adaptive sync SDP guardband
only when it is enabled.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ad2aceb526ff..70121f4d5a90 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7271,7 +7271,6 @@ int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 ty
 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 			       bool assume_all_enabled)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
 	int sdp_guardband = 0;
 
 	if (assume_all_enabled ||
@@ -7286,8 +7285,8 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));
 
-	if ((assume_all_enabled && HAS_AS_SDP(display)) ||
-	    crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+	if (crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
 		sdp_guardband = max(sdp_guardband,
 				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
 
-- 
2.45.2

✓ CI.KUnit: success for Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[Patchwork]

== Series Details ==

Series: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM
URL   : https://patchwork.freedesktop.org/series/161978/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:25:30] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:25:34] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[14:26:11] Starting KUnit Kernel (1/1)...
[14:26:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:26:12] ================== guc_buf (11 subtests) ===================
[14:26:12] [PASSED] test_smallest
[14:26:12] [PASSED] test_largest
[14:26:12] [PASSED] test_granular
[14:26:12] [PASSED] test_unique
[14:26:12] [PASSED] test_overlap
[14:26:12] [PASSED] test_reusable
[14:26:12] [PASSED] test_too_big
[14:26:12] [PASSED] test_flush
[14:26:12] [PASSED] test_lookup
[14:26:12] [PASSED] test_data
[14:26:12] [PASSED] test_class
[14:26:12] ===================== [PASSED] guc_buf =====================
[14:26:12] =================== guc_dbm (7 subtests) ===================
[14:26:12] [PASSED] test_empty
[14:26:12] [PASSED] test_default
[14:26:12] ======================== test_size  ========================
[14:26:12] [PASSED] 4
[14:26:12] [PASSED] 8
[14:26:12] [PASSED] 32
[14:26:12] [PASSED] 256
[14:26:12] ==================== [PASSED] test_size ====================
[14:26:12] ======================= test_reuse  ========================
[14:26:12] [PASSED] 4
[14:26:12] [PASSED] 8
[14:26:12] [PASSED] 32
[14:26:12] [PASSED] 256
[14:26:12] =================== [PASSED] test_reuse ====================
[14:26:12] =================== test_range_overlap  ====================
[14:26:12] [PASSED] 4
[14:26:12] [PASSED] 8
[14:26:12] [PASSED] 32
[14:26:12] [PASSED] 256
[14:26:12] =============== [PASSED] test_range_overlap ================
[14:26:12] =================== test_range_compact  ====================
[14:26:12] [PASSED] 4
[14:26:12] [PASSED] 8
[14:26:12] [PASSED] 32
[14:26:12] [PASSED] 256
[14:26:12] =============== [PASSED] test_range_compact ================
[14:26:12] ==================== test_range_spare  =====================
[14:26:12] [PASSED] 4
[14:26:12] [PASSED] 8
[14:26:12] [PASSED] 32
[14:26:12] [PASSED] 256
[14:26:12] ================ [PASSED] test_range_spare =================
[14:26:12] ===================== [PASSED] guc_dbm =====================
[14:26:12] =================== guc_idm (6 subtests) ===================
[14:26:12] [PASSED] bad_init
[14:26:12] [PASSED] no_init
[14:26:12] [PASSED] init_fini
[14:26:12] [PASSED] check_used
[14:26:12] [PASSED] check_quota
[14:26:12] [PASSED] check_all
[14:26:12] ===================== [PASSED] guc_idm =====================
[14:26:12] ================== no_relay (3 subtests) ===================
[14:26:12] [PASSED] xe_drops_guc2pf_if_not_ready
[14:26:12] [PASSED] xe_drops_guc2vf_if_not_ready
[14:26:12] [PASSED] xe_rejects_send_if_not_ready
[14:26:12] ==================== [PASSED] no_relay =====================
[14:26:12] ================== pf_relay (14 subtests) ==================
[14:26:12] [PASSED] pf_rejects_guc2pf_too_short
[14:26:12] [PASSED] pf_rejects_guc2pf_too_long
[14:26:12] [PASSED] pf_rejects_guc2pf_no_payload
[14:26:12] [PASSED] pf_fails_no_payload
[14:26:12] [PASSED] pf_fails_bad_origin
[14:26:12] [PASSED] pf_fails_bad_type
[14:26:12] [PASSED] pf_txn_reports_error
[14:26:12] [PASSED] pf_txn_sends_pf2guc
[14:26:12] [PASSED] pf_sends_pf2guc
[14:26:12] [SKIPPED] pf_loopback_nop
[14:26:12] [SKIPPED] pf_loopback_echo
[14:26:12] [SKIPPED] pf_loopback_fail
[14:26:12] [SKIPPED] pf_loopback_busy
[14:26:12] [SKIPPED] pf_loopback_retry
[14:26:12] ==================== [PASSED] pf_relay =====================
[14:26:12] ================== vf_relay (3 subtests) ===================
[14:26:12] [PASSED] vf_rejects_guc2vf_too_short
[14:26:12] [PASSED] vf_rejects_guc2vf_too_long
[14:26:12] [PASSED] vf_rejects_guc2vf_no_payload
[14:26:12] ==================== [PASSED] vf_relay =====================
[14:26:12] ================ pf_gt_config (9 subtests) =================
[14:26:12] [PASSED] fair_contexts_1vf
[14:26:12] [PASSED] fair_doorbells_1vf
[14:26:12] [PASSED] fair_ggtt_1vf
[14:26:12] ====================== fair_vram_1vf  ======================
[14:26:12] [PASSED] 3.50 GiB
[14:26:12] [PASSED] 11.5 GiB
[14:26:12] [PASSED] 15.5 GiB
[14:26:12] [PASSED] 31.5 GiB
[14:26:12] [PASSED] 63.5 GiB
[14:26:12] [PASSED] 13.9 GiB
[14:26:12] ================== [PASSED] fair_vram_1vf ==================
[14:26:12] ================ fair_vram_1vf_admin_only  =================
[14:26:12] [PASSED] 3.50 GiB
[14:26:12] [PASSED] 11.5 GiB
[14:26:12] [PASSED] 15.5 GiB
[14:26:12] [PASSED] 31.5 GiB
[14:26:12] [PASSED] 63.5 GiB
[14:26:12] [PASSED] 13.9 GiB
[14:26:12] ============ [PASSED] fair_vram_1vf_admin_only =============
[14:26:12] ====================== fair_contexts  ======================
[14:26:12] [PASSED] 1 VF
[14:26:12] [PASSED] 2 VFs
[14:26:12] [PASSED] 3 VFs
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[14:26:12] [PASSED] 61 VFs
[14:26:12] [PASSED] 62 VFs
[14:26:12] [PASSED] 63 VFs
[14:26:12] ================== [PASSED] fair_contexts ==================
[14:26:12] ===================== fair_doorbells  ======================
[14:26:12] [PASSED] 1 VF
[14:26:12] [PASSED] 2 VFs
[14:26:12] [PASSED] 3 VFs
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[14:26:12] [PASSED] 50 VFs
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[14:26:12] [PASSED] 53 VFs
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[14:26:12] [PASSED] 56 VFs
[14:26:12] [PASSED] 57 VFs
[14:26:12] [PASSED] 58 VFs
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[14:26:12] [PASSED] 60 VFs
[14:26:12] [PASSED] 61 VFs
[14:26:12] [PASSED] 62 VFs
[14:26:12] [PASSED] 63 VFs
[14:26:12] ================= [PASSED] fair_doorbells ==================
[14:26:12] ======================== fair_ggtt  ========================
[14:26:12] [PASSED] 1 VF
[14:26:12] [PASSED] 2 VFs
[14:26:12] [PASSED] 3 VFs
[14:26:12] [PASSED] 4 VFs
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[14:26:12] [PASSED] 11 VFs
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[14:26:12] [PASSED] 38 VFs
[14:26:12] [PASSED] 39 VFs
[14:26:12] [PASSED] 40 VFs
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[14:26:12] [PASSED] 42 VFs
[14:26:12] [PASSED] 43 VFs
[14:26:12] [PASSED] 44 VFs
[14:26:12] [PASSED] 45 VFs
[14:26:12] [PASSED] 46 VFs
[14:26:12] [PASSED] 47 VFs
[14:26:12] [PASSED] 48 VFs
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[14:26:12] [PASSED] 50 VFs
[14:26:12] [PASSED] 51 VFs
[14:26:12] [PASSED] 52 VFs
[14:26:12] [PASSED] 53 VFs
[14:26:12] [PASSED] 54 VFs
[14:26:12] [PASSED] 55 VFs
[14:26:12] [PASSED] 56 VFs
[14:26:12] [PASSED] 57 VFs
[14:26:12] [PASSED] 58 VFs
[14:26:12] [PASSED] 59 VFs
[14:26:12] [PASSED] 60 VFs
[14:26:12] [PASSED] 61 VFs
[14:26:12] [PASSED] 62 VFs
[14:26:12] [PASSED] 63 VFs
[14:26:12] ==================== [PASSED] fair_ggtt ====================
[14:26:12] ======================== fair_vram  ========================
[14:26:12] [PASSED] 1 VF
[14:26:12] [PASSED] 2 VFs
[14:26:12] [PASSED] 3 VFs
[14:26:12] [PASSED] 4 VFs
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[14:26:12] [PASSED] 24 VFs
[14:26:12] [PASSED] 25 VFs
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[14:26:12] [PASSED] 35 VFs
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[14:26:12] [PASSED] 38 VFs
[14:26:12] [PASSED] 39 VFs
[14:26:12] [PASSED] 40 VFs
[14:26:12] [PASSED] 41 VFs
[14:26:12] [PASSED] 42 VFs
[14:26:12] [PASSED] 43 VFs
[14:26:12] [PASSED] 44 VFs
[14:26:12] [PASSED] 45 VFs
[14:26:12] [PASSED] 46 VFs
[14:26:12] [PASSED] 47 VFs
[14:26:12] [PASSED] 48 VFs
[14:26:12] [PASSED] 49 VFs
[14:26:12] [PASSED] 50 VFs
[14:26:12] [PASSED] 51 VFs
[14:26:12] [PASSED] 52 VFs
[14:26:12] [PASSED] 53 VFs
[14:26:12] [PASSED] 54 VFs
[14:26:12] [PASSED] 55 VFs
[14:26:12] [PASSED] 56 VFs
[14:26:12] [PASSED] 57 VFs
[14:26:12] [PASSED] 58 VFs
[14:26:12] [PASSED] 59 VFs
[14:26:12] [PASSED] 60 VFs
[14:26:12] [PASSED] 61 VFs
[14:26:12] [PASSED] 62 VFs
[14:26:12] [PASSED] 63 VFs
[14:26:12] ==================== [PASSED] fair_vram ====================
[14:26:12] ================== [PASSED] pf_gt_config ===================
[14:26:12] ===================== lmtt (1 subtest) =====================
[14:26:12] ======================== test_ops  =========================
[14:26:12] [PASSED] 2-level
[14:26:12] [PASSED] multi-level
[14:26:12] ==================== [PASSED] test_ops =====================
[14:26:12] ====================== [PASSED] lmtt =======================
[14:26:12] ================= pf_service (11 subtests) =================
[14:26:12] [PASSED] pf_negotiate_any
[14:26:12] [PASSED] pf_negotiate_base_match
[14:26:12] [PASSED] pf_negotiate_base_newer
[14:26:12] [PASSED] pf_negotiate_base_next
[14:26:12] [SKIPPED] pf_negotiate_base_older
[14:26:12] [PASSED] pf_negotiate_base_prev
[14:26:12] [PASSED] pf_negotiate_latest_match
[14:26:12] [PASSED] pf_negotiate_latest_newer
[14:26:12] [PASSED] pf_negotiate_latest_next
[14:26:12] [SKIPPED] pf_negotiate_latest_older
[14:26:12] [SKIPPED] pf_negotiate_latest_prev
[14:26:12] =================== [PASSED] pf_service ====================
[14:26:12] ================= xe_guc_g2g (2 subtests) ==================
[14:26:12] ============== xe_live_guc_g2g_kunit_default  ==============
[14:26:12] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[14:26:12] ============== xe_live_guc_g2g_kunit_allmem  ===============
[14:26:12] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[14:26:12] =================== [SKIPPED] xe_guc_g2g ===================
[14:26:12] =================== xe_mocs (2 subtests) ===================
[14:26:12] ================ xe_live_mocs_kernel_kunit  ================
[14:26:12] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[14:26:12] ================ xe_live_mocs_reset_kunit  =================
[14:26:12] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[14:26:12] ==================== [SKIPPED] xe_mocs =====================
[14:26:12] ================= xe_migrate (2 subtests) ==================
[14:26:12] ================= xe_migrate_sanity_kunit  =================
[14:26:12] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[14:26:12] ================== xe_validate_ccs_kunit  ==================
[14:26:12] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[14:26:12] =================== [SKIPPED] xe_migrate ===================
[14:26:12] ================== xe_dma_buf (1 subtest) ==================
[14:26:12] ==================== xe_dma_buf_kunit  =====================
[14:26:12] ================ [SKIPPED] xe_dma_buf_kunit ================
[14:26:12] =================== [SKIPPED] xe_dma_buf ===================
[14:26:12] ================= xe_bo_shrink (1 subtest) =================
[14:26:12] =================== xe_bo_shrink_kunit  ====================
[14:26:12] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[14:26:12] ================== [SKIPPED] xe_bo_shrink ==================
[14:26:12] ==================== xe_bo (2 subtests) ====================
[14:26:12] ================== xe_ccs_migrate_kunit  ===================
[14:26:12] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[14:26:12] ==================== xe_bo_evict_kunit  ====================
[14:26:12] =============== [SKIPPED] xe_bo_evict_kunit ================
[14:26:12] ===================== [SKIPPED] xe_bo ======================
[14:26:12] ==================== args (13 subtests) ====================
[14:26:12] [PASSED] count_args_test
[14:26:12] [PASSED] call_args_example
[14:26:12] [PASSED] call_args_test
[14:26:12] [PASSED] drop_first_arg_example
[14:26:12] [PASSED] drop_first_arg_test
[14:26:12] [PASSED] first_arg_example
[14:26:12] [PASSED] first_arg_test
[14:26:12] [PASSED] last_arg_example
[14:26:12] [PASSED] last_arg_test
[14:26:12] [PASSED] pick_arg_example
[14:26:12] [PASSED] if_args_example
[14:26:12] [PASSED] if_args_test
[14:26:12] [PASSED] sep_comma_example
[14:26:12] ====================== [PASSED] args =======================
[14:26:12] =================== xe_pci (3 subtests) ====================
[14:26:12] ==================== check_graphics_ip  ====================
[14:26:12] [PASSED] 12.00 Xe_LP
[14:26:12] [PASSED] 12.10 Xe_LP+
[14:26:12] [PASSED] 12.55 Xe_HPG
[14:26:12] [PASSED] 12.60 Xe_HPC
[14:26:12] [PASSED] 12.70 Xe_LPG
[14:26:12] [PASSED] 12.71 Xe_LPG
[14:26:12] [PASSED] 12.74 Xe_LPG+
[14:26:12] [PASSED] 20.01 Xe2_HPG
[14:26:12] [PASSED] 20.02 Xe2_HPG
[14:26:12] [PASSED] 20.04 Xe2_LPG
[14:26:12] [PASSED] 30.00 Xe3_LPG
[14:26:12] [PASSED] 30.01 Xe3_LPG
[14:26:12] [PASSED] 30.03 Xe3_LPG
[14:26:12] [PASSED] 30.04 Xe3_LPG
[14:26:12] [PASSED] 30.05 Xe3_LPG
[14:26:12] [PASSED] 35.10 Xe3p_LPG
[14:26:12] [PASSED] 35.11 Xe3p_XPC
[14:26:12] ================ [PASSED] check_graphics_ip ================
[14:26:12] ===================== check_media_ip  ======================
[14:26:12] [PASSED] 12.00 Xe_M
[14:26:12] [PASSED] 12.55 Xe_HPM
[14:26:12] [PASSED] 13.00 Xe_LPM+
[14:26:12] [PASSED] 13.01 Xe2_HPM
[14:26:12] [PASSED] 20.00 Xe2_LPM
[14:26:12] [PASSED] 30.00 Xe3_LPM
[14:26:12] [PASSED] 30.02 Xe3_LPM
[14:26:12] [PASSED] 35.00 Xe3p_LPM
[14:26:12] [PASSED] 35.03 Xe3p_HPM
[14:26:12] ================= [PASSED] check_media_ip ==================
[14:26:12] =================== check_platform_desc  ===================
[14:26:12] [PASSED] 0x9A60 (TIGERLAKE)
[14:26:12] [PASSED] 0x9A68 (TIGERLAKE)
[14:26:12] [PASSED] 0x9A70 (TIGERLAKE)
[14:26:12] [PASSED] 0x9A40 (TIGERLAKE)
[14:26:12] [PASSED] 0x9A49 (TIGERLAKE)
[14:26:12] [PASSED] 0x9A59 (TIGERLAKE)
[14:26:12] [PASSED] 0x9A78 (TIGERLAKE)
[14:26:12] [PASSED] 0x9AC0 (TIGERLAKE)
[14:26:12] [PASSED] 0x9AC9 (TIGERLAKE)
[14:26:12] [PASSED] 0x9AD9 (TIGERLAKE)
[14:26:12] [PASSED] 0x9AF8 (TIGERLAKE)
[14:26:12] [PASSED] 0x4C80 (ROCKETLAKE)
[14:26:12] [PASSED] 0x4C8A (ROCKETLAKE)
[14:26:12] [PASSED] 0x4C8B (ROCKETLAKE)
[14:26:12] [PASSED] 0x4C8C (ROCKETLAKE)
[14:26:12] [PASSED] 0x4C90 (ROCKETLAKE)
[14:26:12] [PASSED] 0x4C9A (ROCKETLAKE)
[14:26:12] [PASSED] 0x4680 (ALDERLAKE_S)
[14:26:12] [PASSED] 0x4682 (ALDERLAKE_S)
[14:26:12] [PASSED] 0x4688 (ALDERLAKE_S)
[14:26:12] [PASSED] 0x468A (ALDERLAKE_S)
[14:26:12] [PASSED] 0x468B (ALDERLAKE_S)
[14:26:12] [PASSED] 0x4690 (ALDERLAKE_S)
[14:26:12] [PASSED] 0x4692 (ALDERLAKE_S)
[14:26:12] [PASSED] 0x4693 (ALDERLAKE_S)
[14:26:12] [PASSED] 0x46A0 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46A1 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46A2 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46A3 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46A6 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46A8 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46AA (ALDERLAKE_P)
[14:26:12] [PASSED] 0x462A (ALDERLAKE_P)
[14:26:12] [PASSED] 0x4626 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x4628 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46B0 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46B1 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46B2 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46B3 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46C0 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46C1 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46C2 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46C3 (ALDERLAKE_P)
[14:26:12] [PASSED] 0x46D0 (ALDERLAKE_N)
[14:26:12] [PASSED] 0x46D1 (ALDERLAKE_N)
[14:26:12] [PASSED] 0x46D2 (ALDERLAKE_N)
[14:26:12] [PASSED] 0x46D3 (ALDERLAKE_N)
[14:26:12] [PASSED] 0x46D4 (ALDERLAKE_N)
[14:26:12] [PASSED] 0xA721 (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA7A1 (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA7A9 (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA7AC (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA7AD (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA720 (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA7A0 (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA7A8 (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA7AA (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA7AB (ALDERLAKE_P)
[14:26:12] [PASSED] 0xA780 (ALDERLAKE_S)
[14:26:12] [PASSED] 0xA781 (ALDERLAKE_S)
[14:26:12] [PASSED] 0xA782 (ALDERLAKE_S)
[14:26:12] [PASSED] 0xA783 (ALDERLAKE_S)
[14:26:12] [PASSED] 0xA788 (ALDERLAKE_S)
[14:26:12] [PASSED] 0xA789 (ALDERLAKE_S)
[14:26:12] [PASSED] 0xA78A (ALDERLAKE_S)
[14:26:12] [PASSED] 0xA78B (ALDERLAKE_S)
[14:26:12] [PASSED] 0x4905 (DG1)
[14:26:12] [PASSED] 0x4906 (DG1)
[14:26:12] [PASSED] 0x4907 (DG1)
[14:26:12] [PASSED] 0x4908 (DG1)
[14:26:12] [PASSED] 0x4909 (DG1)
[14:26:12] [PASSED] 0x56C0 (DG2)
[14:26:12] [PASSED] 0x56C2 (DG2)
[14:26:12] [PASSED] 0x56C1 (DG2)
[14:26:12] [PASSED] 0x7D51 (METEORLAKE)
[14:26:12] [PASSED] 0x7DD1 (METEORLAKE)
[14:26:12] [PASSED] 0x7D41 (METEORLAKE)
[14:26:12] [PASSED] 0x7D67 (METEORLAKE)
[14:26:12] [PASSED] 0xB640 (METEORLAKE)
[14:26:12] [PASSED] 0x56A0 (DG2)
[14:26:12] [PASSED] 0x56A1 (DG2)
[14:26:12] [PASSED] 0x56A2 (DG2)
[14:26:12] [PASSED] 0x56BE (DG2)
[14:26:12] [PASSED] 0x56BF (DG2)
[14:26:12] [PASSED] 0x5690 (DG2)
[14:26:12] [PASSED] 0x5691 (DG2)
[14:26:12] [PASSED] 0x5692 (DG2)
[14:26:12] [PASSED] 0x56A5 (DG2)
[14:26:12] [PASSED] 0x56A6 (DG2)
[14:26:12] [PASSED] 0x56B0 (DG2)
[14:26:12] [PASSED] 0x56B1 (DG2)
[14:26:12] [PASSED] 0x56BA (DG2)
[14:26:12] [PASSED] 0x56BB (DG2)
[14:26:12] [PASSED] 0x56BC (DG2)
[14:26:12] [PASSED] 0x56BD (DG2)
[14:26:12] [PASSED] 0x5693 (DG2)
[14:26:12] [PASSED] 0x5694 (DG2)
[14:26:12] [PASSED] 0x5695 (DG2)
[14:26:12] [PASSED] 0x56A3 (DG2)
[14:26:12] [PASSED] 0x56A4 (DG2)
[14:26:12] [PASSED] 0x56B2 (DG2)
[14:26:12] [PASSED] 0x56B3 (DG2)
[14:26:12] [PASSED] 0x5696 (DG2)
[14:26:12] [PASSED] 0x5697 (DG2)
[14:26:12] [PASSED] 0xB69 (PVC)
[14:26:12] [PASSED] 0xB6E (PVC)
[14:26:12] [PASSED] 0xBD4 (PVC)
[14:26:12] [PASSED] 0xBD5 (PVC)
[14:26:12] [PASSED] 0xBD6 (PVC)
[14:26:12] [PASSED] 0xBD7 (PVC)
[14:26:12] [PASSED] 0xBD8 (PVC)
[14:26:12] [PASSED] 0xBD9 (PVC)
[14:26:12] [PASSED] 0xBDA (PVC)
[14:26:12] [PASSED] 0xBDB (PVC)
[14:26:12] [PASSED] 0xBE0 (PVC)
[14:26:12] [PASSED] 0xBE1 (PVC)
[14:26:12] [PASSED] 0xBE5 (PVC)
[14:26:12] [PASSED] 0x7D40 (METEORLAKE)
[14:26:12] [PASSED] 0x7D45 (METEORLAKE)
[14:26:12] [PASSED] 0x7D55 (METEORLAKE)
[14:26:12] [PASSED] 0x7D60 (METEORLAKE)
[14:26:12] [PASSED] 0x7DD5 (METEORLAKE)
[14:26:12] [PASSED] 0x6420 (LUNARLAKE)
[14:26:12] [PASSED] 0x64A0 (LUNARLAKE)
[14:26:12] [PASSED] 0x64B0 (LUNARLAKE)
[14:26:12] [PASSED] 0xE202 (BATTLEMAGE)
[14:26:12] [PASSED] 0xE209 (BATTLEMAGE)
[14:26:12] [PASSED] 0xE20B (BATTLEMAGE)
[14:26:12] [PASSED] 0xE20C (BATTLEMAGE)
[14:26:12] [PASSED] 0xE20D (BATTLEMAGE)
[14:26:12] [PASSED] 0xE210 (BATTLEMAGE)
[14:26:12] [PASSED] 0xE211 (BATTLEMAGE)
[14:26:12] [PASSED] 0xE212 (BATTLEMAGE)
[14:26:12] [PASSED] 0xE216 (BATTLEMAGE)
[14:26:12] [PASSED] 0xE220 (BATTLEMAGE)
[14:26:12] [PASSED] 0xE221 (BATTLEMAGE)
[14:26:12] [PASSED] 0xE222 (BATTLEMAGE)
[14:26:12] [PASSED] 0xE223 (BATTLEMAGE)
[14:26:12] [PASSED] 0xB080 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB081 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB082 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB083 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB084 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB085 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB086 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB087 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB08F (PANTHERLAKE)
[14:26:12] [PASSED] 0xB090 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB0A0 (PANTHERLAKE)
[14:26:12] [PASSED] 0xB0B0 (PANTHERLAKE)
[14:26:12] [PASSED] 0xFD80 (PANTHERLAKE)
[14:26:12] [PASSED] 0xFD81 (PANTHERLAKE)
[14:26:12] [PASSED] 0xD740 (NOVALAKE_S)
[14:26:12] [PASSED] 0xD741 (NOVALAKE_S)
[14:26:12] [PASSED] 0xD742 (NOVALAKE_S)
[14:26:12] [PASSED] 0xD743 (NOVALAKE_S)
[14:26:12] [PASSED] 0xD744 (NOVALAKE_S)
[14:26:12] [PASSED] 0xD745 (NOVALAKE_S)
[14:26:12] [PASSED] 0x674C (CRESCENTISLAND)
[14:26:12] [PASSED] 0xD750 (NOVALAKE_P)
[14:26:12] [PASSED] 0xD751 (NOVALAKE_P)
[14:26:12] [PASSED] 0xD752 (NOVALAKE_P)
[14:26:12] [PASSED] 0xD753 (NOVALAKE_P)
[14:26:12] [PASSED] 0xD754 (NOVALAKE_P)
[14:26:12] [PASSED] 0xD755 (NOVALAKE_P)
[14:26:12] [PASSED] 0xD756 (NOVALAKE_P)
[14:26:12] [PASSED] 0xD757 (NOVALAKE_P)
[14:26:12] [PASSED] 0xD75F (NOVALAKE_P)
[14:26:12] =============== [PASSED] check_platform_desc ===============
[14:26:12] ===================== [PASSED] xe_pci ======================
[14:26:12] =================== xe_rtp (2 subtests) ====================
[14:26:12] =============== xe_rtp_process_to_sr_tests  ================
[14:26:12] [PASSED] coalesce-same-reg
[14:26:12] [PASSED] no-match-no-add
[14:26:12] [PASSED] match-or
[14:26:12] [PASSED] match-or-xfail
[14:26:12] [PASSED] no-match-no-add-multiple-rules
[14:26:12] [PASSED] two-regs-two-entries
[14:26:12] [PASSED] clr-one-set-other
[14:26:12] [PASSED] set-field
[14:26:12] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[14:26:12] [PASSED] conflict-not-disjoint
[14:26:12] [PASSED] conflict-reg-type
[14:26:12] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[14:26:12] ================== xe_rtp_process_tests  ===================
[14:26:12] [PASSED] active1
[14:26:12] [PASSED] active2
[14:26:12] [PASSED] active-inactive
[14:26:12] [PASSED] inactive-active
[14:26:12] [PASSED] inactive-1st_or_active-inactive
[14:26:12] [PASSED] inactive-2nd_or_active-inactive
[14:26:12] [PASSED] inactive-last_or_active-inactive
[14:26:12] [PASSED] inactive-no_or_active-inactive
[14:26:12] ============== [PASSED] xe_rtp_process_tests ===============
[14:26:12] ===================== [PASSED] xe_rtp ======================
[14:26:12] ==================== xe_wa (1 subtest) =====================
[14:26:12] ======================== xe_wa_gt  =========================
[14:26:12] [PASSED] TIGERLAKE B0
[14:26:12] [PASSED] DG1 A0
[14:26:12] [PASSED] DG1 B0
[14:26:12] [PASSED] ALDERLAKE_S A0
[14:26:12] [PASSED] ALDERLAKE_S B0
[14:26:12] [PASSED] ALDERLAKE_S C0
[14:26:12] [PASSED] ALDERLAKE_S D0
[14:26:12] [PASSED] ALDERLAKE_P A0
[14:26:12] [PASSED] ALDERLAKE_P B0
[14:26:12] [PASSED] ALDERLAKE_P C0
[14:26:12] [PASSED] ALDERLAKE_S RPLS D0
[14:26:12] [PASSED] ALDERLAKE_P RPLU E0
[14:26:12] [PASSED] DG2 G10 C0
[14:26:12] [PASSED] DG2 G11 B1
[14:26:12] [PASSED] DG2 G12 A1
[14:26:12] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:26:12] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:26:12] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[14:26:12] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[14:26:12] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[14:26:12] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[14:26:12] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[14:26:12] ==================== [PASSED] xe_wa_gt =====================
[14:26:12] ====================== [PASSED] xe_wa ======================
[14:26:12] ============================================================
[14:26:12] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[14:26:12] Elapsed time: 42.419s total, 4.327s configuring, 37.425s building, 0.633s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[14:26:12] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:26:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[14:26:43] Starting KUnit Kernel (1/1)...
[14:26:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:26:43] ============ drm_test_pick_cmdline (2 subtests) ============
[14:26:43] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[14:26:43] =============== drm_test_pick_cmdline_named  ===============
[14:26:43] [PASSED] NTSC
[14:26:43] [PASSED] NTSC-J
[14:26:43] [PASSED] PAL
[14:26:43] [PASSED] PAL-M
[14:26:43] =========== [PASSED] drm_test_pick_cmdline_named ===========
[14:26:43] ============== [PASSED] drm_test_pick_cmdline ==============
[14:26:43] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:26:43] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:26:43] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:26:43] =========== drm_validate_clone_mode (2 subtests) ===========
[14:26:43] ============== drm_test_check_in_clone_mode  ===============
[14:26:43] [PASSED] in_clone_mode
[14:26:43] [PASSED] not_in_clone_mode
[14:26:43] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:26:43] =============== drm_test_check_valid_clones  ===============
[14:26:43] [PASSED] not_in_clone_mode
[14:26:43] [PASSED] valid_clone
[14:26:43] [PASSED] invalid_clone
[14:26:43] =========== [PASSED] drm_test_check_valid_clones ===========
[14:26:43] ============= [PASSED] drm_validate_clone_mode =============
[14:26:43] ============= drm_validate_modeset (1 subtest) =============
[14:26:43] [PASSED] drm_test_check_connector_changed_modeset
[14:26:43] ============== [PASSED] drm_validate_modeset ===============
[14:26:43] ====== drm_test_bridge_get_current_state (2 subtests) ======
[14:26:43] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:26:43] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[14:26:43] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:26:43] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:26:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:26:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:26:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[14:26:43] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:26:43] ============== drm_bridge_alloc (2 subtests) ===============
[14:26:43] [PASSED] drm_test_drm_bridge_alloc_basic
[14:26:43] [PASSED] drm_test_drm_bridge_alloc_get_put
[14:26:43] ================ [PASSED] drm_bridge_alloc =================
[14:26:43] ============= drm_cmdline_parser (40 subtests) =============
[14:26:43] [PASSED] drm_test_cmdline_force_d_only
[14:26:43] [PASSED] drm_test_cmdline_force_D_only_dvi
[14:26:43] [PASSED] drm_test_cmdline_force_D_only_hdmi
[14:26:43] [PASSED] drm_test_cmdline_force_D_only_not_digital
[14:26:43] [PASSED] drm_test_cmdline_force_e_only
[14:26:43] [PASSED] drm_test_cmdline_res
[14:26:43] [PASSED] drm_test_cmdline_res_vesa
[14:26:43] [PASSED] drm_test_cmdline_res_vesa_rblank
[14:26:43] [PASSED] drm_test_cmdline_res_rblank
[14:26:43] [PASSED] drm_test_cmdline_res_bpp
[14:26:43] [PASSED] drm_test_cmdline_res_refresh
[14:26:43] [PASSED] drm_test_cmdline_res_bpp_refresh
[14:26:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[14:26:43] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[14:26:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[14:26:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[14:26:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[14:26:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[14:26:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[14:26:43] [PASSED] drm_test_cmdline_res_margins_force_on
[14:26:43] [PASSED] drm_test_cmdline_res_vesa_margins
[14:26:43] [PASSED] drm_test_cmdline_name
[14:26:43] [PASSED] drm_test_cmdline_name_bpp
[14:26:43] [PASSED] drm_test_cmdline_name_option
[14:26:43] [PASSED] drm_test_cmdline_name_bpp_option
[14:26:43] [PASSED] drm_test_cmdline_rotate_0
[14:26:43] [PASSED] drm_test_cmdline_rotate_90
[14:26:43] [PASSED] drm_test_cmdline_rotate_180
[14:26:43] [PASSED] drm_test_cmdline_rotate_270
[14:26:43] [PASSED] drm_test_cmdline_hmirror
[14:26:43] [PASSED] drm_test_cmdline_vmirror
[14:26:43] [PASSED] drm_test_cmdline_margin_options
[14:26:43] [PASSED] drm_test_cmdline_multiple_options
[14:26:43] [PASSED] drm_test_cmdline_bpp_extra_and_option
[14:26:43] [PASSED] drm_test_cmdline_extra_and_option
[14:26:43] [PASSED] drm_test_cmdline_freestanding_options
[14:26:43] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[14:26:43] [PASSED] drm_test_cmdline_panel_orientation
[14:26:43] ================ drm_test_cmdline_invalid  =================
[14:26:43] [PASSED] margin_only
[14:26:43] [PASSED] interlace_only
[14:26:43] [PASSED] res_missing_x
[14:26:43] [PASSED] res_missing_y
[14:26:43] [PASSED] res_bad_y
[14:26:43] [PASSED] res_missing_y_bpp
[14:26:43] [PASSED] res_bad_bpp
[14:26:43] [PASSED] res_bad_refresh
[14:26:43] [PASSED] res_bpp_refresh_force_on_off
[14:26:43] [PASSED] res_invalid_mode
[14:26:43] [PASSED] res_bpp_wrong_place_mode
[14:26:43] [PASSED] name_bpp_refresh
[14:26:43] [PASSED] name_refresh
[14:26:43] [PASSED] name_refresh_wrong_mode
[14:26:43] [PASSED] name_refresh_invalid_mode
[14:26:43] [PASSED] rotate_multiple
[14:26:43] [PASSED] rotate_invalid_val
[14:26:43] [PASSED] rotate_truncated
[14:26:43] [PASSED] invalid_option
[14:26:43] [PASSED] invalid_tv_option
[14:26:43] [PASSED] truncated_tv_option
[14:26:43] ============ [PASSED] drm_test_cmdline_invalid =============
[14:26:43] =============== drm_test_cmdline_tv_options  ===============
[14:26:43] [PASSED] NTSC
[14:26:43] [PASSED] NTSC_443
[14:26:43] [PASSED] NTSC_J
[14:26:43] [PASSED] PAL
[14:26:43] [PASSED] PAL_M
[14:26:43] [PASSED] PAL_N
[14:26:43] [PASSED] SECAM
[14:26:43] [PASSED] MONO_525
[14:26:43] [PASSED] MONO_625
[14:26:43] =========== [PASSED] drm_test_cmdline_tv_options ===========
[14:26:43] =============== [PASSED] drm_cmdline_parser ================
[14:26:43] ========== drmm_connector_hdmi_init (20 subtests) ==========
[14:26:43] [PASSED] drm_test_connector_hdmi_init_valid
[14:26:43] [PASSED] drm_test_connector_hdmi_init_bpc_8
[14:26:43] [PASSED] drm_test_connector_hdmi_init_bpc_10
[14:26:43] [PASSED] drm_test_connector_hdmi_init_bpc_12
[14:26:43] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[14:26:43] [PASSED] drm_test_connector_hdmi_init_bpc_null
[14:26:43] [PASSED] drm_test_connector_hdmi_init_formats_empty
[14:26:43] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[14:26:43] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[14:26:43] [PASSED] supported_formats=0x9 yuv420_allowed=1
[14:26:43] [PASSED] supported_formats=0x9 yuv420_allowed=0
[14:26:43] [PASSED] supported_formats=0x3 yuv420_allowed=1
[14:26:43] [PASSED] supported_formats=0x3 yuv420_allowed=0
[14:26:43] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:26:43] [PASSED] drm_test_connector_hdmi_init_null_ddc
[14:26:43] [PASSED] drm_test_connector_hdmi_init_null_product
[14:26:43] [PASSED] drm_test_connector_hdmi_init_null_vendor
[14:26:43] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[14:26:43] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[14:26:43] [PASSED] drm_test_connector_hdmi_init_product_valid
[14:26:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[14:26:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[14:26:43] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[14:26:43] ========= drm_test_connector_hdmi_init_type_valid  =========
[14:26:43] [PASSED] HDMI-A
[14:26:43] [PASSED] HDMI-B
[14:26:43] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[14:26:43] ======== drm_test_connector_hdmi_init_type_invalid  ========
[14:26:43] [PASSED] Unknown
[14:26:43] [PASSED] VGA
[14:26:43] [PASSED] DVI-I
[14:26:43] [PASSED] DVI-D
[14:26:43] [PASSED] DVI-A
[14:26:43] [PASSED] Composite
[14:26:43] [PASSED] SVIDEO
[14:26:43] [PASSED] LVDS
[14:26:43] [PASSED] Component
[14:26:43] [PASSED] DIN
[14:26:43] [PASSED] DP
[14:26:43] [PASSED] TV
[14:26:43] [PASSED] eDP
[14:26:43] [PASSED] Virtual
[14:26:43] [PASSED] DSI
[14:26:43] [PASSED] DPI
[14:26:43] [PASSED] Writeback
[14:26:43] [PASSED] SPI
[14:26:43] [PASSED] USB
[14:26:43] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[14:26:43] ============ [PASSED] drmm_connector_hdmi_init =============
[14:26:43] ============= drmm_connector_init (3 subtests) =============
[14:26:43] [PASSED] drm_test_drmm_connector_init
[14:26:43] [PASSED] drm_test_drmm_connector_init_null_ddc
[14:26:43] ========= drm_test_drmm_connector_init_type_valid  =========
[14:26:43] [PASSED] Unknown
[14:26:43] [PASSED] VGA
[14:26:43] [PASSED] DVI-I
[14:26:43] [PASSED] DVI-D
[14:26:43] [PASSED] DVI-A
[14:26:43] [PASSED] Composite
[14:26:43] [PASSED] SVIDEO
[14:26:43] [PASSED] LVDS
[14:26:43] [PASSED] Component
[14:26:43] [PASSED] DIN
[14:26:43] [PASSED] DP
[14:26:43] [PASSED] HDMI-A
[14:26:43] [PASSED] HDMI-B
[14:26:43] [PASSED] TV
[14:26:43] [PASSED] eDP
[14:26:43] [PASSED] Virtual
[14:26:43] [PASSED] DSI
[14:26:43] [PASSED] DPI
[14:26:43] [PASSED] Writeback
[14:26:43] [PASSED] SPI
[14:26:43] [PASSED] USB
[14:26:43] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[14:26:43] =============== [PASSED] drmm_connector_init ===============
[14:26:43] ========= drm_connector_dynamic_init (6 subtests) ==========
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_init
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_init_properties
[14:26:43] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[14:26:43] [PASSED] Unknown
[14:26:43] [PASSED] VGA
[14:26:43] [PASSED] DVI-I
[14:26:43] [PASSED] DVI-D
[14:26:43] [PASSED] DVI-A
[14:26:43] [PASSED] Composite
[14:26:43] [PASSED] SVIDEO
[14:26:43] [PASSED] LVDS
[14:26:43] [PASSED] Component
[14:26:43] [PASSED] DIN
[14:26:43] [PASSED] DP
[14:26:43] [PASSED] HDMI-A
[14:26:43] [PASSED] HDMI-B
[14:26:43] [PASSED] TV
[14:26:43] [PASSED] eDP
[14:26:43] [PASSED] Virtual
[14:26:43] [PASSED] DSI
[14:26:43] [PASSED] DPI
[14:26:43] [PASSED] Writeback
[14:26:43] [PASSED] SPI
[14:26:43] [PASSED] USB
[14:26:43] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[14:26:43] ======== drm_test_drm_connector_dynamic_init_name  =========
[14:26:43] [PASSED] Unknown
[14:26:43] [PASSED] VGA
[14:26:43] [PASSED] DVI-I
[14:26:43] [PASSED] DVI-D
[14:26:43] [PASSED] DVI-A
[14:26:43] [PASSED] Composite
[14:26:43] [PASSED] SVIDEO
[14:26:43] [PASSED] LVDS
[14:26:43] [PASSED] Component
[14:26:43] [PASSED] DIN
[14:26:43] [PASSED] DP
[14:26:43] [PASSED] HDMI-A
[14:26:43] [PASSED] HDMI-B
[14:26:43] [PASSED] TV
[14:26:43] [PASSED] eDP
[14:26:43] [PASSED] Virtual
[14:26:43] [PASSED] DSI
[14:26:43] [PASSED] DPI
[14:26:43] [PASSED] Writeback
[14:26:43] [PASSED] SPI
[14:26:43] [PASSED] USB
[14:26:43] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[14:26:43] =========== [PASSED] drm_connector_dynamic_init ============
[14:26:43] ==== drm_connector_dynamic_register_early (4 subtests) =====
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[14:26:43] ====== [PASSED] drm_connector_dynamic_register_early =======
[14:26:43] ======= drm_connector_dynamic_register (7 subtests) ========
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[14:26:43] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[14:26:43] ========= [PASSED] drm_connector_dynamic_register ==========
[14:26:43] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[14:26:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[14:26:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[14:26:43] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[14:26:43] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[14:26:43] ========== drm_test_get_tv_mode_from_name_valid  ===========
[14:26:43] [PASSED] NTSC
[14:26:43] [PASSED] NTSC-443
[14:26:43] [PASSED] NTSC-J
[14:26:43] [PASSED] PAL
[14:26:43] [PASSED] PAL-M
[14:26:43] [PASSED] PAL-N
[14:26:43] [PASSED] SECAM
[14:26:43] [PASSED] Mono
[14:26:43] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[14:26:43] [PASSED] drm_test_get_tv_mode_from_name_truncated
[14:26:43] ============ [PASSED] drm_get_tv_mode_from_name ============
[14:26:43] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[14:26:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[14:26:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[14:26:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[14:26:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[14:26:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[14:26:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[14:26:43] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[14:26:43] [PASSED] VIC 96
[14:26:43] [PASSED] VIC 97
[14:26:43] [PASSED] VIC 101
[14:26:43] [PASSED] VIC 102
[14:26:43] [PASSED] VIC 106
[14:26:43] [PASSED] VIC 107
[14:26:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[14:26:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[14:26:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[14:26:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[14:26:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[14:26:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[14:26:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[14:26:43] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[14:26:43] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[14:26:43] [PASSED] Automatic
[14:26:43] [PASSED] Full
[14:26:43] [PASSED] Limited 16:235
[14:26:43] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[14:26:43] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[14:26:43] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[14:26:43] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[14:26:43] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[14:26:43] [PASSED] RGB
[14:26:43] [PASSED] YUV 4:2:0
[14:26:43] [PASSED] YUV 4:2:2
[14:26:43] [PASSED] YUV 4:4:4
[14:26:43] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[14:26:43] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[14:26:43] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[14:26:43] ============= drm_damage_helper (21 subtests) ==============
[14:26:43] [PASSED] drm_test_damage_iter_no_damage
[14:26:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[14:26:43] [PASSED] drm_test_damage_iter_no_damage_src_moved
[14:26:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[14:26:43] [PASSED] drm_test_damage_iter_no_damage_not_visible
[14:26:43] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[14:26:43] [PASSED] drm_test_damage_iter_no_damage_no_fb
[14:26:43] [PASSED] drm_test_damage_iter_simple_damage
[14:26:43] [PASSED] drm_test_damage_iter_single_damage
[14:26:43] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[14:26:43] [PASSED] drm_test_damage_iter_single_damage_outside_src
[14:26:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[14:26:43] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[14:26:43] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[14:26:43] [PASSED] drm_test_damage_iter_single_damage_src_moved
[14:26:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[14:26:43] [PASSED] drm_test_damage_iter_damage
[14:26:43] [PASSED] drm_test_damage_iter_damage_one_intersect
[14:26:43] [PASSED] drm_test_damage_iter_damage_one_outside
[14:26:43] [PASSED] drm_test_damage_iter_damage_src_moved
[14:26:43] [PASSED] drm_test_damage_iter_damage_not_visible
[14:26:43] ================ [PASSED] drm_damage_helper ================
[14:26:43] ============== drm_dp_mst_helper (3 subtests) ==============
[14:26:43] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[14:26:43] [PASSED] Clock 154000 BPP 30 DSC disabled
[14:26:43] [PASSED] Clock 234000 BPP 30 DSC disabled
[14:26:43] [PASSED] Clock 297000 BPP 24 DSC disabled
[14:26:43] [PASSED] Clock 332880 BPP 24 DSC enabled
[14:26:43] [PASSED] Clock 324540 BPP 24 DSC enabled
[14:26:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[14:26:43] ============== drm_test_dp_mst_calc_pbn_div  ===============
[14:26:43] [PASSED] Link rate 2000000 lane count 4
[14:26:43] [PASSED] Link rate 2000000 lane count 2
[14:26:43] [PASSED] Link rate 2000000 lane count 1
[14:26:43] [PASSED] Link rate 1350000 lane count 4
[14:26:43] [PASSED] Link rate 1350000 lane count 2
[14:26:43] [PASSED] Link rate 1350000 lane count 1
[14:26:43] [PASSED] Link rate 1000000 lane count 4
[14:26:43] [PASSED] Link rate 1000000 lane count 2
[14:26:43] [PASSED] Link rate 1000000 lane count 1
[14:26:43] [PASSED] Link rate 810000 lane count 4
[14:26:43] [PASSED] Link rate 810000 lane count 2
[14:26:43] [PASSED] Link rate 810000 lane count 1
[14:26:43] [PASSED] Link rate 540000 lane count 4
[14:26:43] [PASSED] Link rate 540000 lane count 2
[14:26:43] [PASSED] Link rate 540000 lane count 1
[14:26:43] [PASSED] Link rate 270000 lane count 4
[14:26:43] [PASSED] Link rate 270000 lane count 2
[14:26:43] [PASSED] Link rate 270000 lane count 1
[14:26:43] [PASSED] Link rate 162000 lane count 4
[14:26:43] [PASSED] Link rate 162000 lane count 2
[14:26:43] [PASSED] Link rate 162000 lane count 1
[14:26:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[14:26:43] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[14:26:43] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[14:26:43] [PASSED] DP_POWER_UP_PHY with port number
[14:26:43] [PASSED] DP_POWER_DOWN_PHY with port number
[14:26:43] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[14:26:43] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[14:26:43] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[14:26:43] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[14:26:43] [PASSED] DP_QUERY_PAYLOAD with port number
[14:26:43] [PASSED] DP_QUERY_PAYLOAD with VCPI
[14:26:43] [PASSED] DP_REMOTE_DPCD_READ with port number
[14:26:43] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[14:26:43] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[14:26:43] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[14:26:43] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[14:26:43] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[14:26:43] [PASSED] DP_REMOTE_I2C_READ with port number
[14:26:43] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[14:26:43] [PASSED] DP_REMOTE_I2C_READ with transactions array
[14:26:43] [PASSED] DP_REMOTE_I2C_WRITE with port number
[14:26:43] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[14:26:43] [PASSED] DP_REMOTE_I2C_WRITE with data array
[14:26:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[14:26:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[14:26:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[14:26:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[14:26:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[14:26:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[14:26:43] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[14:26:43] ================ [PASSED] drm_dp_mst_helper ================
[14:26:43] ================== drm_exec (7 subtests) ===================
[14:26:43] [PASSED] sanitycheck
[14:26:43] [PASSED] test_lock
[14:26:43] [PASSED] test_lock_unlock
[14:26:43] [PASSED] test_duplicates
[14:26:43] [PASSED] test_prepare
[14:26:43] [PASSED] test_prepare_array
[14:26:43] [PASSED] test_multiple_loops
[14:26:43] ==================== [PASSED] drm_exec =====================
[14:26:43] =========== drm_format_helper_test (17 subtests) ===========
[14:26:43] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[14:26:43] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[14:26:43] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[14:26:43] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[14:26:43] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[14:26:43] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[14:26:43] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[14:26:43] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[14:26:43] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[14:26:43] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[14:26:43] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[14:26:43] ============== drm_test_fb_xrgb8888_to_mono  ===============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[14:26:43] ==================== drm_test_fb_swab  =====================
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ================ [PASSED] drm_test_fb_swab =================
[14:26:43] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[14:26:43] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[14:26:43] [PASSED] single_pixel_source_buffer
[14:26:43] [PASSED] single_pixel_clip_rectangle
[14:26:43] [PASSED] well_known_colors
[14:26:43] [PASSED] destination_pitch
[14:26:43] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[14:26:43] ================= drm_test_fb_clip_offset  =================
[14:26:43] [PASSED] pass through
[14:26:43] [PASSED] horizontal offset
[14:26:43] [PASSED] vertical offset
[14:26:43] [PASSED] horizontal and vertical offset
[14:26:43] [PASSED] horizontal offset (custom pitch)
[14:26:43] [PASSED] vertical offset (custom pitch)
[14:26:43] [PASSED] horizontal and vertical offset (custom pitch)
[14:26:43] ============= [PASSED] drm_test_fb_clip_offset =============
[14:26:43] =================== drm_test_fb_memcpy  ====================
[14:26:43] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[14:26:43] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[14:26:43] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[14:26:43] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[14:26:43] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[14:26:43] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[14:26:43] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[14:26:43] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[14:26:43] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[14:26:43] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[14:26:43] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[14:26:43] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[14:26:43] =============== [PASSED] drm_test_fb_memcpy ================
[14:26:43] ============= [PASSED] drm_format_helper_test ==============
[14:26:43] ================= drm_format (18 subtests) =================
[14:26:43] [PASSED] drm_test_format_block_width_invalid
[14:26:43] [PASSED] drm_test_format_block_width_one_plane
[14:26:43] [PASSED] drm_test_format_block_width_two_plane
[14:26:43] [PASSED] drm_test_format_block_width_three_plane
[14:26:43] [PASSED] drm_test_format_block_width_tiled
[14:26:43] [PASSED] drm_test_format_block_height_invalid
[14:26:43] [PASSED] drm_test_format_block_height_one_plane
[14:26:43] [PASSED] drm_test_format_block_height_two_plane
[14:26:43] [PASSED] drm_test_format_block_height_three_plane
[14:26:43] [PASSED] drm_test_format_block_height_tiled
[14:26:43] [PASSED] drm_test_format_min_pitch_invalid
[14:26:43] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[14:26:43] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[14:26:43] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[14:26:43] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[14:26:43] [PASSED] drm_test_format_min_pitch_two_plane
[14:26:43] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[14:26:43] [PASSED] drm_test_format_min_pitch_tiled
[14:26:43] =================== [PASSED] drm_format ====================
[14:26:43] ============== drm_framebuffer (10 subtests) ===============
[14:26:43] ========== drm_test_framebuffer_check_src_coords  ==========
[14:26:43] [PASSED] Success: source fits into fb
[14:26:43] [PASSED] Fail: overflowing fb with x-axis coordinate
[14:26:43] [PASSED] Fail: overflowing fb with y-axis coordinate
[14:26:43] [PASSED] Fail: overflowing fb with source width
[14:26:43] [PASSED] Fail: overflowing fb with source height
[14:26:43] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[14:26:43] [PASSED] drm_test_framebuffer_cleanup
[14:26:43] =============== drm_test_framebuffer_create  ===============
[14:26:43] [PASSED] ABGR8888 normal sizes
[14:26:43] [PASSED] ABGR8888 max sizes
[14:26:43] [PASSED] ABGR8888 pitch greater than min required
[14:26:43] [PASSED] ABGR8888 pitch less than min required
[14:26:43] [PASSED] ABGR8888 Invalid width
[14:26:43] [PASSED] ABGR8888 Invalid buffer handle
[14:26:43] [PASSED] No pixel format
[14:26:43] [PASSED] ABGR8888 Width 0
[14:26:43] [PASSED] ABGR8888 Height 0
[14:26:43] [PASSED] ABGR8888 Out of bound height * pitch combination
[14:26:43] [PASSED] ABGR8888 Large buffer offset
[14:26:43] [PASSED] ABGR8888 Buffer offset for inexistent plane
[14:26:43] [PASSED] ABGR8888 Invalid flag
[14:26:43] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[14:26:43] [PASSED] ABGR8888 Valid buffer modifier
[14:26:43] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[14:26:43] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[14:26:43] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[14:26:43] [PASSED] NV12 Normal sizes
[14:26:43] [PASSED] NV12 Max sizes
[14:26:43] [PASSED] NV12 Invalid pitch
[14:26:43] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[14:26:43] [PASSED] NV12 different  modifier per-plane
[14:26:43] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[14:26:43] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[14:26:43] [PASSED] NV12 Modifier for inexistent plane
[14:26:43] [PASSED] NV12 Handle for inexistent plane
[14:26:43] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[14:26:43] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[14:26:43] [PASSED] YVU420 Normal sizes
[14:26:43] [PASSED] YVU420 Max sizes
[14:26:43] [PASSED] YVU420 Invalid pitch
[14:26:43] [PASSED] YVU420 Different pitches
[14:26:43] [PASSED] YVU420 Different buffer offsets/pitches
[14:26:43] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[14:26:43] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[14:26:43] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[14:26:43] [PASSED] YVU420 Valid modifier
[14:26:43] [PASSED] YVU420 Different modifiers per plane
[14:26:43] [PASSED] YVU420 Modifier for inexistent plane
[14:26:43] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[14:26:43] [PASSED] X0L2 Normal sizes
[14:26:43] [PASSED] X0L2 Max sizes
[14:26:43] [PASSED] X0L2 Invalid pitch
[14:26:43] [PASSED] X0L2 Pitch greater than minimum required
[14:26:43] [PASSED] X0L2 Handle for inexistent plane
[14:26:43] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[14:26:43] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[14:26:43] [PASSED] X0L2 Valid modifier
[14:26:43] [PASSED] X0L2 Modifier for inexistent plane
[14:26:43] =========== [PASSED] drm_test_framebuffer_create ===========
[14:26:43] [PASSED] drm_test_framebuffer_free
[14:26:43] [PASSED] drm_test_framebuffer_init
[14:26:43] [PASSED] drm_test_framebuffer_init_bad_format
[14:26:43] [PASSED] drm_test_framebuffer_init_dev_mismatch
[14:26:43] [PASSED] drm_test_framebuffer_lookup
[14:26:43] [PASSED] drm_test_framebuffer_lookup_inexistent
[14:26:43] [PASSED] drm_test_framebuffer_modifiers_not_supported
[14:26:43] ================= [PASSED] drm_framebuffer =================
[14:26:43] ================ drm_gem_shmem (8 subtests) ================
[14:26:43] [PASSED] drm_gem_shmem_test_obj_create
[14:26:43] [PASSED] drm_gem_shmem_test_obj_create_private
[14:26:43] [PASSED] drm_gem_shmem_test_pin_pages
[14:26:43] [PASSED] drm_gem_shmem_test_vmap
[14:26:43] [PASSED] drm_gem_shmem_test_get_sg_table
[14:26:43] [PASSED] drm_gem_shmem_test_get_pages_sgt
[14:26:43] [PASSED] drm_gem_shmem_test_madvise
[14:26:43] [PASSED] drm_gem_shmem_test_purge
[14:26:43] ================== [PASSED] drm_gem_shmem ==================
[14:26:43] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[14:26:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[14:26:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[14:26:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[14:26:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[14:26:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[14:26:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[14:26:43] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[14:26:43] [PASSED] Automatic
[14:26:43] [PASSED] Full
[14:26:43] [PASSED] Limited 16:235
[14:26:43] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[14:26:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[14:26:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[14:26:43] [PASSED] drm_test_check_disable_connector
[14:26:43] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[14:26:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[14:26:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[14:26:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[14:26:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[14:26:43] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[14:26:43] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[14:26:43] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[14:26:43] [PASSED] drm_test_check_output_bpc_dvi
[14:26:43] [PASSED] drm_test_check_output_bpc_format_vic_1
[14:26:43] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[14:26:43] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[14:26:43] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[14:26:43] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[14:26:43] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[14:26:43] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[14:26:43] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[14:26:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[14:26:43] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[14:26:43] [PASSED] drm_test_check_broadcast_rgb_value
[14:26:43] [PASSED] drm_test_check_bpc_8_value
[14:26:43] [PASSED] drm_test_check_bpc_10_value
[14:26:43] [PASSED] drm_test_check_bpc_12_value
[14:26:43] [PASSED] drm_test_check_format_value
[14:26:43] [PASSED] drm_test_check_tmds_char_value
[14:26:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[14:26:43] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[14:26:43] [PASSED] drm_test_check_mode_valid
[14:26:43] [PASSED] drm_test_check_mode_valid_reject
[14:26:43] [PASSED] drm_test_check_mode_valid_reject_rate
[14:26:43] [PASSED] drm_test_check_mode_valid_reject_max_clock
[14:26:43] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[14:26:43] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[14:26:43] [PASSED] drm_test_check_infoframes
[14:26:43] [PASSED] drm_test_check_reject_avi_infoframe
[14:26:43] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[14:26:43] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[14:26:43] [PASSED] drm_test_check_reject_audio_infoframe
[14:26:43] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[14:26:43] ================= drm_managed (2 subtests) =================
[14:26:43] [PASSED] drm_test_managed_release_action
[14:26:43] [PASSED] drm_test_managed_run_action
[14:26:43] =================== [PASSED] drm_managed ===================
[14:26:43] =================== drm_mm (6 subtests) ====================
[14:26:43] [PASSED] drm_test_mm_init
[14:26:43] [PASSED] drm_test_mm_debug
[14:26:43] [PASSED] drm_test_mm_align32
[14:26:43] [PASSED] drm_test_mm_align64
[14:26:43] [PASSED] drm_test_mm_lowest
[14:26:43] [PASSED] drm_test_mm_highest
[14:26:43] ===================== [PASSED] drm_mm ======================
[14:26:43] ============= drm_modes_analog_tv (5 subtests) =============
[14:26:43] [PASSED] drm_test_modes_analog_tv_mono_576i
[14:26:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[14:26:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[14:26:43] [PASSED] drm_test_modes_analog_tv_pal_576i
[14:26:43] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[14:26:43] =============== [PASSED] drm_modes_analog_tv ===============
[14:26:43] ============== drm_plane_helper (2 subtests) ===============
[14:26:43] =============== drm_test_check_plane_state  ================
[14:26:43] [PASSED] clipping_simple
[14:26:43] [PASSED] clipping_rotate_reflect
[14:26:43] [PASSED] positioning_simple
[14:26:43] [PASSED] upscaling
[14:26:43] [PASSED] downscaling
[14:26:43] [PASSED] rounding1
[14:26:43] [PASSED] rounding2
[14:26:43] [PASSED] rounding3
[14:26:43] [PASSED] rounding4
[14:26:43] =========== [PASSED] drm_test_check_plane_state ============
[14:26:43] =========== drm_test_check_invalid_plane_state  ============
[14:26:43] [PASSED] positioning_invalid
[14:26:43] [PASSED] upscaling_invalid
[14:26:43] [PASSED] downscaling_invalid
[14:26:43] ======= [PASSED] drm_test_check_invalid_plane_state ========
[14:26:43] ================ [PASSED] drm_plane_helper =================
[14:26:43] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[14:26:43] ====== drm_test_connector_helper_tv_get_modes_check  =======
[14:26:43] [PASSED] None
[14:26:43] [PASSED] PAL
[14:26:43] [PASSED] NTSC
[14:26:43] [PASSED] Both, NTSC Default
[14:26:43] [PASSED] Both, PAL Default
[14:26:43] [PASSED] Both, NTSC Default, with PAL on command-line
[14:26:43] [PASSED] Both, PAL Default, with NTSC on command-line
[14:26:43] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[14:26:43] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[14:26:43] ================== drm_rect (9 subtests) ===================
[14:26:43] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[14:26:43] [PASSED] drm_test_rect_clip_scaled_not_clipped
[14:26:43] [PASSED] drm_test_rect_clip_scaled_clipped
[14:26:43] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[14:26:43] ================= drm_test_rect_intersect  =================
[14:26:43] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[14:26:43] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[14:26:43] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[14:26:43] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[14:26:43] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[14:26:43] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[14:26:43] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[14:26:43] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[14:26:43] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[14:26:43] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[14:26:43] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[14:26:43] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[14:26:43] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[14:26:43] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[14:26:43] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[14:26:43] ============= [PASSED] drm_test_rect_intersect =============
[14:26:43] ================ drm_test_rect_calc_hscale  ================
[14:26:43] [PASSED] normal use
[14:26:43] [PASSED] out of max range
[14:26:43] [PASSED] out of min range
[14:26:43] [PASSED] zero dst
[14:26:43] [PASSED] negative src
[14:26:43] [PASSED] negative dst
[14:26:43] ============ [PASSED] drm_test_rect_calc_hscale ============
[14:26:43] ================ drm_test_rect_calc_vscale  ================
[14:26:43] [PASSED] normal use
[14:26:43] [PASSED] out of max range
[14:26:43] [PASSED] out of min range
[14:26:43] [PASSED] zero dst
[14:26:43] [PASSED] negative src
[14:26:43] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[14:26:43] ============ [PASSED] drm_test_rect_calc_vscale ============
[14:26:43] ================== drm_test_rect_rotate  ===================
[14:26:43] [PASSED] reflect-x
[14:26:43] [PASSED] reflect-y
[14:26:43] [PASSED] rotate-0
[14:26:43] [PASSED] rotate-90
[14:26:43] [PASSED] rotate-180
[14:26:43] [PASSED] rotate-270
[14:26:43] ============== [PASSED] drm_test_rect_rotate ===============
[14:26:43] ================ drm_test_rect_rotate_inv  =================
[14:26:43] [PASSED] reflect-x
[14:26:43] [PASSED] reflect-y
[14:26:43] [PASSED] rotate-0
[14:26:43] [PASSED] rotate-90
[14:26:43] [PASSED] rotate-180
[14:26:43] [PASSED] rotate-270
[14:26:43] ============ [PASSED] drm_test_rect_rotate_inv =============
[14:26:43] ==================== [PASSED] drm_rect =====================
[14:26:43] ============ drm_sysfb_modeset_test (1 subtest) ============
[14:26:43] ============ drm_test_sysfb_build_fourcc_list  =============
[14:26:43] [PASSED] no native formats
[14:26:43] [PASSED] XRGB8888 as native format
[14:26:43] [PASSED] remove duplicates
[14:26:43] [PASSED] convert alpha formats
[14:26:43] [PASSED] random formats
[14:26:43] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[14:26:43] ============= [PASSED] drm_sysfb_modeset_test ==============
[14:26:43] ================== drm_fixp (2 subtests) ===================
[14:26:43] [PASSED] drm_test_int2fixp
[14:26:43] [PASSED] drm_test_sm2fixp
[14:26:43] ==================== [PASSED] drm_fixp =====================
[14:26:43] ============================================================
[14:26:43] Testing complete. Ran 621 tests: passed: 621
[14:26:43] Elapsed time: 30.794s total, 1.647s configuring, 28.981s building, 0.132s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[14:26:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:26:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[14:26:54] Starting KUnit Kernel (1/1)...
[14:26:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:26:54] ================= ttm_device (5 subtests) ==================
[14:26:54] [PASSED] ttm_device_init_basic
[14:26:54] [PASSED] ttm_device_init_multiple
[14:26:54] [PASSED] ttm_device_fini_basic
[14:26:54] [PASSED] ttm_device_init_no_vma_man
[14:26:54] ================== ttm_device_init_pools  ==================
[14:26:54] [PASSED] No DMA allocations, no DMA32 required
[14:26:54] [PASSED] DMA allocations, DMA32 required
[14:26:54] [PASSED] No DMA allocations, DMA32 required
[14:26:54] [PASSED] DMA allocations, no DMA32 required
[14:26:54] ============== [PASSED] ttm_device_init_pools ==============
[14:26:54] =================== [PASSED] ttm_device ====================
[14:26:54] ================== ttm_pool (8 subtests) ===================
[14:26:54] ================== ttm_pool_alloc_basic  ===================
[14:26:54] [PASSED] One page
[14:26:54] [PASSED] More than one page
[14:26:54] [PASSED] Above the allocation limit
[14:26:54] [PASSED] One page, with coherent DMA mappings enabled
[14:26:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:26:54] ============== [PASSED] ttm_pool_alloc_basic ===============
[14:26:54] ============== ttm_pool_alloc_basic_dma_addr  ==============
[14:26:54] [PASSED] One page
[14:26:54] [PASSED] More than one page
[14:26:54] [PASSED] Above the allocation limit
[14:26:54] [PASSED] One page, with coherent DMA mappings enabled
[14:26:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:26:54] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[14:26:54] [PASSED] ttm_pool_alloc_order_caching_match
[14:26:54] [PASSED] ttm_pool_alloc_caching_mismatch
[14:26:54] [PASSED] ttm_pool_alloc_order_mismatch
[14:26:54] [PASSED] ttm_pool_free_dma_alloc
[14:26:54] [PASSED] ttm_pool_free_no_dma_alloc
[14:26:54] [PASSED] ttm_pool_fini_basic
[14:26:54] ==================== [PASSED] ttm_pool =====================
[14:26:54] ================ ttm_resource (8 subtests) =================
[14:26:54] ================= ttm_resource_init_basic  =================
[14:26:54] [PASSED] Init resource in TTM_PL_SYSTEM
[14:26:54] [PASSED] Init resource in TTM_PL_VRAM
[14:26:54] [PASSED] Init resource in a private placement
[14:26:54] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[14:26:54] ============= [PASSED] ttm_resource_init_basic =============
[14:26:54] [PASSED] ttm_resource_init_pinned
[14:26:54] [PASSED] ttm_resource_fini_basic
[14:26:54] [PASSED] ttm_resource_manager_init_basic
[14:26:54] [PASSED] ttm_resource_manager_usage_basic
[14:26:54] [PASSED] ttm_resource_manager_set_used_basic
[14:26:54] [PASSED] ttm_sys_man_alloc_basic
[14:26:54] [PASSED] ttm_sys_man_free_basic
[14:26:54] ================== [PASSED] ttm_resource ===================
[14:26:54] =================== ttm_tt (15 subtests) ===================
[14:26:54] ==================== ttm_tt_init_basic  ====================
[14:26:54] [PASSED] Page-aligned size
[14:26:54] [PASSED] Extra pages requested
[14:26:54] ================ [PASSED] ttm_tt_init_basic ================
[14:26:54] [PASSED] ttm_tt_init_misaligned
[14:26:54] [PASSED] ttm_tt_fini_basic
[14:26:54] [PASSED] ttm_tt_fini_sg
[14:26:54] [PASSED] ttm_tt_fini_shmem
[14:26:54] [PASSED] ttm_tt_create_basic
[14:26:54] [PASSED] ttm_tt_create_invalid_bo_type
[14:26:54] [PASSED] ttm_tt_create_ttm_exists
[14:26:54] [PASSED] ttm_tt_create_failed
[14:26:54] [PASSED] ttm_tt_destroy_basic
[14:26:54] [PASSED] ttm_tt_populate_null_ttm
[14:26:54] [PASSED] ttm_tt_populate_populated_ttm
[14:26:54] [PASSED] ttm_tt_unpopulate_basic
[14:26:54] [PASSED] ttm_tt_unpopulate_empty_ttm
[14:26:54] [PASSED] ttm_tt_swapin_basic
[14:26:54] ===================== [PASSED] ttm_tt ======================
[14:26:54] =================== ttm_bo (14 subtests) ===================
[14:26:54] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[14:26:54] [PASSED] Cannot be interrupted and sleeps
[14:26:54] [PASSED] Cannot be interrupted, locks straight away
[14:26:54] [PASSED] Can be interrupted, sleeps
[14:26:54] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[14:26:54] [PASSED] ttm_bo_reserve_locked_no_sleep
[14:26:54] [PASSED] ttm_bo_reserve_no_wait_ticket
[14:26:54] [PASSED] ttm_bo_reserve_double_resv
[14:26:54] [PASSED] ttm_bo_reserve_interrupted
[14:26:54] [PASSED] ttm_bo_reserve_deadlock
[14:26:54] [PASSED] ttm_bo_unreserve_basic
[14:26:54] [PASSED] ttm_bo_unreserve_pinned
[14:26:54] [PASSED] ttm_bo_unreserve_bulk
[14:26:54] [PASSED] ttm_bo_fini_basic
[14:26:54] [PASSED] ttm_bo_fini_shared_resv
[14:26:54] [PASSED] ttm_bo_pin_basic
[14:26:54] [PASSED] ttm_bo_pin_unpin_resource
[14:26:54] [PASSED] ttm_bo_multiple_pin_one_unpin
[14:26:54] ===================== [PASSED] ttm_bo ======================
[14:26:54] ============== ttm_bo_validate (21 subtests) ===============
[14:26:54] ============== ttm_bo_init_reserved_sys_man  ===============
[14:26:54] [PASSED] Buffer object for userspace
[14:26:54] [PASSED] Kernel buffer object
[14:26:54] [PASSED] Shared buffer object
[14:26:54] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[14:26:54] ============== ttm_bo_init_reserved_mock_man  ==============
[14:26:54] [PASSED] Buffer object for userspace
[14:26:54] [PASSED] Kernel buffer object
[14:26:54] [PASSED] Shared buffer object
[14:26:54] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[14:26:54] [PASSED] ttm_bo_init_reserved_resv
[14:26:54] ================== ttm_bo_validate_basic  ==================
[14:26:54] [PASSED] Buffer object for userspace
[14:26:54] [PASSED] Kernel buffer object
[14:26:54] [PASSED] Shared buffer object
[14:26:54] ============== [PASSED] ttm_bo_validate_basic ==============
[14:26:54] [PASSED] ttm_bo_validate_invalid_placement
[14:26:54] ============= ttm_bo_validate_same_placement  ==============
[14:26:54] [PASSED] System manager
[14:26:54] [PASSED] VRAM manager
[14:26:54] ========= [PASSED] ttm_bo_validate_same_placement ==========
[14:26:54] [PASSED] ttm_bo_validate_failed_alloc
[14:26:54] [PASSED] ttm_bo_validate_pinned
[14:26:54] [PASSED] ttm_bo_validate_busy_placement
[14:26:54] ================ ttm_bo_validate_multihop  =================
[14:26:54] [PASSED] Buffer object for userspace
[14:26:54] [PASSED] Kernel buffer object
[14:26:54] [PASSED] Shared buffer object
[14:26:54] ============ [PASSED] ttm_bo_validate_multihop =============
[14:26:54] ========== ttm_bo_validate_no_placement_signaled  ==========
[14:26:54] [PASSED] Buffer object in system domain, no page vector
[14:26:54] [PASSED] Buffer object in system domain with an existing page vector
[14:26:54] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[14:26:54] ======== ttm_bo_validate_no_placement_not_signaled  ========
[14:26:54] [PASSED] Buffer object for userspace
[14:26:54] [PASSED] Kernel buffer object
[14:26:54] [PASSED] Shared buffer object
[14:26:54] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[14:26:54] [PASSED] ttm_bo_validate_move_fence_signaled
[14:26:54] ========= ttm_bo_validate_move_fence_not_signaled  =========
[14:26:54] [PASSED] Waits for GPU
[14:26:54] [PASSED] Tries to lock straight away
[14:26:54] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[14:26:54] [PASSED] ttm_bo_validate_happy_evict
[14:26:54] [PASSED] ttm_bo_validate_all_pinned_evict
[14:26:54] [PASSED] ttm_bo_validate_allowed_only_evict
[14:26:54] [PASSED] ttm_bo_validate_deleted_evict
[14:26:54] [PASSED] ttm_bo_validate_busy_domain_evict
[14:26:54] [PASSED] ttm_bo_validate_evict_gutting
[14:26:54] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[14:26:54] ================= [PASSED] ttm_bo_validate =================
[14:26:54] ============================================================
[14:26:54] Testing complete. Ran 101 tests: passed: 101
[14:26:54] Elapsed time: 11.021s total, 1.654s configuring, 9.101s building, 0.234s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 872 bytes --]

== Series Details ==

Series: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM
URL   : https://patchwork.freedesktop.org/series/161978/
State : success

== Summary ==

CI Bug Log - changes from xe-4590-616fe8160929511b0679615cda09751043490b18_BAT -> xe-pw-161978v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 13)
------------------------------

  Missing    (1): bat-bmg-3 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4590-616fe8160929511b0679615cda09751043490b18 -> xe-pw-161978v1

  IGT_8765: 8765
  xe-4590-616fe8160929511b0679615cda09751043490b18: 616fe8160929511b0679615cda09751043490b18
  xe-pw-161978v1: 161978v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/index.html

[-- Attachment #2: Type: text/html, Size: 1420 bytes --]

✗ Xe.CI.FULL: failure for Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 31715 bytes --]

== Series Details ==

Series: Fix Adaptive Sync SDP for PR with Link ON + Auxless ALPM
URL   : https://patchwork.freedesktop.org/series/161978/
State : failure

== Summary ==

CI Bug Log - changes from xe-4590-616fe8160929511b0679615cda09751043490b18_FULL -> xe-pw-161978v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-161978v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-161978v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-161978v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-lnl:          [PASS][1] -> [FAIL][2] +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-lnl-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@xe_exec_system_allocator@process-many-execqueues-new-busy-nomemset:
    - shard-bmg:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-bmg-3/igt@xe_exec_system_allocator@process-many-execqueues-new-busy-nomemset.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-5/igt@xe_exec_system_allocator@process-many-execqueues-new-busy-nomemset.html

  
Known issues
------------

  Here are the changes found in xe-pw-161978v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#1124]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_big_fb@yf-tiled-8bpp-rotate-180.html

  * igt@kms_bw@linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#367]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-1920x1080p:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#367])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_bw@linear-tiling-3-displays-1920x1080p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-b-dp-1:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2652]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-5/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-b-dp-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#2887]) +4 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2887]) +7 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-9/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#373]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2252]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#307] / [Intel XE#6974])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_content_protection@dp-mst-type-1.html
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2390] / [Intel XE#6974]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-9/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@uevent@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][17] ([Intel XE#6707])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-2/igt@kms_content_protection@uevent@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#1424])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_cursor_crc@cursor-random-32x10.html
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2320])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-9/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2321])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2244])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#776])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@psr1:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2374])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#1421]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#7178]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#7178])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#4141]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#7061]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#651]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#2311]) +8 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2313]) +6 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#7061]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#656]) +7 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#1503])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#7130]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#7283])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#7283])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#599])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#2763] / [Intel XE#6886]) +4 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1439] / [Intel XE#836])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@package-g7:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#6813])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_pm_rpm@package-g7.html
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#6814])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-9/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#1406] / [Intel XE#4608]) +3 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf@pipe-b-edp-1.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1128] / [Intel XE#1406])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@pr-sprite-render:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_psr@pr-sprite-render.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#3414] / [Intel XE#3904])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#1127])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_sharpness_filter@filter-basic:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#6503])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@kms_sharpness_filter@filter-basic.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#362])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_eudebug@basic-vm-bind-metadata-discovery:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#4837])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html

  * igt@xe_eudebug@discovery-race:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4837]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@xe_eudebug@discovery-race.html

  * igt@xe_eudebug_online@debugger-reopen:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#4837] / [Intel XE#6665])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_eudebug_online@debugger-reopen.html

  * igt@xe_eudebug_online@pagefault-write-stress:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#6665])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_eudebug_online@pagefault-write-stress.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-vram:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#4837] / [Intel XE#6665])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-vram.html

  * igt@xe_evict@evict-large-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#6540] / [Intel XE#688]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_evict@evict-large-multi-vm.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][58] -> [INCOMPLETE][59] ([Intel XE#6321])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-bmg-5/igt@xe_evict@evict-mixed-many-threads-small.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#1392]) +2 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-bind:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#2322])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-imm:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#7136]) +3 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_exec_fault_mode@once-multi-queue-userptr-rebind-imm.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#7136]) +5 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@xe_exec_fault_mode@twice-multi-queue-userptr.html

  * igt@xe_exec_multi_queue@few-execs-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#6874]) +6 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_exec_multi_queue@few-execs-userptr.html

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-basic:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#6874]) +8 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-9/igt@xe_exec_multi_queue@max-queues-preempt-mode-basic.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          [PASS][66] -> [FAIL][67] ([Intel XE#5625]) +1 other test fail
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#7138]) +2 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-invalidate.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#7138]) +2 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_exec_threads@threads-multi-queue-mixed-userptr.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#6281])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  * igt@xe_multigpu_svm@mgpu-xgpu-access-basic:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#6964])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_multigpu_svm@mgpu-xgpu-access-basic.html

  * igt@xe_oa@non-zero-reason-all:
    - shard-lnl:          [PASS][72] -> [FAIL][73] ([Intel XE#7334]) +1 other test fail
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-lnl-6/igt@xe_oa@non-zero-reason-all.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-6/igt@xe_oa@non-zero-reason-all.html

  * igt@xe_pm@d3cold-i2c:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#5694])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_pm@d3cold-i2c.html
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#5694])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-9/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pm@s3-d3cold-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#2284] / [Intel XE#366])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_pm@s3-d3cold-basic-exec.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-rpm:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#4733])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@xe_pxp@pxp-stale-bo-exec-post-rpm.html

  * igt@xe_query@multigpu-query-topology-l3-bank-mask:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#944])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_query@multigpu-query-topology-l3-bank-mask.html

  * igt@xe_vm@out-of-memory:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#5745])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-3/igt@xe_vm@out-of-memory.html

  
#### Possible fixes ####

  * igt@device_reset@unbind-reset-rebind:
    - shard-lnl:          [DMESG-WARN][80] -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-lnl-5/igt@device_reset@unbind-reset-rebind.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-4/igt@device_reset@unbind-reset-rebind.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][82] ([Intel XE#2142]) -> [PASS][83] +1 other test pass
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_configfs@ctx-restore-mid-bb:
    - shard-lnl:          [ABORT][84] ([Intel XE#7169]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-lnl-5/igt@xe_configfs@ctx-restore-mid-bb.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-lnl-4/igt@xe_configfs@ctx-restore-mid-bb.html

  * igt@xe_exec_system_allocator@many-64k-mmap-remap:
    - shard-bmg:          [DMESG-FAIL][86] -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-bmg-2/igt@xe_exec_system_allocator@many-64k-mmap-remap.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-3/igt@xe_exec_system_allocator@many-64k-mmap-remap.html

  * igt@xe_exec_system_allocator@threads-many-stride-new-nomemset:
    - shard-bmg:          [SKIP][88] ([Intel XE#6703]) -> [PASS][89] +3 other tests pass
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-stride-new-nomemset.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-3/igt@xe_exec_system_allocator@threads-many-stride-new-nomemset.html

  * igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_prepare:
    - shard-bmg:          [ABORT][90] -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-bmg-5/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_prepare.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-6/igt@xe_fault_injection@vm-bind-fail-xe_pt_update_ops_prepare.html

  
#### Warnings ####

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-bmg:          [SKIP][92] ([Intel XE#6703]) -> [SKIP][93] ([Intel XE#2252])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-bmg-2/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-3/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-bmg:          [SKIP][94] ([Intel XE#6703]) -> [SKIP][95] ([Intel XE#2375])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-bmg-2/igt@kms_feature_discovery@dp-mst.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-3/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render:
    - shard-bmg:          [SKIP][96] ([Intel XE#6703]) -> [SKIP][97] ([Intel XE#7061])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-bmg:          [ABORT][98] ([Intel XE#5466]) -> [ABORT][99] ([Intel XE#5466] / [Intel XE#6652])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4590-616fe8160929511b0679615cda09751043490b18/shard-bmg-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/shard-bmg-3/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6813
  [Intel XE#6814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6814
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7130
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7169]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7169
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7334]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7334
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4590-616fe8160929511b0679615cda09751043490b18 -> xe-pw-161978v1

  IGT_8765: 8765
  xe-4590-616fe8160929511b0679615cda09751043490b18: 616fe8160929511b0679615cda09751043490b18
  xe-pw-161978v1: 161978v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-161978v1/index.html

[-- Attachment #2: Type: text/html, Size: 36000 bytes --]

[PATCH 2/4] drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink

[Ankit Nautiyal]

Currently we do not support VRR with HDMI so skip vrr compute
config step for DP PCON with HDMI sink.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 00cbc126fb36..7a58e1f8acea 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -42,7 +42,14 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 	case DRM_MODE_CONNECTOR_DisplayPort:
 		if (connector->mst.dp)
 			return false;
+
 		intel_dp = intel_attached_dp(connector);
+		/*
+		 * VRR via PCON is currently unsupported.
+		 * TODO: Add support for VRR for DP HDMI2.1 PCON.
+		 */
+		if (intel_dp_has_hdmi_sink(intel_dp))
+			return false;
 
 		if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
 			return false;
-- 
2.45.2

[PATCH 00/14] Fix Adaptive Sync SDP for Panel Replay

[Ankit Nautiyal]

Enable Adaptive Sync SDP for Panel replay + auxless ALPM.
First few patches are fixes in existing AS SDP enablement.
Later patches add the support to send AS SDP for Panel replay with Link
ON and with auxless ALPM (Link-Off). 

This series is in continuation from discussions in [1] [2].
[1] https://lore.kernel.org/all/1b8c6c6de1e5fe0db83e6ae942dfee7e6f950767.camel@intel.com/
[2] https://lore.kernel.org/all/aPtqdAxDwiuQZbrn@intel.com/

Rev2:
Add few fixes in AS_SDP and Lobf.

Rev3:
Add patch to avoid VRR with PCON.

Rev4:
- Address review comments.
- Drop Lobf changes. To be sent as a separate series.

Rev5:
- Add AS SDP version and PR and VRR specific bits in drm_dp.h.
- Modify AS SDP compute config to accomodate PR with Link On and Link
  Off.
- Program Downspread Ctrl DPCD bits.
- Make way for T1 and T2 AS SDP transmission timing/position.

Ankit Nautiyal (14):
  drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP
  drm/i915/vrr: Avoid vrr for PCON with HDMI2.1 sink
  drm/i915/dp: Add a helper to decide if AS SDP is needed
  drm/i915/dp: Update the helper intel_dp_needs_as_sdp() for CMRR
  include/drm/display/dp: Add field for storing AS SDP version
  drm/i915/dp: Use version field of AS SDP data structure
  drm/i915/dp: Compute AS SDP after PSR and LOBF
  drm/i915/dp: Add AS SDP support for PR with link ON
  drm/i915/psr: Add helper to check if PR is with link OFF
  drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless
    ALPM
  drm/i915/dp: Program AS SDP DB[1:0] for PR with Link off
  include/drm/display/dp: Add DPCD registers for configuring Panel
    Replay + VRR
  drm/i915/display: Add member to store AS SDP transmission time
  drm/i915/dp: Account for AS_SDP guardband only when enabled

 drivers/gpu/drm/display/drm_dp_helper.c       |  1 +
 drivers/gpu/drm/i915/display/intel_alpm.c     | 21 +++++++-
 drivers/gpu/drm/i915/display/intel_display.c  |  3 +-
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 48 ++++++++++++++-----
 .../drm/i915/display/intel_dp_link_training.c | 10 +++-
 .../drm/i915/display/intel_dp_link_training.h |  3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 13 +++++
 drivers/gpu/drm/i915/display/intel_psr.h      |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 10 ++++
 include/drm/display/drm_dp.h                  |  9 ++++
 include/drm/display/drm_dp_helper.h           |  1 +
 13 files changed, 105 insertions(+), 18 deletions(-)

-- 
2.45.2

[PATCH 08/14] drm/i915/dp: Add AS SDP support for PR with link ON

[Ankit Nautiyal]

Adaptive Sync SDP (AS SDP) is also used for Panel Replay (PR).
For PR with Link ON, the AS SDP version V1 is used. When using
AS SDP Version 1, AS SDP payload and parity bytes are all set to zeroes.

Bspec: 75639
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d08db4938638..5952db6197cf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3115,7 +3115,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 				  struct intel_crtc_state *crtc_state)
 {
 	return crtc_state->vrr.enable ||
-	       crtc_state->cmrr.enable;
+	       crtc_state->cmrr.enable ||
+	       crtc_state->has_panel_replay;
 }
 
 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
@@ -3137,6 +3138,16 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->length = 0x9;
 	as_sdp->duration_incr_ms = 0;
 	as_sdp->version = 0x2;
+
+	if (crtc_state->vrr.enable)
+		as_sdp->version = 0x2;
+	else
+		as_sdp->version = 0x1;
+
+	/* No payload data bytes for Version 1 */
+	if (as_sdp->version == 0x1)
+		return;
+
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
 	if (crtc_state->cmrr.enable) {
@@ -5005,6 +5016,10 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	sdp->sdp_header.HB2 = as_sdp->version;
 	sdp->sdp_header.HB3 = as_sdp->length;
 
+	/* No Payload Data bytes for Version 1 */
+	if (as_sdp->version == 0x1)
+		return length;
+
 	/* Fill AS (Adaptive Sync) SDP Payload */
 	sdp->db[0] = as_sdp->mode;
 	sdp->db[1] = as_sdp->vtotal & 0xFF;
-- 
2.45.2