[PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox

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* [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox
@ 2026-09-24 20:54 Karthik Poosa
  2026-09-24 20:54 ` [PATCH v6 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
                   ` (15 more replies)
  0 siblings, 16 replies; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

This series adds CRI-specific temperature sensor handling to the Xe
hwmon implementation and fixes couple of hwmon issues.

CRI platforms may report unavailable temperature sensors and support
a variable number of VRAM temperature channels depending on platform
configuration. This series adds the required sensor presence checks and
uses platform-reported thermal configuration data to expose only valid
temperature-related hwmon attributes.

The series also corrects the telemetry group selection used for memory
controller temperature reporting.

v2:
 - Address review comments from Sashiko, Badal and Raag.
 - Enable IEEE 754 temperature decoding for MMIO temperature registers.
  - Split sensor validity check into mailbox vs MMIO handling; add
    is_temp_available() / is_temp_is_visible().
 - Temporarily disable memory controller and PCIe temperatures on CRI.

v3:
  - Detect unavailable temperature sensors: rephrase a debug log.
  - Decode mailbox temperatures as 8-bit sign-magnitude values instead of
    s8.
  - Use VRAM temperature sensor count from thermal config on CRI: address
    review comments from sashiko-bot@kernel.org and Rodrigo.
  - Decode CRI temperature registers as IEEE-754: reject temperatures that
    overflow long on 32-bit systems.

v4:
  - Address review comments and issues report from Rodrigo and
    sashiko-bot@kernel.org.
  - Decode mailbox temperatures as 8-bit sign-magnitude values.
  - Cache sensor availability during registration.
  - Enable memory controller and pcie sensors for CRI.
  - Derive the VRAM channel count from the CRI MSU enable mask.
  - Use CRI-specific package and VRAM temperature registers.
  - Handle the CRI memory controller and pcie sensor offsets as per CRI.

v5:
 - Remove the unintended IGT prefix from the patch titles.

v6:
 - Address issues reported by sashiko-bot@kernel.org. 
 - Add VRAM individual channel CRI_VRAM_TEMPERATURE_N register for CRI.

Karthik Poosa (13):
  drm/xe/hwmon: Handle pcode read failures of
    xe_hwmon_pcode_rmw_power_limit
  drm/xe/hwmon: Decode mailbox temperature as sign-magnitude
  drm/xe/hwmon: Fix memory controller thermal data handling
  drm/xe/hwmon: Add helpers to validate thermal sensor readings
  drm/xe/hwmon: Handle unavailable memory controller sensors
  drm/xe/hwmon: Detect unavailable PCIe thermal sensors
  drm/xe/hwmon: Consolidate temperature sensor availability checks
  drm/xe/hwmon: Cache temperature availability to reduce probe time
  drm/xe/hwmon: use CRI-specific package and VRAM temperature registers
  drm/xe/hwmon: Add platform-aware VRAM thermal channel support
  drm/xe/hwmon: Decode CRI temperature registers as IEEE-754
  drm/xe/hwmon: Update memory controller temperature offset for CRI
  drm/xe/hwmon: Update PCIE temperature sensor offset for CRI

 drivers/gpu/drm/xe/regs/xe_pcode_regs.h |   4 +
 drivers/gpu/drm/xe/xe_device_types.h    |   4 +
 drivers/gpu/drm/xe/xe_hwmon.c           | 453 ++++++++++++++++++++----
 drivers/gpu/drm/xe/xe_pci.c             |   4 +
 drivers/gpu/drm/xe/xe_pci_types.h       |   2 +
 5 files changed, 395 insertions(+), 72 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH v6 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-28  0:11   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude Karthik Poosa
                   ` (14 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

Return early when the pcode read operation fails in
xe_hwmon_pcode_rmw_power_limit() and check the returned error in
callers to avoid updating power limit settings with invalid data.

Fixes: 8aa7306631f0 ("drm/xe/hwmon: Fix xe_hwmon_power_max_write")
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
v2: Address sashiko-bot@kernel.org review comments. Return -EIO instead of
    0 on errors in the sysfs store callback to prevent potential userspace
    infinite loops.

 drivers/gpu/drm/xe/xe_hwmon.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 5edeac961ec3..be3fb6733b6f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -232,9 +232,11 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
 						  READ_PSYSGPU_POWER_LIMIT :
 						  READ_PACKAGE_POWER_LIMIT,
 						  prepare_power_limit_param2(hwmon)), &val0, &val1);
-	if (ret)
-		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
+	if (ret) {
+		drm_err(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
 			channel, val0, val1, ret);
+		return ret;
+	}
 
 	if (attr == PL1_HWMON_ATTR)
 		val0 = (val0 & ~clr) | set;
@@ -394,7 +396,9 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channe
 		if (hwmon->xe->info.has_mbx_power_limits) {
 			drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n",
 				PWR_ATTR_TO_STR(attr), channel);
-			xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
+			ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
+			if (ret)
+				goto unlock;
 			xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
 		} else {
 			reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);
@@ -679,11 +683,13 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
 
 	mutex_lock(&hwmon->hwmon_lock);
 
-	if (hwmon->xe->info.has_mbx_power_limits)
-		xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
-	else
+	if (hwmon->xe->info.has_mbx_power_limits) {
+		if (xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy))
+			count = -EIO;
+	} else {
 		r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
 				  PWR_LIM_TIME, rxy);
+	}
 
 	mutex_unlock(&hwmon->hwmon_lock);
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
  2026-09-24 20:54 ` [PATCH v6 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-28  0:15   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 03/13] drm/xe/hwmon: Fix memory controller thermal data handling Karthik Poosa
                   ` (13 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

The mailbox temperature is an 8-bit sign-magnitude value (bit 7 sign,
bits 6:0 magnitude, range -127..127), not two's-complement. Casting the
raw byte to s8 decodes negative readings incorrectly.

Add mbx_temp_decode(), store the raw byte as u8, and use it in
get_mc_temp() and get_pcie_temp() so temperatures are decoded correctly.

Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index be3fb6733b6f..57199ea00a60 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -104,6 +104,10 @@ enum sensor_attr_power {
 /* Index of memory controller in READ_THERMAL_DATA output */
 #define TEMP_INDEX_MCTRL	2
 
+/* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
+#define TEMP_MBX_SIGN		BIT(7)
+#define TEMP_MBX_MAG		GENMASK(6, 0)
+
 /* Maximum characters in hwmon label name */
 #define MAX_LABEL_SIZE		16
 
@@ -139,8 +143,8 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
-	/** @value: signed value from each sensor */
-	s8 value[U8_MAX];
+	/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
+	u8 value[U8_MAX];
 	/** @vram_label: vram label names */
 	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
 };
@@ -814,6 +818,14 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	return ret;
 }
 
+/* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
+static int mbx_temp_decode(u8 value)
+{
+	int temp = value & TEMP_MBX_MAG;
+
+	return (value & TEMP_MBX_SIGN) ? -temp : temp;
+}
+
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
@@ -830,7 +842,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 	}
 
 	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
-		average += hwmon->temp.value[i];
+		average += mbx_temp_decode(hwmon->temp.value[i]);
 
 	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
 	*val = average * MILLIDEGREE_PER_DEGREE;
@@ -853,7 +865,7 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-	*val = (s8)data * MILLIDEGREE_PER_DEGREE;
+	*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
 
 	return 0;
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 03/13] drm/xe/hwmon: Fix memory controller thermal data handling
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
  2026-09-24 20:54 ` [PATCH v6 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
  2026-09-24 20:54 ` [PATCH v6 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-24 20:54 ` [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
                   ` (12 subsequent siblings)
  15 siblings, 0 replies; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

Read all required thermal groups in get_mc_temp() and use an aligned
u32 buffer for PCODE accesses to avoid unaligned memory accesses and
ensure correct MC temperature reporting.


Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
v2: Fix a typo of variable name in kernel-doc. (sashiko)

 drivers/gpu/drm/xe/xe_hwmon.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 57199ea00a60..c743867a2ebf 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -143,8 +143,12 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
-	/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
-	u8 value[U8_MAX];
+	union {
+		/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
+		u8 value[U8_MAX + 1];
+		/** @dword: sensor values as dwords, u32-aligned for pcode reads */
+		u32 dword[DIV_ROUND_UP(U8_MAX + 1, sizeof(u32))];
+	};
 	/** @vram_label: vram label names */
 	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
 };
@@ -829,16 +833,16 @@ static int mbx_temp_decode(u8 value)
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
-	u32 *dword = (u32 *)hwmon->temp.value;
 	s32 average = 0;
 	int ret, i;
 
-	for (i = 0; i < DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32)); i++) {
+	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
-				    (dword + i), NULL);
+				    &hwmon->temp.dword[i], NULL);
 		if (ret)
 			return ret;
-		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i, dword[i]);
+		drm_dbg(&hwmon->xe->drm, "thermal data for group %d val 0x%x\n", i,
+			hwmon->temp.dword[i]);
 	}
 
 	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (2 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 03/13] drm/xe/hwmon: Fix memory controller thermal data handling Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-28  0:19   ` Rodrigo Vivi
  2026-09-28 19:38   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors Karthik Poosa
                   ` (11 subsequent siblings)
  15 siblings, 2 replies; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

Add mmio_temp_valid() and mbx_temp_valid() to check whether a temperature
sensor reading is valid. An MMIO value of 0xFFFFFFFF or a mailbox value of
0xFF indicates the sensor is unavailable.

Gate these checks behind has_mbx_temp_sentinel, enabled on CRI currently.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h |  2 ++
 drivers/gpu/drm/xe/xe_hwmon.c        | 16 ++++++++++++++++
 drivers/gpu/drm/xe/xe_pci.c          |  2 ++
 drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
 4 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 4661bfce2f4e..87554605fa41 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -202,6 +202,8 @@ struct xe_device {
 		 * pcode mailbox commands.
 		 */
 		u8 has_mbx_power_limits:1;
+		/** @info.has_mbx_temp_sentinel: Device has temperature-unavailable sentinels */
+		u8 has_mbx_temp_sentinel:1;
 		/** @info.has_mbx_thermal_info: Device supports thermal mailbox commands */
 		u8 has_mbx_thermal_info:1;
 		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index c743867a2ebf..8a1dbe708828 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -104,6 +104,9 @@ enum sensor_attr_power {
 /* Index of memory controller in READ_THERMAL_DATA output */
 #define TEMP_INDEX_MCTRL	2
 
+/* Mailbox sentinel reported for an unavailable temperature sensor */
+#define TEMP_MBX_INVALID	0xFF
+
 /* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
 #define TEMP_MBX_SIGN		BIT(7)
 #define TEMP_MBX_MAG		GENMASK(6, 0)
@@ -822,6 +825,19 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 	return ret;
 }
 
+static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
+{
+	return hwmon->xe->info.has_mbx_temp_sentinel ? value != U32_MAX
+						     : value != 0;
+}
+
+/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
+static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
+{
+	return hwmon->xe->info.has_mbx_temp_sentinel ? value != TEMP_MBX_INVALID
+						     : value != 0;
+}
+
 /* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
 static int mbx_temp_decode(u8 value)
 {
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index d66d5a0339ae..e656fc012902 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -476,6 +476,7 @@ static const struct xe_device_desc cri_desc = {
 	.has_gsc_nvm = 1,
 	.has_i2c = true,
 	.has_mbx_power_limits = true,
+	.has_mbx_temp_sentinel = true,
 	.has_mbx_thermal_info = true,
 	.has_mert = true,
 	.has_pre_prod_wa = 1,
@@ -796,6 +797,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	/* runtime fusing may force flat_ccs to disabled later */
 	xe->info.has_flat_ccs = desc->has_flat_ccs;
 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
+	xe->info.has_mbx_temp_sentinel = desc->has_mbx_temp_sentinel;
 	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
 	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
 	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index fed509ff601e..0041ec5676d3 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -50,6 +50,7 @@ struct xe_device_desc {
 	u8 has_late_bind:1;
 	u8 has_llc:1;
 	u8 has_mbx_power_limits:1;
+	u8 has_mbx_temp_sentinel:1;
 	u8 has_mbx_thermal_info:1;
 	u8 has_mert:1;
 	u8 has_pre_prod_wa:1;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (3 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-28 16:08   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors Karthik Poosa
                   ` (10 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

Skip memory controller sensors that report invalid readings when
computing the average temperature in get_mc_temp(). Return -ENXIO when
no valid sensor data is available, and allow the helper to be used as
an availability probe by making the output parameter optional.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
---
 drivers/gpu/drm/xe/xe_hwmon.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 8a1dbe708828..83466b8d8d27 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -849,8 +849,8 @@ static int mbx_temp_decode(u8 value)
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	int ret, i, count = 0;
 	s32 average = 0;
-	int ret, i;
 
 	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
@@ -861,11 +861,23 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 			hwmon->temp.dword[i]);
 	}
 
-	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
+	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
+		if (!mbx_temp_valid(hwmon, hwmon->temp.value[i]))
+			continue;
 		average += mbx_temp_decode(hwmon->temp.value[i]);
+		count++;
+	}
+
+	if (!count) {
+		drm_dbg(&hwmon->xe->drm, "Memory controller temperature unavailable!\n");
+		return -ENXIO;
+	}
+
+	average /= count;
+
+	if (val)
+		*val = average * MILLIDEGREE_PER_DEGREE;
 
-	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
-	*val = average * MILLIDEGREE_PER_DEGREE;
 	return 0;
 }
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (4 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-28 16:10   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks Karthik Poosa
                   ` (9 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

Return -ENXIO from get_pcie_temp() when the mailbox reports an invalid
reading, so the PCIe sensor can be treated as unavailable. Guard the val
store so the function can be used purely as an availability probe. No
sysfs visibility changes.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 83466b8d8d27..4a7cf913e6c8 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -897,7 +897,13 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-	*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
+	if (!mbx_temp_valid(hwmon, data)) {
+		drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n");
+		return -ENXIO;
+	}
+
+	if (val)
+		*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
 
 	return 0;
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (5 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-28 19:39   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time Karthik Poosa
                   ` (8 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

Replace is_vram_ch_available() with a generalized is_temp_available()
that validates PKG, VRAM, per-channel VRAM, memory controller and PCIe
sensors using the new validity helpers. Rename the existing callers to
the new helper.

Use is_temp_available() from xe_hwmon_temp_is_visible() so attributes for
sensors that are not present are not exposed during hwmon registration.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
---
 drivers/gpu/drm/xe/xe_hwmon.c | 64 ++++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 4a7cf913e6c8..052b25a233d6 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -1002,19 +1002,39 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
 	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
 }
 
-static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
+static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
-	int vram_id = channel - CHANNEL_VRAM_N;
-	struct xe_reg vram_reg;
+	struct xe_reg reg;
+	u32 reg_val;
 
-	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
-	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
-		return false;
+	switch (channel) {
+	case CHANNEL_PKG:
+	case CHANNEL_VRAM:
+	case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
+		reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
+		if (!xe_reg_is_valid(reg))
+			return false;
+
+		reg_val = xe_mmio_read32(mmio, reg);
+		if (!mmio_temp_valid(hwmon, reg_val)) {
+			drm_dbg(&hwmon->xe->drm,
+				"channel %d temperature unavailable, val 0x%x\n", channel, reg_val);
+			return false;
+		}
+
+		if (channel >= CHANNEL_VRAM_N)
+			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
+				"vram_ch_%d", channel - CHANNEL_VRAM_N);
 
-	/* Create label only for available vram channel */
-	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
-	return true;
+		return true;
+	case CHANNEL_MCTRL:
+		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
+	case CHANNEL_PCIE:
+		return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);
+	default:
+		return false;
+	}
 }
 
 static umode_t
@@ -1024,14 +1044,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_emergency:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
-		case CHANNEL_VRAM:
-			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return (is_temp_available(hwmon, channel) &&
+				hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN]) ? 0444 : 0;
+		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_vram_ch_available(hwmon, channel) &&
+			return (is_temp_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1039,14 +1058,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_crit:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
-		case CHANNEL_VRAM:
-			return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
+			return (is_temp_available(hwmon, channel) &&
+				hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT]) ? 0444 : 0;
+		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_vram_ch_available(hwmon, channel) &&
+			return (is_temp_available(hwmon, channel) &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1054,7 +1072,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_max:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return hwmon->temp.limit[TEMP_LIMIT_PKG_MAX] ? 0444 : 0;
+			return (is_temp_available(hwmon, channel) &&
+				hwmon->temp.limit[TEMP_LIMIT_PKG_MAX]) ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -1063,13 +1082,10 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		switch (channel) {
 		case CHANNEL_PKG:
 		case CHANNEL_VRAM:
-			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
-								channel)) ? 0444 : 0;
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return hwmon->temp.count ? 0444 : 0;
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
+			return is_temp_available(hwmon, channel) ? 0444 : 0;
 		default:
 			return 0;
 		}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (6 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-28 21:17   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 09/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers Karthik Poosa
                   ` (7 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

Avoid probing temperature sensor availability from the hwmon is_visible()
callback. For MCTRL and PCIe channels, that path can trigger repeated
blocking mailbox reads while sysfs attributes are being created, increasing
probe time and making attribute creation sensitive to transient failures.

Probe temperature availability once during preregistration and cache the
result for subsequent visibility checks.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
---
 drivers/gpu/drm/xe/xe_hwmon.c | 39 +++++++++++++++++++++++------------
 1 file changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 052b25a233d6..92280248f1e9 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -146,6 +146,8 @@ struct xe_hwmon_thermal_info {
 	};
 	/** @count: no of temperature sensors available for the platform */
 	u8 count;
+	/** @available: temperature sensor availability cached at registration */
+	bool available[CHANNEL_MAX];
 	union {
 		/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
 		u8 value[U8_MAX + 1];
@@ -1002,7 +1004,7 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
 	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
 }
 
-static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
+static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
 	struct xe_reg reg;
@@ -1023,10 +1025,6 @@ static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
 			return false;
 		}
 
-		if (channel >= CHANNEL_VRAM_N)
-			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
-				"vram_ch_%d", channel - CHANNEL_VRAM_N);
-
 		return true;
 	case CHANNEL_MCTRL:
 		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
@@ -1037,6 +1035,22 @@ static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
 	}
 }
 
+static void xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
+{
+	int channel;
+
+	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
+		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
+
+	for (channel = 0; channel < CHANNEL_MAX; channel++) {
+		hwmon->temp.available[channel] = xe_hwmon_temp_probe(hwmon, channel);
+		if (hwmon->temp.available[channel] &&
+		    in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			snprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N], MAX_LABEL_SIZE,
+				 "vram_ch_%d", channel - CHANNEL_VRAM_N);
+	}
+}
+
 static umode_t
 xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 {
@@ -1046,11 +1060,11 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_PKG:
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN]) ? 0444 : 0;
 		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1060,11 +1074,11 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_PKG:
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT]) ? 0444 : 0;
 		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1072,7 +1086,7 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	case hwmon_temp_max:
 		switch (channel) {
 		case CHANNEL_PKG:
-			return (is_temp_available(hwmon, channel) &&
+			return (hwmon->temp.available[channel] &&
 				hwmon->temp.limit[TEMP_LIMIT_PKG_MAX]) ? 0444 : 0;
 		default:
 			return 0;
@@ -1085,7 +1099,7 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 		case CHANNEL_MCTRL:
 		case CHANNEL_PCIE:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
-			return is_temp_available(hwmon, channel) ? 0444 : 0;
+			return hwmon->temp.available[channel] ? 0444 : 0;
 		default:
 			return 0;
 		}
@@ -1627,8 +1641,7 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
 			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
 
-	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
-		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
+	xe_hwmon_init_temp_info(hwmon);
 }
 
 int xe_hwmon_register(struct xe_device *xe)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 09/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (7 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-24 20:54 ` [PATCH v6 10/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support Karthik Poosa
                   ` (6 subsequent siblings)
  15 siblings, 0 replies; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

Crescent Island uses different MMIO offsets for package and VRAM
temperature than Battlemage. Add CRI-specific register definitions
and select them in xe_hwmon_get_reg() for REG_TEMP handling.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
v2: Update VRAM individual channel temperatures register offset
    for CRI.

v3:
 - Remove unused CRI_MSU_VRAM_ENABLE register.
 - Sort the CRI HWMON registers by increasing offset in xe_pcode_regs.h.

 drivers/gpu/drm/xe/regs/xe_pcode_regs.h | 3 +++
 drivers/gpu/drm/xe/xe_hwmon.c           | 9 ++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
index c63b409d7a82..a969661f0c95 100644
--- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
@@ -28,6 +28,9 @@
 #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
 
 #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
+#define CRI_PACKAGE_TEMPERATURE			XE_REG(0x138344)
+#define CRI_VRAM_TEMPERATURE			XE_REG(0x138348)
 #define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
+#define CRI_VRAM_TEMPERATURE_N(n)		XE_REG(0x138a00 + ((n) * (sizeof(u32))))
 
 #endif /* _XE_PCODE_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 92280248f1e9..1b2e2fbe43c8 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -276,7 +276,14 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 
 	switch (hwmon_reg) {
 	case REG_TEMP:
-		if (xe->info.platform == XE_BATTLEMAGE || xe->info.platform == XE_CRESCENTISLAND) {
+		if (xe->info.platform == XE_CRESCENTISLAND) {
+			if (channel == CHANNEL_PKG)
+				return CRI_PACKAGE_TEMPERATURE;
+			else if (channel == CHANNEL_VRAM)
+				return CRI_VRAM_TEMPERATURE;
+			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+				return CRI_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
+		} else if (xe->info.platform == XE_BATTLEMAGE) {
 			if (channel == CHANNEL_PKG)
 				return BMG_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 10/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (8 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 09/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-29 18:04   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
                   ` (5 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

On CRI, derive the number of available VRAM temperature channels from the
CRI_MSU_VRAM_ENABLE register, where each enabled MSU contributes
VRAM_CHANNELS_PER_MSU channels.
 
Increase the maximum supported VRAM channel count to 80 and use the
derived count to control VRAM sensor enumeration, channel access, and
VRAM label allocation. Add a has_fixed_vram_channels platform flag to
preserve the existing fixed-channel behavior on non-CRI platforms.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---

v2:
 - Use the highest enabled MSU index to determine the VRAM channel bound
   instead of counting enabled MSUs. A sparse mask could expose channels
   beyond the allocated label array, leaving the label pointer unset and
   potentially hanging during sysfs reads.
 - Also return an error when no temperature label matches the requested
   channel.

 drivers/gpu/drm/xe/regs/xe_pcode_regs.h |   1 +
 drivers/gpu/drm/xe/xe_device_types.h    |   2 +
 drivers/gpu/drm/xe/xe_hwmon.c           | 164 +++++++++++++++++++++---
 drivers/gpu/drm/xe/xe_pci.c             |   2 +
 drivers/gpu/drm/xe/xe_pci_types.h       |   1 +
 5 files changed, 154 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
index a969661f0c95..d9e4847dd68e 100644
--- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
@@ -28,6 +28,7 @@
 #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
 
 #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
+#define CRI_MSU_VRAM_ENABLE			XE_REG(0x138340)
 #define CRI_PACKAGE_TEMPERATURE			XE_REG(0x138344)
 #define CRI_VRAM_TEMPERATURE			XE_REG(0x138348)
 #define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 87554605fa41..8a1ca65f5665 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -184,6 +184,8 @@ struct xe_device {
 		u8 has_drm_ras:1;
 		/** @info.has_fan_control: Device supports fan control */
 		u8 has_fan_control:1;
+		/** @info.has_fixed_vram_channels: Device has fixed VRAM temperature channels */
+		u8 has_fixed_vram_channels:1;
 		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
 		u8 has_flat_ccs:1;
 		/** @info.has_gsc_nvm: Device has gsc non-volatile memory */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 1b2e2fbe43c8..0422db647d11 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -39,7 +39,11 @@ enum xe_hwmon_reg_operation {
 	REG_READ64,
 };
 
-#define MAX_VRAM_CHANNELS      (16)
+#define MAX_VRAM_CHANNELS	80
+#define FIXED_VRAM_CHANNELS	16
+
+/* Each MSU enable bit maps to one VRAM subsystem of 4 channels. */
+#define VRAM_CHANNELS_PER_MSU	4
 
 enum xe_hwmon_channel {
 	CHANNEL_CARD,
@@ -48,6 +52,7 @@ enum xe_hwmon_channel {
 	CHANNEL_MCTRL,
 	CHANNEL_PCIE,
 	CHANNEL_VRAM_N,
+	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
 	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
 	CHANNEL_MAX,
 };
@@ -144,18 +149,22 @@ struct xe_hwmon_thermal_info {
 		/** @data: temperature limits in dwords */
 		u32 data[DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32))];
 	};
-	/** @count: no of temperature sensors available for the platform */
+	/** @count: temperature sensors count from READ_THERMAL_CONFIG */
 	u8 count;
+	/** @vram_count: exclusive upper bound for VRAM temperature channel indices */
+	u8 vram_count;
 	/** @available: temperature sensor availability cached at registration */
 	bool available[CHANNEL_MAX];
+	/** @msu_mask: VRAM subsystem enable mask read from MMIO */
+	u32 msu_mask;
 	union {
 		/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
 		u8 value[U8_MAX + 1];
 		/** @dword: sensor values as dwords, u32-aligned for pcode reads */
 		u32 dword[DIV_ROUND_UP(U8_MAX + 1, sizeof(u32))];
 	};
-	/** @vram_label: vram label names */
-	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
+	/** @vram_label: vram label names, dynamically allocated based on vram_count */
+	char (*vram_label)[MAX_LABEL_SIZE];
 };
 
 /**
@@ -269,6 +278,14 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
 	return ret;
 }
 
+static bool xe_hwmon_vram_channel_enabled(const struct xe_hwmon *hwmon, int index)
+{
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
+		return hwmon->temp.msu_mask & BIT(index / VRAM_CHANNELS_PER_MSU);
+
+	return true;
+}
+
 static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
 				      int channel)
 {
@@ -281,14 +298,16 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 				return CRI_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
 				return CRI_VRAM_TEMPERATURE;
-			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
+				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
 				return CRI_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
 		} else if (xe->info.platform == XE_BATTLEMAGE) {
 			if (channel == CHANNEL_PKG)
 				return BMG_PACKAGE_TEMPERATURE;
 			else if (channel == CHANNEL_VRAM)
 				return BMG_VRAM_TEMPERATURE;
-			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
+				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
 				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
 		} else if (xe->info.platform == XE_DG2) {
 			if (channel == CHANNEL_PKG)
@@ -798,6 +817,70 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
+			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
 			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL),
 	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
 			   HWMON_P_CAP,
@@ -812,15 +895,37 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
 static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
 	u32 config = 0;
 	int ret;
 
+	/*
+	 * Only CRI reports dynamic VRAM channel state. Fixed-channel platforms
+	 * set the count up front so those sensors stay visible even if the thermal
+	 * mailbox reads below fail.
+	 */
+	if (hwmon->xe->info.has_fixed_vram_channels)
+		hwmon->temp.vram_count = FIXED_VRAM_CHANNELS;
+
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND) {
+		hwmon->temp.msu_mask = xe_mmio_read32(mmio, CRI_MSU_VRAM_ENABLE);
+		hwmon->temp.vram_count = fls(hwmon->temp.msu_mask) * VRAM_CHANNELS_PER_MSU;
+		drm_dbg(&hwmon->xe->drm, "MSU VRAM enable mask 0x%x, VRAM channel bound %d\n",
+			hwmon->temp.msu_mask, hwmon->temp.vram_count);
+		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS) {
+			drm_warn(&hwmon->xe->drm,
+				 "VRAM channel bound %d exceeds max %d, clamping\n",
+				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
+			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
+		}
+	}
+
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
 			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
 	if (ret)
 		return ret;
 
-	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%x val1 0x%x\n",
+	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%08x val1 0x%08x\n",
 		hwmon->temp.data[0], hwmon->temp.data[1]);
 
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0),
@@ -1025,6 +1130,14 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
 		if (!xe_reg_is_valid(reg))
 			return false;
 
+		/*
+		 * On CRI, VRAM channel presence comes from the MSU enable mask
+		 * (applied in xe_hwmon_get_reg()); the temperature register's
+		 * 0xffffffff sentinel is not reliable for VRAM channels.
+		 */
+		if (hwmon->xe->info.platform == XE_CRESCENTISLAND && channel >= CHANNEL_VRAM_N)
+			return true;
+
 		reg_val = xe_mmio_read32(mmio, reg);
 		if (!mmio_temp_valid(hwmon, reg_val)) {
 			drm_dbg(&hwmon->xe->drm,
@@ -1042,20 +1155,31 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
 	}
 }
 
-static void xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
+static int xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
 {
+	struct device *dev = hwmon->xe->drm.dev;
 	int channel;
 
 	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
 		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
 
+	/* vram_count is known only after reading thermal info above. */
+	if (hwmon->temp.vram_count) {
+		hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
+						      MAX_LABEL_SIZE, GFP_KERNEL);
+		if (!hwmon->temp.vram_label)
+			return -ENOMEM;
+	}
+
 	for (channel = 0; channel < CHANNEL_MAX; channel++) {
 		hwmon->temp.available[channel] = xe_hwmon_temp_probe(hwmon, channel);
-		if (hwmon->temp.available[channel] &&
-		    in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+		if (hwmon->temp.available[channel] && hwmon->temp.vram_label &&
+		    in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 			snprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N], MAX_LABEL_SIZE,
 				 "vram_ch_%d", channel - CHANNEL_VRAM_N);
 	}
+
+	return 0;
 }
 
 static umode_t
@@ -1551,8 +1675,10 @@ static int xe_hwmon_read_label(struct device *dev,
 			*str = "mctrl";
 		else if (channel == CHANNEL_PCIE)
 			*str = "pcie";
-		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
+		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
 			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
+		else
+			return -EOPNOTSUPP;
 		return 0;
 	case hwmon_power:
 	case hwmon_energy:
@@ -1580,7 +1706,7 @@ static const struct hwmon_chip_info hwmon_chip_info = {
 	.info = hwmon_info,
 };
 
-static void
+static int
 xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 {
 	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
@@ -1648,7 +1774,7 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
 		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
 			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
 
-	xe_hwmon_init_temp_info(hwmon);
+	return xe_hwmon_init_temp_info(hwmon);
 }
 
 int xe_hwmon_register(struct xe_device *xe)
@@ -1677,7 +1803,9 @@ int xe_hwmon_register(struct xe_device *xe)
 	hwmon->xe = xe;
 	xe->hwmon = hwmon;
 
-	xe_hwmon_get_preregistration_info(hwmon);
+	ret = xe_hwmon_get_preregistration_info(hwmon);
+	if (ret)
+		goto err_null_hwmon;
 
 	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
 
@@ -1687,10 +1815,14 @@ int xe_hwmon_register(struct xe_device *xe)
 								hwmon_groups);
 	if (IS_ERR(hwmon->hwmon_dev)) {
 		drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
-		xe->hwmon = NULL;
-		return PTR_ERR(hwmon->hwmon_dev);
+		ret = PTR_ERR(hwmon->hwmon_dev);
+		goto err_null_hwmon;
 	}
 
 	return 0;
+
+err_null_hwmon:
+	xe->hwmon = NULL;
+	return ret;
 }
 MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY");
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index e656fc012902..fa32436ecf6f 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -416,6 +416,7 @@ static const struct xe_device_desc bmg_desc = {
 	.dma_mask_size = 46,
 	.has_display = true,
 	.has_fan_control = true,
+	.has_fixed_vram_channels = true,
 	.has_flat_ccs = 1,
 	.has_mbx_power_limits = true,
 	.has_mbx_thermal_info = true,
@@ -794,6 +795,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_cached_pt = desc->has_cached_pt;
 	xe->info.has_drm_ras = desc->has_drm_ras;
 	xe->info.has_fan_control = desc->has_fan_control;
+	xe->info.has_fixed_vram_channels = desc->has_fixed_vram_channels;
 	/* runtime fusing may force flat_ccs to disabled later */
 	xe->info.has_flat_ccs = desc->has_flat_ccs;
 	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 0041ec5676d3..4d1048ca7abe 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -42,6 +42,7 @@ struct xe_device_desc {
 	u8 has_display:1;
 	u8 has_drm_ras:1;
 	u8 has_fan_control:1;
+	u8 has_fixed_vram_channels:1;
 	u8 has_flat_ccs:1;
 	u8 has_gsc_nvm:1;
 	u8 has_heci_gscfi:1;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (9 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 10/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-29 18:24   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI Karthik Poosa
                   ` (4 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

CRI temperature registers encode package and VRAM temperatures as
IEEE-754 floating-point values. Decode these values before exposing
them through hwmon.
 
Use integer-based IEEE-754 decoding since kernel code does not use
floating-point operations and hwmon reports integer temperatures.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Assisted-by: LLM
---

v2: Reject temperatures that overflow long on 32-bit.

v3: Replace magic numbers in xe_hwmon_temperature_decode() with named
    REG_GENMASK()/REG_BIT() defines and use REG_FIELD_GET() for
    extraction. (Rodrigo)

 drivers/gpu/drm/xe/xe_hwmon.c | 92 +++++++++++++++++++++++++++++------
 1 file changed, 78 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 0422db647d11..76251d949b11 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -1239,6 +1239,69 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
 	}
 }
 
+#define IEEE754_SIGN		REG_BIT(31)
+#define IEEE754_EXP_MASK	REG_GENMASK(30, 23)
+#define IEEE754_MANTISSA_MASK	REG_GENMASK(22, 0)
+#define IEEE754_EXP_BIAS	127 /* Exponent bias to obtain the actual exponent */
+#define IEEE754_MANTISSA_BITS	23 /* Mantissa width and implicit leading-1 bit position */
+#define IEEE754_EXP_SPECIAL	0xff /* reserved exponent value encoding infinity or NaN */
+
+/**
+ * xe_hwmon_temperature_decode - Decode an IEEE-754 temperature register value
+ * @reg_val: The raw register value to decode
+ *
+ * IEEE-754 single-precision format:
+ *
+ *  31 30                         23 22                         0
+ * +--+-----------------------------+----------------------------+
+ * | S|          exponent           |          fraction          |
+ * +--+-----------------------------+----------------------------+
+ *
+ * value = (-1)^S * 1.fraction * 2^(exponent - 127)
+ *
+ * Return: 0 on success or an error if @reg_val is non-finite or cannot be
+ * represented in millidegrees Celsius.
+ */
+static int xe_hwmon_temperature_decode(u32 reg_val, long *temperature)
+{
+	u32 exponent = REG_FIELD_GET(IEEE754_EXP_MASK, reg_val);
+	u32 mantissa = REG_FIELD_GET(IEEE754_MANTISSA_MASK, reg_val);
+	s64 value;
+	int shift;
+
+	/* Exponent 0xff encodes infinity or NaN. */
+	if (exponent == IEEE754_EXP_SPECIAL)
+		return -EINVAL;
+
+	/* Subnormal values are smaller than one millidegree Celsius. */
+	if (!exponent) {
+		*temperature = 0;
+		return 0;
+	}
+
+	value = (s64)(mantissa | BIT(IEEE754_MANTISSA_BITS)) * MILLIDEGREE_PER_DEGREE;
+	shift = exponent - (IEEE754_EXP_BIAS + IEEE754_MANTISSA_BITS);
+	if (shift >= 0) {
+		if (shift >= BITS_PER_LONG || value > (LONG_MAX >> shift))
+			return -ERANGE;
+		value <<= shift;
+	} else if (shift > -64) {
+		value >>= -shift;
+	} else {
+		value = 0;
+	}
+
+	/* Ensure the magnitude fits in long, which is 32-bit on some arches. */
+	if (value > LONG_MAX)
+		return -ERANGE;
+
+	if (reg_val & IEEE754_SIGN)
+		value = -value;
+
+	*temperature = value;
+	return 0;
+}
+
 static int
 xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 {
@@ -1248,26 +1311,27 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
 	switch (attr) {
 	case hwmon_temp_input:
 		switch (channel) {
-		case CHANNEL_PKG:
-		case CHANNEL_VRAM:
-			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
-
-			/* HW register value is in degrees Celsius, convert to millidegrees. */
-			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
-			return 0;
 		case CHANNEL_MCTRL:
 			return get_mc_temp(hwmon, val);
 		case CHANNEL_PCIE:
 			return get_pcie_temp(hwmon, val);
+		case CHANNEL_PKG:
+		case CHANNEL_VRAM:
 		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
 			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
-			/*
-			 * This temperature format is 24 bit [31:8] signed integer and 8 bit
-			 * [7:0] fraction.
-			 */
-			*val = (s32)(REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val)) *
-				(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
-				 MILLIDEGREE_PER_DEGREE;
+			if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
+				return xe_hwmon_temperature_decode((u32)reg_val, val);
+			} else if (channel >= CHANNEL_VRAM_N) {
+				/*
+				 * This temperature format is 24 bit [31:8] signed integer and 8 bit
+				 * [7:0] fraction for platforms before CRI.
+				 */
+				*val = (s32)REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val) *
+					(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
+					MILLIDEGREE_PER_DEGREE;
+			} else {
+				*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
+			}
 			return 0;
 		default:
 			return -EOPNOTSUPP;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (10 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-29 18:27   ` Rodrigo Vivi
  2026-09-24 20:54 ` [PATCH v6 13/13] drm/xe/hwmon: Update PCIE temperature sensor " Karthik Poosa
                   ` (3 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

On CRI the memory controller temperatures moved in the READ_THERMAL_DATA
output: they now occupy bytes 16..19 instead of starting at byte 2.

Read and average the CRI memory controller sensors from bytes 16..19,
keeping the existing byte 2..count-1 range for earlier platforms. Only
the group(s) covering the used bytes are fetched.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 76251d949b11..79240d4aadd3 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -109,6 +109,10 @@ enum sensor_attr_power {
 /* Index of memory controller in READ_THERMAL_DATA output */
 #define TEMP_INDEX_MCTRL	2
 
+/* On CRI the memory controller temperatures are READ_THERMAL_DATA bytes 16..19. */
+#define CRI_TEMP_INDEX_MCTRL	16
+#define CRI_TEMP_MCTRL_COUNT	4
+
 /* Mailbox sentinel reported for an unavailable temperature sensor */
 #define TEMP_MBX_INVALID	0xFF
 
@@ -963,10 +967,19 @@ static int mbx_temp_decode(u8 value)
 static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
-	int ret, i, count = 0;
+	int ret, i, start, end, count = 0;
 	s32 average = 0;
 
-	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
+	/* CRI relocated the memory controller temperatures to READ_THERMAL_DATA bytes 16..19. */
+	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
+		start = CRI_TEMP_INDEX_MCTRL;
+		end = CRI_TEMP_INDEX_MCTRL + CRI_TEMP_MCTRL_COUNT;
+	} else {
+		start = TEMP_INDEX_MCTRL;
+		end = hwmon->temp.count - 1;
+	}
+
+	for (i = start / sizeof(u32); i < DIV_ROUND_UP(end, sizeof(u32)); i++) {
 		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
 				    &hwmon->temp.dword[i], NULL);
 		if (ret)
@@ -975,7 +988,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 			hwmon->temp.dword[i]);
 	}
 
-	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
+	for (i = start; i < end; i++) {
 		if (!mbx_temp_valid(hwmon, hwmon->temp.value[i]))
 			continue;
 		average += mbx_temp_decode(hwmon->temp.value[i]);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* [PATCH v6 13/13] drm/xe/hwmon: Update PCIE temperature sensor offset for CRI
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (11 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI Karthik Poosa
@ 2026-09-24 20:54 ` Karthik Poosa
  2026-09-29 18:29   ` Rodrigo Vivi
  2026-09-24 21:05 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev3) Patchwork
                   ` (2 subsequent siblings)
  15 siblings, 1 reply; 36+ messages in thread
From: Karthik Poosa @ 2026-09-24 20:54 UTC (permalink / raw)
  To: intel-xe
  Cc: rodrigo.vivi, anshuman.gupta, badal.nilawar, raag.jadav,
	riana.tauro, sk.anirban, mallesh.koujalagi, soham.purkait,
	Karthik Poosa

On Crescent Island, the PCIe temperature sensor is reported in
READ_THERMAL_DATA group 5, byte 0. Add support for reading the sensor
from this mailbox location.

Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 79240d4aadd3..fcb1d2f14f5a 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -113,6 +113,9 @@ enum sensor_attr_power {
 #define CRI_TEMP_INDEX_MCTRL	16
 #define CRI_TEMP_MCTRL_COUNT	4
 
+/* On CRI the PCIe temperature is READ_THERMAL_DATA byte 20 (group 5, low byte). */
+#define CRI_PCIE_SENSOR_GROUP_ID	5
+
 /* Mailbox sentinel reported for an unavailable temperature sensor */
 #define TEMP_MBX_INVALID	0xFF
 
@@ -1011,16 +1014,21 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
 static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
+	u32 group = PCIE_SENSOR_GROUP_ID;
 	u32 data = 0;
 	int ret;
 
+	/* CRI relocated the PCIe temperature to a different data group. */
+	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
+		group = CRI_PCIE_SENSOR_GROUP_ID;
+
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA,
-						  PCIE_SENSOR_GROUP_ID), &data, NULL);
+						  group), &data, NULL);
 	if (ret)
 		return ret;
 
-	/* Sensor offset is different for G21 */
-	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21)
+	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21 &&
+	    hwmon->xe->info.platform != XE_CRESCENTISLAND)
 		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
 
 	data = REG_FIELD_GET(TEMP_MASK, data);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 36+ messages in thread

* ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev3)
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (12 preceding siblings ...)
  2026-09-24 20:54 ` [PATCH v6 13/13] drm/xe/hwmon: Update PCIE temperature sensor " Karthik Poosa
@ 2026-09-24 21:05 ` Patchwork
  2026-09-24 22:34 ` ✓ Xe.CI.BAT: " Patchwork
  2026-09-25 11:16 ` ✗ Xe.CI.FULL: failure " Patchwork
  15 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2026-09-24 21:05 UTC (permalink / raw)
  To: Karthik Poosa; +Cc: intel-xe

== Series Details ==

Series: drm/xe/hwmon: Update hwmon thermal mailbox (rev3)
URL   : https://patchwork.freedesktop.org/series/174898/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[21:03:48] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:03:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:04:13] Starting KUnit Kernel (1/1)...
[21:04:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:04:13] ============= refcount_interrupt (4 subtests) ==============
[21:04:13] [PASSED] test_single_irq_change
[21:04:13] [PASSED] test_nested_irq_change
[21:04:13] [PASSED] test_multiple_irq_change
[21:04:13] [PASSED] test_irq_save
[21:04:13] =============== [PASSED] refcount_interrupt ================
[21:04:13] ================= gpu_buddy (14 subtests) ==================
[21:04:13] [PASSED] gpu_test_buddy_alloc_limit
[21:04:13] [PASSED] gpu_test_buddy_alloc_optimistic
[21:04:13] [PASSED] gpu_test_buddy_alloc_pessimistic
[21:04:13] [PASSED] gpu_test_buddy_alloc_pathological
[21:04:13] [PASSED] gpu_test_buddy_alloc_contiguous
[21:04:13] [PASSED] gpu_test_buddy_alloc_clear
[21:04:13] [PASSED] gpu_test_buddy_alloc_range
[21:04:13] [PASSED] gpu_test_buddy_alloc_range_bias
[21:04:14] [PASSED] gpu_test_buddy_fragmentation_performance
[21:04:15] [PASSED] gpu_test_buddy_dirty_tracker_performance
[21:04:15] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[21:04:15] [PASSED] gpu_test_buddy_offset_aligned_allocation
[21:04:15] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[21:04:15] [PASSED] gpu_test_buddy_addr_to_block
[21:04:15] ==================== [PASSED] gpu_buddy ====================
[21:04:15] ============================================================
[21:04:15] Testing complete. Ran 18 tests: passed: 18
[21:04:15] Elapsed time: 27.223s total, 4.419s configuring, 20.685s building, 2.052s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:04:15] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:04:17] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:04:52] Starting KUnit Kernel (1/1)...
[21:04:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:04:52] ============= refcount_interrupt (4 subtests) ==============
[21:04:52] [PASSED] test_single_irq_change
[21:04:52] [PASSED] test_nested_irq_change
[21:04:52] [PASSED] test_multiple_irq_change
[21:04:52] [PASSED] test_irq_save
[21:04:52] =============== [PASSED] refcount_interrupt ================
[21:04:52] ================== guc_buf (11 subtests) ===================
[21:04:52] [PASSED] test_smallest
[21:04:52] [PASSED] test_largest
[21:04:52] [PASSED] test_granular
[21:04:52] [PASSED] test_unique
[21:04:52] [PASSED] test_overlap
[21:04:52] [PASSED] test_reusable
[21:04:52] [PASSED] test_too_big
[21:04:52] [PASSED] test_flush
[21:04:52] [PASSED] test_lookup
[21:04:52] [PASSED] test_data
[21:04:52] [PASSED] test_class
[21:04:52] ===================== [PASSED] guc_buf =====================
[21:04:52] =================== guc_dbm (7 subtests) ===================
[21:04:52] [PASSED] test_empty
[21:04:52] [PASSED] test_default
[21:04:52] ======================== test_size  ========================
[21:04:52] [PASSED] 4
[21:04:52] [PASSED] 8
[21:04:52] [PASSED] 32
[21:04:52] [PASSED] 256
[21:04:52] ==================== [PASSED] test_size ====================
[21:04:52] ======================= test_reuse  ========================
[21:04:52] [PASSED] 4
[21:04:52] [PASSED] 8
[21:04:52] [PASSED] 32
[21:04:52] [PASSED] 256
[21:04:52] =================== [PASSED] test_reuse ====================
[21:04:52] =================== test_range_overlap  ====================
[21:04:52] [PASSED] 4
[21:04:52] [PASSED] 8
[21:04:52] [PASSED] 32
[21:04:52] [PASSED] 256
[21:04:52] =============== [PASSED] test_range_overlap ================
[21:04:52] =================== test_range_compact  ====================
[21:04:52] [PASSED] 4
[21:04:52] [PASSED] 8
[21:04:52] [PASSED] 32
[21:04:52] [PASSED] 256
[21:04:52] =============== [PASSED] test_range_compact ================
[21:04:52] ==================== test_range_spare  =====================
[21:04:52] [PASSED] 4
[21:04:52] [PASSED] 8
[21:04:52] [PASSED] 32
[21:04:52] [PASSED] 256
[21:04:52] ================ [PASSED] test_range_spare =================
[21:04:52] ===================== [PASSED] guc_dbm =====================
[21:04:52] =================== guc_idm (6 subtests) ===================
[21:04:52] [PASSED] bad_init
[21:04:52] [PASSED] no_init
[21:04:52] [PASSED] init_fini
[21:04:52] [PASSED] check_used
[21:04:52] [PASSED] check_quota
[21:04:52] [PASSED] check_all
[21:04:52] ===================== [PASSED] guc_idm =====================
[21:04:52] ============== guc_klv_helpers (13 subtests) ===============
[21:04:52] [PASSED] test_count
[21:04:52] [PASSED] test_encode_u32
[21:04:52] [PASSED] test_encode_u64
[21:04:52] [PASSED] test_encode_string
[21:04:52] [PASSED] test_encode_object_raw
[21:04:52] [PASSED] test_encode_object_klv
[21:04:52] [PASSED] test_encode_object_nested
[21:04:52] [PASSED] test_encode_object_basic
[21:04:52] ===================== test_decode_u16  =====================
[21:04:52] [PASSED] empty
[21:04:52] [PASSED] valid
[21:04:52] [PASSED] max
[21:04:52] [PASSED] big
[21:04:52] [PASSED] long
[21:04:52] ================= [PASSED] test_decode_u16 =================
[21:04:52] ===================== test_decode_u32  =====================
[21:04:52] [PASSED] empty
[21:04:52] [PASSED] valid
[21:04:52] [PASSED] max
[21:04:52] [PASSED] long
[21:04:52] ================= [PASSED] test_decode_u32 =================
[21:04:52] ===================== test_decode_u64  =====================
[21:04:52] [PASSED] empty
[21:04:52] [PASSED] short
[21:04:52] [PASSED] valid
[21:04:52] [PASSED] max
[21:04:52] [PASSED] long
[21:04:52] ================= [PASSED] test_decode_u64 =================
[21:04:52] ===================== test_decode_str  =====================
[21:04:52] [PASSED] empty
[21:04:52] [PASSED] one
[21:04:52] [PASSED] one_trash
[21:04:52] [PASSED] two
[21:04:52] [PASSED] two_trash
[21:04:52] [PASSED] three
[21:04:52] [PASSED] dword
[21:04:52] [PASSED] four
[21:04:52] [PASSED] five
[21:04:52] [PASSED] six
[21:04:52] [PASSED] seven
[21:04:52] [PASSED] qword
[21:04:52] ================= [PASSED] test_decode_str =================
[21:04:52] [PASSED] test_print
[21:04:52] ================= [PASSED] guc_klv_helpers =================
[21:04:52] =================== xe_log (4 subtests) ====================
[21:04:52] [PASSED] demo_cper
[21:04:52] [PASSED] demo_dmesg
[21:04:52] ======================= test_dmesg  ========================
[21:04:52] [PASSED] test_fatal
[21:04:52] [PASSED] test_fatal_tile
[21:04:52] [PASSED] test_fatal_gt
[21:04:52] [PASSED] test_fatal_comp
[21:04:52] [PASSED] test_fatal_comp_tile
[21:04:52] [PASSED] test_fatal_comp_gt
[21:04:52] [PASSED] test_fatal_all
[21:04:52] [PASSED] test_recoverable
[21:04:52] [PASSED] test_recoverable_tile
[21:04:52] [PASSED] test_recoverable_gt
[21:04:52] [PASSED] test_recoverable_comp
[21:04:52] [PASSED] test_recoverable_comp_tile
[21:04:52] [PASSED] test_recoverable_comp_gt
[21:04:52] [PASSED] test_recoverable_all
[21:04:52] [PASSED] test_info
[21:04:52] [PASSED] test_info_tile
[21:04:52] [PASSED] test_info_gt
[21:04:52] [PASSED] test_info_err
[21:04:52] [PASSED] test_info_comp
[21:04:52] [PASSED] test_info_comp_tile
[21:04:52] [PASSED] test_info_comp_gt
[21:04:52] [PASSED] test_info_all
[21:04:52] [PASSED] test_hw_fatal
[21:04:52] [PASSED] test_hw_recoverable
[21:04:52] [PASSED] test_hw_corrected
[21:04:52] [PASSED] test_hw_informational
[21:04:52] =================== [PASSED] test_dmesg ====================
[21:04:52] ====================== test_invalid  =======================
[21:04:52] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[21:04:52] ================== [SKIPPED] test_invalid ==================
[21:04:52] ===================== [PASSED] xe_log ======================
[21:04:52] ================== no_relay (3 subtests) ===================
[21:04:52] [PASSED] xe_drops_guc2pf_if_not_ready
[21:04:52] [PASSED] xe_drops_guc2vf_if_not_ready
[21:04:52] [PASSED] xe_rejects_send_if_not_ready
[21:04:52] ==================== [PASSED] no_relay =====================
[21:04:52] ================== pf_relay (14 subtests) ==================
[21:04:52] [PASSED] pf_rejects_guc2pf_too_short
[21:04:52] [PASSED] pf_rejects_guc2pf_too_long
[21:04:52] [PASSED] pf_rejects_guc2pf_no_payload
[21:04:52] [PASSED] pf_fails_no_payload
[21:04:52] [PASSED] pf_fails_bad_origin
[21:04:52] [PASSED] pf_fails_bad_type
[21:04:52] [PASSED] pf_txn_reports_error
[21:04:52] [PASSED] pf_txn_sends_pf2guc
[21:04:52] [PASSED] pf_sends_pf2guc
[21:04:52] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:04:52] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:04:52] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:04:52] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:04:52] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:04:52] ==================== [PASSED] pf_relay =====================
[21:04:52] ================== vf_relay (3 subtests) ===================
[21:04:52] [PASSED] vf_rejects_guc2vf_too_short
[21:04:52] [PASSED] vf_rejects_guc2vf_too_long
[21:04:52] [PASSED] vf_rejects_guc2vf_no_payload
[21:04:52] ==================== [PASSED] vf_relay =====================
[21:04:52] ================ pf_gt_config (9 subtests) =================
[21:04:52] [PASSED] fair_contexts_1vf
[21:04:52] [PASSED] fair_doorbells_1vf
[21:04:52] [PASSED] fair_ggtt_1vf
[21:04:52] ====================== fair_vram_1vf  ======================
[21:04:52] [PASSED] 3.50 GiB
[21:04:52] [PASSED] 11.5 GiB
[21:04:52] [PASSED] 15.5 GiB
[21:04:52] [PASSED] 31.5 GiB
[21:04:52] [PASSED] 63.5 GiB
[21:04:52] [PASSED] 1.91 GiB
[21:04:52] ================== [PASSED] fair_vram_1vf ==================
[21:04:52] ================ fair_vram_1vf_admin_only  =================
[21:04:52] [PASSED] 3.50 GiB
[21:04:52] [PASSED] 11.5 GiB
[21:04:52] [PASSED] 15.5 GiB
[21:04:52] [PASSED] 31.5 GiB
[21:04:52] [PASSED] 63.5 GiB
[21:04:52] [PASSED] 1.91 GiB
[21:04:52] ============ [PASSED] fair_vram_1vf_admin_only =============
[21:04:52] ====================== fair_contexts  ======================
[21:04:52] [PASSED] 1 VF
[21:04:52] [PASSED] 2 VFs
[21:04:52] [PASSED] 3 VFs
[21:04:52] [PASSED] 4 VFs
[21:04:52] [PASSED] 5 VFs
[21:04:52] [PASSED] 6 VFs
[21:04:52] [PASSED] 7 VFs
[21:04:52] [PASSED] 8 VFs
[21:04:52] [PASSED] 9 VFs
[21:04:52] [PASSED] 10 VFs
[21:04:52] [PASSED] 11 VFs
[21:04:52] [PASSED] 12 VFs
[21:04:52] [PASSED] 13 VFs
[21:04:52] [PASSED] 14 VFs
[21:04:52] [PASSED] 15 VFs
[21:04:52] [PASSED] 16 VFs
[21:04:52] [PASSED] 17 VFs
[21:04:52] [PASSED] 18 VFs
[21:04:52] [PASSED] 19 VFs
[21:04:52] [PASSED] 20 VFs
[21:04:52] [PASSED] 21 VFs
[21:04:52] [PASSED] 22 VFs
[21:04:52] [PASSED] 23 VFs
[21:04:52] [PASSED] 24 VFs
[21:04:52] [PASSED] 25 VFs
[21:04:52] [PASSED] 26 VFs
[21:04:52] [PASSED] 27 VFs
[21:04:52] [PASSED] 28 VFs
[21:04:52] [PASSED] 29 VFs
[21:04:52] [PASSED] 30 VFs
[21:04:52] [PASSED] 31 VFs
[21:04:52] [PASSED] 32 VFs
[21:04:52] [PASSED] 33 VFs
[21:04:52] [PASSED] 34 VFs
[21:04:52] [PASSED] 35 VFs
[21:04:52] [PASSED] 36 VFs
[21:04:52] [PASSED] 37 VFs
[21:04:52] [PASSED] 38 VFs
[21:04:52] [PASSED] 39 VFs
[21:04:52] [PASSED] 40 VFs
[21:04:52] [PASSED] 41 VFs
[21:04:52] [PASSED] 42 VFs
[21:04:52] [PASSED] 43 VFs
[21:04:52] [PASSED] 44 VFs
[21:04:52] [PASSED] 45 VFs
[21:04:52] [PASSED] 46 VFs
[21:04:52] [PASSED] 47 VFs
[21:04:52] [PASSED] 48 VFs
[21:04:52] [PASSED] 49 VFs
[21:04:52] [PASSED] 50 VFs
[21:04:52] [PASSED] 51 VFs
[21:04:52] [PASSED] 52 VFs
[21:04:52] [PASSED] 53 VFs
[21:04:52] [PASSED] 54 VFs
[21:04:52] [PASSED] 55 VFs
[21:04:52] [PASSED] 56 VFs
[21:04:52] [PASSED] 57 VFs
[21:04:52] [PASSED] 58 VFs
[21:04:52] [PASSED] 59 VFs
[21:04:52] [PASSED] 60 VFs
[21:04:52] [PASSED] 61 VFs
[21:04:52] [PASSED] 62 VFs
[21:04:52] [PASSED] 63 VFs
[21:04:52] ================== [PASSED] fair_contexts ==================
[21:04:52] ===================== fair_doorbells  ======================
[21:04:52] [PASSED] 1 VF
[21:04:52] [PASSED] 2 VFs
[21:04:52] [PASSED] 3 VFs
[21:04:52] [PASSED] 4 VFs
[21:04:52] [PASSED] 5 VFs
[21:04:52] [PASSED] 6 VFs
[21:04:52] [PASSED] 7 VFs
[21:04:52] [PASSED] 8 VFs
[21:04:52] [PASSED] 9 VFs
[21:04:52] [PASSED] 10 VFs
[21:04:52] [PASSED] 11 VFs
[21:04:52] [PASSED] 12 VFs
[21:04:52] [PASSED] 13 VFs
[21:04:52] [PASSED] 14 VFs
[21:04:52] [PASSED] 15 VFs
[21:04:52] [PASSED] 16 VFs
[21:04:52] [PASSED] 17 VFs
[21:04:52] [PASSED] 18 VFs
[21:04:52] [PASSED] 19 VFs
[21:04:52] [PASSED] 20 VFs
[21:04:52] [PASSED] 21 VFs
[21:04:52] [PASSED] 22 VFs
[21:04:52] [PASSED] 23 VFs
[21:04:52] [PASSED] 24 VFs
[21:04:52] [PASSED] 25 VFs
[21:04:52] [PASSED] 26 VFs
[21:04:52] [PASSED] 27 VFs
[21:04:52] [PASSED] 28 VFs
[21:04:52] [PASSED] 29 VFs
[21:04:52] [PASSED] 30 VFs
[21:04:52] [PASSED] 31 VFs
[21:04:52] [PASSED] 32 VFs
[21:04:52] [PASSED] 33 VFs
[21:04:52] [PASSED] 34 VFs
[21:04:52] [PASSED] 35 VFs
[21:04:52] [PASSED] 36 VFs
[21:04:52] [PASSED] 37 VFs
[21:04:52] [PASSED] 38 VFs
[21:04:52] [PASSED] 39 VFs
[21:04:52] [PASSED] 40 VFs
[21:04:52] [PASSED] 41 VFs
[21:04:52] [PASSED] 42 VFs
[21:04:52] [PASSED] 43 VFs
[21:04:52] [PASSED] 44 VFs
[21:04:52] [PASSED] 45 VFs
[21:04:52] [PASSED] 46 VFs
[21:04:52] [PASSED] 47 VFs
[21:04:52] [PASSED] 48 VFs
[21:04:52] [PASSED] 49 VFs
[21:04:52] [PASSED] 50 VFs
[21:04:52] [PASSED] 51 VFs
[21:04:52] [PASSED] 52 VFs
[21:04:52] [PASSED] 53 VFs
[21:04:52] [PASSED] 54 VFs
[21:04:52] [PASSED] 55 VFs
[21:04:52] [PASSED] 56 VFs
[21:04:52] [PASSED] 57 VFs
[21:04:52] [PASSED] 58 VFs
[21:04:52] [PASSED] 59 VFs
[21:04:52] [PASSED] 60 VFs
[21:04:52] [PASSED] 61 VFs
[21:04:52] [PASSED] 62 VFs
[21:04:52] [PASSED] 63 VFs
[21:04:52] ================= [PASSED] fair_doorbells ==================
[21:04:52] ======================== fair_ggtt  ========================
[21:04:52] [PASSED] 1 VF
[21:04:52] [PASSED] 2 VFs
[21:04:52] [PASSED] 3 VFs
[21:04:52] [PASSED] 4 VFs
[21:04:52] [PASSED] 5 VFs
[21:04:52] [PASSED] 6 VFs
[21:04:52] [PASSED] 7 VFs
[21:04:52] [PASSED] 8 VFs
[21:04:52] [PASSED] 9 VFs
[21:04:52] [PASSED] 10 VFs
[21:04:52] [PASSED] 11 VFs
[21:04:52] [PASSED] 12 VFs
[21:04:52] [PASSED] 13 VFs
[21:04:52] [PASSED] 14 VFs
[21:04:52] [PASSED] 15 VFs
[21:04:52] [PASSED] 16 VFs
[21:04:52] [PASSED] 17 VFs
[21:04:52] [PASSED] 18 VFs
[21:04:52] [PASSED] 19 VFs
[21:04:52] [PASSED] 20 VFs
[21:04:52] [PASSED] 21 VFs
[21:04:52] [PASSED] 22 VFs
[21:04:52] [PASSED] 23 VFs
[21:04:52] [PASSED] 24 VFs
[21:04:52] [PASSED] 25 VFs
[21:04:52] [PASSED] 26 VFs
[21:04:52] [PASSED] 27 VFs
[21:04:52] [PASSED] 28 VFs
[21:04:52] [PASSED] 29 VFs
[21:04:52] [PASSED] 30 VFs
[21:04:52] [PASSED] 31 VFs
[21:04:52] [PASSED] 32 VFs
[21:04:52] [PASSED] 33 VFs
[21:04:52] [PASSED] 34 VFs
[21:04:52] [PASSED] 35 VFs
[21:04:52] [PASSED] 36 VFs
[21:04:52] [PASSED] 37 VFs
[21:04:52] [PASSED] 38 VFs
[21:04:52] [PASSED] 39 VFs
[21:04:52] [PASSED] 40 VFs
[21:04:52] [PASSED] 41 VFs
[21:04:52] [PASSED] 42 VFs
[21:04:52] [PASSED] 43 VFs
[21:04:52] [PASSED] 44 VFs
[21:04:52] [PASSED] 45 VFs
[21:04:52] [PASSED] 46 VFs
[21:04:52] [PASSED] 47 VFs
[21:04:52] [PASSED] 48 VFs
[21:04:52] [PASSED] 49 VFs
[21:04:52] [PASSED] 50 VFs
[21:04:52] [PASSED] 51 VFs
[21:04:52] [PASSED] 52 VFs
[21:04:52] [PASSED] 53 VFs
[21:04:52] [PASSED] 54 VFs
[21:04:52] [PASSED] 55 VFs
[21:04:52] [PASSED] 56 VFs
[21:04:52] [PASSED] 57 VFs
[21:04:52] [PASSED] 58 VFs
[21:04:52] [PASSED] 59 VFs
[21:04:52] [PASSED] 60 VFs
[21:04:52] [PASSED] 61 VFs
[21:04:52] [PASSED] 62 VFs
[21:04:52] [PASSED] 63 VFs
[21:04:52] ==================== [PASSED] fair_ggtt ====================
[21:04:52] ======================== fair_vram  ========================
[21:04:52] [PASSED] 1 VF
[21:04:52] [PASSED] 2 VFs
[21:04:52] [PASSED] 3 VFs
[21:04:52] [PASSED] 4 VFs
[21:04:52] [PASSED] 5 VFs
[21:04:52] [PASSED] 6 VFs
[21:04:52] [PASSED] 7 VFs
[21:04:52] [PASSED] 8 VFs
[21:04:52] [PASSED] 9 VFs
[21:04:52] [PASSED] 10 VFs
[21:04:52] [PASSED] 11 VFs
[21:04:52] [PASSED] 12 VFs
[21:04:52] [PASSED] 13 VFs
[21:04:52] [PASSED] 14 VFs
[21:04:52] [PASSED] 15 VFs
[21:04:52] [PASSED] 16 VFs
[21:04:52] [PASSED] 17 VFs
[21:04:52] [PASSED] 18 VFs
[21:04:52] [PASSED] 19 VFs
[21:04:52] [PASSED] 20 VFs
[21:04:52] [PASSED] 21 VFs
[21:04:52] [PASSED] 22 VFs
[21:04:52] [PASSED] 23 VFs
[21:04:52] [PASSED] 24 VFs
[21:04:52] [PASSED] 25 VFs
[21:04:52] [PASSED] 26 VFs
[21:04:52] [PASSED] 27 VFs
[21:04:52] [PASSED] 28 VFs
[21:04:52] [PASSED] 29 VFs
[21:04:52] [PASSED] 30 VFs
[21:04:52] [PASSED] 31 VFs
[21:04:52] [PASSED] 32 VFs
[21:04:52] [PASSED] 33 VFs
[21:04:52] [PASSED] 34 VFs
[21:04:52] [PASSED] 35 VFs
[21:04:52] [PASSED] 36 VFs
[21:04:52] [PASSED] 37 VFs
[21:04:52] [PASSED] 38 VFs
[21:04:52] [PASSED] 39 VFs
[21:04:52] [PASSED] 40 VFs
[21:04:52] [PASSED] 41 VFs
[21:04:52] [PASSED] 42 VFs
[21:04:52] [PASSED] 43 VFs
[21:04:52] [PASSED] 44 VFs
[21:04:52] [PASSED] 45 VFs
[21:04:52] [PASSED] 46 VFs
[21:04:52] [PASSED] 47 VFs
[21:04:52] [PASSED] 48 VFs
[21:04:52] [PASSED] 49 VFs
[21:04:52] [PASSED] 50 VFs
[21:04:52] [PASSED] 51 VFs
[21:04:52] [PASSED] 52 VFs
[21:04:52] [PASSED] 53 VFs
[21:04:52] [PASSED] 54 VFs
[21:04:52] [PASSED] 55 VFs
[21:04:52] [PASSED] 56 VFs
[21:04:52] [PASSED] 57 VFs
[21:04:52] [PASSED] 58 VFs
[21:04:52] [PASSED] 59 VFs
[21:04:52] [PASSED] 60 VFs
[21:04:52] [PASSED] 61 VFs
[21:04:52] [PASSED] 62 VFs
[21:04:52] [PASSED] 63 VFs
[21:04:52] ==================== [PASSED] fair_vram ====================
[21:04:52] ================== [PASSED] pf_gt_config ===================
[21:04:52] ===================== lmtt (1 subtest) =====================
[21:04:52] ======================== test_ops  =========================
[21:04:52] [PASSED] 2-level
[21:04:52] [PASSED] multi-level
[21:04:52] ==================== [PASSED] test_ops =====================
[21:04:52] ====================== [PASSED] lmtt =======================
[21:04:52] ================= sriov_packet (1 subtest) =================
[21:04:52] [PASSED] test_descriptor_init
[21:04:52] ================== [PASSED] sriov_packet ===================
[21:04:52] ================= pf_service (11 subtests) =================
[21:04:52] [PASSED] pf_negotiate_any
[21:04:52] [PASSED] pf_negotiate_base_match
[21:04:52] [PASSED] pf_negotiate_base_newer
[21:04:52] [PASSED] pf_negotiate_base_next
[21:04:52] [SKIPPED] pf_negotiate_base_older (no older minor)
[21:04:52] [PASSED] pf_negotiate_base_prev
[21:04:52] [PASSED] pf_negotiate_latest_match
[21:04:52] [PASSED] pf_negotiate_latest_newer
[21:04:52] [PASSED] pf_negotiate_latest_next
[21:04:52] [SKIPPED] pf_negotiate_latest_older (no older minor)
[21:04:52] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[21:04:52] =================== [PASSED] pf_service ====================
[21:04:52] ================= xe_guc_g2g (2 subtests) ==================
[21:04:52] ============== xe_live_guc_g2g_kunit_default  ==============
[21:04:52] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:04:52] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:04:52] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:04:52] =================== [SKIPPED] xe_guc_g2g ===================
[21:04:52] =================== xe_mocs (2 subtests) ===================
[21:04:52] ================ xe_live_mocs_kernel_kunit  ================
[21:04:52] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:04:52] ================ xe_live_mocs_reset_kunit  =================
[21:04:52] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:04:52] ==================== [SKIPPED] xe_mocs =====================
[21:04:52] ================= xe_migrate (2 subtests) ==================
[21:04:52] ================= xe_migrate_sanity_kunit  =================
[21:04:52] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:04:52] ================== xe_validate_ccs_kunit  ==================
[21:04:52] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:04:52] =================== [SKIPPED] xe_migrate ===================
[21:04:52] ================== xe_dma_buf (1 subtest) ==================
[21:04:52] ==================== xe_dma_buf_kunit  =====================
[21:04:52] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:04:52] =================== [SKIPPED] xe_dma_buf ===================
[21:04:52] ================= xe_bo_shrink (1 subtest) =================
[21:04:52] =================== xe_bo_shrink_kunit  ====================
[21:04:52] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:04:52] ================== [SKIPPED] xe_bo_shrink ==================
[21:04:52] ==================== xe_bo (2 subtests) ====================
[21:04:52] ================== xe_ccs_migrate_kunit  ===================
[21:04:52] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:04:52] ==================== xe_bo_evict_kunit  ====================
[21:04:52] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:04:52] ===================== [SKIPPED] xe_bo ======================
[21:04:52] =================== xe_any (9 subtests) ====================
[21:04:52] [PASSED] test_to_xe
[21:04:52] [PASSED] test_to_dev
[21:04:52] [PASSED] test_to_pdev
[21:04:52] [PASSED] test_to_drm
[21:04:52] [PASSED] test_if_pdev
[21:04:52] [PASSED] test_if_xe
[21:04:52] [PASSED] test_if_tile
[21:04:52] [PASSED] test_if_gt
[21:04:52] [PASSED] test_to_id
[21:04:52] ===================== [PASSED] xe_any ======================
[21:04:52] ==================== args (13 subtests) ====================
[21:04:52] [PASSED] count_args_test
[21:04:52] [PASSED] call_args_example
[21:04:52] [PASSED] call_args_test
[21:04:52] [PASSED] drop_first_arg_example
[21:04:52] [PASSED] drop_first_arg_test
[21:04:52] [PASSED] first_arg_example
[21:04:52] [PASSED] first_arg_test
[21:04:52] [PASSED] last_arg_example
[21:04:52] [PASSED] last_arg_test
[21:04:52] [PASSED] pick_arg_example
[21:04:52] [PASSED] if_args_example
[21:04:52] [PASSED] if_args_test
[21:04:52] [PASSED] sep_comma_example
[21:04:52] ====================== [PASSED] args =======================
[21:04:52] =================== xe_pci (3 subtests) ====================
[21:04:52] ==================== check_graphics_ip  ====================
[21:04:52] [PASSED] 12.00 Xe_LP
[21:04:52] [PASSED] 12.10 Xe_LP+
[21:04:52] [PASSED] 12.55 Xe_HPG
[21:04:52] [PASSED] 12.60 Xe_HPC
[21:04:52] [PASSED] 12.70 Xe_LPG
[21:04:52] [PASSED] 12.71 Xe_LPG
[21:04:52] [PASSED] 12.74 Xe_LPG+
[21:04:52] [PASSED] 20.01 Xe2_HPG
[21:04:52] [PASSED] 20.02 Xe2_HPG
[21:04:52] [PASSED] 20.04 Xe2_LPG
[21:04:52] [PASSED] 30.00 Xe3_LPG
[21:04:52] [PASSED] 30.01 Xe3_LPG
[21:04:52] [PASSED] 30.03 Xe3_LPG
[21:04:52] [PASSED] 30.04 Xe3_LPG
[21:04:52] [PASSED] 30.05 Xe3_LPG
[21:04:52] [PASSED] 35.10 Xe3p_LPG
[21:04:52] [PASSED] 35.11 Xe3p_XPC
[21:04:52] ================ [PASSED] check_graphics_ip ================
[21:04:52] ===================== check_media_ip  ======================
[21:04:52] [PASSED] 12.00 Xe_M
[21:04:52] [PASSED] 12.55 Xe_HPM
[21:04:52] [PASSED] 13.00 Xe_LPM+
[21:04:52] [PASSED] 13.01 Xe2_HPM
[21:04:52] [PASSED] 20.00 Xe2_LPM
[21:04:52] [PASSED] 30.00 Xe3_LPM
[21:04:52] [PASSED] 30.02 Xe3_LPM
[21:04:52] [PASSED] 35.00 Xe3p_LPM
[21:04:52] [PASSED] 35.03 Xe3p_HPM
[21:04:52] ================= [PASSED] check_media_ip ==================
[21:04:52] =================== check_platform_desc  ===================
[21:04:52] [PASSED] 0x9A60 (TIGERLAKE)
[21:04:52] [PASSED] 0x9A68 (TIGERLAKE)
[21:04:52] [PASSED] 0x9A70 (TIGERLAKE)
[21:04:52] [PASSED] 0x9A40 (TIGERLAKE)
[21:04:52] [PASSED] 0x9A49 (TIGERLAKE)
[21:04:52] [PASSED] 0x9A59 (TIGERLAKE)
[21:04:52] [PASSED] 0x9A78 (TIGERLAKE)
[21:04:52] [PASSED] 0x9AC0 (TIGERLAKE)
[21:04:52] [PASSED] 0x9AC9 (TIGERLAKE)
[21:04:52] [PASSED] 0x9AD9 (TIGERLAKE)
[21:04:52] [PASSED] 0x9AF8 (TIGERLAKE)
[21:04:52] [PASSED] 0x4C80 (ROCKETLAKE)
[21:04:52] [PASSED] 0x4C8A (ROCKETLAKE)
[21:04:52] [PASSED] 0x4C8B (ROCKETLAKE)
[21:04:52] [PASSED] 0x4C8C (ROCKETLAKE)
[21:04:52] [PASSED] 0x4C90 (ROCKETLAKE)
[21:04:52] [PASSED] 0x4C9A (ROCKETLAKE)
[21:04:52] [PASSED] 0x4680 (ALDERLAKE_S)
[21:04:52] [PASSED] 0x4682 (ALDERLAKE_S)
[21:04:52] [PASSED] 0x4688 (ALDERLAKE_S)
[21:04:52] [PASSED] 0x468A (ALDERLAKE_S)
[21:04:52] [PASSED] 0x468B (ALDERLAKE_S)
[21:04:52] [PASSED] 0x4690 (ALDERLAKE_S)
[21:04:52] [PASSED] 0x4692 (ALDERLAKE_S)
[21:04:52] [PASSED] 0x4693 (ALDERLAKE_S)
[21:04:52] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46AA (ALDERLAKE_P)
[21:04:52] [PASSED] 0x462A (ALDERLAKE_P)
[21:04:52] [PASSED] 0x4626 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x4628 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:04:52] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:04:52] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:04:52] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:04:52] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:04:52] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:04:52] [PASSED] 0xA721 (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA720 (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:04:52] [PASSED] 0xA780 (ALDERLAKE_S)
[21:04:52] [PASSED] 0xA781 (ALDERLAKE_S)
[21:04:52] [PASSED] 0xA782 (ALDERLAKE_S)
[21:04:52] [PASSED] 0xA783 (ALDERLAKE_S)
[21:04:52] [PASSED] 0xA788 (ALDERLAKE_S)
[21:04:52] [PASSED] 0xA789 (ALDERLAKE_S)
[21:04:52] [PASSED] 0xA78A (ALDERLAKE_S)
[21:04:52] [PASSED] 0xA78B (ALDERLAKE_S)
[21:04:52] [PASSED] 0x4905 (DG1)
[21:04:52] [PASSED] 0x4906 (DG1)
[21:04:52] [PASSED] 0x4907 (DG1)
[21:04:52] [PASSED] 0x4908 (DG1)
[21:04:52] [PASSED] 0x4909 (DG1)
[21:04:52] [PASSED] 0x56C0 (DG2)
[21:04:52] [PASSED] 0x56C2 (DG2)
[21:04:52] [PASSED] 0x56C1 (DG2)
[21:04:52] [PASSED] 0x7D51 (METEORLAKE)
[21:04:52] [PASSED] 0x7DD1 (METEORLAKE)
[21:04:52] [PASSED] 0x7D41 (METEORLAKE)
[21:04:52] [PASSED] 0x7D67 (METEORLAKE)
[21:04:52] [PASSED] 0xB640 (METEORLAKE)
[21:04:52] [PASSED] 0x56A0 (DG2)
[21:04:52] [PASSED] 0x56A1 (DG2)
[21:04:52] [PASSED] 0x56A2 (DG2)
[21:04:52] [PASSED] 0x56BE (DG2)
[21:04:52] [PASSED] 0x56BF (DG2)
[21:04:52] [PASSED] 0x5690 (DG2)
[21:04:52] [PASSED] 0x5691 (DG2)
[21:04:52] [PASSED] 0x5692 (DG2)
[21:04:52] [PASSED] 0x56A5 (DG2)
[21:04:52] [PASSED] 0x56A6 (DG2)
[21:04:52] [PASSED] 0x56B0 (DG2)
[21:04:52] [PASSED] 0x56B1 (DG2)
[21:04:52] [PASSED] 0x56BA (DG2)
[21:04:52] [PASSED] 0x56BB (DG2)
[21:04:52] [PASSED] 0x56BC (DG2)
[21:04:52] [PASSED] 0x56BD (DG2)
[21:04:52] [PASSED] 0x5693 (DG2)
[21:04:52] [PASSED] 0x5694 (DG2)
[21:04:52] [PASSED] 0x5695 (DG2)
[21:04:52] [PASSED] 0x56A3 (DG2)
[21:04:52] [PASSED] 0x56A4 (DG2)
[21:04:52] [PASSED] 0x56B2 (DG2)
[21:04:52] [PASSED] 0x56B3 (DG2)
[21:04:52] [PASSED] 0x5696 (DG2)
[21:04:52] [PASSED] 0x5697 (DG2)
[21:04:52] [PASSED] 0xB69 (PVC)
[21:04:52] [PASSED] 0xB6E (PVC)
[21:04:52] [PASSED] 0xBD4 (PVC)
[21:04:52] [PASSED] 0xBD5 (PVC)
[21:04:52] [PASSED] 0xBD6 (PVC)
[21:04:52] [PASSED] 0xBD7 (PVC)
[21:04:52] [PASSED] 0xBD8 (PVC)
[21:04:52] [PASSED] 0xBD9 (PVC)
[21:04:52] [PASSED] 0xBDA (PVC)
[21:04:52] [PASSED] 0xBDB (PVC)
[21:04:52] [PASSED] 0xBE0 (PVC)
[21:04:52] [PASSED] 0xBE1 (PVC)
[21:04:52] [PASSED] 0xBE5 (PVC)
[21:04:52] [PASSED] 0x7D40 (METEORLAKE)
[21:04:52] [PASSED] 0x7D45 (METEORLAKE)
[21:04:52] [PASSED] 0x7D55 (METEORLAKE)
[21:04:52] [PASSED] 0x7D60 (METEORLAKE)
[21:04:52] [PASSED] 0x7DD5 (METEORLAKE)
[21:04:52] [PASSED] 0x6420 (LUNARLAKE)
[21:04:52] [PASSED] 0x64A0 (LUNARLAKE)
[21:04:52] [PASSED] 0x64B0 (LUNARLAKE)
[21:04:52] [PASSED] 0xE202 (BATTLEMAGE)
[21:04:52] [PASSED] 0xE209 (BATTLEMAGE)
[21:04:52] [PASSED] 0xE20B (BATTLEMAGE)
[21:04:52] [PASSED] 0xE20C (BATTLEMAGE)
[21:04:52] [PASSED] 0xE20D (BATTLEMAGE)
[21:04:52] [PASSED] 0xE210 (BATTLEMAGE)
[21:04:52] [PASSED] 0xE211 (BATTLEMAGE)
[21:04:52] [PASSED] 0xE212 (BATTLEMAGE)
[21:04:52] [PASSED] 0xE216 (BATTLEMAGE)
[21:04:52] [PASSED] 0xE220 (BATTLEMAGE)
[21:04:52] [PASSED] 0xE221 (BATTLEMAGE)
[21:04:52] [PASSED] 0xE222 (BATTLEMAGE)
[21:04:52] [PASSED] 0xE223 (BATTLEMAGE)
[21:04:52] [PASSED] 0xB080 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB081 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB082 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB083 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB084 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB085 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB086 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB087 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB08F (PANTHERLAKE)
[21:04:52] [PASSED] 0xB090 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:04:52] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:04:52] [PASSED] 0xFD80 (PANTHERLAKE)
[21:04:52] [PASSED] 0xFD81 (PANTHERLAKE)
[21:04:52] [PASSED] 0xD740 (NOVALAKE_S)
[21:04:52] [PASSED] 0xD741 (NOVALAKE_S)
[21:04:52] [PASSED] 0xD742 (NOVALAKE_S)
[21:04:52] [PASSED] 0xD743 (NOVALAKE_S)
[21:04:52] [PASSED] 0xD745 (NOVALAKE_S)
[21:04:52] [PASSED] 0xD74A (NOVALAKE_S)
[21:04:52] [PASSED] 0xD74B (NOVALAKE_S)
[21:04:52] [PASSED] 0x674C (CRESCENTISLAND)
[21:04:52] [PASSED] 0x674D (CRESCENTISLAND)
[21:04:52] [PASSED] 0x674E (CRESCENTISLAND)
[21:04:52] [PASSED] 0x674F (CRESCENTISLAND)
[21:04:52] [PASSED] 0x6750 (CRESCENTISLAND)
[21:04:52] [PASSED] 0xD750 (NOVALAKE_P)
[21:04:52] [PASSED] 0xD751 (NOVALAKE_P)
[21:04:52] [PASSED] 0xD752 (NOVALAKE_P)
[21:04:52] [PASSED] 0xD753 (NOVALAKE_P)
[21:04:52] [PASSED] 0xD754 (NOVALAKE_P)
[21:04:52] [PASSED] 0xD755 (NOVALAKE_P)
[21:04:52] [PASSED] 0xD756 (NOVALAKE_P)
[21:04:52] [PASSED] 0xD757 (NOVALAKE_P)
[21:04:52] [PASSED] 0xD75F (NOVALAKE_P)
[21:04:52] =============== [PASSED] check_platform_desc ===============
[21:04:52] ===================== [PASSED] xe_pci ======================
[21:04:52] ============= xe_rtp_tables_test (5 subtests) ==============
[21:04:52] ================== xe_rtp_table_gt_test  ===================
[21:04:52] [PASSED] gt_was/14011060649
[21:04:52] [PASSED] gt_was/14011059788
[21:04:52] [PASSED] gt_was/14015795083
[21:04:52] [PASSED] gt_was/16021867713
[21:04:52] [PASSED] gt_was/14019449301
[21:04:52] [PASSED] gt_was/16028005424
[21:04:52] [PASSED] gt_was/14026578760
[21:04:52] [PASSED] gt_was/1409420604
[21:04:52] [PASSED] gt_was/1408615072
[21:04:52] [PASSED] gt_was/22010523718
[21:04:52] [PASSED] gt_was/14011006942
[21:04:52] [PASSED] gt_was/14014830051
[21:04:52] [PASSED] gt_was/18018781329
[21:04:52] [PASSED] gt_was/1509235366
[21:04:52] [PASSED] gt_was/18018781329
[21:04:52] [PASSED] gt_was/16016694945
[21:04:52] [PASSED] gt_was/14018575942
[21:04:52] [PASSED] gt_was/22016670082
[21:04:52] [PASSED] gt_was/22016670082
[21:04:52] [PASSED] gt_was/14017421178
[21:04:52] [PASSED] gt_was/16025250150
[21:04:52] [PASSED] gt_was/14021871409
[21:04:52] [PASSED] gt_was/16021865536
[21:04:52] [PASSED] gt_was/14021486841
[21:04:52] [PASSED] gt_was/14025160223
[21:04:52] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[21:04:52] [PASSED] gt_was/14025635424
[21:04:52] [PASSED] gt_was/16028005424
[21:04:52] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:04:52] ================== xe_rtp_table_gt_test  ===================
[21:04:52] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[21:04:52] [PASSED] gt_tunings/Tuning: 32B Access Enable
[21:04:52] [PASSED] gt_tunings/Tuning: L3 cache
[21:04:52] [PASSED] gt_tunings/Tuning: L3 cache - media
[21:04:52] [PASSED] gt_tunings/Tuning: Compression Overfetch
[21:04:52] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[21:04:52] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[21:04:52] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[21:04:52] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[21:04:52] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[21:04:52] [PASSED] gt_tunings/Tuning: Stateless compression control
[21:04:52] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[21:04:52] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[21:04:52] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[21:04:52] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[21:04:52] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:04:52] ================== xe_rtp_table_oob_test  ==================
[21:04:52] [PASSED] oob_was/1607983814
[21:04:52] [PASSED] oob_was/16010904313
[21:04:52] [PASSED] oob_was/18022495364
[21:04:52] [PASSED] oob_was/22012773006
[21:04:52] [PASSED] oob_was/14014475959
[21:04:52] [PASSED] oob_was/22011391025
[21:04:52] [PASSED] oob_was/22012727170
[21:04:52] [PASSED] oob_was/22012727685
[21:04:52] [PASSED] oob_was/22016596838
[21:04:52] [PASSED] oob_was/18020744125
[21:04:52] [PASSED] oob_was/1409600907
[21:04:52] [PASSED] oob_was/22014953428
[21:04:52] [PASSED] oob_was/16017236439
[21:04:52] [PASSED] oob_was/14019821291
[21:04:52] [PASSED] oob_was/14015076503
[21:04:52] [PASSED] oob_was/14018913170
[21:04:52] [PASSED] oob_was/14018094691
[21:04:52] [PASSED] oob_was/18024947630
[21:04:52] [PASSED] oob_was/16022287689
[21:04:52] [PASSED] oob_was/13011645652
[21:04:52] [PASSED] oob_was/14022293748
[21:04:52] [PASSED] oob_was/22019794406
[21:04:52] [PASSED] oob_was/22019338487
[21:04:52] [PASSED] oob_was/16023588340
[21:04:52] [PASSED] oob_was/14019789679
[21:04:52] [PASSED] oob_was/14022866841
[21:04:52] [PASSED] oob_was/16021333562
[21:04:52] [PASSED] oob_was/14016712196
[21:04:52] [PASSED] oob_was/14015568240
[21:04:52] [PASSED] oob_was/18013179988
[21:04:52] [PASSED] oob_was/1508761755
[21:04:52] [PASSED] oob_was/16023105232
[21:04:52] [PASSED] oob_was/16026508708
[21:04:52] [PASSED] oob_was/14020001231
[21:04:52] [PASSED] oob_was/16023683509
[21:04:52] [PASSED] oob_was/14025515070
[21:04:52] [PASSED] oob_was/15015404425_disable
[21:04:52] [PASSED] oob_was/16026007364
[21:04:52] [PASSED] oob_was/14020316580
[21:04:52] [PASSED] oob_was/14025883347
[21:04:52] [PASSED] oob_was/16029380221
[21:04:52] [PASSED] oob_was/22022079272
[21:04:52] [PASSED] oob_was/16029897822
[21:04:52] [PASSED] oob_was/14027054324
[21:04:52] [PASSED] oob_was/14025941587
[21:04:52] ============== [PASSED] xe_rtp_table_oob_test ==============
[21:04:52] ================ xe_rtp_table_dev_oob_test  ================
[21:04:52] [PASSED] device_oob_was/22010954014
[21:04:52] [PASSED] device_oob_was/15015404425
[21:04:52] [PASSED] device_oob_was/22019338487_display
[21:04:52] [PASSED] device_oob_was/14022085890
[21:04:52] [PASSED] device_oob_was/14026539277
[21:04:52] [PASSED] device_oob_was/14026633728
[21:04:52] [PASSED] device_oob_was/14026746987
[21:04:52] [PASSED] device_oob_was/14026779378
[21:04:52] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[21:04:52] ========== xe_rtp_table_missing_upper_bound_test  ==========
[21:04:52] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[21:04:52] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[21:04:52] [PASSED] register_whitelist/1806527549
[21:04:52] [PASSED] register_whitelist/allow_read_ctx_timestamp
[21:04:52] [PASSED] register_whitelist/allow_read_queue_timestamp
[21:04:52] [PASSED] register_whitelist/16014440446
[21:04:52] [PASSED] register_whitelist/16017236439
[21:04:52] [PASSED] register_whitelist/16020183090
[21:04:52] [PASSED] register_whitelist/14024997852
[21:04:52] [PASSED] register_whitelist/14024997852
[21:04:52] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[21:04:52] =============== [PASSED] xe_rtp_tables_test ================
[21:04:52] =================== xe_rtp (3 subtests) ====================
[21:04:52] =================== xe_rtp_rules_tests  ====================
[21:04:52] [PASSED] no
[21:04:52] [PASSED] yes
[21:04:52] [PASSED] no-and-no
[21:04:52] [PASSED] no-and-yes
[21:04:52] [PASSED] yes-and-no
[21:04:52] [PASSED] yes-and-yes
[21:04:52] [PASSED] no-or-no
[21:04:52] [PASSED] no-or-yes
[21:04:52] [PASSED] yes-or-no
[21:04:52] [PASSED] yes-or-yes
[21:04:52] [PASSED] no-yes-or-yes-no
[21:04:52] [PASSED] no-yes-or-yes-yes
[21:04:52] [PASSED] yes-yes-or-no-yes
[21:04:52] [PASSED] yes-yes-or-yes-yes
[21:04:52] [PASSED] no-no-or-yes-or-no
[21:04:52] [PASSED] or
[21:04:52] [PASSED] or-yes
[21:04:52] [PASSED] or-no
[21:04:52] [PASSED] yes-or
[21:04:52] [PASSED] no-or
[21:04:52] [PASSED] no-or-or-yes
[21:04:52] [PASSED] yes-or-or-no
[21:04:52] [PASSED] no-or-or-no
[21:04:52] [PASSED] missing-context-engine-class
[21:04:52] [PASSED] missing-context-engine-class-or-yes
[21:04:52] [PASSED] missing-context-engine-class-or-or-yes
[21:04:52] =============== [PASSED] xe_rtp_rules_tests ================
[21:04:52] =============== xe_rtp_process_to_sr_tests  ================
[21:04:52] [PASSED] coalesce-same-reg
[21:04:52] [PASSED] coalesce-same-reg-literal-and-func
[21:04:52] [PASSED] no-match-no-add
[21:04:52] [PASSED] two-regs-two-entries
[21:04:52] [PASSED] clr-one-set-other
[21:04:52] [PASSED] set-field
[21:04:52] [PASSED] conflict-duplicate
[21:04:52] [PASSED] conflict-not-disjoint
[21:04:52] [PASSED] conflict-not-disjoint-literal-and-func
[21:04:52] [PASSED] conflict-reg-type
[21:04:52] [PASSED] bad-mcr-reg-forced-to-regular
[21:04:52] [PASSED] bad-regular-reg-forced-to-mcr
[21:04:52] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:04:52] ================== xe_rtp_process_tests  ===================
[21:04:52] [PASSED] active1
[21:04:52] [PASSED] active2
[21:04:52] [PASSED] active-inactive
[21:04:52] [PASSED] inactive-active
[21:04:52] [PASSED] inactive-active-inactive
[21:04:52] [PASSED] inactive-inactive-inactive
[21:04:52] ============== [PASSED] xe_rtp_process_tests ===============
[21:04:52] ===================== [PASSED] xe_rtp ======================
[21:04:52] ==================== xe_wa (1 subtest) =====================
[21:04:52] ======================== xe_wa_gt  =========================
[21:04:52] [PASSED] TIGERLAKE B0
[21:04:52] [PASSED] DG1 A0
[21:04:52] [PASSED] DG1 B0
[21:04:52] [PASSED] ALDERLAKE_S A0
[21:04:52] [PASSED] ALDERLAKE_S B0
[21:04:52] [PASSED] ALDERLAKE_S C0
[21:04:52] [PASSED] ALDERLAKE_S D0
[21:04:52] [PASSED] ALDERLAKE_P A0
[21:04:52] [PASSED] ALDERLAKE_P B0
[21:04:52] [PASSED] ALDERLAKE_P C0
[21:04:52] [PASSED] ALDERLAKE_S RPLS D0
[21:04:52] [PASSED] ALDERLAKE_P RPLU E0
[21:04:52] [PASSED] DG2 G10 C0
[21:04:52] [PASSED] DG2 G11 B1
[21:04:52] [PASSED] DG2 G12 A1
[21:04:52] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:04:52] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:04:52] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:04:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:04:52] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:04:52] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:04:52] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:04:52] ==================== [PASSED] xe_wa_gt =====================
[21:04:52] ====================== [PASSED] xe_wa ======================
[21:04:52] ============================================================
[21:04:52] Testing complete. Ran 820 tests: passed: 792, skipped: 28
[21:04:52] Elapsed time: 37.282s total, 1.848s configuring, 34.669s building, 0.712s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:04:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:04:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:05:20] Starting KUnit Kernel (1/1)...
[21:05:20] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:05:20] ============= refcount_interrupt (4 subtests) ==============
[21:05:20] [PASSED] test_single_irq_change
[21:05:20] [PASSED] test_nested_irq_change
[21:05:20] [PASSED] test_multiple_irq_change
[21:05:20] [PASSED] test_irq_save
[21:05:20] =============== [PASSED] refcount_interrupt ================
[21:05:20] ============ drm_test_pick_cmdline (2 subtests) ============
[21:05:20] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:05:20] =============== drm_test_pick_cmdline_named  ===============
[21:05:20] [PASSED] NTSC
[21:05:20] [PASSED] NTSC-J
[21:05:20] [PASSED] PAL
[21:05:20] [PASSED] PAL-M
[21:05:20] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:05:20] ============== [PASSED] drm_test_pick_cmdline ==============
[21:05:20] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:05:20] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:05:20] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:05:20] =========== drm_validate_clone_mode (2 subtests) ===========
[21:05:20] ============== drm_test_check_in_clone_mode  ===============
[21:05:20] [PASSED] in_clone_mode
[21:05:20] [PASSED] not_in_clone_mode
[21:05:20] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:05:20] =============== drm_test_check_valid_clones  ===============
[21:05:20] [PASSED] not_in_clone_mode
[21:05:20] [PASSED] valid_clone
[21:05:20] [PASSED] invalid_clone
[21:05:20] =========== [PASSED] drm_test_check_valid_clones ===========
[21:05:20] ============= [PASSED] drm_validate_clone_mode =============
[21:05:20] ============= drm_validate_modeset (1 subtest) =============
[21:05:20] [PASSED] drm_test_check_connector_changed_modeset
[21:05:20] ============== [PASSED] drm_validate_modeset ===============
[21:05:20] ====== drm_test_bridge_get_current_state (1 subtest) =======
[21:05:20] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:05:20] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:05:20] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:05:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:05:20] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:05:20] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[21:05:20] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:05:20] ============== drm_bridge_alloc (2 subtests) ===============
[21:05:20] [PASSED] drm_test_drm_bridge_alloc_basic
[21:05:20] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:05:20] ================ [PASSED] drm_bridge_alloc =================
[21:05:20] ============= drm_bridge_bus_fmt (5 subtests) ==============
[21:05:20] [PASSED] drm_test_bridge_rgb_yuv_rgb
[21:05:20] [PASSED] drm_test_bridge_must_convert_to_yuv444
[21:05:20] [PASSED] drm_test_bridge_hdmi_auto_rgb
[21:05:20] [PASSED] drm_test_bridge_auto_first
[21:05:20] [PASSED] drm_test_bridge_rgb_yuv_no_path
[21:05:20] =============== [PASSED] drm_bridge_bus_fmt ================
[21:05:20] ============= drm_cmdline_parser (40 subtests) =============
[21:05:20] [PASSED] drm_test_cmdline_force_d_only
[21:05:20] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:05:20] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:05:20] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:05:20] [PASSED] drm_test_cmdline_force_e_only
[21:05:20] [PASSED] drm_test_cmdline_res
[21:05:20] [PASSED] drm_test_cmdline_res_vesa
[21:05:20] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:05:20] [PASSED] drm_test_cmdline_res_rblank
[21:05:20] [PASSED] drm_test_cmdline_res_bpp
[21:05:20] [PASSED] drm_test_cmdline_res_refresh
[21:05:20] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:05:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:05:20] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:05:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:05:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:05:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:05:20] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:05:20] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:05:20] [PASSED] drm_test_cmdline_res_margins_force_on
[21:05:20] [PASSED] drm_test_cmdline_res_vesa_margins
[21:05:20] [PASSED] drm_test_cmdline_name
[21:05:20] [PASSED] drm_test_cmdline_name_bpp
[21:05:20] [PASSED] drm_test_cmdline_name_option
[21:05:20] [PASSED] drm_test_cmdline_name_bpp_option
[21:05:20] [PASSED] drm_test_cmdline_rotate_0
[21:05:20] [PASSED] drm_test_cmdline_rotate_90
[21:05:20] [PASSED] drm_test_cmdline_rotate_180
[21:05:20] [PASSED] drm_test_cmdline_rotate_270
[21:05:20] [PASSED] drm_test_cmdline_hmirror
[21:05:20] [PASSED] drm_test_cmdline_vmirror
[21:05:20] [PASSED] drm_test_cmdline_margin_options
[21:05:20] [PASSED] drm_test_cmdline_multiple_options
[21:05:20] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:05:20] [PASSED] drm_test_cmdline_extra_and_option
[21:05:20] [PASSED] drm_test_cmdline_freestanding_options
[21:05:20] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:05:20] [PASSED] drm_test_cmdline_panel_orientation
[21:05:20] ================ drm_test_cmdline_invalid  =================
[21:05:20] [PASSED] margin_only
[21:05:20] [PASSED] interlace_only
[21:05:20] [PASSED] res_missing_x
[21:05:20] [PASSED] res_missing_y
[21:05:20] [PASSED] res_bad_y
[21:05:20] [PASSED] res_missing_y_bpp
[21:05:20] [PASSED] res_bad_bpp
[21:05:20] [PASSED] res_bad_refresh
[21:05:20] [PASSED] res_bpp_refresh_force_on_off
[21:05:20] [PASSED] res_invalid_mode
[21:05:20] [PASSED] res_bpp_wrong_place_mode
[21:05:20] [PASSED] name_bpp_refresh
[21:05:20] [PASSED] name_refresh
[21:05:20] [PASSED] name_refresh_wrong_mode
[21:05:20] [PASSED] name_refresh_invalid_mode
[21:05:20] [PASSED] rotate_multiple
[21:05:20] [PASSED] rotate_invalid_val
[21:05:20] [PASSED] rotate_truncated
[21:05:20] [PASSED] invalid_option
[21:05:20] [PASSED] invalid_tv_option
[21:05:20] [PASSED] truncated_tv_option
[21:05:20] ============ [PASSED] drm_test_cmdline_invalid =============
[21:05:20] =============== drm_test_cmdline_tv_options  ===============
[21:05:20] [PASSED] NTSC
[21:05:20] [PASSED] NTSC_443
[21:05:20] [PASSED] NTSC_J
[21:05:20] [PASSED] PAL
[21:05:20] [PASSED] PAL_M
[21:05:20] [PASSED] PAL_N
[21:05:20] [PASSED] SECAM
[21:05:20] [PASSED] MONO_525
[21:05:20] [PASSED] MONO_625
[21:05:20] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:05:20] =============== [PASSED] drm_cmdline_parser ================
[21:05:20] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:05:20] [PASSED] drm_test_connector_hdmi_init_valid
[21:05:20] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:05:20] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:05:20] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:05:20] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:05:20] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:05:20] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:05:20] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:05:20] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:05:20] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:05:20] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:05:20] [PASSED] supported_formats=0x5 yuv420_allowed=1
[21:05:20] [PASSED] supported_formats=0x5 yuv420_allowed=0
[21:05:20] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:05:20] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:05:20] [PASSED] drm_test_connector_hdmi_init_null_product
[21:05:20] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:05:20] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:05:20] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:05:20] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:05:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:05:20] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:05:20] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:05:20] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:05:20] [PASSED] HDMI-A
[21:05:20] [PASSED] HDMI-B
[21:05:20] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:05:20] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:05:20] [PASSED] Unknown
[21:05:20] [PASSED] VGA
[21:05:20] [PASSED] DVI-I
[21:05:20] [PASSED] DVI-D
[21:05:20] [PASSED] DVI-A
[21:05:20] [PASSED] Composite
[21:05:20] [PASSED] SVIDEO
[21:05:20] [PASSED] LVDS
[21:05:20] [PASSED] Component
[21:05:20] [PASSED] DIN
[21:05:20] [PASSED] DP
[21:05:20] [PASSED] TV
[21:05:20] [PASSED] eDP
[21:05:20] [PASSED] Virtual
[21:05:20] [PASSED] DSI
[21:05:20] [PASSED] DPI
[21:05:20] [PASSED] Writeback
[21:05:20] [PASSED] SPI
[21:05:20] [PASSED] USB
[21:05:20] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:05:20] ============ [PASSED] drmm_connector_hdmi_init =============
[21:05:20] ============= drmm_connector_init (3 subtests) =============
[21:05:20] [PASSED] drm_test_drmm_connector_init
[21:05:20] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:05:20] ========= drm_test_drmm_connector_init_type_valid  =========
[21:05:20] [PASSED] Unknown
[21:05:20] [PASSED] VGA
[21:05:20] [PASSED] DVI-I
[21:05:20] [PASSED] DVI-D
[21:05:20] [PASSED] DVI-A
[21:05:20] [PASSED] Composite
[21:05:20] [PASSED] SVIDEO
[21:05:20] [PASSED] LVDS
[21:05:20] [PASSED] Component
[21:05:20] [PASSED] DIN
[21:05:20] [PASSED] DP
[21:05:20] [PASSED] HDMI-A
[21:05:20] [PASSED] HDMI-B
[21:05:20] [PASSED] TV
[21:05:20] [PASSED] eDP
[21:05:20] [PASSED] Virtual
[21:05:20] [PASSED] DSI
[21:05:20] [PASSED] DPI
[21:05:20] [PASSED] Writeback
[21:05:20] [PASSED] SPI
[21:05:20] [PASSED] USB
[21:05:20] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:05:20] =============== [PASSED] drmm_connector_init ===============
[21:05:20] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_init
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:05:20] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:05:20] [PASSED] Unknown
[21:05:20] [PASSED] VGA
[21:05:20] [PASSED] DVI-I
[21:05:20] [PASSED] DVI-D
[21:05:20] [PASSED] DVI-A
[21:05:20] [PASSED] Composite
[21:05:20] [PASSED] SVIDEO
[21:05:20] [PASSED] LVDS
[21:05:20] [PASSED] Component
[21:05:20] [PASSED] DIN
[21:05:20] [PASSED] DP
[21:05:20] [PASSED] HDMI-A
[21:05:20] [PASSED] HDMI-B
[21:05:20] [PASSED] TV
[21:05:20] [PASSED] eDP
[21:05:20] [PASSED] Virtual
[21:05:20] [PASSED] DSI
[21:05:20] [PASSED] DPI
[21:05:20] [PASSED] Writeback
[21:05:20] [PASSED] SPI
[21:05:20] [PASSED] USB
[21:05:20] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:05:20] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:05:20] [PASSED] Unknown
[21:05:20] [PASSED] VGA
[21:05:20] [PASSED] DVI-I
[21:05:20] [PASSED] DVI-D
[21:05:20] [PASSED] DVI-A
[21:05:20] [PASSED] Composite
[21:05:20] [PASSED] SVIDEO
[21:05:20] [PASSED] LVDS
[21:05:20] [PASSED] Component
[21:05:20] [PASSED] DIN
[21:05:20] [PASSED] DP
[21:05:20] [PASSED] HDMI-A
[21:05:20] [PASSED] HDMI-B
[21:05:20] [PASSED] TV
[21:05:20] [PASSED] eDP
[21:05:20] [PASSED] Virtual
[21:05:20] [PASSED] DSI
[21:05:20] [PASSED] DPI
[21:05:20] [PASSED] Writeback
[21:05:20] [PASSED] SPI
[21:05:20] [PASSED] USB
[21:05:20] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:05:20] =========== [PASSED] drm_connector_dynamic_init ============
[21:05:20] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:05:20] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:05:20] ======= drm_connector_dynamic_register (7 subtests) ========
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:05:20] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:05:20] ========= [PASSED] drm_connector_dynamic_register ==========
[21:05:20] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:05:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:05:20] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:05:20] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:05:20] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:05:20] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:05:20] [PASSED] NTSC
[21:05:20] [PASSED] NTSC-443
[21:05:20] [PASSED] NTSC-J
[21:05:20] [PASSED] PAL
[21:05:20] [PASSED] PAL-M
[21:05:20] [PASSED] PAL-N
[21:05:20] [PASSED] SECAM
[21:05:20] [PASSED] Mono
[21:05:20] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:05:20] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:05:20] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:05:20] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:05:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:05:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:05:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:05:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:05:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:05:20] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:05:20] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:05:20] [PASSED] VIC 96
[21:05:20] [PASSED] VIC 97
[21:05:20] [PASSED] VIC 101
[21:05:20] [PASSED] VIC 102
[21:05:20] [PASSED] VIC 106
[21:05:20] [PASSED] VIC 107
[21:05:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:05:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:05:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:05:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:05:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:05:20] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:05:20] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:05:20] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:05:20] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:05:20] [PASSED] Automatic
[21:05:20] [PASSED] Full
[21:05:20] [PASSED] Limited 16:235
[21:05:20] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:05:20] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:05:20] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:05:20] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:05:20] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:05:20] [PASSED] RGB
[21:05:20] [PASSED] YUV 4:2:0
[21:05:20] [PASSED] YUV 4:2:2
[21:05:20] [PASSED] YUV 4:4:4
[21:05:20] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:05:20] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:05:20] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:05:20] ============= drm_damage_helper (21 subtests) ==============
[21:05:20] [PASSED] drm_test_damage_iter_no_damage
[21:05:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:05:20] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:05:20] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:05:20] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:05:20] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:05:20] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:05:20] [PASSED] drm_test_damage_iter_simple_damage
[21:05:20] [PASSED] drm_test_damage_iter_single_damage
[21:05:20] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:05:20] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:05:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:05:20] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:05:20] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:05:20] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:05:20] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:05:20] [PASSED] drm_test_damage_iter_damage
[21:05:20] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:05:20] [PASSED] drm_test_damage_iter_damage_one_outside
[21:05:20] [PASSED] drm_test_damage_iter_damage_src_moved
[21:05:20] [PASSED] drm_test_damage_iter_damage_not_visible
[21:05:20] ================ [PASSED] drm_damage_helper ================
[21:05:20] ============== drm_dp_mst_helper (3 subtests) ==============
[21:05:20] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:05:20] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:05:20] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:05:20] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:05:20] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:05:20] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:05:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:05:20] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:05:20] [PASSED] Link rate 2000000 lane count 4
[21:05:20] [PASSED] Link rate 2000000 lane count 2
[21:05:20] [PASSED] Link rate 2000000 lane count 1
[21:05:20] [PASSED] Link rate 1350000 lane count 4
[21:05:20] [PASSED] Link rate 1350000 lane count 2
[21:05:20] [PASSED] Link rate 1350000 lane count 1
[21:05:20] [PASSED] Link rate 1000000 lane count 4
[21:05:20] [PASSED] Link rate 1000000 lane count 2
[21:05:20] [PASSED] Link rate 1000000 lane count 1
[21:05:20] [PASSED] Link rate 810000 lane count 4
[21:05:20] [PASSED] Link rate 810000 lane count 2
[21:05:20] [PASSED] Link rate 810000 lane count 1
[21:05:20] [PASSED] Link rate 540000 lane count 4
[21:05:20] [PASSED] Link rate 540000 lane count 2
[21:05:20] [PASSED] Link rate 540000 lane count 1
[21:05:20] [PASSED] Link rate 270000 lane count 4
[21:05:20] [PASSED] Link rate 270000 lane count 2
[21:05:20] [PASSED] Link rate 270000 lane count 1
[21:05:20] [PASSED] Link rate 162000 lane count 4
[21:05:20] [PASSED] Link rate 162000 lane count 2
[21:05:20] [PASSED] Link rate 162000 lane count 1
[21:05:20] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:05:20] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:05:20] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:05:20] [PASSED] DP_POWER_UP_PHY with port number
[21:05:20] [PASSED] DP_POWER_DOWN_PHY with port number
[21:05:20] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:05:20] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:05:20] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:05:20] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:05:20] [PASSED] DP_QUERY_PAYLOAD with port number
[21:05:20] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:05:20] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:05:20] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:05:20] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:05:20] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:05:20] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:05:20] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:05:20] [PASSED] DP_REMOTE_I2C_READ with port number
[21:05:20] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:05:20] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:05:20] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:05:20] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:05:20] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:05:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:05:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:05:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:05:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:05:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:05:20] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:05:20] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:05:20] ================ [PASSED] drm_dp_mst_helper ================
[21:05:20] ================== drm_exec (7 subtests) ===================
[21:05:20] [PASSED] sanitycheck
[21:05:20] [PASSED] test_lock
[21:05:20] [PASSED] test_lock_unlock
[21:05:20] [PASSED] test_duplicates
[21:05:20] [PASSED] test_prepare
[21:05:20] [PASSED] test_prepare_array
[21:05:20] [PASSED] test_multiple_loops
[21:05:20] ==================== [PASSED] drm_exec =====================
[21:05:20] =========== drm_format_helper_test (17 subtests) ===========
[21:05:20] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:05:20] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:05:20] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:05:20] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:05:20] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:05:20] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:05:20] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:05:20] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:05:20] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:05:20] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:05:20] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:05:20] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:05:20] ==================== drm_test_fb_swab  =====================
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ================ [PASSED] drm_test_fb_swab =================
[21:05:20] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:05:20] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:05:20] [PASSED] single_pixel_source_buffer
[21:05:20] [PASSED] single_pixel_clip_rectangle
[21:05:20] [PASSED] well_known_colors
[21:05:20] [PASSED] destination_pitch
[21:05:20] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:05:20] ================= drm_test_fb_clip_offset  =================
[21:05:20] [PASSED] pass through
[21:05:20] [PASSED] horizontal offset
[21:05:20] [PASSED] vertical offset
[21:05:20] [PASSED] horizontal and vertical offset
[21:05:20] [PASSED] horizontal offset (custom pitch)
[21:05:20] [PASSED] vertical offset (custom pitch)
[21:05:20] [PASSED] horizontal and vertical offset (custom pitch)
[21:05:20] ============= [PASSED] drm_test_fb_clip_offset =============
[21:05:20] =================== drm_test_fb_memcpy  ====================
[21:05:20] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:05:20] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:05:20] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:05:20] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:05:20] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:05:20] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:05:20] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:05:20] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:05:20] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:05:20] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:05:20] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:05:20] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:05:20] =============== [PASSED] drm_test_fb_memcpy ================
[21:05:20] ============= [PASSED] drm_format_helper_test ==============
[21:05:20] ================= drm_format (18 subtests) =================
[21:05:20] [PASSED] drm_test_format_block_width_invalid
[21:05:20] [PASSED] drm_test_format_block_width_one_plane
[21:05:20] [PASSED] drm_test_format_block_width_two_plane
[21:05:20] [PASSED] drm_test_format_block_width_three_plane
[21:05:20] [PASSED] drm_test_format_block_width_tiled
[21:05:20] [PASSED] drm_test_format_block_height_invalid
[21:05:20] [PASSED] drm_test_format_block_height_one_plane
[21:05:20] [PASSED] drm_test_format_block_height_two_plane
[21:05:20] [PASSED] drm_test_format_block_height_three_plane
[21:05:20] [PASSED] drm_test_format_block_height_tiled
[21:05:20] [PASSED] drm_test_format_min_pitch_invalid
[21:05:20] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:05:20] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:05:20] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:05:20] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:05:20] [PASSED] drm_test_format_min_pitch_two_plane
[21:05:20] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:05:20] [PASSED] drm_test_format_min_pitch_tiled
[21:05:20] =================== [PASSED] drm_format ====================
[21:05:20] ============== drm_framebuffer (10 subtests) ===============
[21:05:20] ========== drm_test_framebuffer_check_src_coords  ==========
[21:05:20] [PASSED] Success: source fits into fb
[21:05:20] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:05:20] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:05:20] [PASSED] Fail: overflowing fb with source width
[21:05:20] [PASSED] Fail: overflowing fb with source height
[21:05:20] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:05:20] [PASSED] drm_test_framebuffer_cleanup
[21:05:20] =============== drm_test_framebuffer_create  ===============
[21:05:20] [PASSED] ABGR8888 normal sizes
[21:05:20] [PASSED] ABGR8888 max sizes
[21:05:20] [PASSED] ABGR8888 pitch greater than min required
[21:05:20] [PASSED] ABGR8888 pitch less than min required
[21:05:20] [PASSED] ABGR8888 Invalid width
[21:05:20] [PASSED] ABGR8888 Invalid buffer handle
[21:05:20] [PASSED] No pixel format
[21:05:20] [PASSED] ABGR8888 Width 0
[21:05:20] [PASSED] ABGR8888 Height 0
[21:05:20] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:05:20] [PASSED] ABGR8888 Large buffer offset
[21:05:20] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:05:20] [PASSED] ABGR8888 Invalid flag
[21:05:20] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:05:20] [PASSED] ABGR8888 Valid buffer modifier
[21:05:20] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:05:20] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:05:20] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:05:20] [PASSED] NV12 Normal sizes
[21:05:20] [PASSED] NV12 Max sizes
[21:05:20] [PASSED] NV12 Invalid pitch
[21:05:20] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:05:20] [PASSED] NV12 different  modifier per-plane
[21:05:20] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:05:20] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:05:20] [PASSED] NV12 Modifier for inexistent plane
[21:05:20] [PASSED] NV12 Handle for inexistent plane
[21:05:20] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:05:20] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:05:20] [PASSED] YVU420 Normal sizes
[21:05:20] [PASSED] YVU420 Max sizes
[21:05:20] [PASSED] YVU420 Invalid pitch
[21:05:20] [PASSED] YVU420 Different pitches
[21:05:20] [PASSED] YVU420 Different buffer offsets/pitches
[21:05:20] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:05:20] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:05:20] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:05:20] [PASSED] YVU420 Valid modifier
[21:05:20] [PASSED] YVU420 Different modifiers per plane
[21:05:20] [PASSED] YVU420 Modifier for inexistent plane
[21:05:20] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:05:20] [PASSED] X0L2 Normal sizes
[21:05:20] [PASSED] X0L2 Max sizes
[21:05:20] [PASSED] X0L2 Invalid pitch
[21:05:20] [PASSED] X0L2 Pitch greater than minimum required
[21:05:20] [PASSED] X0L2 Handle for inexistent plane
[21:05:20] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:05:20] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:05:20] [PASSED] X0L2 Valid modifier
[21:05:20] [PASSED] X0L2 Modifier for inexistent plane
[21:05:20] =========== [PASSED] drm_test_framebuffer_create ===========
[21:05:20] [PASSED] drm_test_framebuffer_free
[21:05:20] [PASSED] drm_test_framebuffer_init
[21:05:20] [PASSED] drm_test_framebuffer_init_bad_format
[21:05:20] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:05:20] [PASSED] drm_test_framebuffer_lookup
[21:05:20] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:05:20] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:05:20] ================= [PASSED] drm_framebuffer =================
[21:05:20] ================ drm_gem_shmem (8 subtests) ================
[21:05:20] [PASSED] drm_gem_shmem_test_obj_create
[21:05:20] [PASSED] drm_gem_shmem_test_obj_create_private
[21:05:20] [PASSED] drm_gem_shmem_test_pin_pages
[21:05:20] [PASSED] drm_gem_shmem_test_vmap
[21:05:20] [PASSED] drm_gem_shmem_test_get_sg_table
[21:05:20] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:05:20] [PASSED] drm_gem_shmem_test_madvise
[21:05:20] [PASSED] drm_gem_shmem_test_purge
[21:05:20] ================== [PASSED] drm_gem_shmem ==================
[21:05:20] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[21:05:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:05:20] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:05:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:05:20] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:05:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:05:20] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:05:20] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:05:20] [PASSED] Automatic
[21:05:20] [PASSED] Full
[21:05:20] [PASSED] Limited 16:235
[21:05:20] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:05:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:05:20] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:05:20] [PASSED] drm_test_check_disable_connector
[21:05:20] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:05:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:05:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:05:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:05:20] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:05:20] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:05:20] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:05:20] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:05:20] [PASSED] drm_test_check_output_bpc_dvi
[21:05:20] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:05:20] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:05:20] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:05:20] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:05:20] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:05:20] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:05:20] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:05:20] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:05:20] ============ drm_test_check_hdmi_color_format  =============
[21:05:20] [PASSED] AUTO -> RGB
[21:05:20] [PASSED] YCBCR422 -> YUV422
[21:05:20] [PASSED] YCBCR420 -> YUV420
[21:05:20] [PASSED] YCBCR444 -> YUV444
[21:05:20] [PASSED] RGB -> RGB
[21:05:20] ======== [PASSED] drm_test_check_hdmi_color_format =========
[21:05:20] ======== drm_test_check_hdmi_color_format_420_only  ========
[21:05:20] [PASSED] RGB should fail
[21:05:20] [PASSED] YUV444 should fail
[21:05:20] [PASSED] YUV422 should fail
[21:05:20] [PASSED] YUV420 should work
[21:05:20] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[21:05:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:05:20] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:05:20] [PASSED] drm_test_check_broadcast_rgb_value
[21:05:20] [PASSED] drm_test_check_bpc_8_value
[21:05:20] [PASSED] drm_test_check_bpc_10_value
[21:05:20] [PASSED] drm_test_check_bpc_12_value
[21:05:20] [PASSED] drm_test_check_format_value
[21:05:20] [PASSED] drm_test_check_tmds_char_value
[21:05:20] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:05:20] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[21:05:20] [PASSED] drm_test_check_mode_valid
[21:05:20] [PASSED] drm_test_check_mode_valid_reject
[21:05:20] [PASSED] drm_test_check_mode_valid_reject_rate
[21:05:20] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:05:20] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[21:05:20] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[21:05:20] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[21:05:20] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:05:20] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[21:05:20] [PASSED] drm_test_check_infoframes
[21:05:20] [PASSED] drm_test_check_reject_avi_infoframe
[21:05:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[21:05:20] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[21:05:20] [PASSED] drm_test_check_reject_audio_infoframe
[21:05:20] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[21:05:20] ================= drm_managed (2 subtests) =================
[21:05:20] [PASSED] drm_test_managed_release_action
[21:05:20] [PASSED] drm_test_managed_run_action
[21:05:20] =================== [PASSED] drm_managed ===================
[21:05:20] =================== drm_mm (6 subtests) ====================
[21:05:20] [PASSED] drm_test_mm_init
[21:05:20] [PASSED] drm_test_mm_debug
[21:05:20] [PASSED] drm_test_mm_align32
[21:05:20] [PASSED] drm_test_mm_align64
[21:05:20] [PASSED] drm_test_mm_lowest
[21:05:20] [PASSED] drm_test_mm_highest
[21:05:20] ===================== [PASSED] drm_mm ======================
[21:05:20] ============= drm_modes_analog_tv (5 subtests) =============
[21:05:20] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:05:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:05:20] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:05:20] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:05:20] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:05:20] =============== [PASSED] drm_modes_analog_tv ===============
[21:05:20] ============== drm_panic_helper (3 subtests) ===============
[21:05:20] ============= drm_test_panic_screen_user_map  ==============
[21:05:20] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:05:20] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:05:20] ========= [PASSED] drm_test_panic_screen_user_map ==========
[21:05:20] ============= drm_test_panic_screen_user_page  =============
[21:05:20] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:05:20] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:05:20] ========= [PASSED] drm_test_panic_screen_user_page =========
[21:05:20] ========== drm_test_panic_screen_user_set_pixel  ===========
[21:05:20] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:05:20] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[21:05:20] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[21:05:20] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[21:05:20] ================ [PASSED] drm_panic_helper =================
[21:05:20] ============== drm_plane_helper (2 subtests) ===============
[21:05:20] =============== drm_test_check_plane_state  ================
[21:05:20] [PASSED] clipping_simple
[21:05:20] [PASSED] clipping_rotate_reflect
[21:05:20] [PASSED] positioning_simple
[21:05:20] [PASSED] upscaling
[21:05:20] [PASSED] downscaling
[21:05:20] [PASSED] rounding1
[21:05:20] [PASSED] rounding2
[21:05:20] [PASSED] rounding3
[21:05:20] [PASSED] rounding4
[21:05:20] =========== [PASSED] drm_test_check_plane_state ============
[21:05:20] =========== drm_test_check_invalid_plane_state  ============
[21:05:20] [PASSED] positioning_invalid
[21:05:20] [PASSED] upscaling_invalid
[21:05:20] [PASSED] downscaling_invalid
[21:05:20] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:05:20] ================ [PASSED] drm_plane_helper =================
[21:05:20] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:05:20] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:05:20] [PASSED] None
[21:05:20] [PASSED] PAL
[21:05:20] [PASSED] NTSC
[21:05:20] [PASSED] Both, NTSC Default
[21:05:20] [PASSED] Both, PAL Default
[21:05:20] [PASSED] Both, NTSC Default, with PAL on command-line
[21:05:20] [PASSED] Both, PAL Default, with NTSC on command-line
[21:05:20] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:05:20] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:05:20] ================== drm_rect (9 subtests) ===================
[21:05:20] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:05:20] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:05:20] [PASSED] drm_test_rect_clip_scaled_clipped
[21:05:20] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:05:20] ================= drm_test_rect_intersect  =================
[21:05:20] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:05:20] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:05:20] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:05:20] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:05:20] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:05:20] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:05:20] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:05:20] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:05:20] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:05:20] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:05:20] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:05:20] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:05:20] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:05:20] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:05:20] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:05:20] ============= [PASSED] drm_test_rect_intersect =============
[21:05:20] ================ drm_test_rect_calc_hscale  ================
[21:05:20] [PASSED] normal use
[21:05:20] [PASSED] out of max range
[21:05:20] [PASSED] out of min range
[21:05:20] [PASSED] zero dst
[21:05:20] [PASSED] negative src
[21:05:20] [PASSED] negative dst
[21:05:20] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:05:20] ================ drm_test_rect_calc_vscale  ================
[21:05:20] [PASSED] normal use
[21:05:20] [PASSED] out of max range
[21:05:20] [PASSED] out of min range
[21:05:20] [PASSED] zero dst
[21:05:20] [PASSED] negative src
[21:05:20] [PASSED] negative dst
[21:05:20] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:05:20] ================== drm_test_rect_rotate  ===================
[21:05:20] [PASSED] reflect-x
[21:05:20] [PASSED] reflect-y
[21:05:20] [PASSED] rotate-0
[21:05:20] [PASSED] rotate-90
[21:05:20] [PASSED] rotate-180
[21:05:20] [PASSED] rotate-270
[21:05:20] ============== [PASSED] drm_test_rect_rotate ===============
[21:05:20] ================ drm_test_rect_rotate_inv  =================
[21:05:20] [PASSED] reflect-x
[21:05:20] [PASSED] reflect-y
[21:05:20] [PASSED] rotate-0
[21:05:20] [PASSED] rotate-90
[21:05:20] [PASSED] rotate-180
[21:05:20] [PASSED] rotate-270
[21:05:20] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:05:20] ==================== [PASSED] drm_rect =====================
[21:05:20] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:05:20] ============ drm_test_sysfb_build_fourcc_list  =============
[21:05:20] [PASSED] no native formats
[21:05:20] [PASSED] XRGB8888 as native format
[21:05:20] [PASSED] remove duplicates
[21:05:20] [PASSED] convert alpha formats
[21:05:20] [PASSED] random formats
[21:05:20] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:05:20] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:05:20] ================== drm_fixp (2 subtests) ===================
[21:05:20] [PASSED] drm_test_int2fixp
[21:05:20] [PASSED] drm_test_sm2fixp
[21:05:20] ==================== [PASSED] drm_fixp =====================
[21:05:20] ============================================================
[21:05:20] Testing complete. Ran 671 tests: passed: 671
[21:05:20] Elapsed time: 27.665s total, 1.850s configuring, 25.349s building, 0.463s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:05:20] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:05:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:05:32] Starting KUnit Kernel (1/1)...
[21:05:32] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:05:32] ============= refcount_interrupt (4 subtests) ==============
[21:05:32] [PASSED] test_single_irq_change
[21:05:32] [PASSED] test_nested_irq_change
[21:05:32] [PASSED] test_multiple_irq_change
[21:05:32] [PASSED] test_irq_save
[21:05:32] =============== [PASSED] refcount_interrupt ================
[21:05:32] ================= ttm_device (5 subtests) ==================
[21:05:32] [PASSED] ttm_device_init_basic
[21:05:32] [PASSED] ttm_device_init_multiple
[21:05:32] [PASSED] ttm_device_fini_basic
[21:05:32] [PASSED] ttm_device_init_no_vma_man
[21:05:32] ================== ttm_device_init_pools  ==================
[21:05:32] [PASSED] No DMA allocations, no DMA32 required
[21:05:32] [PASSED] DMA allocations, DMA32 required
[21:05:32] [PASSED] No DMA allocations, DMA32 required
[21:05:32] [PASSED] DMA allocations, no DMA32 required
[21:05:32] ============== [PASSED] ttm_device_init_pools ==============
[21:05:32] =================== [PASSED] ttm_device ====================
[21:05:32] ================== ttm_pool (8 subtests) ===================
[21:05:32] ================== ttm_pool_alloc_basic  ===================
[21:05:32] [PASSED] One page
[21:05:32] [PASSED] More than one page
[21:05:32] [PASSED] Above the allocation limit
[21:05:32] [PASSED] One page, with coherent DMA mappings enabled
[21:05:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:05:32] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:05:32] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:05:32] [PASSED] One page
[21:05:32] [PASSED] More than one page
[21:05:32] [PASSED] Above the allocation limit
[21:05:32] [PASSED] One page, with coherent DMA mappings enabled
[21:05:32] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:05:32] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:05:32] [PASSED] ttm_pool_alloc_order_caching_match
[21:05:32] [PASSED] ttm_pool_alloc_caching_mismatch
[21:05:32] [PASSED] ttm_pool_alloc_order_mismatch
[21:05:32] [PASSED] ttm_pool_free_dma_alloc
[21:05:32] [PASSED] ttm_pool_free_no_dma_alloc
[21:05:32] [PASSED] ttm_pool_fini_basic
[21:05:32] ==================== [PASSED] ttm_pool =====================
[21:05:32] ================ ttm_resource (8 subtests) =================
[21:05:32] ================= ttm_resource_init_basic  =================
[21:05:32] [PASSED] Init resource in TTM_PL_SYSTEM
[21:05:32] [PASSED] Init resource in TTM_PL_VRAM
[21:05:32] [PASSED] Init resource in a private placement
[21:05:32] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:05:32] ============= [PASSED] ttm_resource_init_basic =============
[21:05:32] [PASSED] ttm_resource_init_pinned
[21:05:32] [PASSED] ttm_resource_fini_basic
[21:05:32] [PASSED] ttm_resource_manager_init_basic
[21:05:32] [PASSED] ttm_resource_manager_usage_basic
[21:05:32] [PASSED] ttm_resource_manager_set_used_basic
[21:05:32] [PASSED] ttm_sys_man_alloc_basic
[21:05:32] [PASSED] ttm_sys_man_free_basic
[21:05:32] ================== [PASSED] ttm_resource ===================
[21:05:32] =================== ttm_tt (15 subtests) ===================
[21:05:32] ==================== ttm_tt_init_basic  ====================
[21:05:32] [PASSED] Page-aligned size
[21:05:32] [PASSED] Extra pages requested
[21:05:32] ================ [PASSED] ttm_tt_init_basic ================
[21:05:32] [PASSED] ttm_tt_init_misaligned
[21:05:32] [PASSED] ttm_tt_fini_basic
[21:05:32] [PASSED] ttm_tt_fini_sg
[21:05:32] [PASSED] ttm_tt_fini_shmem
[21:05:32] [PASSED] ttm_tt_create_basic
[21:05:32] [PASSED] ttm_tt_create_invalid_bo_type
[21:05:32] [PASSED] ttm_tt_create_ttm_exists
[21:05:32] [PASSED] ttm_tt_create_failed
[21:05:32] [PASSED] ttm_tt_destroy_basic
[21:05:32] [PASSED] ttm_tt_populate_null_ttm
[21:05:32] [PASSED] ttm_tt_populate_populated_ttm
[21:05:32] [PASSED] ttm_tt_unpopulate_basic
[21:05:32] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:05:32] [PASSED] ttm_tt_swapin_basic
[21:05:32] ===================== [PASSED] ttm_tt ======================
[21:05:32] =================== ttm_bo (14 subtests) ===================
[21:05:32] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:05:32] [PASSED] Cannot be interrupted and sleeps
[21:05:32] [PASSED] Cannot be interrupted, locks straight away
[21:05:32] [PASSED] Can be interrupted, sleeps
[21:05:32] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:05:32] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:05:32] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:05:32] [PASSED] ttm_bo_reserve_double_resv
[21:05:32] [PASSED] ttm_bo_reserve_interrupted
[21:05:32] [PASSED] ttm_bo_reserve_deadlock
[21:05:32] [PASSED] ttm_bo_unreserve_basic
[21:05:32] [PASSED] ttm_bo_unreserve_pinned
[21:05:32] [PASSED] ttm_bo_unreserve_bulk
[21:05:32] [PASSED] ttm_bo_fini_basic
[21:05:32] [PASSED] ttm_bo_fini_shared_resv
[21:05:32] [PASSED] ttm_bo_pin_basic
[21:05:32] [PASSED] ttm_bo_pin_unpin_resource
[21:05:32] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:05:32] ===================== [PASSED] ttm_bo ======================
[21:05:32] ============== ttm_bo_validate (22 subtests) ===============
[21:05:32] ============== ttm_bo_init_reserved_sys_man  ===============
[21:05:32] [PASSED] Buffer object for userspace
[21:05:32] [PASSED] Kernel buffer object
[21:05:32] [PASSED] Shared buffer object
[21:05:32] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:05:32] ============== ttm_bo_init_reserved_mock_man  ==============
[21:05:32] [PASSED] Buffer object for userspace
[21:05:32] [PASSED] Kernel buffer object
[21:05:32] [PASSED] Shared buffer object
[21:05:32] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:05:32] [PASSED] ttm_bo_init_reserved_resv
[21:05:32] ================== ttm_bo_validate_basic  ==================
[21:05:32] [PASSED] Buffer object for userspace
[21:05:32] [PASSED] Kernel buffer object
[21:05:32] [PASSED] Shared buffer object
[21:05:32] ============== [PASSED] ttm_bo_validate_basic ==============
[21:05:32] [PASSED] ttm_bo_validate_invalid_placement
[21:05:32] ============= ttm_bo_validate_same_placement  ==============
[21:05:32] [PASSED] System manager
[21:05:32] [PASSED] VRAM manager
[21:05:32] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:05:32] [PASSED] ttm_bo_validate_failed_alloc
[21:05:32] [PASSED] ttm_bo_validate_pinned
[21:05:32] [PASSED] ttm_bo_validate_busy_placement
[21:05:32] ================ ttm_bo_validate_multihop  =================
[21:05:32] [PASSED] Buffer object for userspace
[21:05:32] [PASSED] Kernel buffer object
[21:05:32] [PASSED] Shared buffer object
[21:05:32] ============ [PASSED] ttm_bo_validate_multihop =============
[21:05:32] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:05:32] [PASSED] Buffer object in system domain, no page vector
[21:05:32] [PASSED] Buffer object in system domain with an existing page vector
[21:05:32] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:05:32] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:05:32] [PASSED] Buffer object for userspace
[21:05:32] [PASSED] Kernel buffer object
[21:05:32] [PASSED] Shared buffer object
[21:05:32] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:05:32] [PASSED] ttm_bo_validate_move_fence_signaled
[21:05:32] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:05:32] [PASSED] Waits for GPU
[21:05:32] [PASSED] Tries to lock straight away
[21:05:33] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:05:33] [PASSED] ttm_bo_validate_swapout
[21:05:33] [PASSED] ttm_bo_validate_happy_evict
[21:05:33] [PASSED] ttm_bo_validate_all_pinned_evict
[21:05:33] [PASSED] ttm_bo_validate_allowed_only_evict
[21:05:33] [PASSED] ttm_bo_validate_deleted_evict
[21:05:33] [PASSED] ttm_bo_validate_busy_domain_evict
[21:05:33] [PASSED] ttm_bo_validate_evict_gutting
[21:05:33] [PASSED] ttm_bo_validate_recrusive_evict
[21:05:33] ================= [PASSED] ttm_bo_validate =================
[21:05:33] ============================================================
[21:05:33] Testing complete. Ran 106 tests: passed: 106
[21:05:33] Elapsed time: 12.176s total, 1.796s configuring, 10.115s building, 0.213s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[21:05:33] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:05:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:05:43] Starting KUnit Kernel (1/1)...
[21:05:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:05:43] ============= refcount_interrupt (4 subtests) ==============
[21:05:43] [PASSED] test_single_irq_change
[21:05:43] [PASSED] test_nested_irq_change
[21:05:43] [PASSED] test_multiple_irq_change
[21:05:43] [PASSED] test_irq_save
[21:05:43] =============== [PASSED] refcount_interrupt ================
[21:05:43] =============== dma-buf-fence (12 subtests) ================
[21:05:43] [PASSED] test_sanitycheck
[21:05:43] [PASSED] test_signaling
[21:05:43] [PASSED] test_add_callback
[21:05:43] [PASSED] test_late_add_callback
[21:05:43] [PASSED] test_rm_callback
[21:05:43] [PASSED] test_late_rm_callback
[21:05:43] [PASSED] test_status
[21:05:43] [PASSED] test_error
[21:05:43] [PASSED] test_wait
[21:05:43] [PASSED] test_wait_timeout
[21:05:43] [PASSED] test_stub
[21:05:43] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[21:05:43] ================== [PASSED] dma-buf-fence ==================
[21:05:43] ============ dma-buf-fence-chain (11 subtests) =============
[21:05:43] [PASSED] test_sanitycheck
[21:05:43] [PASSED] test_find_seqno
[21:05:43] [PASSED] test_find_signaled
[21:05:43] [PASSED] test_find_out_of_order
[21:05:48] [PASSED] test_find_gap
[21:05:48] [PASSED] test_find_race
[21:05:48] [PASSED] test_signal_forward
[21:05:48] [PASSED] test_signal_backward
[21:05:48] [PASSED] test_wait_forward
[21:05:48] [PASSED] test_wait_backward
[21:05:48] [PASSED] test_wait_random
[21:05:48] =============== [PASSED] dma-buf-fence-chain ===============
[21:05:48] ============ dma-buf-fence-unwrap (10 subtests) ============
[21:05:48] [PASSED] test_sanitycheck
[21:05:48] [PASSED] test_unwrap_array
[21:05:48] [PASSED] test_unwrap_chain
[21:05:48] [PASSED] test_unwrap_chain_array
[21:05:48] [PASSED] test_unwrap_merge
[21:05:48] [PASSED] test_unwrap_merge_duplicate
[21:05:48] [PASSED] test_unwrap_merge_seqno
[21:05:48] [PASSED] test_unwrap_merge_order
[21:05:48] [PASSED] test_unwrap_merge_complex
[21:05:48] [PASSED] test_unwrap_merge_complex_seqno
[21:05:48] ============== [PASSED] dma-buf-fence-unwrap ===============
[21:05:48] ================ dma-buf-resv (5 subtests) =================
[21:05:48] [PASSED] test_sanitycheck
[21:05:48] ===================== test_signaling  ======================
[21:05:48] [PASSED] kernel
[21:05:48] [PASSED] write
[21:05:48] [PASSED] read
[21:05:48] [PASSED] bookkeep
[21:05:48] ================= [PASSED] test_signaling ==================
[21:05:48] ====================== test_for_each  ======================
[21:05:48] [PASSED] kernel
[21:05:48] [PASSED] write
[21:05:48] [PASSED] read
[21:05:48] [PASSED] bookkeep
[21:05:48] ================== [PASSED] test_for_each ==================
[21:05:48] ================= test_for_each_unlocked  ==================
[21:05:48] [PASSED] kernel
[21:05:48] [PASSED] write
[21:05:48] [PASSED] read
[21:05:48] [PASSED] bookkeep
[21:05:48] ============= [PASSED] test_for_each_unlocked ==============
[21:05:48] ===================== test_get_fences  =====================
[21:05:48] [PASSED] kernel
[21:05:48] [PASSED] write
[21:05:48] [PASSED] read
[21:05:48] [PASSED] bookkeep
[21:05:48] ================= [PASSED] test_get_fences =================
[21:05:48] ================== [PASSED] dma-buf-resv ===================
[21:05:48] ============================================================
[21:05:48] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[21:05:48] Elapsed time: 15.709s total, 1.823s configuring, 8.565s building, 5.279s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 36+ messages in thread

* ✓ Xe.CI.BAT: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev3)
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (13 preceding siblings ...)
  2026-09-24 21:05 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev3) Patchwork
@ 2026-09-24 22:34 ` Patchwork
  2026-09-25 11:16 ` ✗ Xe.CI.FULL: failure " Patchwork
  15 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2026-09-24 22:34 UTC (permalink / raw)
  To: Karthik Poosa; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 2306 bytes --]

== Series Details ==

Series: drm/xe/hwmon: Update hwmon thermal mailbox (rev3)
URL   : https://patchwork.freedesktop.org/series/174898/
State : success

== Summary ==

CI Bug Log - changes from xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371_BAT -> xe-pw-174898v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (15 -> 15)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-174898v3_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-bmg-2:          [PASS][1] -> [ABORT][2] ([Intel XE#8007])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html

  * igt@xe_waitfence@engine:
    - bat-ptl-1:          [PASS][3] -> [FAIL][4] ([Intel XE#9109])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/bat-ptl-1/igt@xe_waitfence@engine.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/bat-ptl-1/igt@xe_waitfence@engine.html

  
#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-ptl-2:          [FAIL][5] ([Intel XE#9109]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/bat-ptl-2/igt@xe_waitfence@engine.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/bat-ptl-2/igt@xe_waitfence@engine.html

  
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#9109]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9109


Build changes
-------------

  * Linux: xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371 -> xe-pw-174898v3

  IGT_9112: 8d3284b5ae16ca1aef353dfaffb6c0896ceacc19 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371: 2ac16c180109b3f1ed00e7a2c4459eaacfc80371
  xe-pw-174898v3: 174898v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/index.html

[-- Attachment #2: Type: text/html, Size: 3003 bytes --]

^ permalink raw reply	[flat|nested] 36+ messages in thread

* ✗ Xe.CI.FULL: failure for drm/xe/hwmon: Update hwmon thermal mailbox (rev3)
  2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
                   ` (14 preceding siblings ...)
  2026-09-24 22:34 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-09-25 11:16 ` Patchwork
  15 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2026-09-25 11:16 UTC (permalink / raw)
  To: Karthik Poosa; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 56275 bytes --]

== Series Details ==

Series: drm/xe/hwmon: Update hwmon thermal mailbox (rev3)
URL   : https://patchwork.freedesktop.org/series/174898/
State : failure

== Summary ==

CI Bug Log - changes from xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371_FULL -> xe-pw-174898v3_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-174898v3_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-174898v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-174898v3_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-c-edp-1:
    - shard-ptl:          NOTRUN -> [DMESG-WARN][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_async_flips@async-flip-suspend-resume@pipe-c-edp-1.html

  
Known issues
------------

  Here are the changes found in xe-pw-174898v3_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-write:
    - shard-bmg:          NOTRUN -> [FAIL][2] ([Intel XE#8583])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@intel_hwmon@hwmon-write.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-ptl:          NOTRUN -> [ABORT][3] ([Intel XE#9362] / [Intel XE#9387])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-a-edp-1:
    - shard-ptl:          NOTRUN -> [ABORT][4] ([Intel XE#9362]) +2 other tests abort
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-edp-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-ptl:          NOTRUN -> [SKIP][5] ([Intel XE#6925])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-ptl:          NOTRUN -> [SKIP][6] ([Intel XE#5901])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2327]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-ptl:          NOTRUN -> [SKIP][8] ([Intel XE#7085])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-addfb-size-overflow:
    - shard-ptl:          NOTRUN -> [SKIP][9] ([Intel XE#5855])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@kms_big_fb@x-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-ptl:          NOTRUN -> [SKIP][10] ([Intel XE#5808]) +20 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#1124]) +5 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2328] / [Intel XE#7367])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-ptl:          NOTRUN -> [SKIP][13] ([Intel XE#5851])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#7679]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p:
    - shard-ptl:          NOTRUN -> [SKIP][15] ([Intel XE#7679]) +2 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_bw@connected-linear-tiling-4-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2560x1440p:
    - shard-ptl:          NOTRUN -> [SKIP][16] ([Intel XE#367]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_bw@linear-tiling-3-displays-target-2560x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs:
    - shard-ptl:          NOTRUN -> [SKIP][17] ([Intel XE#5822]) +15 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2887])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-hdmi-a-3:
    - shard-bmg:          [PASS][19] -> [INCOMPLETE][20] ([Intel XE#7084] / [Intel XE#8150])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-hdmi-a-3.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#3432]) +2 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-edp-1:
    - shard-ptl:          [PASS][22] -> [ABORT][23] ([Intel XE#9362]) +4 other tests abort
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-ptl-3/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-edp-1.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2652]) +17 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-ptl:          NOTRUN -> [SKIP][25] ([Intel XE#2252]) +7 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-ptl:          NOTRUN -> [SKIP][26] ([Intel XE#5824])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020:
    - shard-ptl:          NOTRUN -> [SKIP][27] ([Intel XE#8391]) +5 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2252]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lim@pipe-c-plane-1:
    - shard-bmg:          NOTRUN -> [FAIL][29] ([Intel XE#9333]) +12 other tests fail
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt2020-lim@pipe-c-plane-1.html

  * igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim@pipe-c-plane-1:
    - shard-ptl:          NOTRUN -> [FAIL][30] ([Intel XE#9333]) +25 other tests fail
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim@pipe-c-plane-1.html

  * igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-a-plane-3:
    - shard-ptl:          NOTRUN -> [SKIP][31] ([Intel XE#6969]) +7 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-a-plane-3.html

  * igt@kms_content_protection@dp-mst-type-0-suspend-resume:
    - shard-ptl:          NOTRUN -> [SKIP][32] ([Intel XE#6974])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html

  * igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][33] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent-hdcp14:
    - shard-ptl:          NOTRUN -> [SKIP][34] ([Intel XE#7642])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@kms_content_protection@uevent-hdcp14.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2320]) +3 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_crc@cursor-rapid-movement-64x21:
    - shard-ptl:          NOTRUN -> [SKIP][36] ([Intel XE#5900]) +5 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-ptl:          NOTRUN -> [SKIP][38] ([Intel XE#5962]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-ptl:          NOTRUN -> [SKIP][39] ([Intel XE#5962] / [Intel XE#7343]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-ptl:          NOTRUN -> [SKIP][40] ([Intel XE#6035])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#4331] / [Intel XE#7227])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-with-bpc-formats-ultrajoiner:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#8265])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_dsc@dsc-with-bpc-formats-ultrajoiner.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-ptl:          NOTRUN -> [SKIP][43] ([Intel XE#5907]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#4422] / [Intel XE#7442])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3:
    - shard-bmg:          [PASS][45] -> [DMESG-WARN][46] ([Intel XE#9390]) +1 other test dmesg-warn
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-ptl:          NOTRUN -> [SKIP][47] ([Intel XE#2316]) +5 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [PASS][48] -> [FAIL][49] ([Intel XE#301])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][50] -> [FAIL][51] ([Intel XE#301] / [Intel XE#3149])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-ptl:          NOTRUN -> [SKIP][52] ([Intel XE#5828]) +3 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-ptl:          NOTRUN -> [SKIP][53] ([Intel XE#7178]) +4 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][55] ([Intel XE#6312]) +18 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#4141]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#7061] / [Intel XE#7356])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt:
    - shard-ptl:          NOTRUN -> [SKIP][58] ([Intel XE#5800] / [Intel XE#6312]) +13 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][59] ([Intel XE#7061] / [Intel XE#7356]) +5 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][60] ([Intel XE#2311]) +20 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][61] ([Intel XE#7061]) +5 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][62] ([Intel XE#7865]) +29 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-ptl:          NOTRUN -> [SKIP][63] ([Intel XE#5812]) +100 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y:
    - shard-ptl:          NOTRUN -> [SKIP][64] ([Intel XE#7399])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#2313]) +20 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_hdmi_audio_bw@audio-bw-hblank80:
    - shard-ptl:          NOTRUN -> [SKIP][66] ([Intel XE#9312]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html

  * igt@kms_hdr@static-toggle:
    - shard-ptl:          NOTRUN -> [SKIP][67] ([Intel XE#5917] / [Intel XE#6174])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#4298] / [Intel XE#5873])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#6911] / [Intel XE#7466])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-ptl:          NOTRUN -> [SKIP][70] ([Intel XE#6900])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_mst@mst-suspend-read-crc:
    - shard-ptl:          NOTRUN -> [SKIP][71] ([Intel XE#8348])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_mst@mst-suspend-read-crc.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-ptl:          NOTRUN -> [SKIP][72] ([Intel XE#6912])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#7283])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier:
    - shard-ptl:          NOTRUN -> [SKIP][74] ([Intel XE#7283]) +4 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2393])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-ptl:          NOTRUN -> [SKIP][76] ([Intel XE#4596] / [Intel XE#5854])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5:
    - shard-ptl:          NOTRUN -> [SKIP][77] ([Intel XE#6886]) +4 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@kms_plane_scaling@planes-downscale-factor-0-5.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-ptl:          NOTRUN -> [SKIP][79] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc3co-vpb-simulation@psr2-yuv420:
    - shard-ptl:          NOTRUN -> [SKIP][80] ([Intel XE#8396]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_pm_dc@dc3co-vpb-simulation@psr2-yuv420.html

  * igt@kms_pm_dc@dc5-psr-suspend-resume:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#8854])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_pm_dc@dc5-psr-suspend-resume.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#7794])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-ptl:          NOTRUN -> [SKIP][83] ([Intel XE#7304]) +3 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][84] ([Intel XE#5858]) +1 other test skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][85] ([Intel XE#5858] / [Intel XE#7304]) +3 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#1489]) +3 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#2387] / [Intel XE#7429])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-cursor-plane-move:
    - shard-ptl:          NOTRUN -> [SKIP][88] ([Intel XE#1406]) +3 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_psr@fbc-pr-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-ptl:          NOTRUN -> [SKIP][89] ([Intel XE#1406] / [Intel XE#5835]) +3 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@psr-basic:
    - shard-bmg:          NOTRUN -> [SKIP][90] ([Intel XE#2234] / [Intel XE#2850]) +3 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_psr@psr-basic.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#2234])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-ptl:          NOTRUN -> [SKIP][92] ([Intel XE#5821]) +2 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-ptl:          NOTRUN -> [SKIP][93] ([Intel XE#5813]) +1 other test skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#3904] / [Intel XE#7342])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#2413])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-ptl:          NOTRUN -> [SKIP][96] ([Intel XE#5910])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@invalid-filter-with-plane:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#6503])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@kms_sharpness_filter@invalid-filter-with-plane.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-ptl:          NOTRUN -> [SKIP][98] ([Intel XE#5848])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-ptl:          NOTRUN -> [SKIP][99] ([Intel XE#5857])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@cmrr-video-mode:
    - shard-bmg:          NOTRUN -> [SKIP][100] ([Intel XE#9271])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_vrr@cmrr-video-mode.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-ptl:          NOTRUN -> [SKIP][101] ([Intel XE#5948] / [Intel XE#9277])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@runner@aborted:
    - shard-ptl:          NOTRUN -> [FAIL][102] ([Intel XE#9371])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@runner@aborted.html

  * igt@sriov_basic@pf-unbind-with-vf-probed:
    - shard-bmg:          NOTRUN -> [ABORT][103] ([Intel XE#8868])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@sriov_basic@pf-unbind-with-vf-probed.html

  * igt@xe_ccs@suspend-resume:
    - shard-bmg:          [PASS][104] -> [ABORT][105] ([Intel XE#9362]) +2 other tests abort
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-8/igt@xe_ccs@suspend-resume.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-7/igt@xe_ccs@suspend-resume.html

  * igt@xe_evict@evict-beng-threads-large-multi-vm:
    - shard-ptl:          NOTRUN -> [SKIP][106] ([Intel XE#5764]) +18 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@xe_evict@evict-beng-threads-large-multi-vm.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd:
    - shard-ptl:          NOTRUN -> [SKIP][107] ([Intel XE#6144]) +1 other test skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd.html

  * igt@xe_exec_balancer@many-virtual-userptr-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][108] ([Intel XE#7482]) +24 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@xe_exec_balancer@many-virtual-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap:
    - shard-ptl:          NOTRUN -> [SKIP][109] ([Intel XE#5575] / [Intel XE#7484]) +8 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html

  * igt@xe_exec_basic@multigpu-once-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][110] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@xe_exec_basic@multigpu-once-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-imm:
    - shard-ptl:          NOTRUN -> [SKIP][111] ([Intel XE#8374]) +14 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr-rebind-imm.html

  * igt@xe_exec_fault_mode@once-multi-queue-rebind-imm:
    - shard-bmg:          NOTRUN -> [SKIP][112] ([Intel XE#8374]) +4 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@xe_exec_fault_mode@once-multi-queue-rebind-imm.html

  * igt@xe_exec_multi_queue@few-execs-basic-smem:
    - shard-ptl:          NOTRUN -> [SKIP][113] ([Intel XE#8364]) +30 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@xe_exec_multi_queue@few-execs-basic-smem.html

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#8364]) +11 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@xe_exec_multi_queue@max-queues-preempt-mode-userptr-invalidate.html

  * igt@xe_exec_reset@cm-multi-queue-gt-reset:
    - shard-bmg:          NOTRUN -> [SKIP][115] ([Intel XE#8369])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@xe_exec_reset@cm-multi-queue-gt-reset.html

  * igt@xe_exec_reset@multi-queue-gt-reset:
    - shard-ptl:          NOTRUN -> [SKIP][116] ([Intel XE#8369]) +3 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@xe_exec_reset@multi-queue-gt-reset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-huge-nomemset:
    - shard-lnl:          [PASS][117] -> [FAIL][118] ([Intel XE#8058])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-lnl-6/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-huge-nomemset.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-huge-nomemset.html

  * igt@xe_exec_threads@threads-multi-queue-hang-fd-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][119] ([Intel XE#8378]) +2 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@xe_exec_threads@threads-multi-queue-hang-fd-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-shared-vm-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][120] ([Intel XE#8378]) +8 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@xe_exec_threads@threads-multi-queue-shared-vm-rebind.html

  * igt@xe_fault_injection@vm-create-fail-xe_pt_create:
    - shard-lnl:          [PASS][121] -> [ABORT][122] ([Intel XE#8007])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-lnl-6/igt@xe_fault_injection@vm-create-fail-xe_pt_create.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-lnl-1/igt@xe_fault_injection@vm-create-fail-xe_pt_create.html

  * igt@xe_gpgpu_fill@offset-4x4:
    - shard-ptl:          NOTRUN -> [SKIP][123] ([Intel XE#7954])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@xe_gpgpu_fill@offset-4x4.html

  * igt@xe_madvise@atomic-device:
    - shard-ptl:          NOTRUN -> [SKIP][124] ([Intel XE#7980])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@xe_madvise@atomic-device.html

  * igt@xe_mempage_offline@inject-duplicate-page:
    - shard-ptl:          NOTRUN -> [SKIP][125] ([Intel XE#9203])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@xe_mempage_offline@inject-duplicate-page.html

  * igt@xe_mmap@pci-membarrier-bad-object:
    - shard-ptl:          NOTRUN -> [SKIP][126] ([Intel XE#5100] / [Intel XE#7408])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@xe_mmap@pci-membarrier-bad-object.html

  * igt@xe_multigpu_svm@mgpu-coherency-fail-basic:
    - shard-bmg:          NOTRUN -> [SKIP][127] ([Intel XE#6964])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@xe_multigpu_svm@mgpu-coherency-fail-basic.html

  * igt@xe_multigpu_svm@mgpu-pagefault-basic:
    - shard-ptl:          NOTRUN -> [SKIP][128] ([Intel XE#6964]) +3 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@xe_multigpu_svm@mgpu-pagefault-basic.html

  * igt@xe_page_reclaim@many-vma-same-bo:
    - shard-ptl:          NOTRUN -> [SKIP][129] ([Intel XE#7793]) +2 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@xe_page_reclaim@many-vma-same-bo.html

  * igt@xe_pat@l2-flush-opt-svm-pat-restrict:
    - shard-bmg:          NOTRUN -> [SKIP][130] ([Intel XE#7590])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@xe_pat@l2-flush-opt-svm-pat-restrict.html

  * igt@xe_pat@pat-sw-hw-compare:
    - shard-ptl:          NOTRUN -> [FAIL][131] ([Intel XE#7695]) +1 other test fail
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@xe_pat@pat-sw-hw-compare.html

  * igt@xe_pm@d3cold-mocs:
    - shard-ptl:          NOTRUN -> [SKIP][132] ([Intel XE#5741]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-1/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pm@d3hot-mmap-vram:
    - shard-ptl:          NOTRUN -> [SKIP][133] ([Intel XE#5834])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-4/igt@xe_pm@d3hot-mmap-vram.html

  * igt@xe_pm@s3-mocs:
    - shard-ptl:          NOTRUN -> [SKIP][134] ([Intel XE#6867]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@xe_pm@s3-mocs.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-lnl:          [PASS][135] -> [ABORT][136] ([Intel XE#9362]) +2 other tests abort
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-lnl-2/igt@xe_pm@s4-vm-bind-userptr.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-lnl-5/igt@xe_pm@s4-vm-bind-userptr.html

  * igt@xe_query@multigpu-query-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][137] ([Intel XE#944])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@xe_query@multigpu-query-cs-cycles.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-ptl:          NOTRUN -> [SKIP][138] ([Intel XE#6019]) +1 other test skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@xe_query@multigpu-query-invalid-size.html

  * igt@xe_survivability@i2c-functionality:
    - shard-ptl:          NOTRUN -> [SKIP][139] ([Intel XE#8415] / [Intel XE#8432])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-3/igt@xe_survivability@i2c-functionality.html

  * igt@xe_vm@out-of-memory:
    - shard-ptl:          NOTRUN -> [SKIP][140] ([Intel XE#5745] / [Intel XE#7892])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@xe_vm@out-of-memory.html

  * igt@xe_vm@overcommit-fault-vram-lr-no-overcommit:
    - shard-ptl:          NOTRUN -> [SKIP][141] ([Intel XE#7892])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@xe_vm@overcommit-fault-vram-lr-no-overcommit.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-bmg:          [ABORT][142] ([Intel XE#9399] / [Intel XE#9409]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-5/igt@kms_async_flips@async-flip-suspend-resume.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-b-hdmi-a-3:
    - shard-bmg:          [ABORT][144] ([Intel XE#9409]) -> [PASS][145]
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-5/igt@kms_async_flips@async-flip-suspend-resume@pipe-b-hdmi-a-3.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_async_flips@async-flip-suspend-resume@pipe-b-hdmi-a-3.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1:
    - shard-ptl:          [ABORT][146] ([Intel XE#9362]) -> [PASS][147] +12 other tests pass
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-ptl-5/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-2/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [FAIL][148] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][149] +1 other test pass
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [FAIL][150] ([Intel XE#301]) -> [PASS][151] +1 other test pass
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [DMESG-WARN][152] ([Intel XE#9365]) -> [PASS][153] +2 other tests pass
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-8/igt@kms_flip@flip-vs-suspend-interruptible.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-9/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-ptl:          [ABORT][154] ([Intel XE#9363]) -> [PASS][155] +1 other test pass
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-ptl-5/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-ptl-5/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][156] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][157]
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-6/igt@xe_evict@evict-mixed-many-threads-small.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create_bind:
    - shard-bmg:          [ABORT][158] ([Intel XE#8007]) -> [PASS][159]
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-2/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create_bind.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-6/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create_bind.html

  * igt@xe_gt_freq@freq_suspend:
    - shard-bmg:          [ABORT][160] ([Intel XE#9362]) -> [PASS][161]
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-9/igt@xe_gt_freq@freq_suspend.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-8/igt@xe_gt_freq@freq_suspend.html

  
#### Warnings ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][162] ([Intel XE#7084] / [Intel XE#8150]) -> [ABORT][163] ([Intel XE#9362])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][164] ([Intel XE#301]) -> [FAIL][165] ([Intel XE#301] / [Intel XE#3149])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][166] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][167] ([Intel XE#1729] / [Intel XE#7424])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][168] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][169] ([Intel XE#2509] / [Intel XE#7437])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_pat@pat-sw-hw-suspend:
    - shard-bmg:          [DMESG-FAIL][170] -> [FAIL][171] ([Intel XE#7695])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371/shard-bmg-7/igt@xe_pat@pat-sw-hw-suspend.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/shard-bmg-5/igt@xe_pat@pat-sw-hw-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5741
  [Intel XE#5745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5745
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
  [Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
  [Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5821
  [Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
  [Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
  [Intel XE#5828]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5828
  [Intel XE#5834]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5834
  [Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5851]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5851
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5855]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5855
  [Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
  [Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
  [Intel XE#5873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5873
  [Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
  [Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
  [Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
  [Intel XE#5910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5910
  [Intel XE#5917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5917
  [Intel XE#5948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5948
  [Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
  [Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6144
  [Intel XE#6174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6174
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6867]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6867
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6925
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7227
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7794
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7954]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7954
  [Intel XE#7980]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7980
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8058]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8058
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8348
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8391
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8415]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8415
  [Intel XE#8432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8432
  [Intel XE#8583]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8583
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8854
  [Intel XE#8868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8868
  [Intel XE#9203]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9203
  [Intel XE#9271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9271
  [Intel XE#9277]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9277
  [Intel XE#9312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9312
  [Intel XE#9333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9333
  [Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
  [Intel XE#9363]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9363
  [Intel XE#9365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9365
  [Intel XE#9371]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9371
  [Intel XE#9387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9387
  [Intel XE#9390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9390
  [Intel XE#9399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9399
  [Intel XE#9409]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9409
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371 -> xe-pw-174898v3

  IGT_9112: 8d3284b5ae16ca1aef353dfaffb6c0896ceacc19 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5823-2ac16c180109b3f1ed00e7a2c4459eaacfc80371: 2ac16c180109b3f1ed00e7a2c4459eaacfc80371
  xe-pw-174898v3: 174898v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-174898v3/index.html

[-- Attachment #2: Type: text/html, Size: 62898 bytes --]

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit
  2026-09-24 20:54 ` [PATCH v6 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
@ 2026-09-28  0:11   ` Rodrigo Vivi
  2026-09-28 15:32     ` Poosa, Karthik
  0 siblings, 1 reply; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-28  0:11 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:17AM +0530, Karthik Poosa wrote:
> Return early when the pcode read operation fails in
> xe_hwmon_pcode_rmw_power_limit() and check the returned error in
> callers to avoid updating power limit settings with invalid data.
> 
> Fixes: 8aa7306631f0 ("drm/xe/hwmon: Fix xe_hwmon_power_max_write")
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
> v2: Address sashiko-bot@kernel.org review comments. Return -EIO instead of
>     0 on errors in the sysfs store callback to prevent potential userspace
>     infinite loops.
> 
>  drivers/gpu/drm/xe/xe_hwmon.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 5edeac961ec3..be3fb6733b6f 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -232,9 +232,11 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
>  						  READ_PSYSGPU_POWER_LIMIT :
>  						  READ_PACKAGE_POWER_LIMIT,
>  						  prepare_power_limit_param2(hwmon)), &val0, &val1);
> -	if (ret)
> -		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
> +	if (ret) {
> +		drm_err(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
>  			channel, val0, val1, ret);
> +		return ret;
> +	}
>  
>  	if (attr == PL1_HWMON_ATTR)
>  		val0 = (val0 & ~clr) | set;
> @@ -394,7 +396,9 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channe
>  		if (hwmon->xe->info.has_mbx_power_limits) {
>  			drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n",
>  				PWR_ATTR_TO_STR(attr), channel);
> -			xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
> +			ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
> +			if (ret)
> +				goto unlock;
>  			xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
>  		} else {
>  			reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);
> @@ -679,11 +683,13 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
>  
>  	mutex_lock(&hwmon->hwmon_lock);
>  
> -	if (hwmon->xe->info.has_mbx_power_limits)
> -		xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
> -	else
> +	if (hwmon->xe->info.has_mbx_power_limits) {
> +		if (xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy))
> +			count = -EIO;

please use ret for this, not changing count...
and you may set ret = count earlier, or something like that...

> +	} else {
>  		r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
>  				  PWR_LIM_TIME, rxy);
> +	}
>  
>  	mutex_unlock(&hwmon->hwmon_lock);
>  
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude
  2026-09-24 20:54 ` [PATCH v6 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude Karthik Poosa
@ 2026-09-28  0:15   ` Rodrigo Vivi
  0 siblings, 0 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-28  0:15 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:18AM +0530, Karthik Poosa wrote:
> The mailbox temperature is an 8-bit sign-magnitude value (bit 7 sign,
> bits 6:0 magnitude, range -127..127), not two's-complement. Casting the
> raw byte to s8 decodes negative readings incorrectly.
> 
> Add mbx_temp_decode(), store the raw byte as u8, and use it in
> get_mc_temp() and get_pcie_temp() so temperatures are decoded correctly.
> 
> Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> ---
>  drivers/gpu/drm/xe/xe_hwmon.c | 20 ++++++++++++++++----
>  1 file changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index be3fb6733b6f..57199ea00a60 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -104,6 +104,10 @@ enum sensor_attr_power {
>  /* Index of memory controller in READ_THERMAL_DATA output */
>  #define TEMP_INDEX_MCTRL	2
>  
> +/* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
> +#define TEMP_MBX_SIGN		BIT(7)
> +#define TEMP_MBX_MAG		GENMASK(6, 0)
> +
>  /* Maximum characters in hwmon label name */
>  #define MAX_LABEL_SIZE		16
>  
> @@ -139,8 +143,8 @@ struct xe_hwmon_thermal_info {
>  	};
>  	/** @count: no of temperature sensors available for the platform */
>  	u8 count;
> -	/** @value: signed value from each sensor */
> -	s8 value[U8_MAX];
> +	/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
> +	u8 value[U8_MAX];
>  	/** @vram_label: vram label names */
>  	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
>  };
> @@ -814,6 +818,14 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	return ret;
>  }
>  
> +/* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
> +static int mbx_temp_decode(u8 value)
> +{
> +	int temp = value & TEMP_MBX_MAG;
> +
> +	return (value & TEMP_MBX_SIGN) ? -temp : temp;
> +}
> +
>  static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> @@ -830,7 +842,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  	}
>  
>  	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
> -		average += hwmon->temp.value[i];
> +		average += mbx_temp_decode(hwmon->temp.value[i]);
>  
>  	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
>  	*val = average * MILLIDEGREE_PER_DEGREE;
> @@ -853,7 +865,7 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
>  		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
>  
>  	data = REG_FIELD_GET(TEMP_MASK, data);
> -	*val = (s8)data * MILLIDEGREE_PER_DEGREE;
> +	*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
>  
>  	return 0;
>  }
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings
  2026-09-24 20:54 ` [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
@ 2026-09-28  0:19   ` Rodrigo Vivi
  2026-09-28 16:08     ` Poosa, Karthik
  2026-09-28 19:38   ` Rodrigo Vivi
  1 sibling, 1 reply; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-28  0:19 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:20AM +0530, Karthik Poosa wrote:
> Add mmio_temp_valid() and mbx_temp_valid() to check whether a temperature
> sensor reading is valid. An MMIO value of 0xFFFFFFFF or a mailbox value of
> 0xFF indicates the sensor is unavailable.
> 
> Gate these checks behind has_mbx_temp_sentinel, enabled on CRI currently.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device_types.h |  2 ++
>  drivers/gpu/drm/xe/xe_hwmon.c        | 16 ++++++++++++++++
>  drivers/gpu/drm/xe/xe_pci.c          |  2 ++
>  drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
>  4 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 4661bfce2f4e..87554605fa41 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -202,6 +202,8 @@ struct xe_device {
>  		 * pcode mailbox commands.
>  		 */
>  		u8 has_mbx_power_limits:1;
> +		/** @info.has_mbx_temp_sentinel: Device has temperature-unavailable sentinels */
> +		u8 has_mbx_temp_sentinel:1;
>  		/** @info.has_mbx_thermal_info: Device supports thermal mailbox commands */
>  		u8 has_mbx_thermal_info:1;
>  		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index c743867a2ebf..8a1dbe708828 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -104,6 +104,9 @@ enum sensor_attr_power {
>  /* Index of memory controller in READ_THERMAL_DATA output */
>  #define TEMP_INDEX_MCTRL	2
>  
> +/* Mailbox sentinel reported for an unavailable temperature sensor */
> +#define TEMP_MBX_INVALID	0xFF
> +
>  /* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
>  #define TEMP_MBX_SIGN		BIT(7)
>  #define TEMP_MBX_MAG		GENMASK(6, 0)
> @@ -822,6 +825,19 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	return ret;
>  }
>  
> +static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
> +{
> +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != U32_MAX
> +						     : value != 0;

_mbx_ seems a wrong prefix now...

And this patch is kind of hard to review alone without its usage...

> +}
> +
> +/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
> +static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
> +{
> +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != TEMP_MBX_INVALID
> +						     : value != 0;
> +}
> +
>  /* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
>  static int mbx_temp_decode(u8 value)
>  {
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index d66d5a0339ae..e656fc012902 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -476,6 +476,7 @@ static const struct xe_device_desc cri_desc = {
>  	.has_gsc_nvm = 1,
>  	.has_i2c = true,
>  	.has_mbx_power_limits = true,
> +	.has_mbx_temp_sentinel = true,
>  	.has_mbx_thermal_info = true,
>  	.has_mert = true,
>  	.has_pre_prod_wa = 1,
> @@ -796,6 +797,7 @@ static int xe_info_init_early(struct xe_device *xe,
>  	/* runtime fusing may force flat_ccs to disabled later */
>  	xe->info.has_flat_ccs = desc->has_flat_ccs;
>  	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
> +	xe->info.has_mbx_temp_sentinel = desc->has_mbx_temp_sentinel;
>  	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
>  	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
>  	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index fed509ff601e..0041ec5676d3 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -50,6 +50,7 @@ struct xe_device_desc {
>  	u8 has_late_bind:1;
>  	u8 has_llc:1;
>  	u8 has_mbx_power_limits:1;
> +	u8 has_mbx_temp_sentinel:1;
>  	u8 has_mbx_thermal_info:1;
>  	u8 has_mert:1;
>  	u8 has_pre_prod_wa:1;
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit
  2026-09-28  0:11   ` Rodrigo Vivi
@ 2026-09-28 15:32     ` Poosa, Karthik
  0 siblings, 0 replies; 36+ messages in thread
From: Poosa, Karthik @ 2026-09-28 15:32 UTC (permalink / raw)
  To: Rodrigo Vivi
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait


On 28-09-2026 05:41, Rodrigo Vivi wrote:
> On Fri, Sep 25, 2026 at 02:24:17AM +0530, Karthik Poosa wrote:
>> Return early when the pcode read operation fails in
>> xe_hwmon_pcode_rmw_power_limit() and check the returned error in
>> callers to avoid updating power limit settings with invalid data.
>>
>> Fixes: 8aa7306631f0 ("drm/xe/hwmon: Fix xe_hwmon_power_max_write")
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>> v2: Address sashiko-bot@kernel.org review comments. Return -EIO instead of
>>      0 on errors in the sysfs store callback to prevent potential userspace
>>      infinite loops.
>>
>>   drivers/gpu/drm/xe/xe_hwmon.c | 18 ++++++++++++------
>>   1 file changed, 12 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 5edeac961ec3..be3fb6733b6f 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -232,9 +232,11 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
>>   						  READ_PSYSGPU_POWER_LIMIT :
>>   						  READ_PACKAGE_POWER_LIMIT,
>>   						  prepare_power_limit_param2(hwmon)), &val0, &val1);
>> -	if (ret)
>> -		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
>> +	if (ret) {
>> +		drm_err(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
>>   			channel, val0, val1, ret);
>> +		return ret;
>> +	}
>>   
>>   	if (attr == PL1_HWMON_ATTR)
>>   		val0 = (val0 & ~clr) | set;
>> @@ -394,7 +396,9 @@ static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channe
>>   		if (hwmon->xe->info.has_mbx_power_limits) {
>>   			drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n",
>>   				PWR_ATTR_TO_STR(attr), channel);
>> -			xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
>> +			ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0);
>> +			if (ret)
>> +				goto unlock;
>>   			xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val);
>>   		} else {
>>   			reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0);
>> @@ -679,11 +683,13 @@ xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *a
>>   
>>   	mutex_lock(&hwmon->hwmon_lock);
>>   
>> -	if (hwmon->xe->info.has_mbx_power_limits)
>> -		xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy);
>> -	else
>> +	if (hwmon->xe->info.has_mbx_power_limits) {
>> +		if (xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy))
>> +			count = -EIO;
> please use ret for this, not changing count...
> and you may set ret = count earlier, or something like that...
ok
>
>> +	} else {
>>   		r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel),
>>   				  PWR_LIM_TIME, rxy);
>> +	}
>>   
>>   	mutex_unlock(&hwmon->hwmon_lock);
>>   
>> -- 
>> 2.25.1
>>

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings
  2026-09-28  0:19   ` Rodrigo Vivi
@ 2026-09-28 16:08     ` Poosa, Karthik
  2026-09-28 17:59       ` Rodrigo Vivi
  0 siblings, 1 reply; 36+ messages in thread
From: Poosa, Karthik @ 2026-09-28 16:08 UTC (permalink / raw)
  To: Rodrigo Vivi
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait


On 28-09-2026 05:49, Rodrigo Vivi wrote:
> On Fri, Sep 25, 2026 at 02:24:20AM +0530, Karthik Poosa wrote:
>> Add mmio_temp_valid() and mbx_temp_valid() to check whether a temperature
>> sensor reading is valid. An MMIO value of 0xFFFFFFFF or a mailbox value of
>> 0xFF indicates the sensor is unavailable.
>>
>> Gate these checks behind has_mbx_temp_sentinel, enabled on CRI currently.
>>
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_device_types.h |  2 ++
>>   drivers/gpu/drm/xe/xe_hwmon.c        | 16 ++++++++++++++++
>>   drivers/gpu/drm/xe/xe_pci.c          |  2 ++
>>   drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
>>   4 files changed, 21 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index 4661bfce2f4e..87554605fa41 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -202,6 +202,8 @@ struct xe_device {
>>   		 * pcode mailbox commands.
>>   		 */
>>   		u8 has_mbx_power_limits:1;
>> +		/** @info.has_mbx_temp_sentinel: Device has temperature-unavailable sentinels */
>> +		u8 has_mbx_temp_sentinel:1;
>>   		/** @info.has_mbx_thermal_info: Device supports thermal mailbox commands */
>>   		u8 has_mbx_thermal_info:1;
>>   		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index c743867a2ebf..8a1dbe708828 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -104,6 +104,9 @@ enum sensor_attr_power {
>>   /* Index of memory controller in READ_THERMAL_DATA output */
>>   #define TEMP_INDEX_MCTRL	2
>>   
>> +/* Mailbox sentinel reported for an unavailable temperature sensor */
>> +#define TEMP_MBX_INVALID	0xFF
>> +
>>   /* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
>>   #define TEMP_MBX_SIGN		BIT(7)
>>   #define TEMP_MBX_MAG		GENMASK(6, 0)
>> @@ -822,6 +825,19 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>   	return ret;
>>   }
>>   
>> +static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
>> +{
>> +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != U32_MAX
>> +						     : value != 0;
> _mbx_ seems a wrong prefix now...
you are right, I can rename to .has_temp_sentinel
>
> And this patch is kind of hard to review alone without its usage...

shall merge this patch with the next 3 patches then ?

[PATCH v6 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors

[PATCH v6 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors

[PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor 
availability checks

>
>> +}
>> +
>> +/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
>> +static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
>> +{
>> +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != TEMP_MBX_INVALID
>> +						     : value != 0;
>> +}
>> +
>>   /* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
>>   static int mbx_temp_decode(u8 value)
>>   {
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index d66d5a0339ae..e656fc012902 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -476,6 +476,7 @@ static const struct xe_device_desc cri_desc = {
>>   	.has_gsc_nvm = 1,
>>   	.has_i2c = true,
>>   	.has_mbx_power_limits = true,
>> +	.has_mbx_temp_sentinel = true,
>>   	.has_mbx_thermal_info = true,
>>   	.has_mert = true,
>>   	.has_pre_prod_wa = 1,
>> @@ -796,6 +797,7 @@ static int xe_info_init_early(struct xe_device *xe,
>>   	/* runtime fusing may force flat_ccs to disabled later */
>>   	xe->info.has_flat_ccs = desc->has_flat_ccs;
>>   	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
>> +	xe->info.has_mbx_temp_sentinel = desc->has_mbx_temp_sentinel;
>>   	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
>>   	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
>>   	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
>> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>> index fed509ff601e..0041ec5676d3 100644
>> --- a/drivers/gpu/drm/xe/xe_pci_types.h
>> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
>> @@ -50,6 +50,7 @@ struct xe_device_desc {
>>   	u8 has_late_bind:1;
>>   	u8 has_llc:1;
>>   	u8 has_mbx_power_limits:1;
>> +	u8 has_mbx_temp_sentinel:1;
>>   	u8 has_mbx_thermal_info:1;
>>   	u8 has_mert:1;
>>   	u8 has_pre_prod_wa:1;
>> -- 
>> 2.25.1
>>

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors
  2026-09-24 20:54 ` [PATCH v6 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors Karthik Poosa
@ 2026-09-28 16:08   ` Rodrigo Vivi
  0 siblings, 0 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-28 16:08 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:21AM +0530, Karthik Poosa wrote:
> Skip memory controller sensors that report invalid readings when
> computing the average temperature in get_mc_temp(). Return -ENXIO when
> no valid sensor data is available, and allow the helper to be used as
> an availability probe by making the output parameter optional.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> Fixes: 3a0cb885e111 ("drm/xe/hwmon: Expose memory controller temperature")

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_hwmon.c | 20 ++++++++++++++++----
>  1 file changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 8a1dbe708828..83466b8d8d27 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -849,8 +849,8 @@ static int mbx_temp_decode(u8 value)
>  static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> +	int ret, i, count = 0;
>  	s32 average = 0;
> -	int ret, i;
>  
>  	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
>  		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
> @@ -861,11 +861,23 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  			hwmon->temp.dword[i]);
>  	}
>  
> -	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++)
> +	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
> +		if (!mbx_temp_valid(hwmon, hwmon->temp.value[i]))
> +			continue;
>  		average += mbx_temp_decode(hwmon->temp.value[i]);
> +		count++;
> +	}
> +
> +	if (!count) {
> +		drm_dbg(&hwmon->xe->drm, "Memory controller temperature unavailable!\n");
> +		return -ENXIO;
> +	}
> +
> +	average /= count;
> +
> +	if (val)
> +		*val = average * MILLIDEGREE_PER_DEGREE;
>  
> -	average /= (hwmon->temp.count - TEMP_INDEX_MCTRL - 1);
> -	*val = average * MILLIDEGREE_PER_DEGREE;
>  	return 0;
>  }
>  
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors
  2026-09-24 20:54 ` [PATCH v6 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors Karthik Poosa
@ 2026-09-28 16:10   ` Rodrigo Vivi
  0 siblings, 0 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-28 16:10 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:22AM +0530, Karthik Poosa wrote:
> Return -ENXIO from get_pcie_temp() when the mailbox reports an invalid
> reading, so the PCIe sensor can be treated as unavailable. Guard the val
> store so the function can be used purely as an availability probe. No
> sysfs visibility changes.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_hwmon.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 83466b8d8d27..4a7cf913e6c8 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -897,7 +897,13 @@ static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
>  		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
>  
>  	data = REG_FIELD_GET(TEMP_MASK, data);
> -	*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
> +	if (!mbx_temp_valid(hwmon, data)) {
> +		drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n");
> +		return -ENXIO;
> +	}
> +
> +	if (val)
> +		*val = mbx_temp_decode(data) * MILLIDEGREE_PER_DEGREE;
>  
>  	return 0;
>  }
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings
  2026-09-28 16:08     ` Poosa, Karthik
@ 2026-09-28 17:59       ` Rodrigo Vivi
  0 siblings, 0 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-28 17:59 UTC (permalink / raw)
  To: Poosa, Karthik
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Mon, Sep 28, 2026 at 09:38:06PM +0530, Poosa, Karthik wrote:
> 
> On 28-09-2026 05:49, Rodrigo Vivi wrote:
> > On Fri, Sep 25, 2026 at 02:24:20AM +0530, Karthik Poosa wrote:
> > > Add mmio_temp_valid() and mbx_temp_valid() to check whether a temperature
> > > sensor reading is valid. An MMIO value of 0xFFFFFFFF or a mailbox value of
> > > 0xFF indicates the sensor is unavailable.
> > > 
> > > Gate these checks behind has_mbx_temp_sentinel, enabled on CRI currently.
> > > 
> > > Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> > > ---
> > >   drivers/gpu/drm/xe/xe_device_types.h |  2 ++
> > >   drivers/gpu/drm/xe/xe_hwmon.c        | 16 ++++++++++++++++
> > >   drivers/gpu/drm/xe/xe_pci.c          |  2 ++
> > >   drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
> > >   4 files changed, 21 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> > > index 4661bfce2f4e..87554605fa41 100644
> > > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > > @@ -202,6 +202,8 @@ struct xe_device {
> > >   		 * pcode mailbox commands.
> > >   		 */
> > >   		u8 has_mbx_power_limits:1;
> > > +		/** @info.has_mbx_temp_sentinel: Device has temperature-unavailable sentinels */
> > > +		u8 has_mbx_temp_sentinel:1;
> > >   		/** @info.has_mbx_thermal_info: Device supports thermal mailbox commands */
> > >   		u8 has_mbx_thermal_info:1;
> > >   		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
> > > diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> > > index c743867a2ebf..8a1dbe708828 100644
> > > --- a/drivers/gpu/drm/xe/xe_hwmon.c
> > > +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> > > @@ -104,6 +104,9 @@ enum sensor_attr_power {
> > >   /* Index of memory controller in READ_THERMAL_DATA output */
> > >   #define TEMP_INDEX_MCTRL	2
> > > +/* Mailbox sentinel reported for an unavailable temperature sensor */
> > > +#define TEMP_MBX_INVALID	0xFF
> > > +
> > >   /* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
> > >   #define TEMP_MBX_SIGN		BIT(7)
> > >   #define TEMP_MBX_MAG		GENMASK(6, 0)
> > > @@ -822,6 +825,19 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
> > >   	return ret;
> > >   }
> > > +static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
> > > +{
> > > +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != U32_MAX
> > > +						     : value != 0;
> > _mbx_ seems a wrong prefix now...
> you are right, I can rename to .has_temp_sentinel
> > 
> > And this patch is kind of hard to review alone without its usage...
> 
> shall merge this patch with the next 3 patches then ?

nah, just rename it and feel free to use:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

since I ended up already checking the usages anyway ;)

> 
> [PATCH v6 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors
> 
> [PATCH v6 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors
> 
> [PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor availability
> checks
> 
> > 
> > > +}
> > > +
> > > +/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
> > > +static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
> > > +{
> > > +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != TEMP_MBX_INVALID
> > > +						     : value != 0;
> > > +}
> > > +
> > >   /* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
> > >   static int mbx_temp_decode(u8 value)
> > >   {
> > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > index d66d5a0339ae..e656fc012902 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > @@ -476,6 +476,7 @@ static const struct xe_device_desc cri_desc = {
> > >   	.has_gsc_nvm = 1,
> > >   	.has_i2c = true,
> > >   	.has_mbx_power_limits = true,
> > > +	.has_mbx_temp_sentinel = true,
> > >   	.has_mbx_thermal_info = true,
> > >   	.has_mert = true,
> > >   	.has_pre_prod_wa = 1,
> > > @@ -796,6 +797,7 @@ static int xe_info_init_early(struct xe_device *xe,
> > >   	/* runtime fusing may force flat_ccs to disabled later */
> > >   	xe->info.has_flat_ccs = desc->has_flat_ccs;
> > >   	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
> > > +	xe->info.has_mbx_temp_sentinel = desc->has_mbx_temp_sentinel;
> > >   	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
> > >   	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
> > >   	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
> > > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> > > index fed509ff601e..0041ec5676d3 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > > @@ -50,6 +50,7 @@ struct xe_device_desc {
> > >   	u8 has_late_bind:1;
> > >   	u8 has_llc:1;
> > >   	u8 has_mbx_power_limits:1;
> > > +	u8 has_mbx_temp_sentinel:1;
> > >   	u8 has_mbx_thermal_info:1;
> > >   	u8 has_mert:1;
> > >   	u8 has_pre_prod_wa:1;
> > > -- 
> > > 2.25.1
> > > 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings
  2026-09-24 20:54 ` [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
  2026-09-28  0:19   ` Rodrigo Vivi
@ 2026-09-28 19:38   ` Rodrigo Vivi
  2026-09-29 16:48     ` Poosa, Karthik
  1 sibling, 1 reply; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-28 19:38 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:20AM +0530, Karthik Poosa wrote:
> Add mmio_temp_valid() and mbx_temp_valid() to check whether a temperature
> sensor reading is valid. An MMIO value of 0xFFFFFFFF or a mailbox value of
> 0xFF indicates the sensor is unavailable.
> 
> Gate these checks behind has_mbx_temp_sentinel, enabled on CRI currently.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device_types.h |  2 ++
>  drivers/gpu/drm/xe/xe_hwmon.c        | 16 ++++++++++++++++
>  drivers/gpu/drm/xe/xe_pci.c          |  2 ++
>  drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
>  4 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 4661bfce2f4e..87554605fa41 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -202,6 +202,8 @@ struct xe_device {
>  		 * pcode mailbox commands.
>  		 */
>  		u8 has_mbx_power_limits:1;
> +		/** @info.has_mbx_temp_sentinel: Device has temperature-unavailable sentinels */
> +		u8 has_mbx_temp_sentinel:1;
>  		/** @info.has_mbx_thermal_info: Device supports thermal mailbox commands */
>  		u8 has_mbx_thermal_info:1;
>  		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index c743867a2ebf..8a1dbe708828 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -104,6 +104,9 @@ enum sensor_attr_power {
>  /* Index of memory controller in READ_THERMAL_DATA output */
>  #define TEMP_INDEX_MCTRL	2
>  
> +/* Mailbox sentinel reported for an unavailable temperature sensor */
> +#define TEMP_MBX_INVALID	0xFF
> +
>  /* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
>  #define TEMP_MBX_SIGN		BIT(7)
>  #define TEMP_MBX_MAG		GENMASK(6, 0)
> @@ -822,6 +825,19 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  	return ret;
>  }
>  
> +static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
> +{
> +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != U32_MAX
> +						     : value != 0;
> +}
> +
> +/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
> +static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
> +{
> +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != TEMP_MBX_INVALID
> +						     : value != 0;
> +}

When reviewing the patch 7, I noticed a small change that took me back to the
temp valid...

What if temperature is 0 ?!
Why isn't it valid?

> +
>  /* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
>  static int mbx_temp_decode(u8 value)
>  {
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index d66d5a0339ae..e656fc012902 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -476,6 +476,7 @@ static const struct xe_device_desc cri_desc = {
>  	.has_gsc_nvm = 1,
>  	.has_i2c = true,
>  	.has_mbx_power_limits = true,
> +	.has_mbx_temp_sentinel = true,
>  	.has_mbx_thermal_info = true,
>  	.has_mert = true,
>  	.has_pre_prod_wa = 1,
> @@ -796,6 +797,7 @@ static int xe_info_init_early(struct xe_device *xe,
>  	/* runtime fusing may force flat_ccs to disabled later */
>  	xe->info.has_flat_ccs = desc->has_flat_ccs;
>  	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
> +	xe->info.has_mbx_temp_sentinel = desc->has_mbx_temp_sentinel;
>  	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
>  	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
>  	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index fed509ff601e..0041ec5676d3 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -50,6 +50,7 @@ struct xe_device_desc {
>  	u8 has_late_bind:1;
>  	u8 has_llc:1;
>  	u8 has_mbx_power_limits:1;
> +	u8 has_mbx_temp_sentinel:1;
>  	u8 has_mbx_thermal_info:1;
>  	u8 has_mert:1;
>  	u8 has_pre_prod_wa:1;
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks
  2026-09-24 20:54 ` [PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks Karthik Poosa
@ 2026-09-28 19:39   ` Rodrigo Vivi
  0 siblings, 0 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-28 19:39 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:23AM +0530, Karthik Poosa wrote:
> Replace is_vram_ch_available() with a generalized is_temp_available()
> that validates PKG, VRAM, per-channel VRAM, memory controller and PCIe
> sensors using the new validity helpers. Rename the existing callers to
> the new helper.
> 
> Use is_temp_available() from xe_hwmon_temp_is_visible() so attributes for
> sensors that are not present are not exposed during hwmon registration.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> Assisted-by: LLM
> ---
>  drivers/gpu/drm/xe/xe_hwmon.c | 64 ++++++++++++++++++++++-------------
>  1 file changed, 40 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 4a7cf913e6c8..052b25a233d6 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -1002,19 +1002,39 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
>  	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
>  }
>  
> -static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel)
> +static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
>  {
>  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> -	int vram_id = channel - CHANNEL_VRAM_N;
> -	struct xe_reg vram_reg;
> +	struct xe_reg reg;
> +	u32 reg_val;
>  
> -	vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> -	if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg))
> -		return false;
> +	switch (channel) {
> +	case CHANNEL_PKG:
> +	case CHANNEL_VRAM:
> +	case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> +		reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel);
> +		if (!xe_reg_is_valid(reg))
> +			return false;
> +
> +		reg_val = xe_mmio_read32(mmio, reg);
> +		if (!mmio_temp_valid(hwmon, reg_val)) {
> +			drm_dbg(&hwmon->xe->drm,
> +				"channel %d temperature unavailable, val 0x%x\n", channel, reg_val);
> +			return false;
> +		}
> +
> +		if (channel >= CHANNEL_VRAM_N)
> +			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
> +				"vram_ch_%d", channel - CHANNEL_VRAM_N);
>  
> -	/* Create label only for available vram channel */
> -	sprintf(hwmon->temp.vram_label[vram_id], "vram_ch_%d", vram_id);
> -	return true;
> +		return true;
> +	case CHANNEL_MCTRL:
> +		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
> +	case CHANNEL_PCIE:
> +		return hwmon->temp.count && !get_pcie_temp(hwmon, NULL);
> +	default:
> +		return false;
> +	}
>  }
>  
>  static umode_t
> @@ -1024,14 +1044,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  	case hwmon_temp_emergency:
>  		switch (channel) {
>  		case CHANNEL_PKG:
> -			return hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN] ? 0444 : 0;
> -		case CHANNEL_VRAM:
> -			return hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN] ? 0444 : 0;
>  		case CHANNEL_MCTRL:
>  		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return (is_temp_available(hwmon, channel) &&
> +				hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN]) ? 0444 : 0;
> +		case CHANNEL_VRAM:
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> -			return (is_vram_ch_available(hwmon, channel) &&
> +			return (is_temp_available(hwmon, channel) &&
>  				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
>  		default:
>  			return 0;
> @@ -1039,14 +1058,13 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  	case hwmon_temp_crit:
>  		switch (channel) {
>  		case CHANNEL_PKG:
> -			return hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT] ? 0444 : 0;
> -		case CHANNEL_VRAM:
> -			return hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT] ? 0444 : 0;
>  		case CHANNEL_MCTRL:
>  		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
> +			return (is_temp_available(hwmon, channel) &&
> +				hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT]) ? 0444 : 0;
> +		case CHANNEL_VRAM:
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> -			return (is_vram_ch_available(hwmon, channel) &&
> +			return (is_temp_available(hwmon, channel) &&
>  				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
>  		default:
>  			return 0;
> @@ -1054,7 +1072,8 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  	case hwmon_temp_max:
>  		switch (channel) {
>  		case CHANNEL_PKG:
> -			return hwmon->temp.limit[TEMP_LIMIT_PKG_MAX] ? 0444 : 0;
> +			return (is_temp_available(hwmon, channel) &&
> +				hwmon->temp.limit[TEMP_LIMIT_PKG_MAX]) ? 0444 : 0;
>  		default:
>  			return 0;
>  		}
> @@ -1063,13 +1082,10 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  		switch (channel) {
>  		case CHANNEL_PKG:
>  		case CHANNEL_VRAM:
> -			return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP,
> -								channel)) ? 0444 : 0;
>  		case CHANNEL_MCTRL:
>  		case CHANNEL_PCIE:
> -			return hwmon->temp.count ? 0444 : 0;
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> -			return is_vram_ch_available(hwmon, channel) ? 0444 : 0;
> +			return is_temp_available(hwmon, channel) ? 0444 : 0;

now, if temp = 0 at probe, then it won't appear. What made me to question
patch 4 again...

But other then this, this patch looks correct:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  		default:
>  			return 0;
>  		}
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time
  2026-09-24 20:54 ` [PATCH v6 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time Karthik Poosa
@ 2026-09-28 21:17   ` Rodrigo Vivi
  0 siblings, 0 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-28 21:17 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:24AM +0530, Karthik Poosa wrote:
> Avoid probing temperature sensor availability from the hwmon is_visible()
> callback. For MCTRL and PCIe channels, that path can trigger repeated
> blocking mailbox reads while sysfs attributes are being created, increasing
> probe time and making attribute creation sensitive to transient failures.
> 
> Probe temperature availability once during preregistration and cache the
> result for subsequent visibility checks.

fine to cache, perhaps wroth checking that 0 temp case..

but this patch itself looks good:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> Assisted-by: LLM
> ---
>  drivers/gpu/drm/xe/xe_hwmon.c | 39 +++++++++++++++++++++++------------
>  1 file changed, 26 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 052b25a233d6..92280248f1e9 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -146,6 +146,8 @@ struct xe_hwmon_thermal_info {
>  	};
>  	/** @count: no of temperature sensors available for the platform */
>  	u8 count;
> +	/** @available: temperature sensor availability cached at registration */
> +	bool available[CHANNEL_MAX];
>  	union {
>  		/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
>  		u8 value[U8_MAX + 1];
> @@ -1002,7 +1004,7 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu
>  	*value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
>  }
>  
> -static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
> +static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
>  {
>  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>  	struct xe_reg reg;
> @@ -1023,10 +1025,6 @@ static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
>  			return false;
>  		}
>  
> -		if (channel >= CHANNEL_VRAM_N)
> -			sprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N],
> -				"vram_ch_%d", channel - CHANNEL_VRAM_N);
> -
>  		return true;
>  	case CHANNEL_MCTRL:
>  		return hwmon->temp.count && !get_mc_temp(hwmon, NULL);
> @@ -1037,6 +1035,22 @@ static bool is_temp_available(struct xe_hwmon *hwmon, int channel)
>  	}
>  }
>  
> +static void xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
> +{
> +	int channel;
> +
> +	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
> +		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
> +
> +	for (channel = 0; channel < CHANNEL_MAX; channel++) {
> +		hwmon->temp.available[channel] = xe_hwmon_temp_probe(hwmon, channel);
> +		if (hwmon->temp.available[channel] &&
> +		    in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> +			snprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N], MAX_LABEL_SIZE,
> +				 "vram_ch_%d", channel - CHANNEL_VRAM_N);
> +	}
> +}
> +
>  static umode_t
>  xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  {
> @@ -1046,11 +1060,11 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  		case CHANNEL_PKG:
>  		case CHANNEL_MCTRL:
>  		case CHANNEL_PCIE:
> -			return (is_temp_available(hwmon, channel) &&
> +			return (hwmon->temp.available[channel] &&
>  				hwmon->temp.limit[TEMP_LIMIT_PKG_SHUTDOWN]) ? 0444 : 0;
>  		case CHANNEL_VRAM:
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> -			return (is_temp_available(hwmon, channel) &&
> +			return (hwmon->temp.available[channel] &&
>  				hwmon->temp.limit[TEMP_LIMIT_MEM_SHUTDOWN]) ? 0444 : 0;
>  		default:
>  			return 0;
> @@ -1060,11 +1074,11 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  		case CHANNEL_PKG:
>  		case CHANNEL_MCTRL:
>  		case CHANNEL_PCIE:
> -			return (is_temp_available(hwmon, channel) &&
> +			return (hwmon->temp.available[channel] &&
>  				hwmon->temp.limit[TEMP_LIMIT_PKG_CRIT]) ? 0444 : 0;
>  		case CHANNEL_VRAM:
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> -			return (is_temp_available(hwmon, channel) &&
> +			return (hwmon->temp.available[channel] &&
>  				hwmon->temp.limit[TEMP_LIMIT_MEM_CRIT]) ? 0444 : 0;
>  		default:
>  			return 0;
> @@ -1072,7 +1086,7 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  	case hwmon_temp_max:
>  		switch (channel) {
>  		case CHANNEL_PKG:
> -			return (is_temp_available(hwmon, channel) &&
> +			return (hwmon->temp.available[channel] &&
>  				hwmon->temp.limit[TEMP_LIMIT_PKG_MAX]) ? 0444 : 0;
>  		default:
>  			return 0;
> @@ -1085,7 +1099,7 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  		case CHANNEL_MCTRL:
>  		case CHANNEL_PCIE:
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
> -			return is_temp_available(hwmon, channel) ? 0444 : 0;
> +			return hwmon->temp.available[channel] ? 0444 : 0;
>  		default:
>  			return 0;
>  		}
> @@ -1627,8 +1641,7 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
>  		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
>  			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
>  
> -	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
> -		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
> +	xe_hwmon_init_temp_info(hwmon);
>  }
>  
>  int xe_hwmon_register(struct xe_device *xe)
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings
  2026-09-28 19:38   ` Rodrigo Vivi
@ 2026-09-29 16:48     ` Poosa, Karthik
  2026-09-29 18:26       ` Rodrigo Vivi
  0 siblings, 1 reply; 36+ messages in thread
From: Poosa, Karthik @ 2026-09-29 16:48 UTC (permalink / raw)
  To: Rodrigo Vivi
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait


On 29-09-2026 01:08, Rodrigo Vivi wrote:
> On Fri, Sep 25, 2026 at 02:24:20AM +0530, Karthik Poosa wrote:
>> Add mmio_temp_valid() and mbx_temp_valid() to check whether a temperature
>> sensor reading is valid. An MMIO value of 0xFFFFFFFF or a mailbox value of
>> 0xFF indicates the sensor is unavailable.
>>
>> Gate these checks behind has_mbx_temp_sentinel, enabled on CRI currently.
>>
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_device_types.h |  2 ++
>>   drivers/gpu/drm/xe/xe_hwmon.c        | 16 ++++++++++++++++
>>   drivers/gpu/drm/xe/xe_pci.c          |  2 ++
>>   drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
>>   4 files changed, 21 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index 4661bfce2f4e..87554605fa41 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -202,6 +202,8 @@ struct xe_device {
>>   		 * pcode mailbox commands.
>>   		 */
>>   		u8 has_mbx_power_limits:1;
>> +		/** @info.has_mbx_temp_sentinel: Device has temperature-unavailable sentinels */
>> +		u8 has_mbx_temp_sentinel:1;
>>   		/** @info.has_mbx_thermal_info: Device supports thermal mailbox commands */
>>   		u8 has_mbx_thermal_info:1;
>>   		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index c743867a2ebf..8a1dbe708828 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -104,6 +104,9 @@ enum sensor_attr_power {
>>   /* Index of memory controller in READ_THERMAL_DATA output */
>>   #define TEMP_INDEX_MCTRL	2
>>   
>> +/* Mailbox sentinel reported for an unavailable temperature sensor */
>> +#define TEMP_MBX_INVALID	0xFF
>> +
>>   /* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
>>   #define TEMP_MBX_SIGN		BIT(7)
>>   #define TEMP_MBX_MAG		GENMASK(6, 0)
>> @@ -822,6 +825,19 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>   	return ret;
>>   }
>>   
>> +static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
>> +{
>> +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != U32_MAX
>> +						     : value != 0;
>> +}
>> +
>> +/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
>> +static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
>> +{
>> +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != TEMP_MBX_INVALID
>> +						     : value != 0;
>> +}
> When reviewing the patch 7, I noticed a small change that took me back to the
> temp valid...
>
> What if temperature is 0 ?!
> Why isn't it valid?
This can happen on pre-CRI platforms (.has_mbx_temp_sentinel!=true), 
where temperature sentinel is not supported.
In that case, we shall return true here on those platforms.
>
>> +
>>   /* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
>>   static int mbx_temp_decode(u8 value)
>>   {
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index d66d5a0339ae..e656fc012902 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -476,6 +476,7 @@ static const struct xe_device_desc cri_desc = {
>>   	.has_gsc_nvm = 1,
>>   	.has_i2c = true,
>>   	.has_mbx_power_limits = true,
>> +	.has_mbx_temp_sentinel = true,
>>   	.has_mbx_thermal_info = true,
>>   	.has_mert = true,
>>   	.has_pre_prod_wa = 1,
>> @@ -796,6 +797,7 @@ static int xe_info_init_early(struct xe_device *xe,
>>   	/* runtime fusing may force flat_ccs to disabled later */
>>   	xe->info.has_flat_ccs = desc->has_flat_ccs;
>>   	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
>> +	xe->info.has_mbx_temp_sentinel = desc->has_mbx_temp_sentinel;
>>   	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
>>   	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
>>   	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
>> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>> index fed509ff601e..0041ec5676d3 100644
>> --- a/drivers/gpu/drm/xe/xe_pci_types.h
>> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
>> @@ -50,6 +50,7 @@ struct xe_device_desc {
>>   	u8 has_late_bind:1;
>>   	u8 has_llc:1;
>>   	u8 has_mbx_power_limits:1;
>> +	u8 has_mbx_temp_sentinel:1;
>>   	u8 has_mbx_thermal_info:1;
>>   	u8 has_mert:1;
>>   	u8 has_pre_prod_wa:1;
>> -- 
>> 2.25.1
>>

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 10/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support
  2026-09-24 20:54 ` [PATCH v6 10/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support Karthik Poosa
@ 2026-09-29 18:04   ` Rodrigo Vivi
  2026-10-01 19:02     ` Poosa, Karthik
  0 siblings, 1 reply; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-29 18:04 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:26AM +0530, Karthik Poosa wrote:
> On CRI, derive the number of available VRAM temperature channels from the
> CRI_MSU_VRAM_ENABLE register, where each enabled MSU contributes
> VRAM_CHANNELS_PER_MSU channels.
>  
> Increase the maximum supported VRAM channel count to 80 and use the
> derived count to control VRAM sensor enumeration, channel access, and
> VRAM label allocation. Add a has_fixed_vram_channels platform flag to
> preserve the existing fixed-channel behavior on non-CRI platforms.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
> 
> v2:
>  - Use the highest enabled MSU index to determine the VRAM channel bound
>    instead of counting enabled MSUs. A sparse mask could expose channels
>    beyond the allocated label array, leaving the label pointer unset and
>    potentially hanging during sysfs reads.
>  - Also return an error when no temperature label matches the requested
>    channel.
> 
>  drivers/gpu/drm/xe/regs/xe_pcode_regs.h |   1 +
>  drivers/gpu/drm/xe/xe_device_types.h    |   2 +
>  drivers/gpu/drm/xe/xe_hwmon.c           | 164 +++++++++++++++++++++---
>  drivers/gpu/drm/xe/xe_pci.c             |   2 +
>  drivers/gpu/drm/xe/xe_pci_types.h       |   1 +
>  5 files changed, 154 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
> index a969661f0c95..d9e4847dd68e 100644
> --- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
> @@ -28,6 +28,7 @@
>  #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
>  
>  #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
> +#define CRI_MSU_VRAM_ENABLE			XE_REG(0x138340)

can you please share again the ref to this?

>  #define CRI_PACKAGE_TEMPERATURE			XE_REG(0x138344)
>  #define CRI_VRAM_TEMPERATURE			XE_REG(0x138348)
>  #define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 87554605fa41..8a1ca65f5665 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -184,6 +184,8 @@ struct xe_device {
>  		u8 has_drm_ras:1;
>  		/** @info.has_fan_control: Device supports fan control */
>  		u8 has_fan_control:1;
> +		/** @info.has_fixed_vram_channels: Device has fixed VRAM temperature channels */
> +		u8 has_fixed_vram_channels:1;
>  		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
>  		u8 has_flat_ccs:1;
>  		/** @info.has_gsc_nvm: Device has gsc non-volatile memory */
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 1b2e2fbe43c8..0422db647d11 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -39,7 +39,11 @@ enum xe_hwmon_reg_operation {
>  	REG_READ64,
>  };
>  
> -#define MAX_VRAM_CHANNELS      (16)
> +#define MAX_VRAM_CHANNELS	80
> +#define FIXED_VRAM_CHANNELS	16
> +
> +/* Each MSU enable bit maps to one VRAM subsystem of 4 channels. */
> +#define VRAM_CHANNELS_PER_MSU	4
>  
>  enum xe_hwmon_channel {
>  	CHANNEL_CARD,
> @@ -48,6 +52,7 @@ enum xe_hwmon_channel {
>  	CHANNEL_MCTRL,
>  	CHANNEL_PCIE,
>  	CHANNEL_VRAM_N,
> +	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
>  	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
>  	CHANNEL_MAX,
>  };
> @@ -144,18 +149,22 @@ struct xe_hwmon_thermal_info {
>  		/** @data: temperature limits in dwords */
>  		u32 data[DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32))];
>  	};
> -	/** @count: no of temperature sensors available for the platform */
> +	/** @count: temperature sensors count from READ_THERMAL_CONFIG */
>  	u8 count;
> +	/** @vram_count: exclusive upper bound for VRAM temperature channel indices */
> +	u8 vram_count;
>  	/** @available: temperature sensor availability cached at registration */
>  	bool available[CHANNEL_MAX];
> +	/** @msu_mask: VRAM subsystem enable mask read from MMIO */
> +	u32 msu_mask;
>  	union {
>  		/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
>  		u8 value[U8_MAX + 1];
>  		/** @dword: sensor values as dwords, u32-aligned for pcode reads */
>  		u32 dword[DIV_ROUND_UP(U8_MAX + 1, sizeof(u32))];
>  	};
> -	/** @vram_label: vram label names */
> -	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
> +	/** @vram_label: vram label names, dynamically allocated based on vram_count */
> +	char (*vram_label)[MAX_LABEL_SIZE];
>  };
>  
>  /**
> @@ -269,6 +278,14 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
>  	return ret;
>  }
>  
> +static bool xe_hwmon_vram_channel_enabled(const struct xe_hwmon *hwmon, int index)
> +{
> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
> +		return hwmon->temp.msu_mask & BIT(index / VRAM_CHANNELS_PER_MSU);
> +
> +	return true;
> +}
> +
>  static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
>  				      int channel)
>  {
> @@ -281,14 +298,16 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
>  				return CRI_PACKAGE_TEMPERATURE;
>  			else if (channel == CHANNEL_VRAM)
>  				return CRI_VRAM_TEMPERATURE;
> -			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> +			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
> +				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
>  				return CRI_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
>  		} else if (xe->info.platform == XE_BATTLEMAGE) {
>  			if (channel == CHANNEL_PKG)
>  				return BMG_PACKAGE_TEMPERATURE;
>  			else if (channel == CHANNEL_VRAM)
>  				return BMG_VRAM_TEMPERATURE;
> -			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> +			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
> +				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
>  				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
>  		} else if (xe->info.platform == XE_DG2) {
>  			if (channel == CHANNEL_PKG)
> @@ -798,6 +817,70 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>  			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>  			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>  			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,

I was wondering if there was something better we could get here...
and LLM suggested me a reduction from 80 to 8 lines:

#define TEMP_CFG_CARD HWMON_T_LABEL
#define TEMP_CFG_PKG  (HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | \
                       HWMON_T_LABEL | HWMON_T_MAX)
#define TEMP_CFG_SENSOR       (HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL)

/*
 * Indexed by &enum xe_hwmon_channel and zero-terminated; hwmon derives the
 * channel count from the array contents. Sizing on CHANNEL_MAX keeps this in
 * lockstep with the enum.
 */
static const u32 hwmon_temp_config[CHANNEL_MAX + 1] = {
      [CHANNEL_CARD]                          = TEMP_CFG_CARD,
      [CHANNEL_PKG]                           = TEMP_CFG_PKG,
      [CHANNEL_VRAM]                          = TEMP_CFG_SENSOR,
      [CHANNEL_MCTRL]                         = TEMP_CFG_SENSOR,
      [CHANNEL_PCIE]                          = TEMP_CFG_SENSOR,
      [CHANNEL_VRAM_N ... CHANNEL_VRAM_N_MAX] = TEMP_CFG_SENSOR,
      [CHANNEL_MAX]                           = 0,    /* terminator */
};

static const struct hwmon_channel_info hwmon_temp_info = {
      .type = hwmon_temp,
      .config = hwmon_temp_config,
};

static const struct hwmon_channel_info * const hwmon_info[] = {
      &hwmon_temp_info,
      HWMON_CHANNEL_INFO(power, ...),
      /* unchanged */
};

can be done in a follow up though...

Everything else looks sane... I just need to double check the regs again...

>  			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL),
>  	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>  			   HWMON_P_CAP,
> @@ -812,15 +895,37 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>  static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> +	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>  	u32 config = 0;
>  	int ret;
>  
> +	/*
> +	 * Only CRI reports dynamic VRAM channel state. Fixed-channel platforms
> +	 * set the count up front so those sensors stay visible even if the thermal
> +	 * mailbox reads below fail.
> +	 */
> +	if (hwmon->xe->info.has_fixed_vram_channels)
> +		hwmon->temp.vram_count = FIXED_VRAM_CHANNELS;
> +
> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND) {
> +		hwmon->temp.msu_mask = xe_mmio_read32(mmio, CRI_MSU_VRAM_ENABLE);
> +		hwmon->temp.vram_count = fls(hwmon->temp.msu_mask) * VRAM_CHANNELS_PER_MSU;
> +		drm_dbg(&hwmon->xe->drm, "MSU VRAM enable mask 0x%x, VRAM channel bound %d\n",
> +			hwmon->temp.msu_mask, hwmon->temp.vram_count);
> +		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS) {
> +			drm_warn(&hwmon->xe->drm,
> +				 "VRAM channel bound %d exceeds max %d, clamping\n",
> +				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
> +			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
> +		}
> +	}
> +
>  	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
>  			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
>  	if (ret)
>  		return ret;
>  
> -	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%x val1 0x%x\n",
> +	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%08x val1 0x%08x\n",
>  		hwmon->temp.data[0], hwmon->temp.data[1]);
>  
>  	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0),
> @@ -1025,6 +1130,14 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
>  		if (!xe_reg_is_valid(reg))
>  			return false;
>  
> +		/*
> +		 * On CRI, VRAM channel presence comes from the MSU enable mask
> +		 * (applied in xe_hwmon_get_reg()); the temperature register's
> +		 * 0xffffffff sentinel is not reliable for VRAM channels.
> +		 */
> +		if (hwmon->xe->info.platform == XE_CRESCENTISLAND && channel >= CHANNEL_VRAM_N)
> +			return true;
> +
>  		reg_val = xe_mmio_read32(mmio, reg);
>  		if (!mmio_temp_valid(hwmon, reg_val)) {
>  			drm_dbg(&hwmon->xe->drm,
> @@ -1042,20 +1155,31 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
>  	}
>  }
>  
> -static void xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
> +static int xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
>  {
> +	struct device *dev = hwmon->xe->drm.dev;
>  	int channel;
>  
>  	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
>  		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
>  
> +	/* vram_count is known only after reading thermal info above. */
> +	if (hwmon->temp.vram_count) {
> +		hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
> +						      MAX_LABEL_SIZE, GFP_KERNEL);
> +		if (!hwmon->temp.vram_label)
> +			return -ENOMEM;
> +	}
> +
>  	for (channel = 0; channel < CHANNEL_MAX; channel++) {
>  		hwmon->temp.available[channel] = xe_hwmon_temp_probe(hwmon, channel);
> -		if (hwmon->temp.available[channel] &&
> -		    in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> +		if (hwmon->temp.available[channel] && hwmon->temp.vram_label &&
> +		    in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
>  			snprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N], MAX_LABEL_SIZE,
>  				 "vram_ch_%d", channel - CHANNEL_VRAM_N);
>  	}
> +
> +	return 0;
>  }
>  
>  static umode_t
> @@ -1551,8 +1675,10 @@ static int xe_hwmon_read_label(struct device *dev,
>  			*str = "mctrl";
>  		else if (channel == CHANNEL_PCIE)
>  			*str = "pcie";
> -		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
> +		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
>  			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
> +		else
> +			return -EOPNOTSUPP;
>  		return 0;
>  	case hwmon_power:
>  	case hwmon_energy:
> @@ -1580,7 +1706,7 @@ static const struct hwmon_chip_info hwmon_chip_info = {
>  	.info = hwmon_info,
>  };
>  
> -static void
> +static int
>  xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
>  {
>  	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
> @@ -1648,7 +1774,7 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
>  		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
>  			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
>  
> -	xe_hwmon_init_temp_info(hwmon);
> +	return xe_hwmon_init_temp_info(hwmon);
>  }
>  
>  int xe_hwmon_register(struct xe_device *xe)
> @@ -1677,7 +1803,9 @@ int xe_hwmon_register(struct xe_device *xe)
>  	hwmon->xe = xe;
>  	xe->hwmon = hwmon;
>  
> -	xe_hwmon_get_preregistration_info(hwmon);
> +	ret = xe_hwmon_get_preregistration_info(hwmon);
> +	if (ret)
> +		goto err_null_hwmon;
>  
>  	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
>  
> @@ -1687,10 +1815,14 @@ int xe_hwmon_register(struct xe_device *xe)
>  								hwmon_groups);
>  	if (IS_ERR(hwmon->hwmon_dev)) {
>  		drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
> -		xe->hwmon = NULL;
> -		return PTR_ERR(hwmon->hwmon_dev);
> +		ret = PTR_ERR(hwmon->hwmon_dev);
> +		goto err_null_hwmon;
>  	}
>  
>  	return 0;
> +
> +err_null_hwmon:
> +	xe->hwmon = NULL;
> +	return ret;
>  }
>  MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY");
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index e656fc012902..fa32436ecf6f 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -416,6 +416,7 @@ static const struct xe_device_desc bmg_desc = {
>  	.dma_mask_size = 46,
>  	.has_display = true,
>  	.has_fan_control = true,
> +	.has_fixed_vram_channels = true,
>  	.has_flat_ccs = 1,
>  	.has_mbx_power_limits = true,
>  	.has_mbx_thermal_info = true,
> @@ -794,6 +795,7 @@ static int xe_info_init_early(struct xe_device *xe,
>  	xe->info.has_cached_pt = desc->has_cached_pt;
>  	xe->info.has_drm_ras = desc->has_drm_ras;
>  	xe->info.has_fan_control = desc->has_fan_control;
> +	xe->info.has_fixed_vram_channels = desc->has_fixed_vram_channels;
>  	/* runtime fusing may force flat_ccs to disabled later */
>  	xe->info.has_flat_ccs = desc->has_flat_ccs;
>  	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 0041ec5676d3..4d1048ca7abe 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -42,6 +42,7 @@ struct xe_device_desc {
>  	u8 has_display:1;
>  	u8 has_drm_ras:1;
>  	u8 has_fan_control:1;
> +	u8 has_fixed_vram_channels:1;
>  	u8 has_flat_ccs:1;
>  	u8 has_gsc_nvm:1;
>  	u8 has_heci_gscfi:1;
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754
  2026-09-24 20:54 ` [PATCH v6 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
@ 2026-09-29 18:24   ` Rodrigo Vivi
  0 siblings, 0 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-29 18:24 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:27AM +0530, Karthik Poosa wrote:
> CRI temperature registers encode package and VRAM temperatures as
> IEEE-754 floating-point values. Decode these values before exposing
> them through hwmon.
>  
> Use integer-based IEEE-754 decoding since kernel code does not use
> floating-point operations and hwmon reports integer temperatures.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> Assisted-by: LLM

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
> 
> v2: Reject temperatures that overflow long on 32-bit.
> 
> v3: Replace magic numbers in xe_hwmon_temperature_decode() with named
>     REG_GENMASK()/REG_BIT() defines and use REG_FIELD_GET() for
>     extraction. (Rodrigo)
> 
>  drivers/gpu/drm/xe/xe_hwmon.c | 92 +++++++++++++++++++++++++++++------
>  1 file changed, 78 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 0422db647d11..76251d949b11 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -1239,6 +1239,69 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
>  	}
>  }
>  
> +#define IEEE754_SIGN		REG_BIT(31)
> +#define IEEE754_EXP_MASK	REG_GENMASK(30, 23)
> +#define IEEE754_MANTISSA_MASK	REG_GENMASK(22, 0)
> +#define IEEE754_EXP_BIAS	127 /* Exponent bias to obtain the actual exponent */
> +#define IEEE754_MANTISSA_BITS	23 /* Mantissa width and implicit leading-1 bit position */
> +#define IEEE754_EXP_SPECIAL	0xff /* reserved exponent value encoding infinity or NaN */
> +
> +/**
> + * xe_hwmon_temperature_decode - Decode an IEEE-754 temperature register value
> + * @reg_val: The raw register value to decode
> + *
> + * IEEE-754 single-precision format:
> + *
> + *  31 30                         23 22                         0
> + * +--+-----------------------------+----------------------------+
> + * | S|          exponent           |          fraction          |
> + * +--+-----------------------------+----------------------------+
> + *
> + * value = (-1)^S * 1.fraction * 2^(exponent - 127)
> + *
> + * Return: 0 on success or an error if @reg_val is non-finite or cannot be
> + * represented in millidegrees Celsius.
> + */
> +static int xe_hwmon_temperature_decode(u32 reg_val, long *temperature)
> +{
> +	u32 exponent = REG_FIELD_GET(IEEE754_EXP_MASK, reg_val);
> +	u32 mantissa = REG_FIELD_GET(IEEE754_MANTISSA_MASK, reg_val);
> +	s64 value;
> +	int shift;
> +
> +	/* Exponent 0xff encodes infinity or NaN. */
> +	if (exponent == IEEE754_EXP_SPECIAL)
> +		return -EINVAL;
> +
> +	/* Subnormal values are smaller than one millidegree Celsius. */
> +	if (!exponent) {
> +		*temperature = 0;
> +		return 0;
> +	}
> +
> +	value = (s64)(mantissa | BIT(IEEE754_MANTISSA_BITS)) * MILLIDEGREE_PER_DEGREE;
> +	shift = exponent - (IEEE754_EXP_BIAS + IEEE754_MANTISSA_BITS);
> +	if (shift >= 0) {
> +		if (shift >= BITS_PER_LONG || value > (LONG_MAX >> shift))
> +			return -ERANGE;
> +		value <<= shift;
> +	} else if (shift > -64) {
> +		value >>= -shift;
> +	} else {
> +		value = 0;
> +	}
> +
> +	/* Ensure the magnitude fits in long, which is 32-bit on some arches. */
> +	if (value > LONG_MAX)
> +		return -ERANGE;
> +
> +	if (reg_val & IEEE754_SIGN)
> +		value = -value;
> +
> +	*temperature = value;
> +	return 0;
> +}
> +
>  static int
>  xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  {
> @@ -1248,26 +1311,27 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val)
>  	switch (attr) {
>  	case hwmon_temp_input:
>  		switch (channel) {
> -		case CHANNEL_PKG:
> -		case CHANNEL_VRAM:
> -			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
> -
> -			/* HW register value is in degrees Celsius, convert to millidegrees. */
> -			*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> -			return 0;
>  		case CHANNEL_MCTRL:
>  			return get_mc_temp(hwmon, val);
>  		case CHANNEL_PCIE:
>  			return get_pcie_temp(hwmon, val);
> +		case CHANNEL_PKG:
> +		case CHANNEL_VRAM:
>  		case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX:
>  			reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel));
> -			/*
> -			 * This temperature format is 24 bit [31:8] signed integer and 8 bit
> -			 * [7:0] fraction.
> -			 */
> -			*val = (s32)(REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val)) *
> -				(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
> -				 MILLIDEGREE_PER_DEGREE;
> +			if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
> +				return xe_hwmon_temperature_decode((u32)reg_val, val);
> +			} else if (channel >= CHANNEL_VRAM_N) {
> +				/*
> +				 * This temperature format is 24 bit [31:8] signed integer and 8 bit
> +				 * [7:0] fraction for platforms before CRI.
> +				 */
> +				*val = (s32)REG_FIELD_GET(TEMP_MASK_VRAM_N, reg_val) *
> +					(REG_FIELD_GET(TEMP_SIGN_MASK, reg_val) ? -1 : 1) *
> +					MILLIDEGREE_PER_DEGREE;
> +			} else {
> +				*val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE;
> +			}
>  			return 0;
>  		default:
>  			return -EOPNOTSUPP;
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings
  2026-09-29 16:48     ` Poosa, Karthik
@ 2026-09-29 18:26       ` Rodrigo Vivi
  0 siblings, 0 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-29 18:26 UTC (permalink / raw)
  To: Poosa, Karthik
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Tue, Sep 29, 2026 at 10:18:14PM +0530, Poosa, Karthik wrote:
> 
> On 29-09-2026 01:08, Rodrigo Vivi wrote:
> > On Fri, Sep 25, 2026 at 02:24:20AM +0530, Karthik Poosa wrote:
> > > Add mmio_temp_valid() and mbx_temp_valid() to check whether a temperature
> > > sensor reading is valid. An MMIO value of 0xFFFFFFFF or a mailbox value of
> > > 0xFF indicates the sensor is unavailable.
> > > 
> > > Gate these checks behind has_mbx_temp_sentinel, enabled on CRI currently.
> > > 
> > > Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> > > ---
> > >   drivers/gpu/drm/xe/xe_device_types.h |  2 ++
> > >   drivers/gpu/drm/xe/xe_hwmon.c        | 16 ++++++++++++++++
> > >   drivers/gpu/drm/xe/xe_pci.c          |  2 ++
> > >   drivers/gpu/drm/xe/xe_pci_types.h    |  1 +
> > >   4 files changed, 21 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> > > index 4661bfce2f4e..87554605fa41 100644
> > > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > > @@ -202,6 +202,8 @@ struct xe_device {
> > >   		 * pcode mailbox commands.
> > >   		 */
> > >   		u8 has_mbx_power_limits:1;
> > > +		/** @info.has_mbx_temp_sentinel: Device has temperature-unavailable sentinels */
> > > +		u8 has_mbx_temp_sentinel:1;
> > >   		/** @info.has_mbx_thermal_info: Device supports thermal mailbox commands */
> > >   		u8 has_mbx_thermal_info:1;
> > >   		/** @info.has_mem_copy_instr: Device supports MEM_COPY instruction */
> > > diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> > > index c743867a2ebf..8a1dbe708828 100644
> > > --- a/drivers/gpu/drm/xe/xe_hwmon.c
> > > +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> > > @@ -104,6 +104,9 @@ enum sensor_attr_power {
> > >   /* Index of memory controller in READ_THERMAL_DATA output */
> > >   #define TEMP_INDEX_MCTRL	2
> > > +/* Mailbox sentinel reported for an unavailable temperature sensor */
> > > +#define TEMP_MBX_INVALID	0xFF
> > > +
> > >   /* Mailbox temperature is sign-magnitude: bit 7 sign, bits 6:0 magnitude. */
> > >   #define TEMP_MBX_SIGN		BIT(7)
> > >   #define TEMP_MBX_MAG		GENMASK(6, 0)
> > > @@ -822,6 +825,19 @@ static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
> > >   	return ret;
> > >   }
> > > +static inline bool mmio_temp_valid(const struct xe_hwmon *hwmon, u32 value)
> > > +{
> > > +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != U32_MAX
> > > +						     : value != 0;
> > > +}
> > > +
> > > +/* Mailbox temperature is sign-magnitude (bit 7 sign, bits 6:0 magnitude). */
> > > +static inline bool mbx_temp_valid(const struct xe_hwmon *hwmon, u8 value)
> > > +{
> > > +	return hwmon->xe->info.has_mbx_temp_sentinel ? value != TEMP_MBX_INVALID
> > > +						     : value != 0;
> > > +}
> > When reviewing the patch 7, I noticed a small change that took me back to the
> > temp valid...
> > 
> > What if temperature is 0 ?!
> > Why isn't it valid?
> This can happen on pre-CRI platforms (.has_mbx_temp_sentinel!=true), where
> temperature sentinel is not supported.
> In that case, we shall return true here on those platforms.

thanks for the clarification.
rv-b remains

> > 
> > > +
> > >   /* Decode an 8-bit sign-magnitude mailbox temperature to degrees Celsius. */
> > >   static int mbx_temp_decode(u8 value)
> > >   {
> > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > index d66d5a0339ae..e656fc012902 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > @@ -476,6 +476,7 @@ static const struct xe_device_desc cri_desc = {
> > >   	.has_gsc_nvm = 1,
> > >   	.has_i2c = true,
> > >   	.has_mbx_power_limits = true,
> > > +	.has_mbx_temp_sentinel = true,
> > >   	.has_mbx_thermal_info = true,
> > >   	.has_mert = true,
> > >   	.has_pre_prod_wa = 1,
> > > @@ -796,6 +797,7 @@ static int xe_info_init_early(struct xe_device *xe,
> > >   	/* runtime fusing may force flat_ccs to disabled later */
> > >   	xe->info.has_flat_ccs = desc->has_flat_ccs;
> > >   	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
> > > +	xe->info.has_mbx_temp_sentinel = desc->has_mbx_temp_sentinel;
> > >   	xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
> > >   	xe->info.has_gsc_nvm = desc->has_gsc_nvm;
> > >   	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
> > > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> > > index fed509ff601e..0041ec5676d3 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > > @@ -50,6 +50,7 @@ struct xe_device_desc {
> > >   	u8 has_late_bind:1;
> > >   	u8 has_llc:1;
> > >   	u8 has_mbx_power_limits:1;
> > > +	u8 has_mbx_temp_sentinel:1;
> > >   	u8 has_mbx_thermal_info:1;
> > >   	u8 has_mert:1;
> > >   	u8 has_pre_prod_wa:1;
> > > -- 
> > > 2.25.1
> > > 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI
  2026-09-24 20:54 ` [PATCH v6 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI Karthik Poosa
@ 2026-09-29 18:27   ` Rodrigo Vivi
  0 siblings, 0 replies; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-29 18:27 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:28AM +0530, Karthik Poosa wrote:
> On CRI the memory controller temperatures moved in the READ_THERMAL_DATA
> output: they now occupy bytes 16..19 instead of starting at byte 2.
> 
> Read and average the CRI memory controller sensors from bytes 16..19,
> keeping the existing byte 2..count-1 range for earlier platforms. Only
> the group(s) covering the used bytes are fetched.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_hwmon.c | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 76251d949b11..79240d4aadd3 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -109,6 +109,10 @@ enum sensor_attr_power {
>  /* Index of memory controller in READ_THERMAL_DATA output */
>  #define TEMP_INDEX_MCTRL	2
>  
> +/* On CRI the memory controller temperatures are READ_THERMAL_DATA bytes 16..19. */
> +#define CRI_TEMP_INDEX_MCTRL	16
> +#define CRI_TEMP_MCTRL_COUNT	4
> +
>  /* Mailbox sentinel reported for an unavailable temperature sensor */
>  #define TEMP_MBX_INVALID	0xFF
>  
> @@ -963,10 +967,19 @@ static int mbx_temp_decode(u8 value)
>  static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> -	int ret, i, count = 0;
> +	int ret, i, start, end, count = 0;
>  	s32 average = 0;
>  
> -	for (i = 0; i < DIV_ROUND_UP(hwmon->temp.count, sizeof(u32)); i++) {
> +	/* CRI relocated the memory controller temperatures to READ_THERMAL_DATA bytes 16..19. */
> +	if (hwmon->xe->info.platform >= XE_CRESCENTISLAND) {
> +		start = CRI_TEMP_INDEX_MCTRL;
> +		end = CRI_TEMP_INDEX_MCTRL + CRI_TEMP_MCTRL_COUNT;
> +	} else {
> +		start = TEMP_INDEX_MCTRL;
> +		end = hwmon->temp.count - 1;
> +	}
> +
> +	for (i = start / sizeof(u32); i < DIV_ROUND_UP(end, sizeof(u32)); i++) {
>  		ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, i),
>  				    &hwmon->temp.dword[i], NULL);
>  		if (ret)
> @@ -975,7 +988,7 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  			hwmon->temp.dword[i]);
>  	}
>  
> -	for (i = TEMP_INDEX_MCTRL; i < hwmon->temp.count - 1; i++) {
> +	for (i = start; i < end; i++) {
>  		if (!mbx_temp_valid(hwmon, hwmon->temp.value[i]))
>  			continue;
>  		average += mbx_temp_decode(hwmon->temp.value[i]);
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 13/13] drm/xe/hwmon: Update PCIE temperature sensor offset for CRI
  2026-09-24 20:54 ` [PATCH v6 13/13] drm/xe/hwmon: Update PCIE temperature sensor " Karthik Poosa
@ 2026-09-29 18:29   ` Rodrigo Vivi
  2026-09-30 17:11     ` Poosa, Karthik
  0 siblings, 1 reply; 36+ messages in thread
From: Rodrigo Vivi @ 2026-09-29 18:29 UTC (permalink / raw)
  To: Karthik Poosa
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait

On Fri, Sep 25, 2026 at 02:24:29AM +0530, Karthik Poosa wrote:
> On Crescent Island, the PCIe temperature sensor is reported in
> READ_THERMAL_DATA group 5, byte 0. Add support for reading the sensor
> from this mailbox location.
> 
> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hwmon.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 79240d4aadd3..fcb1d2f14f5a 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -113,6 +113,9 @@ enum sensor_attr_power {
>  #define CRI_TEMP_INDEX_MCTRL	16
>  #define CRI_TEMP_MCTRL_COUNT	4
>  
> +/* On CRI the PCIe temperature is READ_THERMAL_DATA byte 20 (group 5, low byte). */
> +#define CRI_PCIE_SENSOR_GROUP_ID	5
> +
>  /* Mailbox sentinel reported for an unavailable temperature sensor */
>  #define TEMP_MBX_INVALID	0xFF
>  
> @@ -1011,16 +1014,21 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>  static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
> +	u32 group = PCIE_SENSOR_GROUP_ID;
>  	u32 data = 0;
>  	int ret;
>  
> +	/* CRI relocated the PCIe temperature to a different data group. */
> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
> +		group = CRI_PCIE_SENSOR_GROUP_ID;
> +
>  	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA,
> -						  PCIE_SENSOR_GROUP_ID), &data, NULL);
> +						  group), &data, NULL);
>  	if (ret)
>  		return ret;
>  
> -	/* Sensor offset is different for G21 */
> -	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21)
> +	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21 &&
> +	    hwmon->xe->info.platform != XE_CRESCENTISLAND)

this is deserving a info flag no?!

>  		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
>  
>  	data = REG_FIELD_GET(TEMP_MASK, data);
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 13/13] drm/xe/hwmon: Update PCIE temperature sensor offset for CRI
  2026-09-29 18:29   ` Rodrigo Vivi
@ 2026-09-30 17:11     ` Poosa, Karthik
  0 siblings, 0 replies; 36+ messages in thread
From: Poosa, Karthik @ 2026-09-30 17:11 UTC (permalink / raw)
  To: Rodrigo Vivi
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait


On 29-09-2026 23:59, Rodrigo Vivi wrote:
> On Fri, Sep 25, 2026 at 02:24:29AM +0530, Karthik Poosa wrote:
>> On Crescent Island, the PCIe temperature sensor is reported in
>> READ_THERMAL_DATA group 5, byte 0. Add support for reading the sensor
>> from this mailbox location.
>>
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_hwmon.c | 14 +++++++++++---
>>   1 file changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 79240d4aadd3..fcb1d2f14f5a 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -113,6 +113,9 @@ enum sensor_attr_power {
>>   #define CRI_TEMP_INDEX_MCTRL	16
>>   #define CRI_TEMP_MCTRL_COUNT	4
>>   
>> +/* On CRI the PCIe temperature is READ_THERMAL_DATA byte 20 (group 5, low byte). */
>> +#define CRI_PCIE_SENSOR_GROUP_ID	5
>> +
>>   /* Mailbox sentinel reported for an unavailable temperature sensor */
>>   #define TEMP_MBX_INVALID	0xFF
>>   
>> @@ -1011,16 +1014,21 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val)
>>   static int get_pcie_temp(struct xe_hwmon *hwmon, long *val)
>>   {
>>   	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>> +	u32 group = PCIE_SENSOR_GROUP_ID;
>>   	u32 data = 0;
>>   	int ret;
>>   
>> +	/* CRI relocated the PCIe temperature to a different data group. */
>> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
>> +		group = CRI_PCIE_SENSOR_GROUP_ID;
>> +
>>   	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA,
>> -						  PCIE_SENSOR_GROUP_ID), &data, NULL);
>> +						  group), &data, NULL);
>>   	if (ret)
>>   		return ret;
>>   
>> -	/* Sensor offset is different for G21 */
>> -	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21)
>> +	if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21 &&
>> +	    hwmon->xe->info.platform != XE_CRESCENTISLAND)
> this is deserving a info flag no?!
yes that looks cleaner, we can add xe.info.pcie_temp_sensor_offset and 
compute group id and byte offset in the group from that.
>
>>   		data = REG_FIELD_GET(PCIE_SENSOR_MASK, data);
>>   
>>   	data = REG_FIELD_GET(TEMP_MASK, data);
>> -- 
>> 2.25.1
>>

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH v6 10/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support
  2026-09-29 18:04   ` Rodrigo Vivi
@ 2026-10-01 19:02     ` Poosa, Karthik
  0 siblings, 0 replies; 36+ messages in thread
From: Poosa, Karthik @ 2026-10-01 19:02 UTC (permalink / raw)
  To: Rodrigo Vivi
  Cc: intel-xe, anshuman.gupta, badal.nilawar, raag.jadav, riana.tauro,
	sk.anirban, mallesh.koujalagi, soham.purkait


On 29-09-2026 23:34, Rodrigo Vivi wrote:
> On Fri, Sep 25, 2026 at 02:24:26AM +0530, Karthik Poosa wrote:
>> On CRI, derive the number of available VRAM temperature channels from the
>> CRI_MSU_VRAM_ENABLE register, where each enabled MSU contributes
>> VRAM_CHANNELS_PER_MSU channels.
>>   
>> Increase the maximum supported VRAM channel count to 80 and use the
>> derived count to control VRAM sensor enumeration, channel access, and
>> VRAM label allocation. Add a has_fixed_vram_channels platform flag to
>> preserve the existing fixed-channel behavior on non-CRI platforms.
>>
>> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
>> ---
>>
>> v2:
>>   - Use the highest enabled MSU index to determine the VRAM channel bound
>>     instead of counting enabled MSUs. A sparse mask could expose channels
>>     beyond the allocated label array, leaving the label pointer unset and
>>     potentially hanging during sysfs reads.
>>   - Also return an error when no temperature label matches the requested
>>     channel.
>>
>>   drivers/gpu/drm/xe/regs/xe_pcode_regs.h |   1 +
>>   drivers/gpu/drm/xe/xe_device_types.h    |   2 +
>>   drivers/gpu/drm/xe/xe_hwmon.c           | 164 +++++++++++++++++++++---
>>   drivers/gpu/drm/xe/xe_pci.c             |   2 +
>>   drivers/gpu/drm/xe/xe_pci_types.h       |   1 +
>>   5 files changed, 154 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
>> index a969661f0c95..d9e4847dd68e 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
>> @@ -28,6 +28,7 @@
>>   #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
>>   
>>   #define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
>> +#define CRI_MSU_VRAM_ENABLE			XE_REG(0x138340)
> can you please share again the ref to this?
shared offline
>
>>   #define CRI_PACKAGE_TEMPERATURE			XE_REG(0x138344)
>>   #define CRI_VRAM_TEMPERATURE			XE_REG(0x138348)
>>   #define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index 87554605fa41..8a1ca65f5665 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -184,6 +184,8 @@ struct xe_device {
>>   		u8 has_drm_ras:1;
>>   		/** @info.has_fan_control: Device supports fan control */
>>   		u8 has_fan_control:1;
>> +		/** @info.has_fixed_vram_channels: Device has fixed VRAM temperature channels */
>> +		u8 has_fixed_vram_channels:1;
>>   		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
>>   		u8 has_flat_ccs:1;
>>   		/** @info.has_gsc_nvm: Device has gsc non-volatile memory */
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> index 1b2e2fbe43c8..0422db647d11 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -39,7 +39,11 @@ enum xe_hwmon_reg_operation {
>>   	REG_READ64,
>>   };
>>   
>> -#define MAX_VRAM_CHANNELS      (16)
>> +#define MAX_VRAM_CHANNELS	80
>> +#define FIXED_VRAM_CHANNELS	16
>> +
>> +/* Each MSU enable bit maps to one VRAM subsystem of 4 channels. */
>> +#define VRAM_CHANNELS_PER_MSU	4
>>   
>>   enum xe_hwmon_channel {
>>   	CHANNEL_CARD,
>> @@ -48,6 +52,7 @@ enum xe_hwmon_channel {
>>   	CHANNEL_MCTRL,
>>   	CHANNEL_PCIE,
>>   	CHANNEL_VRAM_N,
>> +	/* Compile-time upper bound; actual channel count is hwmon->temp.vram_count */
>>   	CHANNEL_VRAM_N_MAX = CHANNEL_VRAM_N + MAX_VRAM_CHANNELS - 1,
>>   	CHANNEL_MAX,
>>   };
>> @@ -144,18 +149,22 @@ struct xe_hwmon_thermal_info {
>>   		/** @data: temperature limits in dwords */
>>   		u32 data[DIV_ROUND_UP(TEMP_LIMIT_MAX, sizeof(u32))];
>>   	};
>> -	/** @count: no of temperature sensors available for the platform */
>> +	/** @count: temperature sensors count from READ_THERMAL_CONFIG */
>>   	u8 count;
>> +	/** @vram_count: exclusive upper bound for VRAM temperature channel indices */
>> +	u8 vram_count;
>>   	/** @available: temperature sensor availability cached at registration */
>>   	bool available[CHANNEL_MAX];
>> +	/** @msu_mask: VRAM subsystem enable mask read from MMIO */
>> +	u32 msu_mask;
>>   	union {
>>   		/** @value: per-sensor raw mailbox temperature; bit7=sign, bits6:0=magnitude */
>>   		u8 value[U8_MAX + 1];
>>   		/** @dword: sensor values as dwords, u32-aligned for pcode reads */
>>   		u32 dword[DIV_ROUND_UP(U8_MAX + 1, sizeof(u32))];
>>   	};
>> -	/** @vram_label: vram label names */
>> -	char vram_label[MAX_VRAM_CHANNELS][MAX_LABEL_SIZE];
>> +	/** @vram_label: vram label names, dynamically allocated based on vram_count */
>> +	char (*vram_label)[MAX_LABEL_SIZE];
>>   };
>>   
>>   /**
>> @@ -269,6 +278,14 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
>>   	return ret;
>>   }
>>   
>> +static bool xe_hwmon_vram_channel_enabled(const struct xe_hwmon *hwmon, int index)
>> +{
>> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND)
>> +		return hwmon->temp.msu_mask & BIT(index / VRAM_CHANNELS_PER_MSU);
>> +
>> +	return true;
>> +}
>> +
>>   static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
>>   				      int channel)
>>   {
>> @@ -281,14 +298,16 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
>>   				return CRI_PACKAGE_TEMPERATURE;
>>   			else if (channel == CHANNEL_VRAM)
>>   				return CRI_VRAM_TEMPERATURE;
>> -			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
>> +			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
>> +				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
>>   				return CRI_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
>>   		} else if (xe->info.platform == XE_BATTLEMAGE) {
>>   			if (channel == CHANNEL_PKG)
>>   				return BMG_PACKAGE_TEMPERATURE;
>>   			else if (channel == CHANNEL_VRAM)
>>   				return BMG_VRAM_TEMPERATURE;
>> -			else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
>> +			else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count) &&
>> +				 xe_hwmon_vram_channel_enabled(hwmon, channel - CHANNEL_VRAM_N))
>>   				return BMG_VRAM_TEMPERATURE_N(channel - CHANNEL_VRAM_N);
>>   		} else if (xe->info.platform == XE_DG2) {
>>   			if (channel == CHANNEL_PKG)
>> @@ -798,6 +817,70 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>>   			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>>   			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>>   			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
>> +			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL,
> I was wondering if there was something better we could get here...
> and LLM suggested me a reduction from 80 to 8 lines:
>
> #define TEMP_CFG_CARD HWMON_T_LABEL
> #define TEMP_CFG_PKG  (HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | \
>                         HWMON_T_LABEL | HWMON_T_MAX)
> #define TEMP_CFG_SENSOR       (HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL)
>
> /*
>   * Indexed by &enum xe_hwmon_channel and zero-terminated; hwmon derives the
>   * channel count from the array contents. Sizing on CHANNEL_MAX keeps this in
>   * lockstep with the enum.
>   */
> static const u32 hwmon_temp_config[CHANNEL_MAX + 1] = {
>        [CHANNEL_CARD]                          = TEMP_CFG_CARD,
>        [CHANNEL_PKG]                           = TEMP_CFG_PKG,
>        [CHANNEL_VRAM]                          = TEMP_CFG_SENSOR,
>        [CHANNEL_MCTRL]                         = TEMP_CFG_SENSOR,
>        [CHANNEL_PCIE]                          = TEMP_CFG_SENSOR,
>        [CHANNEL_VRAM_N ... CHANNEL_VRAM_N_MAX] = TEMP_CFG_SENSOR,
>        [CHANNEL_MAX]                           = 0,    /* terminator */
> };
>
> static const struct hwmon_channel_info hwmon_temp_info = {
>        .type = hwmon_temp,
>        .config = hwmon_temp_config,
> };
>
> static const struct hwmon_channel_info * const hwmon_info[] = {
>        &hwmon_temp_info,
>        HWMON_CHANNEL_INFO(power, ...),
>        /* unchanged */
> };
>
> can be done in a follow up though...
i think we shall make do this in separate patch series
> Everything else looks sane... I just need to double check the regs again...
shared these details offline
>
>>   			   HWMON_T_CRIT | HWMON_T_EMERGENCY | HWMON_T_INPUT | HWMON_T_LABEL),
>>   	HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT |
>>   			   HWMON_P_CAP,
>> @@ -812,15 +895,37 @@ static const struct hwmon_channel_info * const hwmon_info[] = {
>>   static int xe_hwmon_pcode_read_thermal_info(struct xe_hwmon *hwmon)
>>   {
>>   	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
>> +	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>>   	u32 config = 0;
>>   	int ret;
>>   
>> +	/*
>> +	 * Only CRI reports dynamic VRAM channel state. Fixed-channel platforms
>> +	 * set the count up front so those sensors stay visible even if the thermal
>> +	 * mailbox reads below fail.
>> +	 */
>> +	if (hwmon->xe->info.has_fixed_vram_channels)
>> +		hwmon->temp.vram_count = FIXED_VRAM_CHANNELS;
>> +
>> +	if (hwmon->xe->info.platform == XE_CRESCENTISLAND) {
>> +		hwmon->temp.msu_mask = xe_mmio_read32(mmio, CRI_MSU_VRAM_ENABLE);
>> +		hwmon->temp.vram_count = fls(hwmon->temp.msu_mask) * VRAM_CHANNELS_PER_MSU;
>> +		drm_dbg(&hwmon->xe->drm, "MSU VRAM enable mask 0x%x, VRAM channel bound %d\n",
>> +			hwmon->temp.msu_mask, hwmon->temp.vram_count);
>> +		if (hwmon->temp.vram_count > MAX_VRAM_CHANNELS) {
>> +			drm_warn(&hwmon->xe->drm,
>> +				 "VRAM channel bound %d exceeds max %d, clamping\n",
>> +				 hwmon->temp.vram_count, MAX_VRAM_CHANNELS);
>> +			hwmon->temp.vram_count = MAX_VRAM_CHANNELS;
>> +		}
>> +	}
>> +
>>   	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_LIMITS, 0),
>>   			    &hwmon->temp.data[0], &hwmon->temp.data[1]);
>>   	if (ret)
>>   		return ret;
>>   
>> -	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%x val1 0x%x\n",
>> +	drm_dbg(&hwmon->xe->drm, "thermal info read val 0x%08x val1 0x%08x\n",
>>   		hwmon->temp.data[0], hwmon->temp.data[1]);
>>   
>>   	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_CONFIG, 0),
>> @@ -1025,6 +1130,14 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
>>   		if (!xe_reg_is_valid(reg))
>>   			return false;
>>   
>> +		/*
>> +		 * On CRI, VRAM channel presence comes from the MSU enable mask
>> +		 * (applied in xe_hwmon_get_reg()); the temperature register's
>> +		 * 0xffffffff sentinel is not reliable for VRAM channels.
>> +		 */
>> +		if (hwmon->xe->info.platform == XE_CRESCENTISLAND && channel >= CHANNEL_VRAM_N)
>> +			return true;
>> +
>>   		reg_val = xe_mmio_read32(mmio, reg);
>>   		if (!mmio_temp_valid(hwmon, reg_val)) {
>>   			drm_dbg(&hwmon->xe->drm,
>> @@ -1042,20 +1155,31 @@ static bool xe_hwmon_temp_probe(struct xe_hwmon *hwmon, int channel)
>>   	}
>>   }
>>   
>> -static void xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
>> +static int xe_hwmon_init_temp_info(struct xe_hwmon *hwmon)
>>   {
>> +	struct device *dev = hwmon->xe->drm.dev;
>>   	int channel;
>>   
>>   	if (hwmon->xe->info.has_mbx_thermal_info && xe_hwmon_pcode_read_thermal_info(hwmon))
>>   		drm_warn(&hwmon->xe->drm, "Thermal mailbox not supported by card firmware\n");
>>   
>> +	/* vram_count is known only after reading thermal info above. */
>> +	if (hwmon->temp.vram_count) {
>> +		hwmon->temp.vram_label = devm_kcalloc(dev, hwmon->temp.vram_count,
>> +						      MAX_LABEL_SIZE, GFP_KERNEL);
>> +		if (!hwmon->temp.vram_label)
>> +			return -ENOMEM;
>> +	}
>> +
>>   	for (channel = 0; channel < CHANNEL_MAX; channel++) {
>>   		hwmon->temp.available[channel] = xe_hwmon_temp_probe(hwmon, channel);
>> -		if (hwmon->temp.available[channel] &&
>> -		    in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
>> +		if (hwmon->temp.available[channel] && hwmon->temp.vram_label &&
>> +		    in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
>>   			snprintf(hwmon->temp.vram_label[channel - CHANNEL_VRAM_N], MAX_LABEL_SIZE,
>>   				 "vram_ch_%d", channel - CHANNEL_VRAM_N);
>>   	}
>> +
>> +	return 0;
>>   }
>>   
>>   static umode_t
>> @@ -1551,8 +1675,10 @@ static int xe_hwmon_read_label(struct device *dev,
>>   			*str = "mctrl";
>>   		else if (channel == CHANNEL_PCIE)
>>   			*str = "pcie";
>> -		else if (in_range(channel, CHANNEL_VRAM_N, MAX_VRAM_CHANNELS))
>> +		else if (in_range(channel, CHANNEL_VRAM_N, hwmon->temp.vram_count))
>>   			*str = hwmon->temp.vram_label[channel - CHANNEL_VRAM_N];
>> +		else
>> +			return -EOPNOTSUPP;
>>   		return 0;
>>   	case hwmon_power:
>>   	case hwmon_energy:
>> @@ -1580,7 +1706,7 @@ static const struct hwmon_chip_info hwmon_chip_info = {
>>   	.info = hwmon_info,
>>   };
>>   
>> -static void
>> +static int
>>   xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
>>   {
>>   	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
>> @@ -1648,7 +1774,7 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
>>   		if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
>>   			xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
>>   
>> -	xe_hwmon_init_temp_info(hwmon);
>> +	return xe_hwmon_init_temp_info(hwmon);
>>   }
>>   
>>   int xe_hwmon_register(struct xe_device *xe)
>> @@ -1677,7 +1803,9 @@ int xe_hwmon_register(struct xe_device *xe)
>>   	hwmon->xe = xe;
>>   	xe->hwmon = hwmon;
>>   
>> -	xe_hwmon_get_preregistration_info(hwmon);
>> +	ret = xe_hwmon_get_preregistration_info(hwmon);
>> +	if (ret)
>> +		goto err_null_hwmon;
>>   
>>   	drm_dbg(&xe->drm, "Register xe hwmon interface\n");
>>   
>> @@ -1687,10 +1815,14 @@ int xe_hwmon_register(struct xe_device *xe)
>>   								hwmon_groups);
>>   	if (IS_ERR(hwmon->hwmon_dev)) {
>>   		drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
>> -		xe->hwmon = NULL;
>> -		return PTR_ERR(hwmon->hwmon_dev);
>> +		ret = PTR_ERR(hwmon->hwmon_dev);
>> +		goto err_null_hwmon;
>>   	}
>>   
>>   	return 0;
>> +
>> +err_null_hwmon:
>> +	xe->hwmon = NULL;
>> +	return ret;
>>   }
>>   MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY");
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index e656fc012902..fa32436ecf6f 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -416,6 +416,7 @@ static const struct xe_device_desc bmg_desc = {
>>   	.dma_mask_size = 46,
>>   	.has_display = true,
>>   	.has_fan_control = true,
>> +	.has_fixed_vram_channels = true,
>>   	.has_flat_ccs = 1,
>>   	.has_mbx_power_limits = true,
>>   	.has_mbx_thermal_info = true,
>> @@ -794,6 +795,7 @@ static int xe_info_init_early(struct xe_device *xe,
>>   	xe->info.has_cached_pt = desc->has_cached_pt;
>>   	xe->info.has_drm_ras = desc->has_drm_ras;
>>   	xe->info.has_fan_control = desc->has_fan_control;
>> +	xe->info.has_fixed_vram_channels = desc->has_fixed_vram_channels;
>>   	/* runtime fusing may force flat_ccs to disabled later */
>>   	xe->info.has_flat_ccs = desc->has_flat_ccs;
>>   	xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
>> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>> index 0041ec5676d3..4d1048ca7abe 100644
>> --- a/drivers/gpu/drm/xe/xe_pci_types.h
>> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
>> @@ -42,6 +42,7 @@ struct xe_device_desc {
>>   	u8 has_display:1;
>>   	u8 has_drm_ras:1;
>>   	u8 has_fan_control:1;
>> +	u8 has_fixed_vram_channels:1;
>>   	u8 has_flat_ccs:1;
>>   	u8 has_gsc_nvm:1;
>>   	u8 has_heci_gscfi:1;
>> -- 
>> 2.25.1
>>

^ permalink raw reply	[flat|nested] 36+ messages in thread

end of thread, other threads:[~2026-10-01 19:02 UTC | newest]

Thread overview: 36+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-24 20:54 [PATCH v6 00/13] drm/xe/hwmon: Update hwmon thermal mailbox Karthik Poosa
2026-09-24 20:54 ` [PATCH v6 01/13] drm/xe/hwmon: Handle pcode read failures of xe_hwmon_pcode_rmw_power_limit Karthik Poosa
2026-09-28  0:11   ` Rodrigo Vivi
2026-09-28 15:32     ` Poosa, Karthik
2026-09-24 20:54 ` [PATCH v6 02/13] drm/xe/hwmon: Decode mailbox temperature as sign-magnitude Karthik Poosa
2026-09-28  0:15   ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 03/13] drm/xe/hwmon: Fix memory controller thermal data handling Karthik Poosa
2026-09-24 20:54 ` [PATCH v6 04/13] drm/xe/hwmon: Add helpers to validate thermal sensor readings Karthik Poosa
2026-09-28  0:19   ` Rodrigo Vivi
2026-09-28 16:08     ` Poosa, Karthik
2026-09-28 17:59       ` Rodrigo Vivi
2026-09-28 19:38   ` Rodrigo Vivi
2026-09-29 16:48     ` Poosa, Karthik
2026-09-29 18:26       ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 05/13] drm/xe/hwmon: Handle unavailable memory controller sensors Karthik Poosa
2026-09-28 16:08   ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 06/13] drm/xe/hwmon: Detect unavailable PCIe thermal sensors Karthik Poosa
2026-09-28 16:10   ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 07/13] drm/xe/hwmon: Consolidate temperature sensor availability checks Karthik Poosa
2026-09-28 19:39   ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 08/13] drm/xe/hwmon: Cache temperature availability to reduce probe time Karthik Poosa
2026-09-28 21:17   ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 09/13] drm/xe/hwmon: use CRI-specific package and VRAM temperature registers Karthik Poosa
2026-09-24 20:54 ` [PATCH v6 10/13] drm/xe/hwmon: Add platform-aware VRAM thermal channel support Karthik Poosa
2026-09-29 18:04   ` Rodrigo Vivi
2026-10-01 19:02     ` Poosa, Karthik
2026-09-24 20:54 ` [PATCH v6 11/13] drm/xe/hwmon: Decode CRI temperature registers as IEEE-754 Karthik Poosa
2026-09-29 18:24   ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 12/13] drm/xe/hwmon: Update memory controller temperature offset for CRI Karthik Poosa
2026-09-29 18:27   ` Rodrigo Vivi
2026-09-24 20:54 ` [PATCH v6 13/13] drm/xe/hwmon: Update PCIE temperature sensor " Karthik Poosa
2026-09-29 18:29   ` Rodrigo Vivi
2026-09-30 17:11     ` Poosa, Karthik
2026-09-24 21:05 ` ✓ CI.KUnit: success for drm/xe/hwmon: Update hwmon thermal mailbox (rev3) Patchwork
2026-09-24 22:34 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-25 11:16 ` ✗ Xe.CI.FULL: failure " Patchwork

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