* [PATCH 1/5] drm/i915/vrr: Extract helpers to convert between guardband and pipeline_full values
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
@ 2025-09-17 20:34 ` Ville Syrjala
2025-09-18 9:39 ` Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 2/5] drm/i915/vrr: Readout framestart_delay earlier Ville Syrjala
` (6 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2025-09-17 20:34 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
I'd like to move towards a world where we can't more or less
pretend that the ICl/TGL VRR hardware works the same way as
ADL+. To that end extract some helpers to convert between
the guardband and pipeline_full representations.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++++++++++------
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 3eed37f271b0..5fee85b0bc99 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -119,6 +119,20 @@ static int intel_vrr_vmin_flipline(const struct intel_crtc_state *crtc_state)
return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display);
}
+static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state,
+ int guardband)
+{
+ /* hardware imposes one extra scanline somewhere */
+ return guardband - crtc_state->framestart_delay - 1;
+}
+
+static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *crtc_state,
+ int pipeline_full)
+{
+ /* hardware imposes one extra scanline somewhere */
+ return pipeline_full + crtc_state->framestart_delay + 1;
+}
+
/*
* Without VRR registers get latched at:
* vblank_start
@@ -142,8 +156,8 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
if (DISPLAY_VER(display) >= 13)
return crtc_state->vrr.guardband;
else
- /* hardware imposes one extra scanline somewhere */
- return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
+ return intel_vrr_pipeline_full_to_guardband(crtc_state,
+ crtc_state->vrr.pipeline_full);
}
int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
@@ -417,18 +431,18 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ int guardband;
if (!intel_vrr_possible(crtc_state))
return;
+ guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
+
if (DISPLAY_VER(display) >= 13) {
- crtc_state->vrr.guardband =
- crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
+ crtc_state->vrr.guardband = guardband;
} else {
- /* hardware imposes one extra scanline somewhere */
crtc_state->vrr.pipeline_full =
- min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
- crtc_state->framestart_delay - 1);
+ min(255, intel_vrr_guardband_to_pipeline_full(crtc_state, guardband));
/*
* vmin/vmax/flipline also need to be adjusted by
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 1/5] drm/i915/vrr: Extract helpers to convert between guardband and pipeline_full values
2025-09-17 20:34 ` [PATCH 1/5] drm/i915/vrr: Extract helpers to convert between guardband and pipeline_full values Ville Syrjala
@ 2025-09-18 9:39 ` Nautiyal, Ankit K
0 siblings, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-18 9:39 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On 9/18/2025 2:04 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I'd like to move towards a world where we can't more or less
> pretend that the ICl/TGL VRR hardware works the same way as
> ADL+. To that end extract some helpers to convert between
> the guardband and pipeline_full representations.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks for this, it will really help to just work with guardband instead
of pipeline_full and all.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++++++++++------
> 1 file changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 3eed37f271b0..5fee85b0bc99 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -119,6 +119,20 @@ static int intel_vrr_vmin_flipline(const struct intel_crtc_state *crtc_state)
> return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display);
> }
>
> +static int intel_vrr_guardband_to_pipeline_full(const struct intel_crtc_state *crtc_state,
> + int guardband)
> +{
> + /* hardware imposes one extra scanline somewhere */
> + return guardband - crtc_state->framestart_delay - 1;
> +}
> +
> +static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *crtc_state,
> + int pipeline_full)
> +{
> + /* hardware imposes one extra scanline somewhere */
> + return pipeline_full + crtc_state->framestart_delay + 1;
> +}
> +
> /*
> * Without VRR registers get latched at:
> * vblank_start
> @@ -142,8 +156,8 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
> if (DISPLAY_VER(display) >= 13)
> return crtc_state->vrr.guardband;
> else
> - /* hardware imposes one extra scanline somewhere */
> - return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
> + return intel_vrr_pipeline_full_to_guardband(crtc_state,
> + crtc_state->vrr.pipeline_full);
> }
>
> int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
> @@ -417,18 +431,18 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> + int guardband;
>
> if (!intel_vrr_possible(crtc_state))
> return;
>
> + guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
> +
> if (DISPLAY_VER(display) >= 13) {
> - crtc_state->vrr.guardband =
> - crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
> + crtc_state->vrr.guardband = guardband;
> } else {
> - /* hardware imposes one extra scanline somewhere */
> crtc_state->vrr.pipeline_full =
> - min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
> - crtc_state->framestart_delay - 1);
> + min(255, intel_vrr_guardband_to_pipeline_full(crtc_state, guardband));
>
> /*
> * vmin/vmax/flipline also need to be adjusted by
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 2/5] drm/i915/vrr: Readout framestart_delay earlier
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
2025-09-17 20:34 ` [PATCH 1/5] drm/i915/vrr: Extract helpers to convert between guardband and pipeline_full values Ville Syrjala
@ 2025-09-17 20:34 ` Ville Syrjala
2025-09-18 9:40 ` Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl Ville Syrjala
` (5 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2025-09-17 20:34 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to pretend that ICL/TGL VRR hardware has a similar guardband
as on ADL+ we'll need access to framestart_delay already during
intel_vrr_get_config(). Hoist the framestart_delay to an earlier point
to make that possible.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a743d1339550..c7d85fd38890 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3891,6 +3891,15 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
intel_joiner_get_config(pipe_config);
intel_dsc_get_config(pipe_config);
+ if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
+ tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
+
+ pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
+ } else {
+ /* no idea if this is correct */
+ pipe_config->framestart_delay = 1;
+ }
+
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
DISPLAY_VER(display) >= 11)
intel_get_transcoder_timings(crtc, pipe_config);
@@ -3942,15 +3951,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1;
}
- if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
- tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
-
- pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
- } else {
- /* no idea if this is correct */
- pipe_config->framestart_delay = 1;
- }
-
out:
intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 2/5] drm/i915/vrr: Readout framestart_delay earlier
2025-09-17 20:34 ` [PATCH 2/5] drm/i915/vrr: Readout framestart_delay earlier Ville Syrjala
@ 2025-09-18 9:40 ` Nautiyal, Ankit K
0 siblings, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-18 9:40 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On 9/18/2025 2:04 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In order to pretend that ICL/TGL VRR hardware has a similar guardband
> as on ADL+ we'll need access to framestart_delay already during
> intel_vrr_get_config(). Hoist the framestart_delay to an earlier point
> to make that possible.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a743d1339550..c7d85fd38890 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3891,6 +3891,15 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> intel_joiner_get_config(pipe_config);
> intel_dsc_get_config(pipe_config);
>
> + if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> + tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
> +
> + pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
> + } else {
> + /* no idea if this is correct */
> + pipe_config->framestart_delay = 1;
> + }
> +
> if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> DISPLAY_VER(display) >= 11)
> intel_get_transcoder_timings(crtc, pipe_config);
> @@ -3942,15 +3951,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->pixel_multiplier = 1;
> }
>
> - if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> - tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
> -
> - pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
> - } else {
> - /* no idea if this is correct */
> - pipe_config->framestart_delay = 1;
> - }
> -
> out:
> intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
2025-09-17 20:34 ` [PATCH 1/5] drm/i915/vrr: Extract helpers to convert between guardband and pipeline_full values Ville Syrjala
2025-09-17 20:34 ` [PATCH 2/5] drm/i915/vrr: Readout framestart_delay earlier Ville Syrjala
@ 2025-09-17 20:34 ` Ville Syrjala
2025-09-18 9:37 ` Nautiyal, Ankit K
2025-09-18 18:00 ` Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 4/5] drm/i915/vrr: Annotate some functions with "hw" Ville Syrjala
` (4 subsequent siblings)
7 siblings, 2 replies; 21+ messages in thread
From: Ville Syrjala @ 2025-09-17 20:34 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
While ICL/TGL VRR hardware doesn't have a register for the guardband
value, our lives will be simpler if we pretend that it does. Start
by computing the guardband the same as on ADL+ and storing it in
the state, and only then we convert it into the corresponding
pipeline_full value that the hardware can consume. During readout we
do the opposite.
I was debating whether to completely remove pipeline_full from the
crtc state, but decided to keep it for now. Mainly because we check
it in vrr_params_changed() and simply checking the guardband instead
isn't 100% equivalent; Theoretically, framestart_delay may have
changed in the opposite direction to pipeline_full, keeping the
derived guardband value unchaged. One solution would be to also check
framestart_delay, but that feels a bit leaky abstraction wise.
Also note that we don't currently handle the maximum limit of 255
scanlines for the pipeline_full in a very nice way. The actual
position of the delayed vblank will move because of that clamping,
and so some of our code may get confused. But fixing this shall
wait a for now.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 36 +++++++++++---------
2 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c7d85fd38890..f4124c79bc83 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3891,6 +3891,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
intel_joiner_get_config(pipe_config);
intel_dsc_get_config(pipe_config);
+ /* intel_vrr_get_config() depends on .framestart_delay */
if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5fee85b0bc99..9cdcc2558ead 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -151,13 +151,7 @@ static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *c
*/
static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
-
- if (DISPLAY_VER(display) >= 13)
- return crtc_state->vrr.guardband;
- else
- return intel_vrr_pipeline_full_to_guardband(crtc_state,
- crtc_state->vrr.pipeline_full);
+ return crtc_state->vrr.guardband;
}
int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
@@ -431,18 +425,22 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
- int guardband;
if (!intel_vrr_possible(crtc_state))
return;
- guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
+ crtc_state->vrr.guardband =
+ crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
+
+ if (DISPLAY_VER(display) < 13) {
+ /* FIXME handle the limit in a proper way */
+ crtc_state->vrr.guardband =
+ min(crtc_state->vrr.guardband,
+ intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
- if (DISPLAY_VER(display) >= 13) {
- crtc_state->vrr.guardband = guardband;
- } else {
crtc_state->vrr.pipeline_full =
- min(255, intel_vrr_guardband_to_pipeline_full(crtc_state, guardband));
+ intel_vrr_guardband_to_pipeline_full(crtc_state,
+ crtc_state->vrr.guardband);
/*
* vmin/vmax/flipline also need to be adjusted by
@@ -734,14 +732,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
TRANS_CMRR_M_HI(display, cpu_transcoder));
}
- if (DISPLAY_VER(display) >= 13)
+ if (DISPLAY_VER(display) >= 13) {
crtc_state->vrr.guardband =
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
- else
- if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
+ } else {
+ if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) {
crtc_state->vrr.pipeline_full =
REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
+ crtc_state->vrr.guardband =
+ intel_vrr_pipeline_full_to_guardband(crtc_state,
+ crtc_state->vrr.pipeline_full);
+ }
+ }
+
if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
crtc_state->vrr.flipline = intel_de_read(display,
TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl
2025-09-17 20:34 ` [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl Ville Syrjala
@ 2025-09-18 9:37 ` Nautiyal, Ankit K
2025-09-18 12:21 ` Ville Syrjälä
2025-09-18 18:00 ` Nautiyal, Ankit K
1 sibling, 1 reply; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-18 9:37 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On 9/18/2025 2:04 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> While ICL/TGL VRR hardware doesn't have a register for the guardband
> value, our lives will be simpler if we pretend that it does. Start
> by computing the guardband the same as on ADL+ and storing it in
> the state, and only then we convert it into the corresponding
> pipeline_full value that the hardware can consume. During readout we
> do the opposite.
>
> I was debating whether to completely remove pipeline_full from the
> crtc state, but decided to keep it for now. Mainly because we check
> it in vrr_params_changed() and simply checking the guardband instead
> isn't 100% equivalent; Theoretically, framestart_delay may have
> changed in the opposite direction to pipeline_full, keeping the
> derived guardband value unchaged. One solution would be to also check
> framestart_delay, but that feels a bit leaky abstraction wise.
>
> Also note that we don't currently handle the maximum limit of 255
> scanlines for the pipeline_full in a very nice way. The actual
> position of the delayed vblank will move because of that clamping,
> and so some of our code may get confused. But fixing this shall
> wait a for now.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 36 +++++++++++---------
> 2 files changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c7d85fd38890..f4124c79bc83 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3891,6 +3891,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> intel_joiner_get_config(pipe_config);
> intel_dsc_get_config(pipe_config);
>
> + /* intel_vrr_get_config() depends on .framestart_delay */
> if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5fee85b0bc99..9cdcc2558ead 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -151,13 +151,7 @@ static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *c
> */
> static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_display *display = to_intel_display(crtc_state);
> -
> - if (DISPLAY_VER(display) >= 13)
> - return crtc_state->vrr.guardband;
> - else
> - return intel_vrr_pipeline_full_to_guardband(crtc_state,
> - crtc_state->vrr.pipeline_full);
> + return crtc_state->vrr.guardband;
> }
>
> int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
> @@ -431,18 +425,22 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> - int guardband;
>
> if (!intel_vrr_possible(crtc_state))
> return;
>
> - guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
> + crtc_state->vrr.guardband =
> + crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
> +
> + if (DISPLAY_VER(display) < 13) {
> + /* FIXME handle the limit in a proper way */
> + crtc_state->vrr.guardband =
> + min(crtc_state->vrr.guardband,
> + intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
>
> - if (DISPLAY_VER(display) >= 13) {
> - crtc_state->vrr.guardband = guardband;
> - } else {
> crtc_state->vrr.pipeline_full =
> - min(255, intel_vrr_guardband_to_pipeline_full(crtc_state, guardband));
> + intel_vrr_guardband_to_pipeline_full(crtc_state,
> + crtc_state->vrr.guardband);
For removing the #FIXME to handle the limit what can be required:
Do we need to abstract it with intel_vrr_clamp_pipeline_full() or else
we need:
crtc_state->vrr.pipeline_full = min(255,
intel_vrr_guardband_to_pipeline_full(crtc_state,
crtc_state->vrr.guardband));
crtc_state->vrr.guardband =
intel_vrr_guardband_to_pipeline_full(crtc_state,
crtc_state->vrr.pipeline_full);
(Though this might be bit confusing since we use guardband to get
pipline and again change guardband.)
Regards,
Ankit
>
> /*
> * vmin/vmax/flipline also need to be adjusted by
> @@ -734,14 +732,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> TRANS_CMRR_M_HI(display, cpu_transcoder));
> }
>
> - if (DISPLAY_VER(display) >= 13)
> + if (DISPLAY_VER(display) >= 13) {
> crtc_state->vrr.guardband =
> REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
> - else
> - if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
> + } else {
> + if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) {
> crtc_state->vrr.pipeline_full =
> REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
>
> + crtc_state->vrr.guardband =
> + intel_vrr_pipeline_full_to_guardband(crtc_state,
> + crtc_state->vrr.pipeline_full);
> + }
> + }
> +
> if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
> crtc_state->vrr.flipline = intel_de_read(display,
> TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl
2025-09-18 9:37 ` Nautiyal, Ankit K
@ 2025-09-18 12:21 ` Ville Syrjälä
2025-09-18 13:59 ` Nautiyal, Ankit K
0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2025-09-18 12:21 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe
On Thu, Sep 18, 2025 at 03:07:20PM +0530, Nautiyal, Ankit K wrote:
>
> On 9/18/2025 2:04 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > While ICL/TGL VRR hardware doesn't have a register for the guardband
> > value, our lives will be simpler if we pretend that it does. Start
> > by computing the guardband the same as on ADL+ and storing it in
> > the state, and only then we convert it into the corresponding
> > pipeline_full value that the hardware can consume. During readout we
> > do the opposite.
> >
> > I was debating whether to completely remove pipeline_full from the
> > crtc state, but decided to keep it for now. Mainly because we check
> > it in vrr_params_changed() and simply checking the guardband instead
> > isn't 100% equivalent; Theoretically, framestart_delay may have
> > changed in the opposite direction to pipeline_full, keeping the
> > derived guardband value unchaged. One solution would be to also check
> > framestart_delay, but that feels a bit leaky abstraction wise.
> >
> > Also note that we don't currently handle the maximum limit of 255
> > scanlines for the pipeline_full in a very nice way. The actual
> > position of the delayed vblank will move because of that clamping,
> > and so some of our code may get confused. But fixing this shall
> > wait a for now.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > drivers/gpu/drm/i915/display/intel_vrr.c | 36 +++++++++++---------
> > 2 files changed, 21 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index c7d85fd38890..f4124c79bc83 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3891,6 +3891,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > intel_joiner_get_config(pipe_config);
> > intel_dsc_get_config(pipe_config);
> >
> > + /* intel_vrr_get_config() depends on .framestart_delay */
> > if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> > tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 5fee85b0bc99..9cdcc2558ead 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -151,13 +151,7 @@ static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *c
> > */
> > static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
> > {
> > - struct intel_display *display = to_intel_display(crtc_state);
> > -
> > - if (DISPLAY_VER(display) >= 13)
> > - return crtc_state->vrr.guardband;
> > - else
> > - return intel_vrr_pipeline_full_to_guardband(crtc_state,
> > - crtc_state->vrr.pipeline_full);
> > + return crtc_state->vrr.guardband;
> > }
> >
> > int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
> > @@ -431,18 +425,22 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> > - int guardband;
> >
> > if (!intel_vrr_possible(crtc_state))
> > return;
> >
> > - guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
> > + crtc_state->vrr.guardband =
> > + crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
> > +
> > + if (DISPLAY_VER(display) < 13) {
> > + /* FIXME handle the limit in a proper way */
> > + crtc_state->vrr.guardband =
> > + min(crtc_state->vrr.guardband,
> > + intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
> >
> > - if (DISPLAY_VER(display) >= 13) {
> > - crtc_state->vrr.guardband = guardband;
> > - } else {
> > crtc_state->vrr.pipeline_full =
> > - min(255, intel_vrr_guardband_to_pipeline_full(crtc_state, guardband));
> > + intel_vrr_guardband_to_pipeline_full(crtc_state,
> > + crtc_state->vrr.guardband);
>
>
> For removing the #FIXME to handle the limit what can be required:
>
> Do we need to abstract it with intel_vrr_clamp_pipeline_full() or else
> we need:
I haven't though in detail how we should do this, but basically we
have two constraints that limit the max guardband:
- actual vblank_length-SCL
- hardware register limit (~255 for icl/tgl, (apparently)
65535 for for adl+)
So when calculating the guardband we just have to clamp it
the minimum of those.
>
> crtc_state->vrr.pipeline_full = min(255,
> intel_vrr_guardband_to_pipeline_full(crtc_state,
> crtc_state->vrr.guardband));
>
> crtc_state->vrr.guardband =
> intel_vrr_guardband_to_pipeline_full(crtc_state,
> crtc_state->vrr.pipeline_full);
>
> (Though this might be bit confusing since we use guardband to get
> pipline and again change guardband.)
>
>
> Regards,
>
> Ankit
>
>
> >
> > /*
> > * vmin/vmax/flipline also need to be adjusted by
> > @@ -734,14 +732,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> > TRANS_CMRR_M_HI(display, cpu_transcoder));
> > }
> >
> > - if (DISPLAY_VER(display) >= 13)
> > + if (DISPLAY_VER(display) >= 13) {
> > crtc_state->vrr.guardband =
> > REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
> > - else
> > - if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
> > + } else {
> > + if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) {
> > crtc_state->vrr.pipeline_full =
> > REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
> >
> > + crtc_state->vrr.guardband =
> > + intel_vrr_pipeline_full_to_guardband(crtc_state,
> > + crtc_state->vrr.pipeline_full);
> > + }
> > + }
> > +
> > if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
> > crtc_state->vrr.flipline = intel_de_read(display,
> > TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl
2025-09-18 12:21 ` Ville Syrjälä
@ 2025-09-18 13:59 ` Nautiyal, Ankit K
0 siblings, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-18 13:59 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On 9/18/2025 5:51 PM, Ville Syrjälä wrote:
> On Thu, Sep 18, 2025 at 03:07:20PM +0530, Nautiyal, Ankit K wrote:
>> On 9/18/2025 2:04 AM, Ville Syrjala wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> While ICL/TGL VRR hardware doesn't have a register for the guardband
>>> value, our lives will be simpler if we pretend that it does. Start
>>> by computing the guardband the same as on ADL+ and storing it in
>>> the state, and only then we convert it into the corresponding
>>> pipeline_full value that the hardware can consume. During readout we
>>> do the opposite.
>>>
>>> I was debating whether to completely remove pipeline_full from the
>>> crtc state, but decided to keep it for now. Mainly because we check
>>> it in vrr_params_changed() and simply checking the guardband instead
>>> isn't 100% equivalent; Theoretically, framestart_delay may have
>>> changed in the opposite direction to pipeline_full, keeping the
>>> derived guardband value unchaged. One solution would be to also check
>>> framestart_delay, but that feels a bit leaky abstraction wise.
>>>
>>> Also note that we don't currently handle the maximum limit of 255
>>> scanlines for the pipeline_full in a very nice way. The actual
>>> position of the delayed vblank will move because of that clamping,
>>> and so some of our code may get confused. But fixing this shall
>>> wait a for now.
>>>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_display.c | 1 +
>>> drivers/gpu/drm/i915/display/intel_vrr.c | 36 +++++++++++---------
>>> 2 files changed, 21 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>> index c7d85fd38890..f4124c79bc83 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -3891,6 +3891,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>>> intel_joiner_get_config(pipe_config);
>>> intel_dsc_get_config(pipe_config);
>>>
>>> + /* intel_vrr_get_config() depends on .framestart_delay */
>>> if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
>>> tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> index 5fee85b0bc99..9cdcc2558ead 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> @@ -151,13 +151,7 @@ static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *c
>>> */
>>> static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
>>> {
>>> - struct intel_display *display = to_intel_display(crtc_state);
>>> -
>>> - if (DISPLAY_VER(display) >= 13)
>>> - return crtc_state->vrr.guardband;
>>> - else
>>> - return intel_vrr_pipeline_full_to_guardband(crtc_state,
>>> - crtc_state->vrr.pipeline_full);
>>> + return crtc_state->vrr.guardband;
>>> }
>>>
>>> int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
>>> @@ -431,18 +425,22 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>>> {
>>> struct intel_display *display = to_intel_display(crtc_state);
>>> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>>> - int guardband;
>>>
>>> if (!intel_vrr_possible(crtc_state))
>>> return;
>>>
>>> - guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
>>> + crtc_state->vrr.guardband =
>>> + crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
>>> +
>>> + if (DISPLAY_VER(display) < 13) {
>>> + /* FIXME handle the limit in a proper way */
>>> + crtc_state->vrr.guardband =
>>> + min(crtc_state->vrr.guardband,
>>> + intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
>>>
>>> - if (DISPLAY_VER(display) >= 13) {
>>> - crtc_state->vrr.guardband = guardband;
>>> - } else {
>>> crtc_state->vrr.pipeline_full =
>>> - min(255, intel_vrr_guardband_to_pipeline_full(crtc_state, guardband));
>>> + intel_vrr_guardband_to_pipeline_full(crtc_state,
>>> + crtc_state->vrr.guardband);
>>
>> For removing the #FIXME to handle the limit what can be required:
>>
>> Do we need to abstract it with intel_vrr_clamp_pipeline_full() or else
>> we need:
> I haven't though in detail how we should do this, but basically we
> have two constraints that limit the max guardband:
> - actual vblank_length-SCL
> - hardware register limit (~255 for icl/tgl, (apparently)
> 65535 for for adl+)
>
> So when calculating the guardband we just have to clamp it
> the minimum of those.
Ah ok. So something like:
max_guardband = min (pipeline_full_to_guardband(255), vblank_length - scl);
crtc_state->vrr.guardband = min(crtc_state->vrr.guardband, max_guardband);
So with the set_context_latency thing we can properly clamp this and
remove the #Fix me.
Regards,
Ankit
>
>> crtc_state->vrr.pipeline_full = min(255,
>> intel_vrr_guardband_to_pipeline_full(crtc_state,
>> crtc_state->vrr.guardband));
>>
>> crtc_state->vrr.guardband =
>> intel_vrr_guardband_to_pipeline_full(crtc_state,
>> crtc_state->vrr.pipeline_full);
>>
>> (Though this might be bit confusing since we use guardband to get
>> pipline and again change guardband.)
>>
>>
>> Regards,
>>
>> Ankit
>>
>>
>>>
>>> /*
>>> * vmin/vmax/flipline also need to be adjusted by
>>> @@ -734,14 +732,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>> TRANS_CMRR_M_HI(display, cpu_transcoder));
>>> }
>>>
>>> - if (DISPLAY_VER(display) >= 13)
>>> + if (DISPLAY_VER(display) >= 13) {
>>> crtc_state->vrr.guardband =
>>> REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
>>> - else
>>> - if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
>>> + } else {
>>> + if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) {
>>> crtc_state->vrr.pipeline_full =
>>> REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
>>>
>>> + crtc_state->vrr.guardband =
>>> + intel_vrr_pipeline_full_to_guardband(crtc_state,
>>> + crtc_state->vrr.pipeline_full);
>>> + }
>>> + }
>>> +
>>> if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
>>> crtc_state->vrr.flipline = intel_de_read(display,
>>> TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl
2025-09-17 20:34 ` [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl Ville Syrjala
2025-09-18 9:37 ` Nautiyal, Ankit K
@ 2025-09-18 18:00 ` Nautiyal, Ankit K
1 sibling, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-18 18:00 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On 9/18/2025 2:04 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> While ICL/TGL VRR hardware doesn't have a register for the guardband
> value, our lives will be simpler if we pretend that it does. Start
> by computing the guardband the same as on ADL+ and storing it in
> the state, and only then we convert it into the corresponding
> pipeline_full value that the hardware can consume. During readout we
> do the opposite.
>
> I was debating whether to completely remove pipeline_full from the
> crtc state, but decided to keep it for now. Mainly because we check
> it in vrr_params_changed() and simply checking the guardband instead
> isn't 100% equivalent; Theoretically, framestart_delay may have
> changed in the opposite direction to pipeline_full, keeping the
> derived guardband value unchaged. One solution would be to also check
> framestart_delay, but that feels a bit leaky abstraction wise.
>
> Also note that we don't currently handle the maximum limit of 255
> scanlines for the pipeline_full in a very nice way. The actual
> position of the delayed vblank will move because of that clamping,
> and so some of our code may get confused. But fixing this shall
> wait a for now.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 36 +++++++++++---------
> 2 files changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c7d85fd38890..f4124c79bc83 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3891,6 +3891,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> intel_joiner_get_config(pipe_config);
> intel_dsc_get_config(pipe_config);
>
> + /* intel_vrr_get_config() depends on .framestart_delay */
> if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
> tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5fee85b0bc99..9cdcc2558ead 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -151,13 +151,7 @@ static int intel_vrr_pipeline_full_to_guardband(const struct intel_crtc_state *c
> */
> static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_display *display = to_intel_display(crtc_state);
> -
> - if (DISPLAY_VER(display) >= 13)
> - return crtc_state->vrr.guardband;
> - else
> - return intel_vrr_pipeline_full_to_guardband(crtc_state,
> - crtc_state->vrr.pipeline_full);
> + return crtc_state->vrr.guardband;
> }
>
> int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
> @@ -431,18 +425,22 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> - int guardband;
>
> if (!intel_vrr_possible(crtc_state))
> return;
>
> - guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
> + crtc_state->vrr.guardband =
> + crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start;
> +
> + if (DISPLAY_VER(display) < 13) {
> + /* FIXME handle the limit in a proper way */
> + crtc_state->vrr.guardband =
> + min(crtc_state->vrr.guardband,
> + intel_vrr_pipeline_full_to_guardband(crtc_state, 255));
>
> - if (DISPLAY_VER(display) >= 13) {
> - crtc_state->vrr.guardband = guardband;
> - } else {
> crtc_state->vrr.pipeline_full =
> - min(255, intel_vrr_guardband_to_pipeline_full(crtc_state, guardband));
> + intel_vrr_guardband_to_pipeline_full(crtc_state,
> + crtc_state->vrr.guardband);
>
> /*
> * vmin/vmax/flipline also need to be adjusted by
> @@ -734,14 +732,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> TRANS_CMRR_M_HI(display, cpu_transcoder));
> }
>
> - if (DISPLAY_VER(display) >= 13)
> + if (DISPLAY_VER(display) >= 13) {
> crtc_state->vrr.guardband =
> REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
> - else
> - if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
> + } else {
> + if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE) {
> crtc_state->vrr.pipeline_full =
> REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
>
> + crtc_state->vrr.guardband =
> + intel_vrr_pipeline_full_to_guardband(crtc_state,
> + crtc_state->vrr.pipeline_full);
> + }
> + }
> +
> if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) {
> crtc_state->vrr.flipline = intel_de_read(display,
> TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1;
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 4/5] drm/i915/vrr: Annotate some functions with "hw"
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
` (2 preceding siblings ...)
2025-09-17 20:34 ` [PATCH 3/5] drm/i915/vrr: Store guardband in crtc state even for icl/tgl Ville Syrjala
@ 2025-09-17 20:34 ` Ville Syrjala
2025-09-18 9:41 ` Nautiyal, Ankit K
2025-09-17 20:34 ` [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper Ville Syrjala
` (3 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2025-09-17 20:34 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_vrr_fixed_rr_*() return values that have had the TGL
SCL adjustment applied to them. So we should indicate that these
values are only really useful when fed to the hardware. Add
a "_hw_" indicator to the function names to reflect that fact.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 9cdcc2558ead..71fb64c92165 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -263,7 +263,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
* Vtotal value.
*/
static
-int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
+int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
@@ -276,24 +276,24 @@ int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
}
static
-int intel_vrr_fixed_rr_vmax(const struct intel_crtc_state *crtc_state)
+int intel_vrr_fixed_rr_hw_vmax(const struct intel_crtc_state *crtc_state)
{
- return intel_vrr_fixed_rr_vtotal(crtc_state);
+ return intel_vrr_fixed_rr_hw_vtotal(crtc_state);
}
static
-int intel_vrr_fixed_rr_vmin(const struct intel_crtc_state *crtc_state)
+int intel_vrr_fixed_rr_hw_vmin(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- return intel_vrr_fixed_rr_vtotal(crtc_state) -
+ return intel_vrr_fixed_rr_hw_vtotal(crtc_state) -
intel_vrr_flipline_offset(display);
}
static
-int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state)
+int intel_vrr_fixed_rr_hw_flipline(const struct intel_crtc_state *crtc_state)
{
- return intel_vrr_fixed_rr_vtotal(crtc_state);
+ return intel_vrr_fixed_rr_hw_vtotal(crtc_state);
}
void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
@@ -305,11 +305,11 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
return;
intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
- intel_vrr_fixed_rr_vmin(crtc_state) - 1);
+ intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
- intel_vrr_fixed_rr_vmax(crtc_state) - 1);
+ intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
- intel_vrr_fixed_rr_flipline(crtc_state) - 1);
+ intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
}
static
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 4/5] drm/i915/vrr: Annotate some functions with "hw"
2025-09-17 20:34 ` [PATCH 4/5] drm/i915/vrr: Annotate some functions with "hw" Ville Syrjala
@ 2025-09-18 9:41 ` Nautiyal, Ankit K
0 siblings, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-18 9:41 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On 9/18/2025 2:04 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_vrr_fixed_rr_*() return values that have had the TGL
> SCL adjustment applied to them. So we should indicate that these
> values are only really useful when fed to the hardware. Add
> a "_hw_" indicator to the function names to reflect that fact.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 9cdcc2558ead..71fb64c92165 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -263,7 +263,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
> * Vtotal value.
> */
> static
> -int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
> +int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
> @@ -276,24 +276,24 @@ int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
> }
>
> static
> -int intel_vrr_fixed_rr_vmax(const struct intel_crtc_state *crtc_state)
> +int intel_vrr_fixed_rr_hw_vmax(const struct intel_crtc_state *crtc_state)
> {
> - return intel_vrr_fixed_rr_vtotal(crtc_state);
> + return intel_vrr_fixed_rr_hw_vtotal(crtc_state);
> }
>
> static
> -int intel_vrr_fixed_rr_vmin(const struct intel_crtc_state *crtc_state)
> +int intel_vrr_fixed_rr_hw_vmin(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
>
> - return intel_vrr_fixed_rr_vtotal(crtc_state) -
> + return intel_vrr_fixed_rr_hw_vtotal(crtc_state) -
> intel_vrr_flipline_offset(display);
> }
>
> static
> -int intel_vrr_fixed_rr_flipline(const struct intel_crtc_state *crtc_state)
> +int intel_vrr_fixed_rr_hw_flipline(const struct intel_crtc_state *crtc_state)
> {
> - return intel_vrr_fixed_rr_vtotal(crtc_state);
> + return intel_vrr_fixed_rr_hw_vtotal(crtc_state);
> }
>
> void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
> @@ -305,11 +305,11 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
> return;
>
> intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> - intel_vrr_fixed_rr_vmin(crtc_state) - 1);
> + intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
> intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> - intel_vrr_fixed_rr_vmax(crtc_state) - 1);
> + intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
> intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
> - intel_vrr_fixed_rr_flipline(crtc_state) - 1);
> + intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
> }
>
> static
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
` (3 preceding siblings ...)
2025-09-17 20:34 ` [PATCH 4/5] drm/i915/vrr: Annotate some functions with "hw" Ville Syrjala
@ 2025-09-17 20:34 ` Ville Syrjala
2025-09-18 9:33 ` Nautiyal, Ankit K
2025-09-17 20:48 ` ✓ CI.KUnit: success for drm/i915/vrr: Hide icl/tgl idiosyncrasies better Patchwork
` (2 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjala @ 2025-09-17 20:34 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently our crtc_state->vrr.{vmin.vmax,flipline} are mangled on
TGL to account for the SCL delay (the hardware requires this mangling
or the actual vtotals will become incorrect). Unfortunately this
means that one can't simply use these values directly in many places,
and instead we always have to go through functions that undo the
damage first. This is all rather fragile.
Simplify our lives a bit by hiding this mangling deeper inside
the low level VRR code, leaving the number stored in the crtc
state actually something that humans can use.
This does introduce a dependdency as intel_vrr_get_config()
will now need to know the SCL value, which is read out in
intel_get_transcoder_timings(). I suppose we could simply
duplicate the SCL readout in both places should this become
a real hinderance. For now just leave a note around the
intel_get_transcoder_timings() call to remind us.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++
drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++---------
2 files changed, 47 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f4124c79bc83..18b9baa96241 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3901,6 +3901,10 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
pipe_config->framestart_delay = 1;
}
+ /*
+ * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY
+ * readout done by intel_get_transcoder_timings().
+ */
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
DISPLAY_VER(display) >= 11)
intel_get_transcoder_timings(crtc, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 71fb64c92165..71a985d00604 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -156,25 +156,13 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
-
/* Min vblank actually determined by flipline */
- if (DISPLAY_VER(display) >= 13)
- return intel_vrr_vmin_flipline(crtc_state);
- else
- return intel_vrr_vmin_flipline(crtc_state) +
- intel_vrr_real_vblank_delay(crtc_state);
+ return intel_vrr_vmin_flipline(crtc_state);
}
int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
-
- if (DISPLAY_VER(display) >= 13)
- return crtc_state->vrr.vmax;
- else
- return crtc_state->vrr.vmax +
- intel_vrr_real_vblank_delay(crtc_state);
+ return crtc_state->vrr.vmax;
}
int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
@@ -258,6 +246,21 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
+static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
+ int value)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ /*
+ * On TGL vmin/vmax/flipline also need to be
+ * adjusted by the SCL to maintain correct vtotals.
+ */
+ if (DISPLAY_VER(display) >= 13)
+ return value;
+ else
+ return value - intel_vrr_real_vblank_delay(crtc_state);
+}
+
/*
* For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
* Vtotal value.
@@ -265,14 +268,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
static
int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
- int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
-
- if (DISPLAY_VER(display) >= 13)
- return crtc_vtotal;
- else
- return crtc_vtotal -
- intel_vrr_real_vblank_delay(crtc_state);
+ return intel_vrr_hw_value(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
}
static
@@ -441,14 +437,6 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
crtc_state->vrr.pipeline_full =
intel_vrr_guardband_to_pipeline_full(crtc_state,
crtc_state->vrr.guardband);
-
- /*
- * vmin/vmax/flipline also need to be adjusted by
- * the vblank delay to maintain correct vtotals.
- */
- crtc_state->vrr.vmin -= intel_vrr_real_vblank_delay(crtc_state);
- crtc_state->vrr.vmax -= intel_vrr_real_vblank_delay(crtc_state);
- crtc_state->vrr.flipline -= intel_vrr_real_vblank_delay(crtc_state);
}
}
@@ -607,6 +595,21 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
}
+static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
+{
+ return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin);
+}
+
+static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
+{
+ return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmax);
+}
+
+static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state)
+{
+ return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline);
+}
+
void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -616,11 +619,11 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
return;
intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
- crtc_state->vrr.vmin - 1);
+ intel_vrr_hw_vmin(crtc_state) - 1);
intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
- crtc_state->vrr.vmax - 1);
+ intel_vrr_hw_vmax(crtc_state) - 1);
intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
- crtc_state->vrr.flipline - 1);
+ intel_vrr_hw_flipline(crtc_state) - 1);
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
TRANS_PUSH_EN);
@@ -754,6 +757,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.vmin = intel_de_read(display,
TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
+ if (DISPLAY_VER(display) < 13) {
+ /* undo what intel_vrr_hw_value() does when writing the values */
+ crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
+ crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
+ crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
+ }
+
/*
* For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
* bits are not filled. Since for these platforms TRAN_VMIN is always
--
2.49.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper
2025-09-17 20:34 ` [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper Ville Syrjala
@ 2025-09-18 9:33 ` Nautiyal, Ankit K
2025-09-18 12:14 ` Ville Syrjälä
0 siblings, 1 reply; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-18 9:33 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: intel-xe
On 9/18/2025 2:04 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently our crtc_state->vrr.{vmin.vmax,flipline} are mangled on
> TGL to account for the SCL delay (the hardware requires this mangling
> or the actual vtotals will become incorrect).
Please correct me if I am wrong:
For display < 13 VRR hardware inserts one extra scanline just after
vactive. So we need to have flipline, vmax, vmin vtotal shifted by 1.
This is computed in intel_vrr_extra_vblank_delay()
For display < 13 hardware expects flipline >= vmin (so we add flipline +
1, not related to vblank delay.
For some platforms intel_psr_min_vblank_delay() of 1 is required so that
moves the vblank start with this amount. we can account for this delay
by intel_vrr_real_vblank_delay().
So for the SCL delay mentioned here should'nt we
use intel_vrr_extra_vblank_delay() in the computation below?
Regards,
Ankit
> Unfortunately this
> means that one can't simply use these values directly in many places,
> and instead we always have to go through functions that undo the
> damage first. This is all rather fragile.
>
> Simplify our lives a bit by hiding this mangling deeper inside
> the low level VRR code, leaving the number stored in the crtc
> state actually something that humans can use.
>
> This does introduce a dependdency as intel_vrr_get_config()
> will now need to know the SCL value, which is read out in
> intel_get_transcoder_timings(). I suppose we could simply
> duplicate the SCL readout in both places should this become
> a real hinderance. For now just leave a note around the
> intel_get_transcoder_timings() call to remind us.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++
> drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++---------
> 2 files changed, 47 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f4124c79bc83..18b9baa96241 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3901,6 +3901,10 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->framestart_delay = 1;
> }
>
> + /*
> + * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY
> + * readout done by intel_get_transcoder_timings().
> + */
> if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> DISPLAY_VER(display) >= 11)
> intel_get_transcoder_timings(crtc, pipe_config);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 71fb64c92165..71a985d00604 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -156,25 +156,13 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
>
> int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_display *display = to_intel_display(crtc_state);
> -
> /* Min vblank actually determined by flipline */
> - if (DISPLAY_VER(display) >= 13)
> - return intel_vrr_vmin_flipline(crtc_state);
> - else
> - return intel_vrr_vmin_flipline(crtc_state) +
> - intel_vrr_real_vblank_delay(crtc_state);
> + return intel_vrr_vmin_flipline(crtc_state);
> }
>
> int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_display *display = to_intel_display(crtc_state);
> -
> - if (DISPLAY_VER(display) >= 13)
> - return crtc_state->vrr.vmax;
> - else
> - return crtc_state->vrr.vmax +
> - intel_vrr_real_vblank_delay(crtc_state);
> + return crtc_state->vrr.vmax;
> }
>
> int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
> @@ -258,6 +246,21 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> }
>
> +static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
> + int value)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + /*
> + * On TGL vmin/vmax/flipline also need to be
> + * adjusted by the SCL to maintain correct vtotals.
> + */
> + if (DISPLAY_VER(display) >= 13)
> + return value;
> + else
> + return value - intel_vrr_real_vblank_delay(crtc_state);
> +}
> +
> /*
> * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
> * Vtotal value.
> @@ -265,14 +268,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
> static
> int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state)
> {
> - struct intel_display *display = to_intel_display(crtc_state);
> - int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
> -
> - if (DISPLAY_VER(display) >= 13)
> - return crtc_vtotal;
> - else
> - return crtc_vtotal -
> - intel_vrr_real_vblank_delay(crtc_state);
> + return intel_vrr_hw_value(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
> }
>
> static
> @@ -441,14 +437,6 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> crtc_state->vrr.pipeline_full =
> intel_vrr_guardband_to_pipeline_full(crtc_state,
> crtc_state->vrr.guardband);
> -
> - /*
> - * vmin/vmax/flipline also need to be adjusted by
> - * the vblank delay to maintain correct vtotals.
> - */
> - crtc_state->vrr.vmin -= intel_vrr_real_vblank_delay(crtc_state);
> - crtc_state->vrr.vmax -= intel_vrr_real_vblank_delay(crtc_state);
> - crtc_state->vrr.flipline -= intel_vrr_real_vblank_delay(crtc_state);
> }
> }
>
> @@ -607,6 +595,21 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
> EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> }
>
> +static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
> +{
> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin);
> +}
> +
> +static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
> +{
> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmax);
> +}
> +
> +static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state)
> +{
> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline);
> +}
> +
> void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> @@ -616,11 +619,11 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> return;
>
> intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> - crtc_state->vrr.vmin - 1);
> + intel_vrr_hw_vmin(crtc_state) - 1);
> intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> - crtc_state->vrr.vmax - 1);
> + intel_vrr_hw_vmax(crtc_state) - 1);
> intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
> - crtc_state->vrr.flipline - 1);
> + intel_vrr_hw_flipline(crtc_state) - 1);
>
> intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> TRANS_PUSH_EN);
> @@ -754,6 +757,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> crtc_state->vrr.vmin = intel_de_read(display,
> TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
>
> + if (DISPLAY_VER(display) < 13) {
> + /* undo what intel_vrr_hw_value() does when writing the values */
> + crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
> + crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
> + crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
> + }
> +
> /*
> * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> * bits are not filled. Since for these platforms TRAN_VMIN is always
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper
2025-09-18 9:33 ` Nautiyal, Ankit K
@ 2025-09-18 12:14 ` Ville Syrjälä
2025-09-18 13:42 ` Nautiyal, Ankit K
0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2025-09-18 12:14 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe
On Thu, Sep 18, 2025 at 03:03:02PM +0530, Nautiyal, Ankit K wrote:
>
> On 9/18/2025 2:04 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Currently our crtc_state->vrr.{vmin.vmax,flipline} are mangled on
> > TGL to account for the SCL delay (the hardware requires this mangling
> > or the actual vtotals will become incorrect).
>
> Please correct me if I am wrong:
>
> For display < 13 VRR hardware inserts one extra scanline just after
> vactive. So we need to have flipline, vmax, vmin vtotal shifted by 1.
> This is computed in intel_vrr_extra_vblank_delay()
vmin/vmax/flipline stay put, but we need to account for that extra
scanline when calculating the guadband/pipeline_full.
>
> For display < 13 hardware expects flipline >= vmin (so we add flipline +
> 1, not related to vblank delay.
>
> For some platforms intel_psr_min_vblank_delay() of 1 is required so that
> moves the vblank start with this amount. we can account for this delay
> by intel_vrr_real_vblank_delay().
That 1 scaline is just the minimum size for SCL. And once we start
tracking the SCL explicitly then AFAICS pretty much all
intel_vrr_real_vblank_delay() calls can just be replaced with
crtc_state->set_context_latency.
>
> So for the SCL delay mentioned here should'nt we
> use intel_vrr_extra_vblank_delay() in the computation below?
I think we should be able to get rid of intel_vrr_extra_vblank_delay()
for the most part. As state we just need to account for it when
calculating the guardband/pipeline_full.
>
>
> Regards,
>
> Ankit
>
>
>
> > Unfortunately this
> > means that one can't simply use these values directly in many places,
> > and instead we always have to go through functions that undo the
> > damage first. This is all rather fragile.
> >
> > Simplify our lives a bit by hiding this mangling deeper inside
> > the low level VRR code, leaving the number stored in the crtc
> > state actually something that humans can use.
> >
> > This does introduce a dependdency as intel_vrr_get_config()
> > will now need to know the SCL value, which is read out in
> > intel_get_transcoder_timings(). I suppose we could simply
> > duplicate the SCL readout in both places should this become
> > a real hinderance. For now just leave a note around the
> > intel_get_transcoder_timings() call to remind us.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 4 ++
> > drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++---------
> > 2 files changed, 47 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f4124c79bc83..18b9baa96241 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3901,6 +3901,10 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> > pipe_config->framestart_delay = 1;
> > }
> >
> > + /*
> > + * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY
> > + * readout done by intel_get_transcoder_timings().
> > + */
> > if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> > DISPLAY_VER(display) >= 11)
> > intel_get_transcoder_timings(crtc, pipe_config);
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 71fb64c92165..71a985d00604 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -156,25 +156,13 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
> >
> > int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
> > {
> > - struct intel_display *display = to_intel_display(crtc_state);
> > -
> > /* Min vblank actually determined by flipline */
> > - if (DISPLAY_VER(display) >= 13)
> > - return intel_vrr_vmin_flipline(crtc_state);
> > - else
> > - return intel_vrr_vmin_flipline(crtc_state) +
> > - intel_vrr_real_vblank_delay(crtc_state);
> > + return intel_vrr_vmin_flipline(crtc_state);
> > }
> >
> > int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
> > {
> > - struct intel_display *display = to_intel_display(crtc_state);
> > -
> > - if (DISPLAY_VER(display) >= 13)
> > - return crtc_state->vrr.vmax;
> > - else
> > - return crtc_state->vrr.vmax +
> > - intel_vrr_real_vblank_delay(crtc_state);
> > + return crtc_state->vrr.vmax;
> > }
> >
> > int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
> > @@ -258,6 +246,21 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
> > crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> > }
> >
> > +static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
> > + int value)
> > +{
> > + struct intel_display *display = to_intel_display(crtc_state);
> > +
> > + /*
> > + * On TGL vmin/vmax/flipline also need to be
> > + * adjusted by the SCL to maintain correct vtotals.
> > + */
> > + if (DISPLAY_VER(display) >= 13)
> > + return value;
> > + else
> > + return value - intel_vrr_real_vblank_delay(crtc_state);
> > +}
> > +
> > /*
> > * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
> > * Vtotal value.
> > @@ -265,14 +268,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
> > static
> > int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state)
> > {
> > - struct intel_display *display = to_intel_display(crtc_state);
> > - int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
> > -
> > - if (DISPLAY_VER(display) >= 13)
> > - return crtc_vtotal;
> > - else
> > - return crtc_vtotal -
> > - intel_vrr_real_vblank_delay(crtc_state);
> > + return intel_vrr_hw_value(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
> > }
> >
> > static
> > @@ -441,14 +437,6 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> > crtc_state->vrr.pipeline_full =
> > intel_vrr_guardband_to_pipeline_full(crtc_state,
> > crtc_state->vrr.guardband);
> > -
> > - /*
> > - * vmin/vmax/flipline also need to be adjusted by
> > - * the vblank delay to maintain correct vtotals.
> > - */
> > - crtc_state->vrr.vmin -= intel_vrr_real_vblank_delay(crtc_state);
> > - crtc_state->vrr.vmax -= intel_vrr_real_vblank_delay(crtc_state);
> > - crtc_state->vrr.flipline -= intel_vrr_real_vblank_delay(crtc_state);
> > }
> > }
> >
> > @@ -607,6 +595,21 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
> > EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> > }
> >
> > +static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
> > +{
> > + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin);
> > +}
> > +
> > +static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
> > +{
> > + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmax);
> > +}
> > +
> > +static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state)
> > +{
> > + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline);
> > +}
> > +
> > void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> > {
> > struct intel_display *display = to_intel_display(crtc_state);
> > @@ -616,11 +619,11 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> > return;
> >
> > intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> > - crtc_state->vrr.vmin - 1);
> > + intel_vrr_hw_vmin(crtc_state) - 1);
> > intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> > - crtc_state->vrr.vmax - 1);
> > + intel_vrr_hw_vmax(crtc_state) - 1);
> > intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
> > - crtc_state->vrr.flipline - 1);
> > + intel_vrr_hw_flipline(crtc_state) - 1);
> >
> > intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> > TRANS_PUSH_EN);
> > @@ -754,6 +757,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> > crtc_state->vrr.vmin = intel_de_read(display,
> > TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
> >
> > + if (DISPLAY_VER(display) < 13) {
> > + /* undo what intel_vrr_hw_value() does when writing the values */
> > + crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
> > + crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
> > + crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
> > + }
> > +
> > /*
> > * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> > * bits are not filled. Since for these platforms TRAN_VMIN is always
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper
2025-09-18 12:14 ` Ville Syrjälä
@ 2025-09-18 13:42 ` Nautiyal, Ankit K
2025-09-18 14:18 ` Ville Syrjälä
0 siblings, 1 reply; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-18 13:42 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
[-- Attachment #1: Type: text/plain, Size: 9691 bytes --]
On 9/18/2025 5:44 PM, Ville Syrjälä wrote:
> On Thu, Sep 18, 2025 at 03:03:02PM +0530, Nautiyal, Ankit K wrote:
>> On 9/18/2025 2:04 AM, Ville Syrjala wrote:
>>> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>>
>>> Currently our crtc_state->vrr.{vmin.vmax,flipline} are mangled on
>>> TGL to account for the SCL delay (the hardware requires this mangling
>>> or the actual vtotals will become incorrect).
>> Please correct me if I am wrong:
>>
>> For display < 13 VRR hardware inserts one extra scanline just after
>> vactive. So we need to have flipline, vmax, vmin vtotal shifted by 1.
>> This is computed in intel_vrr_extra_vblank_delay()
> vmin/vmax/flipline stay put, but we need to account for that extra
> scanline when calculating the guadband/pipeline_full.
>
>> For display < 13 hardware expects flipline >= vmin (so we add flipline +
>> 1, not related to vblank delay.
>>
>> For some platforms intel_psr_min_vblank_delay() of 1 is required so that
>> moves the vblank start with this amount. we can account for this delay
>> by intel_vrr_real_vblank_delay().
> That 1 scaline is just the minimum size for SCL. And once we start
> tracking the SCL explicitly then AFAICS pretty much all
> intel_vrr_real_vblank_delay() calls can just be replaced with
> crtc_state->set_context_latency.
>
>> So for the SCL delay mentioned here should'nt we
>> use intel_vrr_extra_vblank_delay() in the computation below?
> I think we should be able to get rid of intel_vrr_extra_vblank_delay()
> for the most part. As state we just need to account for it when
> calculating the guardband/pipeline_full.
Hmm do you mean something like below:
void intel_vrr_compute_scl(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
int scl = 0; /*lines before delayed vblank */
if (!HAS_DSB(display))
return 0;
/*Account for 1 scanline thing for ICL/TGL */
scl = intel_vrr_extra_vblank_delay(display);
scl = max(scl, intel_psr_min_vblank_delay(crtc_state));
crtc_state->vrr.set_context_latency = scl;
}
And then in place of intel_vrr_real_vblank_delay() we can use the
crtc_state->vrr.set_context_latency.
Regards,
Ankit
>
>>
>> Regards,
>>
>> Ankit
>>
>>
>>
>>> Unfortunately this
>>> means that one can't simply use these values directly in many places,
>>> and instead we always have to go through functions that undo the
>>> damage first. This is all rather fragile.
>>>
>>> Simplify our lives a bit by hiding this mangling deeper inside
>>> the low level VRR code, leaving the number stored in the crtc
>>> state actually something that humans can use.
>>>
>>> This does introduce a dependdency as intel_vrr_get_config()
>>> will now need to know the SCL value, which is read out in
>>> intel_get_transcoder_timings(). I suppose we could simply
>>> duplicate the SCL readout in both places should this become
>>> a real hinderance. For now just leave a note around the
>>> intel_get_transcoder_timings() call to remind us.
>>>
>>> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_display.c | 4 ++
>>> drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++---------
>>> 2 files changed, 47 insertions(+), 33 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>> index f4124c79bc83..18b9baa96241 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -3901,6 +3901,10 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>>> pipe_config->framestart_delay = 1;
>>> }
>>>
>>> + /*
>>> + * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY
>>> + * readout done by intel_get_transcoder_timings().
>>> + */
>>> if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
>>> DISPLAY_VER(display) >= 11)
>>> intel_get_transcoder_timings(crtc, pipe_config);
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> index 71fb64c92165..71a985d00604 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> @@ -156,25 +156,13 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
>>>
>>> int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
>>> {
>>> - struct intel_display *display = to_intel_display(crtc_state);
>>> -
>>> /* Min vblank actually determined by flipline */
>>> - if (DISPLAY_VER(display) >= 13)
>>> - return intel_vrr_vmin_flipline(crtc_state);
>>> - else
>>> - return intel_vrr_vmin_flipline(crtc_state) +
>>> - intel_vrr_real_vblank_delay(crtc_state);
>>> + return intel_vrr_vmin_flipline(crtc_state);
>>> }
>>>
>>> int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
>>> {
>>> - struct intel_display *display = to_intel_display(crtc_state);
>>> -
>>> - if (DISPLAY_VER(display) >= 13)
>>> - return crtc_state->vrr.vmax;
>>> - else
>>> - return crtc_state->vrr.vmax +
>>> - intel_vrr_real_vblank_delay(crtc_state);
>>> + return crtc_state->vrr.vmax;
>>> }
>>>
>>> int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
>>> @@ -258,6 +246,21 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
>>> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>> }
>>>
>>> +static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
>>> + int value)
>>> +{
>>> + struct intel_display *display = to_intel_display(crtc_state);
>>> +
>>> + /*
>>> + * On TGL vmin/vmax/flipline also need to be
>>> + * adjusted by the SCL to maintain correct vtotals.
>>> + */
>>> + if (DISPLAY_VER(display) >= 13)
>>> + return value;
>>> + else
>>> + return value - intel_vrr_real_vblank_delay(crtc_state);
>>> +}
>>> +
>>> /*
>>> * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
>>> * Vtotal value.
>>> @@ -265,14 +268,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
>>> static
>>> int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state)
>>> {
>>> - struct intel_display *display = to_intel_display(crtc_state);
>>> - int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
>>> -
>>> - if (DISPLAY_VER(display) >= 13)
>>> - return crtc_vtotal;
>>> - else
>>> - return crtc_vtotal -
>>> - intel_vrr_real_vblank_delay(crtc_state);
>>> + return intel_vrr_hw_value(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
>>> }
>>>
>>> static
>>> @@ -441,14 +437,6 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>>> crtc_state->vrr.pipeline_full =
>>> intel_vrr_guardband_to_pipeline_full(crtc_state,
>>> crtc_state->vrr.guardband);
>>> -
>>> - /*
>>> - * vmin/vmax/flipline also need to be adjusted by
>>> - * the vblank delay to maintain correct vtotals.
>>> - */
>>> - crtc_state->vrr.vmin -= intel_vrr_real_vblank_delay(crtc_state);
>>> - crtc_state->vrr.vmax -= intel_vrr_real_vblank_delay(crtc_state);
>>> - crtc_state->vrr.flipline -= intel_vrr_real_vblank_delay(crtc_state);
>>> }
>>> }
>>>
>>> @@ -607,6 +595,21 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
>>> EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>>> }
>>>
>>> +static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
>>> +{
>>> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin);
>>> +}
>>> +
>>> +static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
>>> +{
>>> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmax);
>>> +}
>>> +
>>> +static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state)
>>> +{
>>> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline);
>>> +}
>>> +
>>> void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>>> {
>>> struct intel_display *display = to_intel_display(crtc_state);
>>> @@ -616,11 +619,11 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>>> return;
>>>
>>> intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
>>> - crtc_state->vrr.vmin - 1);
>>> + intel_vrr_hw_vmin(crtc_state) - 1);
>>> intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
>>> - crtc_state->vrr.vmax - 1);
>>> + intel_vrr_hw_vmax(crtc_state) - 1);
>>> intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
>>> - crtc_state->vrr.flipline - 1);
>>> + intel_vrr_hw_flipline(crtc_state) - 1);
>>>
>>> intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
>>> TRANS_PUSH_EN);
>>> @@ -754,6 +757,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>> crtc_state->vrr.vmin = intel_de_read(display,
>>> TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
>>>
>>> + if (DISPLAY_VER(display) < 13) {
>>> + /* undo what intel_vrr_hw_value() does when writing the values */
>>> + crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
>>> + crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
>>> + crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
>>> + }
>>> +
>>> /*
>>> * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
>>> * bits are not filled. Since for these platforms TRAN_VMIN is always
[-- Attachment #2: Type: text/html, Size: 11005 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper
2025-09-18 13:42 ` Nautiyal, Ankit K
@ 2025-09-18 14:18 ` Ville Syrjälä
2025-09-18 17:58 ` Nautiyal, Ankit K
0 siblings, 1 reply; 21+ messages in thread
From: Ville Syrjälä @ 2025-09-18 14:18 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx, intel-xe
On Thu, Sep 18, 2025 at 07:12:40PM +0530, Nautiyal, Ankit K wrote:
>
> On 9/18/2025 5:44 PM, Ville Syrjälä wrote:
> > On Thu, Sep 18, 2025 at 03:03:02PM +0530, Nautiyal, Ankit K wrote:
> >> On 9/18/2025 2:04 AM, Ville Syrjala wrote:
> >>> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
> >>>
> >>> Currently our crtc_state->vrr.{vmin.vmax,flipline} are mangled on
> >>> TGL to account for the SCL delay (the hardware requires this mangling
> >>> or the actual vtotals will become incorrect).
> >> Please correct me if I am wrong:
> >>
> >> For display < 13 VRR hardware inserts one extra scanline just after
> >> vactive. So we need to have flipline, vmax, vmin vtotal shifted by 1.
> >> This is computed in intel_vrr_extra_vblank_delay()
> > vmin/vmax/flipline stay put, but we need to account for that extra
> > scanline when calculating the guadband/pipeline_full.
> >
> >> For display < 13 hardware expects flipline >= vmin (so we add flipline +
> >> 1, not related to vblank delay.
> >>
> >> For some platforms intel_psr_min_vblank_delay() of 1 is required so that
> >> moves the vblank start with this amount. we can account for this delay
> >> by intel_vrr_real_vblank_delay().
> > That 1 scaline is just the minimum size for SCL. And once we start
> > tracking the SCL explicitly then AFAICS pretty much all
> > intel_vrr_real_vblank_delay() calls can just be replaced with
> > crtc_state->set_context_latency.
> >
> >> So for the SCL delay mentioned here should'nt we
> >> use intel_vrr_extra_vblank_delay() in the computation below?
> > I think we should be able to get rid of intel_vrr_extra_vblank_delay()
> > for the most part. As state we just need to account for it when
> > calculating the guardband/pipeline_full.
>
> Hmm do you mean something like below:
>
> void intel_vrr_compute_scl(struct intel_crtc_state *crtc_state)
I'd probably s/scl/set_context_latency/ to use consistent spelling
everywhere.
> {
> struct intel_display *display = to_intel_display(crtc_state);
> int scl = 0; /*lines before delayed vblank */
>
> if (!HAS_DSB(display))
> return 0;
>
> /*Account for 1 scanline thing for ICL/TGL */
> scl = intel_vrr_extra_vblank_delay(display);
We don't want to account for that here. It needs to be part
of the guardband calculation instead.
So basically the max guardband is actually
vblank_len-SCL-extra_vblank_delay.
>
> scl = max(scl, intel_psr_min_vblank_delay(crtc_state));
That PSR thing should probably also be renamed to ..._set_context_latency()
We might want to redesign that PSR part a bit at some point since
IIRC you don't actually need to use SCL here, and instead you can
just make sure the guardband doesn't take up the whole vblank,
when using the VRR timing generator. For the legacy timing generator
using SCL is the only option though. So I suppose we could avoid using
SCL here at least for the always_use_vrr_tg()==true cases. But we can
stick to SCL for now and revisit this later.
>
> crtc_state->vrr.set_context_latency = scl;
> }
>
> And then in place of intel_vrr_real_vblank_delay() we can use the
> crtc_state->vrr.set_context_latency.
>
> Regards,
>
> Ankit
>
>
> >
> >>
> >> Regards,
> >>
> >> Ankit
> >>
> >>
> >>
> >>> Unfortunately this
> >>> means that one can't simply use these values directly in many places,
> >>> and instead we always have to go through functions that undo the
> >>> damage first. This is all rather fragile.
> >>>
> >>> Simplify our lives a bit by hiding this mangling deeper inside
> >>> the low level VRR code, leaving the number stored in the crtc
> >>> state actually something that humans can use.
> >>>
> >>> This does introduce a dependdency as intel_vrr_get_config()
> >>> will now need to know the SCL value, which is read out in
> >>> intel_get_transcoder_timings(). I suppose we could simply
> >>> duplicate the SCL readout in both places should this become
> >>> a real hinderance. For now just leave a note around the
> >>> intel_get_transcoder_timings() call to remind us.
> >>>
> >>> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>
> >>> ---
> >>> drivers/gpu/drm/i915/display/intel_display.c | 4 ++
> >>> drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++---------
> >>> 2 files changed, 47 insertions(+), 33 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >>> index f4124c79bc83..18b9baa96241 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >>> @@ -3901,6 +3901,10 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
> >>> pipe_config->framestart_delay = 1;
> >>> }
> >>>
> >>> + /*
> >>> + * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY
> >>> + * readout done by intel_get_transcoder_timings().
> >>> + */
> >>> if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
> >>> DISPLAY_VER(display) >= 11)
> >>> intel_get_transcoder_timings(crtc, pipe_config);
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> >>> index 71fb64c92165..71a985d00604 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> >>> @@ -156,25 +156,13 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
> >>>
> >>> int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
> >>> {
> >>> - struct intel_display *display = to_intel_display(crtc_state);
> >>> -
> >>> /* Min vblank actually determined by flipline */
> >>> - if (DISPLAY_VER(display) >= 13)
> >>> - return intel_vrr_vmin_flipline(crtc_state);
> >>> - else
> >>> - return intel_vrr_vmin_flipline(crtc_state) +
> >>> - intel_vrr_real_vblank_delay(crtc_state);
> >>> + return intel_vrr_vmin_flipline(crtc_state);
> >>> }
> >>>
> >>> int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
> >>> {
> >>> - struct intel_display *display = to_intel_display(crtc_state);
> >>> -
> >>> - if (DISPLAY_VER(display) >= 13)
> >>> - return crtc_state->vrr.vmax;
> >>> - else
> >>> - return crtc_state->vrr.vmax +
> >>> - intel_vrr_real_vblank_delay(crtc_state);
> >>> + return crtc_state->vrr.vmax;
> >>> }
> >>>
> >>> int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
> >>> @@ -258,6 +246,21 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
> >>> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> >>> }
> >>>
> >>> +static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
> >>> + int value)
> >>> +{
> >>> + struct intel_display *display = to_intel_display(crtc_state);
> >>> +
> >>> + /*
> >>> + * On TGL vmin/vmax/flipline also need to be
> >>> + * adjusted by the SCL to maintain correct vtotals.
> >>> + */
> >>> + if (DISPLAY_VER(display) >= 13)
> >>> + return value;
> >>> + else
> >>> + return value - intel_vrr_real_vblank_delay(crtc_state);
> >>> +}
> >>> +
> >>> /*
> >>> * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
> >>> * Vtotal value.
> >>> @@ -265,14 +268,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
> >>> static
> >>> int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state)
> >>> {
> >>> - struct intel_display *display = to_intel_display(crtc_state);
> >>> - int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
> >>> -
> >>> - if (DISPLAY_VER(display) >= 13)
> >>> - return crtc_vtotal;
> >>> - else
> >>> - return crtc_vtotal -
> >>> - intel_vrr_real_vblank_delay(crtc_state);
> >>> + return intel_vrr_hw_value(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
> >>> }
> >>>
> >>> static
> >>> @@ -441,14 +437,6 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> >>> crtc_state->vrr.pipeline_full =
> >>> intel_vrr_guardband_to_pipeline_full(crtc_state,
> >>> crtc_state->vrr.guardband);
> >>> -
> >>> - /*
> >>> - * vmin/vmax/flipline also need to be adjusted by
> >>> - * the vblank delay to maintain correct vtotals.
> >>> - */
> >>> - crtc_state->vrr.vmin -= intel_vrr_real_vblank_delay(crtc_state);
> >>> - crtc_state->vrr.vmax -= intel_vrr_real_vblank_delay(crtc_state);
> >>> - crtc_state->vrr.flipline -= intel_vrr_real_vblank_delay(crtc_state);
> >>> }
> >>> }
> >>>
> >>> @@ -607,6 +595,21 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
> >>> EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> >>> }
> >>>
> >>> +static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
> >>> +{
> >>> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin);
> >>> +}
> >>> +
> >>> +static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
> >>> +{
> >>> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmax);
> >>> +}
> >>> +
> >>> +static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state)
> >>> +{
> >>> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline);
> >>> +}
> >>> +
> >>> void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> >>> {
> >>> struct intel_display *display = to_intel_display(crtc_state);
> >>> @@ -616,11 +619,11 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> >>> return;
> >>>
> >>> intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> >>> - crtc_state->vrr.vmin - 1);
> >>> + intel_vrr_hw_vmin(crtc_state) - 1);
> >>> intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> >>> - crtc_state->vrr.vmax - 1);
> >>> + intel_vrr_hw_vmax(crtc_state) - 1);
> >>> intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
> >>> - crtc_state->vrr.flipline - 1);
> >>> + intel_vrr_hw_flipline(crtc_state) - 1);
> >>>
> >>> intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> >>> TRANS_PUSH_EN);
> >>> @@ -754,6 +757,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> >>> crtc_state->vrr.vmin = intel_de_read(display,
> >>> TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
> >>>
> >>> + if (DISPLAY_VER(display) < 13) {
> >>> + /* undo what intel_vrr_hw_value() does when writing the values */
> >>> + crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
> >>> + crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
> >>> + crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
> >>> + }
> >>> +
> >>> /*
> >>> * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> >>> * bits are not filled. Since for these platforms TRAN_VMIN is always
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper
2025-09-18 14:18 ` Ville Syrjälä
@ 2025-09-18 17:58 ` Nautiyal, Ankit K
0 siblings, 0 replies; 21+ messages in thread
From: Nautiyal, Ankit K @ 2025-09-18 17:58 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On 9/18/2025 7:48 PM, Ville Syrjälä wrote:
> On Thu, Sep 18, 2025 at 07:12:40PM +0530, Nautiyal, Ankit K wrote:
>> On 9/18/2025 5:44 PM, Ville Syrjälä wrote:
>>> On Thu, Sep 18, 2025 at 03:03:02PM +0530, Nautiyal, Ankit K wrote:
>>>> On 9/18/2025 2:04 AM, Ville Syrjala wrote:
>>>>> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>>>>
>>>>> Currently our crtc_state->vrr.{vmin.vmax,flipline} are mangled on
>>>>> TGL to account for the SCL delay (the hardware requires this mangling
>>>>> or the actual vtotals will become incorrect).
>>>> Please correct me if I am wrong:
>>>>
>>>> For display < 13 VRR hardware inserts one extra scanline just after
>>>> vactive. So we need to have flipline, vmax, vmin vtotal shifted by 1.
>>>> This is computed in intel_vrr_extra_vblank_delay()
>>> vmin/vmax/flipline stay put, but we need to account for that extra
>>> scanline when calculating the guadband/pipeline_full.
>>>
>>>> For display < 13 hardware expects flipline >= vmin (so we add flipline +
>>>> 1, not related to vblank delay.
>>>>
>>>> For some platforms intel_psr_min_vblank_delay() of 1 is required so that
>>>> moves the vblank start with this amount. we can account for this delay
>>>> by intel_vrr_real_vblank_delay().
>>> That 1 scaline is just the minimum size for SCL. And once we start
>>> tracking the SCL explicitly then AFAICS pretty much all
>>> intel_vrr_real_vblank_delay() calls can just be replaced with
>>> crtc_state->set_context_latency.
>>>
>>>> So for the SCL delay mentioned here should'nt we
>>>> use intel_vrr_extra_vblank_delay() in the computation below?
>>> I think we should be able to get rid of intel_vrr_extra_vblank_delay()
>>> for the most part. As state we just need to account for it when
>>> calculating the guardband/pipeline_full.
>> Hmm do you mean something like below:
>>
>> void intel_vrr_compute_scl(struct intel_crtc_state *crtc_state)
> I'd probably s/scl/set_context_latency/ to use consistent spelling
> everywhere.
Sure.
>
>> {
>> struct intel_display *display = to_intel_display(crtc_state);
>> int scl = 0; /*lines before delayed vblank */
>>
>> if (!HAS_DSB(display))
>> return 0;
>>
>> /*Account for 1 scanline thing for ICL/TGL */
>> scl = intel_vrr_extra_vblank_delay(display);
> We don't want to account for that here. It needs to be part
> of the guardband calculation instead.
>
> So basically the max guardband is actually
> vblank_len-SCL-extra_vblank_delay.
Alright, I think I got some idea now.
>
>> scl = max(scl, intel_psr_min_vblank_delay(crtc_state));
> That PSR thing should probably also be renamed to ..._set_context_latency()
>
> We might want to redesign that PSR part a bit at some point since
> IIRC you don't actually need to use SCL here, and instead you can
> just make sure the guardband doesn't take up the whole vblank,
> when using the VRR timing generator. For the legacy timing generator
> using SCL is the only option though. So I suppose we could avoid using
> SCL here at least for the always_use_vrr_tg()==true cases. But we can
> stick to SCL for now and revisit this later.
Thanks for the clarification.
Patch looks good to me.
nitpick: typo in subject s/manging/mangling
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
>> crtc_state->vrr.set_context_latency = scl;
>> }
>>
>> And then in place of intel_vrr_real_vblank_delay() we can use the
>> crtc_state->vrr.set_context_latency.
>>
>> Regards,
>>
>> Ankit
>>
>>
>>>> Regards,
>>>>
>>>> Ankit
>>>>
>>>>
>>>>
>>>>> Unfortunately this
>>>>> means that one can't simply use these values directly in many places,
>>>>> and instead we always have to go through functions that undo the
>>>>> damage first. This is all rather fragile.
>>>>>
>>>>> Simplify our lives a bit by hiding this mangling deeper inside
>>>>> the low level VRR code, leaving the number stored in the crtc
>>>>> state actually something that humans can use.
>>>>>
>>>>> This does introduce a dependdency as intel_vrr_get_config()
>>>>> will now need to know the SCL value, which is read out in
>>>>> intel_get_transcoder_timings(). I suppose we could simply
>>>>> duplicate the SCL readout in both places should this become
>>>>> a real hinderance. For now just leave a note around the
>>>>> intel_get_transcoder_timings() call to remind us.
>>>>>
>>>>> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/display/intel_display.c | 4 ++
>>>>> drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++---------
>>>>> 2 files changed, 47 insertions(+), 33 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>>>> index f4124c79bc83..18b9baa96241 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>>> @@ -3901,6 +3901,10 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>>>>> pipe_config->framestart_delay = 1;
>>>>> }
>>>>>
>>>>> + /*
>>>>> + * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY
>>>>> + * readout done by intel_get_transcoder_timings().
>>>>> + */
>>>>> if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
>>>>> DISPLAY_VER(display) >= 11)
>>>>> intel_get_transcoder_timings(crtc, pipe_config);
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>>>>> index 71fb64c92165..71a985d00604 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>>>> @@ -156,25 +156,13 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
>>>>>
>>>>> int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
>>>>> {
>>>>> - struct intel_display *display = to_intel_display(crtc_state);
>>>>> -
>>>>> /* Min vblank actually determined by flipline */
>>>>> - if (DISPLAY_VER(display) >= 13)
>>>>> - return intel_vrr_vmin_flipline(crtc_state);
>>>>> - else
>>>>> - return intel_vrr_vmin_flipline(crtc_state) +
>>>>> - intel_vrr_real_vblank_delay(crtc_state);
>>>>> + return intel_vrr_vmin_flipline(crtc_state);
>>>>> }
>>>>>
>>>>> int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
>>>>> {
>>>>> - struct intel_display *display = to_intel_display(crtc_state);
>>>>> -
>>>>> - if (DISPLAY_VER(display) >= 13)
>>>>> - return crtc_state->vrr.vmax;
>>>>> - else
>>>>> - return crtc_state->vrr.vmax +
>>>>> - intel_vrr_real_vblank_delay(crtc_state);
>>>>> + return crtc_state->vrr.vmax;
>>>>> }
>>>>>
>>>>> int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
>>>>> @@ -258,6 +246,21 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
>>>>> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>>>> }
>>>>>
>>>>> +static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
>>>>> + int value)
>>>>> +{
>>>>> + struct intel_display *display = to_intel_display(crtc_state);
>>>>> +
>>>>> + /*
>>>>> + * On TGL vmin/vmax/flipline also need to be
>>>>> + * adjusted by the SCL to maintain correct vtotals.
>>>>> + */
>>>>> + if (DISPLAY_VER(display) >= 13)
>>>>> + return value;
>>>>> + else
>>>>> + return value - intel_vrr_real_vblank_delay(crtc_state);
>>>>> +}
>>>>> +
>>>>> /*
>>>>> * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
>>>>> * Vtotal value.
>>>>> @@ -265,14 +268,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
>>>>> static
>>>>> int intel_vrr_fixed_rr_hw_vtotal(const struct intel_crtc_state *crtc_state)
>>>>> {
>>>>> - struct intel_display *display = to_intel_display(crtc_state);
>>>>> - int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
>>>>> -
>>>>> - if (DISPLAY_VER(display) >= 13)
>>>>> - return crtc_vtotal;
>>>>> - else
>>>>> - return crtc_vtotal -
>>>>> - intel_vrr_real_vblank_delay(crtc_state);
>>>>> + return intel_vrr_hw_value(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
>>>>> }
>>>>>
>>>>> static
>>>>> @@ -441,14 +437,6 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>>>>> crtc_state->vrr.pipeline_full =
>>>>> intel_vrr_guardband_to_pipeline_full(crtc_state,
>>>>> crtc_state->vrr.guardband);
>>>>> -
>>>>> - /*
>>>>> - * vmin/vmax/flipline also need to be adjusted by
>>>>> - * the vblank delay to maintain correct vtotals.
>>>>> - */
>>>>> - crtc_state->vrr.vmin -= intel_vrr_real_vblank_delay(crtc_state);
>>>>> - crtc_state->vrr.vmax -= intel_vrr_real_vblank_delay(crtc_state);
>>>>> - crtc_state->vrr.flipline -= intel_vrr_real_vblank_delay(crtc_state);
>>>>> }
>>>>> }
>>>>>
>>>>> @@ -607,6 +595,21 @@ void intel_vrr_set_db_point_and_transmission_line(const struct intel_crtc_state
>>>>> EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
>>>>> }
>>>>>
>>>>> +static int intel_vrr_hw_vmin(const struct intel_crtc_state *crtc_state)
>>>>> +{
>>>>> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmin);
>>>>> +}
>>>>> +
>>>>> +static int intel_vrr_hw_vmax(const struct intel_crtc_state *crtc_state)
>>>>> +{
>>>>> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.vmax);
>>>>> +}
>>>>> +
>>>>> +static int intel_vrr_hw_flipline(const struct intel_crtc_state *crtc_state)
>>>>> +{
>>>>> + return intel_vrr_hw_value(crtc_state, crtc_state->vrr.flipline);
>>>>> +}
>>>>> +
>>>>> void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>>>>> {
>>>>> struct intel_display *display = to_intel_display(crtc_state);
>>>>> @@ -616,11 +619,11 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>>>>> return;
>>>>>
>>>>> intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
>>>>> - crtc_state->vrr.vmin - 1);
>>>>> + intel_vrr_hw_vmin(crtc_state) - 1);
>>>>> intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
>>>>> - crtc_state->vrr.vmax - 1);
>>>>> + intel_vrr_hw_vmax(crtc_state) - 1);
>>>>> intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
>>>>> - crtc_state->vrr.flipline - 1);
>>>>> + intel_vrr_hw_flipline(crtc_state) - 1);
>>>>>
>>>>> intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
>>>>> TRANS_PUSH_EN);
>>>>> @@ -754,6 +757,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>>>> crtc_state->vrr.vmin = intel_de_read(display,
>>>>> TRANS_VRR_VMIN(display, cpu_transcoder)) + 1;
>>>>>
>>>>> + if (DISPLAY_VER(display) < 13) {
>>>>> + /* undo what intel_vrr_hw_value() does when writing the values */
>>>>> + crtc_state->vrr.flipline += intel_vrr_real_vblank_delay(crtc_state);
>>>>> + crtc_state->vrr.vmax += intel_vrr_real_vblank_delay(crtc_state);
>>>>> + crtc_state->vrr.vmin += intel_vrr_real_vblank_delay(crtc_state);
>>>>> + }
>>>>> +
>>>>> /*
>>>>> * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
>>>>> * bits are not filled. Since for these platforms TRAN_VMIN is always
^ permalink raw reply [flat|nested] 21+ messages in thread
* ✓ CI.KUnit: success for drm/i915/vrr: Hide icl/tgl idiosyncrasies better
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
` (4 preceding siblings ...)
2025-09-17 20:34 ` [PATCH 5/5] drm/i915/vrr: Move the TGL SCL manging of vmin/vmax/flipline deeper Ville Syrjala
@ 2025-09-17 20:48 ` Patchwork
2025-09-17 21:28 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-18 2:13 ` ✗ Xe.CI.Full: failure " Patchwork
7 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-09-17 20:48 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-xe
== Series Details ==
Series: drm/i915/vrr: Hide icl/tgl idiosyncrasies better
URL : https://patchwork.freedesktop.org/series/154669/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:46:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:46:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[20:47:34] Starting KUnit Kernel (1/1)...
[20:47:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:47:34] ================== guc_buf (11 subtests) ===================
[20:47:34] [PASSED] test_smallest
[20:47:34] [PASSED] test_largest
[20:47:34] [PASSED] test_granular
[20:47:34] [PASSED] test_unique
[20:47:34] [PASSED] test_overlap
[20:47:34] [PASSED] test_reusable
[20:47:34] [PASSED] test_too_big
[20:47:34] [PASSED] test_flush
[20:47:34] [PASSED] test_lookup
[20:47:34] [PASSED] test_data
[20:47:34] [PASSED] test_class
[20:47:34] ===================== [PASSED] guc_buf =====================
[20:47:34] =================== guc_dbm (7 subtests) ===================
[20:47:34] [PASSED] test_empty
[20:47:34] [PASSED] test_default
[20:47:34] ======================== test_size ========================
[20:47:34] [PASSED] 4
[20:47:34] [PASSED] 8
[20:47:34] [PASSED] 32
[20:47:34] [PASSED] 256
[20:47:34] ==================== [PASSED] test_size ====================
[20:47:34] ======================= test_reuse ========================
[20:47:34] [PASSED] 4
[20:47:34] [PASSED] 8
[20:47:34] [PASSED] 32
[20:47:34] [PASSED] 256
[20:47:34] =================== [PASSED] test_reuse ====================
[20:47:34] =================== test_range_overlap ====================
[20:47:34] [PASSED] 4
[20:47:34] [PASSED] 8
[20:47:34] [PASSED] 32
[20:47:34] [PASSED] 256
[20:47:34] =============== [PASSED] test_range_overlap ================
[20:47:34] =================== test_range_compact ====================
[20:47:34] [PASSED] 4
[20:47:34] [PASSED] 8
[20:47:34] [PASSED] 32
[20:47:34] [PASSED] 256
[20:47:34] =============== [PASSED] test_range_compact ================
[20:47:34] ==================== test_range_spare =====================
[20:47:34] [PASSED] 4
[20:47:34] [PASSED] 8
[20:47:34] [PASSED] 32
[20:47:34] [PASSED] 256
[20:47:34] ================ [PASSED] test_range_spare =================
[20:47:34] ===================== [PASSED] guc_dbm =====================
[20:47:34] =================== guc_idm (6 subtests) ===================
[20:47:34] [PASSED] bad_init
[20:47:34] [PASSED] no_init
[20:47:34] [PASSED] init_fini
[20:47:34] [PASSED] check_used
[20:47:34] [PASSED] check_quota
[20:47:34] [PASSED] check_all
[20:47:34] ===================== [PASSED] guc_idm =====================
[20:47:34] ================== no_relay (3 subtests) ===================
[20:47:34] [PASSED] xe_drops_guc2pf_if_not_ready
[20:47:34] [PASSED] xe_drops_guc2vf_if_not_ready
[20:47:34] [PASSED] xe_rejects_send_if_not_ready
[20:47:34] ==================== [PASSED] no_relay =====================
[20:47:34] ================== pf_relay (14 subtests) ==================
[20:47:34] [PASSED] pf_rejects_guc2pf_too_short
[20:47:34] [PASSED] pf_rejects_guc2pf_too_long
[20:47:34] [PASSED] pf_rejects_guc2pf_no_payload
[20:47:34] [PASSED] pf_fails_no_payload
[20:47:34] [PASSED] pf_fails_bad_origin
[20:47:34] [PASSED] pf_fails_bad_type
[20:47:34] [PASSED] pf_txn_reports_error
[20:47:34] [PASSED] pf_txn_sends_pf2guc
[20:47:34] [PASSED] pf_sends_pf2guc
[20:47:34] [SKIPPED] pf_loopback_nop
[20:47:34] [SKIPPED] pf_loopback_echo
[20:47:34] [SKIPPED] pf_loopback_fail
[20:47:34] [SKIPPED] pf_loopback_busy
[20:47:34] [SKIPPED] pf_loopback_retry
[20:47:34] ==================== [PASSED] pf_relay =====================
[20:47:34] ================== vf_relay (3 subtests) ===================
[20:47:34] [PASSED] vf_rejects_guc2vf_too_short
[20:47:34] [PASSED] vf_rejects_guc2vf_too_long
[20:47:34] [PASSED] vf_rejects_guc2vf_no_payload
[20:47:34] ==================== [PASSED] vf_relay =====================
[20:47:34] ===================== lmtt (1 subtest) =====================
[20:47:34] ======================== test_ops =========================
[20:47:34] [PASSED] 2-level
[20:47:34] [PASSED] multi-level
[20:47:34] ==================== [PASSED] test_ops =====================
[20:47:34] ====================== [PASSED] lmtt =======================
[20:47:34] ================= pf_service (11 subtests) =================
[20:47:34] [PASSED] pf_negotiate_any
[20:47:34] [PASSED] pf_negotiate_base_match
[20:47:34] [PASSED] pf_negotiate_base_newer
[20:47:34] [PASSED] pf_negotiate_base_next
[20:47:34] [SKIPPED] pf_negotiate_base_older
[20:47:34] [PASSED] pf_negotiate_base_prev
[20:47:34] [PASSED] pf_negotiate_latest_match
[20:47:34] [PASSED] pf_negotiate_latest_newer
[20:47:34] [PASSED] pf_negotiate_latest_next
[20:47:34] [SKIPPED] pf_negotiate_latest_older
[20:47:34] [SKIPPED] pf_negotiate_latest_prev
[20:47:34] =================== [PASSED] pf_service ====================
[20:47:34] ================= xe_guc_g2g (2 subtests) ==================
[20:47:34] ============== xe_live_guc_g2g_kunit_default ==============
[20:47:34] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:47:34] ============== xe_live_guc_g2g_kunit_allmem ===============
[20:47:34] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:47:34] =================== [SKIPPED] xe_guc_g2g ===================
[20:47:34] =================== xe_mocs (2 subtests) ===================
[20:47:34] ================ xe_live_mocs_kernel_kunit ================
[20:47:34] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:47:34] ================ xe_live_mocs_reset_kunit =================
[20:47:34] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:47:34] ==================== [SKIPPED] xe_mocs =====================
[20:47:34] ================= xe_migrate (2 subtests) ==================
[20:47:34] ================= xe_migrate_sanity_kunit =================
[20:47:34] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:47:34] ================== xe_validate_ccs_kunit ==================
[20:47:34] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:47:34] =================== [SKIPPED] xe_migrate ===================
[20:47:34] ================== xe_dma_buf (1 subtest) ==================
[20:47:34] ==================== xe_dma_buf_kunit =====================
[20:47:34] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:47:34] =================== [SKIPPED] xe_dma_buf ===================
[20:47:34] ================= xe_bo_shrink (1 subtest) =================
[20:47:34] =================== xe_bo_shrink_kunit ====================
[20:47:34] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:47:34] ================== [SKIPPED] xe_bo_shrink ==================
[20:47:34] ==================== xe_bo (2 subtests) ====================
[20:47:34] ================== xe_ccs_migrate_kunit ===================
[20:47:34] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:47:34] ==================== xe_bo_evict_kunit ====================
[20:47:34] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:47:34] ===================== [SKIPPED] xe_bo ======================
[20:47:34] ==================== args (11 subtests) ====================
[20:47:34] [PASSED] count_args_test
[20:47:34] [PASSED] call_args_example
[20:47:34] [PASSED] call_args_test
[20:47:34] [PASSED] drop_first_arg_example
[20:47:34] [PASSED] drop_first_arg_test
[20:47:34] [PASSED] first_arg_example
[20:47:34] [PASSED] first_arg_test
[20:47:34] [PASSED] last_arg_example
[20:47:34] [PASSED] last_arg_test
[20:47:34] [PASSED] pick_arg_example
[20:47:34] [PASSED] sep_comma_example
[20:47:34] ====================== [PASSED] args =======================
[20:47:34] =================== xe_pci (3 subtests) ====================
[20:47:34] ==================== check_graphics_ip ====================
[20:47:34] [PASSED] 12.00 Xe_LP
[20:47:34] [PASSED] 12.10 Xe_LP+
[20:47:34] [PASSED] 12.55 Xe_HPG
[20:47:34] [PASSED] 12.60 Xe_HPC
[20:47:34] [PASSED] 12.70 Xe_LPG
[20:47:34] [PASSED] 12.71 Xe_LPG
[20:47:34] [PASSED] 12.74 Xe_LPG+
[20:47:34] [PASSED] 20.01 Xe2_HPG
[20:47:34] [PASSED] 20.02 Xe2_HPG
[20:47:34] [PASSED] 20.04 Xe2_LPG
[20:47:34] [PASSED] 30.00 Xe3_LPG
[20:47:34] [PASSED] 30.01 Xe3_LPG
[20:47:34] [PASSED] 30.03 Xe3_LPG
[20:47:34] ================ [PASSED] check_graphics_ip ================
[20:47:34] ===================== check_media_ip ======================
[20:47:34] [PASSED] 12.00 Xe_M
[20:47:34] [PASSED] 12.55 Xe_HPM
[20:47:34] [PASSED] 13.00 Xe_LPM+
[20:47:34] [PASSED] 13.01 Xe2_HPM
[20:47:34] [PASSED] 20.00 Xe2_LPM
[20:47:34] [PASSED] 30.00 Xe3_LPM
[20:47:34] [PASSED] 30.02 Xe3_LPM
[20:47:34] ================= [PASSED] check_media_ip ==================
[20:47:34] ================= check_platform_gt_count =================
[20:47:34] [PASSED] 0x9A60 (TIGERLAKE)
[20:47:34] [PASSED] 0x9A68 (TIGERLAKE)
[20:47:34] [PASSED] 0x9A70 (TIGERLAKE)
[20:47:34] [PASSED] 0x9A40 (TIGERLAKE)
[20:47:34] [PASSED] 0x9A49 (TIGERLAKE)
[20:47:34] [PASSED] 0x9A59 (TIGERLAKE)
[20:47:34] [PASSED] 0x9A78 (TIGERLAKE)
[20:47:34] [PASSED] 0x9AC0 (TIGERLAKE)
[20:47:34] [PASSED] 0x9AC9 (TIGERLAKE)
[20:47:34] [PASSED] 0x9AD9 (TIGERLAKE)
[20:47:34] [PASSED] 0x9AF8 (TIGERLAKE)
[20:47:34] [PASSED] 0x4C80 (ROCKETLAKE)
[20:47:34] [PASSED] 0x4C8A (ROCKETLAKE)
[20:47:34] [PASSED] 0x4C8B (ROCKETLAKE)
[20:47:34] [PASSED] 0x4C8C (ROCKETLAKE)
[20:47:34] [PASSED] 0x4C90 (ROCKETLAKE)
[20:47:34] [PASSED] 0x4C9A (ROCKETLAKE)
[20:47:34] [PASSED] 0x4680 (ALDERLAKE_S)
[20:47:34] [PASSED] 0x4682 (ALDERLAKE_S)
[20:47:34] [PASSED] 0x4688 (ALDERLAKE_S)
[20:47:34] [PASSED] 0x468A (ALDERLAKE_S)
[20:47:34] [PASSED] 0x468B (ALDERLAKE_S)
[20:47:34] [PASSED] 0x4690 (ALDERLAKE_S)
[20:47:34] [PASSED] 0x4692 (ALDERLAKE_S)
[20:47:34] [PASSED] 0x4693 (ALDERLAKE_S)
[20:47:34] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46AA (ALDERLAKE_P)
[20:47:34] [PASSED] 0x462A (ALDERLAKE_P)
[20:47:34] [PASSED] 0x4626 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x4628 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46B0 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:47:34] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:47:34] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:47:34] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:47:34] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:47:34] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:47:34] [PASSED] 0xA721 (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA720 (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:47:34] [PASSED] 0xA780 (ALDERLAKE_S)
[20:47:34] [PASSED] 0xA781 (ALDERLAKE_S)
[20:47:34] [PASSED] 0xA782 (ALDERLAKE_S)
[20:47:34] [PASSED] 0xA783 (ALDERLAKE_S)
[20:47:34] [PASSED] 0xA788 (ALDERLAKE_S)
[20:47:34] [PASSED] 0xA789 (ALDERLAKE_S)
[20:47:34] [PASSED] 0xA78A (ALDERLAKE_S)
[20:47:34] [PASSED] 0xA78B (ALDERLAKE_S)
[20:47:34] [PASSED] 0x4905 (DG1)
[20:47:34] [PASSED] 0x4906 (DG1)
[20:47:34] [PASSED] 0x4907 (DG1)
[20:47:34] [PASSED] 0x4908 (DG1)
[20:47:34] [PASSED] 0x4909 (DG1)
[20:47:34] [PASSED] 0x56C0 (DG2)
[20:47:34] [PASSED] 0x56C2 (DG2)
[20:47:34] [PASSED] 0x56C1 (DG2)
[20:47:34] [PASSED] 0x7D51 (METEORLAKE)
[20:47:34] [PASSED] 0x7DD1 (METEORLAKE)
[20:47:34] [PASSED] 0x7D41 (METEORLAKE)
[20:47:34] [PASSED] 0x7D67 (METEORLAKE)
[20:47:34] [PASSED] 0xB640 (METEORLAKE)
[20:47:34] [PASSED] 0x56A0 (DG2)
[20:47:34] [PASSED] 0x56A1 (DG2)
[20:47:34] [PASSED] 0x56A2 (DG2)
[20:47:34] [PASSED] 0x56BE (DG2)
[20:47:34] [PASSED] 0x56BF (DG2)
[20:47:34] [PASSED] 0x5690 (DG2)
[20:47:34] [PASSED] 0x5691 (DG2)
[20:47:34] [PASSED] 0x5692 (DG2)
[20:47:34] [PASSED] 0x56A5 (DG2)
[20:47:34] [PASSED] 0x56A6 (DG2)
[20:47:34] [PASSED] 0x56B0 (DG2)
[20:47:34] [PASSED] 0x56B1 (DG2)
[20:47:34] [PASSED] 0x56BA (DG2)
[20:47:34] [PASSED] 0x56BB (DG2)
[20:47:34] [PASSED] 0x56BC (DG2)
[20:47:34] [PASSED] 0x56BD (DG2)
[20:47:34] [PASSED] 0x5693 (DG2)
[20:47:34] [PASSED] 0x5694 (DG2)
[20:47:34] [PASSED] 0x5695 (DG2)
[20:47:34] [PASSED] 0x56A3 (DG2)
[20:47:34] [PASSED] 0x56A4 (DG2)
[20:47:34] [PASSED] 0x56B2 (DG2)
[20:47:34] [PASSED] 0x56B3 (DG2)
[20:47:34] [PASSED] 0x5696 (DG2)
[20:47:34] [PASSED] 0x5697 (DG2)
[20:47:34] [PASSED] 0xB69 (PVC)
[20:47:34] [PASSED] 0xB6E (PVC)
[20:47:34] [PASSED] 0xBD4 (PVC)
[20:47:34] [PASSED] 0xBD5 (PVC)
[20:47:34] [PASSED] 0xBD6 (PVC)
[20:47:34] [PASSED] 0xBD7 (PVC)
[20:47:34] [PASSED] 0xBD8 (PVC)
[20:47:34] [PASSED] 0xBD9 (PVC)
[20:47:34] [PASSED] 0xBDA (PVC)
[20:47:34] [PASSED] 0xBDB (PVC)
[20:47:34] [PASSED] 0xBE0 (PVC)
[20:47:34] [PASSED] 0xBE1 (PVC)
[20:47:34] [PASSED] 0xBE5 (PVC)
[20:47:34] [PASSED] 0x7D40 (METEORLAKE)
[20:47:34] [PASSED] 0x7D45 (METEORLAKE)
[20:47:34] [PASSED] 0x7D55 (METEORLAKE)
[20:47:34] [PASSED] 0x7D60 (METEORLAKE)
[20:47:34] [PASSED] 0x7DD5 (METEORLAKE)
[20:47:34] [PASSED] 0x6420 (LUNARLAKE)
[20:47:34] [PASSED] 0x64A0 (LUNARLAKE)
[20:47:34] [PASSED] 0x64B0 (LUNARLAKE)
[20:47:34] [PASSED] 0xE202 (BATTLEMAGE)
[20:47:34] [PASSED] 0xE209 (BATTLEMAGE)
[20:47:34] [PASSED] 0xE20B (BATTLEMAGE)
[20:47:34] [PASSED] 0xE20C (BATTLEMAGE)
[20:47:34] [PASSED] 0xE20D (BATTLEMAGE)
[20:47:34] [PASSED] 0xE210 (BATTLEMAGE)
[20:47:34] [PASSED] 0xE211 (BATTLEMAGE)
[20:47:34] [PASSED] 0xE212 (BATTLEMAGE)
[20:47:34] [PASSED] 0xE216 (BATTLEMAGE)
[20:47:34] [PASSED] 0xE220 (BATTLEMAGE)
[20:47:34] [PASSED] 0xE221 (BATTLEMAGE)
[20:47:34] [PASSED] 0xE222 (BATTLEMAGE)
[20:47:34] [PASSED] 0xE223 (BATTLEMAGE)
[20:47:34] [PASSED] 0xB080 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB081 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB082 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB083 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB084 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB085 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB086 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB087 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB08F (PANTHERLAKE)
[20:47:34] [PASSED] 0xB090 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:47:34] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:47:34] [PASSED] 0xFD80 (PANTHERLAKE)
[20:47:34] [PASSED] 0xFD81 (PANTHERLAKE)
[20:47:34] ============= [PASSED] check_platform_gt_count =============
[20:47:34] ===================== [PASSED] xe_pci ======================
[20:47:34] =================== xe_rtp (2 subtests) ====================
[20:47:34] =============== xe_rtp_process_to_sr_tests ================
[20:47:34] [PASSED] coalesce-same-reg
[20:47:34] [PASSED] no-match-no-add
[20:47:34] [PASSED] match-or
[20:47:34] [PASSED] match-or-xfail
[20:47:34] [PASSED] no-match-no-add-multiple-rules
[20:47:34] [PASSED] two-regs-two-entries
[20:47:34] [PASSED] clr-one-set-other
[20:47:34] [PASSED] set-field
[20:47:34] [PASSED] conflict-duplicate
[20:47:34] [PASSED] conflict-not-disjoint
[20:47:34] [PASSED] conflict-reg-type
[20:47:34] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:47:34] ================== xe_rtp_process_tests ===================
[20:47:34] [PASSED] active1
[20:47:34] [PASSED] active2
[20:47:34] [PASSED] active-inactive
[20:47:34] [PASSED] inactive-active
[20:47:34] [PASSED] inactive-1st_or_active-inactive
[20:47:34] [PASSED] inactive-2nd_or_active-inactive
[20:47:34] [PASSED] inactive-last_or_active-inactive
[20:47:34] [PASSED] inactive-no_or_active-inactive
[20:47:34] ============== [PASSED] xe_rtp_process_tests ===============
[20:47:34] ===================== [PASSED] xe_rtp ======================
[20:47:34] ==================== xe_wa (1 subtest) =====================
[20:47:34] ======================== xe_wa_gt =========================
[20:47:34] [PASSED] TIGERLAKE B0
[20:47:34] [PASSED] DG1 A0
[20:47:34] [PASSED] DG1 B0
[20:47:34] [PASSED] ALDERLAKE_S A0
[20:47:34] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[20:47:34] [PASSED] ALDERLAKE_S C0
[20:47:34] [PASSED] ALDERLAKE_S D0
[20:47:34] [PASSED] ALDERLAKE_P A0
[20:47:34] [PASSED] ALDERLAKE_P B0
[20:47:34] [PASSED] ALDERLAKE_P C0
[20:47:34] [PASSED] ALDERLAKE_S RPLS D0
[20:47:34] [PASSED] ALDERLAKE_P RPLU E0
[20:47:34] [PASSED] DG2 G10 C0
[20:47:34] [PASSED] DG2 G11 B1
[20:47:34] [PASSED] DG2 G12 A1
[20:47:34] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:47:34] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:47:34] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:47:34] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:47:34] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:47:34] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:47:34] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:47:34] ==================== [PASSED] xe_wa_gt =====================
[20:47:34] ====================== [PASSED] xe_wa ======================
[20:47:34] ============================================================
[20:47:34] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[20:47:34] Elapsed time: 40.766s total, 4.349s configuring, 35.950s building, 0.410s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:47:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:47:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[20:48:05] Starting KUnit Kernel (1/1)...
[20:48:05] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:48:05] ============ drm_test_pick_cmdline (2 subtests) ============
[20:48:05] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:48:05] =============== drm_test_pick_cmdline_named ===============
[20:48:05] [PASSED] NTSC
[20:48:05] [PASSED] NTSC-J
[20:48:05] [PASSED] PAL
[20:48:05] [PASSED] PAL-M
[20:48:05] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:48:05] ============== [PASSED] drm_test_pick_cmdline ==============
[20:48:05] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:48:05] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:48:05] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:48:05] =========== drm_validate_clone_mode (2 subtests) ===========
[20:48:05] ============== drm_test_check_in_clone_mode ===============
[20:48:05] [PASSED] in_clone_mode
[20:48:05] [PASSED] not_in_clone_mode
[20:48:05] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:48:05] =============== drm_test_check_valid_clones ===============
[20:48:05] [PASSED] not_in_clone_mode
[20:48:05] [PASSED] valid_clone
[20:48:05] [PASSED] invalid_clone
[20:48:05] =========== [PASSED] drm_test_check_valid_clones ===========
[20:48:05] ============= [PASSED] drm_validate_clone_mode =============
[20:48:05] ============= drm_validate_modeset (1 subtest) =============
[20:48:05] [PASSED] drm_test_check_connector_changed_modeset
[20:48:05] ============== [PASSED] drm_validate_modeset ===============
[20:48:05] ====== drm_test_bridge_get_current_state (2 subtests) ======
[20:48:05] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:48:05] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[20:48:05] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:48:05] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:48:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:48:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:48:05] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[20:48:05] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:48:05] ============== drm_bridge_alloc (2 subtests) ===============
[20:48:05] [PASSED] drm_test_drm_bridge_alloc_basic
[20:48:05] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:48:05] ================ [PASSED] drm_bridge_alloc =================
[20:48:05] ================== drm_buddy (7 subtests) ==================
[20:48:05] [PASSED] drm_test_buddy_alloc_limit
[20:48:05] [PASSED] drm_test_buddy_alloc_optimistic
[20:48:05] [PASSED] drm_test_buddy_alloc_pessimistic
[20:48:05] [PASSED] drm_test_buddy_alloc_pathological
[20:48:05] [PASSED] drm_test_buddy_alloc_contiguous
[20:48:05] [PASSED] drm_test_buddy_alloc_clear
[20:48:05] [PASSED] drm_test_buddy_alloc_range_bias
[20:48:05] ==================== [PASSED] drm_buddy ====================
[20:48:05] ============= drm_cmdline_parser (40 subtests) =============
[20:48:05] [PASSED] drm_test_cmdline_force_d_only
[20:48:05] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:48:05] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:48:05] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:48:05] [PASSED] drm_test_cmdline_force_e_only
[20:48:05] [PASSED] drm_test_cmdline_res
[20:48:05] [PASSED] drm_test_cmdline_res_vesa
[20:48:05] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:48:05] [PASSED] drm_test_cmdline_res_rblank
[20:48:05] [PASSED] drm_test_cmdline_res_bpp
[20:48:05] [PASSED] drm_test_cmdline_res_refresh
[20:48:05] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:48:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:48:05] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:48:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:48:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:48:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:48:05] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:48:05] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:48:05] [PASSED] drm_test_cmdline_res_margins_force_on
[20:48:05] [PASSED] drm_test_cmdline_res_vesa_margins
[20:48:05] [PASSED] drm_test_cmdline_name
[20:48:05] [PASSED] drm_test_cmdline_name_bpp
[20:48:05] [PASSED] drm_test_cmdline_name_option
[20:48:05] [PASSED] drm_test_cmdline_name_bpp_option
[20:48:05] [PASSED] drm_test_cmdline_rotate_0
[20:48:05] [PASSED] drm_test_cmdline_rotate_90
[20:48:05] [PASSED] drm_test_cmdline_rotate_180
[20:48:05] [PASSED] drm_test_cmdline_rotate_270
[20:48:05] [PASSED] drm_test_cmdline_hmirror
[20:48:05] [PASSED] drm_test_cmdline_vmirror
[20:48:05] [PASSED] drm_test_cmdline_margin_options
[20:48:05] [PASSED] drm_test_cmdline_multiple_options
[20:48:05] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:48:05] [PASSED] drm_test_cmdline_extra_and_option
[20:48:05] [PASSED] drm_test_cmdline_freestanding_options
[20:48:05] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:48:05] [PASSED] drm_test_cmdline_panel_orientation
[20:48:05] ================ drm_test_cmdline_invalid =================
[20:48:05] [PASSED] margin_only
[20:48:05] [PASSED] interlace_only
[20:48:05] [PASSED] res_missing_x
[20:48:05] [PASSED] res_missing_y
[20:48:05] [PASSED] res_bad_y
[20:48:05] [PASSED] res_missing_y_bpp
[20:48:05] [PASSED] res_bad_bpp
[20:48:05] [PASSED] res_bad_refresh
[20:48:05] [PASSED] res_bpp_refresh_force_on_off
[20:48:05] [PASSED] res_invalid_mode
[20:48:05] [PASSED] res_bpp_wrong_place_mode
[20:48:05] [PASSED] name_bpp_refresh
[20:48:05] [PASSED] name_refresh
[20:48:05] [PASSED] name_refresh_wrong_mode
[20:48:05] [PASSED] name_refresh_invalid_mode
[20:48:05] [PASSED] rotate_multiple
[20:48:05] [PASSED] rotate_invalid_val
[20:48:05] [PASSED] rotate_truncated
[20:48:05] [PASSED] invalid_option
[20:48:05] [PASSED] invalid_tv_option
[20:48:05] [PASSED] truncated_tv_option
[20:48:05] ============ [PASSED] drm_test_cmdline_invalid =============
[20:48:05] =============== drm_test_cmdline_tv_options ===============
[20:48:05] [PASSED] NTSC
[20:48:05] [PASSED] NTSC_443
[20:48:05] [PASSED] NTSC_J
[20:48:05] [PASSED] PAL
[20:48:05] [PASSED] PAL_M
[20:48:05] [PASSED] PAL_N
[20:48:05] [PASSED] SECAM
[20:48:05] [PASSED] MONO_525
[20:48:05] [PASSED] MONO_625
[20:48:05] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:48:05] =============== [PASSED] drm_cmdline_parser ================
[20:48:05] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:48:05] [PASSED] drm_test_connector_hdmi_init_valid
[20:48:05] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:48:05] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:48:05] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:48:05] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:48:05] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:48:05] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:48:05] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:48:05] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:48:05] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:48:05] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:48:05] [PASSED] supported_formats=0x3 yuv420_allowed=1
[20:48:05] [PASSED] supported_formats=0x3 yuv420_allowed=0
[20:48:05] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:48:05] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:48:05] [PASSED] drm_test_connector_hdmi_init_null_product
[20:48:05] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:48:05] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:48:05] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:48:05] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:48:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:48:05] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:48:05] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:48:05] ========= drm_test_connector_hdmi_init_type_valid =========
[20:48:05] [PASSED] HDMI-A
[20:48:05] [PASSED] HDMI-B
[20:48:05] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:48:05] ======== drm_test_connector_hdmi_init_type_invalid ========
[20:48:05] [PASSED] Unknown
[20:48:05] [PASSED] VGA
[20:48:05] [PASSED] DVI-I
[20:48:05] [PASSED] DVI-D
[20:48:05] [PASSED] DVI-A
[20:48:05] [PASSED] Composite
[20:48:05] [PASSED] SVIDEO
[20:48:05] [PASSED] LVDS
[20:48:05] [PASSED] Component
[20:48:05] [PASSED] DIN
[20:48:05] [PASSED] DP
[20:48:05] [PASSED] TV
[20:48:05] [PASSED] eDP
[20:48:05] [PASSED] Virtual
[20:48:05] [PASSED] DSI
[20:48:05] [PASSED] DPI
[20:48:05] [PASSED] Writeback
[20:48:05] [PASSED] SPI
[20:48:05] [PASSED] USB
[20:48:05] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:48:05] ============ [PASSED] drmm_connector_hdmi_init =============
[20:48:05] ============= drmm_connector_init (3 subtests) =============
[20:48:05] [PASSED] drm_test_drmm_connector_init
[20:48:05] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:48:05] ========= drm_test_drmm_connector_init_type_valid =========
[20:48:05] [PASSED] Unknown
[20:48:05] [PASSED] VGA
[20:48:05] [PASSED] DVI-I
[20:48:05] [PASSED] DVI-D
[20:48:05] [PASSED] DVI-A
[20:48:05] [PASSED] Composite
[20:48:05] [PASSED] SVIDEO
[20:48:05] [PASSED] LVDS
[20:48:05] [PASSED] Component
[20:48:05] [PASSED] DIN
[20:48:05] [PASSED] DP
[20:48:05] [PASSED] HDMI-A
[20:48:05] [PASSED] HDMI-B
[20:48:05] [PASSED] TV
[20:48:05] [PASSED] eDP
[20:48:05] [PASSED] Virtual
[20:48:05] [PASSED] DSI
[20:48:05] [PASSED] DPI
[20:48:05] [PASSED] Writeback
[20:48:05] [PASSED] SPI
[20:48:05] [PASSED] USB
[20:48:05] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:48:05] =============== [PASSED] drmm_connector_init ===============
[20:48:05] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_init
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:48:05] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[20:48:05] [PASSED] Unknown
[20:48:05] [PASSED] VGA
[20:48:05] [PASSED] DVI-I
[20:48:05] [PASSED] DVI-D
[20:48:05] [PASSED] DVI-A
[20:48:05] [PASSED] Composite
[20:48:05] [PASSED] SVIDEO
[20:48:05] [PASSED] LVDS
[20:48:05] [PASSED] Component
[20:48:05] [PASSED] DIN
[20:48:05] [PASSED] DP
[20:48:05] [PASSED] HDMI-A
[20:48:05] [PASSED] HDMI-B
[20:48:05] [PASSED] TV
[20:48:05] [PASSED] eDP
[20:48:05] [PASSED] Virtual
[20:48:05] [PASSED] DSI
[20:48:05] [PASSED] DPI
[20:48:05] [PASSED] Writeback
[20:48:05] [PASSED] SPI
[20:48:05] [PASSED] USB
[20:48:05] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:48:05] ======== drm_test_drm_connector_dynamic_init_name =========
[20:48:05] [PASSED] Unknown
[20:48:05] [PASSED] VGA
[20:48:05] [PASSED] DVI-I
[20:48:05] [PASSED] DVI-D
[20:48:05] [PASSED] DVI-A
[20:48:05] [PASSED] Composite
[20:48:05] [PASSED] SVIDEO
[20:48:05] [PASSED] LVDS
[20:48:05] [PASSED] Component
[20:48:05] [PASSED] DIN
[20:48:05] [PASSED] DP
[20:48:05] [PASSED] HDMI-A
[20:48:05] [PASSED] HDMI-B
[20:48:05] [PASSED] TV
[20:48:05] [PASSED] eDP
[20:48:05] [PASSED] Virtual
[20:48:05] [PASSED] DSI
[20:48:05] [PASSED] DPI
[20:48:05] [PASSED] Writeback
[20:48:05] [PASSED] SPI
[20:48:05] [PASSED] USB
[20:48:05] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:48:05] =========== [PASSED] drm_connector_dynamic_init ============
[20:48:05] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:48:05] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:48:05] ======= drm_connector_dynamic_register (7 subtests) ========
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:48:05] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:48:05] ========= [PASSED] drm_connector_dynamic_register ==========
[20:48:05] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:48:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:48:05] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:48:05] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:48:05] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:48:05] ========== drm_test_get_tv_mode_from_name_valid ===========
[20:48:05] [PASSED] NTSC
[20:48:05] [PASSED] NTSC-443
[20:48:05] [PASSED] NTSC-J
[20:48:05] [PASSED] PAL
[20:48:05] [PASSED] PAL-M
[20:48:05] [PASSED] PAL-N
[20:48:05] [PASSED] SECAM
[20:48:05] [PASSED] Mono
[20:48:05] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:48:05] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:48:05] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:48:05] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:48:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:48:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:48:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:48:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:48:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:48:05] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:48:05] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[20:48:05] [PASSED] VIC 96
[20:48:05] [PASSED] VIC 97
[20:48:05] [PASSED] VIC 101
[20:48:05] [PASSED] VIC 102
[20:48:05] [PASSED] VIC 106
[20:48:05] [PASSED] VIC 107
[20:48:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:48:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:48:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:48:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:48:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:48:05] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:48:05] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:48:05] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:48:05] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[20:48:05] [PASSED] Automatic
[20:48:05] [PASSED] Full
[20:48:05] [PASSED] Limited 16:235
[20:48:05] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:48:05] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:48:05] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:48:05] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:48:05] === drm_test_drm_hdmi_connector_get_output_format_name ====
[20:48:05] [PASSED] RGB
[20:48:05] [PASSED] YUV 4:2:0
[20:48:05] [PASSED] YUV 4:2:2
[20:48:05] [PASSED] YUV 4:4:4
[20:48:05] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:48:05] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:48:05] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:48:05] ============= drm_damage_helper (21 subtests) ==============
[20:48:05] [PASSED] drm_test_damage_iter_no_damage
[20:48:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:48:05] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:48:05] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:48:05] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:48:05] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:48:05] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:48:05] [PASSED] drm_test_damage_iter_simple_damage
[20:48:05] [PASSED] drm_test_damage_iter_single_damage
[20:48:05] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:48:05] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:48:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:48:05] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:48:05] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:48:05] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:48:05] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:48:05] [PASSED] drm_test_damage_iter_damage
[20:48:05] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:48:05] [PASSED] drm_test_damage_iter_damage_one_outside
[20:48:05] [PASSED] drm_test_damage_iter_damage_src_moved
[20:48:05] [PASSED] drm_test_damage_iter_damage_not_visible
[20:48:05] ================ [PASSED] drm_damage_helper ================
[20:48:05] ============== drm_dp_mst_helper (3 subtests) ==============
[20:48:05] ============== drm_test_dp_mst_calc_pbn_mode ==============
[20:48:05] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:48:05] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:48:05] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:48:05] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:48:05] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:48:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:48:05] ============== drm_test_dp_mst_calc_pbn_div ===============
[20:48:05] [PASSED] Link rate 2000000 lane count 4
[20:48:05] [PASSED] Link rate 2000000 lane count 2
[20:48:05] [PASSED] Link rate 2000000 lane count 1
[20:48:05] [PASSED] Link rate 1350000 lane count 4
[20:48:05] [PASSED] Link rate 1350000 lane count 2
[20:48:05] [PASSED] Link rate 1350000 lane count 1
[20:48:05] [PASSED] Link rate 1000000 lane count 4
[20:48:05] [PASSED] Link rate 1000000 lane count 2
[20:48:05] [PASSED] Link rate 1000000 lane count 1
[20:48:05] [PASSED] Link rate 810000 lane count 4
[20:48:05] [PASSED] Link rate 810000 lane count 2
[20:48:05] [PASSED] Link rate 810000 lane count 1
[20:48:05] [PASSED] Link rate 540000 lane count 4
[20:48:05] [PASSED] Link rate 540000 lane count 2
[20:48:05] [PASSED] Link rate 540000 lane count 1
[20:48:05] [PASSED] Link rate 270000 lane count 4
[20:48:05] [PASSED] Link rate 270000 lane count 2
[20:48:05] [PASSED] Link rate 270000 lane count 1
[20:48:05] [PASSED] Link rate 162000 lane count 4
[20:48:05] [PASSED] Link rate 162000 lane count 2
[20:48:05] [PASSED] Link rate 162000 lane count 1
[20:48:05] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:48:05] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[20:48:05] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:48:05] [PASSED] DP_POWER_UP_PHY with port number
[20:48:05] [PASSED] DP_POWER_DOWN_PHY with port number
[20:48:05] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:48:05] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:48:05] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:48:05] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:48:05] [PASSED] DP_QUERY_PAYLOAD with port number
[20:48:05] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:48:05] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:48:05] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:48:05] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:48:05] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:48:05] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:48:05] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:48:05] [PASSED] DP_REMOTE_I2C_READ with port number
[20:48:05] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:48:05] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:48:05] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:48:05] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:48:05] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:48:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:48:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:48:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:48:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:48:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:48:05] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:48:05] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:48:05] ================ [PASSED] drm_dp_mst_helper ================
[20:48:05] ================== drm_exec (7 subtests) ===================
[20:48:05] [PASSED] sanitycheck
[20:48:05] [PASSED] test_lock
[20:48:05] [PASSED] test_lock_unlock
[20:48:05] [PASSED] test_duplicates
[20:48:05] [PASSED] test_prepare
[20:48:05] [PASSED] test_prepare_array
[20:48:05] [PASSED] test_multiple_loops
[20:48:05] ==================== [PASSED] drm_exec =====================
[20:48:05] =========== drm_format_helper_test (17 subtests) ===========
[20:48:05] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:48:05] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:48:05] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:48:05] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:48:05] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:48:05] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:48:05] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:48:05] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:48:05] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:48:05] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:48:05] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:48:05] ============== drm_test_fb_xrgb8888_to_mono ===============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:48:05] ==================== drm_test_fb_swab =====================
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ================ [PASSED] drm_test_fb_swab =================
[20:48:05] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:48:05] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[20:48:05] [PASSED] single_pixel_source_buffer
[20:48:05] [PASSED] single_pixel_clip_rectangle
[20:48:05] [PASSED] well_known_colors
[20:48:05] [PASSED] destination_pitch
[20:48:05] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:48:05] ================= drm_test_fb_clip_offset =================
[20:48:05] [PASSED] pass through
[20:48:05] [PASSED] horizontal offset
[20:48:05] [PASSED] vertical offset
[20:48:05] [PASSED] horizontal and vertical offset
[20:48:05] [PASSED] horizontal offset (custom pitch)
[20:48:05] [PASSED] vertical offset (custom pitch)
[20:48:05] [PASSED] horizontal and vertical offset (custom pitch)
[20:48:05] ============= [PASSED] drm_test_fb_clip_offset =============
[20:48:05] =================== drm_test_fb_memcpy ====================
[20:48:05] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:48:05] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:48:05] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:48:05] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:48:05] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:48:05] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:48:05] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:48:05] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:48:05] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:48:05] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:48:05] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:48:05] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:48:05] =============== [PASSED] drm_test_fb_memcpy ================
[20:48:05] ============= [PASSED] drm_format_helper_test ==============
[20:48:05] ================= drm_format (18 subtests) =================
[20:48:05] [PASSED] drm_test_format_block_width_invalid
[20:48:05] [PASSED] drm_test_format_block_width_one_plane
[20:48:05] [PASSED] drm_test_format_block_width_two_plane
[20:48:05] [PASSED] drm_test_format_block_width_three_plane
[20:48:05] [PASSED] drm_test_format_block_width_tiled
[20:48:05] [PASSED] drm_test_format_block_height_invalid
[20:48:05] [PASSED] drm_test_format_block_height_one_plane
[20:48:05] [PASSED] drm_test_format_block_height_two_plane
[20:48:05] [PASSED] drm_test_format_block_height_three_plane
[20:48:05] [PASSED] drm_test_format_block_height_tiled
[20:48:05] [PASSED] drm_test_format_min_pitch_invalid
[20:48:05] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:48:05] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:48:05] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:48:05] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:48:05] [PASSED] drm_test_format_min_pitch_two_plane
[20:48:05] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:48:05] [PASSED] drm_test_format_min_pitch_tiled
[20:48:05] =================== [PASSED] drm_format ====================
[20:48:05] ============== drm_framebuffer (10 subtests) ===============
[20:48:05] ========== drm_test_framebuffer_check_src_coords ==========
[20:48:05] [PASSED] Success: source fits into fb
[20:48:05] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:48:05] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:48:05] [PASSED] Fail: overflowing fb with source width
[20:48:05] [PASSED] Fail: overflowing fb with source height
[20:48:05] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:48:05] [PASSED] drm_test_framebuffer_cleanup
[20:48:05] =============== drm_test_framebuffer_create ===============
[20:48:05] [PASSED] ABGR8888 normal sizes
[20:48:05] [PASSED] ABGR8888 max sizes
[20:48:05] [PASSED] ABGR8888 pitch greater than min required
[20:48:05] [PASSED] ABGR8888 pitch less than min required
[20:48:05] [PASSED] ABGR8888 Invalid width
[20:48:05] [PASSED] ABGR8888 Invalid buffer handle
[20:48:05] [PASSED] No pixel format
[20:48:05] [PASSED] ABGR8888 Width 0
[20:48:05] [PASSED] ABGR8888 Height 0
[20:48:05] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:48:05] [PASSED] ABGR8888 Large buffer offset
[20:48:05] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:48:05] [PASSED] ABGR8888 Invalid flag
[20:48:05] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:48:05] [PASSED] ABGR8888 Valid buffer modifier
[20:48:05] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:48:05] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:48:05] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:48:05] [PASSED] NV12 Normal sizes
[20:48:05] [PASSED] NV12 Max sizes
[20:48:05] [PASSED] NV12 Invalid pitch
[20:48:05] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:48:05] [PASSED] NV12 different modifier per-plane
[20:48:05] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:48:05] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:48:05] [PASSED] NV12 Modifier for inexistent plane
[20:48:05] [PASSED] NV12 Handle for inexistent plane
[20:48:05] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:48:05] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:48:05] [PASSED] YVU420 Normal sizes
[20:48:05] [PASSED] YVU420 Max sizes
[20:48:05] [PASSED] YVU420 Invalid pitch
[20:48:05] [PASSED] YVU420 Different pitches
[20:48:05] [PASSED] YVU420 Different buffer offsets/pitches
[20:48:05] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:48:05] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:48:05] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:48:05] [PASSED] YVU420 Valid modifier
[20:48:05] [PASSED] YVU420 Different modifiers per plane
[20:48:05] [PASSED] YVU420 Modifier for inexistent plane
[20:48:05] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:48:05] [PASSED] X0L2 Normal sizes
[20:48:05] [PASSED] X0L2 Max sizes
[20:48:05] [PASSED] X0L2 Invalid pitch
[20:48:05] [PASSED] X0L2 Pitch greater than minimum required
[20:48:05] [PASSED] X0L2 Handle for inexistent plane
[20:48:05] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:48:05] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:48:05] [PASSED] X0L2 Valid modifier
[20:48:05] [PASSED] X0L2 Modifier for inexistent plane
[20:48:05] =========== [PASSED] drm_test_framebuffer_create ===========
[20:48:05] [PASSED] drm_test_framebuffer_free
[20:48:05] [PASSED] drm_test_framebuffer_init
[20:48:05] [PASSED] drm_test_framebuffer_init_bad_format
[20:48:05] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:48:05] [PASSED] drm_test_framebuffer_lookup
[20:48:05] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:48:05] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:48:05] ================= [PASSED] drm_framebuffer =================
[20:48:05] ================ drm_gem_shmem (8 subtests) ================
[20:48:05] [PASSED] drm_gem_shmem_test_obj_create
[20:48:05] [PASSED] drm_gem_shmem_test_obj_create_private
[20:48:05] [PASSED] drm_gem_shmem_test_pin_pages
[20:48:05] [PASSED] drm_gem_shmem_test_vmap
[20:48:05] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:48:05] [PASSED] drm_gem_shmem_test_get_sg_table
[20:48:05] [PASSED] drm_gem_shmem_test_madvise
[20:48:05] [PASSED] drm_gem_shmem_test_purge
[20:48:05] ================== [PASSED] drm_gem_shmem ==================
[20:48:05] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[20:48:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:48:05] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:48:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:48:05] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:48:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:48:05] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:48:05] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[20:48:05] [PASSED] Automatic
[20:48:05] [PASSED] Full
[20:48:05] [PASSED] Limited 16:235
[20:48:05] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:48:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:48:05] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:48:05] [PASSED] drm_test_check_disable_connector
[20:48:05] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:48:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:48:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:48:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:48:05] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:48:05] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:48:05] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:48:05] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:48:05] [PASSED] drm_test_check_output_bpc_dvi
[20:48:05] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:48:05] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:48:05] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:48:05] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:48:05] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:48:05] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:48:05] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:48:05] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:48:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:48:05] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:48:05] [PASSED] drm_test_check_broadcast_rgb_value
[20:48:05] [PASSED] drm_test_check_bpc_8_value
[20:48:05] [PASSED] drm_test_check_bpc_10_value
[20:48:05] [PASSED] drm_test_check_bpc_12_value
[20:48:05] [PASSED] drm_test_check_format_value
[20:48:05] [PASSED] drm_test_check_tmds_char_value
[20:48:05] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:48:05] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[20:48:05] [PASSED] drm_test_check_mode_valid
[20:48:05] [PASSED] drm_test_check_mode_valid_reject
[20:48:05] [PASSED] drm_test_check_mode_valid_reject_rate
[20:48:05] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:48:05] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:48:05] ================= drm_managed (2 subtests) =================
[20:48:05] [PASSED] drm_test_managed_release_action
[20:48:05] [PASSED] drm_test_managed_run_action
[20:48:05] =================== [PASSED] drm_managed ===================
[20:48:05] =================== drm_mm (6 subtests) ====================
[20:48:05] [PASSED] drm_test_mm_init
[20:48:05] [PASSED] drm_test_mm_debug
[20:48:05] [PASSED] drm_test_mm_align32
[20:48:05] [PASSED] drm_test_mm_align64
[20:48:05] [PASSED] drm_test_mm_lowest
[20:48:05] [PASSED] drm_test_mm_highest
[20:48:05] ===================== [PASSED] drm_mm ======================
[20:48:05] ============= drm_modes_analog_tv (5 subtests) =============
[20:48:05] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:48:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:48:05] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:48:05] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:48:05] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:48:05] =============== [PASSED] drm_modes_analog_tv ===============
[20:48:05] ============== drm_plane_helper (2 subtests) ===============
[20:48:05] =============== drm_test_check_plane_state ================
[20:48:05] [PASSED] clipping_simple
[20:48:05] [PASSED] clipping_rotate_reflect
[20:48:05] [PASSED] positioning_simple
[20:48:05] [PASSED] upscaling
[20:48:05] [PASSED] downscaling
[20:48:05] [PASSED] rounding1
[20:48:05] [PASSED] rounding2
[20:48:05] [PASSED] rounding3
[20:48:05] [PASSED] rounding4
[20:48:05] =========== [PASSED] drm_test_check_plane_state ============
[20:48:05] =========== drm_test_check_invalid_plane_state ============
[20:48:05] [PASSED] positioning_invalid
[20:48:05] [PASSED] upscaling_invalid
[20:48:05] [PASSED] downscaling_invalid
[20:48:05] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:48:05] ================ [PASSED] drm_plane_helper =================
[20:48:05] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:48:05] ====== drm_test_connector_helper_tv_get_modes_check =======
[20:48:05] [PASSED] None
[20:48:05] [PASSED] PAL
[20:48:05] [PASSED] NTSC
[20:48:05] [PASSED] Both, NTSC Default
[20:48:05] [PASSED] Both, PAL Default
[20:48:05] [PASSED] Both, NTSC Default, with PAL on command-line
[20:48:05] [PASSED] Both, PAL Default, with NTSC on command-line
[20:48:05] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:48:05] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:48:05] ================== drm_rect (9 subtests) ===================
[20:48:05] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:48:05] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:48:05] [PASSED] drm_test_rect_clip_scaled_clipped
[20:48:05] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:48:05] ================= drm_test_rect_intersect =================
[20:48:05] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:48:05] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:48:05] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:48:05] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:48:05] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:48:05] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:48:05] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:48:05] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:48:05] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:48:05] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:48:05] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:48:05] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:48:05] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:48:05] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:48:05] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:48:05] ============= [PASSED] drm_test_rect_intersect =============
[20:48:05] ================ drm_test_rect_calc_hscale ================
[20:48:05] [PASSED] normal use
[20:48:05] [PASSED] out of max range
[20:48:05] [PASSED] out of min range
[20:48:05] [PASSED] zero dst
[20:48:05] [PASSED] negative src
[20:48:05] [PASSED] negative dst
[20:48:05] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:48:05] ================ drm_test_rect_calc_vscale ================
[20:48:05] [PASSED] normal use
[20:48:05] [PASSED] out of max range
[20:48:05] [PASSED] out of min range
[20:48:05] [PASSED] zero dst
[20:48:05] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[20:48:05] [PASSED] negative dst
[20:48:05] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:48:05] ================== drm_test_rect_rotate ===================
[20:48:05] [PASSED] reflect-x
[20:48:05] [PASSED] reflect-y
[20:48:05] [PASSED] rotate-0
[20:48:05] [PASSED] rotate-90
[20:48:05] [PASSED] rotate-180
[20:48:05] [PASSED] rotate-270
[20:48:05] ============== [PASSED] drm_test_rect_rotate ===============
[20:48:05] ================ drm_test_rect_rotate_inv =================
[20:48:05] [PASSED] reflect-x
[20:48:05] [PASSED] reflect-y
[20:48:05] [PASSED] rotate-0
[20:48:05] [PASSED] rotate-90
[20:48:05] [PASSED] rotate-180
[20:48:05] [PASSED] rotate-270
[20:48:05] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:48:05] ==================== [PASSED] drm_rect =====================
[20:48:05] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:48:05] ============ drm_test_sysfb_build_fourcc_list =============
[20:48:05] [PASSED] no native formats
[20:48:05] [PASSED] XRGB8888 as native format
[20:48:05] [PASSED] remove duplicates
[20:48:05] [PASSED] convert alpha formats
[20:48:05] [PASSED] random formats
[20:48:05] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:48:05] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:48:05] ============================================================
[20:48:05] Testing complete. Ran 621 tests: passed: 621
[20:48:05] Elapsed time: 30.330s total, 1.778s configuring, 28.386s building, 0.144s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:48:05] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:48:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[20:48:15] Starting KUnit Kernel (1/1)...
[20:48:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:48:16] ================= ttm_device (5 subtests) ==================
[20:48:16] [PASSED] ttm_device_init_basic
[20:48:16] [PASSED] ttm_device_init_multiple
[20:48:16] [PASSED] ttm_device_fini_basic
[20:48:16] [PASSED] ttm_device_init_no_vma_man
[20:48:16] ================== ttm_device_init_pools ==================
[20:48:16] [PASSED] No DMA allocations, no DMA32 required
[20:48:16] [PASSED] DMA allocations, DMA32 required
[20:48:16] [PASSED] No DMA allocations, DMA32 required
[20:48:16] [PASSED] DMA allocations, no DMA32 required
[20:48:16] ============== [PASSED] ttm_device_init_pools ==============
[20:48:16] =================== [PASSED] ttm_device ====================
[20:48:16] ================== ttm_pool (8 subtests) ===================
[20:48:16] ================== ttm_pool_alloc_basic ===================
[20:48:16] [PASSED] One page
[20:48:16] [PASSED] More than one page
[20:48:16] [PASSED] Above the allocation limit
[20:48:16] [PASSED] One page, with coherent DMA mappings enabled
[20:48:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:48:16] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:48:16] ============== ttm_pool_alloc_basic_dma_addr ==============
[20:48:16] [PASSED] One page
[20:48:16] [PASSED] More than one page
[20:48:16] [PASSED] Above the allocation limit
[20:48:16] [PASSED] One page, with coherent DMA mappings enabled
[20:48:16] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:48:16] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:48:16] [PASSED] ttm_pool_alloc_order_caching_match
[20:48:16] [PASSED] ttm_pool_alloc_caching_mismatch
[20:48:16] [PASSED] ttm_pool_alloc_order_mismatch
[20:48:16] [PASSED] ttm_pool_free_dma_alloc
[20:48:16] [PASSED] ttm_pool_free_no_dma_alloc
[20:48:16] [PASSED] ttm_pool_fini_basic
[20:48:16] ==================== [PASSED] ttm_pool =====================
[20:48:16] ================ ttm_resource (8 subtests) =================
[20:48:16] ================= ttm_resource_init_basic =================
[20:48:16] [PASSED] Init resource in TTM_PL_SYSTEM
[20:48:16] [PASSED] Init resource in TTM_PL_VRAM
[20:48:16] [PASSED] Init resource in a private placement
[20:48:16] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:48:16] ============= [PASSED] ttm_resource_init_basic =============
[20:48:16] [PASSED] ttm_resource_init_pinned
[20:48:16] [PASSED] ttm_resource_fini_basic
[20:48:16] [PASSED] ttm_resource_manager_init_basic
[20:48:16] [PASSED] ttm_resource_manager_usage_basic
[20:48:16] [PASSED] ttm_resource_manager_set_used_basic
[20:48:16] [PASSED] ttm_sys_man_alloc_basic
[20:48:16] [PASSED] ttm_sys_man_free_basic
[20:48:16] ================== [PASSED] ttm_resource ===================
[20:48:16] =================== ttm_tt (15 subtests) ===================
[20:48:16] ==================== ttm_tt_init_basic ====================
[20:48:16] [PASSED] Page-aligned size
[20:48:16] [PASSED] Extra pages requested
[20:48:16] ================ [PASSED] ttm_tt_init_basic ================
[20:48:16] [PASSED] ttm_tt_init_misaligned
[20:48:16] [PASSED] ttm_tt_fini_basic
[20:48:16] [PASSED] ttm_tt_fini_sg
[20:48:16] [PASSED] ttm_tt_fini_shmem
[20:48:16] [PASSED] ttm_tt_create_basic
[20:48:16] [PASSED] ttm_tt_create_invalid_bo_type
[20:48:16] [PASSED] ttm_tt_create_ttm_exists
[20:48:16] [PASSED] ttm_tt_create_failed
[20:48:16] [PASSED] ttm_tt_destroy_basic
[20:48:16] [PASSED] ttm_tt_populate_null_ttm
[20:48:16] [PASSED] ttm_tt_populate_populated_ttm
[20:48:16] [PASSED] ttm_tt_unpopulate_basic
[20:48:16] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:48:16] [PASSED] ttm_tt_swapin_basic
[20:48:16] ===================== [PASSED] ttm_tt ======================
[20:48:16] =================== ttm_bo (14 subtests) ===================
[20:48:16] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[20:48:16] [PASSED] Cannot be interrupted and sleeps
[20:48:16] [PASSED] Cannot be interrupted, locks straight away
[20:48:16] [PASSED] Can be interrupted, sleeps
[20:48:16] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:48:16] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:48:16] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:48:16] [PASSED] ttm_bo_reserve_double_resv
[20:48:16] [PASSED] ttm_bo_reserve_interrupted
[20:48:16] [PASSED] ttm_bo_reserve_deadlock
[20:48:16] [PASSED] ttm_bo_unreserve_basic
[20:48:16] [PASSED] ttm_bo_unreserve_pinned
[20:48:16] [PASSED] ttm_bo_unreserve_bulk
[20:48:16] [PASSED] ttm_bo_fini_basic
[20:48:16] [PASSED] ttm_bo_fini_shared_resv
[20:48:16] [PASSED] ttm_bo_pin_basic
[20:48:16] [PASSED] ttm_bo_pin_unpin_resource
[20:48:16] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:48:16] ===================== [PASSED] ttm_bo ======================
[20:48:16] ============== ttm_bo_validate (21 subtests) ===============
[20:48:16] ============== ttm_bo_init_reserved_sys_man ===============
[20:48:16] [PASSED] Buffer object for userspace
[20:48:16] [PASSED] Kernel buffer object
[20:48:16] [PASSED] Shared buffer object
[20:48:16] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:48:16] ============== ttm_bo_init_reserved_mock_man ==============
[20:48:16] [PASSED] Buffer object for userspace
[20:48:16] [PASSED] Kernel buffer object
[20:48:16] [PASSED] Shared buffer object
[20:48:16] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:48:16] [PASSED] ttm_bo_init_reserved_resv
[20:48:16] ================== ttm_bo_validate_basic ==================
[20:48:16] [PASSED] Buffer object for userspace
[20:48:16] [PASSED] Kernel buffer object
[20:48:16] [PASSED] Shared buffer object
[20:48:16] ============== [PASSED] ttm_bo_validate_basic ==============
[20:48:16] [PASSED] ttm_bo_validate_invalid_placement
[20:48:16] ============= ttm_bo_validate_same_placement ==============
[20:48:16] [PASSED] System manager
[20:48:16] [PASSED] VRAM manager
[20:48:16] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:48:16] [PASSED] ttm_bo_validate_failed_alloc
[20:48:16] [PASSED] ttm_bo_validate_pinned
[20:48:16] [PASSED] ttm_bo_validate_busy_placement
[20:48:16] ================ ttm_bo_validate_multihop =================
[20:48:16] [PASSED] Buffer object for userspace
[20:48:16] [PASSED] Kernel buffer object
[20:48:16] [PASSED] Shared buffer object
[20:48:16] ============ [PASSED] ttm_bo_validate_multihop =============
[20:48:16] ========== ttm_bo_validate_no_placement_signaled ==========
[20:48:16] [PASSED] Buffer object in system domain, no page vector
[20:48:16] [PASSED] Buffer object in system domain with an existing page vector
[20:48:16] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:48:16] ======== ttm_bo_validate_no_placement_not_signaled ========
[20:48:16] [PASSED] Buffer object for userspace
[20:48:16] [PASSED] Kernel buffer object
[20:48:16] [PASSED] Shared buffer object
[20:48:16] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:48:16] [PASSED] ttm_bo_validate_move_fence_signaled
[20:48:16] ========= ttm_bo_validate_move_fence_not_signaled =========
[20:48:16] [PASSED] Waits for GPU
[20:48:16] [PASSED] Tries to lock straight away
[20:48:16] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:48:16] [PASSED] ttm_bo_validate_happy_evict
[20:48:16] [PASSED] ttm_bo_validate_all_pinned_evict
[20:48:16] [PASSED] ttm_bo_validate_allowed_only_evict
[20:48:16] [PASSED] ttm_bo_validate_deleted_evict
[20:48:16] [PASSED] ttm_bo_validate_busy_domain_evict
[20:48:16] [PASSED] ttm_bo_validate_evict_gutting
[20:48:16] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[20:48:16] ================= [PASSED] ttm_bo_validate =================
[20:48:16] ============================================================
[20:48:16] Testing complete. Ran 101 tests: passed: 101
[20:48:16] Elapsed time: 10.862s total, 1.668s configuring, 8.928s building, 0.234s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 21+ messages in thread* ✓ Xe.CI.BAT: success for drm/i915/vrr: Hide icl/tgl idiosyncrasies better
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
` (5 preceding siblings ...)
2025-09-17 20:48 ` ✓ CI.KUnit: success for drm/i915/vrr: Hide icl/tgl idiosyncrasies better Patchwork
@ 2025-09-17 21:28 ` Patchwork
2025-09-18 2:13 ` ✗ Xe.CI.Full: failure " Patchwork
7 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-09-17 21:28 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1458 bytes --]
== Series Details ==
Series: drm/i915/vrr: Hide icl/tgl idiosyncrasies better
URL : https://patchwork.freedesktop.org/series/154669/
State : success
== Summary ==
CI Bug Log - changes from xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781_BAT -> xe-pw-154669v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-154669v1_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-dpms:
- bat-adlp-7: [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/bat-adlp-7/igt@kms_flip@basic-flip-vs-dpms.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/bat-adlp-7/igt@kms_flip@basic-flip-vs-dpms.html
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
Build changes
-------------
* Linux: xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781 -> xe-pw-154669v1
IGT_8543: 8543
xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781: 9fab6e66b0f21d7175cd687e62dedd1b2d5d2781
xe-pw-154669v1: 154669v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/index.html
[-- Attachment #2: Type: text/html, Size: 2023 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread* ✗ Xe.CI.Full: failure for drm/i915/vrr: Hide icl/tgl idiosyncrasies better
2025-09-17 20:34 [PATCH 0/5] drm/i915/vrr: Hide icl/tgl idiosyncrasies better Ville Syrjala
` (6 preceding siblings ...)
2025-09-17 21:28 ` ✓ Xe.CI.BAT: " Patchwork
@ 2025-09-18 2:13 ` Patchwork
7 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2025-09-18 2:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 35502 bytes --]
== Series Details ==
Series: drm/i915/vrr: Hide icl/tgl idiosyncrasies better
URL : https://patchwork.freedesktop.org/series/154669/
State : failure
== Summary ==
CI Bug Log - changes from xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781_FULL -> xe-pw-154669v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-154669v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-154669v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-154669v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1:
- shard-adlp: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-3/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-9/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html
* igt@xe_oa@oa-exponents:
- shard-bmg: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-7/igt@xe_oa@oa-exponents.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-3/igt@xe_oa@oa-exponents.html
* igt@xe_oa@oa-exponents@ccs-0:
- shard-bmg: NOTRUN -> [INCOMPLETE][5]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-3/igt@xe_oa@oa-exponents@ccs-0.html
Known issues
------------
Here are the changes found in xe-pw-154669v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@crc-atomic@pipe-b-hdmi-a-1:
- shard-adlp: [PASS][6] -> [DMESG-FAIL][7] ([Intel XE#4543])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-9/igt@kms_async_flips@crc-atomic@pipe-b-hdmi-a-1.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-9/igt@kms_async_flips@crc-atomic@pipe-b-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-dg2-set2: NOTRUN -> [SKIP][8] ([Intel XE#316])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-432/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#1124])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-dg2-set2: NOTRUN -> [SKIP][10] ([Intel XE#607])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_bw@linear-tiling-2-displays-1920x1080p:
- shard-dg2-set2: NOTRUN -> [SKIP][11] ([Intel XE#367])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
* igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-c-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#787]) +153 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-432/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-c-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][13] ([Intel XE#3442])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][14] ([Intel XE#455] / [Intel XE#787]) +23 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [PASS][15] -> [INCOMPLETE][16] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: [PASS][17] -> [INCOMPLETE][18] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6:
- shard-dg2-set2: [PASS][19] -> [INCOMPLETE][20] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
- shard-dg2-set2: [PASS][21] -> [INCOMPLETE][22] ([Intel XE#1727] / [Intel XE#3113])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-5/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][24] ([Intel XE#373]) +2 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#307])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@srm@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][26] ([Intel XE#1178]) +2 other tests fail
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-435/igt@kms_content_protection@srm@pipe-a-dp-4.html
* igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
- shard-adlp: [PASS][27] -> [DMESG-WARN][28] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-1/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-8/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-bmg: [PASS][29] -> [SKIP][30] ([Intel XE#2291])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][31] -> [FAIL][32] ([Intel XE#4633])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_dp_linktrain_fallback@dp-fallback:
- shard-bmg: [PASS][33] -> [SKIP][34] ([Intel XE#4294])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-8/igt@kms_dp_linktrain_fallback@dp-fallback.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-bmg: [PASS][35] -> [SKIP][36] ([Intel XE#2316]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-1/igt@kms_flip@2x-nonexisting-fb.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-6/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@flip-vs-dpms-on-nop-interruptible:
- shard-adlp: [PASS][37] -> [DMESG-WARN][38] ([Intel XE#4543]) +3 other tests dmesg-warn
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-3/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-3/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a6:
- shard-dg2-set2: [PASS][39] -> [FAIL][40] ([Intel XE#301]) +1 other test fail
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-464/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a6.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a6.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-dg2-set2: [PASS][41] -> [INCOMPLETE][42] ([Intel XE#2049] / [Intel XE#2597])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-432/igt@kms_flip@flip-vs-suspend-interruptible.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-433/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@d-dp4:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][43] ([Intel XE#2049] / [Intel XE#2597])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-433/igt@kms_flip@flip-vs-suspend-interruptible@d-dp4.html
* igt@kms_flip@modeset-vs-vblank-race:
- shard-adlp: [PASS][44] -> [DMESG-WARN][45] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#5208])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-1/igt@kms_flip@modeset-vs-vblank-race.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-8/igt@kms_flip@modeset-vs-vblank-race.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
- shard-dg2-set2: NOTRUN -> [SKIP][46] ([Intel XE#455]) +3 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-pri-indfb-multidraw:
- shard-dg2-set2: NOTRUN -> [SKIP][47] ([Intel XE#651]) +9 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][48] ([Intel XE#653]) +8 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][49] ([Intel XE#2925])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
- shard-dg2-set2: NOTRUN -> [FAIL][50] ([Intel XE#616]) +2 other tests fail
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-433/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
- shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@psr-primary-page-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][52] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-432/igt@kms_psr@psr-primary-page-flip.html
* igt@kms_setmode@basic:
- shard-dg2-set2: [PASS][53] -> [FAIL][54] ([Intel XE#2883])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-433/igt@kms_setmode@basic.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-432/igt@kms_setmode@basic.html
* igt@kms_setmode@basic@pipe-b-dp-2:
- shard-dg2-set2: NOTRUN -> [FAIL][55] ([Intel XE#2883]) +4 other tests fail
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-432/igt@kms_setmode@basic@pipe-b-dp-2.html
* igt@kms_vblank@ts-continuation-dpms-suspend:
- shard-adlp: [PASS][56] -> [INCOMPLETE][57] ([Intel XE#4488]) +1 other test incomplete
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-3/igt@kms_vblank@ts-continuation-dpms-suspend.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-9/igt@kms_vblank@ts-continuation-dpms-suspend.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [PASS][58] -> [FAIL][59] ([Intel XE#4459]) +1 other test fail
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-lnl-4/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@xe_eu_stall@non-blocking-read:
- shard-dg2-set2: NOTRUN -> [SKIP][60] ([Intel XE#5626])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_eu_stall@non-blocking-read.html
* igt@xe_eudebug@basic-vm-bind-extended-discovery:
- shard-dg2-set2: NOTRUN -> [SKIP][61] ([Intel XE#4837]) +3 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_eudebug@basic-vm-bind-extended-discovery.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
- shard-dg2-set2: [PASS][62] -> [SKIP][63] ([Intel XE#1392]) +6 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-435/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@once-invalid-userptr-fault:
- shard-dg2-set2: NOTRUN -> [SKIP][64] ([Intel XE#288]) +7 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_exec_fault_mode@once-invalid-userptr-fault.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-adlp: [PASS][65] -> [DMESG-WARN][66] ([Intel XE#3876])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-3/igt@xe_exec_reset@parallel-gt-reset.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-9/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_exec_system_allocator@threads-many-large-execqueues-malloc-mlock-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][67] ([Intel XE#4915]) +65 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_exec_system_allocator@threads-many-large-execqueues-malloc-mlock-nomemset.html
* igt@xe_oa@disabled-read-error:
- shard-dg2-set2: NOTRUN -> [SKIP][68] ([Intel XE#3573]) +2 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_oa@disabled-read-error.html
* igt@xe_pat@pat-index-xehpc:
- shard-dg2-set2: NOTRUN -> [SKIP][69] ([Intel XE#2838] / [Intel XE#979])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pm@s3-d3cold-basic-exec:
- shard-dg2-set2: NOTRUN -> [SKIP][70] ([Intel XE#2284] / [Intel XE#366])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_pm@s3-d3cold-basic-exec.html
* igt@xe_pxp@pxp-termination-key-update-post-rpm:
- shard-dg2-set2: NOTRUN -> [SKIP][71] ([Intel XE#4733])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_pxp@pxp-termination-key-update-post-rpm.html
* igt@xe_sriov_auto_provisioning@exclusive-ranges:
- shard-dg2-set2: NOTRUN -> [SKIP][72] ([Intel XE#4130])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
#### Possible fixes ####
* igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
- shard-adlp: [FAIL][73] ([Intel XE#3908]) -> [PASS][74] +1 other test pass
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-9/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-6/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
* igt@kms_big_fb@linear-8bpp-rotate-180:
- shard-adlp: [DMESG-WARN][75] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][76] +4 other tests pass
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-6/igt@kms_big_fb@linear-8bpp-rotate-180.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-1/igt@kms_big_fb@linear-8bpp-rotate-180.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][77] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
- shard-dg2-set2: [INCOMPLETE][79] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-bmg: [SKIP][81] ([Intel XE#2291]) -> [PASS][82] +1 other test pass
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-dg2-set2: [INCOMPLETE][83] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-435/igt@kms_flip@2x-flip-vs-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-432/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-bmg: [SKIP][85] ([Intel XE#2316]) -> [PASS][86] +3 other tests pass
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-2/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-lnl: [FAIL][87] ([Intel XE#301]) -> [PASS][88] +3 other tests pass
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-rmfb-interruptible:
- shard-adlp: [DMESG-WARN][89] ([Intel XE#5208]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-6/igt@kms_flip@flip-vs-rmfb-interruptible.html
* igt@kms_flip@flip-vs-rmfb-interruptible@d-hdmi-a1:
- shard-adlp: [DMESG-WARN][91] ([Intel XE#4543]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-9/igt@kms_flip@flip-vs-rmfb-interruptible@d-hdmi-a1.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-6/igt@kms_flip@flip-vs-rmfb-interruptible@d-hdmi-a1.html
* igt@kms_setmode@basic:
- shard-adlp: [FAIL][93] ([Intel XE#2883]) -> [PASS][94] +1 other test pass
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-1/igt@kms_setmode@basic.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-8/igt@kms_setmode@basic.html
* igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
- shard-dg2-set2: [SKIP][95] ([Intel XE#1392]) -> [PASS][96] +4 other tests pass
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
* igt@xe_pm@s4-exec-after:
- shard-lnl: [DMESG-WARN][97] ([Intel XE#6090]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-lnl-7/igt@xe_pm@s4-exec-after.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-lnl-2/igt@xe_pm@s4-exec-after.html
#### Warnings ####
* igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1:
- shard-adlp: [DMESG-FAIL][99] ([Intel XE#4543]) -> [FAIL][100] ([Intel XE#3884])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-9/igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-9/igt@kms_async_flips@crc-atomic@pipe-c-hdmi-a-1.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-adlp: [DMESG-FAIL][101] ([Intel XE#4543]) -> [DMESG-FAIL][102] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4543])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
- shard-bmg: [SKIP][103] ([Intel XE#2312]) -> [SKIP][104] ([Intel XE#2311]) +7 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][105] ([Intel XE#2311]) -> [SKIP][106] ([Intel XE#2312]) +7 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][107] ([Intel XE#5390]) -> [SKIP][108] ([Intel XE#2312]) +3 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-bmg: [SKIP][109] ([Intel XE#2312]) -> [SKIP][110] ([Intel XE#5390]) +4 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][111] ([Intel XE#2312]) -> [SKIP][112] ([Intel XE#2313]) +8 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][113] ([Intel XE#2313]) -> [SKIP][114] ([Intel XE#2312]) +7 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][115] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][116] ([Intel XE#3544])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg2-set2: [SKIP][117] ([Intel XE#1500]) -> [SKIP][118] ([Intel XE#362])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-bmg: [ABORT][119] ([Intel XE#5466] / [Intel XE#5530]) -> [ABORT][120] ([Intel XE#4917] / [Intel XE#5466] / [Intel XE#5530])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-bmg-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-bmg-4/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-dg2-set2: [TIMEOUT][121] -> [INCOMPLETE][122] ([Intel XE#569])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781/shard-dg2-433/igt@xe_pm@s3-vm-bind-unbind-all.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/shard-dg2-436/igt@xe_pm@s3-vm-bind-unbind-all.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
[Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
[Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
[Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4294
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
[Intel XE#4488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4488
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6090
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
Build changes
-------------
* Linux: xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781 -> xe-pw-154669v1
IGT_8543: 8543
xe-3785-9fab6e66b0f21d7175cd687e62dedd1b2d5d2781: 9fab6e66b0f21d7175cd687e62dedd1b2d5d2781
xe-pw-154669v1: 154669v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154669v1/index.html
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