[PATCH v6 00/24] CPU binds and ULLS on migration queue

[PATCH v6 00/24] CPU binds and ULLS on migration queue

[Matthew Brost]

We now have data demonstrating the need for CPU binds and ULLS on the
migration queue, based on results generated from [1].

On BMG, measurements show that when the GPU is continuously processing
faults, copy jobs run approximately 30–40µs faster (depending on the
test case) with ULLS compared to traditional GuC submission with SLPC
enabled on the migration queue. Startup from a cold GPU shows an even
larger speedup. Given the critical nature of fault performance, ULLS
appears to be a worthwhile feature.

In addition to driver telemetry, UMD compute benchmarks consistently
show multiple GB/s improvement in pagefault benchmarks with ULLS enabled.

ULLS will consume more power (not yet measured) due to a continuously
running batch on the paging engine. However, compute UMDs already do
this on engines exposed to users, so this seems like a worthwhile
tradeoff. To mitigate power concerns, ULLS will exit after a period of
time in which no faults have been processed.

CPU binds are required for ULLS to function, as the migration queue
needs exclusive access to the paging hardware engine. Thus, CPU binds
are included here.

Beyond being a requirement for ULLS, CPU binds should also reduce
VM-bind latency, provide clearer multi-tile and TLB-invalidation
layering, reduce pressure on GuC during fault storms as it is bypassed,
and decouple kernel binds from unrelated copy/clear jobs—especially
beneficial when faults are serviced in parallel. In a parallel-faulting
test case, average bind time was reduced by approximately 15µs. In the
worst case, 2MB copy time (~60–140µs) × (number of pagefault threads −
1) of latency would otherwise be added to a single fault. Reducing this
latency increases overall throughput of the fault handler.

This series can be merged in phases:

Phase 1: CPU binds (patches 1–13)
Phase 2: CPU-bind components and multi-tile relayers (patches 14–17)
Phase 3: ULLS on the migration execution queue (patches 18–25)

v2:
 - Use delayed worker to exit ULLS mode in an effort to save on power
 - Various other cleanups
v3:
 - CPU bind component, multi-tile relayer
 - Split CPU bind patches in many small patches
v4:
 - Rebase, address feedback, add ULLS doc patch
v5:
 - Address Sashiko feedback, fix checkpatch issues
v6:
 - Reworked ULLS to drop KMD MMIO ring tail write, move this to ring
   instruction(s)
 - Several other small cleanups based on Sashiko feedback

Matt

[1] https://patchwork.freedesktop.org/series/149811/

Matthew Brost (24):
  drm/xe: Drop struct xe_migrate_pt_update argument from populate/clear
    vfuns
  drm/xe: Add xe_migrate_update_pgtables_cpu_execute helper
  drm/xe: Decouple exec queue idle check from LRC
  drm/xe: Add job count to GuC exec queue snapshot
  drm/xe: Update xe_bo_put_deferred arguments to include writeback flag
  drm/xe: Add XE_BO_FLAG_PUT_VM_ASYNC
  drm/xe: Update scheduler job layer to support PT jobs
  drm/xe: Add helpers to access PT ops
  drm/xe: Add struct xe_pt_job_ops
  drm/xe: Update GuC submission backend to run PT jobs
  drm/xe: Store level in struct xe_vm_pgtable_update
  drm/xe: Don't use migrate exec queue for page fault binds
  drm/xe: Enable CPU binds for jobs
  drm/xe: Remove unused arguments from xe_migrate_pt_update_ops
  drm/xe: Make bind queues operate cross-tile
  drm/xe: Add CPU bind layer
  drm/xe: Add device flag to enable PT mirroring across tiles
  drm/xe: Add ULLS support to LRC
  drm/xe: Add ULLS migration job support to migration layer
  drm/xe: Add ULLS migration job support to ring ops
  drm/xe: Add ULLS migration job support to GuC submission
  drm/xe: Enter ULLS for migration jobs upon page fault or SVM prefetch
  drm/xe: Add modparam to enable / disable ULLS on migrate queue
  drm/xe: Document ULLS for migration jobs

 Documentation/gpu/xe/xe_migrate.rst      |   3 +
 drivers/gpu/drm/xe/Makefile              |   1 +
 drivers/gpu/drm/xe/xe_bo.c               |   8 +-
 drivers/gpu/drm/xe/xe_bo.h               |  11 +-
 drivers/gpu/drm/xe/xe_bo_types.h         |   2 -
 drivers/gpu/drm/xe/xe_cpu_bind.c         | 298 +++++++++
 drivers/gpu/drm/xe/xe_cpu_bind.h         | 118 ++++
 drivers/gpu/drm/xe/xe_debugfs.c          |   1 +
 drivers/gpu/drm/xe/xe_defaults.h         |   1 +
 drivers/gpu/drm/xe/xe_device.c           |   6 +
 drivers/gpu/drm/xe/xe_device_types.h     |  11 +
 drivers/gpu/drm/xe/xe_drm_client.c       |   2 +-
 drivers/gpu/drm/xe/xe_exec_queue.c       | 163 ++---
 drivers/gpu/drm/xe/xe_exec_queue.h       |  16 +-
 drivers/gpu/drm/xe/xe_exec_queue_types.h |  20 +-
 drivers/gpu/drm/xe/xe_guc_submit.c       |  79 ++-
 drivers/gpu/drm/xe/xe_guc_submit_types.h |   2 +
 drivers/gpu/drm/xe/xe_lrc.c              |  73 +++
 drivers/gpu/drm/xe/xe_lrc.h              |   4 +
 drivers/gpu/drm/xe/xe_lrc_types.h        |   4 +
 drivers/gpu/drm/xe/xe_migrate.c          | 759 ++++++++++------------
 drivers/gpu/drm/xe/xe_migrate.h          |  95 +--
 drivers/gpu/drm/xe/xe_module.c           |   4 +
 drivers/gpu/drm/xe/xe_module.h           |   1 +
 drivers/gpu/drm/xe/xe_pagefault.c        |   3 +
 drivers/gpu/drm/xe/xe_pci.c              |   2 +
 drivers/gpu/drm/xe/xe_pci_types.h        |   3 +-
 drivers/gpu/drm/xe/xe_pt.c               | 785 ++++++++++++++---------
 drivers/gpu/drm/xe/xe_pt.h               |  12 +-
 drivers/gpu/drm/xe/xe_pt_types.h         |  49 +-
 drivers/gpu/drm/xe/xe_ring_ops.c         |  86 +++
 drivers/gpu/drm/xe/xe_ring_ops_types.h   |  24 +
 drivers/gpu/drm/xe/xe_sched_job.c        | 103 ++-
 drivers/gpu/drm/xe/xe_sched_job.h        |  56 ++
 drivers/gpu/drm/xe/xe_sched_job_types.h  |  49 +-
 drivers/gpu/drm/xe/xe_sync.c             |  20 +-
 drivers/gpu/drm/xe/xe_tlb_inval_job.c    |  28 +-
 drivers/gpu/drm/xe/xe_tlb_inval_job.h    |   4 +-
 drivers/gpu/drm/xe/xe_trace.h            |   2 +-
 drivers/gpu/drm/xe/xe_vm.c               | 240 +++----
 drivers/gpu/drm/xe/xe_vm.h               |   3 +
 drivers/gpu/drm/xe/xe_vm_types.h         |  12 +-
 42 files changed, 1956 insertions(+), 1207 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_cpu_bind.c
 create mode 100644 drivers/gpu/drm/xe/xe_cpu_bind.h

-- 
2.34.1

[PATCH v6 01/24] drm/xe: Drop struct xe_migrate_pt_update argument from populate/clear vfuns

[Matthew Brost]

Remove the xe_migrate_pt_update argument from the populate and clear
vfuns. This structure will not be available in run_job, where CPU binds
will be implemented. The populate path no longer needs it, and the clear
path already uses the VM field instead.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-2-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_migrate.c |  9 +++++----
 drivers/gpu/drm/xe/xe_migrate.h | 12 +++++-------
 drivers/gpu/drm/xe/xe_pt.c      | 12 +++++-------
 3 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index ff45c24d8889..149c5fa654e6 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -1760,6 +1760,7 @@ static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs,
 			  struct xe_migrate_pt_update *pt_update)
 {
 	const struct xe_migrate_pt_update_ops *ops = pt_update->ops;
+	struct xe_vm *vm = pt_update->vops->vm;
 	u32 chunk;
 	u32 ofs = update->ofs, size = update->qwords;
 
@@ -1791,10 +1792,10 @@ static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs,
 		bb->cs[bb->len++] = lower_32_bits(addr);
 		bb->cs[bb->len++] = upper_32_bits(addr);
 		if (pt_op->bind)
-			ops->populate(pt_update, tile, NULL, bb->cs + bb->len,
+			ops->populate(tile, NULL, bb->cs + bb->len,
 				      ofs, chunk, update);
 		else
-			ops->clear(pt_update, tile, NULL, bb->cs + bb->len,
+			ops->clear(vm, tile, NULL, bb->cs + bb->len,
 				   ofs, chunk, update);
 
 		bb->len += chunk * 2;
@@ -1851,12 +1852,12 @@ xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
 				&pt_op->entries[j];
 
 			if (pt_op->bind)
-				ops->populate(pt_update, m->tile,
+				ops->populate(m->tile,
 					      &update->pt_bo->vmap, NULL,
 					      update->ofs, update->qwords,
 					      update);
 			else
-				ops->clear(pt_update, m->tile,
+				ops->clear(vm, m->tile,
 					   &update->pt_bo->vmap, NULL,
 					   update->ofs, update->qwords, update);
 		}
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index a9acc62f78f0..2ec9de896dfe 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -40,7 +40,6 @@ enum xe_migrate_copy_dir {
 struct xe_migrate_pt_update_ops {
 	/**
 	 * @populate: Populate a command buffer or page-table with ptes.
-	 * @pt_update: Embeddable callback argument.
 	 * @tile: The tile for the current operation.
 	 * @map: struct iosys_map into the memory to be populated.
 	 * @pos: If @map is NULL, map into the memory to be populated.
@@ -52,13 +51,12 @@ struct xe_migrate_pt_update_ops {
 	 * page-table system to populate command buffers or shared
 	 * page-tables with PTEs.
 	 */
-	void (*populate)(struct xe_migrate_pt_update *pt_update,
-			 struct xe_tile *tile, struct iosys_map *map,
+	void (*populate)(struct xe_tile *tile, struct iosys_map *map,
 			 void *pos, u32 ofs, u32 num_qwords,
 			 const struct xe_vm_pgtable_update *update);
 	/**
 	 * @clear: Clear a command buffer or page-table with ptes.
-	 * @pt_update: Embeddable callback argument.
+	 * @vm: VM being updated
 	 * @tile: The tile for the current operation.
 	 * @map: struct iosys_map into the memory to be populated.
 	 * @pos: If @map is NULL, map into the memory to be populated.
@@ -70,9 +68,9 @@ struct xe_migrate_pt_update_ops {
 	 * page-table system to populate command buffers or shared
 	 * page-tables with PTEs.
 	 */
-	void (*clear)(struct xe_migrate_pt_update *pt_update,
-		      struct xe_tile *tile, struct iosys_map *map,
-		      void *pos, u32 ofs, u32 num_qwords,
+	void (*clear)(struct xe_vm *vm, struct xe_tile *tile,
+		      struct iosys_map *map, void *pos, u32 ofs,
+		      u32 num_qwords,
 		      const struct xe_vm_pgtable_update *update);
 
 	/**
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 5d990c1c3740..854c0a59af71 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -1092,9 +1092,8 @@ bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,
 }
 
 static void
-xe_vm_populate_pgtable(struct xe_migrate_pt_update *pt_update, struct xe_tile *tile,
-		       struct iosys_map *map, void *data,
-		       u32 qword_ofs, u32 num_qwords,
+xe_vm_populate_pgtable(struct xe_tile *tile, struct iosys_map *map,
+		       void *data, u32 qword_ofs, u32 num_qwords,
 		       const struct xe_vm_pgtable_update *update)
 {
 	struct xe_pt_entry *ptes = update->pt_entries;
@@ -2008,12 +2007,11 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
 }
 
 static void
-xe_migrate_clear_pgtable_callback(struct xe_migrate_pt_update *pt_update,
-				  struct xe_tile *tile, struct iosys_map *map,
-				  void *ptr, u32 qword_ofs, u32 num_qwords,
+xe_migrate_clear_pgtable_callback(struct xe_vm *vm, struct xe_tile *tile,
+				  struct iosys_map *map, void *ptr,
+				  u32 qword_ofs, u32 num_qwords,
 				  const struct xe_vm_pgtable_update *update)
 {
-	struct xe_vm *vm = pt_update->vops->vm;
 	u64 empty = __xe_pt_empty_pte(tile, vm, update->pt->level);
 	int i;
 
-- 
2.34.1

[PATCH v6 02/24] drm/xe: Add xe_migrate_update_pgtables_cpu_execute helper

[Matthew Brost]

Add the xe_migrate_update_pgtables_cpu_execute helper, which performs
the CPU-side page-table update. This will support implementing CPU
binds, as the submission backend can call this helper once a bind job’s
dependencies are resolved. While here, add assertions to provide basic
sanity checks on tht function arguments.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-3-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_migrate.c | 58 ++++++++++++++++++++-------------
 1 file changed, 35 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 149c5fa654e6..68a0b05f56ec 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -1819,6 +1819,38 @@ struct migrate_test_params {
 	container_of(_priv, struct migrate_test_params, base)
 #endif
 
+static void
+xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
+				       const struct xe_migrate_pt_update_ops *ops,
+				       struct xe_vm_pgtable_update_op *pt_op,
+				       u32 num_ops)
+{
+	u32 j, i;
+
+	for (j = 0; j < num_ops; ++j, ++pt_op) {
+		for (i = 0; i < pt_op->num_entries; i++) {
+			const struct xe_vm_pgtable_update *update =
+				&pt_op->entries[i];
+
+			xe_tile_assert(tile, update);
+			xe_tile_assert(tile, update->pt_bo);
+			xe_tile_assert(tile, !iosys_map_is_null(&update->pt_bo->vmap));
+
+			if (pt_op->bind)
+				ops->populate(tile, &update->pt_bo->vmap,
+					      NULL, update->ofs, update->qwords,
+					      update);
+			else
+				ops->clear(vm, tile, &update->pt_bo->vmap,
+					   NULL, update->ofs, update->qwords,
+					   update);
+		}
+	}
+
+	trace_xe_vm_cpu_bind(vm);
+	xe_device_wmb(vm->xe);
+}
+
 static struct dma_fence *
 xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
 			       struct xe_migrate_pt_update *pt_update)
@@ -1831,7 +1863,6 @@ xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
 	struct xe_vm_pgtable_update_ops *pt_update_ops =
 		&pt_update->vops->pt_update_ops[pt_update->tile_id];
 	int err;
-	u32 i, j;
 
 	if (XE_TEST_ONLY(test && test->force_gpu))
 		return ERR_PTR(-ETIME);
@@ -1843,28 +1874,9 @@ xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
 			return ERR_PTR(err);
 	}
 
-	for (i = 0; i < pt_update_ops->num_ops; ++i) {
-		const struct xe_vm_pgtable_update_op *pt_op =
-			&pt_update_ops->ops[i];
-
-		for (j = 0; j < pt_op->num_entries; j++) {
-			const struct xe_vm_pgtable_update *update =
-				&pt_op->entries[j];
-
-			if (pt_op->bind)
-				ops->populate(m->tile,
-					      &update->pt_bo->vmap, NULL,
-					      update->ofs, update->qwords,
-					      update);
-			else
-				ops->clear(vm, m->tile,
-					   &update->pt_bo->vmap, NULL,
-					   update->ofs, update->qwords, update);
-		}
-	}
-
-	trace_xe_vm_cpu_bind(vm);
-	xe_device_wmb(vm->xe);
+	xe_migrate_update_pgtables_cpu_execute(vm, m->tile, ops,
+					       pt_update_ops->ops,
+					       pt_update_ops->num_ops);
 
 	return dma_fence_get_stub();
 }
-- 
2.34.1

[PATCH v6 03/24] drm/xe: Decouple exec queue idle check from LRC

[Matthew Brost]

We already maintain a job count for each exec queue, so simplify the idle
check to rely on the job count rather than the LRC state. This decouples
exec queues from LRC-based backends and avoids unnecessarily coupling idle
detection to backend-specific implementation details.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-4-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_exec_queue.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index e63559a2f582..7bbb31431900 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -1580,20 +1580,7 @@ bool xe_exec_queue_is_lr(struct xe_exec_queue *q)
  */
 bool xe_exec_queue_is_idle(struct xe_exec_queue *q)
 {
-	if (xe_exec_queue_is_parallel(q)) {
-		int i;
-
-		for (i = 0; i < q->width; ++i) {
-			if (xe_lrc_seqno(q->lrc[i]) !=
-			    q->lrc[i]->fence_ctx.next_seqno - 1)
-				return false;
-		}
-
-		return true;
-	}
-
-	return xe_lrc_seqno(q->lrc[0]) ==
-		q->lrc[0]->fence_ctx.next_seqno - 1;
+	return !atomic_read(&q->job_cnt);
 }
 
 /**
-- 
2.34.1

[PATCH v6 04/24] drm/xe: Add job count to GuC exec queue snapshot

[Matthew Brost]

Add the job count to the GuC exec queue snapshot, as this is useful
debug information.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-5-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_guc_submit.c       | 2 ++
 drivers/gpu/drm/xe/xe_guc_submit_types.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 0a6e2b81b5a5..8b8673f4e037 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -3684,6 +3684,7 @@ xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q)
 	snapshot->logical_mask = q->logical_mask;
 	snapshot->width = q->width;
 	snapshot->refcount = kref_read(&q->refcount);
+	snapshot->jobcount = atomic_read(&q->job_cnt);
 	snapshot->sched_timeout = sched->base.timeout;
 	snapshot->sched_props.timeslice_us = q->sched_props.timeslice_us;
 	snapshot->sched_props.preempt_timeout_us =
@@ -3756,6 +3757,7 @@ xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snaps
 	drm_printf(p, "\tLogical mask: 0x%x\n", snapshot->logical_mask);
 	drm_printf(p, "\tWidth: %d\n", snapshot->width);
 	drm_printf(p, "\tRef: %d\n", snapshot->refcount);
+	drm_printf(p, "\tJob count: %d\n", snapshot->jobcount);
 	drm_printf(p, "\tTimeout: %ld (ms)\n", snapshot->sched_timeout);
 	drm_printf(p, "\tTimeslice: %u (us)\n",
 		   snapshot->sched_props.timeslice_us);
diff --git a/drivers/gpu/drm/xe/xe_guc_submit_types.h b/drivers/gpu/drm/xe/xe_guc_submit_types.h
index 7824f61b1290..8271702e692e 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_submit_types.h
@@ -77,6 +77,8 @@ struct xe_guc_submit_exec_queue_snapshot {
 	u16 width;
 	/** @refcount: ref count of this exec queue */
 	u32 refcount;
+	/** @jobcount: job count of this exec queue */
+	u32 jobcount;
 	/**
 	 * @sched_timeout: the time after which a job is removed from the
 	 * scheduler.
-- 
2.34.1

[PATCH v6 05/24] drm/xe: Update xe_bo_put_deferred arguments to include writeback flag

[Matthew Brost]

Update the xe_bo_put_deferred arguments to include a writeback flag,
which indicates whether the BO was added to the deferred list. This is
useful when the caller needs to take additional actions after the BO has
been queued for deferred release.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-6-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_bo.h         | 10 ++++++++--
 drivers/gpu/drm/xe/xe_drm_client.c |  2 +-
 drivers/gpu/drm/xe/xe_pt.c         |  2 +-
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index eede678ad303..01975586ee88 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -495,6 +495,8 @@ void __xe_bo_release_dummy(struct kref *kref);
  * @bo: The bo to put.
  * @deferred: List to which to add the buffer object if we cannot put, or
  * NULL if the function is to put unconditionally.
+ * @added: BO was added to deferred list, written back to caller, can be NULL if
+ * writeback is not needed. Only set to true when added, never set to false.
  *
  * Since the final freeing of an object includes both sleeping and (!)
  * memory allocation in the dma_resv individualization, it's not ok
@@ -514,7 +516,8 @@ void __xe_bo_release_dummy(struct kref *kref);
  * false otherwise.
  */
 static inline bool
-xe_bo_put_deferred(struct xe_bo *bo, struct llist_head *deferred)
+xe_bo_put_deferred(struct xe_bo *bo, struct llist_head *deferred,
+		   bool *added)
 {
 	if (!deferred) {
 		xe_bo_put(bo);
@@ -524,6 +527,9 @@ xe_bo_put_deferred(struct xe_bo *bo, struct llist_head *deferred)
 	if (!kref_put(&bo->ttm.base.refcount, __xe_bo_release_dummy))
 		return false;
 
+	if (added)
+		*added = true;
+
 	return llist_add(&bo->freed, deferred);
 }
 
@@ -540,7 +546,7 @@ xe_bo_put_async(struct xe_bo *bo)
 {
 	struct xe_bo_dev *bo_device = &xe_bo_device(bo)->bo_device;
 
-	if (xe_bo_put_deferred(bo, &bo_device->async_list))
+	if (xe_bo_put_deferred(bo, &bo_device->async_list, NULL))
 		schedule_work(&bo_device->async_free);
 }
 
diff --git a/drivers/gpu/drm/xe/xe_drm_client.c b/drivers/gpu/drm/xe/xe_drm_client.c
index e116fb562c4c..4c424d1c6721 100644
--- a/drivers/gpu/drm/xe/xe_drm_client.c
+++ b/drivers/gpu/drm/xe/xe_drm_client.c
@@ -256,7 +256,7 @@ static void show_meminfo(struct drm_printer *p, struct drm_file *file)
 			xe_assert(xef->xe, !list_empty(&bo->client_link));
 		}
 
-		xe_bo_put_deferred(bo, &deferred);
+		xe_bo_put_deferred(bo, &deferred, NULL);
 	}
 	spin_unlock(&client->bos_lock);
 
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 854c0a59af71..3170df1f3fbf 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -213,7 +213,7 @@ void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred)
 
 	XE_WARN_ON(!list_empty(&pt->bo->ttm.base.gpuva.list));
 	xe_bo_unpin(pt->bo);
-	xe_bo_put_deferred(pt->bo, deferred);
+	xe_bo_put_deferred(pt->bo, deferred, NULL);
 
 	if (pt->level > 0 && pt->num_live) {
 		struct xe_pt_dir *pt_dir = as_xe_pt_dir(pt);
-- 
2.34.1

[PATCH v6 06/24] drm/xe: Add XE_BO_FLAG_PUT_VM_ASYNC

[Matthew Brost]

Add XE_BO_FLAG_PUT_VM_ASYNC, which indicates that an async BO put must
also drop an additional reference to the BO’s VM. This is useful when a
kernel BO, one that does not normally hold a VM reference, needs to be
put asynchronously, ensuring the shared dma-resv object does not
disappear before the BO.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-7-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_bo.c | 8 +++++++-
 drivers/gpu/drm/xe/xe_bo.h | 1 +
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index b162753cebb7..aea4b0fee8e3 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -3998,8 +3998,14 @@ void xe_bo_put_commit(struct llist_head *deferred)
 	if (!freed)
 		return;
 
-	llist_for_each_entry_safe(bo, next, freed, freed)
+	llist_for_each_entry_safe(bo, next, freed, freed) {
+		struct xe_vm *vm = bo->vm;
+		bool async = bo->flags & XE_BO_FLAG_PUT_VM_ASYNC;
+
 		drm_gem_object_free(&bo->ttm.base.refcount);
+		if (async)
+			xe_vm_put(vm);
+	}
 }
 
 static void xe_bo_dev_work_func(struct work_struct *work)
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index 01975586ee88..2168aac1ed1e 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -54,6 +54,7 @@
 #define XE_BO_FLAG_FORCE_USER_VRAM	BIT(25)
 #define XE_BO_FLAG_NO_COMPRESSION	BIT(26)
 #define XE_BO_FLAG_NEEDS_1G		BIT(27)
+#define XE_BO_FLAG_PUT_VM_ASYNC		BIT(28)
 
 /* this one is trigger internally only */
 #define XE_BO_FLAG_INTERNAL_TEST	BIT(30)
-- 
2.34.1

[PATCH v6 07/24] drm/xe: Update scheduler job layer to support PT jobs

[Matthew Brost]

Update the scheduler job layer to support PT jobs. PT jobs are executed
entirely on the CPU and do not require LRC fences or a batch address.
Repurpose the LRC fence storage to hold PT‑job arguments and update the
scheduler job layer to distinguish between PT jobs and jobs that require
an LRC.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-8-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_sched_job.c       | 95 ++++++++++++++++---------
 drivers/gpu/drm/xe/xe_sched_job_types.h | 31 +++++++-
 drivers/gpu/drm/xe/xe_trace.h           |  2 +-
 3 files changed, 92 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
index a4fa00632a30..841d67ebd5b0 100644
--- a/drivers/gpu/drm/xe/xe_sched_job.c
+++ b/drivers/gpu/drm/xe/xe_sched_job.c
@@ -26,19 +26,22 @@ static struct kmem_cache *xe_sched_job_parallel_slab;
 
 int __init xe_sched_job_module_init(void)
 {
+	struct xe_sched_job *job;
+	size_t size;
+
+	size = struct_size(job, ptrs, 1);
 	xe_sched_job_slab =
-		kmem_cache_create("xe_sched_job",
-				  sizeof(struct xe_sched_job) +
-				  sizeof(struct xe_job_ptrs), 0,
+		kmem_cache_create("xe_sched_job", size, 0,
 				  SLAB_HWCACHE_ALIGN, NULL);
 	if (!xe_sched_job_slab)
 		return -ENOMEM;
 
+	size = max_t(size_t,
+		     struct_size(job, ptrs,
+				 XE_HW_ENGINE_MAX_INSTANCE),
+		     struct_size(job, pt_update, 1));
 	xe_sched_job_parallel_slab =
-		kmem_cache_create("xe_sched_job_parallel",
-				  sizeof(struct xe_sched_job) +
-				  sizeof(struct xe_job_ptrs) *
-				  XE_HW_ENGINE_MAX_INSTANCE, 0,
+		kmem_cache_create("xe_sched_job_parallel", size, 0,
 				  SLAB_HWCACHE_ALIGN, NULL);
 	if (!xe_sched_job_parallel_slab) {
 		kmem_cache_destroy(xe_sched_job_slab);
@@ -84,6 +87,9 @@ static void xe_sched_job_free_fences(struct xe_sched_job *job)
 {
 	int i;
 
+	if (job->is_pt_job)
+		return;
+
 	for (i = 0; i < job->q->width; ++i) {
 		struct xe_job_ptrs *ptrs = &job->ptrs[i];
 
@@ -93,10 +99,23 @@ static void xe_sched_job_free_fences(struct xe_sched_job *job)
 	}
 }
 
+/**
+ * xe_sched_job_create() - Create a scheduler job
+ * @q: exec queue to create the scheduler job for
+ * @batch_addr: array of batch addresses for the job; must match the width of
+ * @q, or NULL to indicate a PT job that does not require a batch address
+ *
+ * Create a scheduler job for submission.
+ *
+ * Context: Reclaim
+ *
+ * Return: a &xe_sched_job object on success, or an ERR_PTR on failure.
+ */
 struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
 					 u64 *batch_addr)
 {
 	bool is_migration = xe_sched_job_is_migration(q);
+	struct xe_device *xe = gt_to_xe(q->gt);
 	struct xe_sched_job *job;
 	int err;
 	int i;
@@ -105,6 +124,9 @@ struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
 	/* only a kernel context can submit a vm-less job */
 	XE_WARN_ON(!q->vm && !(q->flags & EXEC_QUEUE_FLAG_KERNEL));
 
+	xe_assert(xe, batch_addr ||
+		  q->flags & (EXEC_QUEUE_FLAG_VM | EXEC_QUEUE_FLAG_MIGRATE));
+
 	job = job_alloc(xe_exec_queue_is_parallel(q) || is_migration);
 	if (!job)
 		return ERR_PTR(-ENOMEM);
@@ -119,34 +141,39 @@ struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
 	if (err)
 		goto err_free;
 
-	for (i = 0; i < q->width; ++i) {
-		struct dma_fence *fence = xe_lrc_alloc_seqno_fence();
-		struct dma_fence_chain *chain;
-
-		if (IS_ERR(fence)) {
-			err = PTR_ERR(fence);
-			goto err_sched_job;
+	if (!batch_addr) {
+		job->fence = dma_fence_get_stub();
+		job->is_pt_job = true;
+	} else {
+		for (i = 0; i < q->width; ++i) {
+			struct dma_fence *fence = xe_lrc_alloc_seqno_fence();
+			struct dma_fence_chain *chain;
+
+			if (IS_ERR(fence)) {
+				err = PTR_ERR(fence);
+				goto err_sched_job;
+			}
+			job->ptrs[i].lrc_fence = fence;
+
+			if (i + 1 == q->width)
+				continue;
+
+			chain = dma_fence_chain_alloc();
+			if (!chain) {
+				err = -ENOMEM;
+				goto err_sched_job;
+			}
+			job->ptrs[i].chain_fence = chain;
 		}
-		job->ptrs[i].lrc_fence = fence;
 
-		if (i + 1 == q->width)
-			continue;
+		width = q->width;
+		if (is_migration)
+			width = 2;
 
-		chain = dma_fence_chain_alloc();
-		if (!chain) {
-			err = -ENOMEM;
-			goto err_sched_job;
-		}
-		job->ptrs[i].chain_fence = chain;
+		for (i = 0; i < width; ++i)
+			job->ptrs[i].batch_addr = batch_addr[i];
 	}
 
-	width = q->width;
-	if (is_migration)
-		width = 2;
-
-	for (i = 0; i < width; ++i)
-		job->ptrs[i].batch_addr = batch_addr[i];
-
 	atomic_inc(&q->job_cnt);
 	xe_pm_runtime_get_noresume(job_to_xe(job));
 	trace_xe_sched_job_create(job);
@@ -246,7 +273,7 @@ bool xe_sched_job_completed(struct xe_sched_job *job)
 void xe_sched_job_arm(struct xe_sched_job *job)
 {
 	struct xe_exec_queue *q = job->q;
-	struct dma_fence *fence, *prev;
+	struct dma_fence *fence = job->fence, *prev;
 	struct xe_vm *vm = q->vm;
 	u64 seqno = 0;
 	int i;
@@ -266,6 +293,9 @@ void xe_sched_job_arm(struct xe_sched_job *job)
 		job->ring_ops_flush_tlb = true;
 	}
 
+	if (job->is_pt_job)
+		goto arm;
+
 	/* Arm the pre-allocated fences */
 	for (i = 0; i < q->width; prev = fence, ++i) {
 		struct dma_fence_chain *chain;
@@ -286,6 +316,7 @@ void xe_sched_job_arm(struct xe_sched_job *job)
 		fence = &chain->base;
 	}
 
+arm:
 	job->fence = dma_fence_get(fence);	/* Pairs with put in scheduler */
 	drm_sched_job_arm(&job->drm);
 }
@@ -329,7 +360,7 @@ xe_sched_job_snapshot_capture(struct xe_sched_job *job)
 
 	snapshot->batch_addr_len = q->width;
 	for (i = 0; i < q->width; i++)
-		snapshot->batch_addr[i] =
+		snapshot->batch_addr[i] = job->is_pt_job ? 0 :
 			xe_device_uncanonicalize_addr(xe, job->ptrs[i].batch_addr);
 
 	return snapshot;
diff --git a/drivers/gpu/drm/xe/xe_sched_job_types.h b/drivers/gpu/drm/xe/xe_sched_job_types.h
index 0490b1247a6e..5e1824c36c74 100644
--- a/drivers/gpu/drm/xe/xe_sched_job_types.h
+++ b/drivers/gpu/drm/xe/xe_sched_job_types.h
@@ -10,10 +10,29 @@
 
 #include <drm/gpu_scheduler.h>
 
-struct xe_exec_queue;
 struct dma_fence;
 struct dma_fence_chain;
 
+struct xe_exec_queue;
+struct xe_migrate_pt_update_ops;
+struct xe_pt_job_ops;
+struct xe_tile;
+struct xe_vm;
+
+/**
+ * struct xe_pt_update_args - PT update arguments
+ */
+struct xe_pt_update_args {
+	/** @vm: VM which is being bound */
+	struct xe_vm *vm;
+	/** @tile: Tile which page tables belong to */
+	struct xe_tile *tile;
+	/** @ops: Migrate PT update ops */
+	const struct xe_migrate_pt_update_ops *ops;
+	/** @pt_job_ops: PT job ops state */
+	struct xe_pt_job_ops *pt_job_ops;
+};
+
 /**
  * struct xe_job_ptrs - Per hw engine instance data
  */
@@ -71,8 +90,14 @@ struct xe_sched_job {
 	bool restore_replay;
 	/** @last_replay: last job being replayed */
 	bool last_replay;
-	/** @ptrs: per instance pointers. */
-	struct xe_job_ptrs ptrs[];
+	/** @is_pt_job: is a PT job */
+	bool is_pt_job;
+	union {
+		/** @ptrs: per instance pointers. */
+		DECLARE_FLEX_ARRAY(struct xe_job_ptrs, ptrs);
+		/** @pt_update: PT update arguments */
+		DECLARE_FLEX_ARRAY(struct xe_pt_update_args, pt_update);
+	};
 };
 
 struct xe_sched_job_snapshot {
diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
index 2fe8f89a1e34..d4e9d91f6f7f 100644
--- a/drivers/gpu/drm/xe/xe_trace.h
+++ b/drivers/gpu/drm/xe/xe_trace.h
@@ -261,7 +261,7 @@ DECLARE_EVENT_CLASS(xe_sched_job,
 			   __entry->flags = job->q->flags;
 			   __entry->error = job->fence ? job->fence->error : 0;
 			   __entry->fence = job->fence;
-			   __entry->batch_addr = (u64)job->ptrs[0].batch_addr;
+			   __entry->batch_addr = job->is_pt_job ? 0 : (u64)job->ptrs[0].batch_addr;
 			   ),
 
 		    TP_printk("dev=%s, fence=%p, seqno=%u, lrc_seqno=%u, gt=%u, guc_id=%d, batch_addr=0x%012llx, guc_state=0x%x, flags=0x%x, error=%d",
-- 
2.34.1

[PATCH v6 08/24] drm/xe: Add helpers to access PT ops

[Matthew Brost]

Add helpers to access PT ops, making it easier to shuffle the location of
the ops structures without requiring widespread code changes.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-9-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_pt.c | 65 ++++++++++++++++++++++++++------------
 1 file changed, 45 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 3170df1f3fbf..e560f167fdf1 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -2078,13 +2078,37 @@ xe_pt_commit_prepare_unbind(struct xe_vma *vma,
 	}
 }
 
+static struct xe_vm_pgtable_update_op *
+to_pt_op(struct xe_vm_pgtable_update_ops *pt_update_ops, u32 op_idx)
+{
+	return &pt_update_ops->ops[op_idx];
+}
+
+static u32
+get_current_op(struct xe_vm_pgtable_update_ops *pt_update_ops)
+{
+	return pt_update_ops->current_op;
+}
+
+static struct xe_vm_pgtable_update_op *
+to_current_pt_op(struct xe_vm_pgtable_update_ops *pt_update_ops)
+{
+	return to_pt_op(pt_update_ops, get_current_op(pt_update_ops));
+}
+
+static void
+incr_current_op(struct xe_vm_pgtable_update_ops *pt_update_ops)
+{
+	++pt_update_ops->current_op;
+}
+
 static void
 xe_pt_update_ops_rfence_interval(struct xe_vm_pgtable_update_ops *pt_update_ops,
 				 u64 start, u64 end)
 {
 	u64 last;
-	u32 current_op = pt_update_ops->current_op;
-	struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[current_op];
+	struct xe_vm_pgtable_update_op *pt_op =
+		to_current_pt_op(pt_update_ops);
 	int i, level = 0;
 
 	for (i = 0; i < pt_op->num_entries; i++) {
@@ -2119,8 +2143,8 @@ static int bind_op_prepare(struct xe_vm *vm, struct xe_tile *tile,
 			   struct xe_vm_pgtable_update_ops *pt_update_ops,
 			   struct xe_vma *vma, bool invalidate_on_bind)
 {
-	u32 current_op = pt_update_ops->current_op;
-	struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[current_op];
+	struct xe_vm_pgtable_update_op *pt_op =
+		to_current_pt_op(pt_update_ops);
 	int err;
 
 	xe_tile_assert(tile, !xe_vma_is_cpu_addr_mirror(vma));
@@ -2149,7 +2173,7 @@ static int bind_op_prepare(struct xe_vm *vm, struct xe_tile *tile,
 		xe_pt_update_ops_rfence_interval(pt_update_ops,
 						 xe_vma_start(vma),
 						 xe_vma_end(vma));
-		++pt_update_ops->current_op;
+		incr_current_op(pt_update_ops);
 		pt_update_ops->needs_svm_lock |= xe_vma_is_userptr(vma);
 
 		/*
@@ -2192,8 +2216,8 @@ static int bind_range_prepare(struct xe_vm *vm, struct xe_tile *tile,
 			      struct xe_vm_pgtable_update_ops *pt_update_ops,
 			      struct xe_vma *vma, struct xe_svm_range *range)
 {
-	u32 current_op = pt_update_ops->current_op;
-	struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[current_op];
+	struct xe_vm_pgtable_update_op *pt_op =
+		to_current_pt_op(pt_update_ops);
 	int err;
 
 	xe_tile_assert(tile, xe_vma_is_cpu_addr_mirror(vma));
@@ -2217,7 +2241,7 @@ static int bind_range_prepare(struct xe_vm *vm, struct xe_tile *tile,
 		xe_pt_update_ops_rfence_interval(pt_update_ops,
 						 xe_svm_range_start(range),
 						 xe_svm_range_end(range));
-		++pt_update_ops->current_op;
+		incr_current_op(pt_update_ops);
 		pt_update_ops->needs_svm_lock = true;
 
 		pt_op->vma = vma;
@@ -2235,8 +2259,8 @@ static int unbind_op_prepare(struct xe_tile *tile,
 			     struct xe_vma *vma)
 {
 	struct xe_device *xe = tile_to_xe(tile);
-	u32 current_op = pt_update_ops->current_op;
-	struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[current_op];
+	struct xe_vm_pgtable_update_op *pt_op =
+		to_current_pt_op(pt_update_ops);
 	int err;
 
 	if (!((vma->tile_present | vma->tile_staged) & BIT(tile->id)))
@@ -2275,7 +2299,7 @@ static int unbind_op_prepare(struct xe_tile *tile,
 				pt_op->num_entries, false);
 	xe_pt_update_ops_rfence_interval(pt_update_ops, xe_vma_start(vma),
 					 xe_vma_end(vma));
-	++pt_update_ops->current_op;
+	incr_current_op(pt_update_ops);
 	pt_update_ops->needs_svm_lock |= xe_vma_is_userptr(vma);
 	pt_update_ops->needs_invalidation = true;
 
@@ -2315,8 +2339,8 @@ static int unbind_range_prepare(struct xe_vm *vm,
 				struct xe_vm_pgtable_update_ops *pt_update_ops,
 				struct xe_svm_range *range)
 {
-	u32 current_op = pt_update_ops->current_op;
-	struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[current_op];
+	struct xe_vm_pgtable_update_op *pt_op =
+		to_current_pt_op(pt_update_ops);
 
 	if (!(range->tile_present & BIT(tile->id)))
 		return 0;
@@ -2337,7 +2361,7 @@ static int unbind_range_prepare(struct xe_vm *vm,
 				pt_op->num_entries, false);
 	xe_pt_update_ops_rfence_interval(pt_update_ops, xe_svm_range_start(range),
 					 xe_svm_range_end(range));
-	++pt_update_ops->current_op;
+	incr_current_op(pt_update_ops);
 	pt_update_ops->needs_svm_lock = true;
 	pt_update_ops->needs_invalidation |= xe_vm_has_scratch(vm) ||
 		xe_vm_has_valid_gpu_mapping(tile, range->tile_present,
@@ -2494,7 +2518,7 @@ int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops)
 			return err;
 	}
 
-	xe_tile_assert(tile, pt_update_ops->current_op <=
+	xe_tile_assert(tile, get_current_op(pt_update_ops) <=
 		       pt_update_ops->num_ops);
 
 #ifdef TEST_VM_OPS_ERROR
@@ -2727,7 +2751,7 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
 	lockdep_assert_held(&vm->lock);
 	xe_vm_assert_held(vm);
 
-	if (!pt_update_ops->current_op) {
+	if (!get_current_op(pt_update_ops)) {
 		xe_tile_assert(tile, xe_vm_in_fault_mode(vm));
 
 		return dma_fence_get_stub();
@@ -2795,8 +2819,9 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
 	}
 
 	/* Point of no return - VM killed if failure after this */
-	for (i = 0; i < pt_update_ops->current_op; ++i) {
-		struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[i];
+	for (i = 0; i < get_current_op(pt_update_ops); ++i) {
+		struct xe_vm_pgtable_update_op *pt_op =
+			to_pt_op(pt_update_ops, i);
 
 		xe_pt_commit(pt_op->vma, pt_op->entries,
 			     pt_op->num_entries, &pt_update_ops->deferred);
@@ -2920,9 +2945,9 @@ void xe_pt_update_ops_abort(struct xe_tile *tile, struct xe_vma_ops *vops)
 
 	for (i = pt_update_ops->num_ops - 1; i >= 0; --i) {
 		struct xe_vm_pgtable_update_op *pt_op =
-			&pt_update_ops->ops[i];
+			to_pt_op(pt_update_ops, i);
 
-		if (!pt_op->vma || i >= pt_update_ops->current_op)
+		if (!pt_op->vma || i >= get_current_op(pt_update_ops))
 			continue;
 
 		if (pt_op->bind)
-- 
2.34.1

[PATCH v6 09/24] drm/xe: Add struct xe_pt_job_ops

[Matthew Brost]

Add struct xe_pt_job_ops, a dynamically refcounted object that contains
the information required to issue a CPU bind via a job after the initial
bind IOCTL returns.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-10-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_migrate.c  |  10 +--
 drivers/gpu/drm/xe/xe_pt.c       | 136 +++++++++++++++++++++++++++----
 drivers/gpu/drm/xe/xe_pt.h       |   4 +
 drivers/gpu/drm/xe/xe_pt_types.h |  27 ++++--
 drivers/gpu/drm/xe/xe_vm.c       |  10 +--
 5 files changed, 152 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 68a0b05f56ec..217e526526e0 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -1875,7 +1875,7 @@ xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
 	}
 
 	xe_migrate_update_pgtables_cpu_execute(vm, m->tile, ops,
-					       pt_update_ops->ops,
+					       pt_update_ops->pt_job_ops->ops,
 					       pt_update_ops->num_ops);
 
 	return dma_fence_get_stub();
@@ -1902,7 +1902,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
 	bool usm = is_migrate && xe->info.has_usm;
 
 	for (i = 0; i < pt_update_ops->num_ops; ++i) {
-		struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[i];
+		struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->pt_job_ops->ops[i];
 		struct xe_vm_pgtable_update *updates = pt_op->entries;
 
 		num_updates += pt_op->num_entries;
@@ -1971,7 +1971,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
 
 			for (; i < pt_update_ops->num_ops; ++i) {
 				struct xe_vm_pgtable_update_op *pt_op =
-					&pt_update_ops->ops[i];
+					&pt_update_ops->pt_job_ops->ops[i];
 				struct xe_vm_pgtable_update *updates = pt_op->entries;
 
 				for (; j < pt_op->num_entries; ++j, ++current_update, ++idx) {
@@ -2008,7 +2008,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
 			(page_ofs / sizeof(u64)) * XE_PAGE_SIZE;
 		for (i = 0; i < pt_update_ops->num_ops; ++i) {
 			struct xe_vm_pgtable_update_op *pt_op =
-				&pt_update_ops->ops[i];
+				&pt_update_ops->pt_job_ops->ops[i];
 			struct xe_vm_pgtable_update *updates = pt_op->entries;
 
 			for (j = 0; j < pt_op->num_entries; ++j) {
@@ -2026,7 +2026,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
 
 		for (i = 0; i < pt_update_ops->num_ops; ++i) {
 			struct xe_vm_pgtable_update_op *pt_op =
-				&pt_update_ops->ops[i];
+				&pt_update_ops->pt_job_ops->ops[i];
 			struct xe_vm_pgtable_update *updates = pt_op->entries;
 
 			for (j = 0; j < pt_op->num_entries; ++j)
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index e560f167fdf1..30127ebf1b60 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -206,6 +206,7 @@ unsigned int xe_pt_shift(unsigned int level)
  */
 void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred)
 {
+	bool added = false;
 	int i;
 
 	if (!pt)
@@ -213,7 +214,19 @@ void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred)
 
 	XE_WARN_ON(!list_empty(&pt->bo->ttm.base.gpuva.list));
 	xe_bo_unpin(pt->bo);
-	xe_bo_put_deferred(pt->bo, deferred, NULL);
+	xe_bo_put_deferred(pt->bo, deferred, &added);
+	if (added) {
+		xe_assert(pt->bo->vm->xe, !kref_read(&pt->bo->ttm.base.refcount));
+
+		/*
+		 * We need the VM present until the BO is destroyed as it shares
+		 * a dma-resv and BO destroy is async. Reinit BO refcount so
+		 * xe_bo_put_async can be used when the PT job ops refcount goes
+		 * to zero.
+		 */
+		xe_vm_get(pt->bo->vm);
+		pt->bo->flags |= XE_BO_FLAG_PUT_VM_ASYNC;
+	}
 
 	if (pt->level > 0 && pt->num_live) {
 		struct xe_pt_dir *pt_dir = as_xe_pt_dir(pt);
@@ -2081,13 +2094,13 @@ xe_pt_commit_prepare_unbind(struct xe_vma *vma,
 static struct xe_vm_pgtable_update_op *
 to_pt_op(struct xe_vm_pgtable_update_ops *pt_update_ops, u32 op_idx)
 {
-	return &pt_update_ops->ops[op_idx];
+	return &pt_update_ops->pt_job_ops->ops[op_idx];
 }
 
 static u32
 get_current_op(struct xe_vm_pgtable_update_ops *pt_update_ops)
 {
-	return pt_update_ops->current_op;
+	return pt_update_ops->pt_job_ops->current_op;
 }
 
 static struct xe_vm_pgtable_update_op *
@@ -2099,7 +2112,7 @@ to_current_pt_op(struct xe_vm_pgtable_update_ops *pt_update_ops)
 static void
 incr_current_op(struct xe_vm_pgtable_update_ops *pt_update_ops)
 {
-	++pt_update_ops->current_op;
+	++pt_update_ops->pt_job_ops->current_op;
 }
 
 static void
@@ -2473,8 +2486,7 @@ static int op_prepare(struct xe_vm *vm,
 static void
 xe_pt_update_ops_init(struct xe_vm_pgtable_update_ops *pt_update_ops)
 {
-	init_llist_head(&pt_update_ops->deferred);
-	pt_update_ops->current_op = 0;
+	pt_update_ops->pt_job_ops->current_op = 0;
 	pt_update_ops->start = ~0x0ull;
 	pt_update_ops->last = 0x0ull;
 	pt_update_ops->needs_svm_lock = false;
@@ -2824,7 +2836,8 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
 			to_pt_op(pt_update_ops, i);
 
 		xe_pt_commit(pt_op->vma, pt_op->entries,
-			     pt_op->num_entries, &pt_update_ops->deferred);
+			     pt_op->num_entries,
+			     &pt_update_ops->pt_job_ops->deferred);
 		pt_op->vma = NULL;	/* skip in xe_pt_update_ops_abort */
 	}
 
@@ -2912,19 +2925,8 @@ void xe_pt_update_ops_fini(struct xe_tile *tile, struct xe_vma_ops *vops)
 {
 	struct xe_vm_pgtable_update_ops *pt_update_ops =
 		&vops->pt_update_ops[tile->id];
-	int i;
 
 	xe_page_reclaim_entries_put(pt_update_ops->prl.entries);
-
-	lockdep_assert_held(&vops->vm->lock);
-	xe_vm_assert_held(vops->vm);
-
-	for (i = 0; i < pt_update_ops->current_op; ++i) {
-		struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[i];
-
-		xe_pt_free_bind(pt_op->entries, pt_op->num_entries);
-	}
-	xe_bo_put_commit(&vops->pt_update_ops[tile->id].deferred);
 }
 
 /**
@@ -2961,3 +2963,101 @@ void xe_pt_update_ops_abort(struct xe_tile *tile, struct xe_vma_ops *vops)
 
 	xe_pt_update_ops_fini(tile, vops);
 }
+
+/**
+ * xe_pt_job_ops_alloc() - Allocate PT job ops
+ * @num_ops: Number of VM PT update ops
+ *
+ * Allocate PT job ops and internal array of VM PT update ops.
+ *
+ * Return: Pointer to PT job ops or NULL
+ */
+struct xe_pt_job_ops *xe_pt_job_ops_alloc(u32 num_ops)
+{
+	struct xe_pt_job_ops *pt_job_ops;
+
+	pt_job_ops = kmalloc_obj(*pt_job_ops);
+	if (!pt_job_ops)
+		return NULL;
+
+	pt_job_ops->ops = kvmalloc_array(num_ops, sizeof(*pt_job_ops->ops),
+					 GFP_KERNEL);
+	if (!pt_job_ops->ops) {
+		kfree(pt_job_ops);
+		return NULL;
+	}
+
+	pt_job_ops->current_op = 0;
+	kref_init(&pt_job_ops->refcount);
+	init_llist_head(&pt_job_ops->deferred);
+
+	return pt_job_ops;
+}
+
+/**
+ * xe_pt_job_ops_get() - Get PT job ops
+ * @pt_job_ops: PT job ops to get
+ *
+ * Take a reference to PT job ops
+ *
+ * Return: Pointer to PT job ops or NULL
+ */
+struct xe_pt_job_ops *xe_pt_job_ops_get(struct xe_pt_job_ops *pt_job_ops)
+{
+	if (pt_job_ops)
+		kref_get(&pt_job_ops->refcount);
+
+	return pt_job_ops;
+}
+
+static void xe_pt_update_ops_free(struct xe_vm_pgtable_update_op *pt_op,
+				  u32 num_ops)
+{
+	u32 i;
+
+	for (i = 0; i < num_ops; ++i, ++pt_op)
+		xe_pt_free_bind(pt_op->entries, pt_op->num_entries);
+}
+
+static void xe_pt_job_ops_destroy(struct kref *ref)
+{
+	struct xe_pt_job_ops *pt_job_ops =
+		container_of(ref, struct xe_pt_job_ops, refcount);
+	struct llist_node *freed;
+	struct xe_bo *bo, *next;
+
+	xe_pt_update_ops_free(pt_job_ops->ops,
+			      pt_job_ops->current_op);
+
+	freed = llist_del_all(&pt_job_ops->deferred);
+	if (freed) {
+		llist_for_each_entry_safe(bo, next, freed, freed) {
+			struct xe_bo_dev *bo_device =
+				&xe_bo_device(bo)->bo_device;
+			/*
+			 * If called from run_job, we are in the dma-fencing
+			 * path and cannot take dma-resv locks so use an async
+			 * put.
+			 */
+			if (llist_add(&bo->freed, &bo_device->async_list))
+				schedule_work(&bo_device->async_free);
+		}
+	}
+
+	kvfree(pt_job_ops->ops);
+	kfree(pt_job_ops);
+}
+
+/**
+ * xe_pt_job_ops_put() - Put PT job ops
+ * @pt_job_ops: PT job ops to put
+ *
+ * Drop a reference to PT job ops
+ */
+void xe_pt_job_ops_put(struct xe_pt_job_ops *pt_job_ops)
+{
+	if (!pt_job_ops)
+		return;
+
+	kref_put(&pt_job_ops->refcount, xe_pt_job_ops_destroy);
+}
diff --git a/drivers/gpu/drm/xe/xe_pt.h b/drivers/gpu/drm/xe/xe_pt.h
index 4daeebaab5a1..5faddb8e700c 100644
--- a/drivers/gpu/drm/xe/xe_pt.h
+++ b/drivers/gpu/drm/xe/xe_pt.h
@@ -49,4 +49,8 @@ bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma);
 bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,
 			  struct xe_svm_range *range);
 
+struct xe_pt_job_ops *xe_pt_job_ops_alloc(u32 num_ops);
+struct xe_pt_job_ops *xe_pt_job_ops_get(struct xe_pt_job_ops *pt_job_ops);
+void xe_pt_job_ops_put(struct xe_pt_job_ops *pt_job_ops);
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h
index a7d1bb708b69..39c5b89ce9b7 100644
--- a/drivers/gpu/drm/xe/xe_pt_types.h
+++ b/drivers/gpu/drm/xe/xe_pt_types.h
@@ -91,12 +91,29 @@ struct xe_vm_pgtable_update_op {
 	bool rebind;
 };
 
+/**
+ * struct xe_pt_job_ops - Page-table update operations (dynamically allocated)
+ *
+ * This is the portion of &struct xe_vma_ops and
+ * &struct xe_vm_pgtable_update_ops that is dynamically allocated, as it
+ * must remain valid until the associated bind job completes. A reference
+ * count controls its lifetime.
+ */
+struct xe_pt_job_ops {
+	/** @current_op: current page-table update operation */
+	u32 current_op;
+	/** @refcount: reference count */
+	struct kref refcount;
+	/** @deferred: list of deferred PT entries to destroy */
+	struct llist_head deferred;
+	/** @ops: page-table update operations */
+	struct xe_vm_pgtable_update_op *ops;
+};
+
 /** struct xe_vm_pgtable_update_ops: page table update operations */
 struct xe_vm_pgtable_update_ops {
-	/** @ops: operations */
-	struct xe_vm_pgtable_update_op *ops;
-	/** @deferred: deferred list to destroy PT entries */
-	struct llist_head deferred;
+	/** @pt_job_ops: PT update operations dynamic allocation*/
+	struct xe_pt_job_ops *pt_job_ops;
 	/** @q: exec queue for PT operations */
 	struct xe_exec_queue *q;
 	/** @prl: embedded page reclaim list */
@@ -107,8 +124,6 @@ struct xe_vm_pgtable_update_ops {
 	u64 last;
 	/** @num_ops: number of operations */
 	u32 num_ops;
-	/** @current_op: current operations */
-	u32 current_op;
 	/** @needs_svm_lock: Needs SVM lock */
 	bool needs_svm_lock;
 	/** @needs_invalidation: Needs invalidation */
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 753a5fc55baa..2737bd25f39a 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -681,11 +681,9 @@ static int xe_vma_ops_alloc(struct xe_vma_ops *vops, bool array_of_binds)
 		if (!vops->pt_update_ops[i].num_ops)
 			continue;
 
-		vops->pt_update_ops[i].ops =
-			kmalloc_objs(*vops->pt_update_ops[i].ops,
-				     vops->pt_update_ops[i].num_ops,
-				     GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
-		if (!vops->pt_update_ops[i].ops)
+		vops->pt_update_ops[i].pt_job_ops =
+			xe_pt_job_ops_alloc(vops->pt_update_ops[i].num_ops);
+		if (!vops->pt_update_ops[i].pt_job_ops)
 			return array_of_binds ? -ENOBUFS : -ENOMEM;
 	}
 
@@ -732,7 +730,7 @@ static void xe_vma_ops_fini(struct xe_vma_ops *vops)
 	xe_vma_svm_prefetch_ops_fini(vops);
 
 	for (i = 0; i < XE_MAX_TILES_PER_DEVICE; ++i)
-		kfree(vops->pt_update_ops[i].ops);
+		xe_pt_job_ops_put(vops->pt_update_ops[i].pt_job_ops);
 }
 
 static void xe_vma_ops_incr_pt_update_ops(struct xe_vma_ops *vops, u8 tile_mask, int inc_val)
-- 
2.34.1

[PATCH v6 10/24] drm/xe: Update GuC submission backend to run PT jobs

[Matthew Brost]

PT jobs bypass GPU execution for the final step of a bind job, using the
CPU to program the required page tables. Teach the GuC submission backend
how to execute these jobs.

PT job submission is implemented in the GuC backend for simplicity. A
follow-up patch could introduce a dedicated backend for PT jobs.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-11-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_guc_submit.c | 37 ++++++++++++++++++++++++++----
 drivers/gpu/drm/xe/xe_migrate.c    | 13 ++++++++++-
 drivers/gpu/drm/xe/xe_migrate.h    |  7 ++++++
 3 files changed, 51 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 8b8673f4e037..b7ec96650405 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -38,9 +38,11 @@
 #include "xe_lrc.h"
 #include "xe_macros.h"
 #include "xe_map.h"
+#include "xe_migrate.h"
 #include "xe_mocs.h"
 #include "xe_module.h"
 #include "xe_pm.h"
+#include "xe_pt.h"
 #include "xe_ring_ops_types.h"
 #include "xe_sched_job.h"
 #include "xe_sleep.h"
@@ -1237,6 +1239,20 @@ static void submit_exec_queue(struct xe_exec_queue *q, struct xe_sched_job *job)
 	}
 }
 
+static bool is_pt_job(struct xe_sched_job *job)
+{
+	return job->is_pt_job;
+}
+
+static void run_pt_job(struct xe_sched_job *job)
+{
+	xe_migrate_update_pgtables_cpu_execute(job->pt_update[0].vm,
+					       job->pt_update[0].tile,
+					       job->pt_update[0].ops,
+					       job->pt_update[0].pt_job_ops->ops,
+					       job->pt_update[0].pt_job_ops->current_op);
+}
+
 static struct dma_fence *
 guc_exec_queue_run_job(struct drm_sched_job *drm_job)
 {
@@ -1262,14 +1278,25 @@ guc_exec_queue_run_job(struct drm_sched_job *drm_job)
 				register_exec_queue(primary, GUC_CONTEXT_NORMAL);
 		}
 
-		if (!exec_queue_registered(q))
-			register_exec_queue(q, GUC_CONTEXT_NORMAL);
-		if (!job->restore_replay)
-			q->ring_ops->emit_job(job);
-		submit_exec_queue(q, job);
+		if (is_pt_job(job)) {
+			xe_gt_assert(guc_to_gt(guc), !exec_queue_registered(q));
+			run_pt_job(job);
+		} else {
+			if (!exec_queue_registered(q))
+				register_exec_queue(q, GUC_CONTEXT_NORMAL);
+			if (!job->restore_replay)
+				q->ring_ops->emit_job(job);
+			submit_exec_queue(q, job);
+		}
 		job->restore_replay = false;
 	}
 
+	if (is_pt_job(job)) {
+		xe_pt_job_ops_put(job->pt_update[0].pt_job_ops);
+		dma_fence_put(job->fence);	/* Drop ref from xe_sched_job_arm */
+		return NULL;
+	}
+
 run_job_out:
 
 	return job->fence;
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 217e526526e0..53160c2c35a6 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -1819,7 +1819,18 @@ struct migrate_test_params {
 	container_of(_priv, struct migrate_test_params, base)
 #endif
 
-static void
+/**
+ * xe_migrate_update_pgtables_cpu_execute() - Update a VM's PTEs via the CPU
+ * @vm: The VM being updated
+ * @tile: The tile being updated
+ * @ops: The migrate PT update ops
+ * @pt_ops: The VM PT update ops
+ * @num_ops: The number of The VM PT update ops
+ *
+ * Execute the VM PT update ops array which results in a VM's PTEs being updated
+ * via the CPU.
+ */
+void
 xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
 				       const struct xe_migrate_pt_update_ops *ops,
 				       struct xe_vm_pgtable_update_op *pt_op,
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 2ec9de896dfe..04ef20692b6a 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -24,6 +24,7 @@ struct xe_pt;
 struct xe_tile;
 struct xe_vm;
 struct xe_vm_pgtable_update;
+struct xe_vm_pgtable_update_op;
 struct xe_vma;
 
 enum xe_sriov_vf_ccs_rw_ctxs;
@@ -163,6 +164,12 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
 
 struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m);
 
+void
+xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
+				       const struct xe_migrate_pt_update_ops *ops,
+				       struct xe_vm_pgtable_update_op *pt_op,
+				       u32 num_ops);
+
 struct dma_fence *
 xe_migrate_update_pgtables(struct xe_migrate *m,
 			   struct xe_migrate_pt_update *pt_update);
-- 
2.34.1

[PATCH v6 11/24] drm/xe: Store level in struct xe_vm_pgtable_update

[Matthew Brost]

The level was previously extracted from struct xe_pt inside
xe_vm_pgtable_update during CPU binds, which always occurred during the
bind IOCTL. With CPU binds now supported in bind jobs, struct xe_pt may
no longer be valid in memory at that point. To address this, store the
level directly in struct xe_vm_pgtable_update.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-12-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_pt.c       | 3 ++-
 drivers/gpu/drm/xe/xe_pt_types.h | 8 +++++++-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 30127ebf1b60..16126ffc2ec1 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -388,6 +388,7 @@ xe_pt_new_shared(struct xe_walk_update *wupd, struct xe_pt *parent,
 	entry->flags = 0;
 	entry->qwords = 0;
 	entry->pt_bo->update_index = -1;
+	entry->level = parent->level;
 
 	if (alloc_entries) {
 		entry->pt_entries = kmalloc_objs(*entry->pt_entries, XE_PDES);
@@ -2025,7 +2026,7 @@ xe_migrate_clear_pgtable_callback(struct xe_vm *vm, struct xe_tile *tile,
 				  u32 qword_ofs, u32 num_qwords,
 				  const struct xe_vm_pgtable_update *update)
 {
-	u64 empty = __xe_pt_empty_pte(tile, vm, update->pt->level);
+	u64 empty = __xe_pt_empty_pte(tile, vm, update->level);
 	int i;
 
 	if (map && map->is_iomem)
diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h
index 39c5b89ce9b7..ccab6613385f 100644
--- a/drivers/gpu/drm/xe/xe_pt_types.h
+++ b/drivers/gpu/drm/xe/xe_pt_types.h
@@ -65,12 +65,18 @@ struct xe_vm_pgtable_update {
 	/** @qwords: number of PTE's to write */
 	u32 qwords;
 
-	/** @pt: opaque pointer useful for the caller of xe_migrate_update_pgtables */
+	/**
+	 * @pt: opaque pointer useful for PT building in the bind IOCTL. Only
+	 * safe to touch during the bind IOCTL (i.e., not in bind jobs).
+	 */
 	struct xe_pt *pt;
 
 	/** @pt_entries: Newly added pagetable entries */
 	struct xe_pt_entry *pt_entries;
 
+	/** @level: level of update */
+	unsigned int level;
+
 	/** @flags: Target flags */
 	u32 flags;
 };
-- 
2.34.1

[PATCH v6 12/24] drm/xe: Don't use migrate exec queue for page fault binds

[Matthew Brost]

Now that the CPU is always used for binds even in jobs, CPU bind jobs
can pass GPU jobs in the same exec queue resulting dma-fences signaling
out-of-order. Use a dedicated exec queue for binds issued from page
faults to avoid ordering issues and avoid blocking kernel binds on
unrelated copies / clears.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-13-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_migrate.c | 47 ++++++++++++++++++++++++++++++---
 drivers/gpu/drm/xe/xe_migrate.h |  1 +
 drivers/gpu/drm/xe/xe_vm.c      | 17 +++++++-----
 3 files changed, 55 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 53160c2c35a6..ba8e195afcc8 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -51,6 +51,8 @@
 struct xe_migrate {
 	/** @q: Default exec queue used for migration */
 	struct xe_exec_queue *q;
+	/** @bind_q: Default exec queue used for binds */
+	struct xe_exec_queue *bind_q;
 	/** @tile: Backpointer to the tile this struct xe_migrate belongs to. */
 	struct xe_tile *tile;
 	/** @job_mutex: Timeline mutex for @eng. */
@@ -115,6 +117,7 @@ static void xe_migrate_fini(void *arg)
 	mutex_destroy(&m->job_mutex);
 	xe_vm_close_and_put(m->q->vm);
 	xe_exec_queue_put(m->q);
+	xe_exec_queue_put(m->bind_q);
 }
 
 static inline u16 xe_migrate_pat_index(struct xe_device *xe,
@@ -504,6 +507,15 @@ int xe_migrate_init(struct xe_migrate *m)
 			goto err_out;
 		}
 
+		m->bind_q = xe_exec_queue_create(xe, vm, logical_mask, 1, hwe0,
+						 EXEC_QUEUE_FLAG_KERNEL |
+						 EXEC_QUEUE_FLAG_HIGH_PRIORITY |
+						 EXEC_QUEUE_FLAG_MIGRATE, 0);
+		if (IS_ERR(m->bind_q)) {
+			err = PTR_ERR(m->bind_q);
+			goto err_out;
+		}
+
 		/*
 		 * XXX: Currently only reserving 1 (likely slow) BCS instance on
 		 * PVC, may want to revisit if performance is needed.
@@ -514,6 +526,15 @@ int xe_migrate_init(struct xe_migrate *m)
 					    EXEC_QUEUE_FLAG_MIGRATE |
 					    EXEC_QUEUE_FLAG_LOW_LATENCY, 0);
 	} else {
+		m->bind_q = xe_exec_queue_create_class(xe, primary_gt, vm,
+						       XE_ENGINE_CLASS_COPY,
+						       EXEC_QUEUE_FLAG_KERNEL |
+						       EXEC_QUEUE_FLAG_MIGRATE, 0);
+		if (IS_ERR(m->bind_q)) {
+			err = PTR_ERR(m->bind_q);
+			goto err_out;
+		}
+
 		m->q = xe_exec_queue_create_class(xe, primary_gt, vm,
 						  XE_ENGINE_CLASS_COPY,
 						  EXEC_QUEUE_FLAG_KERNEL |
@@ -549,6 +570,8 @@ int xe_migrate_init(struct xe_migrate *m)
 	return err;
 
 err_out:
+	if (!IS_ERR_OR_NULL(m->bind_q))
+		xe_exec_queue_put(m->bind_q);
 	xe_vm_close_and_put(vm);
 	return err;
 
@@ -1505,6 +1528,17 @@ static u32 blt_mem_set_cmd_len(struct xe_device *xe)
 	return 7;
 }
 
+/**
+ * xe_get_migrate_bind_queue() - Get the bind queue from migrate context.
+ * @migrate: Migrate context.
+ *
+ * Return: Pointer to bind queue on success, error on failure
+ */
+struct xe_exec_queue *xe_migrate_bind_queue(struct xe_migrate *migrate)
+{
+	return migrate->bind_q;
+}
+
 static void emit_clear_link_copy(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,
 				 u32 size, u32 pitch)
 {
@@ -1892,6 +1926,11 @@ xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
 	return dma_fence_get_stub();
 }
 
+static bool is_migrate_queue(struct xe_migrate *m, struct xe_exec_queue *q)
+{
+	return m->bind_q == q;
+}
+
 static struct dma_fence *
 __xe_migrate_update_pgtables(struct xe_migrate *m,
 			     struct xe_migrate_pt_update *pt_update,
@@ -1909,7 +1948,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
 	u32 num_updates = 0, current_update = 0;
 	u64 addr;
 	int err = 0;
-	bool is_migrate = pt_update_ops->q == m->q;
+	bool is_migrate = is_migrate_queue(m, pt_update_ops->q);
 	bool usm = is_migrate && xe->info.has_usm;
 
 	for (i = 0; i < pt_update_ops->num_ops; ++i) {
@@ -2631,7 +2670,7 @@ int xe_migrate_access_memory(struct xe_migrate *m, struct xe_bo *bo,
  */
 void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue *q)
 {
-	bool is_migrate = q == m->q;
+	bool is_migrate = is_migrate_queue(m, q);
 
 	if (is_migrate)
 		mutex_lock(&m->job_mutex);
@@ -2649,7 +2688,7 @@ void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue *q)
  */
 void xe_migrate_job_unlock(struct xe_migrate *m, struct xe_exec_queue *q)
 {
-	bool is_migrate = q == m->q;
+	bool is_migrate = is_migrate_queue(m, q);
 
 	if (is_migrate)
 		mutex_unlock(&m->job_mutex);
@@ -2666,7 +2705,7 @@ void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
 {
 	struct xe_migrate *m = gt_to_tile(q->gt)->migrate;
 
-	xe_gt_assert(q->gt, q == m->q);
+	xe_gt_assert(q->gt, q == m->bind_q);
 	lockdep_assert_held(&m->job_mutex);
 }
 #endif
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 04ef20692b6a..7a824654cb72 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -146,6 +146,7 @@ void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
 
 struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate);
 struct xe_exec_queue *xe_migrate_exec_queue(struct xe_migrate *migrate);
+struct xe_exec_queue *xe_migrate_bind_queue(struct xe_migrate *migrate);
 struct dma_fence *xe_migrate_vram_copy_chunk(struct xe_bo *vram_bo, u64 vram_offset,
 					     struct xe_bo *sysmem_bo, u64 sysmem_offset,
 					     u64 size, enum xe_migrate_copy_dir dir);
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 2737bd25f39a..13e984ac4e4f 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -795,7 +795,9 @@ int xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)
 	struct xe_vma *vma, *next;
 	struct xe_vma_ops vops;
 	struct xe_vma_op *op, *next_op;
-	int err, i;
+	struct xe_tile *tile;
+	u8 id;
+	int err;
 
 	lockdep_assert_held(&vm->lock);
 	if ((xe_vm_in_lr_mode(vm) && !rebind_worker) ||
@@ -803,8 +805,11 @@ int xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)
 		return 0;
 
 	xe_vma_ops_init(&vops, vm, NULL, NULL, 0);
-	for (i = 0; i < XE_MAX_TILES_PER_DEVICE; ++i)
-		vops.pt_update_ops[i].wait_vm_bookkeep = true;
+	for_each_tile(tile, vm->xe, id) {
+		vops.pt_update_ops[id].wait_vm_bookkeep = true;
+		vops.pt_update_ops[id].q =
+			xe_migrate_bind_queue(tile->migrate);
+	}
 
 	xe_vm_assert_held(vm);
 	list_for_each_entry(vma, &vm->rebind_list, combined_links.rebind) {
@@ -862,7 +867,7 @@ struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_ma
 	for_each_tile(tile, vm->xe, id) {
 		vops.pt_update_ops[id].wait_vm_bookkeep = true;
 		vops.pt_update_ops[tile->id].q =
-			xe_migrate_exec_queue(tile->migrate);
+			xe_migrate_bind_queue(tile->migrate);
 	}
 
 	err = xe_vm_ops_add_rebind(&vops, vma, tile_mask);
@@ -954,7 +959,7 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm,
 	for_each_tile(tile, vm->xe, id) {
 		vops.pt_update_ops[id].wait_vm_bookkeep = true;
 		vops.pt_update_ops[tile->id].q =
-			xe_migrate_exec_queue(tile->migrate);
+			xe_migrate_bind_queue(tile->migrate);
 	}
 
 	err = xe_vm_ops_add_range_rebind(&vops, vma, range, tile_mask);
@@ -1038,7 +1043,7 @@ struct dma_fence *xe_vm_range_unbind(struct xe_vm *vm,
 	for_each_tile(tile, vm->xe, id) {
 		vops.pt_update_ops[id].wait_vm_bookkeep = true;
 		vops.pt_update_ops[tile->id].q =
-			xe_migrate_exec_queue(tile->migrate);
+			xe_migrate_bind_queue(tile->migrate);
 	}
 
 	err = xe_vm_ops_add_range_unbind(&vops, range);
-- 
2.34.1

[PATCH v6 13/24] drm/xe: Enable CPU binds for jobs

[Matthew Brost]

No reason to use the GPU for binds.

Benefits of CPU-based binds:
- Lower latency once dependencies are resolved, as there is no
  interaction with the GuC or a hardware context switch both of which
  are relatively slow.
- Large arrays of binds do not risk running out of migration PTEs,
  avoiding -ENOBUFS being returned to userspace.
- Kernel binds are decoupled from the migration exec queue (which issues
  copies and clears), so they cannot get stuck behind unrelated
  jobs—this can be a problem with parallel GPU faults.
- Paves the for path decouping binds from tiles and individual engines
- Enables ULLS on the migration exec queue, as this queue has exclusive
  access to the paging copy engine.

Update migration layer to formulate a PT job which will issue CPU bind
in the submission backend.

All code related to GPU-based binding has been removed.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-14-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_bo_types.h |   2 -
 drivers/gpu/drm/xe/xe_migrate.c  | 249 +++----------------------------
 drivers/gpu/drm/xe/xe_pt.c       |   1 -
 3 files changed, 17 insertions(+), 235 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index 0eb93052c1d5..8ec4a01a0092 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -90,8 +90,6 @@ struct xe_bo {
 
 	/** @freed: List node for delayed put. */
 	struct llist_node freed;
-	/** @update_index: Update index if PT BO */
-	int update_index;
 	/** @created: Whether the bo has passed initial creation */
 	bool created;
 
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index ba8e195afcc8..e5c46e0fa960 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -77,18 +77,12 @@ struct xe_migrate {
 	 * Protected by @job_mutex.
 	 */
 	struct dma_fence *fence;
-	/**
-	 * @vm_update_sa: For integrated, used to suballocate page-tables
-	 * out of the pt_bo.
-	 */
-	struct drm_suballoc_manager vm_update_sa;
 	/** @min_chunk_size: For dgfx, Minimum chunk size */
 	u64 min_chunk_size;
 };
 
 #define MAX_PREEMPTDISABLE_TRANSFER SZ_8M /* Around 1ms. */
 #define MAX_CCS_LIMITED_TRANSFER SZ_4M /* XE_PAGE_SIZE * (FIELD_MAX(XE2_CCS_SIZE_MASK) + 1) */
-#define NUM_KERNEL_PDE 15
 #define NUM_PT_SLOTS 48
 #define LEVEL0_PAGE_TABLE_ENCODE_SIZE SZ_2M
 #define MAX_NUM_PTE 512
@@ -113,7 +107,6 @@ static void xe_migrate_fini(void *arg)
 
 	dma_fence_put(m->fence);
 	xe_bo_put(m->pt_bo);
-	drm_suballoc_manager_fini(&m->vm_update_sa);
 	mutex_destroy(&m->job_mutex);
 	xe_vm_close_and_put(m->q->vm);
 	xe_exec_queue_put(m->q);
@@ -234,8 +227,6 @@ static int xe_migrate_pt_bo_alloc(struct xe_tile *tile, struct xe_migrate *m,
 	BUILD_BUG_ON(NUM_PT_SLOTS > SZ_2M/XE_PAGE_SIZE);
 	/* Must be a multiple of 64K to support all platforms */
 	BUILD_BUG_ON(NUM_PT_SLOTS * XE_PAGE_SIZE % SZ_64K);
-	/* And one slot reserved for the 4KiB page table updates */
-	BUILD_BUG_ON(!(NUM_KERNEL_PDE & 1));
 
 	/* Need to be sure everything fits in the first PT, or create more */
 	xe_tile_assert(tile, m->batch_base_ofs + xe_bo_size(batch) < SZ_2M);
@@ -391,17 +382,9 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 		}
 	}
 
-	if (ofs)
-		*ofs = map_ofs;
-}
-
-static void xe_migrate_suballoc_manager_init(struct xe_migrate *m, u32 map_ofs)
-{
 	/*
 	 * Example layout created above, with root level = 3:
 	 * [PT0...PT7]: kernel PT's for copy/clear; 64 or 4KiB PTE's
-	 * [PT8]: Kernel PT for VM_BIND, 4 KiB PTE's
-	 * [PT9...PT40]: Userspace PT's for VM_BIND, 4 KiB PTE's
 	 * [PT41 = PDE 0] [PT44...PT47 = 4K and 2M vram identity maps]
 	 *
 	 * This makes the lowest part of the VM point to the pagetables.
@@ -409,19 +392,13 @@ static void xe_migrate_suballoc_manager_init(struct xe_migrate *m, u32 map_ofs)
 	 * and flushes, other parts of the VM can be used either for copying and
 	 * clearing.
 	 *
-	 * For performance, the kernel reserves PDE's, so about 20 are left
-	 * for async VM updates.
-	 *
 	 * To make it easier to work, each scratch PT is put in slot (1 + PT #)
 	 * everywhere, this allows lockless updates to scratch pages by using
 	 * the different addresses in VM.
 	 */
-#define NUM_VMUSA_UNIT_PER_PAGE	32
-#define VM_SA_UPDATE_UNIT_SIZE		(XE_PAGE_SIZE / NUM_VMUSA_UNIT_PER_PAGE)
-#define NUM_VMUSA_WRITES_PER_UNIT	(VM_SA_UPDATE_UNIT_SIZE / sizeof(u64))
-	drm_suballoc_manager_init(&m->vm_update_sa,
-				  (size_t)(map_ofs / XE_PAGE_SIZE - NUM_KERNEL_PDE) *
-				  NUM_VMUSA_UNIT_PER_PAGE, 0);
+
+	if (ofs)
+		*ofs = map_ofs;
 }
 
 static bool xe_migrate_needs_ccs_emit(struct xe_device *xe)
@@ -466,7 +443,6 @@ static int xe_migrate_lock_prepare_vm(struct xe_tile *tile, struct xe_migrate *m
 			return err;
 
 		xe_migrate_prepare_vm(tile, m, vm, &map_ofs);
-		xe_migrate_suballoc_manager_init(m, map_ofs);
 		drm_exec_retry_on_contention(&exec);
 		xe_validation_retry_on_oom(&ctx, &err);
 	}
@@ -1169,6 +1145,9 @@ struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate)
 	return migrate->q->lrc[0];
 }
 
+/* XXX: With CPU binds this can be removed in a follow up */
+#define NUM_KERNEL_PDE 15
+
 static u64 migrate_vm_ppgtt_addr_tlb_inval(void)
 {
 	/*
@@ -1788,56 +1767,6 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
 	return fence;
 }
 
-static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs,
-			  const struct xe_vm_pgtable_update_op *pt_op,
-			  const struct xe_vm_pgtable_update *update,
-			  struct xe_migrate_pt_update *pt_update)
-{
-	const struct xe_migrate_pt_update_ops *ops = pt_update->ops;
-	struct xe_vm *vm = pt_update->vops->vm;
-	u32 chunk;
-	u32 ofs = update->ofs, size = update->qwords;
-
-	/*
-	 * If we have 512 entries (max), we would populate it ourselves,
-	 * and update the PDE above it to the new pointer.
-	 * The only time this can only happen if we have to update the top
-	 * PDE. This requires a BO that is almost vm->size big.
-	 *
-	 * This shouldn't be possible in practice.. might change when 16K
-	 * pages are used. Hence the assert.
-	 */
-	xe_tile_assert(tile, update->qwords < MAX_NUM_PTE);
-	if (!ppgtt_ofs)
-		ppgtt_ofs = xe_migrate_vram_ofs(tile_to_xe(tile),
-						xe_bo_addr(update->pt_bo, 0,
-							   XE_PAGE_SIZE), false);
-
-	do {
-		u64 addr = ppgtt_ofs + ofs * 8;
-
-		chunk = min(size, MAX_PTE_PER_SDI);
-
-		/* Ensure populatefn can do memset64 by aligning bb->cs */
-		if (!(bb->len & 1))
-			bb->cs[bb->len++] = MI_NOOP;
-
-		bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);
-		bb->cs[bb->len++] = lower_32_bits(addr);
-		bb->cs[bb->len++] = upper_32_bits(addr);
-		if (pt_op->bind)
-			ops->populate(tile, NULL, bb->cs + bb->len,
-				      ofs, chunk, update);
-		else
-			ops->clear(vm, tile, NULL, bb->cs + bb->len,
-				   ofs, chunk, update);
-
-		bb->len += chunk * 2;
-		ofs += chunk;
-		size -= chunk;
-	} while (size);
-}
-
 struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m)
 {
 	return xe_vm_get(m->q->vm);
@@ -1938,162 +1867,18 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
 {
 	const struct xe_migrate_pt_update_ops *ops = pt_update->ops;
 	struct xe_tile *tile = m->tile;
-	struct xe_gt *gt = tile->primary_gt;
-	struct xe_device *xe = tile_to_xe(tile);
 	struct xe_sched_job *job;
 	struct dma_fence *fence;
-	struct drm_suballoc *sa_bo = NULL;
-	struct xe_bb *bb;
-	u32 i, j, batch_size = 0, ppgtt_ofs, update_idx, page_ofs = 0;
-	u32 num_updates = 0, current_update = 0;
-	u64 addr;
-	int err = 0;
 	bool is_migrate = is_migrate_queue(m, pt_update_ops->q);
-	bool usm = is_migrate && xe->info.has_usm;
-
-	for (i = 0; i < pt_update_ops->num_ops; ++i) {
-		struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->pt_job_ops->ops[i];
-		struct xe_vm_pgtable_update *updates = pt_op->entries;
-
-		num_updates += pt_op->num_entries;
-		for (j = 0; j < pt_op->num_entries; ++j) {
-			u32 num_cmds = DIV_ROUND_UP(updates[j].qwords,
-						    MAX_PTE_PER_SDI);
-
-			/* align noop + MI_STORE_DATA_IMM cmd prefix */
-			batch_size += 4 * num_cmds + updates[j].qwords * 2;
-		}
-	}
-
-	/* fixed + PTE entries */
-	if (IS_DGFX(xe))
-		batch_size += 2;
-	else
-		batch_size += 6 * (num_updates / MAX_PTE_PER_SDI + 1) +
-			num_updates * 2;
-
-	bb = xe_bb_new(gt, batch_size, usm);
-	if (IS_ERR(bb))
-		return ERR_CAST(bb);
-
-	/* For sysmem PTE's, need to map them in our hole.. */
-	if (!IS_DGFX(xe)) {
-		u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
-		u32 ptes, ofs;
-
-		ppgtt_ofs = NUM_KERNEL_PDE - 1;
-		if (!is_migrate) {
-			u32 num_units = DIV_ROUND_UP(num_updates,
-						     NUM_VMUSA_WRITES_PER_UNIT);
-
-			if (num_units > m->vm_update_sa.size) {
-				err = -ENOBUFS;
-				goto err_bb;
-			}
-			sa_bo = drm_suballoc_new(&m->vm_update_sa, num_units,
-						 GFP_KERNEL, true, 0);
-			if (IS_ERR(sa_bo)) {
-				err = PTR_ERR(sa_bo);
-				goto err_bb;
-			}
-
-			ppgtt_ofs = NUM_KERNEL_PDE +
-				(drm_suballoc_soffset(sa_bo) /
-				 NUM_VMUSA_UNIT_PER_PAGE);
-			page_ofs = (drm_suballoc_soffset(sa_bo) %
-				    NUM_VMUSA_UNIT_PER_PAGE) *
-				VM_SA_UPDATE_UNIT_SIZE;
-		}
-
-		/* Map our PT's to gtt */
-		i = 0;
-		j = 0;
-		ptes = num_updates;
-		ofs = ppgtt_ofs * XE_PAGE_SIZE + page_ofs;
-		while (ptes) {
-			u32 chunk = min(MAX_PTE_PER_SDI, ptes);
-			u32 idx = 0;
-
-			bb->cs[bb->len++] = MI_STORE_DATA_IMM |
-				MI_SDI_NUM_QW(chunk);
-			bb->cs[bb->len++] = ofs;
-			bb->cs[bb->len++] = 0; /* upper_32_bits */
-
-			for (; i < pt_update_ops->num_ops; ++i) {
-				struct xe_vm_pgtable_update_op *pt_op =
-					&pt_update_ops->pt_job_ops->ops[i];
-				struct xe_vm_pgtable_update *updates = pt_op->entries;
-
-				for (; j < pt_op->num_entries; ++j, ++current_update, ++idx) {
-					struct xe_vm *vm = pt_update->vops->vm;
-					struct xe_bo *pt_bo = updates[j].pt_bo;
-
-					if (idx == chunk)
-						goto next_cmd;
-
-					xe_tile_assert(tile, xe_bo_size(pt_bo) == SZ_4K);
-
-					/* Map a PT at most once */
-					if (pt_bo->update_index < 0)
-						pt_bo->update_index = current_update;
-
-					addr = vm->pt_ops->pte_encode_bo(pt_bo, 0,
-									 pat_index, 0);
-					bb->cs[bb->len++] = lower_32_bits(addr);
-					bb->cs[bb->len++] = upper_32_bits(addr);
-				}
-
-				j = 0;
-			}
-
-next_cmd:
-			ptes -= chunk;
-			ofs += chunk * sizeof(u64);
-		}
-
-		bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
-		update_idx = bb->len;
-
-		addr = xe_migrate_vm_addr(ppgtt_ofs, 0) +
-			(page_ofs / sizeof(u64)) * XE_PAGE_SIZE;
-		for (i = 0; i < pt_update_ops->num_ops; ++i) {
-			struct xe_vm_pgtable_update_op *pt_op =
-				&pt_update_ops->pt_job_ops->ops[i];
-			struct xe_vm_pgtable_update *updates = pt_op->entries;
-
-			for (j = 0; j < pt_op->num_entries; ++j) {
-				struct xe_bo *pt_bo = updates[j].pt_bo;
-
-				write_pgtable(tile, bb, addr +
-					      pt_bo->update_index * XE_PAGE_SIZE,
-					      pt_op, &updates[j], pt_update);
-			}
-		}
-	} else {
-		/* phys pages, no preamble required */
-		bb->cs[bb->len++] = MI_BATCH_BUFFER_END;
-		update_idx = bb->len;
-
-		for (i = 0; i < pt_update_ops->num_ops; ++i) {
-			struct xe_vm_pgtable_update_op *pt_op =
-				&pt_update_ops->pt_job_ops->ops[i];
-			struct xe_vm_pgtable_update *updates = pt_op->entries;
-
-			for (j = 0; j < pt_op->num_entries; ++j)
-				write_pgtable(tile, bb, 0, pt_op, &updates[j],
-					      pt_update);
-		}
-	}
+	int err;
 
-	job = xe_bb_create_migration_job(pt_update_ops->q, bb,
-					 xe_migrate_batch_base(m, usm),
-					 update_idx);
+	job = xe_sched_job_create(pt_update_ops->q, NULL);
 	if (IS_ERR(job)) {
 		err = PTR_ERR(job);
-		goto err_sa;
+		goto err_out;
 	}
 
-	xe_sched_job_add_migrate_flush(job, MI_INVALIDATE_TLB);
+	xe_tile_assert(tile, job->is_pt_job);
 
 	if (ops->pre_commit) {
 		pt_update->job = job;
@@ -2104,6 +1889,12 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
 	if (is_migrate)
 		mutex_lock(&m->job_mutex);
 
+	job->pt_update[0].vm = pt_update->vops->vm;
+	job->pt_update[0].tile = tile;
+	job->pt_update[0].ops = ops;
+	job->pt_update[0].pt_job_ops =
+		xe_pt_job_ops_get(pt_update_ops->pt_job_ops);
+
 	xe_sched_job_arm(job);
 	fence = dma_fence_get(&job->drm.s_fence->finished);
 	xe_sched_job_push(job);
@@ -2111,17 +1902,11 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
 	if (is_migrate)
 		mutex_unlock(&m->job_mutex);
 
-	xe_bb_free(bb, fence);
-	drm_suballoc_free(sa_bo, fence);
-
 	return fence;
 
 err_job:
 	xe_sched_job_put(job);
-err_sa:
-	drm_suballoc_free(sa_bo, NULL);
-err_bb:
-	xe_bb_free(bb, NULL);
+err_out:
 	return ERR_PTR(err);
 }
 
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 16126ffc2ec1..24190ba4f533 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -387,7 +387,6 @@ xe_pt_new_shared(struct xe_walk_update *wupd, struct xe_pt *parent,
 	entry->pt = parent;
 	entry->flags = 0;
 	entry->qwords = 0;
-	entry->pt_bo->update_index = -1;
 	entry->level = parent->level;
 
 	if (alloc_entries) {
-- 
2.34.1

[PATCH v6 14/24] drm/xe: Remove unused arguments from xe_migrate_pt_update_ops

[Matthew Brost]

Both populate and clear have unused void* ptr arguments, remove these.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-15-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_migrate.c |  4 ++--
 drivers/gpu/drm/xe/xe_migrate.h |  7 ++-----
 drivers/gpu/drm/xe/xe_pt.c      | 37 ++++++++++++---------------------
 3 files changed, 17 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index e5c46e0fa960..22a442d13477 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -1812,11 +1812,11 @@ xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
 
 			if (pt_op->bind)
 				ops->populate(tile, &update->pt_bo->vmap,
-					      NULL, update->ofs, update->qwords,
+					      update->ofs, update->qwords,
 					      update);
 			else
 				ops->clear(vm, tile, &update->pt_bo->vmap,
-					   NULL, update->ofs, update->qwords,
+					   update->ofs, update->qwords,
 					   update);
 		}
 	}
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 7a824654cb72..74ff6446309c 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -43,7 +43,6 @@ struct xe_migrate_pt_update_ops {
 	 * @populate: Populate a command buffer or page-table with ptes.
 	 * @tile: The tile for the current operation.
 	 * @map: struct iosys_map into the memory to be populated.
-	 * @pos: If @map is NULL, map into the memory to be populated.
 	 * @ofs: qword offset into @map, unused if @map is NULL.
 	 * @num_qwords: Number of qwords to write.
 	 * @update: Information about the PTEs to be inserted.
@@ -53,14 +52,13 @@ struct xe_migrate_pt_update_ops {
 	 * page-tables with PTEs.
 	 */
 	void (*populate)(struct xe_tile *tile, struct iosys_map *map,
-			 void *pos, u32 ofs, u32 num_qwords,
+			 u32 ofs, u32 num_qwords,
 			 const struct xe_vm_pgtable_update *update);
 	/**
 	 * @clear: Clear a command buffer or page-table with ptes.
 	 * @vm: VM being updated
 	 * @tile: The tile for the current operation.
 	 * @map: struct iosys_map into the memory to be populated.
-	 * @pos: If @map is NULL, map into the memory to be populated.
 	 * @ofs: qword offset into @map, unused if @map is NULL.
 	 * @num_qwords: Number of qwords to write.
 	 * @update: Information about the PTEs to be inserted.
@@ -70,8 +68,7 @@ struct xe_migrate_pt_update_ops {
 	 * page-tables with PTEs.
 	 */
 	void (*clear)(struct xe_vm *vm, struct xe_tile *tile,
-		      struct iosys_map *map, void *pos, u32 ofs,
-		      u32 num_qwords,
+		      struct iosys_map *map, u32 ofs, u32 num_qwords,
 		      const struct xe_vm_pgtable_update *update);
 
 	/**
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 24190ba4f533..c17d5f96f00a 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -1106,30 +1106,18 @@ bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,
 
 static void
 xe_vm_populate_pgtable(struct xe_tile *tile, struct iosys_map *map,
-		       void *data, u32 qword_ofs, u32 num_qwords,
+		       u32 qword_ofs, u32 num_qwords,
 		       const struct xe_vm_pgtable_update *update)
 {
 	struct xe_pt_entry *ptes = update->pt_entries;
-	u64 *ptr = data;
 	u32 i;
 
-	/*
-	 * @qword_ofs is the absolute entry offset within the page table, while
-	 * @ptes is indexed relative to @update->ofs (its first entry). The GPU
-	 * path (write_pgtable) splits a single update into MAX_PTE_PER_SDI-sized
-	 * chunks, calling this with an advancing @qword_ofs but a fresh @data
-	 * pointer per chunk, so translate back into a @ptes index rather than
-	 * assuming the chunk starts at ptes[0].
-	 */
-	for (i = 0; i < num_qwords; i++) {
-		u32 idx = qword_ofs - update->ofs + i;
+	xe_assert(tile_to_xe(tile), map);
+	xe_assert(tile_to_xe(tile), !iosys_map_is_null(map));
 
-		if (map)
-			xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *
-				  sizeof(u64), u64, ptes[idx].pte);
-		else
-			ptr[i] = ptes[idx].pte;
-	}
+	for (i = 0; i < num_qwords; i++)
+		xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *
+			  sizeof(u64), u64, ptes[i].pte);
 }
 
 static void xe_pt_cancel_bind(struct xe_vma *vma,
@@ -2021,22 +2009,23 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
 
 static void
 xe_migrate_clear_pgtable_callback(struct xe_vm *vm, struct xe_tile *tile,
-				  struct iosys_map *map, void *ptr,
-				  u32 qword_ofs, u32 num_qwords,
+				  struct iosys_map *map, u32 qword_ofs,
+				  u32 num_qwords,
 				  const struct xe_vm_pgtable_update *update)
 {
 	u64 empty = __xe_pt_empty_pte(tile, vm, update->level);
 	int i;
 
-	if (map && map->is_iomem)
+	xe_assert(vm->xe, map);
+	xe_assert(vm->xe, !iosys_map_is_null(map));
+
+	if (map->is_iomem)
 		for (i = 0; i < num_qwords; ++i)
 			xe_map_wr(tile_to_xe(tile), map, (qword_ofs + i) *
 				  sizeof(u64), u64, empty);
-	else if (map)
+	else
 		memset64(map->vaddr + qword_ofs * sizeof(u64), empty,
 			 num_qwords);
-	else
-		memset64(ptr, empty, num_qwords);
 }
 
 static void xe_pt_abort_unbind(struct xe_vma *vma,
-- 
2.34.1

[PATCH v6 15/24] drm/xe: Make bind queues operate cross-tile

[Matthew Brost]

Since bind jobs execute on the CPU rather than the GPU, maintaining a
per-tile bind queue no longer provides value. Convert the driver to use
a single bind queue shared across tiles. The primary change is routing
all GT TLB invalidations through this unified bind queue.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-16-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_exec_queue.c       | 142 +++++++++--------------
 drivers/gpu/drm/xe/xe_exec_queue.h       |  14 +--
 drivers/gpu/drm/xe/xe_exec_queue_types.h |  20 +---
 drivers/gpu/drm/xe/xe_pt.c               |  22 ++--
 drivers/gpu/drm/xe/xe_sync.c             |  20 +---
 drivers/gpu/drm/xe/xe_tlb_inval_job.c    |  15 ++-
 drivers/gpu/drm/xe/xe_tlb_inval_job.h    |   2 +-
 drivers/gpu/drm/xe/xe_vm.c               |  65 +++++------
 drivers/gpu/drm/xe/xe_vm_types.h         |   2 +-
 9 files changed, 125 insertions(+), 177 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 7bbb31431900..d4c1d0de07b9 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -142,9 +142,8 @@ static void __xe_exec_queue_free(struct xe_exec_queue *q)
 {
 	int i;
 
-	for (i = 0; i < XE_EXEC_QUEUE_TLB_INVAL_COUNT; ++i)
-		if (q->tlb_inval[i].dep_scheduler)
-			xe_dep_scheduler_fini(q->tlb_inval[i].dep_scheduler);
+	for_each_tlb_inval(q, i)
+		xe_dep_scheduler_fini(q->tlb_inval[i].dep_scheduler);
 
 	if (xe_exec_queue_uses_pxp(q))
 		xe_pxp_exec_queue_remove(gt_to_xe(q->gt)->pxp, q);
@@ -166,31 +165,34 @@ static void __xe_exec_queue_free(struct xe_exec_queue *q)
 
 static int alloc_dep_schedulers(struct xe_device *xe, struct xe_exec_queue *q)
 {
-	struct xe_tile *tile = gt_to_tile(q->gt);
-	int i;
+	struct xe_tile *tile;
+	int i = 0, j;
+	u8 id;
 
-	for (i = 0; i < XE_EXEC_QUEUE_TLB_INVAL_COUNT; ++i) {
-		struct xe_dep_scheduler *dep_scheduler;
-		struct xe_gt *gt;
-		struct workqueue_struct *wq;
+	for_each_tile(tile, xe, id) {
+		for (j = 0; j < (XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT + 1); ++j, ++i) {
+			struct xe_dep_scheduler *dep_scheduler;
+			struct xe_gt *gt;
+			struct workqueue_struct *wq;
 
-		if (i == XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT)
-			gt = tile->primary_gt;
-		else
-			gt = tile->media_gt;
+			if (j == XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT)
+				gt = tile->primary_gt;
+			else
+				gt = tile->media_gt;
 
-		if (!gt)
-			continue;
+			if (!gt)
+				continue;
 
-		wq = gt->tlb_inval.job_wq;
+			wq = gt->tlb_inval.job_wq;
 
 #define MAX_TLB_INVAL_JOBS	16	/* Picking a reasonable value */
-		dep_scheduler = xe_dep_scheduler_create(xe, wq, q->name,
-							MAX_TLB_INVAL_JOBS);
-		if (IS_ERR(dep_scheduler))
-			return PTR_ERR(dep_scheduler);
+			dep_scheduler = xe_dep_scheduler_create(xe, wq, q->name,
+								MAX_TLB_INVAL_JOBS);
+			if (IS_ERR(dep_scheduler))
+				return PTR_ERR(dep_scheduler);
 
-		q->tlb_inval[i].dep_scheduler = dep_scheduler;
+			q->tlb_inval[i].dep_scheduler = dep_scheduler;
+		}
 	}
 #undef MAX_TLB_INVAL_JOBS
 
@@ -224,7 +226,6 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
 	q->ops = gt->exec_queue_ops;
 	INIT_LIST_HEAD(&q->lr.link);
 	INIT_LIST_HEAD(&q->vm_exec_queue_link);
-	INIT_LIST_HEAD(&q->multi_gt_link);
 	INIT_LIST_HEAD(&q->hw_engine_group_link);
 	INIT_LIST_HEAD(&q->pxp.link);
 	spin_lock_init(&q->multi_queue.lock);
@@ -636,7 +637,6 @@ ALLOW_ERROR_INJECTION(xe_exec_queue_create_bind, ERRNO);
 void xe_exec_queue_destroy(struct kref *ref)
 {
 	struct xe_exec_queue *q = container_of(ref, struct xe_exec_queue, refcount);
-	struct xe_exec_queue *eq, *next;
 	int i;
 
 	xe_assert(gt_to_xe(q->gt), atomic_read(&q->job_cnt) == 0);
@@ -648,15 +648,9 @@ void xe_exec_queue_destroy(struct kref *ref)
 		xe_pxp_exec_queue_remove(gt_to_xe(q->gt)->pxp, q);
 
 	xe_exec_queue_last_fence_put_unlocked(q);
-	for_each_tlb_inval(i)
+	for_each_tlb_inval(q, i)
 		xe_exec_queue_tlb_inval_last_fence_put_unlocked(q, i);
 
-	if (!(q->flags & EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD)) {
-		list_for_each_entry_safe(eq, next, &q->multi_gt_list,
-					 multi_gt_link)
-			xe_exec_queue_put(eq);
-	}
-
 	if (q->user_vm) {
 		xe_vm_put(q->user_vm);
 		q->user_vm = NULL;
@@ -1343,7 +1337,6 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
 		u64_to_user_ptr(args->instances);
 	struct xe_hw_engine *hwe;
 	struct xe_vm *vm;
-	struct xe_tile *tile;
 	struct xe_exec_queue *q = NULL;
 	u32 logical_mask;
 	u32 flags = 0;
@@ -1392,31 +1385,16 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
 			return -ENOENT;
 		}
 
-		for_each_tile(tile, xe, id) {
-			struct xe_exec_queue *new;
-
-			flags |= EXEC_QUEUE_FLAG_VM;
-			if (id)
-				flags |= EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD;
-
-			new = xe_exec_queue_create_bind(xe, tile, vm, flags,
-							args->extensions);
-			if (IS_ERR(new)) {
-				up_read(&vm->lock);
-				xe_vm_put(vm);
-				err = PTR_ERR(new);
-				if (q)
-					goto put_exec_queue;
-				return err;
-			}
-			if (id == 0)
-				q = new;
-			else
-				list_add_tail(&new->multi_gt_list,
-					      &q->multi_gt_link);
-		}
+		flags |= EXEC_QUEUE_FLAG_VM;
+
+		q = xe_exec_queue_create_bind(xe, xe_device_get_root_tile(xe),
+					      vm, flags, args->extensions);
 		up_read(&vm->lock);
 		xe_vm_put(vm);
+		if (IS_ERR(q)) {
+			err = PTR_ERR(q);
+			return err;
+		}
 	} else {
 		logical_mask = calc_validate_logical_mask(xe, eci,
 							  args->width,
@@ -1638,14 +1616,6 @@ void xe_exec_queue_update_run_ticks(struct xe_exec_queue *q)
  */
 void xe_exec_queue_kill(struct xe_exec_queue *q)
 {
-	struct xe_exec_queue *eq = q, *next;
-
-	list_for_each_entry_safe(eq, next, &eq->multi_gt_list,
-				 multi_gt_link) {
-		q->ops->kill(eq);
-		xe_vm_remove_compute_exec_queue(q->vm, eq);
-	}
-
 	q->ops->kill(q);
 	xe_vm_remove_compute_exec_queue(q->vm, q);
 }
@@ -1806,42 +1776,40 @@ void xe_exec_queue_last_fence_set(struct xe_exec_queue *q, struct xe_vm *vm,
  * xe_exec_queue_tlb_inval_last_fence_put() - Drop ref to last TLB invalidation fence
  * @q: The exec queue
  * @vm: The VM the engine does a bind for
- * @type: Either primary or media GT
+ * @idx: Index of tlb invalidation
  */
 void xe_exec_queue_tlb_inval_last_fence_put(struct xe_exec_queue *q,
 					    struct xe_vm *vm,
-					    unsigned int type)
+					    unsigned int idx)
 {
 	xe_exec_queue_last_fence_lockdep_assert(q, vm);
-	xe_assert(vm->xe, type == XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT ||
-		  type == XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT);
+	xe_assert(vm->xe, idx < XE_EXEC_QUEUE_TLB_INVAL_COUNT);
 
-	xe_exec_queue_tlb_inval_last_fence_put_unlocked(q, type);
+	xe_exec_queue_tlb_inval_last_fence_put_unlocked(q, idx);
 }
 
 /**
  * xe_exec_queue_tlb_inval_last_fence_put_unlocked() - Drop ref to last TLB
  * invalidation fence unlocked
  * @q: The exec queue
- * @type: Either primary or media GT
+ * @idx: Index of tlb invalidation
  *
  * Only safe to be called from xe_exec_queue_destroy().
  */
 void xe_exec_queue_tlb_inval_last_fence_put_unlocked(struct xe_exec_queue *q,
-						     unsigned int type)
+						     unsigned int idx)
 {
-	xe_assert(gt_to_xe(q->gt), type == XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT ||
-		  type == XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT);
+	xe_assert(q->vm->xe, idx < XE_EXEC_QUEUE_TLB_INVAL_COUNT);
 
-	dma_fence_put(q->tlb_inval[type].last_fence);
-	q->tlb_inval[type].last_fence = NULL;
+	dma_fence_put(q->tlb_inval[idx].last_fence);
+	q->tlb_inval[idx].last_fence = NULL;
 }
 
 /**
  * xe_exec_queue_tlb_inval_last_fence_get() - Get last fence for TLB invalidation
  * @q: The exec queue
  * @vm: The VM the engine does a bind for
- * @type: Either primary or media GT
+ * @idx: Index of tlb invalidation
  *
  * Get last fence, takes a ref
  *
@@ -1849,22 +1817,21 @@ void xe_exec_queue_tlb_inval_last_fence_put_unlocked(struct xe_exec_queue *q,
  */
 struct dma_fence *xe_exec_queue_tlb_inval_last_fence_get(struct xe_exec_queue *q,
 							 struct xe_vm *vm,
-							 unsigned int type)
+							 unsigned int idx)
 {
 	struct dma_fence *fence;
 
 	xe_exec_queue_last_fence_lockdep_assert(q, vm);
-	xe_assert(vm->xe, type == XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT ||
-		  type == XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT);
+	xe_assert(vm->xe, idx < XE_EXEC_QUEUE_TLB_INVAL_COUNT);
 	xe_assert(vm->xe, q->flags & (EXEC_QUEUE_FLAG_VM |
 				      EXEC_QUEUE_FLAG_MIGRATE));
 
-	if (q->tlb_inval[type].last_fence &&
+	if (q->tlb_inval[idx].last_fence &&
 	    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
-		     &q->tlb_inval[type].last_fence->flags))
-		xe_exec_queue_tlb_inval_last_fence_put(q, vm, type);
+		     &q->tlb_inval[idx].last_fence->flags))
+		xe_exec_queue_tlb_inval_last_fence_put(q, vm, idx);
 
-	fence = q->tlb_inval[type].last_fence ?: dma_fence_get_stub();
+	fence = q->tlb_inval[idx].last_fence ?: dma_fence_get_stub();
 	dma_fence_get(fence);
 	return fence;
 }
@@ -1874,26 +1841,25 @@ struct dma_fence *xe_exec_queue_tlb_inval_last_fence_get(struct xe_exec_queue *q
  * @q: The exec queue
  * @vm: The VM the engine does a bind for
  * @fence: The fence
- * @type: Either primary or media GT
+ * @idx: Index of tlb invalidation
  *
- * Set the last fence for the tlb invalidation type on the queue. Increases
+ * Set the last fence for the tlb invalidation client on the queue. Increases
  * reference count for fence, when closing queue
  * xe_exec_queue_tlb_inval_last_fence_put should be called.
  */
 void xe_exec_queue_tlb_inval_last_fence_set(struct xe_exec_queue *q,
 					    struct xe_vm *vm,
 					    struct dma_fence *fence,
-					    unsigned int type)
+					    unsigned int idx)
 {
 	xe_exec_queue_last_fence_lockdep_assert(q, vm);
-	xe_assert(vm->xe, type == XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT ||
-		  type == XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT);
+	xe_assert(vm->xe, idx < XE_EXEC_QUEUE_TLB_INVAL_COUNT);
 	xe_assert(vm->xe, q->flags & (EXEC_QUEUE_FLAG_VM |
 				      EXEC_QUEUE_FLAG_MIGRATE));
 	xe_assert(vm->xe, !dma_fence_is_container(fence));
 
-	xe_exec_queue_tlb_inval_last_fence_put(q, vm, type);
-	q->tlb_inval[type].last_fence = dma_fence_get(fence);
+	xe_exec_queue_tlb_inval_last_fence_put(q, vm, idx);
+	q->tlb_inval[idx].last_fence = dma_fence_get(fence);
 }
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h
index 0225426c57b0..b02a390ba989 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue.h
@@ -14,9 +14,9 @@ struct drm_file;
 struct xe_device;
 struct xe_file;
 
-#define for_each_tlb_inval(__i)	\
-	for (__i = XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT; \
-	     __i <= XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT; ++__i)
+#define for_each_tlb_inval(__q, __i)	\
+	for (__i = 0; __i < XE_EXEC_QUEUE_TLB_INVAL_COUNT; ++__i)	\
+		for_each_if((__q)->tlb_inval[__i].dep_scheduler)
 
 struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm,
 					   u32 logical_mask, u16 width,
@@ -141,19 +141,19 @@ void xe_exec_queue_last_fence_set(struct xe_exec_queue *e, struct xe_vm *vm,
 
 void xe_exec_queue_tlb_inval_last_fence_put(struct xe_exec_queue *q,
 					    struct xe_vm *vm,
-					    unsigned int type);
+					    unsigned int idx);
 
 void xe_exec_queue_tlb_inval_last_fence_put_unlocked(struct xe_exec_queue *q,
-						     unsigned int type);
+						     unsigned int idx);
 
 struct dma_fence *xe_exec_queue_tlb_inval_last_fence_get(struct xe_exec_queue *q,
 							 struct xe_vm *vm,
-							 unsigned int type);
+							 unsigned int idx);
 
 void xe_exec_queue_tlb_inval_last_fence_set(struct xe_exec_queue *q,
 					    struct xe_vm *vm,
 					    struct dma_fence *fence,
-					    unsigned int type);
+					    unsigned int idx);
 
 void xe_exec_queue_update_run_ticks(struct xe_exec_queue *q);
 
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index 836f88fc0faa..48c05398b016 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -137,16 +137,14 @@ struct xe_exec_queue {
 #define EXEC_QUEUE_FLAG_KERNEL			BIT(0)
 /* for VM jobs. Caller needs to hold rpm ref when creating queue with this flag */
 #define EXEC_QUEUE_FLAG_VM			BIT(1)
-/* child of VM queue for multi-tile VM jobs */
-#define EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD	BIT(2)
 /* kernel exec_queue only, set priority to highest level */
-#define EXEC_QUEUE_FLAG_HIGH_PRIORITY		BIT(3)
+#define EXEC_QUEUE_FLAG_HIGH_PRIORITY		BIT(2)
 /* flag to indicate low latency hint to guc */
-#define EXEC_QUEUE_FLAG_LOW_LATENCY		BIT(4)
+#define EXEC_QUEUE_FLAG_LOW_LATENCY		BIT(3)
 /* for migration (kernel copy, clear, bind) jobs */
-#define EXEC_QUEUE_FLAG_MIGRATE			BIT(5)
+#define EXEC_QUEUE_FLAG_MIGRATE			BIT(4)
 /* for programming COMMON_SLICE_CHICKEN3 on first submission */
-#define EXEC_QUEUE_FLAG_DISABLE_STATE_CACHE_PERF_FIX	BIT(6)
+#define EXEC_QUEUE_FLAG_DISABLE_STATE_CACHE_PERF_FIX	BIT(5)
 
 	/**
 	 * @flags: flags for this exec queue, should statically setup aside from ban
@@ -157,13 +155,6 @@ struct xe_exec_queue {
 	/** @ban_reason: Bitmask of ban reasons (DRM_XE_EXEC_QUEUE_BAN_REASON_*) */
 	atomic_t ban_reason;
 
-	union {
-		/** @multi_gt_list: list head for VM bind engines if multi-GT */
-		struct list_head multi_gt_list;
-		/** @multi_gt_link: link for VM bind engines if multi-GT */
-		struct list_head multi_gt_link;
-	};
-
 	union {
 		/** @execlist: execlist backend specific state for exec queue */
 		struct xe_execlist_exec_queue *execlist;
@@ -230,7 +221,8 @@ struct xe_exec_queue {
 
 #define XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT	0
 #define XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT	1
-#define XE_EXEC_QUEUE_TLB_INVAL_COUNT		(XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT  + 1)
+#define XE_EXEC_QUEUE_TLB_INVAL_COUNT	\
+	((XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT + 1) * 2)
 
 	/** @tlb_inval: TLB invalidations exec queue state */
 	struct {
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index c17d5f96f00a..bdeffd6f1828 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -2710,12 +2710,18 @@ static const struct xe_migrate_pt_update_ops svm_userptr_migrate_ops;
 #endif
 
 static struct xe_dep_scheduler *to_dep_scheduler(struct xe_exec_queue *q,
-						 struct xe_gt *gt)
+						 struct xe_tile *tile,
+						 struct xe_gt *gt,
+						 unsigned int *type)
 {
+	int tile_ofs = tile->id * (XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT + 1);
+
 	if (xe_gt_is_media_type(gt))
-		return q->tlb_inval[XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT].dep_scheduler;
+		*type = tile_ofs + XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT;
+	else
+		*type = tile_ofs + XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT;
 
-	return q->tlb_inval[XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT].dep_scheduler;
+	return q->tlb_inval[*type].dep_scheduler;
 }
 
 /**
@@ -2740,6 +2746,7 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
 	struct xe_tlb_inval_job *ijob = NULL, *mjob = NULL;
 	struct xe_range_fence *rfence;
 	struct xe_vma_op *op;
+	unsigned int type;
 	int err = 0, i;
 	struct xe_migrate_pt_update update = {
 		.ops = pt_update_ops->needs_svm_lock ?
@@ -2766,13 +2773,13 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
 
 	if (pt_update_ops->needs_invalidation) {
 		struct xe_dep_scheduler *dep_scheduler =
-			to_dep_scheduler(q, tile->primary_gt);
+			to_dep_scheduler(q, tile, tile->primary_gt, &type);
 
 		ijob = xe_tlb_inval_job_create(q, &tile->primary_gt->tlb_inval,
 					       dep_scheduler, vm,
 					       pt_update_ops->start,
 					       pt_update_ops->last,
-					       XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT);
+					       type);
 		if (IS_ERR(ijob)) {
 			err = PTR_ERR(ijob);
 			goto kill_vm_tile1;
@@ -2791,14 +2798,15 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
 		}
 
 		if (tile->media_gt) {
-			dep_scheduler = to_dep_scheduler(q, tile->media_gt);
+			dep_scheduler = to_dep_scheduler(q, tile,
+							 tile->media_gt, &type);
 
 			mjob = xe_tlb_inval_job_create(q,
 						       &tile->media_gt->tlb_inval,
 						       dep_scheduler, vm,
 						       pt_update_ops->start,
 						       pt_update_ops->last,
-						       XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT);
+						       type);
 			if (IS_ERR(mjob)) {
 				err = PTR_ERR(mjob);
 				goto free_ijob;
diff --git a/drivers/gpu/drm/xe/xe_sync.c b/drivers/gpu/drm/xe/xe_sync.c
index 37866768d64c..06b1c913588a 100644
--- a/drivers/gpu/drm/xe/xe_sync.c
+++ b/drivers/gpu/drm/xe/xe_sync.c
@@ -345,15 +345,9 @@ xe_sync_in_fence_get(struct xe_sync_entry *sync, int num_sync,
 			return ERR_PTR(-EOPNOTSUPP);
 
 	if (q->flags & EXEC_QUEUE_FLAG_VM) {
-		struct xe_exec_queue *__q;
-		struct xe_tile *tile;
-		u8 id;
-
-		for_each_tile(tile, vm->xe, id) {
+		num_fence++;
+		for_each_tlb_inval(q, i)
 			num_fence++;
-			for_each_tlb_inval(i)
-				num_fence++;
-		}
 
 		fences = kmalloc_objs(*fences, num_fence);
 		if (!fences)
@@ -361,17 +355,9 @@ xe_sync_in_fence_get(struct xe_sync_entry *sync, int num_sync,
 
 		fences[current_fence++] =
 			xe_exec_queue_last_fence_get(q, vm);
-		for_each_tlb_inval(i)
+		for_each_tlb_inval(q, i)
 			fences[current_fence++] =
 				xe_exec_queue_tlb_inval_last_fence_get(q, vm, i);
-		list_for_each_entry(__q, &q->multi_gt_list,
-				    multi_gt_link) {
-			fences[current_fence++] =
-				xe_exec_queue_last_fence_get(__q, vm);
-			for_each_tlb_inval(i)
-				fences[current_fence++] =
-					xe_exec_queue_tlb_inval_last_fence_get(__q, vm, i);
-		}
 
 		xe_assert(vm->xe, current_fence == num_fence);
 		cf = dma_fence_array_create(num_fence, fences,
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.c b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
index 04d21015cd5d..81f560068d3c 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_job.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
@@ -39,8 +39,8 @@ struct xe_tlb_inval_job {
 	u64 start;
 	/** @end: End address to invalidate */
 	u64 end;
-	/** @type: GT type */
-	int type;
+	/** @idx: Index of tlb invalidation */
+	int idx;
 	/** @fence_armed: Fence has been armed */
 	bool fence_armed;
 };
@@ -87,7 +87,7 @@ static const struct xe_dep_job_ops dep_job_ops = {
  * @vm: VM which TLB invalidation is being issued for
  * @start: Start address to invalidate
  * @end: End address to invalidate
- * @type: GT type
+ * @idx: Index of tlb invalidation
  *
  * Create a TLB invalidation job and initialize internal fields. The caller is
  * responsible for releasing the creation reference.
@@ -97,7 +97,7 @@ static const struct xe_dep_job_ops dep_job_ops = {
 struct xe_tlb_inval_job *
 xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
 			struct xe_dep_scheduler *dep_scheduler,
-			struct xe_vm *vm, u64 start, u64 end, int type)
+			struct xe_vm *vm, u64 start, u64 end, int idx)
 {
 	struct xe_tlb_inval_job *job;
 	struct drm_sched_entity *entity =
@@ -105,8 +105,7 @@ xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
 	struct xe_tlb_inval_fence *ifence;
 	int err;
 
-	xe_assert(vm->xe, type == XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT ||
-		  type == XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT);
+	xe_assert(vm->xe, idx < XE_EXEC_QUEUE_TLB_INVAL_COUNT);
 
 	job = kmalloc_obj(*job);
 	if (!job)
@@ -120,7 +119,7 @@ xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
 	job->fence_armed = false;
 	xe_page_reclaim_list_init(&job->prl);
 	job->dep.ops = &dep_job_ops;
-	job->type = type;
+	job->idx = idx;
 	kref_init(&job->refcount);
 	xe_exec_queue_get(q);	/* Pairs with put in xe_tlb_inval_job_destroy */
 	xe_vm_get(vm);		/* Pairs with put in xe_tlb_inval_job_destroy */
@@ -280,7 +279,7 @@ struct dma_fence *xe_tlb_inval_job_push(struct xe_tlb_inval_job *job,
 	/* Let the upper layers fish this out */
 	xe_exec_queue_tlb_inval_last_fence_set(job->q, job->vm,
 					       &job->dep.drm.s_fence->finished,
-					       job->type);
+					       job->idx);
 
 	xe_migrate_job_unlock(m, job->q);
 
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.h b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
index 03d6e21cd611..2a4478f529e6 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_job.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
@@ -20,7 +20,7 @@ struct xe_vm;
 struct xe_tlb_inval_job *
 xe_tlb_inval_job_create(struct xe_exec_queue *q, struct xe_tlb_inval *tlb_inval,
 			struct xe_dep_scheduler *dep_scheduler,
-			struct xe_vm *vm, u64 start, u64 end, int type);
+			struct xe_vm *vm, u64 start, u64 end, int idx);
 
 void xe_tlb_inval_job_add_page_reclaim(struct xe_tlb_inval_job *job,
 				       struct xe_page_reclaim_list *prl);
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 13e984ac4e4f..433a0a681556 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -1815,7 +1815,7 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
 			struct xe_exec_queue *q;
 			u32 create_flags = EXEC_QUEUE_FLAG_VM;
 
-			if (!vm->pt_root[id])
+			if (!vm->pt_root[id] || vm->q)
 				continue;
 
 			if (!xef) /* Not from userspace */
@@ -1826,7 +1826,7 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
 				err = PTR_ERR(q);
 				goto err_close;
 			}
-			vm->q[id] = q;
+			vm->q = q;
 		}
 	}
 
@@ -1933,24 +1933,18 @@ void xe_vm_close_and_put(struct xe_vm *vm)
 	if (xe_vm_in_fault_mode(vm))
 		xe_svm_close(vm);
 
-	down_write(&vm->lock);
-	for_each_tile(tile, xe, id) {
-		if (vm->q[id]) {
-			int i;
+	if (vm->q) {
+		int i;
 
-			xe_exec_queue_last_fence_put(vm->q[id], vm);
-			for_each_tlb_inval(i)
-				xe_exec_queue_tlb_inval_last_fence_put(vm->q[id], vm, i);
-		}
-	}
-	up_write(&vm->lock);
+		down_write(&vm->lock);
+		xe_exec_queue_last_fence_put(vm->q, vm);
+		for_each_tlb_inval(vm->q, i)
+			xe_exec_queue_tlb_inval_last_fence_put(vm->q, vm, i);
+		up_write(&vm->lock);
 
-	for_each_tile(tile, xe, id) {
-		if (vm->q[id]) {
-			xe_exec_queue_kill(vm->q[id]);
-			xe_exec_queue_put(vm->q[id]);
-			vm->q[id] = NULL;
-		}
+		xe_exec_queue_kill(vm->q);
+		xe_exec_queue_put(vm->q);
+		vm->q = NULL;
 	}
 
 	down_write(&vm->lock);
@@ -2084,7 +2078,7 @@ u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile)
 static struct xe_exec_queue *
 to_wait_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)
 {
-	return q ? q : vm->q[0];
+	return q ? q : vm->q;
 }
 
 static struct xe_user_fence *
@@ -3527,13 +3521,10 @@ static int vm_ops_setup_tile_args(struct xe_vm *vm, struct xe_vma_ops *vops)
 		if (vops->pt_update_ops[id].q)
 			continue;
 
-		if (q) {
+		if (q)
 			vops->pt_update_ops[id].q = q;
-			if (vm->pt_root[id] && !list_empty(&q->multi_gt_list))
-				q = list_next_entry(q, multi_gt_list);
-		} else {
-			vops->pt_update_ops[id].q = vm->q[id];
-		}
+		else
+			vops->pt_update_ops[id].q = vm->q;
 	}
 
 	return number_tiles;
@@ -3553,15 +3544,15 @@ static struct dma_fence *ops_execute(struct xe_vm *vm,
 	if (number_tiles == 0)
 		return ERR_PTR(-ENODATA);
 
-	for_each_tile(tile, vm->xe, id) {
+	for_each_tile(tile, vm->xe, id)
 		++n_fence;
 
-		if (!(vops->flags & XE_VMA_OPS_FLAG_SKIP_TLB_WAIT))
-			for_each_tlb_inval(i)
-				++n_fence;
+	if (!(vops->flags & XE_VMA_OPS_FLAG_SKIP_TLB_WAIT)) {
+		for_each_tlb_inval(vops->pt_update_ops[0].q, i)
+			++n_fence;
 	}
 
-	fences = kmalloc_objs(*fences, n_fence);
+	fences = kcalloc(n_fence, sizeof(*fences), GFP_KERNEL);
 	if (!fences) {
 		fence = ERR_PTR(-ENOMEM);
 		goto err_trace;
@@ -3603,9 +3594,15 @@ static struct dma_fence *ops_execute(struct xe_vm *vm,
 			continue;
 
 		xe_migrate_job_lock(tile->migrate, q);
-		for_each_tlb_inval(i)
-			fences[current_fence++] =
-				xe_exec_queue_tlb_inval_last_fence_get(q, vm, i);
+		for_each_tlb_inval(q, i) {
+			if (i >= (tile->id + 1) * XE_MAX_GT_PER_TILE ||
+			    i < tile->id * XE_MAX_GT_PER_TILE)
+				continue;
+
+			fences[current_fence++] = fence ?
+				xe_exec_queue_tlb_inval_last_fence_get(q, vm, i) :
+				dma_fence_get_stub();
+		}
 		xe_migrate_job_unlock(tile->migrate, q);
 	}
 
@@ -4135,7 +4132,7 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
 
 	syncs_user = u64_to_user_ptr(args->syncs);
 	for (num_syncs = 0; num_syncs < args->num_syncs; num_syncs++) {
-		struct xe_exec_queue *__q = q ?: vm->q[0];
+		struct xe_exec_queue *__q = q ?: vm->q;
 
 		err = xe_sync_entry_parse(xe, xef, &syncs[num_syncs],
 					  &syncs_user[num_syncs],
diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h
index 648031e64145..c91cb13fc4f1 100644
--- a/drivers/gpu/drm/xe/xe_vm_types.h
+++ b/drivers/gpu/drm/xe/xe_vm_types.h
@@ -262,7 +262,7 @@ struct xe_vm {
 	struct xe_device *xe;
 
 	/* exec queue used for (un)binding vma's */
-	struct xe_exec_queue *q[XE_MAX_TILES_PER_DEVICE];
+	struct xe_exec_queue *q;
 
 	/** @lru_bulk_move: Bulk LRU move list for this VM's BOs */
 	struct ttm_lru_bulk_move lru_bulk_move;
-- 
2.34.1

[PATCH v6 16/24] drm/xe: Add CPU bind layer

[Matthew Brost]

With CPU binds, it no longer makes sense to implement CPU bind handling
in the migrate layer, as these operations are entirely decoupled from
hardware. Introduce a dedicated CPU bind layer stored at the device
level.

Since CPU binds are tile-independent, update the PT layer to generate a
single bind job even when pages are mirrored across tiles.

This patch is large because the refactor touches multiple file / layers
and ensures functional equivalence before and after the change.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-17-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/Makefile             |   1 +
 drivers/gpu/drm/xe/xe_cpu_bind.c        | 298 +++++++++++++
 drivers/gpu/drm/xe/xe_cpu_bind.h        | 118 +++++
 drivers/gpu/drm/xe/xe_device.c          |   5 +
 drivers/gpu/drm/xe/xe_device_types.h    |   4 +
 drivers/gpu/drm/xe/xe_exec_queue.c      |   3 +-
 drivers/gpu/drm/xe/xe_guc_submit.c      |  41 +-
 drivers/gpu/drm/xe/xe_migrate.c         | 246 -----------
 drivers/gpu/drm/xe/xe_migrate.h         |  94 ----
 drivers/gpu/drm/xe/xe_pt.c              | 549 ++++++++++++------------
 drivers/gpu/drm/xe/xe_pt.h              |   8 +-
 drivers/gpu/drm/xe/xe_pt_types.h        |  14 -
 drivers/gpu/drm/xe/xe_sched_job.c       |  10 +-
 drivers/gpu/drm/xe/xe_sched_job_types.h |  11 +-
 drivers/gpu/drm/xe/xe_tlb_inval_job.c   |  13 +-
 drivers/gpu/drm/xe/xe_tlb_inval_job.h   |   2 -
 drivers/gpu/drm/xe/xe_vm.c              | 155 ++-----
 drivers/gpu/drm/xe/xe_vm_types.h        |  10 +-
 18 files changed, 813 insertions(+), 769 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_cpu_bind.c
 create mode 100644 drivers/gpu/drm/xe/xe_cpu_bind.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 67b8b5477639..0670a3f08ec8 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -35,6 +35,7 @@ $(obj)/generated/%_device_wa_oob.c $(obj)/generated/%_device_wa_oob.h: $(obj)/xe
 xe-y += xe_bb.o \
 	xe_bo.o \
 	xe_bo_evict.o \
+	xe_cpu_bind.o \
 	xe_dep_scheduler.o \
 	xe_devcoredump.o \
 	xe_device.o \
diff --git a/drivers/gpu/drm/xe/xe_cpu_bind.c b/drivers/gpu/drm/xe/xe_cpu_bind.c
new file mode 100644
index 000000000000..ddfa5fb7b711
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cpu_bind.c
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <drm/drm_managed.h>
+#include <linux/mutex.h>
+
+#include "xe_cpu_bind.h"
+#include "xe_device_types.h"
+#include "xe_exec_queue.h"
+#include "xe_pt.h"
+#include "xe_sched_job.h"
+#include "xe_trace_bo.h"
+#include "xe_vm.h"
+
+/**
+ * struct xe_cpu_bind - cpu_bind context.
+ */
+struct xe_cpu_bind {
+	/** @xe: Xe device */
+	struct xe_device *xe;
+	/** @q: Default exec queue used for kernel binds */
+	struct xe_exec_queue *q;
+	/** @job_mutex: Timeline mutex for @q. */
+	struct mutex job_mutex;
+};
+
+static bool is_cpu_bind_queue(struct xe_cpu_bind *cpu_bind,
+			      struct xe_exec_queue *q)
+{
+	return cpu_bind->q == q;
+}
+
+static void xe_cpu_bind_fini(void *arg)
+{
+	struct xe_cpu_bind *cpu_bind = arg;
+
+	mutex_destroy(&cpu_bind->job_mutex);
+	xe_exec_queue_put(cpu_bind->q);
+}
+
+/**
+ * xe_cpu_bind_init() - Initialize a cpu_bind context
+ * @xe: &xe_device
+ *
+ * Return: 0 if successful, negative error code on failure
+ */
+int xe_cpu_bind_init(struct xe_device *xe)
+{
+	struct xe_cpu_bind *cpu_bind =
+		drmm_kzalloc(&xe->drm, sizeof(*cpu_bind), GFP_KERNEL);
+	struct xe_exec_queue *q;
+
+	if (!cpu_bind)
+		return -ENOMEM;
+
+	q = xe_exec_queue_create_bind(xe, xe_device_get_root_tile(xe), NULL,
+				      EXEC_QUEUE_FLAG_KERNEL |
+				      EXEC_QUEUE_FLAG_MIGRATE, 0);
+	if (IS_ERR(q))
+		return PTR_ERR(q);
+
+	cpu_bind->xe = xe;
+	cpu_bind->q = q;
+	xe->cpu_bind = cpu_bind;
+
+	mutex_init(&cpu_bind->job_mutex);
+
+	fs_reclaim_acquire(GFP_KERNEL);
+	might_lock(&cpu_bind->job_mutex);
+	fs_reclaim_release(GFP_KERNEL);
+
+	return devm_add_action_or_reset(cpu_bind->xe->drm.dev, xe_cpu_bind_fini,
+					cpu_bind);
+}
+
+/**
+ * xe_cpu_bind_queue() - Get the bind queue from cpu_bind context.
+ * @cpu_bind: The cpu bind context.
+ *
+ * Return: Pointer to bind queue on success, error on failure
+ */
+struct xe_exec_queue *xe_cpu_bind_queue(struct xe_cpu_bind *cpu_bind)
+{
+	return cpu_bind->q;
+}
+
+/**
+ * xe_cpu_bind_update_pgtables_execute() - Update a VM's PTEs via the CPU
+ * @vm: The VM being updated
+ * @tile: The tile being updated
+ * @ops: The migrate PT update ops
+ * @pt_op: The VM PT update op
+ * @num_ops: The number of The VM PT update ops
+ *
+ * Execute the VM PT update ops array which results in a VM's PTEs being updated
+ * via the CPU.
+ */
+void
+xe_cpu_bind_update_pgtables_execute(struct xe_vm *vm, struct xe_tile *tile,
+				    const struct xe_cpu_bind_pt_update_ops *ops,
+				    struct xe_vm_pgtable_update_op *pt_op,
+				    u32 num_ops)
+{
+	u32 j, i;
+
+	for (j = 0; j < num_ops; ++j, ++pt_op) {
+		for (i = 0; i < pt_op->num_entries; i++) {
+			const struct xe_vm_pgtable_update *update =
+				&pt_op->entries[i];
+
+			xe_assert(vm->xe, update);
+			xe_assert(vm->xe, update->pt_bo);
+			xe_assert(vm->xe, !iosys_map_is_null(&update->pt_bo->vmap));
+
+			if (pt_op->bind)
+				ops->populate(tile, &update->pt_bo->vmap,
+					      update->ofs, update->qwords,
+					      update);
+			else
+				ops->clear(vm, tile, &update->pt_bo->vmap,
+					   update->ofs, update->qwords,
+					   update);
+		}
+	}
+
+	trace_xe_vm_cpu_bind(vm);
+	xe_device_wmb(vm->xe);
+}
+
+static struct dma_fence *
+xe_cpu_bind_update_pgtables_no_job(struct xe_cpu_bind *cpu_bind,
+				   struct xe_cpu_bind_pt_update *pt_update)
+{
+	const struct xe_cpu_bind_pt_update_ops *ops = pt_update->ops;
+	struct xe_vm *vm = pt_update->vops->vm;
+	struct xe_tile *tile;
+	int err, id;
+
+	if (ops->pre_commit) {
+		pt_update->job = NULL;
+		err = ops->pre_commit(pt_update);
+		if (err)
+			return ERR_PTR(err);
+	}
+
+	for_each_tile(tile, vm->xe, id) {
+		struct xe_vm_pgtable_update_ops *pt_update_ops =
+			&pt_update->vops->pt_update_ops[tile->id];
+
+		if (!pt_update_ops->pt_job_ops)
+			continue;
+
+		xe_cpu_bind_update_pgtables_execute(vm, tile, ops,
+						    pt_update_ops->pt_job_ops->ops,
+						    pt_update_ops->pt_job_ops->current_op);
+	}
+
+	return dma_fence_get_stub();
+}
+
+static struct dma_fence *
+xe_cpu_bind_update_pgtables_job(struct xe_cpu_bind *cpu_bind,
+				struct xe_cpu_bind_pt_update *pt_update)
+{
+	const struct xe_cpu_bind_pt_update_ops *ops = pt_update->ops;
+	struct xe_exec_queue *q = pt_update->vops->q;
+	struct xe_device *xe = cpu_bind->xe;
+	struct xe_sched_job *job;
+	struct dma_fence *fence;
+	struct xe_tile *tile;
+	int err, id;
+	bool is_cpu_bind = is_cpu_bind_queue(cpu_bind, q);
+
+	job = xe_sched_job_create(q, NULL);
+	if (IS_ERR(job))
+		return ERR_CAST(job);
+
+	xe_assert(xe, job->is_pt_job);
+
+	if (ops->pre_commit) {
+		pt_update->job = job;
+		err = ops->pre_commit(pt_update);
+		if (err)
+			goto err_job;
+	}
+
+	if (is_cpu_bind)
+		mutex_lock(&cpu_bind->job_mutex);
+
+	job->pt_update[0].vm = pt_update->vops->vm;
+	job->pt_update[0].ops = ops;
+	for_each_tile(tile, xe, id) {
+		struct xe_vm_pgtable_update_ops *pt_update_ops =
+			&pt_update->vops->pt_update_ops[tile->id];
+
+		job->pt_update[0].pt_job_ops[tile->id] =
+			xe_pt_job_ops_get(pt_update_ops->pt_job_ops);
+	}
+
+	xe_sched_job_arm(job);
+	fence = dma_fence_get(&job->drm.s_fence->finished);
+	xe_sched_job_push(job);
+
+	if (is_cpu_bind)
+		mutex_unlock(&cpu_bind->job_mutex);
+
+	return fence;
+
+err_job:
+	xe_sched_job_put(job);
+	return ERR_PTR(err);
+}
+
+/**
+ * xe_cpu_bind_update_pgtables() - Pipelined page-table update
+ * @cpu_bind: The cpu bind context.
+ * @pt_update: PT update arguments
+ *
+ * Perform a pipelined page-table update. The update descriptors are typically
+ * built under the same lock critical section as a call to this function. If
+ * using the default engine for the updates, they will be performed in the
+ * order they grab the job_mutex. If different engines are used, external
+ * synchronization is needed for overlapping updates to maintain page-table
+ * consistency. Note that the meaning of "overlapping" is that the updates
+ * touch the same page-table, which might be a higher-level page-directory.
+ * If no pipelining is needed, then updates may be performed by the cpu.
+ *
+ * Return: A dma_fence that, when signaled, indicates the update completion.
+ */
+struct dma_fence *
+xe_cpu_bind_update_pgtables(struct xe_cpu_bind *cpu_bind,
+			    struct xe_cpu_bind_pt_update *pt_update)
+{
+	struct dma_fence *fence;
+
+	fence = xe_cpu_bind_update_pgtables_no_job(cpu_bind, pt_update);
+
+	/* -ETIME indicates a job is needed, anything else is legit error */
+	if (!IS_ERR(fence) || PTR_ERR(fence) != -ETIME)
+		return fence;
+
+	return xe_cpu_bind_update_pgtables_job(cpu_bind, pt_update);
+}
+
+/**
+ * xe_cpu_bind_job_lock() - Lock cpu_bind job lock
+ * @cpu_bind: The cpu bind context.
+ * @q: Queue associated with the operation which requires a lock
+ *
+ * Lock the cpu_bind job lock if the queue is a cpu bind queue, otherwise
+ * assert the VM's dma-resv is held (user queue's have own locking).
+ */
+void xe_cpu_bind_job_lock(struct xe_cpu_bind *cpu_bind,
+			  struct xe_exec_queue *q)
+{
+	bool is_cpu_bind = is_cpu_bind_queue(cpu_bind, q);
+
+	if (is_cpu_bind)
+		mutex_lock(&cpu_bind->job_mutex);
+	else
+		xe_vm_assert_held(q->user_vm);	/* User queues VM's should be locked */
+}
+
+/**
+ * xe_cpu_bind_job_unlock() - Unlock cpu_bind job lock
+ * @cpu_bind: The cpu bind context.
+ * @q: Queue associated with the operation which requires a lock
+ *
+ * Unlock the cpu_bind job lock if the queue is a cpu bind queue, otherwise
+ * assert the VM's dma-resv is held (user queue's have own locking).
+ */
+void xe_cpu_bind_job_unlock(struct xe_cpu_bind *cpu_bind,
+			    struct xe_exec_queue *q)
+{
+	bool is_cpu_bind = is_cpu_bind_queue(cpu_bind, q);
+
+	if (is_cpu_bind)
+		mutex_unlock(&cpu_bind->job_mutex);
+	else
+		xe_vm_assert_held(q->user_vm);	/* User queues VM's should be locked */
+}
+
+#if IS_ENABLED(CONFIG_PROVE_LOCKING)
+/**
+ * xe_cpu_bind_job_lock_assert() - Assert cpu_bind job lock held of queue
+ * @q: cpu bind queue
+ */
+void xe_cpu_bind_job_lock_assert(struct xe_exec_queue *q)
+{
+	struct xe_device *xe = gt_to_xe(q->gt);
+	struct xe_cpu_bind *cpu_bind = xe->cpu_bind;
+
+	xe_assert(xe, q == cpu_bind->q);
+	lockdep_assert_held(&cpu_bind->job_mutex);
+}
+#endif
diff --git a/drivers/gpu/drm/xe/xe_cpu_bind.h b/drivers/gpu/drm/xe/xe_cpu_bind.h
new file mode 100644
index 000000000000..815a78b97420
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cpu_bind.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_CPU_BIND_H_
+#define _XE_CPU_BIND_H_
+
+#include <linux/types.h>
+
+struct dma_fence;
+struct iosys_map;
+struct xe_cpu_bind;
+struct xe_cpu_bind_pt_update;
+struct xe_device;
+struct xe_tlb_inval_job;
+struct xe_tile;
+struct xe_vm;
+struct xe_vm_pgtable_update;
+struct xe_vm_pgtable_update_op;
+struct xe_vma_ops;
+
+/**
+ * struct xe_cpu_bind_pt_update_ops - Callbacks for the
+ * xe_cpu_bind_update_pgtables() function.
+ */
+struct xe_cpu_bind_pt_update_ops {
+	/**
+	 * @populate: Populate a command buffer or page-table with ptes.
+	 * @tile: The tile for the current operation.
+	 * @map: struct iosys_map into the memory to be populated.
+	 * @ofs: qword offset into @map, unused if @map is NULL.
+	 * @num_qwords: Number of qwords to write.
+	 * @update: Information about the PTEs to be inserted.
+	 *
+	 * This interface is intended to be used as a callback into the
+	 * page-table system to populate command buffers or shared
+	 * page-tables with PTEs.
+	 */
+	void (*populate)(struct xe_tile *tile, struct iosys_map *map,
+			 u32 ofs, u32 num_qwords,
+			 const struct xe_vm_pgtable_update *update);
+	/**
+	 * @clear: Clear a command buffer or page-table with ptes.
+	 * @vm: VM being updated
+	 * @tile: The tile for the current operation.
+	 * @map: struct iosys_map into the memory to be populated.
+	 * @ofs: qword offset into @map, unused if @map is NULL.
+	 * @num_qwords: Number of qwords to write.
+	 * @update: Information about the PTEs to be inserted.
+	 *
+	 * This interface is intended to be used as a callback into the
+	 * page-table system to populate command buffers or shared
+	 * page-tables with PTEs.
+	 */
+	void (*clear)(struct xe_vm *vm, struct xe_tile *tile,
+		      struct iosys_map *map, u32 ofs, u32 num_qwords,
+		      const struct xe_vm_pgtable_update *update);
+
+	/**
+	 * @pre_commit: Callback to be called just before arming the
+	 * sched_job.
+	 * @pt_update: Pointer to embeddable callback argument.
+	 *
+	 * Return: 0 on success, negative error code on error.
+	 */
+	int (*pre_commit)(struct xe_cpu_bind_pt_update *pt_update);
+};
+
+/**
+ * struct xe_cpu_bind_pt_update - Argument to the struct
+ * xe_cpu_bind_pt_update_ops callbacks.
+ *
+ * Intended to be subclassed to support additional arguments if necessary.
+ */
+struct xe_cpu_bind_pt_update {
+	/** @ops: Pointer to the struct xe_cpu_bind_pt_update_ops callbacks */
+	const struct xe_cpu_bind_pt_update_ops *ops;
+	/** @vops: VMA operations */
+	struct xe_vma_ops *vops;
+	/** @job: The job if a GPU page-table update. NULL otherwise */
+	struct xe_sched_job *job;
+	/**
+	 * @ijobs: The TLB invalidation jobs, individual instances can be NULL
+	 */
+#define XE_CPU_BIND_INVAL_JOB_COUNT	4
+	struct xe_tlb_inval_job *ijobs[XE_CPU_BIND_INVAL_JOB_COUNT];
+};
+
+int xe_cpu_bind_init(struct xe_device *xe);
+
+struct xe_exec_queue *xe_cpu_bind_queue(struct xe_cpu_bind *cpu_bind);
+
+void
+xe_cpu_bind_update_pgtables_execute(struct xe_vm *vm, struct xe_tile *tile,
+				    const struct xe_cpu_bind_pt_update_ops *ops,
+				    struct xe_vm_pgtable_update_op *pt_op,
+				    u32 num_ops);
+
+struct dma_fence *
+xe_cpu_bind_update_pgtables(struct xe_cpu_bind *cpu_bind,
+			    struct xe_cpu_bind_pt_update *pt_update);
+
+void xe_cpu_bind_job_lock(struct xe_cpu_bind *cpu_bind,
+			  struct xe_exec_queue *q);
+
+void xe_cpu_bind_job_unlock(struct xe_cpu_bind *cpu_bind,
+			    struct xe_exec_queue *q);
+
+#if IS_ENABLED(CONFIG_PROVE_LOCKING)
+void xe_cpu_bind_job_lock_assert(struct xe_exec_queue *q);
+#else
+static inline void xe_cpu_bind_job_lock_assert(struct xe_exec_queue *q)
+{
+}
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 8583b2e9ecf4..ade971de1652 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -27,6 +27,7 @@
 #include "xe_bo_evict.h"
 #include "xe_configfs.h"
 #include "xe_debugfs.h"
+#include "xe_cpu_bind.h"
 #include "xe_defaults.h"
 #include "xe_devcoredump.h"
 #include "xe_device_sysfs.h"
@@ -1075,6 +1076,10 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		return err;
 
+	err = xe_cpu_bind_init(xe);
+	if (err)
+		return err;
+
 	err = xe_pagefault_init(xe);
 	if (err)
 		return err;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 180d450a6deb..bc60833c39a7 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -38,6 +38,7 @@
 struct drm_pagemap_shrinker;
 struct intel_display;
 struct intel_dg_nvm_dev;
+struct xe_cpu_bind;
 struct xe_ggtt;
 struct xe_i2c;
 struct xe_pat_ops;
@@ -559,6 +560,9 @@ struct xe_device {
 	/** @sc: System Controller */
 	struct xe_sysctrl sc;
 
+	/** @cpu_bind: CPU bind object */
+	struct xe_cpu_bind *cpu_bind;
+
 	/** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */
 	u32 atomic_svm_timeslice_ms;
 
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index d4c1d0de07b9..d4ae58cb2761 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -14,6 +14,7 @@
 #include <uapi/drm/xe_drm.h>
 
 #include "xe_bo.h"
+#include "xe_cpu_bind.h"
 #include "xe_dep_scheduler.h"
 #include "xe_device.h"
 #include "xe_gt.h"
@@ -1666,7 +1667,7 @@ static void xe_exec_queue_last_fence_lockdep_assert(struct xe_exec_queue *q,
 						    struct xe_vm *vm)
 {
 	if (q->flags & EXEC_QUEUE_FLAG_MIGRATE) {
-		xe_migrate_job_lock_assert(q);
+		xe_cpu_bind_job_lock_assert(q);
 	} else if (q->flags & EXEC_QUEUE_FLAG_VM) {
 		lockdep_assert_held(&vm->lock);
 	} else {
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index b7ec96650405..5e3e911a397b 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -19,6 +19,7 @@
 #include "abi/guc_klvs_abi.h"
 #include "xe_assert.h"
 #include "xe_bo.h"
+#include "xe_cpu_bind.h"
 #include "xe_devcoredump.h"
 #include "xe_device.h"
 #include "xe_exec_queue.h"
@@ -38,7 +39,6 @@
 #include "xe_lrc.h"
 #include "xe_macros.h"
 #include "xe_map.h"
-#include "xe_migrate.h"
 #include "xe_mocs.h"
 #include "xe_module.h"
 #include "xe_pm.h"
@@ -1244,13 +1244,36 @@ static bool is_pt_job(struct xe_sched_job *job)
 	return job->is_pt_job;
 }
 
-static void run_pt_job(struct xe_sched_job *job)
+static void run_pt_job(struct xe_device *xe, struct xe_sched_job *job)
 {
-	xe_migrate_update_pgtables_cpu_execute(job->pt_update[0].vm,
-					       job->pt_update[0].tile,
-					       job->pt_update[0].ops,
-					       job->pt_update[0].pt_job_ops->ops,
-					       job->pt_update[0].pt_job_ops->current_op);
+	struct xe_tile *tile;
+	int id;
+
+	for_each_tile(tile, xe, id) {
+		struct xe_pt_job_ops *pt_job_ops =
+			job->pt_update[0].pt_job_ops[id];
+
+		if (!pt_job_ops || !pt_job_ops->current_op)
+			continue;
+
+		xe_cpu_bind_update_pgtables_execute(job->pt_update[0].vm, tile,
+						    job->pt_update[0].ops,
+						    pt_job_ops->ops,
+						    pt_job_ops->current_op);
+	}
+}
+
+static void put_pt_job(struct xe_device *xe, struct xe_sched_job *job)
+{
+	struct xe_tile *tile;
+	int id;
+
+	for_each_tile(tile, xe, id) {
+		struct xe_pt_job_ops *pt_job_ops =
+			job->pt_update[0].pt_job_ops[id];
+
+		xe_pt_job_ops_put(pt_job_ops);
+	}
 }
 
 static struct dma_fence *
@@ -1280,7 +1303,7 @@ guc_exec_queue_run_job(struct drm_sched_job *drm_job)
 
 		if (is_pt_job(job)) {
 			xe_gt_assert(guc_to_gt(guc), !exec_queue_registered(q));
-			run_pt_job(job);
+			run_pt_job(guc_to_xe(guc), job);
 		} else {
 			if (!exec_queue_registered(q))
 				register_exec_queue(q, GUC_CONTEXT_NORMAL);
@@ -1292,7 +1315,7 @@ guc_exec_queue_run_job(struct drm_sched_job *drm_job)
 	}
 
 	if (is_pt_job(job)) {
-		xe_pt_job_ops_put(job->pt_update[0].pt_job_ops);
+		put_pt_job(guc_to_xe(guc), job);
 		dma_fence_put(job->fence);	/* Drop ref from xe_sched_job_arm */
 		return NULL;
 	}
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 22a442d13477..f7e1a81434b2 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -51,8 +51,6 @@
 struct xe_migrate {
 	/** @q: Default exec queue used for migration */
 	struct xe_exec_queue *q;
-	/** @bind_q: Default exec queue used for binds */
-	struct xe_exec_queue *bind_q;
 	/** @tile: Backpointer to the tile this struct xe_migrate belongs to. */
 	struct xe_tile *tile;
 	/** @job_mutex: Timeline mutex for @eng. */
@@ -110,7 +108,6 @@ static void xe_migrate_fini(void *arg)
 	mutex_destroy(&m->job_mutex);
 	xe_vm_close_and_put(m->q->vm);
 	xe_exec_queue_put(m->q);
-	xe_exec_queue_put(m->bind_q);
 }
 
 static inline u16 xe_migrate_pat_index(struct xe_device *xe,
@@ -483,15 +480,6 @@ int xe_migrate_init(struct xe_migrate *m)
 			goto err_out;
 		}
 
-		m->bind_q = xe_exec_queue_create(xe, vm, logical_mask, 1, hwe0,
-						 EXEC_QUEUE_FLAG_KERNEL |
-						 EXEC_QUEUE_FLAG_HIGH_PRIORITY |
-						 EXEC_QUEUE_FLAG_MIGRATE, 0);
-		if (IS_ERR(m->bind_q)) {
-			err = PTR_ERR(m->bind_q);
-			goto err_out;
-		}
-
 		/*
 		 * XXX: Currently only reserving 1 (likely slow) BCS instance on
 		 * PVC, may want to revisit if performance is needed.
@@ -502,15 +490,6 @@ int xe_migrate_init(struct xe_migrate *m)
 					    EXEC_QUEUE_FLAG_MIGRATE |
 					    EXEC_QUEUE_FLAG_LOW_LATENCY, 0);
 	} else {
-		m->bind_q = xe_exec_queue_create_class(xe, primary_gt, vm,
-						       XE_ENGINE_CLASS_COPY,
-						       EXEC_QUEUE_FLAG_KERNEL |
-						       EXEC_QUEUE_FLAG_MIGRATE, 0);
-		if (IS_ERR(m->bind_q)) {
-			err = PTR_ERR(m->bind_q);
-			goto err_out;
-		}
-
 		m->q = xe_exec_queue_create_class(xe, primary_gt, vm,
 						  XE_ENGINE_CLASS_COPY,
 						  EXEC_QUEUE_FLAG_KERNEL |
@@ -546,8 +525,6 @@ int xe_migrate_init(struct xe_migrate *m)
 	return err;
 
 err_out:
-	if (!IS_ERR_OR_NULL(m->bind_q))
-		xe_exec_queue_put(m->bind_q);
 	xe_vm_close_and_put(vm);
 	return err;
 
@@ -1507,17 +1484,6 @@ static u32 blt_mem_set_cmd_len(struct xe_device *xe)
 	return 7;
 }
 
-/**
- * xe_get_migrate_bind_queue() - Get the bind queue from migrate context.
- * @migrate: Migrate context.
- *
- * Return: Pointer to bind queue on success, error on failure
- */
-struct xe_exec_queue *xe_migrate_bind_queue(struct xe_migrate *migrate)
-{
-	return migrate->bind_q;
-}
-
 static void emit_clear_link_copy(struct xe_gt *gt, struct xe_bb *bb, u64 src_ofs,
 				 u32 size, u32 pitch)
 {
@@ -1782,168 +1748,6 @@ struct migrate_test_params {
 	container_of(_priv, struct migrate_test_params, base)
 #endif
 
-/**
- * xe_migrate_update_pgtables_cpu_execute() - Update a VM's PTEs via the CPU
- * @vm: The VM being updated
- * @tile: The tile being updated
- * @ops: The migrate PT update ops
- * @pt_ops: The VM PT update ops
- * @num_ops: The number of The VM PT update ops
- *
- * Execute the VM PT update ops array which results in a VM's PTEs being updated
- * via the CPU.
- */
-void
-xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
-				       const struct xe_migrate_pt_update_ops *ops,
-				       struct xe_vm_pgtable_update_op *pt_op,
-				       u32 num_ops)
-{
-	u32 j, i;
-
-	for (j = 0; j < num_ops; ++j, ++pt_op) {
-		for (i = 0; i < pt_op->num_entries; i++) {
-			const struct xe_vm_pgtable_update *update =
-				&pt_op->entries[i];
-
-			xe_tile_assert(tile, update);
-			xe_tile_assert(tile, update->pt_bo);
-			xe_tile_assert(tile, !iosys_map_is_null(&update->pt_bo->vmap));
-
-			if (pt_op->bind)
-				ops->populate(tile, &update->pt_bo->vmap,
-					      update->ofs, update->qwords,
-					      update);
-			else
-				ops->clear(vm, tile, &update->pt_bo->vmap,
-					   update->ofs, update->qwords,
-					   update);
-		}
-	}
-
-	trace_xe_vm_cpu_bind(vm);
-	xe_device_wmb(vm->xe);
-}
-
-static struct dma_fence *
-xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
-			       struct xe_migrate_pt_update *pt_update)
-{
-	XE_TEST_DECLARE(struct migrate_test_params *test =
-			to_migrate_test_params
-			(xe_cur_kunit_priv(XE_TEST_LIVE_MIGRATE));)
-	const struct xe_migrate_pt_update_ops *ops = pt_update->ops;
-	struct xe_vm *vm = pt_update->vops->vm;
-	struct xe_vm_pgtable_update_ops *pt_update_ops =
-		&pt_update->vops->pt_update_ops[pt_update->tile_id];
-	int err;
-
-	if (XE_TEST_ONLY(test && test->force_gpu))
-		return ERR_PTR(-ETIME);
-
-	if (ops->pre_commit) {
-		pt_update->job = NULL;
-		err = ops->pre_commit(pt_update);
-		if (err)
-			return ERR_PTR(err);
-	}
-
-	xe_migrate_update_pgtables_cpu_execute(vm, m->tile, ops,
-					       pt_update_ops->pt_job_ops->ops,
-					       pt_update_ops->num_ops);
-
-	return dma_fence_get_stub();
-}
-
-static bool is_migrate_queue(struct xe_migrate *m, struct xe_exec_queue *q)
-{
-	return m->bind_q == q;
-}
-
-static struct dma_fence *
-__xe_migrate_update_pgtables(struct xe_migrate *m,
-			     struct xe_migrate_pt_update *pt_update,
-			     struct xe_vm_pgtable_update_ops *pt_update_ops)
-{
-	const struct xe_migrate_pt_update_ops *ops = pt_update->ops;
-	struct xe_tile *tile = m->tile;
-	struct xe_sched_job *job;
-	struct dma_fence *fence;
-	bool is_migrate = is_migrate_queue(m, pt_update_ops->q);
-	int err;
-
-	job = xe_sched_job_create(pt_update_ops->q, NULL);
-	if (IS_ERR(job)) {
-		err = PTR_ERR(job);
-		goto err_out;
-	}
-
-	xe_tile_assert(tile, job->is_pt_job);
-
-	if (ops->pre_commit) {
-		pt_update->job = job;
-		err = ops->pre_commit(pt_update);
-		if (err)
-			goto err_job;
-	}
-	if (is_migrate)
-		mutex_lock(&m->job_mutex);
-
-	job->pt_update[0].vm = pt_update->vops->vm;
-	job->pt_update[0].tile = tile;
-	job->pt_update[0].ops = ops;
-	job->pt_update[0].pt_job_ops =
-		xe_pt_job_ops_get(pt_update_ops->pt_job_ops);
-
-	xe_sched_job_arm(job);
-	fence = dma_fence_get(&job->drm.s_fence->finished);
-	xe_sched_job_push(job);
-
-	if (is_migrate)
-		mutex_unlock(&m->job_mutex);
-
-	return fence;
-
-err_job:
-	xe_sched_job_put(job);
-err_out:
-	return ERR_PTR(err);
-}
-
-/**
- * xe_migrate_update_pgtables() - Pipelined page-table update
- * @m: The migrate context.
- * @pt_update: PT update arguments
- *
- * Perform a pipelined page-table update. The update descriptors are typically
- * built under the same lock critical section as a call to this function. If
- * using the default engine for the updates, they will be performed in the
- * order they grab the job_mutex. If different engines are used, external
- * synchronization is needed for overlapping updates to maintain page-table
- * consistency. Note that the meaning of "overlapping" is that the updates
- * touch the same page-table, which might be a higher-level page-directory.
- * If no pipelining is needed, then updates may be performed by the cpu.
- *
- * Return: A dma_fence that, when signaled, indicates the update completion.
- */
-struct dma_fence *
-xe_migrate_update_pgtables(struct xe_migrate *m,
-			   struct xe_migrate_pt_update *pt_update)
-
-{
-	struct xe_vm_pgtable_update_ops *pt_update_ops =
-		&pt_update->vops->pt_update_ops[pt_update->tile_id];
-	struct dma_fence *fence;
-
-	fence =  xe_migrate_update_pgtables_cpu(m, pt_update);
-
-	/* -ETIME indicates a job is needed, anything else is legit error */
-	if (!IS_ERR(fence) || PTR_ERR(fence) != -ETIME)
-		return fence;
-
-	return __xe_migrate_update_pgtables(m, pt_update, pt_update_ops);
-}
-
 /**
  * xe_migrate_wait() - Complete all operations using the xe_migrate context
  * @m: Migrate context to wait for.
@@ -2445,56 +2249,6 @@ int xe_migrate_access_memory(struct xe_migrate *m, struct xe_bo *bo,
 	return IS_ERR(fence) ? PTR_ERR(fence) : 0;
 }
 
-/**
- * xe_migrate_job_lock() - Lock migrate job lock
- * @m: The migration context.
- * @q: Queue associated with the operation which requires a lock
- *
- * Lock the migrate job lock if the queue is a migration queue, otherwise
- * assert the VM's dma-resv is held (user queue's have own locking).
- */
-void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue *q)
-{
-	bool is_migrate = is_migrate_queue(m, q);
-
-	if (is_migrate)
-		mutex_lock(&m->job_mutex);
-	else
-		xe_vm_assert_held(q->user_vm);	/* User queues VM's should be locked */
-}
-
-/**
- * xe_migrate_job_unlock() - Unlock migrate job lock
- * @m: The migration context.
- * @q: Queue associated with the operation which requires a lock
- *
- * Unlock the migrate job lock if the queue is a migration queue, otherwise
- * assert the VM's dma-resv is held (user queue's have own locking).
- */
-void xe_migrate_job_unlock(struct xe_migrate *m, struct xe_exec_queue *q)
-{
-	bool is_migrate = is_migrate_queue(m, q);
-
-	if (is_migrate)
-		mutex_unlock(&m->job_mutex);
-	else
-		xe_vm_assert_held(q->user_vm);	/* User queues VM's should be locked */
-}
-
-#if IS_ENABLED(CONFIG_PROVE_LOCKING)
-/**
- * xe_migrate_job_lock_assert() - Assert migrate job lock held of queue
- * @q: Migrate queue
- */
-void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
-{
-	struct xe_migrate *m = gt_to_tile(q->gt)->migrate;
-
-	xe_gt_assert(q->gt, q == m->bind_q);
-	lockdep_assert_held(&m->job_mutex);
-}
-#endif
-
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 #include "tests/xe_migrate.c"
 #endif
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 74ff6446309c..fa381ec36ef1 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -34,78 +34,6 @@ enum xe_migrate_copy_dir {
 	XE_MIGRATE_COPY_TO_SRAM,
 };
 
-/**
- * struct xe_migrate_pt_update_ops - Callbacks for the
- * xe_migrate_update_pgtables() function.
- */
-struct xe_migrate_pt_update_ops {
-	/**
-	 * @populate: Populate a command buffer or page-table with ptes.
-	 * @tile: The tile for the current operation.
-	 * @map: struct iosys_map into the memory to be populated.
-	 * @ofs: qword offset into @map, unused if @map is NULL.
-	 * @num_qwords: Number of qwords to write.
-	 * @update: Information about the PTEs to be inserted.
-	 *
-	 * This interface is intended to be used as a callback into the
-	 * page-table system to populate command buffers or shared
-	 * page-tables with PTEs.
-	 */
-	void (*populate)(struct xe_tile *tile, struct iosys_map *map,
-			 u32 ofs, u32 num_qwords,
-			 const struct xe_vm_pgtable_update *update);
-	/**
-	 * @clear: Clear a command buffer or page-table with ptes.
-	 * @vm: VM being updated
-	 * @tile: The tile for the current operation.
-	 * @map: struct iosys_map into the memory to be populated.
-	 * @ofs: qword offset into @map, unused if @map is NULL.
-	 * @num_qwords: Number of qwords to write.
-	 * @update: Information about the PTEs to be inserted.
-	 *
-	 * This interface is intended to be used as a callback into the
-	 * page-table system to populate command buffers or shared
-	 * page-tables with PTEs.
-	 */
-	void (*clear)(struct xe_vm *vm, struct xe_tile *tile,
-		      struct iosys_map *map, u32 ofs, u32 num_qwords,
-		      const struct xe_vm_pgtable_update *update);
-
-	/**
-	 * @pre_commit: Callback to be called just before arming the
-	 * sched_job.
-	 * @pt_update: Pointer to embeddable callback argument.
-	 *
-	 * Return: 0 on success, negative error code on error.
-	 */
-	int (*pre_commit)(struct xe_migrate_pt_update *pt_update);
-};
-
-/**
- * struct xe_migrate_pt_update - Argument to the
- * struct xe_migrate_pt_update_ops callbacks.
- *
- * Intended to be subclassed to support additional arguments if necessary.
- */
-struct xe_migrate_pt_update {
-	/** @ops: Pointer to the struct xe_migrate_pt_update_ops callbacks */
-	const struct xe_migrate_pt_update_ops *ops;
-	/** @vops: VMA operations */
-	struct xe_vma_ops *vops;
-	/** @job: The job if a GPU page-table update. NULL otherwise */
-	struct xe_sched_job *job;
-	/**
-	 * @ijob: The TLB invalidation job for primary GT. NULL otherwise
-	 */
-	struct xe_tlb_inval_job *ijob;
-	/**
-	 * @mjob: The TLB invalidation job for media GT. NULL otherwise
-	 */
-	struct xe_tlb_inval_job *mjob;
-	/** @tile_id: Tile ID of the update */
-	u8 tile_id;
-};
-
 struct xe_migrate *xe_migrate_alloc(struct xe_tile *tile);
 int xe_migrate_init(struct xe_migrate *m);
 
@@ -143,7 +71,6 @@ void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
 
 struct xe_lrc *xe_migrate_lrc(struct xe_migrate *migrate);
 struct xe_exec_queue *xe_migrate_exec_queue(struct xe_migrate *migrate);
-struct xe_exec_queue *xe_migrate_bind_queue(struct xe_migrate *migrate);
 struct dma_fence *xe_migrate_vram_copy_chunk(struct xe_bo *vram_bo, u64 vram_offset,
 					     struct xe_bo *sysmem_bo, u64 sysmem_offset,
 					     u64 size, enum xe_migrate_copy_dir dir);
@@ -162,29 +89,8 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
 
 struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m);
 
-void
-xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
-				       const struct xe_migrate_pt_update_ops *ops,
-				       struct xe_vm_pgtable_update_op *pt_op,
-				       u32 num_ops);
-
-struct dma_fence *
-xe_migrate_update_pgtables(struct xe_migrate *m,
-			   struct xe_migrate_pt_update *pt_update);
-
 void xe_migrate_wait(struct xe_migrate *m);
 
-#if IS_ENABLED(CONFIG_PROVE_LOCKING)
-void xe_migrate_job_lock_assert(struct xe_exec_queue *q);
-#else
-static inline void xe_migrate_job_lock_assert(struct xe_exec_queue *q)
-{
-}
-#endif
-
-void xe_migrate_job_lock(struct xe_migrate *m, struct xe_exec_queue *q);
-void xe_migrate_job_unlock(struct xe_migrate *m, struct xe_exec_queue *q);
-
 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
 int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
 				 struct xe_bo *scratch_bo,
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index bdeffd6f1828..05bbac6c2632 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -7,12 +7,12 @@
 
 #include "regs/xe_gtt_defs.h"
 #include "xe_bo.h"
+#include "xe_cpu_bind.h"
 #include "xe_device.h"
 #include "xe_drm_client.h"
 #include "xe_exec_queue.h"
 #include "xe_gt.h"
 #include "xe_gt_stats.h"
-#include "xe_migrate.h"
 #include "xe_page_reclaim.h"
 #include "xe_pat.h"
 #include "xe_pt_types.h"
@@ -1401,11 +1401,9 @@ static int op_add_deps(struct xe_vm *vm, struct xe_vma_op *op,
 }
 
 static int xe_pt_vm_dependencies(struct xe_sched_job *job,
-				 struct xe_tlb_inval_job *ijob,
-				 struct xe_tlb_inval_job *mjob,
+				 struct xe_tlb_inval_job **ijobs,
 				 struct xe_vm *vm,
 				 struct xe_vma_ops *vops,
-				 struct xe_vm_pgtable_update_ops *pt_update_ops,
 				 struct xe_range_fence_tree *rftree)
 {
 	struct xe_range_fence *rtfence;
@@ -1418,20 +1416,22 @@ static int xe_pt_vm_dependencies(struct xe_sched_job *job,
 	if (!job && !no_in_syncs(vops->syncs, vops->num_syncs))
 		return -ETIME;
 
-	if (!job && !xe_exec_queue_is_idle(pt_update_ops->q))
+	if (!job && !xe_exec_queue_is_idle(vops->q))
 		return -ETIME;
 
-	if (pt_update_ops->wait_vm_bookkeep || pt_update_ops->wait_vm_kernel) {
-		err = job_test_add_deps(job, xe_vm_resv(vm),
-					pt_update_ops->wait_vm_bookkeep ?
-					DMA_RESV_USAGE_BOOKKEEP :
-					DMA_RESV_USAGE_KERNEL);
+	if (vops->flags & (XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP |
+			   XE_VMA_OPS_FLAG_WAIT_VM_KERNEL)) {
+		enum dma_resv_usage usage = DMA_RESV_USAGE_KERNEL;
+
+		if (vops->flags & XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP)
+			usage = DMA_RESV_USAGE_BOOKKEEP;
+
+		err = job_test_add_deps(job, xe_vm_resv(vm), usage);
 		if (err)
 			return err;
 	}
 
-	rtfence = xe_range_fence_tree_first(rftree, pt_update_ops->start,
-					    pt_update_ops->last);
+	rtfence = xe_range_fence_tree_first(rftree, vops->start, vops->last);
 	while (rtfence) {
 		fence = rtfence->fence;
 
@@ -1449,9 +1449,8 @@ static int xe_pt_vm_dependencies(struct xe_sched_job *job,
 				return err;
 		}
 
-		rtfence = xe_range_fence_tree_next(rtfence,
-						   pt_update_ops->start,
-						   pt_update_ops->last);
+		rtfence = xe_range_fence_tree_next(rtfence, vops->start,
+						   vops->last);
 	}
 
 	list_for_each_entry(op, &vops->list, link) {
@@ -1464,14 +1463,11 @@ static int xe_pt_vm_dependencies(struct xe_sched_job *job,
 		err = xe_sync_entry_add_deps(&vops->syncs[i], job);
 
 	if (job) {
-		if (ijob) {
-			err = xe_tlb_inval_job_alloc_dep(ijob);
-			if (err)
-				return err;
-		}
+		for (i = 0; i < XE_CPU_BIND_INVAL_JOB_COUNT; ++i) {
+			if (!ijobs[i])
+				continue;
 
-		if (mjob) {
-			err = xe_tlb_inval_job_alloc_dep(mjob);
+			err = xe_tlb_inval_job_alloc_dep(ijobs[i]);
 			if (err)
 				return err;
 		}
@@ -1480,17 +1476,14 @@ static int xe_pt_vm_dependencies(struct xe_sched_job *job,
 	return err;
 }
 
-static int xe_pt_pre_commit(struct xe_migrate_pt_update *pt_update)
+static int xe_pt_pre_commit(struct xe_cpu_bind_pt_update *pt_update)
 {
 	struct xe_vma_ops *vops = pt_update->vops;
 	struct xe_vm *vm = vops->vm;
-	struct xe_range_fence_tree *rftree = &vm->rftree[pt_update->tile_id];
-	struct xe_vm_pgtable_update_ops *pt_update_ops =
-		&vops->pt_update_ops[pt_update->tile_id];
+	struct xe_range_fence_tree *rftree = &vm->rftree;
 
-	return xe_pt_vm_dependencies(pt_update->job, pt_update->ijob,
-				     pt_update->mjob, vm, pt_update->vops,
-				     pt_update_ops, rftree);
+	return xe_pt_vm_dependencies(pt_update->job, pt_update->ijobs,
+				     vm, vops, rftree);
 }
 
 #if IS_ENABLED(CONFIG_DRM_GPUSVM)
@@ -1550,8 +1543,7 @@ static bool xe_pt_userptr_inject_eagain(struct xe_userptr_vma *uvma)
 
 #endif
 
-static int vma_check_userptr(struct xe_vm *vm, struct xe_vma *vma,
-			     struct xe_vm_pgtable_update_ops *pt_update)
+static int vma_check_userptr(struct xe_vm *vm, struct xe_vma *vma)
 {
 	struct xe_userptr_vma *uvma;
 	unsigned long notifier_seq;
@@ -1581,8 +1573,7 @@ static int vma_check_userptr(struct xe_vm *vm, struct xe_vma *vma,
 	return 0;
 }
 
-static int op_check_svm_userptr(struct xe_vm *vm, struct xe_vma_op *op,
-				struct xe_vm_pgtable_update_ops *pt_update)
+static int op_check_svm_userptr(struct xe_vm *vm, struct xe_vma_op *op)
 {
 	int err = 0;
 
@@ -1593,13 +1584,13 @@ static int op_check_svm_userptr(struct xe_vm *vm, struct xe_vma_op *op,
 		if (!op->map.immediate && xe_vm_in_fault_mode(vm))
 			break;
 
-		err = vma_check_userptr(vm, op->map.vma, pt_update);
+		err = vma_check_userptr(vm, op->map.vma);
 		break;
 	case DRM_GPUVA_OP_REMAP:
 		if (op->remap.prev && !op->remap.skip_prev)
-			err = vma_check_userptr(vm, op->remap.prev, pt_update);
+			err = vma_check_userptr(vm, op->remap.prev);
 		if (!err && op->remap.next && !op->remap.skip_next)
-			err = vma_check_userptr(vm, op->remap.next, pt_update);
+			err = vma_check_userptr(vm, op->remap.next);
 		break;
 	case DRM_GPUVA_OP_UNMAP:
 		break;
@@ -1619,7 +1610,7 @@ static int op_check_svm_userptr(struct xe_vm *vm, struct xe_vma_op *op,
 				}
 			}
 		} else {
-			err = vma_check_userptr(vm, gpuva_to_vma(op->base.prefetch.va), pt_update);
+			err = vma_check_userptr(vm, gpuva_to_vma(op->base.prefetch.va));
 		}
 		break;
 #if IS_ENABLED(CONFIG_DRM_XE_GPUSVM)
@@ -1645,12 +1636,10 @@ static int op_check_svm_userptr(struct xe_vm *vm, struct xe_vma_op *op,
 	return err;
 }
 
-static int xe_pt_svm_userptr_pre_commit(struct xe_migrate_pt_update *pt_update)
+static int xe_pt_svm_userptr_pre_commit(struct xe_cpu_bind_pt_update *pt_update)
 {
 	struct xe_vm *vm = pt_update->vops->vm;
 	struct xe_vma_ops *vops = pt_update->vops;
-	struct xe_vm_pgtable_update_ops *pt_update_ops =
-		&vops->pt_update_ops[pt_update->tile_id];
 	struct xe_vma_op *op;
 	int err;
 
@@ -1661,7 +1650,7 @@ static int xe_pt_svm_userptr_pre_commit(struct xe_migrate_pt_update *pt_update)
 	xe_pt_svm_userptr_notifier_lock(vm);
 
 	list_for_each_entry(op, &vops->list, link) {
-		err = op_check_svm_userptr(vm, op, pt_update_ops);
+		err = op_check_svm_userptr(vm, op);
 		if (err) {
 			xe_pt_svm_userptr_notifier_unlock(vm);
 			break;
@@ -2008,10 +1997,10 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
 }
 
 static void
-xe_migrate_clear_pgtable_callback(struct xe_vm *vm, struct xe_tile *tile,
-				  struct iosys_map *map, u32 qword_ofs,
-				  u32 num_qwords,
-				  const struct xe_vm_pgtable_update *update)
+xe_pt_clear_pgtable_callback(struct xe_vm *vm, struct xe_tile *tile,
+			     struct iosys_map *map, u32 qword_ofs,
+			     u32 num_qwords,
+			     const struct xe_vm_pgtable_update *update)
 {
 	u64 empty = __xe_pt_empty_pte(tile, vm, update->level);
 	int i;
@@ -2089,6 +2078,9 @@ to_pt_op(struct xe_vm_pgtable_update_ops *pt_update_ops, u32 op_idx)
 static u32
 get_current_op(struct xe_vm_pgtable_update_ops *pt_update_ops)
 {
+	if (!pt_update_ops->pt_job_ops)
+		return 0;
+
 	return pt_update_ops->pt_job_ops->current_op;
 }
 
@@ -2378,6 +2370,7 @@ static int unbind_range_prepare(struct xe_vm *vm,
 
 static int op_prepare(struct xe_vm *vm,
 		      struct xe_tile *tile,
+		      struct xe_vma_ops *vops,
 		      struct xe_vm_pgtable_update_ops *pt_update_ops,
 		      struct xe_vma_op *op)
 {
@@ -2394,7 +2387,7 @@ static int op_prepare(struct xe_vm *vm,
 
 		err = bind_op_prepare(vm, tile, pt_update_ops, op->map.vma,
 				      op->map.invalidate_on_bind);
-		pt_update_ops->wait_vm_kernel = true;
+		vops->flags |= XE_VMA_OPS_FLAG_WAIT_VM_KERNEL;
 		break;
 	case DRM_GPUVA_OP_REMAP:
 	{
@@ -2408,12 +2401,12 @@ static int op_prepare(struct xe_vm *vm,
 		if (!err && op->remap.prev && !op->remap.skip_prev) {
 			err = bind_op_prepare(vm, tile, pt_update_ops,
 					      op->remap.prev, false);
-			pt_update_ops->wait_vm_bookkeep = true;
+			vops->flags |= XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
 		}
 		if (!err && op->remap.next && !op->remap.skip_next) {
 			err = bind_op_prepare(vm, tile, pt_update_ops,
 					      op->remap.next, false);
-			pt_update_ops->wait_vm_bookkeep = true;
+			vops->flags |= XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
 		}
 		break;
 	}
@@ -2449,7 +2442,7 @@ static int op_prepare(struct xe_vm *vm,
 			}
 		} else {
 			err = bind_op_prepare(vm, tile, pt_update_ops, vma, false);
-			pt_update_ops->wait_vm_kernel = true;
+			vops->flags |= XE_VMA_OPS_FLAG_WAIT_VM_KERNEL;
 		}
 		break;
 	}
@@ -2483,18 +2476,8 @@ xe_pt_update_ops_init(struct xe_vm_pgtable_update_ops *pt_update_ops)
 	xe_page_reclaim_list_init(&pt_update_ops->prl);
 }
 
-/**
- * xe_pt_update_ops_prepare() - Prepare PT update operations
- * @tile: Tile of PT update operations
- * @vops: VMA operationa
- *
- * Prepare PT update operations which includes updating internal PT state,
- * allocate memory for page tables, populate page table being pruned in, and
- * create PT update operations for leaf insertion / removal.
- *
- * Return: 0 on success, negative error code on error.
- */
-int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops)
+static int __xe_pt_update_ops_prepare(struct xe_tile *tile,
+				      struct xe_vma_ops *vops)
 {
 	struct xe_vm_pgtable_update_ops *pt_update_ops =
 		&vops->pt_update_ops[tile->id];
@@ -2513,7 +2496,7 @@ int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops)
 		return err;
 
 	list_for_each_entry(op, &vops->list, link) {
-		err = op_prepare(vops->vm, tile, pt_update_ops, op);
+		err = op_prepare(vops->vm, tile, vops, pt_update_ops, op);
 
 		if (err)
 			return err;
@@ -2522,6 +2505,16 @@ int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops)
 	xe_tile_assert(tile, get_current_op(pt_update_ops) <=
 		       pt_update_ops->num_ops);
 
+	/* Propagate individual tile state up to VMA operation */
+	if (pt_update_ops->start < vops->start)
+		vops->start = pt_update_ops->start;
+	if (pt_update_ops->last > vops->last)
+		vops->last = pt_update_ops->last;
+	if (pt_update_ops->needs_invalidation)
+		vops->flags |= XE_VMA_OPS_FLAG_NEEDS_INVALIDATION;
+	if (pt_update_ops->needs_svm_lock)
+		vops->flags |= XE_VMA_OPS_FLAG_NEEDS_SVM_LOCK;
+
 #ifdef TEST_VM_OPS_ERROR
 	if (vops->inject_error &&
 	    vops->vm->xe->vm_inject_error_position == FORCE_OP_ERROR_PREPARE)
@@ -2530,35 +2523,68 @@ int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops)
 
 	return 0;
 }
-ALLOW_ERROR_INJECTION(xe_pt_update_ops_prepare, ERRNO);
 
-static void bind_op_commit(struct xe_vm *vm, struct xe_tile *tile,
-			   struct xe_vm_pgtable_update_ops *pt_update_ops,
-			   struct xe_vma *vma, struct dma_fence *fence,
-			   struct dma_fence *fence2, bool invalidate_on_bind)
+/**
+ * xe_pt_update_ops_prepare() - Prepare PT update operations
+ * @xe: xe device.
+ * @vops: VMA operationa
+ *
+ * Prepare PT update operations which includes updating internal PT state,
+ * allocate memory for page tables, populate page table being pruned in, and
+ * create PT update operations for leaf insertion / removal.
+ *
+ * Return: 0 on success, negative error code on error.
+ */
+int xe_pt_update_ops_prepare(struct xe_device *xe, struct xe_vma_ops *vops)
 {
-	xe_tile_assert(tile, !xe_vma_is_cpu_addr_mirror(vma));
+	struct xe_tile *tile;
+	int id, err;
+
+	for_each_tile(tile, xe, id) {
+		if (!vops->pt_update_ops[id].num_ops)
+			continue;
 
-	if (!xe_vma_has_no_bo(vma) && !xe_vma_bo(vma)->vm) {
-		dma_resv_add_fence(xe_vma_bo(vma)->ttm.base.resv, fence,
-				   pt_update_ops->wait_vm_bookkeep ?
-				   DMA_RESV_USAGE_KERNEL :
-				   DMA_RESV_USAGE_BOOKKEEP);
-		if (fence2)
-			dma_resv_add_fence(xe_vma_bo(vma)->ttm.base.resv, fence2,
-					   pt_update_ops->wait_vm_bookkeep ?
-					   DMA_RESV_USAGE_KERNEL :
-					   DMA_RESV_USAGE_BOOKKEEP);
+		err = __xe_pt_update_ops_prepare(tile, vops);
+		if (err)
+			return err;
 	}
+
+	return 0;
+}
+ALLOW_ERROR_INJECTION(xe_pt_update_ops_prepare, ERRNO);
+
+static void vma_add_fences(struct xe_vma *vma, struct dma_fence **fences,
+			   int fence_count, enum dma_resv_usage usage)
+{
+	int i;
+
+	if (xe_vma_has_no_bo(vma) || xe_vma_bo(vma)->vm)
+		return;
+
+	for (i = 0; i < fence_count; ++i)
+		if (fences[i])
+			dma_resv_add_fence(xe_vma_bo(vma)->ttm.base.resv,
+					   fences[i], usage);
+}
+
+static void bind_op_commit(struct xe_vm *vm, struct xe_vma *vma,
+			   struct dma_fence **fences, int fence_count,
+			   enum dma_resv_usage usage, u8 tile_mask,
+			   bool invalidate_on_bind)
+{
+	xe_assert(vm->xe, !xe_vma_is_cpu_addr_mirror(vma));
+
+	vma_add_fences(vma, fences, fence_count, usage);
+
 	/* All WRITE_ONCE pair with READ_ONCE in xe_vm_has_valid_gpu_mapping() */
-	WRITE_ONCE(vma->tile_present, vma->tile_present | BIT(tile->id));
+	WRITE_ONCE(vma->tile_present, vma->tile_present | tile_mask);
 	if (invalidate_on_bind)
 		WRITE_ONCE(vma->tile_invalidated,
-			   vma->tile_invalidated | BIT(tile->id));
+			   vma->tile_invalidated | tile_mask);
 	else
 		WRITE_ONCE(vma->tile_invalidated,
-			   vma->tile_invalidated & ~BIT(tile->id));
-	vma->tile_staged &= ~BIT(tile->id);
+			   vma->tile_invalidated & ~tile_mask);
+	vma->tile_staged &= ~tile_mask;
 	if (xe_vma_is_userptr(vma)) {
 		xe_svm_assert_held_read_or_inject_write(vm);
 		to_userptr_vma(vma)->userptr.initial_bind = true;
@@ -2568,31 +2594,21 @@ static void bind_op_commit(struct xe_vm *vm, struct xe_tile *tile,
 	 * Kick rebind worker if this bind triggers preempt fences and not in
 	 * the rebind worker
 	 */
-	if (pt_update_ops->wait_vm_bookkeep &&
+	if (usage == DMA_RESV_USAGE_KERNEL &&
 	    xe_vm_in_preempt_fence_mode(vm) &&
 	    !current->mm)
 		xe_vm_queue_rebind_worker(vm);
 }
 
-static void unbind_op_commit(struct xe_vm *vm, struct xe_tile *tile,
-			     struct xe_vm_pgtable_update_ops *pt_update_ops,
-			     struct xe_vma *vma, struct dma_fence *fence,
-			     struct dma_fence *fence2)
+static void unbind_op_commit(struct xe_vm *vm, struct xe_vma *vma,
+			     struct dma_fence **fences, int fence_count,
+			     enum dma_resv_usage usage, u8 tile_mask)
 {
-	xe_tile_assert(tile, !xe_vma_is_cpu_addr_mirror(vma));
+	xe_assert(vm->xe, !xe_vma_is_cpu_addr_mirror(vma));
 
-	if (!xe_vma_has_no_bo(vma) && !xe_vma_bo(vma)->vm) {
-		dma_resv_add_fence(xe_vma_bo(vma)->ttm.base.resv, fence,
-				   pt_update_ops->wait_vm_bookkeep ?
-				   DMA_RESV_USAGE_KERNEL :
-				   DMA_RESV_USAGE_BOOKKEEP);
-		if (fence2)
-			dma_resv_add_fence(xe_vma_bo(vma)->ttm.base.resv, fence2,
-					   pt_update_ops->wait_vm_bookkeep ?
-					   DMA_RESV_USAGE_KERNEL :
-					   DMA_RESV_USAGE_BOOKKEEP);
-	}
-	vma->tile_present &= ~BIT(tile->id);
+	vma_add_fences(vma, fences, fence_count, usage);
+
+	vma->tile_present &= ~tile_mask;
 	if (!vma->tile_present) {
 		list_del_init(&vma->combined_links.rebind);
 		if (xe_vma_is_userptr(vma)) {
@@ -2607,21 +2623,19 @@ static void unbind_op_commit(struct xe_vm *vm, struct xe_tile *tile,
 
 static void range_present_and_invalidated_tile(struct xe_vm *vm,
 					       struct xe_svm_range *range,
-					       u8 tile_id)
+					       u8 tile_mask)
 {
 	/* All WRITE_ONCE pair with READ_ONCE in xe_vm_has_valid_gpu_mapping() */
 
 	lockdep_assert_held(&vm->svm.gpusvm.notifier_lock);
 
-	WRITE_ONCE(range->tile_present, range->tile_present | BIT(tile_id));
-	WRITE_ONCE(range->tile_invalidated, range->tile_invalidated & ~BIT(tile_id));
+	WRITE_ONCE(range->tile_present, range->tile_present | tile_mask);
+	WRITE_ONCE(range->tile_invalidated, range->tile_invalidated & ~tile_mask);
 }
 
-static void op_commit(struct xe_vm *vm,
-		      struct xe_tile *tile,
-		      struct xe_vm_pgtable_update_ops *pt_update_ops,
-		      struct xe_vma_op *op, struct dma_fence *fence,
-		      struct dma_fence *fence2)
+static void op_commit(struct xe_vm *vm, struct xe_vma_op *op,
+		      struct dma_fence **fences, int fence_count,
+		      enum dma_resv_usage usage, u8 tile_mask)
 {
 	xe_vm_assert_held(vm);
 
@@ -2631,8 +2645,8 @@ static void op_commit(struct xe_vm *vm,
 		    (op->map.vma_flags & XE_VMA_SYSTEM_ALLOCATOR))
 			break;
 
-		bind_op_commit(vm, tile, pt_update_ops, op->map.vma, fence,
-			       fence2, op->map.invalidate_on_bind);
+		bind_op_commit(vm, op->map.vma, fences, fence_count, usage,
+			       tile_mask, op->map.invalidate_on_bind);
 		break;
 	case DRM_GPUVA_OP_REMAP:
 	{
@@ -2641,14 +2655,15 @@ static void op_commit(struct xe_vm *vm,
 		if (xe_vma_is_cpu_addr_mirror(old))
 			break;
 
-		unbind_op_commit(vm, tile, pt_update_ops, old, fence, fence2);
+		unbind_op_commit(vm, old, fences, fence_count, usage,
+				 tile_mask);
 
 		if (op->remap.prev && !op->remap.skip_prev)
-			bind_op_commit(vm, tile, pt_update_ops, op->remap.prev,
-				       fence, fence2, false);
+			bind_op_commit(vm, op->remap.prev, fences, fence_count,
+				       usage, tile_mask, false);
 		if (op->remap.next && !op->remap.skip_next)
-			bind_op_commit(vm, tile, pt_update_ops, op->remap.next,
-				       fence, fence2, false);
+			bind_op_commit(vm, op->remap.next, fences, fence_count,
+				       usage, tile_mask, false);
 		break;
 	}
 	case DRM_GPUVA_OP_UNMAP:
@@ -2656,8 +2671,8 @@ static void op_commit(struct xe_vm *vm,
 		struct xe_vma *vma = gpuva_to_vma(op->base.unmap.va);
 
 		if (!xe_vma_is_cpu_addr_mirror(vma))
-			unbind_op_commit(vm, tile, pt_update_ops, vma, fence,
-					 fence2);
+			unbind_op_commit(vm, vma, fences, fence_count,
+					 usage, tile_mask);
 		break;
 	}
 	case DRM_GPUVA_OP_PREFETCH:
@@ -2669,10 +2684,11 @@ static void op_commit(struct xe_vm *vm,
 			unsigned long i;
 
 			xa_for_each(&op->prefetch_range.range, i, range)
-				range_present_and_invalidated_tile(vm, range, tile->id);
+				range_present_and_invalidated_tile(vm, range,
+								   tile_mask);
 		} else {
-			bind_op_commit(vm, tile, pt_update_ops, vma, fence,
-				       fence2, false);
+			bind_op_commit(vm, vma, fences, fence_count, usage,
+				       tile_mask, false);
 		}
 		break;
 	}
@@ -2680,11 +2696,12 @@ static void op_commit(struct xe_vm *vm,
 	{
 		/* WRITE_ONCE pairs with READ_ONCE in xe_vm_has_valid_gpu_mapping() */
 		if (op->subop == XE_VMA_SUBOP_MAP_RANGE)
-			range_present_and_invalidated_tile(vm, op->map_range.range, tile->id);
+			range_present_and_invalidated_tile(vm, op->map_range.range,
+							   tile_mask);
 		else if (op->subop == XE_VMA_SUBOP_UNMAP_RANGE)
 			WRITE_ONCE(op->unmap_range.range->tile_present,
 				   op->unmap_range.range->tile_present &
-				   ~BIT(tile->id));
+				   ~tile_mask);
 
 		break;
 	}
@@ -2693,40 +2710,25 @@ static void op_commit(struct xe_vm *vm,
 	}
 }
 
-static const struct xe_migrate_pt_update_ops migrate_ops = {
+static const struct xe_cpu_bind_pt_update_ops cpu_bind_ops = {
 	.populate = xe_vm_populate_pgtable,
-	.clear = xe_migrate_clear_pgtable_callback,
+	.clear = xe_pt_clear_pgtable_callback,
 	.pre_commit = xe_pt_pre_commit,
 };
 
 #if IS_ENABLED(CONFIG_DRM_GPUSVM)
-static const struct xe_migrate_pt_update_ops svm_userptr_migrate_ops = {
+static const struct xe_cpu_bind_pt_update_ops svm_userptr_cpu_bind_ops = {
 	.populate = xe_vm_populate_pgtable,
-	.clear = xe_migrate_clear_pgtable_callback,
+	.clear = xe_pt_clear_pgtable_callback,
 	.pre_commit = xe_pt_svm_userptr_pre_commit,
 };
 #else
-static const struct xe_migrate_pt_update_ops svm_userptr_migrate_ops;
+static const struct xe_cpu_bind_pt_update_ops svm_userptr_cpu_bind_ops;
 #endif
 
-static struct xe_dep_scheduler *to_dep_scheduler(struct xe_exec_queue *q,
-						 struct xe_tile *tile,
-						 struct xe_gt *gt,
-						 unsigned int *type)
-{
-	int tile_ofs = tile->id * (XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT + 1);
-
-	if (xe_gt_is_media_type(gt))
-		*type = tile_ofs + XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT;
-	else
-		*type = tile_ofs + XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT;
-
-	return q->tlb_inval[*type].dep_scheduler;
-}
-
 /**
  * xe_pt_update_ops_run() - Run PT update operations
- * @tile: Tile of PT update operations
+ * @xe: xe device.
  * @vops: VMA operationa
  *
  * Run PT update operations which includes committing internal PT state changes,
@@ -2736,82 +2738,83 @@ static struct xe_dep_scheduler *to_dep_scheduler(struct xe_exec_queue *q,
  * Return: fence on success, negative ERR_PTR on error.
  */
 struct dma_fence *
-xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
+xe_pt_update_ops_run(struct xe_device *xe, struct xe_vma_ops *vops)
 {
 	struct xe_vm *vm = vops->vm;
-	struct xe_vm_pgtable_update_ops *pt_update_ops =
-		&vops->pt_update_ops[tile->id];
-	struct xe_exec_queue *q = pt_update_ops->q;
-	struct dma_fence *fence, *ifence = NULL, *mfence = NULL;
-	struct xe_tlb_inval_job *ijob = NULL, *mjob = NULL;
+	struct xe_exec_queue *q = vops->q;
+	struct dma_fence *fence;
+	struct dma_fence *ifences[XE_CPU_BIND_INVAL_JOB_COUNT] = {};
 	struct xe_range_fence *rfence;
+	enum dma_resv_usage usage = DMA_RESV_USAGE_BOOKKEEP;
 	struct xe_vma_op *op;
-	unsigned int type;
-	int err = 0, i;
-	struct xe_migrate_pt_update update = {
-		.ops = pt_update_ops->needs_svm_lock ?
-			&svm_userptr_migrate_ops :
-			&migrate_ops,
+	struct xe_tile *tile;
+	int err = 0, total_ops = 0, i, j;
+	u8 tile_mask = 0;
+	bool needs_invalidation = vops->flags &
+		XE_VMA_OPS_FLAG_NEEDS_INVALIDATION;
+	bool needs_svm_lock = vops->flags &
+		XE_VMA_OPS_FLAG_NEEDS_SVM_LOCK;
+	struct xe_cpu_bind_pt_update update = {
+		.ops = needs_svm_lock ? &svm_userptr_cpu_bind_ops :
+			&cpu_bind_ops,
 		.vops = vops,
-		.tile_id = tile->id,
 	};
 
 	lockdep_assert_held(&vm->lock);
 	xe_vm_assert_held(vm);
 
-	if (!get_current_op(pt_update_ops)) {
-		xe_tile_assert(tile, xe_vm_in_fault_mode(vm));
+	for_each_tile(tile, xe, j) {
+		struct xe_vm_pgtable_update_ops *pt_update_ops =
+			&vops->pt_update_ops[j];
 
+		total_ops += get_current_op(pt_update_ops);
+	}
+	if (!total_ops) {
+		xe_assert(xe, xe_vm_in_fault_mode(vm));
 		return dma_fence_get_stub();
 	}
 
 #ifdef TEST_VM_OPS_ERROR
 	if (vops->inject_error &&
-	    vm->xe->vm_inject_error_position == FORCE_OP_ERROR_RUN)
+	    xe->vm_inject_error_position == FORCE_OP_ERROR_RUN)
 		return ERR_PTR(-ENOSPC);
 #endif
 
-	if (pt_update_ops->needs_invalidation) {
-		struct xe_dep_scheduler *dep_scheduler =
-			to_dep_scheduler(q, tile, tile->primary_gt, &type);
-
-		ijob = xe_tlb_inval_job_create(q, &tile->primary_gt->tlb_inval,
-					       dep_scheduler, vm,
-					       pt_update_ops->start,
-					       pt_update_ops->last,
-					       type);
-		if (IS_ERR(ijob)) {
-			err = PTR_ERR(ijob);
-			goto kill_vm_tile1;
-		}
-		update.ijob = ijob;
-		/*
-		 * Only add page reclaim for the primary GT. Media GT does not have
-		 * any PPC to flush, so enabling the PPC flush bit for media is
-		 * effectively a NOP and provides no performance benefit nor
-		 * interfere with primary GT.
-		 */
-		if (xe_page_reclaim_list_valid(&pt_update_ops->prl)) {
-			xe_tlb_inval_job_add_page_reclaim(ijob, &pt_update_ops->prl);
-			/* Release ref from alloc, job will now handle it */
-			xe_page_reclaim_list_invalidate(&pt_update_ops->prl);
-		}
-
-		if (tile->media_gt) {
-			dep_scheduler = to_dep_scheduler(q, tile,
-							 tile->media_gt, &type);
-
-			mjob = xe_tlb_inval_job_create(q,
-						       &tile->media_gt->tlb_inval,
-						       dep_scheduler, vm,
-						       pt_update_ops->start,
-						       pt_update_ops->last,
-						       type);
-			if (IS_ERR(mjob)) {
-				err = PTR_ERR(mjob);
+	if (needs_invalidation) {
+		for_each_tlb_inval(q, i) {
+			struct xe_dep_scheduler *dep_scheduler =
+				q->tlb_inval[i].dep_scheduler;
+			struct xe_tile *tile =
+				&xe->tiles[i / XE_MAX_GT_PER_TILE];
+			struct xe_vm_pgtable_update_ops *pt_update_ops =
+				&vops->pt_update_ops[tile->id];
+			struct xe_page_reclaim_list *prl = &pt_update_ops->prl;
+			struct xe_tlb_inval_job *ijob;
+			struct xe_gt *gt = i % XE_MAX_GT_PER_TILE ?
+				tile->media_gt : tile->primary_gt;
+
+			ijob = xe_tlb_inval_job_create(q, &gt->tlb_inval,
+						       dep_scheduler,
+						       vm, vops->start,
+						       vops->last, i);
+			if (IS_ERR(ijob)) {
+				err = PTR_ERR(ijob);
 				goto free_ijob;
 			}
-			update.mjob = mjob;
+
+			update.ijobs[i] = ijob;
+
+			/*
+			 * Only add page reclaim for the primary GT. Media GT
+			 * does not have any PPC to flush, so enabling the PPC
+			 * flush bit for media is effectively a NOP and provides
+			 * no performance benefit nor interfere with primary GT.
+			 */
+			if (xe_page_reclaim_list_valid(prl)) {
+				xe_tlb_inval_job_add_page_reclaim(ijob, prl);
+				/* Release ref from alloc, job will now handle it */
+				xe_page_reclaim_list_invalidate(prl);
+			}
 		}
 	}
 
@@ -2821,67 +2824,61 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
 		goto free_ijob;
 	}
 
-	fence = xe_migrate_update_pgtables(tile->migrate, &update);
+	fence = xe_cpu_bind_update_pgtables(xe->cpu_bind, &update);
 	if (IS_ERR(fence)) {
 		err = PTR_ERR(fence);
 		goto free_rfence;
 	}
 
 	/* Point of no return - VM killed if failure after this */
-	for (i = 0; i < get_current_op(pt_update_ops); ++i) {
-		struct xe_vm_pgtable_update_op *pt_op =
-			to_pt_op(pt_update_ops, i);
-
-		xe_pt_commit(pt_op->vma, pt_op->entries,
-			     pt_op->num_entries,
-			     &pt_update_ops->pt_job_ops->deferred);
-		pt_op->vma = NULL;	/* skip in xe_pt_update_ops_abort */
+	for_each_tile(tile, xe, j) {
+		struct xe_vm_pgtable_update_ops *pt_update_ops =
+			&vops->pt_update_ops[j];
+
+		for (i = 0; i < get_current_op(pt_update_ops); ++i) {
+			struct xe_vm_pgtable_update_op *pt_op =
+				to_pt_op(pt_update_ops, i);
+
+			xe_pt_commit(pt_op->vma, pt_op->entries,
+				     pt_op->num_entries,
+				     &pt_update_ops->pt_job_ops->deferred);
+			pt_op->vma = NULL;	/* skip in xe_pt_update_ops_abort */
+			tile_mask |= BIT(tile->id);
+		}
 	}
 
-	if (xe_range_fence_insert(&vm->rftree[tile->id], rfence,
+	if (xe_range_fence_insert(&vm->rftree, rfence,
 				  &xe_range_fence_kfree_ops,
-				  pt_update_ops->start,
-				  pt_update_ops->last, fence))
+				  vops->start, vops->last, fence))
 		dma_fence_wait(fence, false);
 
-	if (ijob)
-		ifence = xe_tlb_inval_job_push(ijob, tile->migrate, fence);
-	if (mjob)
-		mfence = xe_tlb_inval_job_push(mjob, tile->migrate, fence);
+	if (vops->flags & XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP)
+		usage = DMA_RESV_USAGE_KERNEL;
 
-	if (!mjob && !ijob) {
-		dma_resv_add_fence(xe_vm_resv(vm), fence,
-				   pt_update_ops->wait_vm_bookkeep ?
-				   DMA_RESV_USAGE_KERNEL :
-				   DMA_RESV_USAGE_BOOKKEEP);
-
-		list_for_each_entry(op, &vops->list, link)
-			op_commit(vops->vm, tile, pt_update_ops, op, fence, NULL);
-	} else if (ijob && !mjob) {
-		dma_resv_add_fence(xe_vm_resv(vm), ifence,
-				   pt_update_ops->wait_vm_bookkeep ?
-				   DMA_RESV_USAGE_KERNEL :
-				   DMA_RESV_USAGE_BOOKKEEP);
+	if (!needs_invalidation) {
+		dma_resv_add_fence(xe_vm_resv(vm), fence, usage);
 
 		list_for_each_entry(op, &vops->list, link)
-			op_commit(vops->vm, tile, pt_update_ops, op, ifence, NULL);
+			op_commit(vops->vm, op, &fence, 1, usage, tile_mask);
 	} else {
-		dma_resv_add_fence(xe_vm_resv(vm), ifence,
-				   pt_update_ops->wait_vm_bookkeep ?
-				   DMA_RESV_USAGE_KERNEL :
-				   DMA_RESV_USAGE_BOOKKEEP);
+		for (i = 0; i < XE_CPU_BIND_INVAL_JOB_COUNT; ++i) {
+			if (!update.ijobs[i])
+				continue;
+
+			ifences[i] = xe_tlb_inval_job_push(update.ijobs[i],
+							   fence);
+			xe_assert(xe, !IS_ERR_OR_NULL(ifences[i]));
 
-		dma_resv_add_fence(xe_vm_resv(vm), mfence,
-				   pt_update_ops->wait_vm_bookkeep ?
-				   DMA_RESV_USAGE_KERNEL :
-				   DMA_RESV_USAGE_BOOKKEEP);
+			dma_resv_add_fence(xe_vm_resv(vm), ifences[i], usage);
+		}
 
 		list_for_each_entry(op, &vops->list, link)
-			op_commit(vops->vm, tile, pt_update_ops, op, ifence,
-				  mfence);
+			op_commit(vops->vm, op, ifences,
+				  XE_CPU_BIND_INVAL_JOB_COUNT, usage,
+				  tile_mask);
 	}
 
-	if (pt_update_ops->needs_svm_lock)
+	if (needs_svm_lock)
 		xe_pt_svm_userptr_notifier_unlock(vm);
 
 	/*
@@ -2891,21 +2888,18 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
 	if (!(q->flags & EXEC_QUEUE_FLAG_MIGRATE))
 		xe_exec_queue_last_fence_set(q, vm, fence);
 
-	xe_tlb_inval_job_put(mjob);
-	xe_tlb_inval_job_put(ijob);
-	dma_fence_put(ifence);
-	dma_fence_put(mfence);
+	for (i = 0; i < XE_CPU_BIND_INVAL_JOB_COUNT; ++i) {
+		xe_tlb_inval_job_put(update.ijobs[i]);
+		dma_fence_put(ifences[i]);
+	}
 
 	return fence;
 
 free_rfence:
 	kfree(rfence);
 free_ijob:
-	xe_tlb_inval_job_put(mjob);
-	xe_tlb_inval_job_put(ijob);
-kill_vm_tile1:
-	if (err != -EAGAIN && err != -ENODATA && tile->id)
-		xe_vm_kill(vops->vm, false);
+	for (i = 0; i < XE_CPU_BIND_INVAL_JOB_COUNT; ++i)
+		xe_tlb_inval_job_put(update.ijobs[i]);
 
 	return ERR_PTR(err);
 }
@@ -2913,52 +2907,65 @@ ALLOW_ERROR_INJECTION(xe_pt_update_ops_run, ERRNO);
 
 /**
  * xe_pt_update_ops_fini() - Finish PT update operations
- * @tile: Tile of PT update operations
+ * @xe: xe device.
  * @vops: VMA operations
  *
  * Finish PT update operations by committing to destroy page table memory
  */
-void xe_pt_update_ops_fini(struct xe_tile *tile, struct xe_vma_ops *vops)
+void xe_pt_update_ops_fini(struct xe_device *xe, struct xe_vma_ops *vops)
 {
-	struct xe_vm_pgtable_update_ops *pt_update_ops =
-		&vops->pt_update_ops[tile->id];
+	struct xe_tile *tile;
+	int id;
+
+	for_each_tile(tile, xe, id) {
+		struct xe_vm_pgtable_update_ops *pt_update_ops =
+			&vops->pt_update_ops[id];
 
-	xe_page_reclaim_entries_put(pt_update_ops->prl.entries);
+		if (!pt_update_ops->num_ops)
+			continue;
+
+		xe_page_reclaim_entries_put(pt_update_ops->prl.entries);
+	}
 }
 
 /**
  * xe_pt_update_ops_abort() - Abort PT update operations
- * @tile: Tile of PT update operations
+ * @xe: xe device.
  * @vops: VMA operationa
  *
  *  Abort PT update operations by unwinding internal PT state
  */
-void xe_pt_update_ops_abort(struct xe_tile *tile, struct xe_vma_ops *vops)
+void xe_pt_update_ops_abort(struct xe_device *xe, struct xe_vma_ops *vops)
 {
-	struct xe_vm_pgtable_update_ops *pt_update_ops =
-		&vops->pt_update_ops[tile->id];
-	int i;
+	struct xe_tile *tile;
+	int id;
 
 	lockdep_assert_held(&vops->vm->lock);
 	xe_vm_assert_held(vops->vm);
 
-	for (i = pt_update_ops->num_ops - 1; i >= 0; --i) {
-		struct xe_vm_pgtable_update_op *pt_op =
-			to_pt_op(pt_update_ops, i);
+	for_each_tile(tile, xe, id) {
+		struct xe_vm_pgtable_update_ops *pt_update_ops =
+			&vops->pt_update_ops[id];
+		int i;
 
-		if (!pt_op->vma || i >= get_current_op(pt_update_ops))
-			continue;
+		for (i = pt_update_ops->num_ops - 1; i >= 0; --i) {
+			struct xe_vm_pgtable_update_op *pt_op =
+				to_pt_op(pt_update_ops, i);
 
-		if (pt_op->bind)
-			xe_pt_abort_bind(pt_op->vma, pt_op->entries,
-					 pt_op->num_entries,
-					 pt_op->rebind);
-		else
-			xe_pt_abort_unbind(pt_op->vma, pt_op->entries,
-					   pt_op->num_entries);
+			if (!pt_op->vma || i >= get_current_op(pt_update_ops))
+				continue;
+
+			if (pt_op->bind)
+				xe_pt_abort_bind(pt_op->vma, pt_op->entries,
+						 pt_op->num_entries,
+						 pt_op->rebind);
+			else
+				xe_pt_abort_unbind(pt_op->vma, pt_op->entries,
+						   pt_op->num_entries);
+		}
 	}
 
-	xe_pt_update_ops_fini(tile, vops);
+	xe_pt_update_ops_fini(xe, vops);
 }
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_pt.h b/drivers/gpu/drm/xe/xe_pt.h
index 5faddb8e700c..cd78141fb81c 100644
--- a/drivers/gpu/drm/xe/xe_pt.h
+++ b/drivers/gpu/drm/xe/xe_pt.h
@@ -39,11 +39,11 @@ void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred);
 
 void xe_pt_clear(struct xe_device *xe, struct xe_pt *pt);
 
-int xe_pt_update_ops_prepare(struct xe_tile *tile, struct xe_vma_ops *vops);
-struct dma_fence *xe_pt_update_ops_run(struct xe_tile *tile,
+int xe_pt_update_ops_prepare(struct xe_device *xe, struct xe_vma_ops *vops);
+struct dma_fence *xe_pt_update_ops_run(struct xe_device *xe,
 				       struct xe_vma_ops *vops);
-void xe_pt_update_ops_fini(struct xe_tile *tile, struct xe_vma_ops *vops);
-void xe_pt_update_ops_abort(struct xe_tile *tile, struct xe_vma_ops *vops);
+void xe_pt_update_ops_fini(struct xe_device *xe, struct xe_vma_ops *vops);
+void xe_pt_update_ops_abort(struct xe_device *xe, struct xe_vma_ops *vops);
 
 bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma);
 bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,
diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h
index ccab6613385f..0d4bac22ee6c 100644
--- a/drivers/gpu/drm/xe/xe_pt_types.h
+++ b/drivers/gpu/drm/xe/xe_pt_types.h
@@ -120,8 +120,6 @@ struct xe_pt_job_ops {
 struct xe_vm_pgtable_update_ops {
 	/** @pt_job_ops: PT update operations dynamic allocation*/
 	struct xe_pt_job_ops *pt_job_ops;
-	/** @q: exec queue for PT operations */
-	struct xe_exec_queue *q;
 	/** @prl: embedded page reclaim list */
 	struct xe_page_reclaim_list prl;
 	/** @start: start address of ops */
@@ -134,18 +132,6 @@ struct xe_vm_pgtable_update_ops {
 	bool needs_svm_lock;
 	/** @needs_invalidation: Needs invalidation */
 	bool needs_invalidation;
-	/**
-	 * @wait_vm_bookkeep: PT operations need to wait until VM is idle
-	 * (bookkeep dma-resv slots are idle) and stage all future VM activity
-	 * behind these operations (install PT operations into VM kernel
-	 * dma-resv slot).
-	 */
-	bool wait_vm_bookkeep;
-	/**
-	 * @wait_vm_kernel: PT operations need to wait until VM kernel dma-resv
-	 * slots are idle.
-	 */
-	bool wait_vm_kernel;
 };
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
index 841d67ebd5b0..ade0a54d5c3f 100644
--- a/drivers/gpu/drm/xe/xe_sched_job.c
+++ b/drivers/gpu/drm/xe/xe_sched_job.c
@@ -73,8 +73,9 @@ static void job_free(struct xe_sched_job *job)
 	struct xe_exec_queue *q = job->q;
 	bool is_migration = xe_sched_job_is_migration(q);
 
-	kmem_cache_free(xe_exec_queue_is_parallel(job->q) || is_migration ?
-			xe_sched_job_parallel_slab : xe_sched_job_slab, job);
+	kmem_cache_free(job->is_pt_job || xe_exec_queue_is_parallel(job->q) ||
+			is_migration ? xe_sched_job_parallel_slab :
+			xe_sched_job_slab, job);
 }
 
 static struct xe_device *job_to_xe(struct xe_sched_job *job)
@@ -127,10 +128,12 @@ struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
 	xe_assert(xe, batch_addr ||
 		  q->flags & (EXEC_QUEUE_FLAG_VM | EXEC_QUEUE_FLAG_MIGRATE));
 
-	job = job_alloc(xe_exec_queue_is_parallel(q) || is_migration);
+	job = job_alloc(!batch_addr || xe_exec_queue_is_parallel(q) ||
+			is_migration);
 	if (!job)
 		return ERR_PTR(-ENOMEM);
 
+	job->is_pt_job = !batch_addr;
 	job->q = q;
 	job->sample_timestamp = U64_MAX;
 	kref_init(&job->refcount);
@@ -143,7 +146,6 @@ struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
 
 	if (!batch_addr) {
 		job->fence = dma_fence_get_stub();
-		job->is_pt_job = true;
 	} else {
 		for (i = 0; i < q->width; ++i) {
 			struct dma_fence *fence = xe_lrc_alloc_seqno_fence();
diff --git a/drivers/gpu/drm/xe/xe_sched_job_types.h b/drivers/gpu/drm/xe/xe_sched_job_types.h
index 5e1824c36c74..9f527ac6df3e 100644
--- a/drivers/gpu/drm/xe/xe_sched_job_types.h
+++ b/drivers/gpu/drm/xe/xe_sched_job_types.h
@@ -14,7 +14,7 @@ struct dma_fence;
 struct dma_fence_chain;
 
 struct xe_exec_queue;
-struct xe_migrate_pt_update_ops;
+struct xe_cpu_bind_pt_update_ops;
 struct xe_pt_job_ops;
 struct xe_tile;
 struct xe_vm;
@@ -25,12 +25,11 @@ struct xe_vm;
 struct xe_pt_update_args {
 	/** @vm: VM which is being bound */
 	struct xe_vm *vm;
-	/** @tile: Tile which page tables belong to */
-	struct xe_tile *tile;
-	/** @ops: Migrate PT update ops */
-	const struct xe_migrate_pt_update_ops *ops;
+	/** @ops: CPU bind PT update ops */
+	const struct xe_cpu_bind_pt_update_ops *ops;
+#define XE_PT_UPDATE_JOB_OPS_COUNT	2
 	/** @pt_job_ops: PT job ops state */
-	struct xe_pt_job_ops *pt_job_ops;
+	struct xe_pt_job_ops *pt_job_ops[XE_PT_UPDATE_JOB_OPS_COUNT];
 };
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.c b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
index 81f560068d3c..7378cfe6e855 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_job.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.c
@@ -4,6 +4,7 @@
  */
 
 #include "xe_assert.h"
+#include "xe_cpu_bind.h"
 #include "xe_dep_job_types.h"
 #include "xe_dep_scheduler.h"
 #include "xe_exec_queue.h"
@@ -12,7 +13,6 @@
 #include "xe_page_reclaim.h"
 #include "xe_tlb_inval.h"
 #include "xe_tlb_inval_job.h"
-#include "xe_migrate.h"
 #include "xe_pm.h"
 #include "xe_vm.h"
 
@@ -218,7 +218,6 @@ int xe_tlb_inval_job_alloc_dep(struct xe_tlb_inval_job *job)
 /**
  * xe_tlb_inval_job_push() - TLB invalidation job push
  * @job: TLB invalidation job to push
- * @m: The migration object being used
  * @fence: Dependency for TLB invalidation job
  *
  * Pushes a TLB invalidation job for execution, using @fence as a dependency.
@@ -230,11 +229,11 @@ int xe_tlb_inval_job_alloc_dep(struct xe_tlb_inval_job *job)
  * Return: Job's finished fence on success, cannot fail
  */
 struct dma_fence *xe_tlb_inval_job_push(struct xe_tlb_inval_job *job,
-					struct xe_migrate *m,
 					struct dma_fence *fence)
 {
 	struct xe_tlb_inval_fence *ifence =
 		container_of(job->fence, typeof(*ifence), base);
+	struct xe_cpu_bind *cpu_bind = gt_to_xe(job->q->gt)->cpu_bind;
 
 	if (!dma_fence_is_signaled(fence)) {
 		void *ptr;
@@ -258,11 +257,11 @@ struct dma_fence *xe_tlb_inval_job_push(struct xe_tlb_inval_job *job,
 	job->fence_armed = true;
 
 	/*
-	 * We need the migration lock to protect the job's seqno and the spsc
-	 * queue, only taken on migration queue, user queues protected dma-resv
+	 * We need the cpu_bind lock to protect the job's seqno and the spsc
+	 * queue, only taken on cpu_bind queue, user queues protected dma-resv
 	 * VM lock.
 	 */
-	xe_migrate_job_lock(m, job->q);
+	xe_cpu_bind_job_lock(cpu_bind, job->q);
 
 	/* Creation ref pairs with put in xe_tlb_inval_job_destroy */
 	xe_tlb_inval_fence_init(job->tlb_inval, ifence, false);
@@ -281,7 +280,7 @@ struct dma_fence *xe_tlb_inval_job_push(struct xe_tlb_inval_job *job,
 					       &job->dep.drm.s_fence->finished,
 					       job->idx);
 
-	xe_migrate_job_unlock(m, job->q);
+	xe_cpu_bind_job_unlock(cpu_bind, job->q);
 
 	/*
 	 * Not using job->fence, as it has its own dma-fence context, which does
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval_job.h b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
index 2a4478f529e6..97e032ea21c3 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval_job.h
+++ b/drivers/gpu/drm/xe/xe_tlb_inval_job.h
@@ -11,7 +11,6 @@
 struct dma_fence;
 struct xe_dep_scheduler;
 struct xe_exec_queue;
-struct xe_migrate;
 struct xe_page_reclaim_list;
 struct xe_tlb_inval;
 struct xe_tlb_inval_job;
@@ -28,7 +27,6 @@ void xe_tlb_inval_job_add_page_reclaim(struct xe_tlb_inval_job *job,
 int xe_tlb_inval_job_alloc_dep(struct xe_tlb_inval_job *job);
 
 struct dma_fence *xe_tlb_inval_job_push(struct xe_tlb_inval_job *job,
-					struct xe_migrate *m,
 					struct dma_fence *fence);
 
 void xe_tlb_inval_job_get(struct xe_tlb_inval_job *job);
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 433a0a681556..fbfc42afef8b 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -24,6 +24,7 @@
 #include "regs/xe_gtt_defs.h"
 #include "xe_assert.h"
 #include "xe_bo.h"
+#include "xe_cpu_bind.h"
 #include "xe_device.h"
 #include "xe_drm_client.h"
 #include "xe_exec_queue.h"
@@ -795,8 +796,6 @@ int xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)
 	struct xe_vma *vma, *next;
 	struct xe_vma_ops vops;
 	struct xe_vma_op *op, *next_op;
-	struct xe_tile *tile;
-	u8 id;
 	int err;
 
 	lockdep_assert_held(&vm->lock);
@@ -804,12 +803,9 @@ int xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)
 	    list_empty(&vm->rebind_list))
 		return 0;
 
-	xe_vma_ops_init(&vops, vm, NULL, NULL, 0);
-	for_each_tile(tile, vm->xe, id) {
-		vops.pt_update_ops[id].wait_vm_bookkeep = true;
-		vops.pt_update_ops[id].q =
-			xe_migrate_bind_queue(tile->migrate);
-	}
+	xe_vma_ops_init(&vops, vm, xe_cpu_bind_queue(vm->xe->cpu_bind),
+			NULL, 0);
+	vops.flags |= XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
 
 	xe_vm_assert_held(vm);
 	list_for_each_entry(vma, &vm->rebind_list, combined_links.rebind) {
@@ -854,21 +850,16 @@ struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_ma
 	struct dma_fence *fence = NULL;
 	struct xe_vma_ops vops;
 	struct xe_vma_op *op, *next_op;
-	struct xe_tile *tile;
-	u8 id;
 	int err;
 
 	lockdep_assert_held(&vm->lock);
 	xe_vm_assert_held(vm);
 	xe_assert(vm->xe, xe_vm_in_fault_mode(vm));
 
-	xe_vma_ops_init(&vops, vm, NULL, NULL, 0);
-	vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT;
-	for_each_tile(tile, vm->xe, id) {
-		vops.pt_update_ops[id].wait_vm_bookkeep = true;
-		vops.pt_update_ops[tile->id].q =
-			xe_migrate_bind_queue(tile->migrate);
-	}
+	xe_vma_ops_init(&vops, vm, xe_cpu_bind_queue(vm->xe->cpu_bind),
+			NULL, 0);
+	vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT |
+		XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
 
 	err = xe_vm_ops_add_rebind(&vops, vma, tile_mask);
 	if (err)
@@ -944,8 +935,6 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm,
 	struct dma_fence *fence = NULL;
 	struct xe_vma_ops vops;
 	struct xe_vma_op *op, *next_op;
-	struct xe_tile *tile;
-	u8 id;
 	int err;
 
 	lockdep_assert_held(&range->lock);
@@ -954,13 +943,10 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm,
 	xe_assert(vm->xe, xe_vm_in_fault_mode(vm));
 	xe_assert(vm->xe, xe_vma_is_cpu_addr_mirror(vma));
 
-	xe_vma_ops_init(&vops, vm, NULL, NULL, 0);
-	vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT;
-	for_each_tile(tile, vm->xe, id) {
-		vops.pt_update_ops[id].wait_vm_bookkeep = true;
-		vops.pt_update_ops[tile->id].q =
-			xe_migrate_bind_queue(tile->migrate);
-	}
+	xe_vma_ops_init(&vops, vm, xe_cpu_bind_queue(vm->xe->cpu_bind),
+			NULL, 0);
+	vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT |
+		XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
 
 	err = xe_vm_ops_add_range_rebind(&vops, vma, range, tile_mask);
 	if (err)
@@ -1027,8 +1013,6 @@ struct dma_fence *xe_vm_range_unbind(struct xe_vm *vm,
 	struct dma_fence *fence = NULL;
 	struct xe_vma_ops vops;
 	struct xe_vma_op *op, *next_op;
-	struct xe_tile *tile;
-	u8 id;
 	int err;
 
 	lockdep_assert_held(&range->lock);
@@ -1039,12 +1023,9 @@ struct dma_fence *xe_vm_range_unbind(struct xe_vm *vm,
 	if (!range->tile_present)
 		return dma_fence_get_stub();
 
-	xe_vma_ops_init(&vops, vm, NULL, NULL, 0);
-	for_each_tile(tile, vm->xe, id) {
-		vops.pt_update_ops[id].wait_vm_bookkeep = true;
-		vops.pt_update_ops[tile->id].q =
-			xe_migrate_bind_queue(tile->migrate);
-	}
+	xe_vma_ops_init(&vops, vm, xe_cpu_bind_queue(vm->xe->cpu_bind),
+			NULL, 0);
+	vops.flags |= XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
 
 	err = xe_vm_ops_add_range_unbind(&vops, range);
 	if (err)
@@ -1715,9 +1696,7 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
 
 	init_rwsem(&vm->exec_queues.lock);
 	xe_vm_init_prove_locking(xe, vm);
-
-	for_each_tile(tile, xe, id)
-		xe_range_fence_tree_init(&vm->rftree[id]);
+	xe_range_fence_tree_init(&vm->rftree);
 
 	vm->pt_ops = &xelp_pt_ops;
 
@@ -1859,8 +1838,7 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
 	xe_svm_fini(vm);
 err_no_resv:
 	mutex_destroy(&vm->snap_mutex);
-	for_each_tile(tile, xe, id)
-		xe_range_fence_tree_fini(&vm->rftree[id]);
+	xe_range_fence_tree_fini(&vm->rftree);
 	ttm_lru_bulk_move_fini(&xe->ttm, &vm->lru_bulk_move);
 	if (vm->xef)
 		xe_file_put(vm->xef);
@@ -1916,10 +1894,8 @@ void xe_vm_close_and_put(struct xe_vm *vm)
 {
 	LIST_HEAD(contested);
 	struct xe_device *xe = vm->xe;
-	struct xe_tile *tile;
 	struct xe_vma *vma, *next_vma;
 	struct drm_gpuva *gpuva, *next;
-	u8 id;
 
 	xe_assert(xe, !vm->preempt.num_exec_queues);
 
@@ -2011,8 +1987,7 @@ void xe_vm_close_and_put(struct xe_vm *vm)
 
 	xe_vm_clear_fault_entries(vm);
 
-	for_each_tile(tile, xe, id)
-		xe_range_fence_tree_fini(&vm->rftree[id]);
+	xe_range_fence_tree_fini(&vm->rftree);
 
 	xe_vm_put(vm);
 }
@@ -3509,23 +3484,16 @@ static void trace_xe_vm_ops_execute(struct xe_vma_ops *vops)
 
 static int vm_ops_setup_tile_args(struct xe_vm *vm, struct xe_vma_ops *vops)
 {
-	struct xe_exec_queue *q = vops->q;
 	struct xe_tile *tile;
 	int number_tiles = 0;
 	u8 id;
 
-	for_each_tile(tile, vm->xe, id) {
+	for_each_tile(tile, vm->xe, id)
 		if (vops->pt_update_ops[id].num_ops)
 			++number_tiles;
 
-		if (vops->pt_update_ops[id].q)
-			continue;
-
-		if (q)
-			vops->pt_update_ops[id].q = q;
-		else
-			vops->pt_update_ops[id].q = vm->q;
-	}
+	if (!vops->q)
+		vops->q = vm->q;
 
 	return number_tiles;
 }
@@ -3533,22 +3501,17 @@ static int vm_ops_setup_tile_args(struct xe_vm *vm, struct xe_vma_ops *vops)
 static struct dma_fence *ops_execute(struct xe_vm *vm,
 				     struct xe_vma_ops *vops)
 {
-	struct xe_tile *tile;
+	struct xe_device *xe = vm->xe;
 	struct dma_fence *fence = NULL;
 	struct dma_fence **fences = NULL;
 	struct dma_fence_array *cf = NULL;
-	int number_tiles = 0, current_fence = 0, n_fence = 0, err, i;
-	u8 id;
+	int current_fence = 0, n_fence = 1, err, i;
 
-	number_tiles = vm_ops_setup_tile_args(vm, vops);
-	if (number_tiles == 0)
+	if (!vm_ops_setup_tile_args(vm, vops))
 		return ERR_PTR(-ENODATA);
 
-	for_each_tile(tile, vm->xe, id)
-		++n_fence;
-
 	if (!(vops->flags & XE_VMA_OPS_FLAG_SKIP_TLB_WAIT)) {
-		for_each_tlb_inval(vops->pt_update_ops[0].q, i)
+		for_each_tlb_inval(vops->q, i)
 			++n_fence;
 	}
 
@@ -3564,69 +3527,39 @@ static struct dma_fence *ops_execute(struct xe_vm *vm,
 		goto err_out;
 	}
 
-	for_each_tile(tile, vm->xe, id) {
-		if (!vops->pt_update_ops[id].num_ops)
-			continue;
-
-		err = xe_pt_update_ops_prepare(tile, vops);
-		if (err) {
-			fence = ERR_PTR(err);
-			goto err_out;
-		}
+	err = xe_pt_update_ops_prepare(xe, vops);
+	if (err) {
+		fence = ERR_PTR(err);
+		goto err_out;
 	}
 
 	trace_xe_vm_ops_execute(vops);
 
-	for_each_tile(tile, vm->xe, id) {
-		struct xe_exec_queue *q = vops->pt_update_ops[tile->id].q;
-
-		fence = NULL;
-		if (!vops->pt_update_ops[id].num_ops)
-			goto collect_fences;
-
-		fence = xe_pt_update_ops_run(tile, vops);
-		if (IS_ERR(fence))
-			goto err_out;
-
-collect_fences:
-		fences[current_fence++] = fence ?: dma_fence_get_stub();
-		if (vops->flags & XE_VMA_OPS_FLAG_SKIP_TLB_WAIT)
-			continue;
-
-		xe_migrate_job_lock(tile->migrate, q);
-		for_each_tlb_inval(q, i) {
-			if (i >= (tile->id + 1) * XE_MAX_GT_PER_TILE ||
-			    i < tile->id * XE_MAX_GT_PER_TILE)
-				continue;
+	fence = xe_pt_update_ops_run(xe, vops);
+	if (IS_ERR(fence))
+		goto err_out;
+	fences[current_fence++] = fence;
 
-			fences[current_fence++] = fence ?
-				xe_exec_queue_tlb_inval_last_fence_get(q, vm, i) :
-				dma_fence_get_stub();
-		}
-		xe_migrate_job_unlock(tile->migrate, q);
+	if (!(vops->flags & XE_VMA_OPS_FLAG_SKIP_TLB_WAIT)) {
+		xe_cpu_bind_job_lock(xe->cpu_bind, vops->q);
+		for_each_tlb_inval(vops->q, i)
+			fences[current_fence++] =
+				xe_exec_queue_tlb_inval_last_fence_get(vops->q,
+								       vm, i);
+		xe_cpu_bind_job_unlock(xe->cpu_bind, vops->q);
 	}
 
-	xe_assert(vm->xe, current_fence == n_fence);
+	xe_assert(xe, current_fence == n_fence);
 	dma_fence_array_init(cf, n_fence, fences, dma_fence_context_alloc(1),
 			     1);
 	fence = &cf->base;
 
-	for_each_tile(tile, vm->xe, id) {
-		if (!vops->pt_update_ops[id].num_ops)
-			continue;
-
-		xe_pt_update_ops_fini(tile, vops);
-	}
+	xe_pt_update_ops_fini(xe, vops);
 
 	return fence;
 
 err_out:
-	for_each_tile(tile, vm->xe, id) {
-		if (!vops->pt_update_ops[id].num_ops)
-			continue;
-
-		xe_pt_update_ops_abort(tile, vops);
-	}
+	xe_pt_update_ops_abort(xe, vops);
 	while (current_fence)
 		dma_fence_put(fences[--current_fence]);
 	kfree(fences);
@@ -3938,6 +3871,8 @@ static void xe_vma_ops_init(struct xe_vma_ops *vops, struct xe_vm *vm,
 	vops->syncs = syncs;
 	vops->num_syncs = num_syncs;
 	vops->flags = 0;
+	vops->start = ~0x0ull;
+	vops->last = 0x0ull;
 }
 
 static int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo *bo,
diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h
index c91cb13fc4f1..fb9305124679 100644
--- a/drivers/gpu/drm/xe/xe_vm_types.h
+++ b/drivers/gpu/drm/xe/xe_vm_types.h
@@ -317,7 +317,7 @@ struct xe_vm {
 	 * @rftree: range fence tree to track updates to page table structure.
 	 * Used to implement conflict tracking between independent bind engines.
 	 */
-	struct xe_range_fence_tree rftree[XE_MAX_TILES_PER_DEVICE];
+	struct xe_range_fence_tree rftree;
 
 	const struct xe_pt_ops *pt_ops;
 
@@ -557,6 +557,10 @@ struct xe_vma_ops {
 	u32 num_syncs;
 	/** @pt_update_ops: page table update operations */
 	struct xe_vm_pgtable_update_ops pt_update_ops[XE_MAX_TILES_PER_DEVICE];
+	/** @start: start address of ops */
+	u64 start;
+	/** @last: last address of ops */
+	u64 last;
 	/** @flag: signify the properties within xe_vma_ops*/
 #define XE_VMA_OPS_FLAG_HAS_SVM_PREFETCH	BIT(0)
 #define XE_VMA_OPS_FLAG_MADVISE			BIT(1)
@@ -566,6 +570,10 @@ struct xe_vma_ops {
 #define XE_VMA_OPS_FLAG_MODIFIES_GPUVA		BIT(5)
 #define XE_VMA_OPS_FLAG_DOWNGRADE_LOCK		BIT(6)
 #define XE_VMA_OPS_FLAG_HAS_SVM_VALID_RANGE	BIT(7)
+#define XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP	BIT(8)
+#define XE_VMA_OPS_FLAG_WAIT_VM_KERNEL		BIT(9)
+#define XE_VMA_OPS_FLAG_NEEDS_INVALIDATION	BIT(10)
+#define XE_VMA_OPS_FLAG_NEEDS_SVM_LOCK		BIT(11)
 	u32 flags;
 #ifdef TEST_VM_OPS_ERROR
 	/** @inject_error: inject error to test error handling */
-- 
2.34.1

[PATCH v6 17/24] drm/xe: Add device flag to enable PT mirroring across tiles

[Matthew Brost]

Some multi-tile devices may want to mirror page tables across tiles for
memory-bandwidth reasons, while others may not. Add a device flag that
allows enabling or disabling page-table mirroring across tiles.

Setting the flag to true (the existing behavior) on PVC, but both modes
have been tested and are working on PVC.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-18-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_device_types.h |  2 ++
 drivers/gpu/drm/xe/xe_migrate.c      |  5 ++--
 drivers/gpu/drm/xe/xe_pci.c          |  2 ++
 drivers/gpu/drm/xe/xe_pci_types.h    |  3 ++-
 drivers/gpu/drm/xe/xe_pt.c           | 36 +++++++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_vm.c           | 37 +++++++++++++++++++++++++---
 drivers/gpu/drm/xe/xe_vm.h           |  3 +++
 7 files changed, 79 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index bc60833c39a7..997ac82fd571 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -224,6 +224,8 @@ struct xe_device {
 		u8 has_usm:1;
 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
 		u8 has_64bit_timestamp:1;
+		/** @info.has_pt_mirror: Device has PT mirroring across tiles */
+		u8 has_pt_mirror:1;
 		/** @info.is_dgfx: is discrete device */
 		u8 is_dgfx:1;
 		/** @info.needs_scratch: needs scratch page for oob prefetch to work */
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index f7e1a81434b2..471ae5741836 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -246,7 +246,8 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 	struct xe_device *xe = tile_to_xe(tile);
 	u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
 	u8 id = tile->id;
-	u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
+	u32 num_entries = NUM_PT_SLOTS, num_level =
+		xe_vm_pt_root(vm, id)->level;
 #define VRAM_IDENTITY_MAP_PT_COUNT	4
 	u32 num_setup = num_level + VRAM_IDENTITY_MAP_PT_COUNT;
 #undef VRAM_IDENTITY_MAP_PT_COUNT
@@ -258,7 +259,7 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 	u64 l1_pt_ofs = xe_bo_size(bo) - 5 * XE_PAGE_SIZE;
 
 	entry = vm->pt_ops->pde_encode_bo(bo, l1_pt_ofs);
-	xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
+	xe_pt_write(xe, &xe_vm_pt_root(vm, id)->bo->vmap, 0, entry);
 
 	map_ofs = (num_entries - num_setup) * XE_PAGE_SIZE;
 
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index ab4da1d9a9f1..d9030cb4f1ad 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -371,6 +371,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
 	.has_display = false,
 	.has_drm_ras = true,
 	.has_gsc_nvm = 1,
+	.has_pt_mirror = 1,
 	.has_heci_gscfi = 1,
 	.max_gt_per_tile = 1,
 	.max_remote_tiles = 1,
@@ -808,6 +809,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_mert = desc->has_mert;
 	xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
 	xe->info.has_pre_prod_wa = desc->has_pre_prod_wa;
+	xe->info.has_pt_mirror = desc->has_pt_mirror;
 	xe->info.has_pxp = desc->has_pxp;
 	xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl;
 	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index fed509ff601e..71068cdb3558 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -52,8 +52,9 @@ struct xe_device_desc {
 	u8 has_mbx_power_limits:1;
 	u8 has_mbx_thermal_info:1;
 	u8 has_mert:1;
-	u8 has_pre_prod_wa:1;
 	u8 has_page_reclaim_hw_assist:1;
+	u8 has_pre_prod_wa:1;
+	u8 has_pt_mirror:1;
 	u8 has_pxp:1;
 	u8 has_soc_remapper_sysctrl:1;
 	u8 has_soc_remapper_telem:1;
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 05bbac6c2632..7e42067c79e4 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -812,7 +812,7 @@ xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
 		.wupd.entries = entries,
 		.clear_pt = clear_pt,
 	};
-	struct xe_pt *pt = vm->pt_root[tile->id];
+	struct xe_pt *pt = xe_vm_pt_root(vm, tile->id);
 	int ret;
 	bool is_purged = false;
 
@@ -1005,6 +1005,11 @@ static int xe_pt_zap_ptes_entry(struct xe_ptw *parent, pgoff_t offset,
 	return 0;
 }
 
+static bool pt_mirroring_disabled_for_tile(struct xe_vm *vm, u8 tile_id)
+{
+	return xe_vm_pt_root(vm, tile_id) != vm->pt_root[tile_id];
+}
+
 static const struct xe_pt_walk_ops xe_pt_zap_ptes_ops = {
 	.pt_entry = xe_pt_zap_ptes_entry,
 };
@@ -1046,6 +1051,9 @@ bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma)
 	if (!(pt_mask & BIT(tile->id)))
 		return false;
 
+	if (pt_mirroring_disabled_for_tile(xe_vma_vm(vma), tile->id))
+		return true;
+
 	(void)xe_pt_walk_shared(&pt->base, pt->level, xe_vma_start(vma),
 				xe_vma_end(vma), &xe_walk.base);
 
@@ -1098,6 +1106,9 @@ bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,
 	if (!(pt_mask & BIT(tile->id)))
 		return false;
 
+	if (pt_mirroring_disabled_for_tile(vm, tile->id))
+		return true;
+
 	(void)xe_pt_walk_shared(&pt->base, pt->level, xe_svm_range_start(range),
 				xe_svm_range_end(range), &xe_walk.base);
 
@@ -1988,7 +1999,7 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
 		.wupd.entries = entries,
 		.prl = pt_update_op->prl,
 	};
-	struct xe_pt *pt = vm->pt_root[tile->id];
+	struct xe_pt *pt = xe_vm_pt_root(vm, tile->id);
 
 	(void)xe_pt_walk_shared(&pt->base, pt->level, start, end,
 				&xe_walk.base);
@@ -2541,9 +2552,21 @@ int xe_pt_update_ops_prepare(struct xe_device *xe, struct xe_vma_ops *vops)
 	int id, err;
 
 	for_each_tile(tile, xe, id) {
+		struct xe_vm_pgtable_update_ops *pt_update_ops =
+			&vops->pt_update_ops[id];
+
 		if (!vops->pt_update_ops[id].num_ops)
 			continue;
 
+		if (pt_mirroring_disabled_for_tile(vops->vm, id)) {
+			struct xe_page_reclaim_list *prl = &pt_update_ops->prl;
+
+			/* Transfer root PT update ops PRL to current */
+			*prl = vops->pt_update_ops[0].prl;
+			xe_page_reclaim_entries_get(prl->entries);
+			continue;
+		}
+
 		err = __xe_pt_update_ops_prepare(tile, vops);
 		if (err)
 			return err;
@@ -2835,6 +2858,12 @@ xe_pt_update_ops_run(struct xe_device *xe, struct xe_vma_ops *vops)
 		struct xe_vm_pgtable_update_ops *pt_update_ops =
 			&vops->pt_update_ops[j];
 
+		if (pt_mirroring_disabled_for_tile(vm, j)) {
+			xe_tile_assert(tile, !get_current_op(pt_update_ops));
+			tile_mask |= BIT(tile->id);
+			continue;
+		}
+
 		for (i = 0; i < get_current_op(pt_update_ops); ++i) {
 			struct xe_vm_pgtable_update_op *pt_op =
 				to_pt_op(pt_update_ops, i);
@@ -2948,6 +2977,9 @@ void xe_pt_update_ops_abort(struct xe_device *xe, struct xe_vma_ops *vops)
 			&vops->pt_update_ops[id];
 		int i;
 
+		if (pt_mirroring_disabled_for_tile(vops->vm, id))
+			continue;
+
 		for (i = pt_update_ops->num_ops - 1; i >= 0; --i) {
 			struct xe_vm_pgtable_update_op *pt_op =
 				to_pt_op(pt_update_ops, i);
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index fbfc42afef8b..795d0ebb1004 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -845,6 +845,14 @@ int xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)
 	return err;
 }
 
+static u8 adjust_rebind_tile_mask(struct xe_vm *vm, u8 tile_mask)
+{
+	if (vm->xe->info.has_pt_mirror)
+		return tile_mask;
+
+	return (0x1 << vm->xe->info.tile_count) - 1;
+}
+
 struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_mask)
 {
 	struct dma_fence *fence = NULL;
@@ -861,7 +869,8 @@ struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_ma
 	vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT |
 		XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
 
-	err = xe_vm_ops_add_rebind(&vops, vma, tile_mask);
+	err = xe_vm_ops_add_rebind(&vops, vma,
+				   adjust_rebind_tile_mask(vm, tile_mask));
 	if (err)
 		return ERR_PTR(err);
 
@@ -948,7 +957,8 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm,
 	vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT |
 		XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
 
-	err = xe_vm_ops_add_range_rebind(&vops, vma, range, tile_mask);
+	err = xe_vm_ops_add_range_rebind(&vops, vma, range,
+					 adjust_rebind_tile_mask(vm, tile_mask));
 	if (err)
 		return ERR_PTR(err);
 
@@ -1738,7 +1748,8 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
 
 		for_each_tile(tile, xe, id) {
 			if (flags & XE_VM_FLAG_MIGRATION &&
-			    tile->id != XE_VM_FLAG_TILE_ID(flags))
+			    tile->id != XE_VM_FLAG_TILE_ID(flags) &&
+			    (vm->xe->info.has_pt_mirror || id))
 				continue;
 
 			vm->pt_root[id] = xe_pt_create(vm, tile, xe->info.vm_max_level,
@@ -2047,7 +2058,7 @@ struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id)
 
 u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile)
 {
-	return vm->pt_ops->pde_encode_bo(vm->pt_root[tile->id]->bo, 0);
+	return vm->pt_ops->pde_encode_bo(xe_vm_pt_root(vm, tile->id)->bo, 0);
 }
 
 static struct xe_exec_queue *
@@ -5072,3 +5083,21 @@ void xe_vm_remove_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)
 	}
 	up_write(&vm->exec_queues.lock);
 }
+
+/**
+ * xe_vm_pt_root() - Retrieve VM page-table root
+ * @vm: The VM.
+ * @tile_id: Tile ID
+ *
+ * Retrieve VM page-table root for a tile ID, used to abstract if PT mirroring is
+ * enabled across tiles.
+ *
+ * Return: VM page-table root for a tile ID
+ */
+struct xe_pt *xe_vm_pt_root(struct xe_vm *vm, u8 tile_id)
+{
+	if (vm->xe->info.has_pt_mirror)
+		return vm->pt_root[tile_id];
+
+	return vm->pt_root[0];
+}
diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h
index c5b900f38ded..89c4f95984a2 100644
--- a/drivers/gpu/drm/xe/xe_vm.h
+++ b/drivers/gpu/drm/xe/xe_vm.h
@@ -436,4 +436,7 @@ static inline struct drm_exec *xe_vm_validation_exec(struct xe_vm *vm)
 	((READ_ONCE(tile_present) & ~READ_ONCE(tile_invalidated)) & BIT((tile)->id))
 
 void xe_vma_mem_attr_copy(struct xe_vma_mem_attr *to, struct xe_vma_mem_attr *from);
+
+struct xe_pt *xe_vm_pt_root(struct xe_vm *vm, u8 tile_id);
+
 #endif
-- 
2.34.1

[PATCH v6 18/24] drm/xe: Add ULLS support to LRC

[Matthew Brost]

Define memory layout for ULLS semaphores stored in LRC memory. Add
support functions to return GGTT address and set semaphore based on a
job's seqno.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-20-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_lrc.c       | 73 +++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_lrc.h       |  4 ++
 drivers/gpu/drm/xe/xe_lrc_types.h |  4 ++
 3 files changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 25fe9dbc9141..c592e7b98072 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -706,6 +706,7 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
 #define LRC_CTX_JOB_TIMESTAMP_OFFSET 512
 #define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
 #define LRC_PARALLEL_PPHWSP_OFFSET 2048
+#define LRC_ULLS_PPHWSP_OFFSET 2048	/* Mutually exclusive with parallel */
 
 #define LRC_SEQNO_OFFSET 0
 #define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8)
@@ -768,6 +769,12 @@ static inline u32 __xe_lrc_engine_id_offset(struct xe_lrc *lrc)
 	return xe_lrc_pphwsp_offset(lrc) + LRC_ENGINE_ID_PPHWSP_OFFSET;
 }
 
+static u32 __xe_lrc_ulls_offset(struct xe_lrc *lrc)
+{
+	/* The ulls is stored in the driver-defined portion of PPHWSP */
+	return xe_lrc_pphwsp_offset(lrc) + LRC_ULLS_PPHWSP_OFFSET;
+}
+
 static u32 __xe_lrc_ctx_timestamp_offset(struct xe_lrc *lrc)
 {
 	return __xe_lrc_regs_offset(lrc) + CTX_TIMESTAMP * sizeof(u32);
@@ -835,6 +842,7 @@ DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo)
 DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo)
 DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo)
 DECL_MAP_ADDR_HELPERS(parallel, lrc->bo)
+DECL_MAP_ADDR_HELPERS(ulls, lrc->bo)
 DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo)
 DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo)
 DECL_MAP_ADDR_HELPERS(queue_timestamp, lrc->bo)
@@ -1805,6 +1813,26 @@ void xe_lrc_set_ring_tail(struct xe_lrc *lrc, u32 tail)
 		xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, tail);
 }
 
+/**
+ * xe_lrc_ring_tail_ggtt_addr() - Saved ring tail GGTT address
+ * @lrc: Pointer to the lrc.
+ *
+ * GGTT address of the ring tail as saved for this context - in the indirect
+ * ring state on platforms which have it, otherwise in the context image.
+ * This is what a context restore loads the tail register from, so a ring
+ * which advances the tail register itself must keep this in sync.
+ *
+ * Returns: saved ring tail GGTT address
+ */
+u32 xe_lrc_ring_tail_ggtt_addr(struct xe_lrc *lrc)
+{
+	if (xe_lrc_has_indirect_ring_state(lrc))
+		return __xe_lrc_indirect_ring_ggtt_addr(lrc) +
+			INDIRECT_CTX_RING_TAIL * sizeof(u32);
+
+	return __xe_lrc_regs_ggtt_addr(lrc) + CTX_RING_TAIL * sizeof(u32);
+}
+
 u32 xe_lrc_ring_tail(struct xe_lrc *lrc)
 {
 	if (xe_lrc_has_indirect_ring_state(lrc))
@@ -1984,6 +2012,51 @@ static u32 xe_lrc_engine_id(struct xe_lrc *lrc)
 	return xe_map_read32(xe, &map);
 }
 
+#define semaphore_offset(seqno) \
+	(sizeof(u32) * ((seqno) % LRC_MIGRATION_ULLS_SEMAPHORE_COUNT))
+
+/**
+ * xe_lrc_ulls_semaphore_ggtt_addr() - ULLS semaphore GGTT address
+ * @lrc: Pointer to the lrc.
+ * @seqno: seqno of current job.
+ *
+ * Calculate ULLS semaphore GGTT address based on input seqno
+ *
+ * Returns: ULLS semaphore GGTT address
+ */
+u32 xe_lrc_ulls_semaphore_ggtt_addr(struct xe_lrc *lrc, u32 seqno)
+{
+	xe_assert(lrc_to_xe(lrc), semaphore_offset(seqno) <
+		  LRC_PPHWSP_SIZE - LRC_ULLS_PPHWSP_OFFSET);
+
+	return __xe_lrc_ulls_ggtt_addr(lrc) + semaphore_offset(seqno);
+}
+
+/**
+ * xe_lrc_set_ulls_semaphore() - Set ULLS semaphore
+ * @lrc: Pointer to the lrc.
+ * @seqno: seqno of current job.
+ *
+ * Set ULLS semaphore based on input seqno
+ */
+void xe_lrc_set_ulls_semaphore(struct xe_lrc *lrc, u32 seqno)
+{
+	struct xe_device *xe = lrc_to_xe(lrc);
+	struct iosys_map map = __xe_lrc_ulls_map(lrc);
+
+	xe_assert(xe, semaphore_offset(seqno) <
+		  LRC_PPHWSP_SIZE - LRC_ULLS_PPHWSP_OFFSET);
+
+	/*
+	 * The ring contents this semaphore releases are ordered by the
+	 * xe_device_wmb() at the end of xe_lrc_write_ring().
+	 */
+	iosys_map_incr(&map, semaphore_offset(seqno));
+	xe_map_write32(xe, &map, LRC_MIGRATION_ULLS_SEMAPHORE_SIGNAL);
+
+	xe_device_wmb(xe);	/* Flush write to hardware */
+}
+
 static int instr_dw(u32 cmd_header)
 {
 	/* GFXPIPE "SINGLE_DW" opcodes are a single dword */
diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index 7be5e3da8bc8..9906ba1fac3e 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -112,6 +112,7 @@ u32 xe_lrc_regs_offset(struct xe_lrc *lrc);
 
 void xe_lrc_set_ring_tail(struct xe_lrc *lrc, u32 tail);
 u32 xe_lrc_ring_tail(struct xe_lrc *lrc);
+u32 xe_lrc_ring_tail_ggtt_addr(struct xe_lrc *lrc);
 void xe_lrc_set_ring_head(struct xe_lrc *lrc, u32 head);
 u32 xe_lrc_ring_head(struct xe_lrc *lrc);
 u32 xe_lrc_ring_space(struct xe_lrc *lrc);
@@ -127,6 +128,9 @@ void xe_default_lrc_update_memirq_regs_with_address(struct xe_hw_engine *hwe);
 void xe_lrc_update_memirq_regs_with_address(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
 					    u32 *regs);
 
+u32 xe_lrc_ulls_semaphore_ggtt_addr(struct xe_lrc *lrc, u32 seqno);
+void xe_lrc_set_ulls_semaphore(struct xe_lrc *lrc, u32 seqno);
+
 u32 xe_lrc_read_ctx_reg(struct xe_lrc *lrc, int reg_nr);
 void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val);
 
diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h b/drivers/gpu/drm/xe/xe_lrc_types.h
index 53ef48feebfc..b18daf1092e6 100644
--- a/drivers/gpu/drm/xe/xe_lrc_types.h
+++ b/drivers/gpu/drm/xe/xe_lrc_types.h
@@ -12,6 +12,10 @@
 
 struct xe_bo;
 
+#define LRC_MIGRATION_ULLS_SEMAPHORE_COUNT	64	/* Must be pow2 */
+#define LRC_MIGRATION_ULLS_SEMAPHORE_CLEAR	0
+#define LRC_MIGRATION_ULLS_SEMAPHORE_SIGNAL	1
+
 /**
  * struct xe_lrc - Logical ring context (LRC) and submission ring object
  */
-- 
2.34.1

[PATCH v6 19/24] drm/xe: Add ULLS migration job support to migration layer

[Matthew Brost]

Add function to enter ULLS mode for migration job and delayed worker to
exit (power saving). ULLS mode expected to entered upon page fault or
SVM prefetch. ULLS mode exit delay is currently set to 5ms.

ULLS mode only support on DGFX and USM platforms where a hardware engine
is reserved for migrations jobs. When in ULLS mode, set several flags on
migration jobs so submission backend / ring ops can properly submit in
ULLS mode.

Upon ULLS mode enter, send a job trigger waiting a semphore pipling
initial GuC / HW conetxt switch.

Upon ULLS mode exit, send a job to trigger that current ULLS
semaphore so the ring can be taken off the hardware.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-21-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_exec_queue.c      |   5 +-
 drivers/gpu/drm/xe/xe_exec_queue.h      |   2 +-
 drivers/gpu/drm/xe/xe_migrate.c         | 198 ++++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_migrate.h         |   2 +
 drivers/gpu/drm/xe/xe_pt.c              |   2 +-
 drivers/gpu/drm/xe/xe_sched_job.h       |  56 +++++++
 drivers/gpu/drm/xe/xe_sched_job_types.h |  19 +++
 drivers/gpu/drm/xe/xe_vm.c              |   2 +-
 8 files changed, 265 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index d4ae58cb2761..c1d0acf480dc 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -1546,6 +1546,7 @@ bool xe_exec_queue_is_lr(struct xe_exec_queue *q)
 /**
  * xe_exec_queue_is_idle() - Whether an exec_queue is idle.
  * @q: The exec_queue
+ * @extra_jobs: Extra jobs on the queue
  *
  * FIXME: Need to determine what to use as the short-lived
  * timeline lock for the exec_queues, so that the return value
@@ -1557,9 +1558,9 @@ bool xe_exec_queue_is_lr(struct xe_exec_queue *q)
  *
  * Return: True if the exec_queue is idle, false otherwise.
  */
-bool xe_exec_queue_is_idle(struct xe_exec_queue *q)
+bool xe_exec_queue_is_idle(struct xe_exec_queue *q, int extra_jobs)
 {
-	return !atomic_read(&q->job_cnt);
+	return !(atomic_read(&q->job_cnt) - extra_jobs);
 }
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h
index b02a390ba989..e8963f85cabd 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue.h
@@ -116,7 +116,7 @@ static inline struct xe_exec_queue *xe_exec_queue_multi_queue_primary(struct xe_
 
 bool xe_exec_queue_is_lr(struct xe_exec_queue *q);
 
-bool xe_exec_queue_is_idle(struct xe_exec_queue *q);
+bool xe_exec_queue_is_idle(struct xe_exec_queue *q, int extra_jobs);
 
 void xe_exec_queue_kill(struct xe_exec_queue *q);
 
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 471ae5741836..3e59aeeca614 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -8,6 +8,7 @@
 #include <linux/bitfield.h>
 #include <linux/sizes.h>
 
+#include <drm/drm_drv.h>
 #include <drm/drm_managed.h>
 #include <drm/drm_pagemap.h>
 #include <drm/ttm/ttm_tt.h>
@@ -23,6 +24,7 @@
 #include "xe_bb.h"
 #include "xe_bo.h"
 #include "xe_exec_queue.h"
+#include "xe_force_wake.h"
 #include "xe_ggtt.h"
 #include "xe_gt.h"
 #include "xe_gt_printk.h"
@@ -32,6 +34,7 @@
 #include "xe_mem_pool.h"
 #include "xe_mocs.h"
 #include "xe_pat.h"
+#include "xe_pm.h"
 #include "xe_printk.h"
 #include "xe_pt.h"
 #include "xe_res_cursor.h"
@@ -77,6 +80,14 @@ struct xe_migrate {
 	struct dma_fence *fence;
 	/** @min_chunk_size: For dgfx, Minimum chunk size */
 	u64 min_chunk_size;
+	/** @ulls: ULLS support */
+	struct {
+		/** @ulls.enabled: ULLS is enabled */
+		bool enabled;
+#define ULLS_EXIT_JIFFIES	msecs_to_jiffies(5)
+		/** @ulls.exit_work: ULLS exit worker */
+		struct delayed_work exit_work;
+	} ulls;
 };
 
 #define MAX_PREEMPTDISABLE_TRANSFER SZ_8M /* Around 1ms. */
@@ -98,6 +109,15 @@ struct xe_migrate {
 static void xe_migrate_fini(void *arg)
 {
 	struct xe_migrate *m = arg;
+	struct xe_device *xe = tile_to_xe(m->tile);
+
+	disable_delayed_work_sync(&m->ulls.exit_work);
+	mutex_lock(&m->job_mutex);
+	if (m->ulls.enabled) {
+		xe_pm_runtime_put(xe);
+		m->ulls.enabled = false;
+	}
+	mutex_unlock(&m->job_mutex);
 
 	xe_vm_lock(m->q->vm, false);
 	xe_bo_unpin(m->pt_bo);
@@ -448,6 +468,161 @@ static int xe_migrate_lock_prepare_vm(struct xe_tile *tile, struct xe_migrate *m
 	return err;
 }
 
+static struct dma_fence *__xe_migrate_job_push(struct xe_migrate *m,
+					       struct xe_sched_job *job,
+					       enum xe_ulls_state ulls)
+{
+	struct dma_fence *fence;
+
+	lockdep_assert_held(&m->job_mutex);
+	xe_tile_assert(m->tile, m->q == job->q);
+
+	job->ulls = ulls;
+	xe_sched_job_arm(job);
+	fence = dma_fence_get(&job->drm.s_fence->finished);
+	xe_sched_job_push(job);
+
+	return fence;
+}
+
+/*
+ * Arm and push a migration job, tagging it as a ULLS job and deferring the
+ * ULLS exit while ULLS mode is active.
+ *
+ * Returns a reference to the job's finished fence.
+ */
+static struct dma_fence *xe_migrate_job_push(struct xe_migrate *m,
+					     struct xe_sched_job *job)
+{
+	enum xe_ulls_state ulls = ULLS_NONE;
+
+	lockdep_assert_held(&m->job_mutex);
+
+	if (m->ulls.enabled) {
+		ulls = ULLS_ACTIVE;
+		mod_delayed_work(system_percpu_wq, &m->ulls.exit_work,
+				 ULLS_EXIT_JIFFIES);
+	}
+
+	return __xe_migrate_job_push(m, job, ulls);
+}
+
+/**
+ * xe_migrate_ulls_enter() - Enter ULLS mode
+ * @m: The migration context.
+ *
+ * If DGFX, enter ULLS mode bypassing GuC / HW context switches by utilizing
+ * semaphore and continuously running batches.
+ */
+void xe_migrate_ulls_enter(struct xe_migrate *m)
+{
+	struct xe_device *xe = tile_to_xe(m->tile);
+	struct xe_sched_job *job = NULL;
+	u64 batch_addr[2] = { 0, 0 };
+	bool alloc = false;
+
+	xe_assert(xe, xe->info.has_usm);
+
+	if (!IS_DGFX(xe))
+		return;
+
+job_alloc:
+	if (alloc) {
+		/*
+		 * Must be done outside job_mutex as that lock is tainted with
+		 * reclaim.
+		 */
+		job = xe_sched_job_create(m->q, batch_addr);
+		if (WARN_ON_ONCE(IS_ERR(job)))
+			return;		/* Not fatal */
+	}
+
+	mutex_lock(&m->job_mutex);
+	if (!m->ulls.enabled) {
+		struct dma_fence *fence;
+
+		if (!job) {
+			alloc = true;
+			mutex_unlock(&m->job_mutex);
+			goto job_alloc;
+		}
+
+		/* Pairs with PM put on ULLS exit */
+		xe_pm_runtime_get_noresume(xe);
+
+		xe_sched_job_get(job);
+		fence = __xe_migrate_job_push(m, job, ULLS_ENTER);
+		dma_fence_put(fence);
+
+		xe_dbg(xe, "Migrate ULLS mode enter");
+		m->ulls.enabled = true;
+	}
+	if (job)
+		xe_sched_job_put(job);
+	if (m->ulls.enabled)
+		mod_delayed_work(system_percpu_wq, &m->ulls.exit_work,
+				 ULLS_EXIT_JIFFIES);
+	mutex_unlock(&m->job_mutex);
+}
+
+static void xe_migrate_ulls_exit(struct work_struct *work)
+{
+	struct xe_migrate *m = container_of(work, struct xe_migrate,
+					    ulls.exit_work.work);
+	struct xe_device *xe = tile_to_xe(m->tile);
+	struct xe_sched_job *job = NULL;
+	struct dma_fence *fence;
+	u64 batch_addr[2] = { 0, 0 };
+	int idx;
+
+	xe_assert(xe, m->ulls.enabled);
+
+	if (!drm_dev_enter(&xe->drm, &idx))
+		return;
+
+	/*
+	 * Must be done outside job_mutex as that lock is tainted with
+	 * reclaim and must be done holding a pm ref.
+	 */
+	job = xe_sched_job_create(m->q, batch_addr);
+	if (WARN_ON_ONCE(IS_ERR(job))) {
+		drm_dev_exit(idx);
+		mod_delayed_work(system_percpu_wq, &m->ulls.exit_work,
+				 ULLS_EXIT_JIFFIES);
+		return;		/* Not fatal */
+	}
+
+	mutex_lock(&m->job_mutex);
+
+	if (!xe_exec_queue_is_idle(m->q, 1))
+		goto unlock_exit;
+
+	xe_sched_job_get(job);
+	fence = __xe_migrate_job_push(m, job, ULLS_EXIT);
+
+	/* Serialize the PM put against the ring being taken off the hardware */
+	dma_fence_wait(fence, false);
+	dma_fence_put(fence);
+
+	m->ulls.enabled = false;
+unlock_exit:
+	if (job)
+		xe_sched_job_put(job);
+	if (!m->ulls.enabled) {
+		/* Pairs with PM get on enter */
+		xe_pm_runtime_put(xe);
+
+		cancel_delayed_work(&m->ulls.exit_work);
+		xe_dbg(xe, "Migrate ULLS mode exit");
+	} else {
+		mod_delayed_work(system_percpu_wq, &m->ulls.exit_work,
+				 ULLS_EXIT_JIFFIES);
+	}
+
+	mutex_unlock(&m->job_mutex);
+	drm_dev_exit(idx);
+}
+
 /**
  * xe_migrate_init() - Initialize a migrate context
  * @m: The migration context
@@ -506,6 +681,8 @@ int xe_migrate_init(struct xe_migrate *m)
 	might_lock(&m->job_mutex);
 	fs_reclaim_release(GFP_KERNEL);
 
+	INIT_DELAYED_WORK(&m->ulls.exit_work, xe_migrate_ulls_exit);
+
 	err = devm_add_action_or_reset(xe->drm.dev, xe_migrate_fini, m);
 	if (err)
 		return err;
@@ -1033,10 +1210,8 @@ static struct dma_fence *__xe_migrate_copy(struct xe_migrate *m,
 		}
 
 		mutex_lock(&m->job_mutex);
-		xe_sched_job_arm(job);
 		dma_fence_put(fence);
-		fence = dma_fence_get(&job->drm.s_fence->finished);
-		xe_sched_job_push(job);
+		fence = xe_migrate_job_push(m, job);
 
 		dma_fence_put(m->fence);
 		m->fence = dma_fence_get(fence);
@@ -1464,10 +1639,8 @@ struct dma_fence *xe_migrate_vram_copy_chunk(struct xe_bo *vram_bo, u64 vram_off
 						     DMA_RESV_USAGE_BOOKKEEP));
 
 		scoped_guard(mutex, &m->job_mutex) {
-			xe_sched_job_arm(job);
 			dma_fence_put(fence);
-			fence = dma_fence_get(&job->drm.s_fence->finished);
-			xe_sched_job_push(job);
+			fence = xe_migrate_job_push(m, job);
 
 			dma_fence_put(m->fence);
 			m->fence = dma_fence_get(fence);
@@ -1701,10 +1874,8 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
 		}
 
 		mutex_lock(&m->job_mutex);
-		xe_sched_job_arm(job);
 		dma_fence_put(fence);
-		fence = dma_fence_get(&job->drm.s_fence->finished);
-		xe_sched_job_push(job);
+		fence = xe_migrate_job_push(m, job);
 
 		dma_fence_put(m->fence);
 		m->fence = dma_fence_get(fence);
@@ -1980,9 +2151,7 @@ static struct dma_fence *xe_migrate_vram(struct xe_migrate *m,
 	}
 
 	mutex_lock(&m->job_mutex);
-	xe_sched_job_arm(job);
-	fence = dma_fence_get(&job->drm.s_fence->finished);
-	xe_sched_job_push(job);
+	fence = xe_migrate_job_push(m, job);
 
 	dma_fence_put(m->fence);
 	m->fence = dma_fence_get(fence);
@@ -2299,10 +2468,7 @@ int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
 		xe_sched_job_add_migrate_flush(job, MI_FLUSH_DW_CCS);
 
 		mutex_lock(&m->job_mutex);
-		xe_sched_job_arm(job);
-
-		fence = dma_fence_get(&job->drm.s_fence->finished);
-		xe_sched_job_push(job);
+		fence = xe_migrate_job_push(m, job);
 		mutex_unlock(&m->job_mutex);
 
 		dma_fence_wait(fence, false);
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index fa381ec36ef1..2e8be10fdb71 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -97,4 +97,6 @@ int xe_migrate_debug_ccs_overlap(struct xe_migrate *m,
 				 bool write_to_ccs);
 #endif
 
+void xe_migrate_ulls_enter(struct xe_migrate *m);
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 7e42067c79e4..885cd7eb8d28 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -1427,7 +1427,7 @@ static int xe_pt_vm_dependencies(struct xe_sched_job *job,
 	if (!job && !no_in_syncs(vops->syncs, vops->num_syncs))
 		return -ETIME;
 
-	if (!job && !xe_exec_queue_is_idle(vops->q))
+	if (!job && !xe_exec_queue_is_idle(vops->q, 0))
 		return -ETIME;
 
 	if (vops->flags & (XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP |
diff --git a/drivers/gpu/drm/xe/xe_sched_job.h b/drivers/gpu/drm/xe/xe_sched_job.h
index 1c1cb44216c3..74ee3279a301 100644
--- a/drivers/gpu/drm/xe/xe_sched_job.h
+++ b/drivers/gpu/drm/xe/xe_sched_job.h
@@ -83,6 +83,62 @@ xe_sched_job_add_migrate_flush(struct xe_sched_job *job, u32 flags)
 	job->migrate_flush_flags = flags;
 }
 
+/**
+ * xe_sched_job_is_ulls - Is a ULLS job
+ * @job: Xe schedule job object
+ *
+ * Return: True if @job is submitted as part of a ULLS sequence, False
+ * otherwise.
+ */
+static inline bool xe_sched_job_is_ulls(struct xe_sched_job *job)
+{
+	return job->ulls != ULLS_NONE;
+}
+
+/**
+ * xe_sched_job_ulls_has_batch - Does a job carry batch buffers
+ * @job: Xe schedule job object
+ *
+ * The ULLS jobs which enter and exit ULLS mode exist only to move the
+ * migration context on and off the hardware, and carry no batch buffers.
+ *
+ * Return: True if @job carries batch buffers, False otherwise.
+ */
+static inline bool xe_sched_job_ulls_has_batch(struct xe_sched_job *job)
+{
+	return job->ulls == ULLS_NONE || job->ulls == ULLS_ACTIVE;
+}
+
+/**
+ * xe_sched_job_ulls_parks - Does a job park the engine for its successor
+ * @job: Xe schedule job object
+ *
+ * A ULLS job which is not the last one emits a postamble, parking the engine
+ * on its successor's semaphore and publishing that successor's ring tail.
+ *
+ * Return: True if @job emits a ULLS postamble, False otherwise.
+ */
+static inline bool xe_sched_job_ulls_parks(struct xe_sched_job *job)
+{
+	return job->ulls == ULLS_ENTER || job->ulls == ULLS_ACTIVE;
+}
+
+/**
+ * xe_sched_job_ulls_is_chained - Has a job's predecessor already published it
+ * @job: Xe schedule job object
+ *
+ * A ULLS job which is not the first one has had its ring tail published by its
+ * predecessor's postamble, which also left the engine parked on this job's
+ * semaphore. Submitting it is a semaphore write alone - no H2G and no ring
+ * tail write.
+ *
+ * Return: True if @job was published by its predecessor, False otherwise.
+ */
+static inline bool xe_sched_job_ulls_is_chained(struct xe_sched_job *job)
+{
+	return job->ulls == ULLS_ACTIVE || job->ulls == ULLS_EXIT;
+}
+
 bool xe_sched_job_is_migration(struct xe_exec_queue *q);
 
 struct xe_sched_job_snapshot *xe_sched_job_snapshot_capture(struct xe_sched_job *job);
diff --git a/drivers/gpu/drm/xe/xe_sched_job_types.h b/drivers/gpu/drm/xe/xe_sched_job_types.h
index 9f527ac6df3e..c8cdbe68843f 100644
--- a/drivers/gpu/drm/xe/xe_sched_job_types.h
+++ b/drivers/gpu/drm/xe/xe_sched_job_types.h
@@ -49,6 +49,23 @@ struct xe_job_ptrs {
 	u32 head;
 };
 
+/**
+ * enum xe_ulls_state - ULLS state of a migration job
+ *
+ * Describes where a job sits in a ULLS (Ultra Low Latency Submission)
+ * sequence. See the ULLS documentation in xe_migrate.c.
+ */
+enum xe_ulls_state {
+	/** @ULLS_NONE: Not a ULLS job */
+	ULLS_NONE = 0,
+	/** @ULLS_ENTER: Job which enters ULLS mode */
+	ULLS_ENTER,
+	/** @ULLS_ACTIVE: Job submitted while in ULLS mode */
+	ULLS_ACTIVE,
+	/** @ULLS_EXIT: Job which exits ULLS mode */
+	ULLS_EXIT,
+};
+
 /**
  * struct xe_sched_job - Xe schedule job (batch buffer tracking)
  */
@@ -79,6 +96,8 @@ struct xe_sched_job {
 	u32 migrate_flush_flags;
 	/** @sample_timestamp: Sampling of job timestamp in TDR */
 	u64 sample_timestamp;
+	/** @ulls: ULLS state of this job */
+	enum xe_ulls_state ulls;
 	/** @ring_ops_flush_tlb: The ring ops need to flush TLB before payload. */
 	bool ring_ops_flush_tlb;
 	/** @ring_ops_force_reset: The ring ops need to trigger a reset before payload. */
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 795d0ebb1004..ee4d149b7453 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -148,7 +148,7 @@ static bool xe_vm_is_idle(struct xe_vm *vm)
 
 	xe_vm_assert_held(vm);
 	list_for_each_entry(q, &vm->preempt.exec_queues, lr.link) {
-		if (!xe_exec_queue_is_idle(q))
+		if (!xe_exec_queue_is_idle(q, 0))
 			return false;
 	}
 
-- 
2.34.1

[PATCH v6 20/24] drm/xe: Add ULLS migration job support to ring ops

[Matthew Brost]

Add preamble and postamble for ULLS migrations jobs. Preamble clears
current semaphore for reuse. Postamble waits on next semaphore which is
set upon next job submission, then advances the ring tail over that job
with an LRI to RING_TAIL, so submitting it costs the CPU nothing beyond
signalling the semaphore.

A job updates the tail on behalf of a successor which has not been
emitted yet, so it cannot know how much ring that successor will occupy.
Pad every ULLS job out to a fixed ULLS_JOB_SIZE_BYTES, which makes the
next tail derivable from where the current job starts. The pad also
supplies the NOPs which must follow an in-ring tail update.

The last ULLS migration job skips BB submission, the postamble and the
tail update (clear current semaphore, write seqno, exit ULLS), padding
the difference so that it still fills a job slot.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-23-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_ring_ops.c       | 86 ++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_ring_ops_types.h | 24 +++++++
 2 files changed, 110 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 39a670e91ba7..f05b4276c8d1 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -494,6 +494,79 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 	xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
 }
 
+static int emit_ulls_preamble(struct xe_lrc *lrc, u32 *dw, int i, u32 seqno)
+{
+	u32 addr = xe_lrc_ulls_semaphore_ggtt_addr(lrc, seqno);
+
+	return emit_store_imm_ggtt(addr, LRC_MIGRATION_ULLS_SEMAPHORE_CLEAR,
+				   dw, i);
+}
+
+/*
+ * Advance the ring tail from within the ring, so submitting the next ULLS job
+ * needs nothing from the CPU beyond signalling the semaphore. All ULLS jobs
+ * occupy exactly ULLS_JOB_SIZE_BYTES, so the tail the next job ends at is two
+ * job slots on from where this job started, even though that job has not been
+ * emitted yet.
+ *
+ * The saved tail is written before the tail register so that a context save
+ * racing the pair can only restore a tail behind the register, never ahead of
+ * it. The register write is deliberately not MI_LRI_FORCE_POSTED: posted, the
+ * new tail can land after the command streamer has already drained this job,
+ * at which point it sees an empty ring, parks, and can be taken off the
+ * hardware with no H2G left to bring it back.
+ *
+ * The tail is published before the semaphore wait rather than after it, so
+ * that the non-posted write drains while the engine is parked anyway instead
+ * of adding a register round trip after the semaphore is signalled.
+ */
+static int emit_ulls_ring_tail(struct xe_gt *gt, struct xe_lrc *lrc, u32 *dw,
+			       int i, u32 head)
+{
+	u32 next_tail = (head + 2 * ULLS_JOB_SIZE_BYTES) & (lrc->ring.size - 1);
+
+	xe_gt_assert(gt, IS_ALIGNED(next_tail, 8));
+
+	i = emit_store_imm_ggtt(xe_lrc_ring_tail_ggtt_addr(lrc), next_tail,
+				dw, i);
+
+	dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) |
+		MI_LRI_LRM_CS_MMIO;
+	dw[i++] = RING_TAIL(0).addr;
+	dw[i++] = next_tail;
+
+	return i;
+}
+
+/* Publish the next job's tail, then park the engine on its semaphore */
+static int emit_ulls_postamble(struct xe_gt *gt, struct xe_lrc *lrc, u32 *dw,
+			       int i, u32 seqno, u32 head)
+{
+	i = emit_ulls_ring_tail(gt, lrc, dw, i, head);
+
+	dw[i++] = MI_SEMAPHORE_WAIT |
+		MI_SEMW_GGTT |
+		MI_SEMW_POLL |
+		MI_SEMW_COMPARE(SAD_EQ_SDD);
+	dw[i++] = LRC_MIGRATION_ULLS_SEMAPHORE_SIGNAL;
+	dw[i++] = xe_lrc_ulls_semaphore_ggtt_addr(lrc, seqno + 1);
+	dw[i++] = 0;
+	dw[i++] = 0;
+
+	return i;
+}
+
+/* Pad out to the fixed ULLS job size */
+static int emit_ulls_pad(struct xe_gt *gt, u32 *dw, int i)
+{
+	xe_gt_assert(gt, i <= ULLS_JOB_SIZE_DW);
+
+	while (i < ULLS_JOB_SIZE_DW)
+		dw[i++] = MI_NOOP;
+
+	return i;
+}
+
 static void emit_migration_job_gen12(struct xe_sched_job *job,
 				     struct xe_lrc *lrc, u32 *head,
 				     u32 seqno)
@@ -507,10 +580,16 @@ static void emit_migration_job_gen12(struct xe_sched_job *job,
 
 	xe_gt_assert(gt, !job->ring_ops_force_reset);
 
+	if (xe_sched_job_is_ulls(job))
+		i = emit_ulls_preamble(lrc, dw, i, seqno);
+
 	i = emit_copy_timestamp(xe, lrc, dw, i);
 
 	i = emit_store_imm_ggtt(saddr, seqno, dw, i);
 
+	if (!xe_sched_job_ulls_has_batch(job))
+		goto seqno_write;
+
 	dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; /* Enabled again below */
 
 	i = emit_bb_start(job->ptrs[0].batch_addr, BIT(8), dw, i);
@@ -521,12 +600,19 @@ static void emit_migration_job_gen12(struct xe_sched_job *job,
 
 	i = emit_bb_start(job->ptrs[1].batch_addr, BIT(8), dw, i);
 
+seqno_write:
 	i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno,
 				job->migrate_flush_flags,
 				dw, i);
 
 	i = emit_user_interrupt(dw, i);
 
+	if (xe_sched_job_ulls_parks(job))
+		i = emit_ulls_postamble(gt, lrc, dw, i, seqno, *head);
+
+	if (xe_sched_job_is_ulls(job))
+		i = emit_ulls_pad(gt, dw, i);
+
 	xe_gt_assert(job->q->gt, i <= MAX_JOB_SIZE_DW);
 
 	xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
index 52ff96bc4100..ea4af321dd7c 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
+++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
@@ -6,6 +6,7 @@
 #ifndef _XE_RING_OPS_TYPES_H_
 #define _XE_RING_OPS_TYPES_H_
 
+#include <linux/build_bug.h>
 #include <linux/types.h>
 
 struct xe_gt;
@@ -14,6 +15,29 @@ struct xe_sched_job;
 #define MAX_JOB_SIZE_DW 74
 #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
 
+/*
+ * ULLS migration jobs advance the ring tail from within the ring itself, so a
+ * job has to know where its successor will end before that successor has been
+ * emitted. Every ULLS job is therefore padded to a fixed size, letting the
+ * next tail be derived arithmetically.
+ *
+ * Sized for the largest such job, emitted by emit_migration_job_gen12():
+ * preamble (4), copy timestamp (8, its size on an SRIOV VF), start seqno
+ * store (4), arbitration off (1), batch buffer starts (2 * 3), pre-parser
+ * bracketed flush invalidate (6), seqno flush (4), user interrupt (3) and
+ * postamble (7 + 5).
+ */
+#define ULLS_JOB_SIZE_DW 48
+#define ULLS_JOB_SIZE_BYTES (ULLS_JOB_SIZE_DW * 4)
+
+/*
+ * RING_TAIL only encodes a qword aligned offset, and xe_lrc_write_ring()
+ * appends a NOP to anything shorter, either of which would desynchronise the
+ * ring from the tail a job predicts for its successor.
+ */
+static_assert(ULLS_JOB_SIZE_BYTES % 8 == 0);
+static_assert(ULLS_JOB_SIZE_DW <= MAX_JOB_SIZE_DW);
+
 /**
  * struct xe_ring_ops - Ring operations
  */
-- 
2.34.1

[PATCH v6 21/24] drm/xe: Add ULLS migration job support to GuC submission

[Matthew Brost]

Add ULLS migration job support to GuC submission backend.

Changes required:
- On migration queue, reduce max jobs to the number of ULLS semaphores
  minus one
- Skip writing the saved ring tail for ULLS jobs except for the first
  ULLS job - the ring updates both the saved tail and the tail register
  itself
- Set ULLS sempahore for current job releasing last job except for first
  ULLS job
- Suppress submit H2G for ULLS except for first ULLS job

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-24-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_guc_submit.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 5e3e911a397b..a83360fcbbf3 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -1189,9 +1189,10 @@ static void submit_exec_queue(struct xe_exec_queue *q, struct xe_sched_job *job)
 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
 
 	if (!job->restore_replay || job->last_replay) {
+		/* A ULLS job past the first publishes its own ring tail */
 		if (xe_exec_queue_is_parallel(q))
 			wq_item_append(q);
-		else
+		else if (!xe_sched_job_ulls_is_chained(job))
 			xe_lrc_set_ring_tail(lrc, lrc->ring.tail);
 		job->last_replay = false;
 	}
@@ -1208,6 +1209,9 @@ static void submit_exec_queue(struct xe_exec_queue *q, struct xe_sched_job *job)
 	if (exec_queue_suspended(q))
 		return;
 
+	if (xe_sched_job_ulls_is_chained(job))
+		xe_lrc_set_ulls_semaphore(lrc, xe_sched_job_lrc_seqno(job));
+
 	if (!exec_queue_enabled(q)) {
 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET;
 		action[len++] = q->guc->id;
@@ -1221,13 +1225,14 @@ static void submit_exec_queue(struct xe_exec_queue *q, struct xe_sched_job *job)
 		set_exec_queue_pending_enable(q);
 		set_exec_queue_enabled(q);
 		trace_xe_exec_queue_scheduling_enable(q);
-	} else {
+	} else if (!xe_sched_job_ulls_is_chained(job)) {
 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT;
 		action[len++] = q->guc->id;
 		trace_xe_exec_queue_submit(q);
 	}
 
-	xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h);
+	if (!xe_sched_job_ulls_is_chained(job) || num_g2h)
+		xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h);
 
 	if (extra_submit) {
 		len = 0;
@@ -2098,6 +2103,7 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
 	struct xe_guc_exec_queue *ge;
 	long timeout;
 	int err, i;
+	int max_jobs = (xe_lrc_ring_size() / MAX_JOB_SIZE_BYTES);
 
 	xe_gt_assert(guc_to_gt(guc), xe_device_uc_enabled(guc_to_xe(guc)));
 
@@ -2137,8 +2143,11 @@ static int guc_exec_queue_init(struct xe_exec_queue *q)
 		submit_wq = primary->guc->sched.base.submit_wq;
 	}
 
+	if (q->vm && q->vm->flags & XE_VM_FLAG_MIGRATION)
+		max_jobs = min(max_jobs, LRC_MIGRATION_ULLS_SEMAPHORE_COUNT - 1);
+
 	err = xe_sched_init(&ge->sched, &drm_sched_ops, &xe_sched_ops,
-			    submit_wq, xe_lrc_ring_size() / MAX_JOB_SIZE_BYTES, 64,
+			    submit_wq, max_jobs, 64,
 			    timeout, guc_to_gt(guc)->ordered_wq, NULL,
 			    ge->name, gt_to_xe(q->gt)->drm.dev);
 	if (err)
-- 
2.34.1

[PATCH v6 22/24] drm/xe: Enter ULLS for migration jobs upon page fault or SVM prefetch

[Matthew Brost]

Call xe_migration_ulls_enter upon page fault or SVM prefetch in an
effort speed up these critical paths.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-25-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_pagefault.c | 3 +++
 drivers/gpu/drm/xe/xe_vm.c        | 4 +++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_pagefault.c b/drivers/gpu/drm/xe/xe_pagefault.c
index e81ca24df37f..ecf2530f0284 100644
--- a/drivers/gpu/drm/xe/xe_pagefault.c
+++ b/drivers/gpu/drm/xe/xe_pagefault.c
@@ -15,6 +15,7 @@
 #include "xe_gt_stats.h"
 #include "xe_hw_engine.h"
 #include "xe_log.h"
+#include "xe_migrate.h"
 #include "xe_pagefault.h"
 #include "xe_pagefault_types.h"
 #include "xe_svm.h"
@@ -262,6 +263,8 @@ static int xe_pagefault_service(struct xe_pagefault *pf)
 	if (IS_ERR(vm))
 		return PTR_ERR(vm);
 
+	xe_migrate_ulls_enter(gt_to_tile(gt)->migrate);
+
 	down_read(&vm->lock);
 
 	if (xe_vm_is_closed(vm)) {
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index ee4d149b7453..c68d3baf1988 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -2526,8 +2526,10 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_vma_ops *vops,
 			ctx.devmem_possible = IS_DGFX(vm->xe) &&
 					      IS_ENABLED(CONFIG_DRM_XE_PAGEMAP);
 
-			for_each_tile(tile, vm->xe, id)
+			for_each_tile(tile, vm->xe, id) {
+				xe_migrate_ulls_enter(tile->migrate);
 				tile_mask |= 0x1 << id;
+			}
 
 			if (prefetch_region == DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC) {
 				dpagemap = xe_vma_resolve_pagemap(vma,
-- 
2.34.1

[PATCH v6 23/24] drm/xe: Add modparam to enable / disable ULLS on migrate queue

[Matthew Brost]

Having modparam to enable / disable ULLS on migrate queue will help with
quick experiments.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260228013501.106680-26-matthew.brost@intel.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_debugfs.c      | 1 +
 drivers/gpu/drm/xe/xe_defaults.h     | 1 +
 drivers/gpu/drm/xe/xe_device.c       | 1 +
 drivers/gpu/drm/xe/xe_device_types.h | 5 +++++
 drivers/gpu/drm/xe/xe_migrate.c      | 2 +-
 drivers/gpu/drm/xe/xe_module.c       | 4 ++++
 drivers/gpu/drm/xe/xe_module.h       | 1 +
 7 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index 80f62634fae5..f3f37d116d62 100644
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -222,6 +222,7 @@ static int info(struct seq_file *m, void *data)
 	drm_printf(&p, "revid %d\n", xe->info.revid);
 	drm_printf(&p, "tile_count %d\n", xe->info.tile_count);
 	drm_printf(&p, "vm_max_level %d\n", xe->info.vm_max_level);
+	drm_printf(&p, "ulls_enable %s\n", str_yes_no(xe->info.ulls_enable));
 	drm_printf(&p, "has_flat_ccs %s\n", str_yes_no(xe->info.has_flat_ccs));
 	drm_printf(&p, "has_usm %s\n", str_yes_no(xe->info.has_usm));
 	drm_printf(&p, "skip_guc_pc %s\n", str_yes_no(xe->info.skip_guc_pc));
diff --git a/drivers/gpu/drm/xe/xe_defaults.h b/drivers/gpu/drm/xe/xe_defaults.h
index 0884224ef7c7..9c7e89a169c5 100644
--- a/drivers/gpu/drm/xe/xe_defaults.h
+++ b/drivers/gpu/drm/xe/xe_defaults.h
@@ -14,6 +14,7 @@
 #endif
 
 #define XE_DEFAULT_PROBE_DISPLAY		IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
+#define XE_DEFAULT_ULLS_ENABLE			true
 #define XE_DEFAULT_VRAM_BAR_SIZE		0
 #define XE_DEFAULT_FORCE_PROBE			CONFIG_DRM_XE_FORCE_PROBE
 #define XE_DEFAULT_MAX_VFS			~0
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index ade971de1652..9b81759af28a 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -520,6 +520,7 @@ static void xe_device_parse_modparam(struct xe_device *xe)
 	xe->atomic_svm_timeslice_ms = 5;
 	xe->min_run_period_lr_ms = 5;
 	xe->info.num_pf_work = xe_modparam.num_pf_work;
+	xe->info.ulls_enable = xe_modparam.ulls_enable;
 	if (xe->info.num_pf_work < 1)
 		xe->info.num_pf_work = 1;
 	else if (xe->info.num_pf_work > XE_PAGEFAULT_WORK_MAX)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 997ac82fd571..fd4560378f5b 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -245,6 +245,11 @@ struct xe_device {
 		u8 skip_pcode:1;
 		/** @info.needs_shared_vf_gt_wq: needs shared GT WQ on VF */
 		u8 needs_shared_vf_gt_wq:1;
+		/**
+		 * @info.ulls_enable: Enable ULLS on migration queue in LR VM
+		 * open
+		 */
+		u8 ulls_enable:1;
 	} info;
 
 	/** @wa_active: keep track of active workarounds */
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 3e59aeeca614..3bc78f761f23 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -523,7 +523,7 @@ void xe_migrate_ulls_enter(struct xe_migrate *m)
 
 	xe_assert(xe, xe->info.has_usm);
 
-	if (!IS_DGFX(xe))
+	if (!IS_DGFX(xe) || !xe->info.ulls_enable)
 		return;
 
 job_alloc:
diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
index 4bc28dfc1992..a8b546550ead 100644
--- a/drivers/gpu/drm/xe/xe_module.c
+++ b/drivers/gpu/drm/xe/xe_module.c
@@ -23,6 +23,7 @@
 
 struct xe_modparam xe_modparam = {
 	.probe_display =	XE_DEFAULT_PROBE_DISPLAY,
+	.ulls_enable =		XE_DEFAULT_ULLS_ENABLE,
 	.guc_log_level =	XE_DEFAULT_GUC_LOG_LEVEL,
 	.force_probe =		XE_DEFAULT_FORCE_PROBE,
 #ifdef CONFIG_PCI_IOV
@@ -44,6 +45,9 @@ MODULE_PARM_DESC(probe_display, "Probe display HW, otherwise it's left untouched
 		 "[default=" __stringify(XE_DEFAULT_PROBE_DISPLAY) "])");
 #endif
 
+module_param_named(ulls_enable, xe_modparam.ulls_enable, bool, 0444);
+MODULE_PARM_DESC(ulls_enable, "Enable ULLS on migration queue if LR VM open (default: true)");
+
 module_param_named(vram_bar_size, xe_modparam.force_vram_bar_size, int, 0600);
 MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size in MiB (<0=disable-resize, 0=max-needed-size, >0=force-size "
 		 "[default=" __stringify(XE_DEFAULT_VRAM_BAR_SIZE) "])");
diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
index 6272d9e41207..5d88448c298a 100644
--- a/drivers/gpu/drm/xe/xe_module.h
+++ b/drivers/gpu/drm/xe/xe_module.h
@@ -13,6 +13,7 @@ struct work_struct;
 /* Module modprobe variables */
 struct xe_modparam {
 	bool probe_display;
+	bool ulls_enable;
 	int force_vram_bar_size;
 	int guc_log_level;
 	char *guc_firmware_path;
-- 
2.34.1

[PATCH v6 24/24] drm/xe: Document ULLS for migration jobs

[Matthew Brost]

Add a kernel-doc DOC section at the top of xe_migrate.c describing the
Ultra Low Latency Submission (ULLS) scheme used for migration jobs.

Cover the motivation (removing the H2G / GuC / context switch latency
from the page fault and SVM prefetch critical paths), the platform
requirements, the LRC PPHWSP semaphore layout and its relationship to
the migration queue job count, the fixed ULLS job size and why it is
needed, the ring preamble / postamble emitted by the ring ops including
the in-ring tail update, the semaphore-only submission fast path in the
GuC backend, and the enter / delayed exit flow along with the ULLS job
flags.

Hook the new section into Documentation/gpu/xe/xe_migrate.rst.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Assisted-by: Github-Copilot:Claude-opus-5
---
 Documentation/gpu/xe/xe_migrate.rst |   3 +
 drivers/gpu/drm/xe/xe_migrate.c     | 146 ++++++++++++++++++++++++++++
 2 files changed, 149 insertions(+)

diff --git a/Documentation/gpu/xe/xe_migrate.rst b/Documentation/gpu/xe/xe_migrate.rst
index f92faec0ac94..d297ee53a582 100644
--- a/Documentation/gpu/xe/xe_migrate.rst
+++ b/Documentation/gpu/xe/xe_migrate.rst
@@ -6,3 +6,6 @@ Migrate Layer
 
 .. kernel-doc:: drivers/gpu/drm/xe/xe_migrate_doc.h
    :doc: Migrate Layer
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_migrate.c
+   :doc: ULLS (Ultra Low Latency Submission) for migration jobs
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 3bc78f761f23..94ad1e7e8bc4 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -48,6 +48,152 @@
 #include "xe_vm.h"
 #include "xe_vram.h"
 
+/**
+ * DOC: ULLS (Ultra Low Latency Submission) for migration jobs
+ *
+ * Migration jobs issued on behalf of GPU page faults and SVM prefetches sit
+ * directly in the critical path of a stalled GPU workload. The dominant cost
+ * of such a job is not the copy or clear itself but the submission latency:
+ * the H2G round trip to GuC, the GuC scheduling decision, and the hardware
+ * context switch required to place the migration LRC on an engine.
+ *
+ * ULLS removes that cost by keeping the migration context resident and
+ * *running* on the hardware engine across jobs. Instead of the ring going
+ * empty and the context being switched out between jobs, the tail of every
+ * ULLS job parks the engine on a semaphore wait for the *next* job's
+ * semaphore, and then advances the ring tail itself. Submitting the next job
+ * therefore costs the CPU a single write to signal that semaphore - no H2G,
+ * no GuC round trip, no context switch, no MMIO.
+ *
+ * Requirements
+ * ------------
+ *
+ * ULLS is only used on DGFX with USM support (where a hardware engine is
+ * reserved exclusively for migration jobs). Because the engine is spinning
+ * on a semaphore while ULLS is active, it can not be shared with user
+ * submissions. It can also be disabled at load time with the
+ * ``xe.ulls_enable`` module parameter.
+ *
+ * Fixed size jobs
+ * ---------------
+ *
+ * A job updates the ring tail to cover its successor, but it is emitted long
+ * before that successor exists, so it can not know how much ring the
+ * successor will occupy. Every ULLS job is therefore padded out to exactly
+ * ULLS_JOB_SIZE_BYTES, which lets the next tail be computed arithmetically
+ * from where the current job started.
+ *
+ * This is why the shorter jobs still have to reach the same size: the "last"
+ * job skips the batch buffers and the postamble, and pads the difference with
+ * MI_NOOP. The "first" job is not covered by any predecessor's tail update
+ * and so is unconstrained, but is padded anyway to keep the arithmetic
+ * uniform.
+ *
+ * Leaving ULLS mode always goes through a "last" job, which emits no tail
+ * update, so an ordinary variable length migration job never follows a
+ * prediction.
+ *
+ * Semaphores
+ * ----------
+ *
+ * The semaphores live in the driver-defined portion of the migration LRC's
+ * PPHWSP (see LRC_ULLS_PPHWSP_OFFSET, mutually exclusive with the parallel
+ * submission area). There are LRC_MIGRATION_ULLS_SEMAPHORE_COUNT of them and
+ * a job's semaphore is selected by ``seqno % COUNT``, so the semaphore ring
+ * wraps with the job seqnos. To guarantee a job can never overwrite the
+ * semaphore of a job still in flight, the GuC backend caps the migration
+ * queue's scheduler job count at LRC_MIGRATION_ULLS_SEMAPHORE_COUNT - 1.
+ *
+ * Ring layout of a ULLS job
+ * -------------------------
+ *
+ * Emitted by emit_migration_job_gen12() in xe_ring_ops.c::
+ *
+ *	preamble:	clear semaphore[seqno]	(reuse for a later wrap)
+ *	<copy timestamp, start seqno store>
+ *	<batch buffer start(s)>			(skipped on first/last job)
+ *	<seqno write + user interrupt>
+ *	postamble:	SDI saved ring tail = end of next job
+ *			LRI RING_TAIL = end of next job
+ *			wait on semaphore[seqno + 1]
+ *						(skipped on the last job)
+ *	pad:		MI_NOOP up to ULLS_JOB_SIZE_DW
+ *
+ * The preamble clears the current job's semaphore so it can be reused once
+ * the seqno space wraps. The postamble is what keeps the engine busy: it
+ * advances the ring tail over the next job and then blocks on that job's
+ * semaphore, which is only signaled when the job is actually submitted. It
+ * advances the saved tail as well as the tail register, keeping the two in
+ * step without any help from the CPU, so a context save and restore can not
+ * rewind the tail behind work which has already been published.
+ *
+ * The tail register write must be non-posted, i.e. it must not carry
+ * MI_LRI_FORCE_POSTED. Posted, the new tail is free to land after the command
+ * streamer has already drained the rest of the job, at which point the command
+ * streamer sees head == the old tail and parks as though the ring were empty.
+ * A parked context can be switched off the hardware, and the fast path below
+ * has no H2G with which to ask GuC to bring it back.
+ *
+ * The tail is published ahead of the semaphore wait rather than after it so
+ * that the non-posted write drains while the engine is parked anyway, keeping
+ * a register round trip off the path between the semaphore being signaled and
+ * the next job running.
+ *
+ * Submission fast path
+ * --------------------
+ *
+ * In submit_exec_queue() (xe_guc_submit.c), a ULLS job that is not the first
+ * one reduces to::
+ *
+ *	xe_lrc_set_ulls_semaphore(lrc, seqno);		release previous job
+ *
+ * The XE_GUC_ACTION_SCHED_CONTEXT H2G is suppressed, and so is the write of
+ * the saved ring tail: the previous job's postamble has already published
+ * this job's tail both in the tail register and in the context image, so the
+ * semaphore signal is all that is left. The previous job's semaphore wait is
+ * satisfied and the engine walks straight into this job.
+ *
+ * This does assume the context stays resident for as long as ULLS mode is
+ * active. Nothing else is scheduled on the reserved engine, so the only ways
+ * off the hardware are the "last" job below, or a reset - and a migration job
+ * failing already wedges the device.
+ *
+ * Enter / exit
+ * ------------
+ *
+ * xe_migrate_ulls_enter() is called from the page fault handler and from the
+ * SVM prefetch path, i.e. exactly where low latency migration matters. It
+ * takes a PM runtime reference (the device must not suspend while the engine
+ * spins), then submits a "first" ULLS job. That first job carries no batch
+ * buffer; it exists only to get the context onto the hardware through the
+ * normal GuC path and to leave the engine waiting on the next semaphore,
+ * pipelining the GuC/HW context switch out of the critical path.
+ *
+ * No forcewake reference is required. Nothing in the fast path touches MMIO,
+ * and the engine keeps itself awake for as long as it is executing the ring.
+ * Not needing host MMIO access is also what lets ULLS run on SRIOV VFs.
+ *
+ * Keeping an engine spinning costs power, so ULLS is not left enabled
+ * indefinitely. Every enter and every ULLS job submission re-arms
+ * @xe_migrate.ulls.exit_work with a ULLS_EXIT_JIFFIES delay. When it fires
+ * with the queue idle, it submits a "last" ULLS job - again with no batch
+ * buffer and, crucially, with no postamble semaphore wait or tail update -
+ * which lets the ring drain so the context can be switched off the hardware.
+ * The PM reference is then dropped. If the queue was not idle, the worker
+ * simply re-arms itself.
+ *
+ * Job state
+ * ---------
+ *
+ * The state above is communicated to the ring ops and GuC backend via
+ * @xe_sched_job.ulls, set under @xe_migrate.job_mutex:
+ *
+ * - %ULLS_NONE: job submitted outside of ULLS mode
+ * - %ULLS_ENTER: job that enters ULLS mode
+ * - %ULLS_ACTIVE: job submitted while in ULLS mode
+ * - %ULLS_EXIT: job that exits ULLS mode
+ */
+
 /**
  * struct xe_migrate - migrate context.
  */
-- 
2.34.1

Re: [PATCH v6 04/24] drm/xe: Add job count to GuC exec queue snapshot

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Format specifier mismatch when printing `jobcount`
--

commit bcb5e4e44e3808966c558f04a63143c713dbc759
Author: Matthew Brost <matthew.brost@intel.com>
drm/xe: Add job count to GuC exec queue snapshot

This commit adds the job count to the GuC exec queue snapshot to provide
useful debugging information.

Link: https://patch.msgid.link/20260228013501.106680-5-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 0a6e2b81b5a53..8b8673f4e037c 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
[ ... ]
> @@ -3756,6 +3757,7 @@ xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snaps
>  	drm_printf(p, "\tLogical mask: 0x%x\n", snapshot->logical_mask);
>  	drm_printf(p, "\tWidth: %d\n", snapshot->width);
>  	drm_printf(p, "\tRef: %d\n", snapshot->refcount);
> +	drm_printf(p, "\tJob count: %d\n", snapshot->jobcount);

[Severity: Low]
Does this code use the wrong format specifier for jobcount?

In xe_guc_submit_types.h, jobcount is declared as an unsigned 32-bit integer
(u32), but it is printed here in xe_guc_exec_queue_snapshot_print() using
the signed %d format specifier instead of %u. While the maximum job count
(1000) easily fits within a signed 32-bit integer, this formally violates
the printf-style format string API constraints.

>  	drm_printf(p, "\tTimeout: %ld (ms)\n", snapshot->sched_timeout);
>  	drm_printf(p, "\tTimeslice: %u (us)\n",
>  		   snapshot->sched_props.timeslice_us);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=4

✗ CI.checkpatch: warning for CPU binds and ULLS on migration queue (rev8)

[Patchwork]

== Series Details ==

Series: CPU binds and ULLS on migration queue (rev8)
URL   : https://patchwork.freedesktop.org/series/149888/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
d875049d2b299159a272bd5151994970cdcd1e31
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit e92543fdc87afd04b2716f44030cb0b79a8b0538
Author: Matthew Brost <matthew.brost@intel.com>
Date:   Fri Sep 4 14:16:13 2026 -0700

    drm/xe: Document ULLS for migration jobs
    
    Add a kernel-doc DOC section at the top of xe_migrate.c describing the
    Ultra Low Latency Submission (ULLS) scheme used for migration jobs.
    
    Cover the motivation (removing the H2G / GuC / context switch latency
    from the page fault and SVM prefetch critical paths), the platform
    requirements, the LRC PPHWSP semaphore layout and its relationship to
    the migration queue job count, the fixed ULLS job size and why it is
    needed, the ring preamble / postamble emitted by the ring ops including
    the in-ring tail update, the semaphore-only submission fast path in the
    GuC backend, and the enter / delayed exit flow along with the ULLS job
    flags.
    
    Hook the new section into Documentation/gpu/xe/xe_migrate.rst.
    
    Signed-off-by: Matthew Brost <matthew.brost@intel.com>
    Assisted-by: Github-Copilot:Claude-opus-5
+ /mt/dim checkpatch 313da1cc22491f07075c7ae36372343aa235d11e drm-intel
3f0964f19092 drm/xe: Drop struct xe_migrate_pt_update argument from populate/clear vfuns
0bb0f74b37c4 drm/xe: Add xe_migrate_update_pgtables_cpu_execute helper
903bc751a0f4 drm/xe: Decouple exec queue idle check from LRC
3ae94e6432cf drm/xe: Add job count to GuC exec queue snapshot
74d624faf20e drm/xe: Update xe_bo_put_deferred arguments to include writeback flag
e0fec97de72d drm/xe: Add XE_BO_FLAG_PUT_VM_ASYNC
c55bdbf1cd3e drm/xe: Update scheduler job layer to support PT jobs
416b38624fd1 drm/xe: Add helpers to access PT ops
0a45e1658d52 drm/xe: Add struct xe_pt_job_ops
c33eb11129ab drm/xe: Update GuC submission backend to run PT jobs
4e1c7a1b0327 drm/xe: Store level in struct xe_vm_pgtable_update
6bf01c038cba drm/xe: Don't use migrate exec queue for page fault binds
682c481214c5 drm/xe: Enable CPU binds for jobs
7897ddeca8bb drm/xe: Remove unused arguments from xe_migrate_pt_update_ops
f136941207a5 drm/xe: Make bind queues operate cross-tile
-:306: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#306: FILE: drivers/gpu/drm/xe/xe_exec_queue.h:17:
+#define for_each_tlb_inval(__q, __i)	\
+	for (__i = 0; __i < XE_EXEC_QUEUE_TLB_INVAL_COUNT; ++__i)	\
+		for_each_if((__q)->tlb_inval[__i].dep_scheduler)

total: 0 errors, 0 warnings, 1 checks, 624 lines checked
11ea65bba5b6 drm/xe: Add CPU bind layer
-:34: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 2327 lines checked
18be7d565070 drm/xe: Add device flag to enable PT mirroring across tiles
30af6af543f0 drm/xe: Add ULLS support to LRC
b1686ea4a5c3 drm/xe: Add ULLS migration job support to migration layer
c126c1ce3e60 drm/xe: Add ULLS migration job support to ring ops
fc79d48c2f1f drm/xe: Add ULLS migration job support to GuC submission
4678e0f306bf drm/xe: Enter ULLS for migration jobs upon page fault or SVM prefetch
b3f372e9a7b0 drm/xe: Add modparam to enable / disable ULLS on migrate queue
e92543fdc87a drm/xe: Document ULLS for migration jobs

✓ CI.KUnit: success for CPU binds and ULLS on migration queue (rev8)

[Patchwork]

== Series Details ==

Series: CPU binds and ULLS on migration queue (rev8)
URL   : https://patchwork.freedesktop.org/series/149888/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[21:24:18] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:24:22] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:24:43] Starting KUnit Kernel (1/1)...
[21:24:43] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:24:43] ============= refcount_interrupt (4 subtests) ==============
[21:24:43] [PASSED] test_single_irq_change
[21:24:43] [PASSED] test_nested_irq_change
[21:24:43] [PASSED] test_multiple_irq_change
[21:24:43] [PASSED] test_irq_save
[21:24:43] =============== [PASSED] refcount_interrupt ================
[21:24:43] ================= gpu_buddy (14 subtests) ==================
[21:24:43] [PASSED] gpu_test_buddy_alloc_limit
[21:24:43] [PASSED] gpu_test_buddy_alloc_optimistic
[21:24:43] [PASSED] gpu_test_buddy_alloc_pessimistic
[21:24:43] [PASSED] gpu_test_buddy_alloc_pathological
[21:24:43] [PASSED] gpu_test_buddy_alloc_contiguous
[21:24:43] [PASSED] gpu_test_buddy_alloc_clear
[21:24:43] [PASSED] gpu_test_buddy_alloc_range
[21:24:43] [PASSED] gpu_test_buddy_alloc_range_bias
[21:24:44] [PASSED] gpu_test_buddy_fragmentation_performance
[21:24:44] [PASSED] gpu_test_buddy_dirty_tracker_performance
[21:24:44] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[21:24:44] [PASSED] gpu_test_buddy_offset_aligned_allocation
[21:24:44] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[21:24:44] [PASSED] gpu_test_buddy_addr_to_block
[21:24:44] ==================== [PASSED] gpu_buddy ====================
[21:24:44] ============================================================
[21:24:44] Testing complete. Ran 18 tests: passed: 18
[21:24:45] Elapsed time: 26.862s total, 4.401s configuring, 20.543s building, 1.862s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:24:45] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:24:46] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:25:21] Starting KUnit Kernel (1/1)...
[21:25:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:25:21] ============= refcount_interrupt (4 subtests) ==============
[21:25:21] [PASSED] test_single_irq_change
[21:25:21] [PASSED] test_nested_irq_change
[21:25:21] [PASSED] test_multiple_irq_change
[21:25:21] [PASSED] test_irq_save
[21:25:21] =============== [PASSED] refcount_interrupt ================
[21:25:21] ================== guc_buf (11 subtests) ===================
[21:25:21] [PASSED] test_smallest
[21:25:21] [PASSED] test_largest
[21:25:21] [PASSED] test_granular
[21:25:21] [PASSED] test_unique
[21:25:21] [PASSED] test_overlap
[21:25:21] [PASSED] test_reusable
[21:25:21] [PASSED] test_too_big
[21:25:21] [PASSED] test_flush
[21:25:21] [PASSED] test_lookup
[21:25:21] [PASSED] test_data
[21:25:21] [PASSED] test_class
[21:25:21] ===================== [PASSED] guc_buf =====================
[21:25:21] =================== guc_dbm (7 subtests) ===================
[21:25:21] [PASSED] test_empty
[21:25:21] [PASSED] test_default
[21:25:21] ======================== test_size  ========================
[21:25:21] [PASSED] 4
[21:25:21] [PASSED] 8
[21:25:21] [PASSED] 32
[21:25:21] [PASSED] 256
[21:25:21] ==================== [PASSED] test_size ====================
[21:25:21] ======================= test_reuse  ========================
[21:25:21] [PASSED] 4
[21:25:21] [PASSED] 8
[21:25:21] [PASSED] 32
[21:25:21] [PASSED] 256
[21:25:21] =================== [PASSED] test_reuse ====================
[21:25:21] =================== test_range_overlap  ====================
[21:25:21] [PASSED] 4
[21:25:21] [PASSED] 8
[21:25:21] [PASSED] 32
[21:25:21] [PASSED] 256
[21:25:21] =============== [PASSED] test_range_overlap ================
[21:25:21] =================== test_range_compact  ====================
[21:25:21] [PASSED] 4
[21:25:21] [PASSED] 8
[21:25:21] [PASSED] 32
[21:25:21] [PASSED] 256
[21:25:21] =============== [PASSED] test_range_compact ================
[21:25:21] ==================== test_range_spare  =====================
[21:25:21] [PASSED] 4
[21:25:21] [PASSED] 8
[21:25:21] [PASSED] 32
[21:25:21] [PASSED] 256
[21:25:21] ================ [PASSED] test_range_spare =================
[21:25:21] ===================== [PASSED] guc_dbm =====================
[21:25:21] =================== guc_idm (6 subtests) ===================
[21:25:21] [PASSED] bad_init
[21:25:21] [PASSED] no_init
[21:25:21] [PASSED] init_fini
[21:25:21] [PASSED] check_used
[21:25:21] [PASSED] check_quota
[21:25:21] [PASSED] check_all
[21:25:21] ===================== [PASSED] guc_idm =====================
[21:25:21] =============== guc_klv_helpers (9 subtests) ===============
[21:25:21] [PASSED] test_count
[21:25:21] [PASSED] test_encode_u32
[21:25:21] [PASSED] test_encode_u64
[21:25:21] [PASSED] test_encode_string
[21:25:21] [PASSED] test_encode_object_raw
[21:25:21] [PASSED] test_encode_object_klv
[21:25:21] [PASSED] test_encode_object_nested
[21:25:21] [PASSED] test_encode_object_basic
[21:25:21] [PASSED] test_print
[21:25:21] ================= [PASSED] guc_klv_helpers =================
[21:25:21] =================== xe_log (4 subtests) ====================
[21:25:21] [PASSED] demo_cper
[21:25:21] [PASSED] demo_dmesg
[21:25:21] ======================= test_dmesg  ========================
[21:25:21] [PASSED] test_fatal
[21:25:21] [PASSED] test_fatal_tile
[21:25:21] [PASSED] test_fatal_gt
[21:25:21] [PASSED] test_fatal_comp
[21:25:21] [PASSED] test_fatal_comp_tile
[21:25:21] [PASSED] test_fatal_comp_gt
[21:25:21] [PASSED] test_fatal_all
[21:25:21] [PASSED] test_recoverable
[21:25:21] [PASSED] test_recoverable_tile
[21:25:21] [PASSED] test_recoverable_gt
[21:25:21] [PASSED] test_recoverable_comp
[21:25:21] [PASSED] test_recoverable_comp_tile
[21:25:21] [PASSED] test_recoverable_comp_gt
[21:25:21] [PASSED] test_recoverable_all
[21:25:21] [PASSED] test_info
[21:25:21] [PASSED] test_info_tile
[21:25:21] [PASSED] test_info_gt
[21:25:21] [PASSED] test_info_err
[21:25:21] [PASSED] test_info_comp
[21:25:21] [PASSED] test_info_comp_tile
[21:25:21] [PASSED] test_info_comp_gt
[21:25:21] [PASSED] test_info_all
[21:25:21] [PASSED] test_hw_fatal
[21:25:21] [PASSED] test_hw_recoverable
[21:25:21] [PASSED] test_hw_corrected
[21:25:21] [PASSED] test_hw_informational
[21:25:21] =================== [PASSED] test_dmesg ====================
[21:25:21] ====================== test_invalid  =======================
[21:25:21] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[21:25:21] ================== [SKIPPED] test_invalid ==================
[21:25:21] ===================== [PASSED] xe_log ======================
[21:25:21] ================== no_relay (3 subtests) ===================
[21:25:21] [PASSED] xe_drops_guc2pf_if_not_ready
[21:25:21] [PASSED] xe_drops_guc2vf_if_not_ready
[21:25:21] [PASSED] xe_rejects_send_if_not_ready
[21:25:21] ==================== [PASSED] no_relay =====================
[21:25:21] ================== pf_relay (14 subtests) ==================
[21:25:21] [PASSED] pf_rejects_guc2pf_too_short
[21:25:21] [PASSED] pf_rejects_guc2pf_too_long
[21:25:21] [PASSED] pf_rejects_guc2pf_no_payload
[21:25:21] [PASSED] pf_fails_no_payload
[21:25:21] [PASSED] pf_fails_bad_origin
[21:25:21] [PASSED] pf_fails_bad_type
[21:25:21] [PASSED] pf_txn_reports_error
[21:25:21] [PASSED] pf_txn_sends_pf2guc
[21:25:21] [PASSED] pf_sends_pf2guc
[21:25:21] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:25:21] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:25:21] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:25:21] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:25:21] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[21:25:21] ==================== [PASSED] pf_relay =====================
[21:25:21] ================== vf_relay (3 subtests) ===================
[21:25:21] [PASSED] vf_rejects_guc2vf_too_short
[21:25:21] [PASSED] vf_rejects_guc2vf_too_long
[21:25:21] [PASSED] vf_rejects_guc2vf_no_payload
[21:25:21] ==================== [PASSED] vf_relay =====================
[21:25:21] ================ pf_gt_config (9 subtests) =================
[21:25:21] [PASSED] fair_contexts_1vf
[21:25:21] [PASSED] fair_doorbells_1vf
[21:25:21] [PASSED] fair_ggtt_1vf
[21:25:21] ====================== fair_vram_1vf  ======================
[21:25:21] [PASSED] 3.50 GiB
[21:25:21] [PASSED] 11.5 GiB
[21:25:21] [PASSED] 15.5 GiB
[21:25:21] [PASSED] 31.5 GiB
[21:25:21] [PASSED] 63.5 GiB
[21:25:21] [PASSED] 1.91 GiB
[21:25:21] ================== [PASSED] fair_vram_1vf ==================
[21:25:21] ================ fair_vram_1vf_admin_only  =================
[21:25:21] [PASSED] 3.50 GiB
[21:25:21] [PASSED] 11.5 GiB
[21:25:21] [PASSED] 15.5 GiB
[21:25:21] [PASSED] 31.5 GiB
[21:25:21] [PASSED] 63.5 GiB
[21:25:21] [PASSED] 1.91 GiB
[21:25:21] ============ [PASSED] fair_vram_1vf_admin_only =============
[21:25:21] ====================== fair_contexts  ======================
[21:25:21] [PASSED] 1 VF
[21:25:21] [PASSED] 2 VFs
[21:25:21] [PASSED] 3 VFs
[21:25:21] [PASSED] 4 VFs
[21:25:21] [PASSED] 5 VFs
[21:25:21] [PASSED] 6 VFs
[21:25:21] [PASSED] 7 VFs
[21:25:21] [PASSED] 8 VFs
[21:25:21] [PASSED] 9 VFs
[21:25:21] [PASSED] 10 VFs
[21:25:21] [PASSED] 11 VFs
[21:25:21] [PASSED] 12 VFs
[21:25:21] [PASSED] 13 VFs
[21:25:21] [PASSED] 14 VFs
[21:25:21] [PASSED] 15 VFs
[21:25:21] [PASSED] 16 VFs
[21:25:21] [PASSED] 17 VFs
[21:25:21] [PASSED] 18 VFs
[21:25:21] [PASSED] 19 VFs
[21:25:21] [PASSED] 20 VFs
[21:25:21] [PASSED] 21 VFs
[21:25:21] [PASSED] 22 VFs
[21:25:21] [PASSED] 23 VFs
[21:25:21] [PASSED] 24 VFs
[21:25:21] [PASSED] 25 VFs
[21:25:21] [PASSED] 26 VFs
[21:25:21] [PASSED] 27 VFs
[21:25:21] [PASSED] 28 VFs
[21:25:21] [PASSED] 29 VFs
[21:25:21] [PASSED] 30 VFs
[21:25:21] [PASSED] 31 VFs
[21:25:21] [PASSED] 32 VFs
[21:25:21] [PASSED] 33 VFs
[21:25:21] [PASSED] 34 VFs
[21:25:21] [PASSED] 35 VFs
[21:25:21] [PASSED] 36 VFs
[21:25:21] [PASSED] 37 VFs
[21:25:21] [PASSED] 38 VFs
[21:25:21] [PASSED] 39 VFs
[21:25:21] [PASSED] 40 VFs
[21:25:21] [PASSED] 41 VFs
[21:25:21] [PASSED] 42 VFs
[21:25:21] [PASSED] 43 VFs
[21:25:21] [PASSED] 44 VFs
[21:25:21] [PASSED] 45 VFs
[21:25:21] [PASSED] 46 VFs
[21:25:21] [PASSED] 47 VFs
[21:25:21] [PASSED] 48 VFs
[21:25:21] [PASSED] 49 VFs
[21:25:21] [PASSED] 50 VFs
[21:25:21] [PASSED] 51 VFs
[21:25:21] [PASSED] 52 VFs
[21:25:21] [PASSED] 53 VFs
[21:25:21] [PASSED] 54 VFs
[21:25:21] [PASSED] 55 VFs
[21:25:21] [PASSED] 56 VFs
[21:25:21] [PASSED] 57 VFs
[21:25:21] [PASSED] 58 VFs
[21:25:21] [PASSED] 59 VFs
[21:25:21] [PASSED] 60 VFs
[21:25:21] [PASSED] 61 VFs
[21:25:21] [PASSED] 62 VFs
[21:25:21] [PASSED] 63 VFs
[21:25:21] ================== [PASSED] fair_contexts ==================
[21:25:21] ===================== fair_doorbells  ======================
[21:25:21] [PASSED] 1 VF
[21:25:21] [PASSED] 2 VFs
[21:25:21] [PASSED] 3 VFs
[21:25:21] [PASSED] 4 VFs
[21:25:21] [PASSED] 5 VFs
[21:25:21] [PASSED] 6 VFs
[21:25:21] [PASSED] 7 VFs
[21:25:21] [PASSED] 8 VFs
[21:25:21] [PASSED] 9 VFs
[21:25:21] [PASSED] 10 VFs
[21:25:21] [PASSED] 11 VFs
[21:25:21] [PASSED] 12 VFs
[21:25:21] [PASSED] 13 VFs
[21:25:21] [PASSED] 14 VFs
[21:25:21] [PASSED] 15 VFs
[21:25:21] [PASSED] 16 VFs
[21:25:21] [PASSED] 17 VFs
[21:25:21] [PASSED] 18 VFs
[21:25:21] [PASSED] 19 VFs
[21:25:21] [PASSED] 20 VFs
[21:25:21] [PASSED] 21 VFs
[21:25:21] [PASSED] 22 VFs
[21:25:21] [PASSED] 23 VFs
[21:25:21] [PASSED] 24 VFs
[21:25:21] [PASSED] 25 VFs
[21:25:21] [PASSED] 26 VFs
[21:25:21] [PASSED] 27 VFs
[21:25:21] [PASSED] 28 VFs
[21:25:21] [PASSED] 29 VFs
[21:25:21] [PASSED] 30 VFs
[21:25:21] [PASSED] 31 VFs
[21:25:21] [PASSED] 32 VFs
[21:25:21] [PASSED] 33 VFs
[21:25:21] [PASSED] 34 VFs
[21:25:21] [PASSED] 35 VFs
[21:25:21] [PASSED] 36 VFs
[21:25:21] [PASSED] 37 VFs
[21:25:21] [PASSED] 38 VFs
[21:25:21] [PASSED] 39 VFs
[21:25:21] [PASSED] 40 VFs
[21:25:21] [PASSED] 41 VFs
[21:25:21] [PASSED] 42 VFs
[21:25:21] [PASSED] 43 VFs
[21:25:21] [PASSED] 44 VFs
[21:25:21] [PASSED] 45 VFs
[21:25:21] [PASSED] 46 VFs
[21:25:21] [PASSED] 47 VFs
[21:25:21] [PASSED] 48 VFs
[21:25:21] [PASSED] 49 VFs
[21:25:21] [PASSED] 50 VFs
[21:25:21] [PASSED] 51 VFs
[21:25:21] [PASSED] 52 VFs
[21:25:21] [PASSED] 53 VFs
[21:25:21] [PASSED] 54 VFs
[21:25:21] [PASSED] 55 VFs
[21:25:21] [PASSED] 56 VFs
[21:25:21] [PASSED] 57 VFs
[21:25:21] [PASSED] 58 VFs
[21:25:21] [PASSED] 59 VFs
[21:25:21] [PASSED] 60 VFs
[21:25:21] [PASSED] 61 VFs
[21:25:21] [PASSED] 62 VFs
[21:25:21] [PASSED] 63 VFs
[21:25:21] ================= [PASSED] fair_doorbells ==================
[21:25:21] ======================== fair_ggtt  ========================
[21:25:21] [PASSED] 1 VF
[21:25:21] [PASSED] 2 VFs
[21:25:21] [PASSED] 3 VFs
[21:25:21] [PASSED] 4 VFs
[21:25:21] [PASSED] 5 VFs
[21:25:21] [PASSED] 6 VFs
[21:25:21] [PASSED] 7 VFs
[21:25:21] [PASSED] 8 VFs
[21:25:21] [PASSED] 9 VFs
[21:25:21] [PASSED] 10 VFs
[21:25:21] [PASSED] 11 VFs
[21:25:21] [PASSED] 12 VFs
[21:25:21] [PASSED] 13 VFs
[21:25:21] [PASSED] 14 VFs
[21:25:21] [PASSED] 15 VFs
[21:25:21] [PASSED] 16 VFs
[21:25:21] [PASSED] 17 VFs
[21:25:21] [PASSED] 18 VFs
[21:25:21] [PASSED] 19 VFs
[21:25:21] [PASSED] 20 VFs
[21:25:21] [PASSED] 21 VFs
[21:25:21] [PASSED] 22 VFs
[21:25:21] [PASSED] 23 VFs
[21:25:21] [PASSED] 24 VFs
[21:25:21] [PASSED] 25 VFs
[21:25:21] [PASSED] 26 VFs
[21:25:21] [PASSED] 27 VFs
[21:25:21] [PASSED] 28 VFs
[21:25:21] [PASSED] 29 VFs
[21:25:21] [PASSED] 30 VFs
[21:25:21] [PASSED] 31 VFs
[21:25:21] [PASSED] 32 VFs
[21:25:21] [PASSED] 33 VFs
[21:25:21] [PASSED] 34 VFs
[21:25:21] [PASSED] 35 VFs
[21:25:21] [PASSED] 36 VFs
[21:25:21] [PASSED] 37 VFs
[21:25:21] [PASSED] 38 VFs
[21:25:21] [PASSED] 39 VFs
[21:25:21] [PASSED] 40 VFs
[21:25:21] [PASSED] 41 VFs
[21:25:21] [PASSED] 42 VFs
[21:25:21] [PASSED] 43 VFs
[21:25:21] [PASSED] 44 VFs
[21:25:21] [PASSED] 45 VFs
[21:25:21] [PASSED] 46 VFs
[21:25:21] [PASSED] 47 VFs
[21:25:21] [PASSED] 48 VFs
[21:25:21] [PASSED] 49 VFs
[21:25:21] [PASSED] 50 VFs
[21:25:21] [PASSED] 51 VFs
[21:25:21] [PASSED] 52 VFs
[21:25:21] [PASSED] 53 VFs
[21:25:21] [PASSED] 54 VFs
[21:25:21] [PASSED] 55 VFs
[21:25:21] [PASSED] 56 VFs
[21:25:21] [PASSED] 57 VFs
[21:25:21] [PASSED] 58 VFs
[21:25:21] [PASSED] 59 VFs
[21:25:21] [PASSED] 60 VFs
[21:25:21] [PASSED] 61 VFs
[21:25:21] [PASSED] 62 VFs
[21:25:21] [PASSED] 63 VFs
[21:25:21] ==================== [PASSED] fair_ggtt ====================
[21:25:21] ======================== fair_vram  ========================
[21:25:21] [PASSED] 1 VF
[21:25:21] [PASSED] 2 VFs
[21:25:21] [PASSED] 3 VFs
[21:25:21] [PASSED] 4 VFs
[21:25:21] [PASSED] 5 VFs
[21:25:21] [PASSED] 6 VFs
[21:25:21] [PASSED] 7 VFs
[21:25:21] [PASSED] 8 VFs
[21:25:21] [PASSED] 9 VFs
[21:25:21] [PASSED] 10 VFs
[21:25:21] [PASSED] 11 VFs
[21:25:21] [PASSED] 12 VFs
[21:25:21] [PASSED] 13 VFs
[21:25:21] [PASSED] 14 VFs
[21:25:21] [PASSED] 15 VFs
[21:25:21] [PASSED] 16 VFs
[21:25:21] [PASSED] 17 VFs
[21:25:21] [PASSED] 18 VFs
[21:25:21] [PASSED] 19 VFs
[21:25:21] [PASSED] 20 VFs
[21:25:21] [PASSED] 21 VFs
[21:25:21] [PASSED] 22 VFs
[21:25:21] [PASSED] 23 VFs
[21:25:21] [PASSED] 24 VFs
[21:25:21] [PASSED] 25 VFs
[21:25:21] [PASSED] 26 VFs
[21:25:21] [PASSED] 27 VFs
[21:25:21] [PASSED] 28 VFs
[21:25:21] [PASSED] 29 VFs
[21:25:21] [PASSED] 30 VFs
[21:25:21] [PASSED] 31 VFs
[21:25:21] [PASSED] 32 VFs
[21:25:21] [PASSED] 33 VFs
[21:25:21] [PASSED] 34 VFs
[21:25:21] [PASSED] 35 VFs
[21:25:21] [PASSED] 36 VFs
[21:25:21] [PASSED] 37 VFs
[21:25:21] [PASSED] 38 VFs
[21:25:21] [PASSED] 39 VFs
[21:25:21] [PASSED] 40 VFs
[21:25:21] [PASSED] 41 VFs
[21:25:21] [PASSED] 42 VFs
[21:25:21] [PASSED] 43 VFs
[21:25:21] [PASSED] 44 VFs
[21:25:21] [PASSED] 45 VFs
[21:25:21] [PASSED] 46 VFs
[21:25:21] [PASSED] 47 VFs
[21:25:21] [PASSED] 48 VFs
[21:25:21] [PASSED] 49 VFs
[21:25:21] [PASSED] 50 VFs
[21:25:21] [PASSED] 51 VFs
[21:25:21] [PASSED] 52 VFs
[21:25:21] [PASSED] 53 VFs
[21:25:21] [PASSED] 54 VFs
[21:25:21] [PASSED] 55 VFs
[21:25:21] [PASSED] 56 VFs
[21:25:21] [PASSED] 57 VFs
[21:25:21] [PASSED] 58 VFs
[21:25:21] [PASSED] 59 VFs
[21:25:21] [PASSED] 60 VFs
[21:25:21] [PASSED] 61 VFs
[21:25:21] [PASSED] 62 VFs
[21:25:21] [PASSED] 63 VFs
[21:25:21] ==================== [PASSED] fair_vram ====================
[21:25:21] ================== [PASSED] pf_gt_config ===================
[21:25:21] ===================== lmtt (1 subtest) =====================
[21:25:21] ======================== test_ops  =========================
[21:25:21] [PASSED] 2-level
[21:25:21] [PASSED] multi-level
[21:25:21] ==================== [PASSED] test_ops =====================
[21:25:21] ====================== [PASSED] lmtt =======================
[21:25:21] ================= sriov_packet (1 subtest) =================
[21:25:21] [PASSED] test_descriptor_init
[21:25:21] ================== [PASSED] sriov_packet ===================
[21:25:21] ================= pf_service (11 subtests) =================
[21:25:21] [PASSED] pf_negotiate_any
[21:25:21] [PASSED] pf_negotiate_base_match
[21:25:21] [PASSED] pf_negotiate_base_newer
[21:25:21] [PASSED] pf_negotiate_base_next
[21:25:21] [SKIPPED] pf_negotiate_base_older (no older minor)
[21:25:21] [PASSED] pf_negotiate_base_prev
[21:25:21] [PASSED] pf_negotiate_latest_match
[21:25:21] [PASSED] pf_negotiate_latest_newer
[21:25:21] [PASSED] pf_negotiate_latest_next
[21:25:21] [SKIPPED] pf_negotiate_latest_older (no older minor)
[21:25:21] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[21:25:21] =================== [PASSED] pf_service ====================
[21:25:21] ================= xe_guc_g2g (2 subtests) ==================
[21:25:21] ============== xe_live_guc_g2g_kunit_default  ==============
[21:25:21] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:25:21] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:25:21] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:25:21] =================== [SKIPPED] xe_guc_g2g ===================
[21:25:21] =================== xe_mocs (2 subtests) ===================
[21:25:21] ================ xe_live_mocs_kernel_kunit  ================
[21:25:21] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:25:21] ================ xe_live_mocs_reset_kunit  =================
[21:25:21] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:25:21] ==================== [SKIPPED] xe_mocs =====================
[21:25:21] ================= xe_migrate (2 subtests) ==================
[21:25:21] ================= xe_migrate_sanity_kunit  =================
[21:25:21] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:25:21] ================== xe_validate_ccs_kunit  ==================
[21:25:21] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:25:21] =================== [SKIPPED] xe_migrate ===================
[21:25:21] ================== xe_dma_buf (1 subtest) ==================
[21:25:21] ==================== xe_dma_buf_kunit  =====================
[21:25:21] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:25:21] =================== [SKIPPED] xe_dma_buf ===================
[21:25:21] ================= xe_bo_shrink (1 subtest) =================
[21:25:21] =================== xe_bo_shrink_kunit  ====================
[21:25:21] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:25:21] ================== [SKIPPED] xe_bo_shrink ==================
[21:25:21] ==================== xe_bo (2 subtests) ====================
[21:25:21] ================== xe_ccs_migrate_kunit  ===================
[21:25:21] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:25:21] ==================== xe_bo_evict_kunit  ====================
[21:25:21] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:25:21] ===================== [SKIPPED] xe_bo ======================
[21:25:21] =================== xe_any (9 subtests) ====================
[21:25:21] [PASSED] test_to_xe
[21:25:21] [PASSED] test_to_dev
[21:25:21] [PASSED] test_to_pdev
[21:25:21] [PASSED] test_to_drm
[21:25:21] [PASSED] test_if_pdev
[21:25:21] [PASSED] test_if_xe
[21:25:21] [PASSED] test_if_tile
[21:25:21] [PASSED] test_if_gt
[21:25:21] [PASSED] test_to_id
[21:25:21] ===================== [PASSED] xe_any ======================
[21:25:21] ==================== args (13 subtests) ====================
[21:25:21] [PASSED] count_args_test
[21:25:21] [PASSED] call_args_example
[21:25:21] [PASSED] call_args_test
[21:25:21] [PASSED] drop_first_arg_example
[21:25:21] [PASSED] drop_first_arg_test
[21:25:21] [PASSED] first_arg_example
[21:25:21] [PASSED] first_arg_test
[21:25:21] [PASSED] last_arg_example
[21:25:21] [PASSED] last_arg_test
[21:25:21] [PASSED] pick_arg_example
[21:25:21] [PASSED] if_args_example
[21:25:21] [PASSED] if_args_test
[21:25:21] [PASSED] sep_comma_example
[21:25:21] ====================== [PASSED] args =======================
[21:25:21] =================== xe_pci (3 subtests) ====================
[21:25:21] ==================== check_graphics_ip  ====================
[21:25:21] [PASSED] 12.00 Xe_LP
[21:25:21] [PASSED] 12.10 Xe_LP+
[21:25:21] [PASSED] 12.55 Xe_HPG
[21:25:21] [PASSED] 12.60 Xe_HPC
[21:25:21] [PASSED] 12.70 Xe_LPG
[21:25:21] [PASSED] 12.71 Xe_LPG
[21:25:21] [PASSED] 12.74 Xe_LPG+
[21:25:21] [PASSED] 20.01 Xe2_HPG
[21:25:21] [PASSED] 20.02 Xe2_HPG
[21:25:21] [PASSED] 20.04 Xe2_LPG
[21:25:21] [PASSED] 30.00 Xe3_LPG
[21:25:21] [PASSED] 30.01 Xe3_LPG
[21:25:21] [PASSED] 30.03 Xe3_LPG
[21:25:21] [PASSED] 30.04 Xe3_LPG
[21:25:21] [PASSED] 30.05 Xe3_LPG
[21:25:21] [PASSED] 35.10 Xe3p_LPG
[21:25:21] [PASSED] 35.11 Xe3p_XPC
[21:25:21] ================ [PASSED] check_graphics_ip ================
[21:25:21] ===================== check_media_ip  ======================
[21:25:21] [PASSED] 12.00 Xe_M
[21:25:21] [PASSED] 12.55 Xe_HPM
[21:25:21] [PASSED] 13.00 Xe_LPM+
[21:25:21] [PASSED] 13.01 Xe2_HPM
[21:25:21] [PASSED] 20.00 Xe2_LPM
[21:25:21] [PASSED] 30.00 Xe3_LPM
[21:25:21] [PASSED] 30.02 Xe3_LPM
[21:25:21] [PASSED] 35.00 Xe3p_LPM
[21:25:21] [PASSED] 35.03 Xe3p_HPM
[21:25:21] ================= [PASSED] check_media_ip ==================
[21:25:21] =================== check_platform_desc  ===================
[21:25:21] [PASSED] 0x9A60 (TIGERLAKE)
[21:25:21] [PASSED] 0x9A68 (TIGERLAKE)
[21:25:21] [PASSED] 0x9A70 (TIGERLAKE)
[21:25:21] [PASSED] 0x9A40 (TIGERLAKE)
[21:25:21] [PASSED] 0x9A49 (TIGERLAKE)
[21:25:21] [PASSED] 0x9A59 (TIGERLAKE)
[21:25:21] [PASSED] 0x9A78 (TIGERLAKE)
[21:25:21] [PASSED] 0x9AC0 (TIGERLAKE)
[21:25:21] [PASSED] 0x9AC9 (TIGERLAKE)
[21:25:21] [PASSED] 0x9AD9 (TIGERLAKE)
[21:25:21] [PASSED] 0x9AF8 (TIGERLAKE)
[21:25:21] [PASSED] 0x4C80 (ROCKETLAKE)
[21:25:21] [PASSED] 0x4C8A (ROCKETLAKE)
[21:25:21] [PASSED] 0x4C8B (ROCKETLAKE)
[21:25:21] [PASSED] 0x4C8C (ROCKETLAKE)
[21:25:21] [PASSED] 0x4C90 (ROCKETLAKE)
[21:25:21] [PASSED] 0x4C9A (ROCKETLAKE)
[21:25:21] [PASSED] 0x4680 (ALDERLAKE_S)
[21:25:21] [PASSED] 0x4682 (ALDERLAKE_S)
[21:25:21] [PASSED] 0x4688 (ALDERLAKE_S)
[21:25:21] [PASSED] 0x468A (ALDERLAKE_S)
[21:25:21] [PASSED] 0x468B (ALDERLAKE_S)
[21:25:21] [PASSED] 0x4690 (ALDERLAKE_S)
[21:25:21] [PASSED] 0x4692 (ALDERLAKE_S)
[21:25:21] [PASSED] 0x4693 (ALDERLAKE_S)
[21:25:21] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46AA (ALDERLAKE_P)
[21:25:21] [PASSED] 0x462A (ALDERLAKE_P)
[21:25:21] [PASSED] 0x4626 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x4628 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:25:21] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:25:21] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:25:21] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:25:21] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:25:21] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:25:21] [PASSED] 0xA721 (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA720 (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:25:21] [PASSED] 0xA780 (ALDERLAKE_S)
[21:25:21] [PASSED] 0xA781 (ALDERLAKE_S)
[21:25:21] [PASSED] 0xA782 (ALDERLAKE_S)
[21:25:21] [PASSED] 0xA783 (ALDERLAKE_S)
[21:25:21] [PASSED] 0xA788 (ALDERLAKE_S)
[21:25:21] [PASSED] 0xA789 (ALDERLAKE_S)
[21:25:21] [PASSED] 0xA78A (ALDERLAKE_S)
[21:25:21] [PASSED] 0xA78B (ALDERLAKE_S)
[21:25:21] [PASSED] 0x4905 (DG1)
[21:25:21] [PASSED] 0x4906 (DG1)
[21:25:21] [PASSED] 0x4907 (DG1)
[21:25:21] [PASSED] 0x4908 (DG1)
[21:25:21] [PASSED] 0x4909 (DG1)
[21:25:21] [PASSED] 0x56C0 (DG2)
[21:25:21] [PASSED] 0x56C2 (DG2)
[21:25:21] [PASSED] 0x56C1 (DG2)
[21:25:21] [PASSED] 0x7D51 (METEORLAKE)
[21:25:21] [PASSED] 0x7DD1 (METEORLAKE)
[21:25:21] [PASSED] 0x7D41 (METEORLAKE)
[21:25:21] [PASSED] 0x7D67 (METEORLAKE)
[21:25:21] [PASSED] 0xB640 (METEORLAKE)
[21:25:21] [PASSED] 0x56A0 (DG2)
[21:25:21] [PASSED] 0x56A1 (DG2)
[21:25:21] [PASSED] 0x56A2 (DG2)
[21:25:21] [PASSED] 0x56BE (DG2)
[21:25:21] [PASSED] 0x56BF (DG2)
[21:25:21] [PASSED] 0x5690 (DG2)
[21:25:21] [PASSED] 0x5691 (DG2)
[21:25:21] [PASSED] 0x5692 (DG2)
[21:25:21] [PASSED] 0x56A5 (DG2)
[21:25:21] [PASSED] 0x56A6 (DG2)
[21:25:21] [PASSED] 0x56B0 (DG2)
[21:25:21] [PASSED] 0x56B1 (DG2)
[21:25:21] [PASSED] 0x56BA (DG2)
[21:25:21] [PASSED] 0x56BB (DG2)
[21:25:21] [PASSED] 0x56BC (DG2)
[21:25:21] [PASSED] 0x56BD (DG2)
[21:25:21] [PASSED] 0x5693 (DG2)
[21:25:21] [PASSED] 0x5694 (DG2)
[21:25:21] [PASSED] 0x5695 (DG2)
[21:25:21] [PASSED] 0x56A3 (DG2)
[21:25:21] [PASSED] 0x56A4 (DG2)
[21:25:21] [PASSED] 0x56B2 (DG2)
[21:25:21] [PASSED] 0x56B3 (DG2)
[21:25:21] [PASSED] 0x5696 (DG2)
[21:25:21] [PASSED] 0x5697 (DG2)
[21:25:21] [PASSED] 0xB69 (PVC)
[21:25:21] [PASSED] 0xB6E (PVC)
[21:25:21] [PASSED] 0xBD4 (PVC)
[21:25:21] [PASSED] 0xBD5 (PVC)
[21:25:21] [PASSED] 0xBD6 (PVC)
[21:25:21] [PASSED] 0xBD7 (PVC)
[21:25:21] [PASSED] 0xBD8 (PVC)
[21:25:21] [PASSED] 0xBD9 (PVC)
[21:25:21] [PASSED] 0xBDA (PVC)
[21:25:21] [PASSED] 0xBDB (PVC)
[21:25:21] [PASSED] 0xBE0 (PVC)
[21:25:21] [PASSED] 0xBE1 (PVC)
[21:25:21] [PASSED] 0xBE5 (PVC)
[21:25:21] [PASSED] 0x7D40 (METEORLAKE)
[21:25:21] [PASSED] 0x7D45 (METEORLAKE)
[21:25:21] [PASSED] 0x7D55 (METEORLAKE)
[21:25:21] [PASSED] 0x7D60 (METEORLAKE)
[21:25:21] [PASSED] 0x7DD5 (METEORLAKE)
[21:25:21] [PASSED] 0x6420 (LUNARLAKE)
[21:25:21] [PASSED] 0x64A0 (LUNARLAKE)
[21:25:21] [PASSED] 0x64B0 (LUNARLAKE)
[21:25:21] [PASSED] 0xE202 (BATTLEMAGE)
[21:25:21] [PASSED] 0xE209 (BATTLEMAGE)
[21:25:21] [PASSED] 0xE20B (BATTLEMAGE)
[21:25:21] [PASSED] 0xE20C (BATTLEMAGE)
[21:25:21] [PASSED] 0xE20D (BATTLEMAGE)
[21:25:21] [PASSED] 0xE210 (BATTLEMAGE)
[21:25:21] [PASSED] 0xE211 (BATTLEMAGE)
[21:25:21] [PASSED] 0xE212 (BATTLEMAGE)
[21:25:21] [PASSED] 0xE216 (BATTLEMAGE)
[21:25:21] [PASSED] 0xE220 (BATTLEMAGE)
[21:25:21] [PASSED] 0xE221 (BATTLEMAGE)
[21:25:21] [PASSED] 0xE222 (BATTLEMAGE)
[21:25:21] [PASSED] 0xE223 (BATTLEMAGE)
[21:25:21] [PASSED] 0xB080 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB081 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB082 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB083 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB084 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB085 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB086 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB087 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB08F (PANTHERLAKE)
[21:25:21] [PASSED] 0xB090 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:25:21] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:25:21] [PASSED] 0xFD80 (PANTHERLAKE)
[21:25:21] [PASSED] 0xFD81 (PANTHERLAKE)
[21:25:21] [PASSED] 0xD740 (NOVALAKE_S)
[21:25:21] [PASSED] 0xD741 (NOVALAKE_S)
[21:25:21] [PASSED] 0xD742 (NOVALAKE_S)
[21:25:21] [PASSED] 0xD743 (NOVALAKE_S)
[21:25:21] [PASSED] 0xD745 (NOVALAKE_S)
[21:25:21] [PASSED] 0xD74A (NOVALAKE_S)
[21:25:21] [PASSED] 0xD74B (NOVALAKE_S)
[21:25:21] [PASSED] 0x674C (CRESCENTISLAND)
[21:25:21] [PASSED] 0x674D (CRESCENTISLAND)
[21:25:21] [PASSED] 0x674E (CRESCENTISLAND)
[21:25:21] [PASSED] 0x674F (CRESCENTISLAND)
[21:25:21] [PASSED] 0x6750 (CRESCENTISLAND)
[21:25:21] [PASSED] 0xD750 (NOVALAKE_P)
[21:25:21] [PASSED] 0xD751 (NOVALAKE_P)
[21:25:21] [PASSED] 0xD752 (NOVALAKE_P)
[21:25:21] [PASSED] 0xD753 (NOVALAKE_P)
[21:25:21] [PASSED] 0xD754 (NOVALAKE_P)
[21:25:21] [PASSED] 0xD755 (NOVALAKE_P)
[21:25:21] [PASSED] 0xD756 (NOVALAKE_P)
[21:25:21] [PASSED] 0xD757 (NOVALAKE_P)
[21:25:21] [PASSED] 0xD75F (NOVALAKE_P)
[21:25:21] =============== [PASSED] check_platform_desc ===============
[21:25:21] ===================== [PASSED] xe_pci ======================
[21:25:21] ============= xe_rtp_tables_test (5 subtests) ==============
[21:25:21] ================== xe_rtp_table_gt_test  ===================
[21:25:21] [PASSED] gt_was/14011060649
[21:25:21] [PASSED] gt_was/14011059788
[21:25:21] [PASSED] gt_was/14015795083
[21:25:21] [PASSED] gt_was/16021867713
[21:25:21] [PASSED] gt_was/14019449301
[21:25:21] [PASSED] gt_was/16028005424
[21:25:21] [PASSED] gt_was/14026578760
[21:25:21] [PASSED] gt_was/1409420604
[21:25:21] [PASSED] gt_was/1408615072
[21:25:21] [PASSED] gt_was/22010523718
[21:25:21] [PASSED] gt_was/14011006942
[21:25:21] [PASSED] gt_was/14014830051
[21:25:21] [PASSED] gt_was/18018781329
[21:25:21] [PASSED] gt_was/1509235366
[21:25:21] [PASSED] gt_was/18018781329
[21:25:21] [PASSED] gt_was/16016694945
[21:25:21] [PASSED] gt_was/14018575942
[21:25:21] [PASSED] gt_was/22016670082
[21:25:21] [PASSED] gt_was/22016670082
[21:25:21] [PASSED] gt_was/14017421178
[21:25:21] [PASSED] gt_was/16025250150
[21:25:21] [PASSED] gt_was/14021871409
[21:25:21] [PASSED] gt_was/16021865536
[21:25:21] [PASSED] gt_was/14021486841
[21:25:21] [PASSED] gt_was/14025160223
[21:25:21] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[21:25:21] [PASSED] gt_was/14025635424
[21:25:21] [PASSED] gt_was/16028005424
[21:25:21] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:25:21] ================== xe_rtp_table_gt_test  ===================
[21:25:21] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[21:25:21] [PASSED] gt_tunings/Tuning: 32B Access Enable
[21:25:21] [PASSED] gt_tunings/Tuning: L3 cache
[21:25:21] [PASSED] gt_tunings/Tuning: L3 cache - media
[21:25:21] [PASSED] gt_tunings/Tuning: Compression Overfetch
[21:25:21] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[21:25:21] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[21:25:21] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[21:25:21] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[21:25:21] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[21:25:21] [PASSED] gt_tunings/Tuning: Stateless compression control
[21:25:21] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[21:25:21] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[21:25:21] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[21:25:21] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[21:25:21] ============== [PASSED] xe_rtp_table_gt_test ===============
[21:25:21] ================== xe_rtp_table_oob_test  ==================
[21:25:21] [PASSED] oob_was/1607983814
[21:25:21] [PASSED] oob_was/16010904313
[21:25:21] [PASSED] oob_was/18022495364
[21:25:21] [PASSED] oob_was/22012773006
[21:25:21] [PASSED] oob_was/14014475959
[21:25:21] [PASSED] oob_was/22011391025
[21:25:21] [PASSED] oob_was/22012727170
[21:25:21] [PASSED] oob_was/22012727685
[21:25:21] [PASSED] oob_was/22016596838
[21:25:21] [PASSED] oob_was/18020744125
[21:25:21] [PASSED] oob_was/1409600907
[21:25:21] [PASSED] oob_was/22014953428
[21:25:21] [PASSED] oob_was/16017236439
[21:25:21] [PASSED] oob_was/14019821291
[21:25:21] [PASSED] oob_was/14015076503
[21:25:21] [PASSED] oob_was/14018913170
[21:25:21] [PASSED] oob_was/14018094691
[21:25:21] [PASSED] oob_was/18024947630
[21:25:21] [PASSED] oob_was/16022287689
[21:25:21] [PASSED] oob_was/13011645652
[21:25:21] [PASSED] oob_was/14022293748
[21:25:21] [PASSED] oob_was/22019794406
[21:25:21] [PASSED] oob_was/22019338487
[21:25:21] [PASSED] oob_was/16023588340
[21:25:21] [PASSED] oob_was/14019789679
[21:25:21] [PASSED] oob_was/14022866841
[21:25:21] [PASSED] oob_was/16021333562
[21:25:21] [PASSED] oob_was/14016712196
[21:25:21] [PASSED] oob_was/14015568240
[21:25:21] [PASSED] oob_was/18013179988
[21:25:21] [PASSED] oob_was/1508761755
[21:25:21] [PASSED] oob_was/16023105232
[21:25:21] [PASSED] oob_was/16026508708
[21:25:21] [PASSED] oob_was/14020001231
[21:25:21] [PASSED] oob_was/16023683509
[21:25:21] [PASSED] oob_was/14025515070
[21:25:21] [PASSED] oob_was/15015404425_disable
[21:25:21] [PASSED] oob_was/16026007364
[21:25:21] [PASSED] oob_was/14020316580
[21:25:21] [PASSED] oob_was/14025883347
[21:25:21] [PASSED] oob_was/16029380221
[21:25:21] [PASSED] oob_was/22022079272
[21:25:21] [PASSED] oob_was/16029897822
[21:25:21] [PASSED] oob_was/14027054324
[21:25:21] ============== [PASSED] xe_rtp_table_oob_test ==============
[21:25:21] ================ xe_rtp_table_dev_oob_test  ================
[21:25:21] [PASSED] device_oob_was/22010954014
[21:25:21] [PASSED] device_oob_was/15015404425
[21:25:21] [PASSED] device_oob_was/22019338487_display
[21:25:21] [PASSED] device_oob_was/14022085890
[21:25:21] [PASSED] device_oob_was/14026539277
[21:25:21] [PASSED] device_oob_was/14026633728
[21:25:21] [PASSED] device_oob_was/14026746987
[21:25:21] [PASSED] device_oob_was/14026779378
[21:25:21] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[21:25:21] ========== xe_rtp_table_missing_upper_bound_test  ==========
[21:25:21] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[21:25:21] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[21:25:21] [PASSED] register_whitelist/1806527549
[21:25:21] [PASSED] register_whitelist/allow_read_ctx_timestamp
[21:25:21] [PASSED] register_whitelist/allow_read_queue_timestamp
[21:25:21] [PASSED] register_whitelist/16014440446
[21:25:21] [PASSED] register_whitelist/16017236439
[21:25:21] [PASSED] register_whitelist/16020183090
[21:25:21] [PASSED] register_whitelist/14024997852
[21:25:21] [PASSED] register_whitelist/14024997852
[21:25:21] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[21:25:21] =============== [PASSED] xe_rtp_tables_test ================
[21:25:21] =================== xe_rtp (3 subtests) ====================
[21:25:21] =================== xe_rtp_rules_tests  ====================
[21:25:21] [PASSED] no
[21:25:21] [PASSED] yes
[21:25:21] [PASSED] no-and-no
[21:25:21] [PASSED] no-and-yes
[21:25:21] [PASSED] yes-and-no
[21:25:21] [PASSED] yes-and-yes
[21:25:21] [PASSED] no-or-no
[21:25:21] [PASSED] no-or-yes
[21:25:21] [PASSED] yes-or-no
[21:25:21] [PASSED] yes-or-yes
[21:25:21] [PASSED] no-yes-or-yes-no
[21:25:21] [PASSED] no-yes-or-yes-yes
[21:25:21] [PASSED] yes-yes-or-no-yes
[21:25:21] [PASSED] yes-yes-or-yes-yes
[21:25:21] [PASSED] no-no-or-yes-or-no
[21:25:21] [PASSED] or
[21:25:21] [PASSED] or-yes
[21:25:21] [PASSED] or-no
[21:25:21] [PASSED] yes-or
[21:25:21] [PASSED] no-or
[21:25:21] [PASSED] no-or-or-yes
[21:25:21] [PASSED] yes-or-or-no
[21:25:21] [PASSED] no-or-or-no
[21:25:21] [PASSED] missing-context-engine-class
[21:25:21] [PASSED] missing-context-engine-class-or-yes
[21:25:21] [PASSED] missing-context-engine-class-or-or-yes
[21:25:21] =============== [PASSED] xe_rtp_rules_tests ================
[21:25:21] =============== xe_rtp_process_to_sr_tests  ================
[21:25:21] [PASSED] coalesce-same-reg
[21:25:21] [PASSED] coalesce-same-reg-literal-and-func
[21:25:21] [PASSED] no-match-no-add
[21:25:21] [PASSED] two-regs-two-entries
[21:25:21] [PASSED] clr-one-set-other
[21:25:21] [PASSED] set-field
[21:25:21] [PASSED] conflict-duplicate
[21:25:21] [PASSED] conflict-not-disjoint
[21:25:21] [PASSED] conflict-not-disjoint-literal-and-func
[21:25:21] [PASSED] conflict-reg-type
[21:25:21] [PASSED] bad-mcr-reg-forced-to-regular
[21:25:21] [PASSED] bad-regular-reg-forced-to-mcr
[21:25:21] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:25:21] ================== xe_rtp_process_tests  ===================
[21:25:21] [PASSED] active1
[21:25:21] [PASSED] active2
[21:25:21] [PASSED] active-inactive
[21:25:21] [PASSED] inactive-active
[21:25:21] [PASSED] inactive-active-inactive
[21:25:21] [PASSED] inactive-inactive-inactive
[21:25:21] ============== [PASSED] xe_rtp_process_tests ===============
[21:25:21] ===================== [PASSED] xe_rtp ======================
[21:25:21] ==================== xe_wa (1 subtest) =====================
[21:25:21] ======================== xe_wa_gt  =========================
[21:25:21] [PASSED] TIGERLAKE B0
[21:25:21] [PASSED] DG1 A0
[21:25:21] [PASSED] DG1 B0
[21:25:21] [PASSED] ALDERLAKE_S A0
[21:25:21] [PASSED] ALDERLAKE_S B0
[21:25:21] [PASSED] ALDERLAKE_S C0
[21:25:21] [PASSED] ALDERLAKE_S D0
[21:25:21] [PASSED] ALDERLAKE_P A0
[21:25:21] [PASSED] ALDERLAKE_P B0
[21:25:21] [PASSED] ALDERLAKE_P C0
[21:25:21] [PASSED] ALDERLAKE_S RPLS D0
[21:25:21] [PASSED] ALDERLAKE_P RPLU E0
[21:25:21] [PASSED] DG2 G10 C0
[21:25:21] [PASSED] DG2 G11 B1
[21:25:21] [PASSED] DG2 G12 A1
[21:25:21] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:25:21] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:25:21] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:25:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:25:21] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:25:21] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:25:21] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:25:21] ==================== [PASSED] xe_wa_gt =====================
[21:25:21] ====================== [PASSED] xe_wa ======================
[21:25:21] ============================================================
[21:25:21] Testing complete. Ran 793 tests: passed: 765, skipped: 28
[21:25:21] Elapsed time: 36.643s total, 1.737s configuring, 34.190s building, 0.695s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:25:21] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:25:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:25:48] Starting KUnit Kernel (1/1)...
[21:25:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:25:49] ============= refcount_interrupt (4 subtests) ==============
[21:25:49] [PASSED] test_single_irq_change
[21:25:49] [PASSED] test_nested_irq_change
[21:25:49] [PASSED] test_multiple_irq_change
[21:25:49] [PASSED] test_irq_save
[21:25:49] =============== [PASSED] refcount_interrupt ================
[21:25:49] ============ drm_test_pick_cmdline (2 subtests) ============
[21:25:49] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:25:49] =============== drm_test_pick_cmdline_named  ===============
[21:25:49] [PASSED] NTSC
[21:25:49] [PASSED] NTSC-J
[21:25:49] [PASSED] PAL
[21:25:49] [PASSED] PAL-M
[21:25:49] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:25:49] ============== [PASSED] drm_test_pick_cmdline ==============
[21:25:49] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:25:49] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:25:49] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:25:49] =========== drm_validate_clone_mode (2 subtests) ===========
[21:25:49] ============== drm_test_check_in_clone_mode  ===============
[21:25:49] [PASSED] in_clone_mode
[21:25:49] [PASSED] not_in_clone_mode
[21:25:49] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:25:49] =============== drm_test_check_valid_clones  ===============
[21:25:49] [PASSED] not_in_clone_mode
[21:25:49] [PASSED] valid_clone
[21:25:49] [PASSED] invalid_clone
[21:25:49] =========== [PASSED] drm_test_check_valid_clones ===========
[21:25:49] ============= [PASSED] drm_validate_clone_mode =============
[21:25:49] ============= drm_validate_modeset (1 subtest) =============
[21:25:49] [PASSED] drm_test_check_connector_changed_modeset
[21:25:49] ============== [PASSED] drm_validate_modeset ===============
[21:25:49] ====== drm_test_bridge_get_current_state (1 subtest) =======
[21:25:49] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:25:49] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:25:49] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:25:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:25:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:25:49] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[21:25:49] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:25:49] ============== drm_bridge_alloc (2 subtests) ===============
[21:25:49] [PASSED] drm_test_drm_bridge_alloc_basic
[21:25:49] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:25:49] ================ [PASSED] drm_bridge_alloc =================
[21:25:49] ============= drm_bridge_bus_fmt (5 subtests) ==============
[21:25:49] [PASSED] drm_test_bridge_rgb_yuv_rgb
[21:25:49] [PASSED] drm_test_bridge_must_convert_to_yuv444
[21:25:49] [PASSED] drm_test_bridge_hdmi_auto_rgb
[21:25:49] [PASSED] drm_test_bridge_auto_first
[21:25:49] [PASSED] drm_test_bridge_rgb_yuv_no_path
[21:25:49] =============== [PASSED] drm_bridge_bus_fmt ================
[21:25:49] ============= drm_cmdline_parser (40 subtests) =============
[21:25:49] [PASSED] drm_test_cmdline_force_d_only
[21:25:49] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:25:49] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:25:49] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:25:49] [PASSED] drm_test_cmdline_force_e_only
[21:25:49] [PASSED] drm_test_cmdline_res
[21:25:49] [PASSED] drm_test_cmdline_res_vesa
[21:25:49] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:25:49] [PASSED] drm_test_cmdline_res_rblank
[21:25:49] [PASSED] drm_test_cmdline_res_bpp
[21:25:49] [PASSED] drm_test_cmdline_res_refresh
[21:25:49] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:25:49] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:25:49] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:25:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:25:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:25:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:25:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:25:49] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:25:49] [PASSED] drm_test_cmdline_res_margins_force_on
[21:25:49] [PASSED] drm_test_cmdline_res_vesa_margins
[21:25:49] [PASSED] drm_test_cmdline_name
[21:25:49] [PASSED] drm_test_cmdline_name_bpp
[21:25:49] [PASSED] drm_test_cmdline_name_option
[21:25:49] [PASSED] drm_test_cmdline_name_bpp_option
[21:25:49] [PASSED] drm_test_cmdline_rotate_0
[21:25:49] [PASSED] drm_test_cmdline_rotate_90
[21:25:49] [PASSED] drm_test_cmdline_rotate_180
[21:25:49] [PASSED] drm_test_cmdline_rotate_270
[21:25:49] [PASSED] drm_test_cmdline_hmirror
[21:25:49] [PASSED] drm_test_cmdline_vmirror
[21:25:49] [PASSED] drm_test_cmdline_margin_options
[21:25:49] [PASSED] drm_test_cmdline_multiple_options
[21:25:49] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:25:49] [PASSED] drm_test_cmdline_extra_and_option
[21:25:49] [PASSED] drm_test_cmdline_freestanding_options
[21:25:49] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:25:49] [PASSED] drm_test_cmdline_panel_orientation
[21:25:49] ================ drm_test_cmdline_invalid  =================
[21:25:49] [PASSED] margin_only
[21:25:49] [PASSED] interlace_only
[21:25:49] [PASSED] res_missing_x
[21:25:49] [PASSED] res_missing_y
[21:25:49] [PASSED] res_bad_y
[21:25:49] [PASSED] res_missing_y_bpp
[21:25:49] [PASSED] res_bad_bpp
[21:25:49] [PASSED] res_bad_refresh
[21:25:49] [PASSED] res_bpp_refresh_force_on_off
[21:25:49] [PASSED] res_invalid_mode
[21:25:49] [PASSED] res_bpp_wrong_place_mode
[21:25:49] [PASSED] name_bpp_refresh
[21:25:49] [PASSED] name_refresh
[21:25:49] [PASSED] name_refresh_wrong_mode
[21:25:49] [PASSED] name_refresh_invalid_mode
[21:25:49] [PASSED] rotate_multiple
[21:25:49] [PASSED] rotate_invalid_val
[21:25:49] [PASSED] rotate_truncated
[21:25:49] [PASSED] invalid_option
[21:25:49] [PASSED] invalid_tv_option
[21:25:49] [PASSED] truncated_tv_option
[21:25:49] ============ [PASSED] drm_test_cmdline_invalid =============
[21:25:49] =============== drm_test_cmdline_tv_options  ===============
[21:25:49] [PASSED] NTSC
[21:25:49] [PASSED] NTSC_443
[21:25:49] [PASSED] NTSC_J
[21:25:49] [PASSED] PAL
[21:25:49] [PASSED] PAL_M
[21:25:49] [PASSED] PAL_N
[21:25:49] [PASSED] SECAM
[21:25:49] [PASSED] MONO_525
[21:25:49] [PASSED] MONO_625
[21:25:49] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:25:49] =============== [PASSED] drm_cmdline_parser ================
[21:25:49] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:25:49] [PASSED] drm_test_connector_hdmi_init_valid
[21:25:49] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:25:49] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:25:49] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:25:49] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:25:49] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:25:49] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:25:49] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:25:49] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:25:49] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:25:49] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:25:49] [PASSED] supported_formats=0x5 yuv420_allowed=1
[21:25:49] [PASSED] supported_formats=0x5 yuv420_allowed=0
[21:25:49] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:25:49] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:25:49] [PASSED] drm_test_connector_hdmi_init_null_product
[21:25:49] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:25:49] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:25:49] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:25:49] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:25:49] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:25:49] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:25:49] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:25:49] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:25:49] [PASSED] HDMI-A
[21:25:49] [PASSED] HDMI-B
[21:25:49] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:25:49] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:25:49] [PASSED] Unknown
[21:25:49] [PASSED] VGA
[21:25:49] [PASSED] DVI-I
[21:25:49] [PASSED] DVI-D
[21:25:49] [PASSED] DVI-A
[21:25:49] [PASSED] Composite
[21:25:49] [PASSED] SVIDEO
[21:25:49] [PASSED] LVDS
[21:25:49] [PASSED] Component
[21:25:49] [PASSED] DIN
[21:25:49] [PASSED] DP
[21:25:49] [PASSED] TV
[21:25:49] [PASSED] eDP
[21:25:49] [PASSED] Virtual
[21:25:49] [PASSED] DSI
[21:25:49] [PASSED] DPI
[21:25:49] [PASSED] Writeback
[21:25:49] [PASSED] SPI
[21:25:49] [PASSED] USB
[21:25:49] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:25:49] ============ [PASSED] drmm_connector_hdmi_init =============
[21:25:49] ============= drmm_connector_init (3 subtests) =============
[21:25:49] [PASSED] drm_test_drmm_connector_init
[21:25:49] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:25:49] ========= drm_test_drmm_connector_init_type_valid  =========
[21:25:49] [PASSED] Unknown
[21:25:49] [PASSED] VGA
[21:25:49] [PASSED] DVI-I
[21:25:49] [PASSED] DVI-D
[21:25:49] [PASSED] DVI-A
[21:25:49] [PASSED] Composite
[21:25:49] [PASSED] SVIDEO
[21:25:49] [PASSED] LVDS
[21:25:49] [PASSED] Component
[21:25:49] [PASSED] DIN
[21:25:49] [PASSED] DP
[21:25:49] [PASSED] HDMI-A
[21:25:49] [PASSED] HDMI-B
[21:25:49] [PASSED] TV
[21:25:49] [PASSED] eDP
[21:25:49] [PASSED] Virtual
[21:25:49] [PASSED] DSI
[21:25:49] [PASSED] DPI
[21:25:49] [PASSED] Writeback
[21:25:49] [PASSED] SPI
[21:25:49] [PASSED] USB
[21:25:49] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:25:49] =============== [PASSED] drmm_connector_init ===============
[21:25:49] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_init
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:25:49] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:25:49] [PASSED] Unknown
[21:25:49] [PASSED] VGA
[21:25:49] [PASSED] DVI-I
[21:25:49] [PASSED] DVI-D
[21:25:49] [PASSED] DVI-A
[21:25:49] [PASSED] Composite
[21:25:49] [PASSED] SVIDEO
[21:25:49] [PASSED] LVDS
[21:25:49] [PASSED] Component
[21:25:49] [PASSED] DIN
[21:25:49] [PASSED] DP
[21:25:49] [PASSED] HDMI-A
[21:25:49] [PASSED] HDMI-B
[21:25:49] [PASSED] TV
[21:25:49] [PASSED] eDP
[21:25:49] [PASSED] Virtual
[21:25:49] [PASSED] DSI
[21:25:49] [PASSED] DPI
[21:25:49] [PASSED] Writeback
[21:25:49] [PASSED] SPI
[21:25:49] [PASSED] USB
[21:25:49] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:25:49] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:25:49] [PASSED] Unknown
[21:25:49] [PASSED] VGA
[21:25:49] [PASSED] DVI-I
[21:25:49] [PASSED] DVI-D
[21:25:49] [PASSED] DVI-A
[21:25:49] [PASSED] Composite
[21:25:49] [PASSED] SVIDEO
[21:25:49] [PASSED] LVDS
[21:25:49] [PASSED] Component
[21:25:49] [PASSED] DIN
[21:25:49] [PASSED] DP
[21:25:49] [PASSED] HDMI-A
[21:25:49] [PASSED] HDMI-B
[21:25:49] [PASSED] TV
[21:25:49] [PASSED] eDP
[21:25:49] [PASSED] Virtual
[21:25:49] [PASSED] DSI
[21:25:49] [PASSED] DPI
[21:25:49] [PASSED] Writeback
[21:25:49] [PASSED] SPI
[21:25:49] [PASSED] USB
[21:25:49] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:25:49] =========== [PASSED] drm_connector_dynamic_init ============
[21:25:49] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:25:49] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:25:49] ======= drm_connector_dynamic_register (7 subtests) ========
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:25:49] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:25:49] ========= [PASSED] drm_connector_dynamic_register ==========
[21:25:49] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:25:49] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:25:49] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:25:49] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:25:49] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:25:49] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:25:49] [PASSED] NTSC
[21:25:49] [PASSED] NTSC-443
[21:25:49] [PASSED] NTSC-J
[21:25:49] [PASSED] PAL
[21:25:49] [PASSED] PAL-M
[21:25:49] [PASSED] PAL-N
[21:25:49] [PASSED] SECAM
[21:25:49] [PASSED] Mono
[21:25:49] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:25:49] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:25:49] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:25:49] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:25:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:25:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:25:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:25:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:25:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:25:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:25:49] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:25:49] [PASSED] VIC 96
[21:25:49] [PASSED] VIC 97
[21:25:49] [PASSED] VIC 101
[21:25:49] [PASSED] VIC 102
[21:25:49] [PASSED] VIC 106
[21:25:49] [PASSED] VIC 107
[21:25:49] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:25:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:25:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:25:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:25:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:25:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:25:49] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:25:49] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:25:49] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:25:49] [PASSED] Automatic
[21:25:49] [PASSED] Full
[21:25:49] [PASSED] Limited 16:235
[21:25:49] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:25:49] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:25:49] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:25:49] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:25:49] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:25:49] [PASSED] RGB
[21:25:49] [PASSED] YUV 4:2:0
[21:25:49] [PASSED] YUV 4:2:2
[21:25:49] [PASSED] YUV 4:4:4
[21:25:49] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:25:49] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:25:49] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:25:49] ============= drm_damage_helper (21 subtests) ==============
[21:25:49] [PASSED] drm_test_damage_iter_no_damage
[21:25:49] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:25:49] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:25:49] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:25:49] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:25:49] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:25:49] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:25:49] [PASSED] drm_test_damage_iter_simple_damage
[21:25:49] [PASSED] drm_test_damage_iter_single_damage
[21:25:49] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:25:49] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:25:49] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:25:49] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:25:49] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:25:49] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:25:49] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:25:49] [PASSED] drm_test_damage_iter_damage
[21:25:49] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:25:49] [PASSED] drm_test_damage_iter_damage_one_outside
[21:25:49] [PASSED] drm_test_damage_iter_damage_src_moved
[21:25:49] [PASSED] drm_test_damage_iter_damage_not_visible
[21:25:49] ================ [PASSED] drm_damage_helper ================
[21:25:49] ============== drm_dp_mst_helper (3 subtests) ==============
[21:25:49] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:25:49] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:25:49] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:25:49] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:25:49] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:25:49] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:25:49] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:25:49] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:25:49] [PASSED] Link rate 2000000 lane count 4
[21:25:49] [PASSED] Link rate 2000000 lane count 2
[21:25:49] [PASSED] Link rate 2000000 lane count 1
[21:25:49] [PASSED] Link rate 1350000 lane count 4
[21:25:49] [PASSED] Link rate 1350000 lane count 2
[21:25:49] [PASSED] Link rate 1350000 lane count 1
[21:25:49] [PASSED] Link rate 1000000 lane count 4
[21:25:49] [PASSED] Link rate 1000000 lane count 2
[21:25:49] [PASSED] Link rate 1000000 lane count 1
[21:25:49] [PASSED] Link rate 810000 lane count 4
[21:25:49] [PASSED] Link rate 810000 lane count 2
[21:25:49] [PASSED] Link rate 810000 lane count 1
[21:25:49] [PASSED] Link rate 540000 lane count 4
[21:25:49] [PASSED] Link rate 540000 lane count 2
[21:25:49] [PASSED] Link rate 540000 lane count 1
[21:25:49] [PASSED] Link rate 270000 lane count 4
[21:25:49] [PASSED] Link rate 270000 lane count 2
[21:25:49] [PASSED] Link rate 270000 lane count 1
[21:25:49] [PASSED] Link rate 162000 lane count 4
[21:25:49] [PASSED] Link rate 162000 lane count 2
[21:25:49] [PASSED] Link rate 162000 lane count 1
[21:25:49] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:25:49] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:25:49] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:25:49] [PASSED] DP_POWER_UP_PHY with port number
[21:25:49] [PASSED] DP_POWER_DOWN_PHY with port number
[21:25:49] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:25:49] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:25:49] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:25:49] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:25:49] [PASSED] DP_QUERY_PAYLOAD with port number
[21:25:49] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:25:49] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:25:49] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:25:49] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:25:49] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:25:49] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:25:49] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:25:49] [PASSED] DP_REMOTE_I2C_READ with port number
[21:25:49] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:25:49] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:25:49] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:25:49] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:25:49] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:25:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:25:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:25:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:25:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:25:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:25:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:25:49] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:25:49] ================ [PASSED] drm_dp_mst_helper ================
[21:25:49] ================== drm_exec (7 subtests) ===================
[21:25:49] [PASSED] sanitycheck
[21:25:49] [PASSED] test_lock
[21:25:49] [PASSED] test_lock_unlock
[21:25:49] [PASSED] test_duplicates
[21:25:49] [PASSED] test_prepare
[21:25:49] [PASSED] test_prepare_array
[21:25:49] [PASSED] test_multiple_loops
[21:25:49] ==================== [PASSED] drm_exec =====================
[21:25:49] =========== drm_format_helper_test (17 subtests) ===========
[21:25:49] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:25:49] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:25:49] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:25:49] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:25:49] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:25:49] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:25:49] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:25:49] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:25:49] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:25:49] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:25:49] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:25:49] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:25:49] ==================== drm_test_fb_swab  =====================
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ================ [PASSED] drm_test_fb_swab =================
[21:25:49] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:25:49] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:25:49] [PASSED] single_pixel_source_buffer
[21:25:49] [PASSED] single_pixel_clip_rectangle
[21:25:49] [PASSED] well_known_colors
[21:25:49] [PASSED] destination_pitch
[21:25:49] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:25:49] ================= drm_test_fb_clip_offset  =================
[21:25:49] [PASSED] pass through
[21:25:49] [PASSED] horizontal offset
[21:25:49] [PASSED] vertical offset
[21:25:49] [PASSED] horizontal and vertical offset
[21:25:49] [PASSED] horizontal offset (custom pitch)
[21:25:49] [PASSED] vertical offset (custom pitch)
[21:25:49] [PASSED] horizontal and vertical offset (custom pitch)
[21:25:49] ============= [PASSED] drm_test_fb_clip_offset =============
[21:25:49] =================== drm_test_fb_memcpy  ====================
[21:25:49] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:25:49] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:25:49] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:25:49] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:25:49] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:25:49] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:25:49] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:25:49] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:25:49] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:25:49] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:25:49] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:25:49] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:25:49] =============== [PASSED] drm_test_fb_memcpy ================
[21:25:49] ============= [PASSED] drm_format_helper_test ==============
[21:25:49] ================= drm_format (18 subtests) =================
[21:25:49] [PASSED] drm_test_format_block_width_invalid
[21:25:49] [PASSED] drm_test_format_block_width_one_plane
[21:25:49] [PASSED] drm_test_format_block_width_two_plane
[21:25:49] [PASSED] drm_test_format_block_width_three_plane
[21:25:49] [PASSED] drm_test_format_block_width_tiled
[21:25:49] [PASSED] drm_test_format_block_height_invalid
[21:25:49] [PASSED] drm_test_format_block_height_one_plane
[21:25:49] [PASSED] drm_test_format_block_height_two_plane
[21:25:49] [PASSED] drm_test_format_block_height_three_plane
[21:25:49] [PASSED] drm_test_format_block_height_tiled
[21:25:49] [PASSED] drm_test_format_min_pitch_invalid
[21:25:49] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:25:49] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:25:49] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:25:49] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:25:49] [PASSED] drm_test_format_min_pitch_two_plane
[21:25:49] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:25:49] [PASSED] drm_test_format_min_pitch_tiled
[21:25:49] =================== [PASSED] drm_format ====================
[21:25:49] ============== drm_framebuffer (10 subtests) ===============
[21:25:49] ========== drm_test_framebuffer_check_src_coords  ==========
[21:25:49] [PASSED] Success: source fits into fb
[21:25:49] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:25:49] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:25:49] [PASSED] Fail: overflowing fb with source width
[21:25:49] [PASSED] Fail: overflowing fb with source height
[21:25:49] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:25:49] [PASSED] drm_test_framebuffer_cleanup
[21:25:49] =============== drm_test_framebuffer_create  ===============
[21:25:49] [PASSED] ABGR8888 normal sizes
[21:25:49] [PASSED] ABGR8888 max sizes
[21:25:49] [PASSED] ABGR8888 pitch greater than min required
[21:25:49] [PASSED] ABGR8888 pitch less than min required
[21:25:49] [PASSED] ABGR8888 Invalid width
[21:25:49] [PASSED] ABGR8888 Invalid buffer handle
[21:25:49] [PASSED] No pixel format
[21:25:49] [PASSED] ABGR8888 Width 0
[21:25:49] [PASSED] ABGR8888 Height 0
[21:25:49] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:25:49] [PASSED] ABGR8888 Large buffer offset
[21:25:49] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:25:49] [PASSED] ABGR8888 Invalid flag
[21:25:49] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:25:49] [PASSED] ABGR8888 Valid buffer modifier
[21:25:49] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:25:49] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:25:49] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:25:49] [PASSED] NV12 Normal sizes
[21:25:49] [PASSED] NV12 Max sizes
[21:25:49] [PASSED] NV12 Invalid pitch
[21:25:49] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:25:49] [PASSED] NV12 different  modifier per-plane
[21:25:49] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:25:49] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:25:49] [PASSED] NV12 Modifier for inexistent plane
[21:25:49] [PASSED] NV12 Handle for inexistent plane
[21:25:49] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:25:49] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:25:49] [PASSED] YVU420 Normal sizes
[21:25:49] [PASSED] YVU420 Max sizes
[21:25:49] [PASSED] YVU420 Invalid pitch
[21:25:49] [PASSED] YVU420 Different pitches
[21:25:49] [PASSED] YVU420 Different buffer offsets/pitches
[21:25:49] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:25:49] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:25:49] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:25:49] [PASSED] YVU420 Valid modifier
[21:25:49] [PASSED] YVU420 Different modifiers per plane
[21:25:49] [PASSED] YVU420 Modifier for inexistent plane
[21:25:49] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:25:49] [PASSED] X0L2 Normal sizes
[21:25:49] [PASSED] X0L2 Max sizes
[21:25:49] [PASSED] X0L2 Invalid pitch
[21:25:49] [PASSED] X0L2 Pitch greater than minimum required
[21:25:49] [PASSED] X0L2 Handle for inexistent plane
[21:25:49] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:25:49] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:25:49] [PASSED] X0L2 Valid modifier
[21:25:49] [PASSED] X0L2 Modifier for inexistent plane
[21:25:49] =========== [PASSED] drm_test_framebuffer_create ===========
[21:25:49] [PASSED] drm_test_framebuffer_free
[21:25:49] [PASSED] drm_test_framebuffer_init
[21:25:49] [PASSED] drm_test_framebuffer_init_bad_format
[21:25:49] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:25:49] [PASSED] drm_test_framebuffer_lookup
[21:25:49] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:25:49] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:25:49] ================= [PASSED] drm_framebuffer =================
[21:25:49] ================ drm_gem_shmem (8 subtests) ================
[21:25:49] [PASSED] drm_gem_shmem_test_obj_create
[21:25:49] [PASSED] drm_gem_shmem_test_obj_create_private
[21:25:49] [PASSED] drm_gem_shmem_test_pin_pages
[21:25:49] [PASSED] drm_gem_shmem_test_vmap
[21:25:49] [PASSED] drm_gem_shmem_test_get_sg_table
[21:25:49] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:25:49] [PASSED] drm_gem_shmem_test_madvise
[21:25:49] [PASSED] drm_gem_shmem_test_purge
[21:25:49] ================== [PASSED] drm_gem_shmem ==================
[21:25:49] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[21:25:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:25:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:25:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:25:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:25:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:25:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:25:49] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:25:49] [PASSED] Automatic
[21:25:49] [PASSED] Full
[21:25:49] [PASSED] Limited 16:235
[21:25:49] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:25:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:25:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:25:49] [PASSED] drm_test_check_disable_connector
[21:25:49] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:25:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:25:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:25:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:25:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:25:49] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:25:49] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:25:49] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:25:49] [PASSED] drm_test_check_output_bpc_dvi
[21:25:49] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:25:49] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:25:49] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:25:49] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:25:49] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:25:49] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:25:49] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:25:49] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:25:49] ============ drm_test_check_hdmi_color_format  =============
[21:25:49] [PASSED] AUTO -> RGB
[21:25:49] [PASSED] YCBCR422 -> YUV422
[21:25:49] [PASSED] YCBCR420 -> YUV420
[21:25:49] [PASSED] YCBCR444 -> YUV444
[21:25:49] [PASSED] RGB -> RGB
[21:25:49] ======== [PASSED] drm_test_check_hdmi_color_format =========
[21:25:49] ======== drm_test_check_hdmi_color_format_420_only  ========
[21:25:49] [PASSED] RGB should fail
[21:25:49] [PASSED] YUV444 should fail
[21:25:49] [PASSED] YUV422 should fail
[21:25:49] [PASSED] YUV420 should work
[21:25:49] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[21:25:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:25:49] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:25:49] [PASSED] drm_test_check_broadcast_rgb_value
[21:25:49] [PASSED] drm_test_check_bpc_8_value
[21:25:49] [PASSED] drm_test_check_bpc_10_value
[21:25:49] [PASSED] drm_test_check_bpc_12_value
[21:25:49] [PASSED] drm_test_check_format_value
[21:25:49] [PASSED] drm_test_check_tmds_char_value
[21:25:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:25:49] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[21:25:49] [PASSED] drm_test_check_mode_valid
[21:25:49] [PASSED] drm_test_check_mode_valid_reject
[21:25:49] [PASSED] drm_test_check_mode_valid_reject_rate
[21:25:49] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:25:49] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[21:25:49] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[21:25:49] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[21:25:49] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:25:49] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[21:25:49] [PASSED] drm_test_check_infoframes
[21:25:49] [PASSED] drm_test_check_reject_avi_infoframe
[21:25:49] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[21:25:49] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[21:25:49] [PASSED] drm_test_check_reject_audio_infoframe
[21:25:49] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[21:25:49] ================= drm_managed (2 subtests) =================
[21:25:49] [PASSED] drm_test_managed_release_action
[21:25:49] [PASSED] drm_test_managed_run_action
[21:25:49] =================== [PASSED] drm_managed ===================
[21:25:49] =================== drm_mm (6 subtests) ====================
[21:25:49] [PASSED] drm_test_mm_init
[21:25:49] [PASSED] drm_test_mm_debug
[21:25:49] [PASSED] drm_test_mm_align32
[21:25:49] [PASSED] drm_test_mm_align64
[21:25:49] [PASSED] drm_test_mm_lowest
[21:25:49] [PASSED] drm_test_mm_highest
[21:25:49] ===================== [PASSED] drm_mm ======================
[21:25:49] ============= drm_modes_analog_tv (5 subtests) =============
[21:25:49] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:25:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:25:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:25:49] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:25:49] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:25:49] =============== [PASSED] drm_modes_analog_tv ===============
[21:25:49] ============== drm_plane_helper (2 subtests) ===============
[21:25:49] =============== drm_test_check_plane_state  ================
[21:25:49] [PASSED] clipping_simple
[21:25:49] [PASSED] clipping_rotate_reflect
[21:25:49] [PASSED] positioning_simple
[21:25:49] [PASSED] upscaling
[21:25:49] [PASSED] downscaling
[21:25:49] [PASSED] rounding1
[21:25:49] [PASSED] rounding2
[21:25:49] [PASSED] rounding3
[21:25:49] [PASSED] rounding4
[21:25:49] =========== [PASSED] drm_test_check_plane_state ============
[21:25:49] =========== drm_test_check_invalid_plane_state  ============
[21:25:49] [PASSED] positioning_invalid
[21:25:49] [PASSED] upscaling_invalid
[21:25:49] [PASSED] downscaling_invalid
[21:25:49] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:25:49] ================ [PASSED] drm_plane_helper =================
[21:25:49] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:25:49] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:25:49] [PASSED] None
[21:25:49] [PASSED] PAL
[21:25:49] [PASSED] NTSC
[21:25:49] [PASSED] Both, NTSC Default
[21:25:49] [PASSED] Both, PAL Default
[21:25:49] [PASSED] Both, NTSC Default, with PAL on command-line
[21:25:49] [PASSED] Both, PAL Default, with NTSC on command-line
[21:25:49] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:25:49] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:25:49] ================== drm_rect (9 subtests) ===================
[21:25:49] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:25:49] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:25:49] [PASSED] drm_test_rect_clip_scaled_clipped
[21:25:49] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:25:49] ================= drm_test_rect_intersect  =================
[21:25:49] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:25:49] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:25:49] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:25:49] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:25:49] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:25:49] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:25:49] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:25:49] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:25:49] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:25:49] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:25:49] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:25:49] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:25:49] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:25:49] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:25:49] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:25:49] ============= [PASSED] drm_test_rect_intersect =============
[21:25:49] ================ drm_test_rect_calc_hscale  ================
[21:25:49] [PASSED] normal use
[21:25:49] [PASSED] out of max range
[21:25:49] [PASSED] out of min range
[21:25:49] [PASSED] zero dst
[21:25:49] [PASSED] negative src
[21:25:49] [PASSED] negative dst
[21:25:49] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:25:49] ================ drm_test_rect_calc_vscale  ================
[21:25:49] [PASSED] normal use
[21:25:49] [PASSED] out of max range
[21:25:49] [PASSED] out of min range
[21:25:49] [PASSED] zero dst
[21:25:49] [PASSED] negative src
[21:25:49] [PASSED] negative dst
[21:25:49] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:25:49] ================== drm_test_rect_rotate  ===================
[21:25:49] [PASSED] reflect-x
[21:25:49] [PASSED] reflect-y
[21:25:49] [PASSED] rotate-0
[21:25:49] [PASSED] rotate-90
[21:25:49] [PASSED] rotate-180
[21:25:49] [PASSED] rotate-270
[21:25:49] ============== [PASSED] drm_test_rect_rotate ===============
[21:25:49] ================ drm_test_rect_rotate_inv  =================
[21:25:49] [PASSED] reflect-x
[21:25:49] [PASSED] reflect-y
[21:25:49] [PASSED] rotate-0
[21:25:49] [PASSED] rotate-90
[21:25:49] [PASSED] rotate-180
[21:25:49] [PASSED] rotate-270
[21:25:49] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:25:49] ==================== [PASSED] drm_rect =====================
[21:25:49] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:25:49] ============ drm_test_sysfb_build_fourcc_list  =============
[21:25:49] [PASSED] no native formats
[21:25:49] [PASSED] XRGB8888 as native format
[21:25:49] [PASSED] remove duplicates
[21:25:49] [PASSED] convert alpha formats
[21:25:49] [PASSED] random formats
[21:25:49] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:25:49] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:25:49] ================== drm_fixp (2 subtests) ===================
[21:25:49] [PASSED] drm_test_int2fixp
[21:25:49] [PASSED] drm_test_sm2fixp
[21:25:49] ==================== [PASSED] drm_fixp =====================
[21:25:49] ============================================================
[21:25:49] Testing complete. Ran 641 tests: passed: 641
[21:25:49] Elapsed time: 27.189s total, 1.757s configuring, 25.218s building, 0.191s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:25:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:25:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:26:00] Starting KUnit Kernel (1/1)...
[21:26:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:26:01] ============= refcount_interrupt (4 subtests) ==============
[21:26:01] [PASSED] test_single_irq_change
[21:26:01] [PASSED] test_nested_irq_change
[21:26:01] [PASSED] test_multiple_irq_change
[21:26:01] [PASSED] test_irq_save
[21:26:01] =============== [PASSED] refcount_interrupt ================
[21:26:01] ================= ttm_device (5 subtests) ==================
[21:26:01] [PASSED] ttm_device_init_basic
[21:26:01] [PASSED] ttm_device_init_multiple
[21:26:01] [PASSED] ttm_device_fini_basic
[21:26:01] [PASSED] ttm_device_init_no_vma_man
[21:26:01] ================== ttm_device_init_pools  ==================
[21:26:01] [PASSED] No DMA allocations, no DMA32 required
[21:26:01] [PASSED] DMA allocations, DMA32 required
[21:26:01] [PASSED] No DMA allocations, DMA32 required
[21:26:01] [PASSED] DMA allocations, no DMA32 required
[21:26:01] ============== [PASSED] ttm_device_init_pools ==============
[21:26:01] =================== [PASSED] ttm_device ====================
[21:26:01] ================== ttm_pool (8 subtests) ===================
[21:26:01] ================== ttm_pool_alloc_basic  ===================
[21:26:01] [PASSED] One page
[21:26:01] [PASSED] More than one page
[21:26:01] [PASSED] Above the allocation limit
[21:26:01] [PASSED] One page, with coherent DMA mappings enabled
[21:26:01] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:26:01] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:26:01] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:26:01] [PASSED] One page
[21:26:01] [PASSED] More than one page
[21:26:01] [PASSED] Above the allocation limit
[21:26:01] [PASSED] One page, with coherent DMA mappings enabled
[21:26:01] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:26:01] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:26:01] [PASSED] ttm_pool_alloc_order_caching_match
[21:26:01] [PASSED] ttm_pool_alloc_caching_mismatch
[21:26:01] [PASSED] ttm_pool_alloc_order_mismatch
[21:26:01] [PASSED] ttm_pool_free_dma_alloc
[21:26:01] [PASSED] ttm_pool_free_no_dma_alloc
[21:26:01] [PASSED] ttm_pool_fini_basic
[21:26:01] ==================== [PASSED] ttm_pool =====================
[21:26:01] ================ ttm_resource (8 subtests) =================
[21:26:01] ================= ttm_resource_init_basic  =================
[21:26:01] [PASSED] Init resource in TTM_PL_SYSTEM
[21:26:01] [PASSED] Init resource in TTM_PL_VRAM
[21:26:01] [PASSED] Init resource in a private placement
[21:26:01] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:26:01] ============= [PASSED] ttm_resource_init_basic =============
[21:26:01] [PASSED] ttm_resource_init_pinned
[21:26:01] [PASSED] ttm_resource_fini_basic
[21:26:01] [PASSED] ttm_resource_manager_init_basic
[21:26:01] [PASSED] ttm_resource_manager_usage_basic
[21:26:01] [PASSED] ttm_resource_manager_set_used_basic
[21:26:01] [PASSED] ttm_sys_man_alloc_basic
[21:26:01] [PASSED] ttm_sys_man_free_basic
[21:26:01] ================== [PASSED] ttm_resource ===================
[21:26:01] =================== ttm_tt (15 subtests) ===================
[21:26:01] ==================== ttm_tt_init_basic  ====================
[21:26:01] [PASSED] Page-aligned size
[21:26:01] [PASSED] Extra pages requested
[21:26:01] ================ [PASSED] ttm_tt_init_basic ================
[21:26:01] [PASSED] ttm_tt_init_misaligned
[21:26:01] [PASSED] ttm_tt_fini_basic
[21:26:01] [PASSED] ttm_tt_fini_sg
[21:26:01] [PASSED] ttm_tt_fini_shmem
[21:26:01] [PASSED] ttm_tt_create_basic
[21:26:01] [PASSED] ttm_tt_create_invalid_bo_type
[21:26:01] [PASSED] ttm_tt_create_ttm_exists
[21:26:01] [PASSED] ttm_tt_create_failed
[21:26:01] [PASSED] ttm_tt_destroy_basic
[21:26:01] [PASSED] ttm_tt_populate_null_ttm
[21:26:01] [PASSED] ttm_tt_populate_populated_ttm
[21:26:01] [PASSED] ttm_tt_unpopulate_basic
[21:26:01] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:26:01] [PASSED] ttm_tt_swapin_basic
[21:26:01] ===================== [PASSED] ttm_tt ======================
[21:26:01] =================== ttm_bo (14 subtests) ===================
[21:26:01] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:26:01] [PASSED] Cannot be interrupted and sleeps
[21:26:01] [PASSED] Cannot be interrupted, locks straight away
[21:26:01] [PASSED] Can be interrupted, sleeps
[21:26:01] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:26:01] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:26:01] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:26:01] [PASSED] ttm_bo_reserve_double_resv
[21:26:01] [PASSED] ttm_bo_reserve_interrupted
[21:26:01] [PASSED] ttm_bo_reserve_deadlock
[21:26:01] [PASSED] ttm_bo_unreserve_basic
[21:26:01] [PASSED] ttm_bo_unreserve_pinned
[21:26:01] [PASSED] ttm_bo_unreserve_bulk
[21:26:01] [PASSED] ttm_bo_fini_basic
[21:26:01] [PASSED] ttm_bo_fini_shared_resv
[21:26:01] [PASSED] ttm_bo_pin_basic
[21:26:01] [PASSED] ttm_bo_pin_unpin_resource
[21:26:01] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:26:01] ===================== [PASSED] ttm_bo ======================
[21:26:01] ============== ttm_bo_validate (22 subtests) ===============
[21:26:01] ============== ttm_bo_init_reserved_sys_man  ===============
[21:26:01] [PASSED] Buffer object for userspace
[21:26:01] [PASSED] Kernel buffer object
[21:26:01] [PASSED] Shared buffer object
[21:26:01] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:26:01] ============== ttm_bo_init_reserved_mock_man  ==============
[21:26:01] [PASSED] Buffer object for userspace
[21:26:01] [PASSED] Kernel buffer object
[21:26:01] [PASSED] Shared buffer object
[21:26:01] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:26:01] [PASSED] ttm_bo_init_reserved_resv
[21:26:01] ================== ttm_bo_validate_basic  ==================
[21:26:01] [PASSED] Buffer object for userspace
[21:26:01] [PASSED] Kernel buffer object
[21:26:01] [PASSED] Shared buffer object
[21:26:01] ============== [PASSED] ttm_bo_validate_basic ==============
[21:26:01] [PASSED] ttm_bo_validate_invalid_placement
[21:26:01] ============= ttm_bo_validate_same_placement  ==============
[21:26:01] [PASSED] System manager
[21:26:01] [PASSED] VRAM manager
[21:26:01] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:26:01] [PASSED] ttm_bo_validate_failed_alloc
[21:26:01] [PASSED] ttm_bo_validate_pinned
[21:26:01] [PASSED] ttm_bo_validate_busy_placement
[21:26:01] ================ ttm_bo_validate_multihop  =================
[21:26:01] [PASSED] Buffer object for userspace
[21:26:01] [PASSED] Kernel buffer object
[21:26:01] [PASSED] Shared buffer object
[21:26:01] ============ [PASSED] ttm_bo_validate_multihop =============
[21:26:01] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:26:01] [PASSED] Buffer object in system domain, no page vector
[21:26:01] [PASSED] Buffer object in system domain with an existing page vector
[21:26:01] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:26:01] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:26:01] [PASSED] Buffer object for userspace
[21:26:01] [PASSED] Kernel buffer object
[21:26:01] [PASSED] Shared buffer object
[21:26:01] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:26:01] [PASSED] ttm_bo_validate_move_fence_signaled
[21:26:01] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:26:01] [PASSED] Waits for GPU
[21:26:01] [PASSED] Tries to lock straight away
[21:26:01] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:26:01] [PASSED] ttm_bo_validate_swapout
[21:26:01] [PASSED] ttm_bo_validate_happy_evict
[21:26:01] [PASSED] ttm_bo_validate_all_pinned_evict
[21:26:01] [PASSED] ttm_bo_validate_allowed_only_evict
[21:26:01] [PASSED] ttm_bo_validate_deleted_evict
[21:26:01] [PASSED] ttm_bo_validate_busy_domain_evict
[21:26:01] [PASSED] ttm_bo_validate_evict_gutting
[21:26:01] [PASSED] ttm_bo_validate_recrusive_evict
[21:26:01] ================= [PASSED] ttm_bo_validate =================
[21:26:01] ============================================================
[21:26:01] Testing complete. Ran 106 tests: passed: 106
[21:26:01] Elapsed time: 11.953s total, 1.782s configuring, 9.957s building, 0.186s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[21:26:01] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:26:03] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:26:11] Starting KUnit Kernel (1/1)...
[21:26:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:26:12] ============= refcount_interrupt (4 subtests) ==============
[21:26:12] [PASSED] test_single_irq_change
[21:26:12] [PASSED] test_nested_irq_change
[21:26:12] [PASSED] test_multiple_irq_change
[21:26:12] [PASSED] test_irq_save
[21:26:12] =============== [PASSED] refcount_interrupt ================
[21:26:12] =============== dma-buf-fence (12 subtests) ================
[21:26:12] [PASSED] test_sanitycheck
[21:26:12] [PASSED] test_signaling
[21:26:12] [PASSED] test_add_callback
[21:26:12] [PASSED] test_late_add_callback
[21:26:12] [PASSED] test_rm_callback
[21:26:12] [PASSED] test_late_rm_callback
[21:26:12] [PASSED] test_status
[21:26:12] [PASSED] test_error
[21:26:12] [PASSED] test_wait
[21:26:12] [PASSED] test_wait_timeout
[21:26:12] [PASSED] test_stub
[21:26:12] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[21:26:12] ================== [PASSED] dma-buf-fence ==================
[21:26:12] ============ dma-buf-fence-chain (11 subtests) =============
[21:26:12] [PASSED] test_sanitycheck
[21:26:12] [PASSED] test_find_seqno
[21:26:12] [PASSED] test_find_signaled
[21:26:12] [PASSED] test_find_out_of_order
[21:26:17] [PASSED] test_find_gap
[21:26:17] [PASSED] test_find_race
[21:26:17] [PASSED] test_signal_forward
[21:26:17] [PASSED] test_signal_backward
[21:26:17] [PASSED] test_wait_forward
[21:26:17] [PASSED] test_wait_backward
[21:26:17] [PASSED] test_wait_random
[21:26:17] =============== [PASSED] dma-buf-fence-chain ===============
[21:26:17] ============ dma-buf-fence-unwrap (10 subtests) ============
[21:26:17] [PASSED] test_sanitycheck
[21:26:17] [PASSED] test_unwrap_array
[21:26:17] [PASSED] test_unwrap_chain
[21:26:17] [PASSED] test_unwrap_chain_array
[21:26:17] [PASSED] test_unwrap_merge
[21:26:17] [PASSED] test_unwrap_merge_duplicate
[21:26:17] [PASSED] test_unwrap_merge_seqno
[21:26:17] [PASSED] test_unwrap_merge_order
[21:26:17] [PASSED] test_unwrap_merge_complex
[21:26:17] [PASSED] test_unwrap_merge_complex_seqno
[21:26:17] ============== [PASSED] dma-buf-fence-unwrap ===============
[21:26:17] ================ dma-buf-resv (5 subtests) =================
[21:26:17] [PASSED] test_sanitycheck
[21:26:17] ===================== test_signaling  ======================
[21:26:17] [PASSED] kernel
[21:26:17] [PASSED] write
[21:26:17] [PASSED] read
[21:26:17] [PASSED] bookkeep
[21:26:17] ================= [PASSED] test_signaling ==================
[21:26:17] ====================== test_for_each  ======================
[21:26:17] [PASSED] kernel
[21:26:17] [PASSED] write
[21:26:17] [PASSED] read
[21:26:17] [PASSED] bookkeep
[21:26:17] ================== [PASSED] test_for_each ==================
[21:26:17] ================= test_for_each_unlocked  ==================
[21:26:17] [PASSED] kernel
[21:26:17] [PASSED] write
[21:26:17] [PASSED] read
[21:26:17] [PASSED] bookkeep
[21:26:17] ============= [PASSED] test_for_each_unlocked ==============
[21:26:17] ===================== test_get_fences  =====================
[21:26:17] [PASSED] kernel
[21:26:17] [PASSED] write
[21:26:17] [PASSED] read
[21:26:17] [PASSED] bookkeep
[21:26:17] ================= [PASSED] test_get_fences =================
[21:26:17] ================== [PASSED] dma-buf-resv ===================
[21:26:17] ============================================================
[21:26:17] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[21:26:17] Elapsed time: 15.951s total, 1.796s configuring, 8.783s building, 5.351s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH v6 02/24] drm/xe: Add xe_migrate_update_pgtables_cpu_execute helper

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Structurally flawed assertions cause kernel oops and include tautological checks.
--

commit 780cddb686fdf43f07c0012e23c36d21d368d194
Author: Matthew Brost <matthew.brost@intel.com>

drm/xe: Add xe_migrate_update_pgtables_cpu_execute helper

This commit extracts the CPU-side page-table update logic into a new helper
function xe_migrate_update_pgtables_cpu_execute. This helper is intended to
support implementing CPU binds when a bind job's dependencies are resolved.
It also introduces basic sanity checks on the function arguments.

Link: https://patch.msgid.link/20260228013501.106680-3-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 149c5fa654e67..68a0b05f56ec9 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c

[ ... ]

> @@ -1819,6 +1819,38 @@ struct migrate_test_params {
>  	container_of(_priv, struct migrate_test_params, base)
>  #endif
>  
> +static void
> +xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
> +				       const struct xe_migrate_pt_update_ops *ops,
> +				       struct xe_vm_pgtable_update_op *pt_op,
> +				       u32 num_ops)
> +{
> +	u32 j, i;
> +
> +	for (j = 0; j < num_ops; ++j, ++pt_op) {
> +		for (i = 0; i < pt_op->num_entries; i++) {
> +			const struct xe_vm_pgtable_update *update =
> +				&pt_op->entries[i];
> +
> +			xe_tile_assert(tile, update);
> +			xe_tile_assert(tile, update->pt_bo);
> +			xe_tile_assert(tile, !iosys_map_is_null(&update->pt_bo->vmap));

[Severity: Medium]
Are these assertions structurally flawed?

First, update is derived from &pt_op->entries[i], meaning the address is
evaluated inline and will never be NULL, making xe_tile_assert(tile, update)
a tautology.

Second, if update->pt_bo is indeed NULL, the
xe_tile_assert(tile, update->pt_bo) macro will warn but execution will
continue. The subsequent assertion computes &update->pt_bo->vmap, yielding an
invalid pointer (NULL + offset), and passes it to iosys_map_is_null(). This
inline function dereferences the pointer, causing a kernel oops/panic. This
defeats the purpose of the sanity checks, as an internal invariant violation
will cause a hard crash.

Note that this code is moved to xe_cpu_bind_update_pgtables_execute in
drivers/gpu/drm/xe/xe_cpu_bind.c by the later patch "drm/xe: Add CPU bind
layer", but the structural flaw remains unfixed there.

> +
> +			if (pt_op->bind)
> +				ops->populate(tile, &update->pt_bo->vmap,
> +					      NULL, update->ofs, update->qwords,
> +					      update);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=2

Re: [PATCH v6 06/24] drm/xe: Add XE_BO_FLAG_PUT_VM_ASYNC

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Premature drop of VM reference in xe_bo_put_commit() allows the VM and its shared dma-resv to be freed while the BO is still alive in TTM, leading to a use-after-free on the resv.
--

commit b2fad1ac33df0229950ed8b4d71c885827c4b7e3
Author: Matthew Brost <matthew.brost@intel.com>

drm/xe: Add XE_BO_FLAG_PUT_VM_ASYNC

This commit adds a new flag, XE_BO_FLAG_PUT_VM_ASYNC, which indicates that an
asynchronous BO put should also drop an additional reference to the BO's VM to
prevent the shared dma-resv from disappearing before the BO.

Link: https://patch.msgid.link/20260228013501.106680-7-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index b162753cebb70..aea4b0fee8e33 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -3998,8 +3998,14 @@ void xe_bo_put_commit(struct llist_head *deferred)
>  	if (!freed)
>  		return;
>  
> -	llist_for_each_entry_safe(bo, next, freed, freed)
> +	llist_for_each_entry_safe(bo, next, freed, freed) {
> +		struct xe_vm *vm = bo->vm;
> +		bool async = bo->flags & XE_BO_FLAG_PUT_VM_ASYNC;
> +
>  		drm_gem_object_free(&bo->ttm.base.refcount);
> +		if (async)
> +			xe_vm_put(vm);

[Severity: High]
Does this sequence drop the VM reference prematurely and risk a use-after-free
on the VM's dma_resv?

Looking at xe_bo_put_commit(), we call drm_gem_object_free(), which can
trigger ttm_bo_release(). If ttm_bo_individualize_resv() fails due to
memory pressure while the VM's shared dma_resv is concurrently locked by
another thread, TTM handles this by queuing the BO for delayed deletion
via ttm_bo_delayed_delete() and returning early.

If TTM returns early keeping the BO alive, and we immediately proceed
to drop the VM reference here:

    drm_gem_object_free(&bo->ttm.base.refcount);
    if (async)
        xe_vm_put(vm);

could this free the VM and its embedded dma_resv if it was the last
reference? Later, when ttm_bo_delayed_delete() executes, it would
attempt to call dma_resv_lock(bo->base.resv) on the freed VM resv,
causing a regression.

Is there a mechanism to ensure the VM stays alive as long as TTM delays the
BO deletion?

> +	}
>  }

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=6

Re: [PATCH v6 07/24] drm/xe: Update scheduler job layer to support PT jobs

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] PT jobs consume the TLB flush seqno without executing a hardware TLB flush, potentially causing subsequent GPU jobs to run with stale page tables.
--

commit 3d489d315c4f278dad409a11a04984a2139095c2
Author: Matthew Brost <matthew.brost@intel.com>

drm/xe: Update scheduler job layer to support PT jobs

Update the scheduler job layer to support PT jobs which execute entirely
on the CPU without requiring LRC fences or a batch address. Repurpose
LRC fence storage for PT-job arguments.

Link: https://patch.msgid.link/20260228013501.106680-8-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
> --- a/drivers/gpu/drm/xe/xe_sched_job.c
> +++ b/drivers/gpu/drm/xe/xe_sched_job.c
[ ... ]
> @@ -266,6 +293,9 @@ void xe_sched_job_arm(struct xe_sched_job *job)
>  		job->ring_ops_flush_tlb = true;
>  	}
>  
> +	if (job->is_pt_job)
> +		goto arm;
> +
>  	/* Arm the pre-allocated fences */
>  	for (i = 0; i < q->width; prev = fence, ++i) {

[Severity: Critical]
Will this cause subsequent GPU jobs to run with stale page tables?

Looking at xe_sched_job_arm() in drivers/gpu/drm/xe/xe_sched_job.c, the code
just above this addition checks if a TLB flush is needed and updates
q->tlb_flush_seqno:

        if (vm && !xe_sched_job_is_migration(q) && !xe_vm_in_lr_mode(vm) &&
            (vm->batch_invalidate_tlb || vm->tlb_flush_seqno != q->tlb_flush_seqno)) {
                xe_vm_assert_held(vm);
                q->tlb_flush_seqno = vm->tlb_flush_seqno;
                job->ring_ops_flush_tlb = true;
        }

If the current job is a PT job, the new check jumps to the arm label,
skipping the hardware ring submission where the flush would normally execute.
Because q->tlb_flush_seqno was already updated, when a subsequent GPU payload
job is submitted to this same queue, it will see the seqnos match and skip
flushing. This could allow the GPU to access memory using a stale TLB.

Should the job->is_pt_job check precede the TLB invalidation check to prevent
the CPU-only PT job from stealing the flush notification?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=7

Re: [PATCH v6 10/24] drm/xe: Update GuC submission backend to run PT jobs

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Critical] PT jobs swallow dependency and cancellation errors, silently reporting false success and potentially leaving page tables in an inconsistent state.
- [High] Memory leak of xe_pt_job_ops and a dma_fence reference when a PT job is canceled or destroyed without being executed.
--

commit c6e167292efa7934a75cd29809e1057eae0d18c2
Author: Matthew Brost <matthew.brost@intel.com>

drm/xe: Update GuC submission backend to run PT jobs

PT jobs bypass GPU execution for the final step of a bind job, using the
CPU to program the required page tables. Teach the GuC submission backend
how to execute these jobs.

Link: https://patch.msgid.link/20260228013501.106680-11-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 8b8673f4e037c..b7ec96650405a 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
[ ... ]
> @@ -1262,14 +1278,25 @@ guc_exec_queue_run_job(struct drm_sched_job *drm_job)
>  				register_exec_queue(primary, GUC_CONTEXT_NORMAL);
>  		}
>  
> -		if (!exec_queue_registered(q))
> -			register_exec_queue(q, GUC_CONTEXT_NORMAL);
> -		if (!job->restore_replay)
> -			q->ring_ops->emit_job(job);
> -		submit_exec_queue(q, job);
> +		if (is_pt_job(job)) {
> +			xe_gt_assert(guc_to_gt(guc), !exec_queue_registered(q));
> +			run_pt_job(job);
> +		} else {
> +			if (!exec_queue_registered(q))
> +				register_exec_queue(q, GUC_CONTEXT_NORMAL);
> +			if (!job->restore_replay)
> +				q->ring_ops->emit_job(job);
> +			submit_exec_queue(q, job);
> +		}
>  		job->restore_replay = false;
>  	}
>  
> +	if (is_pt_job(job)) {
> +		xe_pt_job_ops_put(job->pt_update[0].pt_job_ops);
> +		dma_fence_put(job->fence);	/* Drop ref from xe_sched_job_arm */
> +		return NULL;
> +	}

[Severity: High]
Does this code leak the xe_pt_job_ops array and dma_fence objects when a PT
job is canceled before execution?

Because the cleanup operations (xe_pt_job_ops_put() and the extra
dma_fence_put()) are tied to job execution here in guc_exec_queue_run_job(),
they appear to be missed if the job is destroyed before running.

Looking at xe_sched_job_destroy() in drivers/gpu/drm/xe/xe_sched_job.c:

void xe_sched_job_destroy(struct kref *ref)
{
	...
	xe_sched_job_free_fences(job);
	dma_fence_put(job->fence);
	drm_sched_job_cleanup(&job->drm);
	job_free(job);
	...
}

If a PT job is armed, it takes a reference to pt_job_ops and an extra
reference to job->fence. If the queue is killed and the job aborted before it
executes, xe_sched_job_destroy() misses the xe_pt_job_ops_put() call and
only drops one dma_fence_put() reference.

Can an unprivileged user repeatedly submit PT jobs via bind ioctls and
immediately destroy the queue before execution to trigger this?

[Severity: Critical]
Does returning NULL unconditionally here swallow dependency and cancellation
errors?

If a queue is banned, guc_exec_queue_run_job() skips run_pt_job() but still
returns NULL here, which the DRM scheduler treats as a synchronous success.

Additionally, PT jobs are initialized with a stub fence:

struct xe_sched_job *xe_sched_job_create(...)
{
	...
	if (!batch_addr) {
		job->fence = dma_fence_get_stub();
		job->is_pt_job = true;
	}
	...
}

Since a stub fence is permanently signaled with error = 0,
xe_sched_job_set_error() fails to set any error state, and
xe_sched_job_is_error() evaluates to false.

Can this result in page table updates silently failing while reporting success
to userspace? For unbind operations, this could leave memory mapped in the
GPU after it is freed, potentially allowing read or write access to reallocated
memory from another queue in the same VM.

>  
>  run_job_out:
>  
>  	return job->fence;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=10

Re: [PATCH v6 09/24] drm/xe: Add struct xe_pt_job_ops

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing BO refcount re-initialization causes refcount underflow and memory leak during async free.
--

commit 6e95dc31189c14b0582d03e7feb8e249921d75d3
Author: Matthew Brost <matthew.brost@intel.com>
Subject: drm/xe: Add struct xe_pt_job_ops

This commit introduces struct xe_pt_job_ops, a dynamically refcounted object
containing the information required to issue a CPU bind via a job after the
initial bind IOCTL returns.

Link: https://patch.msgid.link/20260228013501.106680-10-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
> index e560f167fdf1b..30127ebf1b605 100644
> --- a/drivers/gpu/drm/xe/xe_pt.c
> +++ b/drivers/gpu/drm/xe/xe_pt.c

[ ... ]

> @@ -213,7 +214,19 @@ void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred)
>  
>  	XE_WARN_ON(!list_empty(&pt->bo->ttm.base.gpuva.list));
>  	xe_bo_unpin(pt->bo);
> -	xe_bo_put_deferred(pt->bo, deferred, NULL);
> +	xe_bo_put_deferred(pt->bo, deferred, &added);
> +	if (added) {
> +		xe_assert(pt->bo->vm->xe, !kref_read(&pt->bo->ttm.base.refcount));
> +
> +		/*
> +		 * We need the VM present until the BO is destroyed as it shares
> +		 * a dma-resv and BO destroy is async. Reinit BO refcount so
> +		 * xe_bo_put_async can be used when the PT job ops refcount goes
> +		 * to zero.
> +		 */
> +		xe_vm_get(pt->bo->vm);
> +		pt->bo->flags |= XE_BO_FLAG_PUT_VM_ASYNC;
> +	}

[Severity: High]
Does this code forget to actually re-initialize the BO refcount? The comment
explicitly mentions reinitializing the BO refcount so xe_bo_put_async can be
used, but it looks like only the VM is retrieved and the flag is set. Without a
call to reinitialize the kref (like kref_init for pt->bo->ttm.base.refcount), 
the refcount remains at zero.

[ ... ]

> +static void xe_pt_job_ops_destroy(struct kref *ref)
> +{
> +	struct xe_pt_job_ops *pt_job_ops =
> +		container_of(ref, struct xe_pt_job_ops, refcount);
> +	struct llist_node *freed;
> +	struct xe_bo *bo, *next;
> +
> +	xe_pt_update_ops_free(pt_job_ops->ops,
> +			      pt_job_ops->current_op);
> +
> +	freed = llist_del_all(&pt_job_ops->deferred);
> +	if (freed) {
> +		llist_for_each_entry_safe(bo, next, freed, freed) {
> +			struct xe_bo_dev *bo_device =
> +				&xe_bo_device(bo)->bo_device;
> +			/*
> +			 * If called from run_job, we are in the dma-fencing
> +			 * path and cannot take dma-resv locks so use an async
> +			 * put.
> +			 */
> +			if (llist_add(&bo->freed, &bo_device->async_list))
> +				schedule_work(&bo_device->async_free);
> +		}
> +	}

[Severity: High]
Because the BO refcount was left at zero during xe_pt_destroy, will the later
xe_bo_put in the async_free worker trigger a refcount underflow here? A kref_put
on a zero refcount returns false and skips the release function (such as
drm_gem_object_free). Can this cause the page table BO memory to be permanently
leaked?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=9

Re: [PATCH v6 19/24] drm/xe: Add ULLS migration job support to migration layer

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Holding job_mutex while waiting on a dma_fence in xe_migrate_ulls_exit violates the dma_fence contract and risks deadlocks during GPU reset.
--

commit bbc9d2795fb53c65f8a7edb5c701c0f994595d7a
Author: Matthew Brost <matthew.brost@intel.com>

drm/xe: Add ULLS migration job support to migration layer

This commit adds a function to enter ULLS mode for migration jobs and a
delayed worker to exit it for power savings. It sets flags on migration
jobs so submission backends can submit in ULLS mode, which is only
supported on DGFX and USM platforms.

Link: https://patch.msgid.link/20260228013501.106680-21-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 471ae5741836e..3e59aeeca614d 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c

[ ... ]

> @@ -448,6 +468,161 @@ static int xe_migrate_lock_prepare_vm(struct xe_tile *tile, struct xe_migrate *m
[ ... ]
> +static void xe_migrate_ulls_exit(struct work_struct *work)
> +{
[ ... ]
> +	mutex_lock(&m->job_mutex);
> +
> +	if (!xe_exec_queue_is_idle(m->q, 1))
> +		goto unlock_exit;
> +
> +	xe_sched_job_get(job);
> +	fence = __xe_migrate_job_push(m, job, ULLS_EXIT);
> +
> +	/* Serialize the PM put against the ring being taken off the hardware */
> +	dma_fence_wait(fence, false);

[Severity: High]
Can this lead to a deadlock during GPU reset?

In xe_migrate_ulls_exit(), the delayed worker acquires m->job_mutex, pushes
the ULLS_EXIT job, and blocks on its completion fence via dma_fence_wait()
before releasing the mutex.

Since m->job_mutex is explicitly tainted with fs_reclaim during
initialization, marking it as used in memory reclaim paths, blocking on a
dma_fence while holding this lock violates dma_fence locking rules. Fence
signaling can depend on memory allocations, creating a circular dependency
(job_mutex -> dma_fence -> fs_reclaim -> job_mutex).

If the GPU hangs while processing the ULLS_EXIT job, the thread blocks
indefinitely. Will the DRM scheduler's GPU reset recovery path permanently
deadlock here if it needs to evict memory using xe_migrate_copy() or
xe_migrate_clear(), which also attempt to acquire m->job_mutex?

> +	dma_fence_put(fence);
> +
> +	m->ulls.enabled = false;
> +unlock_exit:
> +	if (job)
> +		xe_sched_job_put(job);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=19

Re: [PATCH v6 17/24] drm/xe: Add device flag to enable PT mirroring across tiles

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Unnecessary allocation of page table roots and scratch structures for secondary tiles when PT mirroring is disabled.
--

commit 34b539e899a7643dc15dedad6a3cd229e0c0f4d5
Author: Matthew Brost <matthew.brost@intel.com>

drm/xe: Add device flag to enable PT mirroring across tiles

This commit introduces a device flag to toggle page-table mirroring across
tiles for memory bandwidth considerations. It updates the VM creation,
rebind, and page table update paths to check this flag and fall back to the
primary tile's root page table when mirroring is disabled.

Link: https://patch.msgid.link/20260228013501.106680-18-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c

[ ... ]

> @@ -1738,7 +1748,8 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
>  
>  		for_each_tile(tile, xe, id) {
>  			if (flags & XE_VM_FLAG_MIGRATION &&
> -			    tile->id != XE_VM_FLAG_TILE_ID(flags))
> +			    tile->id != XE_VM_FLAG_TILE_ID(flags) &&
> +			    (vm->xe->info.has_pt_mirror || id))
>  				continue;
>  
>  			vm->pt_root[id] = xe_pt_create(vm, tile, xe->info.vm_max_level,

[Severity: Medium]
Does this code unnecessarily allocate page table roots and scratch structures
for secondary tiles when PT mirroring is disabled?

For standard user VMs, XE_VM_FLAG_MIGRATION is unset, meaning this if
condition evaluates to false and we proceed to allocate pt_root[id] for all
tiles. 

However, when vm->xe->info.has_pt_mirror is false, xe_vm_pt_root()
unconditionally returns pt_root[0]. This means the allocated pt_root[id] 
(and associated scratch page tables up to vm_max_level) for id > 0 will never
be used, permanently wasting VRAM for the lifetime of every VM.

Should there be an explicit check to skip secondary tile allocations when
has_pt_mirror is false, regardless of whether it is a migration VM?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=17

Re: [PATCH v6 13/24] drm/xe: Enable CPU binds for jobs

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Memory leak of `xe_pt_job_ops` and `job->fence` when PT jobs are aborted by the DRM scheduler.
--

commit 5533668320d4e1611a5ff8ddda82df8a65a1b27b
Author: Matthew Brost <matthew.brost@intel.com>

drm/xe: Enable CPU binds for jobs
    
This patch removes GPU-based binding and updates the migration layer to
formulate a PT job which will issue CPU bind in the submission backend. This
lowers latency and avoids running out of migration PTEs.

Link: https://patch.msgid.link/20260228013501.106680-14-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index ba8e195afcc89..e5c46e0fa9607 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
[ ... ]
> @@ -2104,6 +1889,12 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
>  	if (is_migrate)
>  		mutex_lock(&m->job_mutex);
>  
> +	job->pt_update[0].vm = pt_update->vops->vm;
> +	job->pt_update[0].tile = tile;
> +	job->pt_update[0].ops = ops;
> +	job->pt_update[0].pt_job_ops =
> +		xe_pt_job_ops_get(pt_update_ops->pt_job_ops);
> +
>  	xe_sched_job_arm(job);
>  	fence = dma_fence_get(&job->drm.s_fence->finished);
>  	xe_sched_job_push(job);

[Severity: Medium]
Are these references correctly released if the DRM scheduler aborts the job?

When a PT job is created and armed, pt_job_ops gets a reference here, and the
job's fence receives an extra reference. Normally, guc_exec_queue_run_job()
drops both of these references:

drivers/gpu/drm/xe/xe_guc_submit.c:guc_exec_queue_run_job() {
	if (is_pt_job(job)) {
		xe_pt_job_ops_put(job->pt_update[0].pt_job_ops);
		dma_fence_put(job->fence);	/* Drop ref from xe_sched_job_arm */
		return NULL;
	}
...
}

However, if the job is aborted (e.g., queue closed, wedging), run_job() is
bypassed and the scheduler calls xe_sched_job_destroy() instead. Looking at
xe_sched_job_destroy(), it only puts job->fence once and lacks a call to
xe_pt_job_ops_put() entirely:

drivers/gpu/drm/xe/xe_sched_job.c:xe_sched_job_destroy() {
...
	xe_sched_job_free_fences(job);
	dma_fence_put(job->fence);
	drm_sched_job_cleanup(&job->drm);
	job_free(job);
...
}

Does this permanently leak the pt_job_ops structure and the second fence
reference when PT jobs are aborted during error paths?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=13

Re: [PATCH v6 16/24] drm/xe: Add CPU bind layer

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

Pre-existing issues:
- [High] Concurrent RB-tree corruption in `xe_range_fence_insert()` during PREFETCH operations.
- [High] Memory leak of `pt_job_ops` and deferred page table BOs when a PT job is dropped by the DRM scheduler.
--

commit dab33f2788d31662c4784993dd54e7509cc455e6
Author: Matthew Brost <matthew.brost@intel.com>
drm/xe: Add CPU bind layer

This commit introduces a dedicated CPU bind layer at the device level,
decoupling it from the migrate layer. It updates the PT layer to generate
a single bind job when pages are mirrored across tiles. The patch includes
a significant refactor to ensure functional equivalence.

Link: https://patch.msgid.link/20260228013501.106680-17-matthew.brost@intel.com

> diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
> --- a/drivers/gpu/drm/xe/xe_sched_job.c
> +++ b/drivers/gpu/drm/xe/xe_sched_job.c
> @@ -73,8 +73,9 @@ static void job_free(struct xe_sched_job *job)
>  	struct xe_exec_queue *q = job->q;
>  	bool is_migration = xe_sched_job_is_migration(q);
>  
> -	kmem_cache_free(xe_exec_queue_is_parallel(job->q) || is_migration ?
> -			xe_sched_job_parallel_slab : xe_sched_job_slab, job);
> +	kmem_cache_free(job->is_pt_job || xe_exec_queue_is_parallel(job->q) ||
> +			is_migration ? xe_sched_job_parallel_slab :
> +			xe_sched_job_slab, job);
>  }

[Severity: High]
This is a pre-existing issue, but does dropping a PT job leak the pt_job_ops
and its deferred page table BOs?

When a page table update job is created (e.g. in
xe_cpu_bind_update_pgtables_job()), a reference to pt_job_ops is acquired via
xe_pt_job_ops_get(). This is normally released when the job executes in
guc_exec_queue_run_job().

However, if the execution queue is destroyed before execution, the DRM
scheduler aborts the job and calls the backend's .free_job callback
(guc_exec_queue_free_job()). That callback invokes job_free() which frees the
job memory, but fails to call xe_pt_job_ops_put() for PT jobs. This appears
to permanently leak the xe_pt_job_ops structure and the BOs it tracks.

> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
> --- a/drivers/gpu/drm/xe/xe_pt.c
> +++ b/drivers/gpu/drm/xe/xe_pt.c
[ ... ]
> @@ -2821,67 +2824,61 @@ xe_pt_update_ops_run(struct xe_tile *tile, struct xe_vma_ops *vops)
[ ... ]
> -	if (xe_range_fence_insert(&vm->rftree[tile->id], rfence,
> +	if (xe_range_fence_insert(&vm->rftree, rfence,
>  				  &xe_range_fence_kfree_ops,
> -				  pt_update_ops->start,
> -				  pt_update_ops->last, fence))
> +				  vops->start, vops->last, fence))

[Severity: High]
This isn't a bug introduced by this patch, but does xe_range_fence_insert()
have a concurrent RB-tree corruption risk here?

In xe_vm_bind_ioctl(), if an operation does not modify the GPU VA (such as
DRM_XE_VM_BIND_OP_PREFETCH on non-userptr memory),
XE_VMA_OPS_FLAG_DOWNGRADE_LOCK is set and vm->lock is downgraded to a read
lock (downgrade_write(&vm->lock)).

When multiple prefetch binds on the same VM execute concurrently, they will
reach xe_pt_update_ops_run() and unconditionally call xe_range_fence_insert()
to track the page table update. Since xe_range_fence_insert() modifies the
RB-tree directly without any internal synchronization, this concurrent access
under a read lock could lead to structural corruption of the shared
vm->rftree.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904211613.3934307-1-matthew.brost@intel.com?part=16

✓ Xe.CI.BAT: success for CPU binds and ULLS on migration queue (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1543 bytes --]

== Series Details ==

Series: CPU binds and ULLS on migration queue (rev8)
URL   : https://patchwork.freedesktop.org/series/149888/
State : success

== Summary ==

CI Bug Log - changes from xe-5694-313da1cc22491f07075c7ae36372343aa235d11e_BAT -> xe-pw-149888v8_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 11)
------------------------------

  Missing    (3): bat-nvls-2 bat-wcl-1 bat-ptl-vm 

Known issues
------------

  Here are the changes found in xe-pw-149888v8_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-nvls-1:         [PASS][1] -> [DMESG-WARN][2] ([Intel XE#8762] / [Intel XE#9069])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/bat-nvls-1/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/bat-nvls-1/igt@core_hotunplug@unbind-rebind.html

  
  [Intel XE#8762]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8762
  [Intel XE#9069]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9069


Build changes
-------------

  * Linux: xe-5694-313da1cc22491f07075c7ae36372343aa235d11e -> xe-pw-149888v8

  IGT_9084: 9084
  xe-5694-313da1cc22491f07075c7ae36372343aa235d11e: 313da1cc22491f07075c7ae36372343aa235d11e
  xe-pw-149888v8: 149888v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/index.html

[-- Attachment #2: Type: text/html, Size: 2101 bytes --]

✗ Xe.CI.FULL: failure for CPU binds and ULLS on migration queue (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 117341 bytes --]

== Series Details ==

Series: CPU binds and ULLS on migration queue (rev8)
URL   : https://patchwork.freedesktop.org/series/149888/
State : failure

== Summary ==

CI Bug Log - changes from xe-5694-313da1cc22491f07075c7ae36372343aa235d11e_FULL -> xe-pw-149888v8_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-149888v8_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-149888v8_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-149888v8_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_vm@bind-array-enobufs:
    - shard-bmg:          NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_vm@bind-array-enobufs.html

  
Known issues
------------

  Here are the changes found in xe-pw-149888v8_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@info:
    - shard-lnl:          [PASS][2] -> [SKIP][3] ([Intel XE#2134]) +1 other test skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@fbdev@info.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@fbdev@info.html

  * igt@intel_hwmon@hwmon-read:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#1125] / [Intel XE#7312])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-lnl:          NOTRUN -> [SKIP][5] ([Intel XE#3157])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2370]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-9/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#3658] / [Intel XE#7360]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#7059] / [Intel XE#7085])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1407]) +4 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#1124]) +2 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#1428] / [Intel XE#7387])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#1124]) +10 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#7679]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-target-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#367])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_bw@linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2887]) +4 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#3432])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#2887]) +13 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#2669] / [Intel XE#7389]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#7008])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_audio@hdmi-audio-after-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#2252])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_chamelium_audio@hdmi-audio-after-suspend.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#306] / [Intel XE#7358]) +2 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#7358])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_chamelium_color_pipeline@plane-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7358]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2252]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_chamelium_edid@hdmi-edid-change-during-hibernate.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#373]) +7 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#6507])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_color@ctm-0-75:
    - shard-lnl:          [PASS][27] -> [SKIP][28] ([Intel XE#3297]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_color@ctm-0-75.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_color@ctm-0-75.html

  * igt@kms_color@legacy-gamma:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#3297])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_color@legacy-gamma.html

  * igt@kms_color_pipeline@plane-lut1d-pre-ctm3x4:
    - shard-lnl:          [PASS][30] -> [SKIP][31] ([Intel XE#7006])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_color_pipeline@plane-lut1d-pre-ctm3x4.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_color_pipeline@plane-lut1d-pre-ctm3x4.html

  * igt@kms_content_protection@dp-mst-lic-type-0-hdcp14:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#6974])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2390] / [Intel XE#6974])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@uevent:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#7642]) +3 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-rapid-movement-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#1424]) +4 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_cursor_crc@cursor-rapid-movement-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#2321] / [Intel XE#7355])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2320]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-9/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#309] / [Intel XE#7343]) +5 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#1508])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_aux_dev@basic:
    - shard-lnl:          [PASS][40] -> [SKIP][41] ([Intel XE#3009])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_dp_aux_dev@basic.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_dp_aux_dev@basic.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#4354] / [Intel XE#5882])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#9009])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#4331] / [Intel XE#7227])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#8265])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#8265]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#4422] / [Intel XE#7442])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#4422] / [Intel XE#7442])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-9/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-lnl:          [PASS][49] -> [SKIP][50] ([Intel XE#9127])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_fbcon_fbt@fbc.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_fbcon_fbt@psr:
    - shard-lnl:          [PASS][51] -> [SKIP][52] ([Intel XE#8680])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_fbcon_fbt@psr.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@display-3x:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#703] / [Intel XE#7448])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#1138] / [Intel XE#7344])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#1137] / [Intel XE#2375])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-lnl:          [PASS][56] -> [SKIP][57] ([Intel XE#1135])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_feature_discovery@psr1.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#1421]) +4 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@absolute-wf_vblank-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#2482]) +3 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_flip@absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-wf_vblank-interruptible:
    - shard-lnl:          [PASS][60] -> [SKIP][61] ([Intel XE#2482]) +9 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_flip@flip-vs-wf_vblank-interruptible.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_flip@flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385] / [Intel XE#9144])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#1397] / [Intel XE#7385] / [Intel XE#9144])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling:
    - shard-lnl:          [PASS][64] -> [SKIP][65] ([Intel XE#1745] / [Intel XE#9144]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#7178] / [Intel XE#7351]) +5 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#7178] / [Intel XE#7349])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_tiling@flip-change-tiling:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#2682])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_flip_tiling@flip-change-tiling.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#352])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@drrshdr-abgr161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#7779]) +27 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@drrshdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#4141]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#656] / [Intel XE#7905]) +39 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#6312]) +11 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#6312] / [Intel XE#651]) +13 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#1469] / [Intel XE#7399])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#2311]) +12 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#7905]) +42 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#7061])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#2313]) +15 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#7865]) +24 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#7061]) +5 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-render:
    - shard-lnl:          [PASS][82] -> [SKIP][83] ([Intel XE#7779]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-render.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
    - shard-lnl:          [PASS][84] -> [SKIP][85] ([Intel XE#2548] / [Intel XE#7779]) +18 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#7061] / [Intel XE#7356]) +3 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#2548] / [Intel XE#7779]) +14 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html

  * igt@kms_hdmi_inject@inject-4k:
    - shard-lnl:          NOTRUN -> [SKIP][88] ([Intel XE#1470])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_hdmi_inject@inject-4k.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][89] -> [SKIP][90] ([Intel XE#1503])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-9/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][91] ([Intel XE#1503])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_invalid_mode@bad-hsync-start:
    - shard-lnl:          [PASS][92] -> [SKIP][93] ([Intel XE#2568]) +3 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_invalid_mode@bad-hsync-start.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_invalid_mode@bad-hsync-start.html

  * igt@kms_invalid_mode@bad-vsync-start:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#2568])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_invalid_mode@bad-vsync-start.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#6900] / [Intel XE#7362])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#4298] / [Intel XE#5873])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_mst@mst-suspend-read-crc:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#8348])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_mst@mst-suspend-read-crc.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#4329] / [Intel XE#6912] / [Intel XE#7375])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@pixel-format-linear-modifier-source-clamping:
    - shard-lnl:          [PASS][99] -> [SKIP][100] ([Intel XE#7250] / [Intel XE#9128])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_plane@pixel-format-linear-modifier-source-clamping.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane@pixel-format-linear-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#8303]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_plane@pixel-format-x-tiled-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][102] ([Intel XE#7283]) +5 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping.html

  * igt@kms_plane@plane-position-hole:
    - shard-lnl:          [PASS][103] -> [SKIP][104] ([Intel XE#9128])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_plane@plane-position-hole.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane@plane-position-hole.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][105] ([Intel XE#599])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][106] ([Intel XE#4596] / [Intel XE#5854])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][107] ([Intel XE#5020] / [Intel XE#7348])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-modifiers:
    - shard-lnl:          [PASS][108] -> [SKIP][109] ([Intel XE#2763] / [Intel XE#6886] / [Intel XE#7687] / [Intel XE#9125]) +5 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-modifiers.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-modifiers.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers:
    - shard-lnl:          NOTRUN -> [SKIP][110] ([Intel XE#2763] / [Intel XE#6886] / [Intel XE#7687] / [Intel XE#9125]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-modifiers@pipe-a:
    - shard-lnl:          [PASS][111] -> [SKIP][112] ([Intel XE#2763] / [Intel XE#6886]) +5 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-modifiers@pipe-a.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-modifiers@pipe-a.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][113] ([Intel XE#2763] / [Intel XE#6886]) +7 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-lnl:          [PASS][114] -> [SKIP][115] ([Intel XE#870]) +2 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_pm_backlight@basic-brightness.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_dc@dc3co-after-dc6:
    - shard-bmg:          NOTRUN -> [SKIP][116] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_pm_dc@dc3co-after-dc6.html

  * igt@kms_pm_dc@dc3co-after-dc6@psr2-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][117] ([Intel XE#8396]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_pm_dc@dc3co-after-dc6@psr2-xrgb8888.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          NOTRUN -> [FAIL][118] ([Intel XE#8399])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_pm_dc@dc5-dpms.html

  * igt@kms_pm_dc@dc5-dpms-negative:
    - shard-lnl:          NOTRUN -> [SKIP][119] ([Intel XE#1131])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_pm_dc@dc5-dpms-negative.html

  * igt@kms_pm_dc@dc5-psr-suspend-resume:
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#8854])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_pm_dc@dc5-psr-suspend-resume.html

  * igt@kms_pm_rpm@legacy-planes:
    - shard-lnl:          [PASS][121] -> [SKIP][122] ([Intel XE#4886]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_pm_rpm@legacy-planes.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_pm_rpm@legacy-planes.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-lnl:          [PASS][123] -> [SKIP][124] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_pm_rpm@modeset-lpsp.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-stress-extra-wait:
    - shard-lnl:          [PASS][125] -> [SKIP][126] ([Intel XE#1439] / [Intel XE#836])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_pm_rpm@modeset-stress-extra-wait.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_pm_rpm@modeset-stress-extra-wait.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][127] ([Intel XE#2893] / [Intel XE#7304]) +3 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][128] ([Intel XE#4608]) +2 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][129] ([Intel XE#4608] / [Intel XE#7304]) +2 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][130] ([Intel XE#1489]) +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          NOTRUN -> [SKIP][131] ([Intel XE#1489]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf:
    - shard-lnl:          [PASS][132] -> [SKIP][133] ([Intel XE#1489]) +1 other test skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-lnl:          NOTRUN -> [SKIP][134] ([Intel XE#1128] / [Intel XE#7413]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-cursor-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][135] ([Intel XE#1406] / [Intel XE#7345]) +2 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_psr@fbc-psr2-cursor-plane-onoff.html

  * igt@kms_psr@fbc-psr2-no-drrs@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][136] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345]) +3 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_psr@fbc-psr2-no-drrs@edp-1.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-lnl:          NOTRUN -> [SKIP][137] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@pr-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][138] ([Intel XE#1406])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_psr@pr-dpms.html

  * igt@kms_psr@psr2-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][139] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_psr@psr2-no-drrs.html

  * igt@kms_psr@psr2-sprite-plane-onoff:
    - shard-lnl:          [PASS][140] -> [SKIP][141] ([Intel XE#2850] / [Intel XE#929]) +8 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_psr@psr2-sprite-plane-onoff.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_psr@psr2-sprite-plane-onoff.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-lnl:          NOTRUN -> [SKIP][142] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-lnl:          NOTRUN -> [SKIP][143] ([Intel XE#1435] / [Intel XE#9142])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-lnl:          NOTRUN -> [SKIP][144] ([Intel XE#362] / [Intel XE#5848])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-lnl:          NOTRUN -> [SKIP][145] ([Intel XE#330] / [Intel XE#5857])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vblank@query-forked:
    - shard-lnl:          [PASS][146] -> [SKIP][147] ([Intel XE#9125]) +65 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_vblank@query-forked.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_vblank@query-forked.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-bmg:          NOTRUN -> [SKIP][148] ([Intel XE#1499]) +1 other test skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@lobf:
    - shard-lnl:          NOTRUN -> [SKIP][149] ([Intel XE#1499])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_vrr@lobf.html

  * igt@kms_vrr@lobf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][150] ([Intel XE#7638])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@kms_vrr@lobf@pipe-a-edp-1.html

  * igt@kms_vrr@negative-basic:
    - shard-lnl:          NOTRUN -> [SKIP][151] ([Intel XE#9125]) +26 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_vrr@negative-basic.html

  * igt@xe_ccs@vm-bind-decompress:
    - shard-lnl:          NOTRUN -> [SKIP][152] ([Intel XE#7644])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_ccs@vm-bind-decompress.html

  * igt@xe_evict@evict-beng-cm-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][153] ([Intel XE#6540] / [Intel XE#688]) +10 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_evict@evict-beng-cm-threads-small-multi-vm.html

  * igt@xe_evict@evict-small-external-multi-queue:
    - shard-bmg:          NOTRUN -> [SKIP][154] ([Intel XE#8370])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_evict@evict-small-external-multi-queue.html

  * igt@xe_exec_balancer@no-exec-cm-parallel-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][155] ([Intel XE#7482]) +24 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@xe_exec_balancer@no-exec-cm-parallel-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][156] ([Intel XE#2322] / [Intel XE#7372])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][157] ([Intel XE#1392]) +8 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate.html

  * igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-imm:
    - shard-bmg:          NOTRUN -> [SKIP][158] ([Intel XE#8374]) +2 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_exec_fault_mode@once-multi-queue-userptr-invalidate-race-imm.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm:
    - shard-lnl:          NOTRUN -> [SKIP][159] ([Intel XE#8374]) +17 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html

  * igt@xe_exec_multi_queue@many-queues-basic:
    - shard-bmg:          NOTRUN -> [SKIP][160] ([Intel XE#8364]) +8 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-basic.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][161] ([Intel XE#8364]) +37 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_reset@multi-queue-gt-reset:
    - shard-lnl:          NOTRUN -> [SKIP][162] ([Intel XE#8369]) +2 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@xe_exec_reset@multi-queue-gt-reset.html

  * igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race:
    - shard-bmg:          [PASS][163] -> [FAIL][164] ([Intel XE#9096])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-bmg-7/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-10/igt@xe_exec_threads@threads-hang-fd-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][165] ([Intel XE#8378]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][166] ([Intel XE#8378]) +12 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-rebind.html

  * igt@xe_gpgpu_fill@offset-4x4:
    - shard-bmg:          NOTRUN -> [SKIP][167] ([Intel XE#7954])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_gpgpu_fill@offset-4x4.html

  * igt@xe_madvise@atomic-global:
    - shard-lnl:          NOTRUN -> [SKIP][168] ([Intel XE#7980]) +1 other test skip
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_madvise@atomic-global.html

  * igt@xe_mmap@pci-membarrier-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][169] ([Intel XE#5100] / [Intel XE#7322] / [Intel XE#7408])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_mmap@pci-membarrier-parallel.html

  * igt@xe_module_load@load:
    - shard-lnl:          ([PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181], [PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186], [PASS][187], [PASS][188], [PASS][189], [PASS][190]) -> ([PASS][191], [PASS][192], [PASS][193], [PASS][194], [PASS][195], [PASS][196], [PASS][197], [PASS][198], [PASS][199], [PASS][200], [PASS][201], [SKIP][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [PASS][209], [PASS][210]) ([Intel XE#378] / [Intel XE#7405])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@xe_module_load@load.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@xe_module_load@load.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@xe_module_load@load.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-2/igt@xe_module_load@load.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@xe_module_load@load.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-4/igt@xe_module_load@load.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@xe_module_load@load.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@xe_module_load@load.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@xe_module_load@load.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-4/igt@xe_module_load@load.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@xe_module_load@load.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-2/igt@xe_module_load@load.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@xe_module_load@load.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@xe_module_load@load.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@xe_module_load@load.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@xe_module_load@load.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@xe_module_load@load.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@xe_module_load@load.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@xe_module_load@load.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-4/igt@xe_module_load@load.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@xe_module_load@load.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@xe_module_load@load.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@xe_module_load@load.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_module_load@load.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_module_load@load.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-5/igt@xe_module_load@load.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-3/igt@xe_module_load@load.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-3/igt@xe_module_load@load.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-5/igt@xe_module_load@load.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-5/igt@xe_module_load@load.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_module_load@load.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@xe_module_load@load.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@xe_module_load@load.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_module_load@load.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_module_load@load.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_module_load@load.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_module_load@load.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@xe_module_load@load.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@xe_module_load@load.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@xe_module_load@load.html

  * igt@xe_multigpu_svm@mgpu-migration-basic:
    - shard-lnl:          NOTRUN -> [SKIP][211] ([Intel XE#6964]) +3 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_multigpu_svm@mgpu-migration-basic.html

  * igt@xe_page_reclaim@pat-index-xd:
    - shard-bmg:          NOTRUN -> [SKIP][212] ([Intel XE#7793])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_page_reclaim@pat-index-xd.html

  * igt@xe_page_reclaim@prl-invalidate-full:
    - shard-lnl:          NOTRUN -> [SKIP][213] ([Intel XE#7793]) +2 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_page_reclaim@prl-invalidate-full.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-lnl:          [PASS][214] -> [SKIP][215] ([Intel XE#7590] / [Intel XE#9125])
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@xe_pat@display-vs-wb-transient.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pat@pat-sw-hw-compare:
    - shard-lnl:          NOTRUN -> [FAIL][216] ([Intel XE#7695])
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_pat@pat-sw-hw-compare.html

  * igt@xe_pat@xa-app-transient-media-on:
    - shard-bmg:          NOTRUN -> [SKIP][217] ([Intel XE#7590])
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_pat@xa-app-transient-media-on.html

  * igt@xe_peer2peer@write:
    - shard-lnl:          NOTRUN -> [SKIP][218] ([Intel XE#1061] / [Intel XE#7326] / [Intel XE#7353])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_peer2peer@write.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-lnl:          NOTRUN -> [SKIP][219] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370]) +1 other test skip
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@s3-vm-bind-unbind-all:
    - shard-lnl:          NOTRUN -> [SKIP][220] ([Intel XE#584] / [Intel XE#7369]) +1 other test skip
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@xe_pm@s3-vm-bind-unbind-all.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-lnl:          NOTRUN -> [SKIP][221] ([Intel XE#579] / [Intel XE#7329] / [Intel XE#7456])
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_prefetch_fault@l2-prefetch-fault:
    - shard-lnl:          NOTRUN -> [SKIP][222] ([Intel XE#8815])
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_prefetch_fault@l2-prefetch-fault.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][223] ([Intel XE#7599]) +1 other test skip
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][224] ([Intel XE#4733] / [Intel XE#7417])
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-9/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html

  * igt@xe_query@multigpu-query-topology-l3-bank-mask:
    - shard-lnl:          NOTRUN -> [SKIP][225] ([Intel XE#944]) +3 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_query@multigpu-query-topology-l3-bank-mask.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-bmg:          NOTRUN -> [SKIP][226] ([Intel XE#944])
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_sriov_admin@default-sched-attributes-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][227] ([Intel XE#7174])
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@xe_sriov_admin@default-sched-attributes-vfs-disabled.html

  * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs:
    - shard-lnl:          NOTRUN -> [SKIP][228] ([Intel XE#4130] / [Intel XE#7366])
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-lnl:          NOTRUN -> [SKIP][229] ([Intel XE#3342])
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_sriov_scheduling@equal-throughput-low-priority:
    - shard-lnl:          NOTRUN -> [SKIP][230] ([Intel XE#8339])
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_sriov_scheduling@equal-throughput-low-priority.html

  * igt@xe_wedged@wedged-at-any-timeout:
    - shard-lnl:          NOTRUN -> [DMESG-WARN][231] ([Intel XE#8963])
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-2/igt@xe_wedged@wedged-at-any-timeout.html

  
#### Possible fixes ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][232] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][233] +1 other test pass
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_color@deep-color:
    - shard-lnl:          [SKIP][234] ([Intel XE#1511] / [Intel XE#3297]) -> [PASS][235]
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_color@deep-color.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_color@deep-color.html

  * igt@kms_color@legacy-gamma-reset:
    - shard-lnl:          [SKIP][236] ([Intel XE#3297]) -> [PASS][237]
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_color@legacy-gamma-reset.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_color@legacy-gamma-reset.html

  * igt@kms_color_pipeline@plane-ctm3x4:
    - shard-lnl:          [SKIP][238] ([Intel XE#7006]) -> [PASS][239]
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_color_pipeline@plane-ctm3x4.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_color_pipeline@plane-ctm3x4.html

  * igt@kms_cursor_crc@cursor-tearing-position-change:
    - shard-lnl:          [SKIP][240] ([Intel XE#9125]) -> [PASS][241] +39 other tests pass
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_cursor_crc@cursor-tearing-position-change.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_cursor_crc@cursor-tearing-position-change.html

  * igt@kms_fb_coherency@memset-crc:
    - shard-lnl:          [SKIP][242] -> [PASS][243]
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_fb_coherency@memset-crc.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_fb_coherency@memset-crc.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - shard-lnl:          [SKIP][244] ([Intel XE#2482]) -> [PASS][245]
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_flip@basic-flip-vs-modeset.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_flip@basic-flip-vs-modeset.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling:
    - shard-lnl:          [SKIP][246] ([Intel XE#1745] / [Intel XE#9144]) -> [PASS][247] +1 other test pass
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-render:
    - shard-lnl:          [SKIP][248] ([Intel XE#7779]) -> [PASS][249] +1 other test pass
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-render.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-lnl:          [SKIP][250] ([Intel XE#2548] / [Intel XE#7779]) -> [PASS][251] +13 other tests pass
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_invalid_mode@bad-vsync-end:
    - shard-lnl:          [SKIP][252] ([Intel XE#2568]) -> [PASS][253]
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_invalid_mode@bad-vsync-end.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_invalid_mode@bad-vsync-end.html

  * igt@kms_plane@planar-pixel-format-settings:
    - shard-lnl:          [SKIP][254] ([Intel XE#7780] / [Intel XE#9125]) -> [PASS][255]
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_plane@planar-pixel-format-settings.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_plane@planar-pixel-format-settings.html

  * igt@kms_plane@plane-position-covered:
    - shard-lnl:          [SKIP][256] ([Intel XE#9128]) -> [PASS][257] +1 other test pass
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_plane@plane-position-covered.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_plane@plane-position-covered.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a:
    - shard-lnl:          [SKIP][258] ([Intel XE#2763] / [Intel XE#6886]) -> [PASS][259] +7 other tests pass
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25:
    - shard-lnl:          [SKIP][260] ([Intel XE#2763] / [Intel XE#6886] / [Intel XE#7687] / [Intel XE#9125]) -> [PASS][261] +7 other tests pass
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_plane_scaling@planes-upscale-factor-0-25.html

  * igt@kms_pm_dc@dc5-pageflip-negative:
    - shard-lnl:          [SKIP][262] ([Intel XE#6927] / [Intel XE#8854]) -> [PASS][263]
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_pm_dc@dc5-pageflip-negative.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_pm_dc@dc5-pageflip-negative.html

  * igt@kms_pm_rpm@drm-resources-equal:
    - shard-lnl:          [SKIP][264] ([Intel XE#7106]) -> [PASS][265]
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_pm_rpm@drm-resources-equal.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_pm_rpm@drm-resources-equal.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-lnl:          [SKIP][266] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836]) -> [PASS][267]
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          [SKIP][268] ([Intel XE#1489]) -> [PASS][269]
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@psr-dpms:
    - shard-lnl:          [SKIP][270] ([Intel XE#2850] / [Intel XE#929]) -> [PASS][271] +3 other tests pass
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_psr@psr-dpms.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_psr@psr-dpms.html

  * igt@xe_configfs@gt-types-allowed:
    - shard-bmg:          [ABORT][272] ([Intel XE#8007]) -> [PASS][273]
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-bmg-4/igt@xe_configfs@gt-types-allowed.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_configfs@gt-types-allowed.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][274] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][275]
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-6/igt@xe_evict@evict-mixed-many-threads-small.html

  
#### Warnings ####

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-lnl:          [SKIP][276] ([Intel XE#9125]) -> [SKIP][277] ([Intel XE#3279])
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_atomic_transition@plane-all-modeset-transition.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          [SKIP][278] ([Intel XE#9125]) -> [SKIP][279] ([Intel XE#1407]) +4 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-lnl:          [SKIP][280] ([Intel XE#9125]) -> [SKIP][281] ([Intel XE#7059] / [Intel XE#7085])
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-lnl:          [SKIP][282] ([Intel XE#1407]) -> [SKIP][283] ([Intel XE#9125]) +3 other tests skip
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-lnl:          [SKIP][284] ([Intel XE#1477] / [Intel XE#7361]) -> [SKIP][285] ([Intel XE#9125])
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-lnl:          [SKIP][286] ([Intel XE#9125]) -> [SKIP][287] ([Intel XE#1124]) +7 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-lnl:          [SKIP][288] ([Intel XE#1124]) -> [SKIP][289] ([Intel XE#9125]) +10 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-lnl:          [SKIP][290] ([Intel XE#9125]) -> [SKIP][291] ([Intel XE#1467] / [Intel XE#7367])
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_big_fb@yf-tiled-addfb.html
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p:
    - shard-lnl:          [SKIP][292] ([Intel XE#9125]) -> [SKIP][293] ([Intel XE#7679])
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p.html
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-3840x2160p:
    - shard-lnl:          [SKIP][294] ([Intel XE#7679]) -> [SKIP][295] ([Intel XE#9125]) +1 other test skip
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_bw@connected-linear-tiling-3-displays-target-3840x2160p.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_bw@connected-linear-tiling-3-displays-target-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p:
    - shard-lnl:          [SKIP][296] ([Intel XE#9125]) -> [SKIP][297] ([Intel XE#8365])
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p.html
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p:
    - shard-lnl:          [SKIP][298] ([Intel XE#8365]) -> [SKIP][299] ([Intel XE#9125])
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-target-1920x1080p:
    - shard-lnl:          [SKIP][300] ([Intel XE#9125]) -> [SKIP][301] ([Intel XE#367]) +1 other test skip
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_bw@linear-tiling-2-displays-target-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-target-2160x1440p:
    - shard-lnl:          [SKIP][302] ([Intel XE#367]) -> [SKIP][303] ([Intel XE#9125])
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_bw@linear-tiling-3-displays-target-2160x1440p.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_bw@linear-tiling-3-displays-target-2160x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          [SKIP][304] ([Intel XE#9125]) -> [SKIP][305] ([Intel XE#2887]) +11 other tests skip
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          [SKIP][306] ([Intel XE#2887]) -> [SKIP][307] ([Intel XE#9125]) +15 other tests skip
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc.html
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-lnl:          [SKIP][308] ([Intel XE#2669] / [Intel XE#7389]) -> [SKIP][309] ([Intel XE#9125])
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs:
    - shard-lnl:          [SKIP][310] ([Intel XE#9125]) -> [SKIP][311] ([Intel XE#3432])
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs.html
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
    - shard-lnl:          [SKIP][312] ([Intel XE#3432]) -> [SKIP][313] ([Intel XE#9125])
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-lnl:          [SKIP][314] ([Intel XE#9125]) -> [SKIP][315] ([Intel XE#2669] / [Intel XE#7389])
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-lnl:          [SKIP][316] ([Intel XE#4417] / [Intel XE#5447]) -> [SKIP][317] ([Intel XE#9125])
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_cdclk@mode-transition.html
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_cdclk@mode-transition.html

  * igt@kms_content_protection@suspend-resume:
    - shard-lnl:          [SKIP][318] ([Intel XE#7642]) -> [SKIP][319] ([Intel XE#9125]) +3 other tests skip
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_content_protection@suspend-resume.html
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_content_protection@suspend-resume.html

  * igt@kms_content_protection@type1:
    - shard-lnl:          [SKIP][320] ([Intel XE#9125]) -> [SKIP][321] ([Intel XE#7642]) +1 other test skip
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_content_protection@type1.html
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-lnl:          [SKIP][322] ([Intel XE#2321] / [Intel XE#7355]) -> [SKIP][323] ([Intel XE#9125])
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-lnl:          [SKIP][324] ([Intel XE#9125]) -> [SKIP][325] ([Intel XE#2321] / [Intel XE#7355]) +1 other test skip
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_cursor_crc@cursor-onscreen-512x512.html
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-256x85:
    - shard-lnl:          [SKIP][326] ([Intel XE#9125]) -> [SKIP][327] ([Intel XE#1424])
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-lnl:          [SKIP][328] ([Intel XE#1424]) -> [SKIP][329] ([Intel XE#9125]) +5 other tests skip
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_cursor_crc@cursor-sliding-32x10.html
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-lnl:          [SKIP][330] ([Intel XE#9125]) -> [SKIP][331] ([Intel XE#309] / [Intel XE#7343]) +3 other tests skip
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-lnl:          [SKIP][332] ([Intel XE#309] / [Intel XE#7343]) -> [SKIP][333] ([Intel XE#9125]) +4 other tests skip
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-lnl:          [SKIP][334] ([Intel XE#323] / [Intel XE#6035]) -> [SKIP][335] ([Intel XE#9125])
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-lnl:          [SKIP][336] ([Intel XE#9125]) -> [SKIP][337] ([Intel XE#323] / [Intel XE#6035])
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-lnl:          [SKIP][338] ([Intel XE#4302]) -> [SKIP][339] ([Intel XE#9125])
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_display_modes@extended-mode-basic.html
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-lnl:          [SKIP][340] ([Intel XE#9125]) -> [SKIP][341] ([Intel XE#4354] / [Intel XE#7386])
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_dp_link_training@uhbr-mst.html
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-lnl:          [SKIP][342] ([Intel XE#4354] / [Intel XE#5870]) -> [SKIP][343] ([Intel XE#9125])
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_dp_link_training@uhbr-sst.html
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-lnl:          [SKIP][344] ([Intel XE#8265]) -> [SKIP][345] ([Intel XE#9125]) +5 other tests skip
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_dsc@dsc-with-bpc.html
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner:
    - shard-lnl:          [SKIP][346] ([Intel XE#9125]) -> [SKIP][347] ([Intel XE#8265]) +2 other tests skip
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner.html
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area:
    - shard-lnl:          [SKIP][348] ([Intel XE#4422] / [Intel XE#7442]) -> [SKIP][349] ([Intel XE#9125])
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-out-visible-area.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-lnl:          [SKIP][350] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385] / [Intel XE#9144]) -> [SKIP][351] ([Intel XE#1745] / [Intel XE#9144]) +1 other test skip
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          [SKIP][352] ([Intel XE#7779]) -> [SKIP][353] ([Intel XE#6312]) +7 other tests skip
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc.html
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render:
    - shard-lnl:          [SKIP][354] ([Intel XE#6312] / [Intel XE#651]) -> [SKIP][355] ([Intel XE#2548] / [Intel XE#7779]) +15 other tests skip
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render.html
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrshdr-rgb101010-draw-render:
    - shard-lnl:          [SKIP][356] ([Intel XE#6312]) -> [SKIP][357] ([Intel XE#7779]) +16 other tests skip
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_frontbuffer_tracking@drrshdr-rgb101010-draw-render.html
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@drrshdr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          [SKIP][358] ([Intel XE#656] / [Intel XE#7905]) -> [SKIP][359] ([Intel XE#2548] / [Intel XE#7779]) +39 other tests skip
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          [SKIP][360] ([Intel XE#2548] / [Intel XE#7779]) -> [SKIP][361] ([Intel XE#656] / [Intel XE#7905]) +30 other tests skip
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt:
    - shard-lnl:          [SKIP][362] ([Intel XE#7061] / [Intel XE#7356]) -> [SKIP][363] ([Intel XE#7779]) +4 other tests skip
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt.html
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render:
    - shard-lnl:          [SKIP][364] ([Intel XE#7779]) -> [SKIP][365] ([Intel XE#7061] / [Intel XE#7356]) +4 other tests skip
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy:
    - shard-lnl:          [SKIP][366] ([Intel XE#2548] / [Intel XE#7779]) -> [SKIP][367] ([Intel XE#6312] / [Intel XE#651]) +10 other tests skip
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy.html
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc:
    - shard-lnl:          [SKIP][368] ([Intel XE#7061]) -> [SKIP][369] ([Intel XE#7779]) +2 other tests skip
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc.html
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-tiling-y:
    - shard-lnl:          [SKIP][370] ([Intel XE#7399]) -> [SKIP][371] ([Intel XE#7779])
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-7/igt@kms_frontbuffer_tracking@fbchdr-tiling-y.html
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@fbchdr-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-lnl:          [SKIP][372] ([Intel XE#7779]) -> [SKIP][373] ([Intel XE#7865]) +24 other tests skip
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-mmap-wc.html
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-rte:
    - shard-lnl:          [SKIP][374] ([Intel XE#7905]) -> [SKIP][375] ([Intel XE#7779]) +61 other tests skip
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-rte.html
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff:
    - shard-lnl:          [SKIP][376] ([Intel XE#7779]) -> [SKIP][377] ([Intel XE#7905]) +31 other tests skip
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff.html
   [377]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-plflip-blt:
    - shard-lnl:          [SKIP][378] ([Intel XE#7865]) -> [SKIP][379] ([Intel XE#7779]) +29 other tests skip
   [378]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-plflip-blt.html
   [379]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-blt:
    - shard-lnl:          [SKIP][380] ([Intel XE#7779]) -> [SKIP][381] ([Intel XE#7061]) +3 other tests skip
   [380]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-blt.html
   [381]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-4/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][382] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][383] ([Intel XE#3544])
   [382]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
   [383]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-10/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@static-swap:
    - shard-lnl:          [SKIP][384] ([Intel XE#1503]) -> [SKIP][385] ([Intel XE#9125])
   [384]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_hdr@static-swap.html
   [385]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_hdr@static-swap.html

  * igt@kms_plane_lowres@tiling-4:
    - shard-lnl:          [SKIP][386] ([Intel XE#599] / [Intel XE#7382]) -> [SKIP][387] ([Intel XE#9125])
   [386]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_plane_lowres@tiling-4.html
   [387]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane_lowres@tiling-4.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-lnl:          [SKIP][388] ([Intel XE#599]) -> [SKIP][389] ([Intel XE#9125])
   [388]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_plane_lowres@tiling-yf.html
   [389]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-lnl:          [SKIP][390] ([Intel XE#4596] / [Intel XE#5854]) -> [SKIP][391] ([Intel XE#9125]) +1 other test skip
   [390]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_plane_multiple@2x-tiling-none.html
   [391]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-lnl:          [SKIP][392] ([Intel XE#3307]) -> [SKIP][393] ([Intel XE#3307] / [Intel XE#7687] / [Intel XE#9125])
   [392]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_plane_scaling@intel-max-src-size.html
   [393]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c:
    - shard-lnl:          [SKIP][394] ([Intel XE#2763] / [Intel XE#6886]) -> [SKIP][395] ([Intel XE#2763] / [Intel XE#6886] / [Intel XE#7687] / [Intel XE#9125]) +5 other tests skip
   [394]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c.html
   [395]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          [SKIP][396] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304]) -> [SKIP][397] ([Intel XE#1489]) +2 other tests skip
   [396]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html
   [397]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-lnl:          [SKIP][398] ([Intel XE#1489]) -> [SKIP][399] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304]) +2 other tests skip
   [398]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
   [399]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
    - shard-lnl:          [SKIP][400] ([Intel XE#1489]) -> [SKIP][401] ([Intel XE#2893] / [Intel XE#7304]) +1 other test skip
   [400]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
   [401]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-lnl:          [SKIP][402] ([Intel XE#2893] / [Intel XE#7304]) -> [SKIP][403] ([Intel XE#1489]) +3 other tests skip
   [402]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html
   [403]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr@fbc-psr2-primary-blt:
    - shard-lnl:          [SKIP][404] ([Intel XE#1406] / [Intel XE#7345]) -> [SKIP][405] ([Intel XE#2850] / [Intel XE#929]) +3 other tests skip
   [404]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_psr@fbc-psr2-primary-blt.html
   [405]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_psr@fbc-psr2-primary-blt.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-lnl:          [SKIP][406] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][407] ([Intel XE#1406] / [Intel XE#7345])
   [406]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_psr@fbc-psr2-sprite-render.html
   [407]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@pr-primary-blt:
    - shard-lnl:          [SKIP][408] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][409] ([Intel XE#1406]) +4 other tests skip
   [408]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_psr@pr-primary-blt.html
   [409]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_psr@pr-primary-blt.html

  * igt@kms_psr@pr-sprite-blt:
    - shard-lnl:          [SKIP][410] ([Intel XE#1406]) -> [SKIP][411] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [410]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_psr@pr-sprite-blt.html
   [411]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_psr@pr-sprite-blt.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-lnl:          [SKIP][412] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) -> [SKIP][413] ([Intel XE#9125]) +1 other test skip
   [412]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
   [413]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-lnl:          [SKIP][414] ([Intel XE#9125]) -> [SKIP][415] ([Intel XE#1127] / [Intel XE#5813])
   [414]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [415]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-lnl:          [SKIP][416] ([Intel XE#1127] / [Intel XE#5813]) -> [SKIP][417] ([Intel XE#9125])
   [416]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
   [417]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-lnl:          [SKIP][418] ([Intel XE#9125]) -> [SKIP][419] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [418]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-6/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
   [419]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-7/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][420] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][421] ([Intel XE#2509] / [Intel XE#7437])
   [420]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [421]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@lobf-dc3co:
    - shard-lnl:          [SKIP][422] ([Intel XE#8397]) -> [SKIP][423] ([Intel XE#9125])
   [422]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-5/igt@kms_vrr@lobf-dc3co.html
   [423]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@kms_vrr@lobf-dc3co.html

  * igt@xe_exec_reset@gt-reset-fault-injection:
    - shard-bmg:          [DMESG-WARN][424] ([Intel XE#9130]) -> [ABORT][425] ([Intel XE#9131] / [Intel XE#9145])
   [424]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-bmg-5/igt@xe_exec_reset@gt-reset-fault-injection.html
   [425]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-bmg-2/igt@xe_exec_reset@gt-reset-fault-injection.html
    - shard-lnl:          [ABORT][426] ([Intel XE#9140] / [Intel XE#9145]) -> [DMESG-WARN][427] ([Intel XE#9130])
   [426]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-1/igt@xe_exec_reset@gt-reset-fault-injection.html
   [427]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-1/igt@xe_exec_reset@gt-reset-fault-injection.html

  * igt@xe_wedged@basic-wedged:
    - shard-lnl:          [DMESG-WARN][428] ([Intel XE#8963]) -> [ABORT][429] ([Intel XE#8963])
   [428]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5694-313da1cc22491f07075c7ae36372343aa235d11e/shard-lnl-3/igt@xe_wedged@basic-wedged.html
   [429]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/shard-lnl-6/igt@xe_wedged@basic-wedged.html

  
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1131
  [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1511]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1511
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2375
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2482
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2548]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2548
  [Intel XE#2568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2568
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2682]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2682
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
  [Intel XE#3297]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3297
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3307
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4886
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5447
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
  [Intel XE#5870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5870
  [Intel XE#5873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5873
  [Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6927
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
  [Intel XE#7008]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7008
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7106]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7106
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7227
  [Intel XE#7250]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7250
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7312
  [Intel XE#7322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7322
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7329
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7348
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
  [Intel XE#7362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7362
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7367
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
  [Intel XE#7382]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7382
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7386]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7386
  [Intel XE#7387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7387
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7448]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7448
  [Intel XE#7456]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7456
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7638]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7638
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7687]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7687
  [Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
  [Intel XE#7779]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7779
  [Intel XE#7780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7780
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7954]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7954
  [Intel XE#7980]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7980
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8303]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8303
  [Intel XE#8339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8339
  [Intel XE#8348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8348
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8365
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8397
  [Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
  [Intel XE#8680]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8680
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8815]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8815
  [Intel XE#8854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8854
  [Intel XE#8963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8963
  [Intel XE#9009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9009
  [Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
  [Intel XE#9125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9125
  [Intel XE#9127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9127
  [Intel XE#9128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9128
  [Intel XE#9130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9130
  [Intel XE#9131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9131
  [Intel XE#9140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9140
  [Intel XE#9142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9142
  [Intel XE#9144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9144
  [Intel XE#9145]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9145
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5694-313da1cc22491f07075c7ae36372343aa235d11e -> xe-pw-149888v8

  IGT_9084: 9084
  xe-5694-313da1cc22491f07075c7ae36372343aa235d11e: 313da1cc22491f07075c7ae36372343aa235d11e
  xe-pw-149888v8: 149888v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-149888v8/index.html

[-- Attachment #2: Type: text/html, Size: 143673 bytes --]

Re: [PATCH v6 23/24] drm/xe: Add modparam to enable / disable ULLS on migrate queue

[Thomas Hellström]

On Fri, 2026-09-04 at 14:16 -0700, Matthew Brost wrote:
> Having modparam to enable / disable ULLS on migrate queue will help
> with
> quick experiments.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Link:
> https://patch.msgid.link/20260228013501.106680-26-matthew.brost@intel.com
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/xe/xe_debugfs.c      | 1 +
>  drivers/gpu/drm/xe/xe_defaults.h     | 1 +
>  drivers/gpu/drm/xe/xe_device.c       | 1 +
>  drivers/gpu/drm/xe/xe_device_types.h | 5 +++++
>  drivers/gpu/drm/xe/xe_migrate.c      | 2 +-
>  drivers/gpu/drm/xe/xe_module.c       | 4 ++++
>  drivers/gpu/drm/xe/xe_module.h       | 1 +
>  7 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_debugfs.c
> b/drivers/gpu/drm/xe/xe_debugfs.c
> index 80f62634fae5..f3f37d116d62 100644
> --- a/drivers/gpu/drm/xe/xe_debugfs.c
> +++ b/drivers/gpu/drm/xe/xe_debugfs.c
> @@ -222,6 +222,7 @@ static int info(struct seq_file *m, void *data)
>  	drm_printf(&p, "revid %d\n", xe->info.revid);
>  	drm_printf(&p, "tile_count %d\n", xe->info.tile_count);
>  	drm_printf(&p, "vm_max_level %d\n", xe->info.vm_max_level);
> +	drm_printf(&p, "ulls_enable %s\n", str_yes_no(xe-
> >info.ulls_enable));
>  	drm_printf(&p, "has_flat_ccs %s\n", str_yes_no(xe-
> >info.has_flat_ccs));
>  	drm_printf(&p, "has_usm %s\n", str_yes_no(xe-
> >info.has_usm));
>  	drm_printf(&p, "skip_guc_pc %s\n", str_yes_no(xe-
> >info.skip_guc_pc));
> diff --git a/drivers/gpu/drm/xe/xe_defaults.h
> b/drivers/gpu/drm/xe/xe_defaults.h
> index 0884224ef7c7..9c7e89a169c5 100644
> --- a/drivers/gpu/drm/xe/xe_defaults.h
> +++ b/drivers/gpu/drm/xe/xe_defaults.h
> @@ -14,6 +14,7 @@
>  #endif
>  
>  #define
> XE_DEFAULT_PROBE_DISPLAY		IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> +#define XE_DEFAULT_ULLS_ENABLE			true
>  #define XE_DEFAULT_VRAM_BAR_SIZE		0
>  #define
> XE_DEFAULT_FORCE_PROBE			CONFIG_DRM_XE_FORCE_PROBE
>  #define XE_DEFAULT_MAX_VFS			~0
> diff --git a/drivers/gpu/drm/xe/xe_device.c
> b/drivers/gpu/drm/xe/xe_device.c
> index ade971de1652..9b81759af28a 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -520,6 +520,7 @@ static void xe_device_parse_modparam(struct
> xe_device *xe)
>  	xe->atomic_svm_timeslice_ms = 5;
>  	xe->min_run_period_lr_ms = 5;
>  	xe->info.num_pf_work = xe_modparam.num_pf_work;
> +	xe->info.ulls_enable = xe_modparam.ulls_enable;

migrate_ulls_enable?

>  	if (xe->info.num_pf_work < 1)
>  		xe->info.num_pf_work = 1;
>  	else if (xe->info.num_pf_work > XE_PAGEFAULT_WORK_MAX)
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> b/drivers/gpu/drm/xe/xe_device_types.h
> index 997ac82fd571..fd4560378f5b 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -245,6 +245,11 @@ struct xe_device {
>  		u8 skip_pcode:1;
>  		/** @info.needs_shared_vf_gt_wq: needs shared GT WQ
> on VF */
>  		u8 needs_shared_vf_gt_wq:1;
> +		/**
> +		 * @info.ulls_enable: Enable ULLS on migration queue
> in LR VM
> +		 * open
> +		 */
> +		u8 ulls_enable:1;
>  	} info;
>  
>  	/** @wa_active: keep track of active workarounds */
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c
> b/drivers/gpu/drm/xe/xe_migrate.c
> index 3e59aeeca614..3bc78f761f23 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -523,7 +523,7 @@ void xe_migrate_ulls_enter(struct xe_migrate *m)
>  
>  	xe_assert(xe, xe->info.has_usm);
>  
> -	if (!IS_DGFX(xe))
> +	if (!IS_DGFX(xe) || !xe->info.ulls_enable)
>  		return;
>  
>  job_alloc:
> diff --git a/drivers/gpu/drm/xe/xe_module.c
> b/drivers/gpu/drm/xe/xe_module.c
> index 4bc28dfc1992..a8b546550ead 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -23,6 +23,7 @@
>  
>  struct xe_modparam xe_modparam = {
>  	.probe_display =	XE_DEFAULT_PROBE_DISPLAY,
> +	.ulls_enable =		XE_DEFAULT_ULLS_ENABLE,
>  	.guc_log_level =	XE_DEFAULT_GUC_LOG_LEVEL,
>  	.force_probe =		XE_DEFAULT_FORCE_PROBE,
>  #ifdef CONFIG_PCI_IOV
> @@ -44,6 +45,9 @@ MODULE_PARM_DESC(probe_display, "Probe display HW,
> otherwise it's left untouched
>  		 "[default=" __stringify(XE_DEFAULT_PROBE_DISPLAY)
> "])");
>  #endif
>  
> +module_param_named(ulls_enable, xe_modparam.ulls_enable, bool,
> 0444);
> +MODULE_PARM_DESC(ulls_enable, "Enable ULLS on migration queue if LR
> VM open (default: true)");
> +
>  module_param_named(vram_bar_size, xe_modparam.force_vram_bar_size,
> int, 0600);
>  MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size in MiB
> (<0=disable-resize, 0=max-needed-size, >0=force-size "
>  		 "[default=" __stringify(XE_DEFAULT_VRAM_BAR_SIZE)
> "])");
> diff --git a/drivers/gpu/drm/xe/xe_module.h
> b/drivers/gpu/drm/xe/xe_module.h
> index 6272d9e41207..5d88448c298a 100644
> --- a/drivers/gpu/drm/xe/xe_module.h
> +++ b/drivers/gpu/drm/xe/xe_module.h
> @@ -13,6 +13,7 @@ struct work_struct;
>  /* Module modprobe variables */
>  struct xe_modparam {
>  	bool probe_display;
> +	bool ulls_enable;

Shouldn't this be per device rather than per driver? So sysfs knob,
perhaps with a modparam default?

Thanks,
Thomas



>  	int force_vram_bar_size;
>  	int guc_log_level;
>  	char *guc_firmware_path;

Re: [PATCH v6 24/24] drm/xe: Document ULLS for migration jobs

[Thomas Hellström]

On Fri, 2026-09-04 at 14:16 -0700, Matthew Brost wrote:
> Add a kernel-doc DOC section at the top of xe_migrate.c describing
> the
> Ultra Low Latency Submission (ULLS) scheme used for migration jobs.
> 
> Cover the motivation (removing the H2G / GuC / context switch latency
> from the page fault and SVM prefetch critical paths), the platform
> requirements, the LRC PPHWSP semaphore layout and its relationship to
> the migration queue job count, the fixed ULLS job size and why it is
> needed, the ring preamble / postamble emitted by the ring ops
> including
> the in-ring tail update, the semaphore-only submission fast path in
> the
> GuC backend, and the enter / delayed exit flow along with the ULLS
> job
> flags.
> 
> Hook the new section into Documentation/gpu/xe/xe_migrate.rst.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Assisted-by: Github-Copilot:Claude-opus-5
> ---
>  Documentation/gpu/xe/xe_migrate.rst |   3 +
>  drivers/gpu/drm/xe/xe_migrate.c     | 146
> ++++++++++++++++++++++++++++
>  2 files changed, 149 insertions(+)
> 
> diff --git a/Documentation/gpu/xe/xe_migrate.rst
> b/Documentation/gpu/xe/xe_migrate.rst
> index f92faec0ac94..d297ee53a582 100644
> --- a/Documentation/gpu/xe/xe_migrate.rst
> +++ b/Documentation/gpu/xe/xe_migrate.rst
> @@ -6,3 +6,6 @@ Migrate Layer
>  
>  .. kernel-doc:: drivers/gpu/drm/xe/xe_migrate_doc.h
>     :doc: Migrate Layer
> +
> +.. kernel-doc:: drivers/gpu/drm/xe/xe_migrate.c
> +   :doc: ULLS (Ultra Low Latency Submission) for migration jobs
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c
> b/drivers/gpu/drm/xe/xe_migrate.c
> index 3bc78f761f23..94ad1e7e8bc4 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -48,6 +48,152 @@
>  #include "xe_vm.h"
>  #include "xe_vram.h"
>  
> +/**
> + * DOC: ULLS (Ultra Low Latency Submission) for migration jobs
> + *
> + * Migration jobs issued on behalf of GPU page faults and SVM
> prefetches sit
> + * directly in the critical path of a stalled GPU workload. The
> dominant cost
> + * of such a job is not the copy or clear itself but the submission
> latency:
> + * the H2G round trip to GuC, the GuC scheduling decision, and the
> hardware
> + * context switch required to place the migration LRC on an engine.
> + *
> + * ULLS removes that cost by keeping the migration context resident
> and
> + * *running* on the hardware engine across jobs. Instead of the ring
> going
> + * empty and the context being switched out between jobs, the tail
> of every
> + * ULLS job parks the engine on a semaphore wait for the *next*
> job's
> + * semaphore, and then advances the ring tail itself. Submitting the
> next job
> + * therefore costs the CPU a single write to signal that semaphore -
> no H2G,
> + * no GuC round trip, no context switch, no MMIO.

This all assumes the migration LRC empties between jobs. How common is
that to the case where a new job can modify the ring tail before the
previous job finished? Will the HW autotail feature affect the
usefulness of the ULLS migration jobs?

Also worth adding is a discussion around semaphore context switch-out
when stalled, like whether we're inhibiting that explicitly, whether
the engine is assumed to be single-context etc.


> + *
> + * Requirements
> + * ------------
> + *
> + * ULLS is only used on DGFX with USM support (where a hardware
> engine is
> + * reserved exclusively for migration jobs). Because the engine is
> spinning
> + * on a semaphore while ULLS is active, it can not be shared with
> user
> + * submissions. It can also be disabled at load time with the
> + * ``xe.ulls_enable`` module parameter.

Update if decide to use per-device sysfs entry.

Otherwise LGTM.

/Thomas




> + *
> + * Fixed size jobs
> + * ---------------
> + *
> + * A job updates the ring tail to cover its successor, but it is
> emitted long
> + * before that successor exists, so it can not know how much ring
> the
> + * successor will occupy. Every ULLS job is therefore padded out to
> exactly
> + * ULLS_JOB_SIZE_BYTES, which lets the next tail be computed
> arithmetically
> + * from where the current job started.
> + *
> + * This is why the shorter jobs still have to reach the same size:
> the "last"
> + * job skips the batch buffers and the postamble, and pads the
> difference with
> + * MI_NOOP. The "first" job is not covered by any predecessor's tail
> update
> + * and so is unconstrained, but is padded anyway to keep the
> arithmetic
> + * uniform.
> + *
> + * Leaving ULLS mode always goes through a "last" job, which emits
> no tail
> + * update, so an ordinary variable length migration job never
> follows a
> + * prediction.
> + *
> + * Semaphores
> + * ----------
> + *
> + * The semaphores live in the driver-defined portion of the
> migration LRC's
> + * PPHWSP (see LRC_ULLS_PPHWSP_OFFSET, mutually exclusive with the
> parallel
> + * submission area). There are LRC_MIGRATION_ULLS_SEMAPHORE_COUNT of
> them and
> + * a job's semaphore is selected by ``seqno % COUNT``, so the
> semaphore ring
> + * wraps with the job seqnos. To guarantee a job can never overwrite
> the
> + * semaphore of a job still in flight, the GuC backend caps the
> migration
> + * queue's scheduler job count at LRC_MIGRATION_ULLS_SEMAPHORE_COUNT
> - 1.
> + *
> + * Ring layout of a ULLS job
> + * -------------------------
> + *
> + * Emitted by emit_migration_job_gen12() in xe_ring_ops.c::
> + *
> + *	preamble:	clear semaphore[seqno]	(reuse for a later
> wrap)
> + *	<copy timestamp, start seqno store>
> + *	<batch buffer start(s)>			(skipped on
> first/last job)
> + *	<seqno write + user interrupt>
> + *	postamble:	SDI saved ring tail = end of next job
> + *			LRI RING_TAIL = end of next job
> + *			wait on semaphore[seqno + 1]
> + *						(skipped on the last
> job)
> + *	pad:		MI_NOOP up to ULLS_JOB_SIZE_DW
> + *
> + * The preamble clears the current job's semaphore so it can be
> reused once
> + * the seqno space wraps. The postamble is what keeps the engine
> busy: it
> + * advances the ring tail over the next job and then blocks on that
> job's
> + * semaphore, which is only signaled when the job is actually
> submitted. It
> + * advances the saved tail as well as the tail register, keeping the
> two in
> + * step without any help from the CPU, so a context save and restore
> can not
> + * rewind the tail behind work which has already been published.
> + *
> + * The tail register write must be non-posted, i.e. it must not
> carry
> + * MI_LRI_FORCE_POSTED. Posted, the new tail is free to land after
> the command
> + * streamer has already drained the rest of the job, at which point
> the command
> + * streamer sees head == the old tail and parks as though the ring
> were empty.
> + * A parked context can be switched off the hardware, and the fast
> path below
> + * has no H2G with which to ask GuC to bring it back.
> + *
> + * The tail is published ahead of the semaphore wait rather than
> after it so
> + * that the non-posted write drains while the engine is parked
> anyway, keeping
> + * a register round trip off the path between the semaphore being
> signaled and
> + * the next job running.
> + *
> + * Submission fast path
> + * --------------------
> + *
> + * In submit_exec_queue() (xe_guc_submit.c), a ULLS job that is not
> the first
> + * one reduces to::
> + *
> + *	xe_lrc_set_ulls_semaphore(lrc, seqno);		release
> previous job
> + *
> + * The XE_GUC_ACTION_SCHED_CONTEXT H2G is suppressed, and so is the
> write of
> + * the saved ring tail: the previous job's postamble has already
> published
> + * this job's tail both in the tail register and in the context
> image, so the
> + * semaphore signal is all that is left. The previous job's
> semaphore wait is
> + * satisfied and the engine walks straight into this job.
> + *
> + * This does assume the context stays resident for as long as ULLS
> mode is
> + * active. Nothing else is scheduled on the reserved engine, so the
> only ways
> + * off the hardware are the "last" job below, or a reset - and a
> migration job
> + * failing already wedges the device.
> + *
> + * Enter / exit
> + * ------------
> + *
> + * xe_migrate_ulls_enter() is called from the page fault handler and
> from the
> + * SVM prefetch path, i.e. exactly where low latency migration
> matters. It
> + * takes a PM runtime reference (the device must not suspend while
> the engine
> + * spins), then submits a "first" ULLS job. That first job carries
> no batch
> + * buffer; it exists only to get the context onto the hardware
> through the
> + * normal GuC path and to leave the engine waiting on the next
> semaphore,
> + * pipelining the GuC/HW context switch out of the critical path.
> + *
> + * No forcewake reference is required. Nothing in the fast path
> touches MMIO,
> + * and the engine keeps itself awake for as long as it is executing
> the ring.
> + * Not needing host MMIO access is also what lets ULLS run on SRIOV
> VFs.
> + *
> + * Keeping an engine spinning costs power, so ULLS is not left
> enabled
> + * indefinitely. Every enter and every ULLS job submission re-arms
> + * @xe_migrate.ulls.exit_work with a ULLS_EXIT_JIFFIES delay. When
> it fires
> + * with the queue idle, it submits a "last" ULLS job - again with no
> batch
> + * buffer and, crucially, with no postamble semaphore wait or tail
> update -
> + * which lets the ring drain so the context can be switched off the
> hardware.
> + * The PM reference is then dropped. If the queue was not idle, the
> worker
> + * simply re-arms itself.
> + *
> + * Job state
> + * ---------
> + *
> + * The state above is communicated to the ring ops and GuC backend
> via
> + * @xe_sched_job.ulls, set under @xe_migrate.job_mutex:
> + *
> + * - %ULLS_NONE: job submitted outside of ULLS mode
> + * - %ULLS_ENTER: job that enters ULLS mode
> + * - %ULLS_ACTIVE: job submitted while in ULLS mode
> + * - %ULLS_EXIT: job that exits ULLS mode
> + */
> +
>  /**
>   * struct xe_migrate - migrate context.
>   */

Re: [PATCH v6 24/24] drm/xe: Document ULLS for migration jobs

[Matthew Brost]

On Wed, Sep 09, 2026 at 11:01:50AM +0200, Thomas Hellström wrote:
> On Fri, 2026-09-04 at 14:16 -0700, Matthew Brost wrote:
> > Add a kernel-doc DOC section at the top of xe_migrate.c describing
> > the
> > Ultra Low Latency Submission (ULLS) scheme used for migration jobs.
> > 
> > Cover the motivation (removing the H2G / GuC / context switch latency
> > from the page fault and SVM prefetch critical paths), the platform
> > requirements, the LRC PPHWSP semaphore layout and its relationship to
> > the migration queue job count, the fixed ULLS job size and why it is
> > needed, the ring preamble / postamble emitted by the ring ops
> > including
> > the in-ring tail update, the semaphore-only submission fast path in
> > the
> > GuC backend, and the enter / delayed exit flow along with the ULLS
> > job
> > flags.
> > 
> > Hook the new section into Documentation/gpu/xe/xe_migrate.rst.
> > 
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > Assisted-by: Github-Copilot:Claude-opus-5
> > ---
> >  Documentation/gpu/xe/xe_migrate.rst |   3 +
> >  drivers/gpu/drm/xe/xe_migrate.c     | 146
> > ++++++++++++++++++++++++++++
> >  2 files changed, 149 insertions(+)
> > 
> > diff --git a/Documentation/gpu/xe/xe_migrate.rst
> > b/Documentation/gpu/xe/xe_migrate.rst
> > index f92faec0ac94..d297ee53a582 100644
> > --- a/Documentation/gpu/xe/xe_migrate.rst
> > +++ b/Documentation/gpu/xe/xe_migrate.rst
> > @@ -6,3 +6,6 @@ Migrate Layer
> >  
> >  .. kernel-doc:: drivers/gpu/drm/xe/xe_migrate_doc.h
> >     :doc: Migrate Layer
> > +
> > +.. kernel-doc:: drivers/gpu/drm/xe/xe_migrate.c
> > +   :doc: ULLS (Ultra Low Latency Submission) for migration jobs
> > diff --git a/drivers/gpu/drm/xe/xe_migrate.c
> > b/drivers/gpu/drm/xe/xe_migrate.c
> > index 3bc78f761f23..94ad1e7e8bc4 100644
> > --- a/drivers/gpu/drm/xe/xe_migrate.c
> > +++ b/drivers/gpu/drm/xe/xe_migrate.c
> > @@ -48,6 +48,152 @@
> >  #include "xe_vm.h"
> >  #include "xe_vram.h"
> >  
> > +/**
> > + * DOC: ULLS (Ultra Low Latency Submission) for migration jobs
> > + *
> > + * Migration jobs issued on behalf of GPU page faults and SVM
> > prefetches sit
> > + * directly in the critical path of a stalled GPU workload. The
> > dominant cost
> > + * of such a job is not the copy or clear itself but the submission
> > latency:
> > + * the H2G round trip to GuC, the GuC scheduling decision, and the
> > hardware
> > + * context switch required to place the migration LRC on an engine.
> > + *
> > + * ULLS removes that cost by keeping the migration context resident
> > and
> > + * *running* on the hardware engine across jobs. Instead of the ring
> > going
> > + * empty and the context being switched out between jobs, the tail
> > of every
> > + * ULLS job parks the engine on a semaphore wait for the *next*
> > job's
> > + * semaphore, and then advances the ring tail itself. Submitting the
> > next job
> > + * therefore costs the CPU a single write to signal that semaphore -
> > no H2G,
> > + * no GuC round trip, no context switch, no MMIO.
> 
> This all assumes the migration LRC empties between jobs. How common is
> that to the case where a new job can modify the ring tail before the

All I have so far is data from UMD stream access benchmarks, which show
roughly a 50% increase across the board, GT statistics showing a 20-30
µs latency reduction per copy job across various IGTs, and a prefetch
bandwidth IGT showing approximately a 7 GB/s bandwidth increase on our
highest-end BMG part. All of these results point to excessive
context-switching overhead, as the ring must either go idle or initiate
a context switch.

> previous job finished? Will the HW autotail feature affect the
> usefulness of the ULLS migration jobs?
> 

The auto-tail feature appears to be based on the same concept: allowing
contexts to spin on LRC tail updates until they are context-switched
out. The documentation is fairly sparse, though. I found bspec67276 and
HSD 220160875, which seem to indicate that this is supported on BMG. Do
you know if there is better documentation available?

I also haven't been able to find any KMD patches that enable this, which
seems a bit odd. If we can get auto-tail to provide roughly the same
benefits without impacting other clients, it may be worth investigating.
In my opinion, though, that should be done as a follow-up and added to
the backlog.

The ULLS patches are thoroughly tested, relatively small in terms of
both lines of code and complexity, and can be reverted if an alternative
solution proves to be equally effective.

> Also worth adding is a discussion around semaphore context switch-out
> when stalled, like whether we're inhibiting that explicitly, whether
> the engine is assumed to be single-context etc.

Let me add that. I don't disable context switch-out, and having a single
queue on the engine is not explicitly required. However, for practical
purposes, the idea falls apart with more than one queue, since you don't
want to delay another queue from being switched in while a semaphore is
spinning for the duration of the timeslice period (1 ms by default).

My idea was that if we need more than one queue on the paging engine,
the other queues would detect that ULLS is running and issue an
early-exit ULLS job before their submission. Likewise, we would elide
ULLS entry whenever other queues are non-idle.

Matt

> 
> 
> > + *
> > + * Requirements
> > + * ------------
> > + *
> > + * ULLS is only used on DGFX with USM support (where a hardware
> > engine is
> > + * reserved exclusively for migration jobs). Because the engine is
> > spinning
> > + * on a semaphore while ULLS is active, it can not be shared with
> > user
> > + * submissions. It can also be disabled at load time with the
> > + * ``xe.ulls_enable`` module parameter.
> 
> Update if decide to use per-device sysfs entry.
> 
> Otherwise LGTM.
> 
> /Thomas
> 
> 
> 
> 
> > + *
> > + * Fixed size jobs
> > + * ---------------
> > + *
> > + * A job updates the ring tail to cover its successor, but it is
> > emitted long
> > + * before that successor exists, so it can not know how much ring
> > the
> > + * successor will occupy. Every ULLS job is therefore padded out to
> > exactly
> > + * ULLS_JOB_SIZE_BYTES, which lets the next tail be computed
> > arithmetically
> > + * from where the current job started.
> > + *
> > + * This is why the shorter jobs still have to reach the same size:
> > the "last"
> > + * job skips the batch buffers and the postamble, and pads the
> > difference with
> > + * MI_NOOP. The "first" job is not covered by any predecessor's tail
> > update
> > + * and so is unconstrained, but is padded anyway to keep the
> > arithmetic
> > + * uniform.
> > + *
> > + * Leaving ULLS mode always goes through a "last" job, which emits
> > no tail
> > + * update, so an ordinary variable length migration job never
> > follows a
> > + * prediction.
> > + *
> > + * Semaphores
> > + * ----------
> > + *
> > + * The semaphores live in the driver-defined portion of the
> > migration LRC's
> > + * PPHWSP (see LRC_ULLS_PPHWSP_OFFSET, mutually exclusive with the
> > parallel
> > + * submission area). There are LRC_MIGRATION_ULLS_SEMAPHORE_COUNT of
> > them and
> > + * a job's semaphore is selected by ``seqno % COUNT``, so the
> > semaphore ring
> > + * wraps with the job seqnos. To guarantee a job can never overwrite
> > the
> > + * semaphore of a job still in flight, the GuC backend caps the
> > migration
> > + * queue's scheduler job count at LRC_MIGRATION_ULLS_SEMAPHORE_COUNT
> > - 1.
> > + *
> > + * Ring layout of a ULLS job
> > + * -------------------------
> > + *
> > + * Emitted by emit_migration_job_gen12() in xe_ring_ops.c::
> > + *
> > + *	preamble:	clear semaphore[seqno]	(reuse for a later
> > wrap)
> > + *	<copy timestamp, start seqno store>
> > + *	<batch buffer start(s)>			(skipped on
> > first/last job)
> > + *	<seqno write + user interrupt>
> > + *	postamble:	SDI saved ring tail = end of next job
> > + *			LRI RING_TAIL = end of next job
> > + *			wait on semaphore[seqno + 1]
> > + *						(skipped on the last
> > job)
> > + *	pad:		MI_NOOP up to ULLS_JOB_SIZE_DW
> > + *
> > + * The preamble clears the current job's semaphore so it can be
> > reused once
> > + * the seqno space wraps. The postamble is what keeps the engine
> > busy: it
> > + * advances the ring tail over the next job and then blocks on that
> > job's
> > + * semaphore, which is only signaled when the job is actually
> > submitted. It
> > + * advances the saved tail as well as the tail register, keeping the
> > two in
> > + * step without any help from the CPU, so a context save and restore
> > can not
> > + * rewind the tail behind work which has already been published.
> > + *
> > + * The tail register write must be non-posted, i.e. it must not
> > carry
> > + * MI_LRI_FORCE_POSTED. Posted, the new tail is free to land after
> > the command
> > + * streamer has already drained the rest of the job, at which point
> > the command
> > + * streamer sees head == the old tail and parks as though the ring
> > were empty.
> > + * A parked context can be switched off the hardware, and the fast
> > path below
> > + * has no H2G with which to ask GuC to bring it back.
> > + *
> > + * The tail is published ahead of the semaphore wait rather than
> > after it so
> > + * that the non-posted write drains while the engine is parked
> > anyway, keeping
> > + * a register round trip off the path between the semaphore being
> > signaled and
> > + * the next job running.
> > + *
> > + * Submission fast path
> > + * --------------------
> > + *
> > + * In submit_exec_queue() (xe_guc_submit.c), a ULLS job that is not
> > the first
> > + * one reduces to::
> > + *
> > + *	xe_lrc_set_ulls_semaphore(lrc, seqno);		release
> > previous job
> > + *
> > + * The XE_GUC_ACTION_SCHED_CONTEXT H2G is suppressed, and so is the
> > write of
> > + * the saved ring tail: the previous job's postamble has already
> > published
> > + * this job's tail both in the tail register and in the context
> > image, so the
> > + * semaphore signal is all that is left. The previous job's
> > semaphore wait is
> > + * satisfied and the engine walks straight into this job.
> > + *
> > + * This does assume the context stays resident for as long as ULLS
> > mode is
> > + * active. Nothing else is scheduled on the reserved engine, so the
> > only ways
> > + * off the hardware are the "last" job below, or a reset - and a
> > migration job
> > + * failing already wedges the device.
> > + *
> > + * Enter / exit
> > + * ------------
> > + *
> > + * xe_migrate_ulls_enter() is called from the page fault handler and
> > from the
> > + * SVM prefetch path, i.e. exactly where low latency migration
> > matters. It
> > + * takes a PM runtime reference (the device must not suspend while
> > the engine
> > + * spins), then submits a "first" ULLS job. That first job carries
> > no batch
> > + * buffer; it exists only to get the context onto the hardware
> > through the
> > + * normal GuC path and to leave the engine waiting on the next
> > semaphore,
> > + * pipelining the GuC/HW context switch out of the critical path.
> > + *
> > + * No forcewake reference is required. Nothing in the fast path
> > touches MMIO,
> > + * and the engine keeps itself awake for as long as it is executing
> > the ring.
> > + * Not needing host MMIO access is also what lets ULLS run on SRIOV
> > VFs.
> > + *
> > + * Keeping an engine spinning costs power, so ULLS is not left
> > enabled
> > + * indefinitely. Every enter and every ULLS job submission re-arms
> > + * @xe_migrate.ulls.exit_work with a ULLS_EXIT_JIFFIES delay. When
> > it fires
> > + * with the queue idle, it submits a "last" ULLS job - again with no
> > batch
> > + * buffer and, crucially, with no postamble semaphore wait or tail
> > update -
> > + * which lets the ring drain so the context can be switched off the
> > hardware.
> > + * The PM reference is then dropped. If the queue was not idle, the
> > worker
> > + * simply re-arms itself.
> > + *
> > + * Job state
> > + * ---------
> > + *
> > + * The state above is communicated to the ring ops and GuC backend
> > via
> > + * @xe_sched_job.ulls, set under @xe_migrate.job_mutex:
> > + *
> > + * - %ULLS_NONE: job submitted outside of ULLS mode
> > + * - %ULLS_ENTER: job that enters ULLS mode
> > + * - %ULLS_ACTIVE: job submitted while in ULLS mode
> > + * - %ULLS_EXIT: job that exits ULLS mode
> > + */
> > +
> >  /**
> >   * struct xe_migrate - migrate context.
> >   */

Re: [PATCH v6 23/24] drm/xe: Add modparam to enable / disable ULLS on migrate queue

[Matthew Brost]

On Wed, Sep 09, 2026 at 10:03:32AM +0200, Thomas Hellström wrote:
> On Fri, 2026-09-04 at 14:16 -0700, Matthew Brost wrote:
> > Having modparam to enable / disable ULLS on migrate queue will help
> > with
> > quick experiments.
> > 
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > Link:
> > https://patch.msgid.link/20260228013501.106680-26-matthew.brost@intel.com
> > Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> > ---
> >  drivers/gpu/drm/xe/xe_debugfs.c      | 1 +
> >  drivers/gpu/drm/xe/xe_defaults.h     | 1 +
> >  drivers/gpu/drm/xe/xe_device.c       | 1 +
> >  drivers/gpu/drm/xe/xe_device_types.h | 5 +++++
> >  drivers/gpu/drm/xe/xe_migrate.c      | 2 +-
> >  drivers/gpu/drm/xe/xe_module.c       | 4 ++++
> >  drivers/gpu/drm/xe/xe_module.h       | 1 +
> >  7 files changed, 14 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_debugfs.c
> > b/drivers/gpu/drm/xe/xe_debugfs.c
> > index 80f62634fae5..f3f37d116d62 100644
> > --- a/drivers/gpu/drm/xe/xe_debugfs.c
> > +++ b/drivers/gpu/drm/xe/xe_debugfs.c
> > @@ -222,6 +222,7 @@ static int info(struct seq_file *m, void *data)
> >  	drm_printf(&p, "revid %d\n", xe->info.revid);
> >  	drm_printf(&p, "tile_count %d\n", xe->info.tile_count);
> >  	drm_printf(&p, "vm_max_level %d\n", xe->info.vm_max_level);
> > +	drm_printf(&p, "ulls_enable %s\n", str_yes_no(xe-
> > >info.ulls_enable));
> >  	drm_printf(&p, "has_flat_ccs %s\n", str_yes_no(xe-
> > >info.has_flat_ccs));
> >  	drm_printf(&p, "has_usm %s\n", str_yes_no(xe-
> > >info.has_usm));
> >  	drm_printf(&p, "skip_guc_pc %s\n", str_yes_no(xe-
> > >info.skip_guc_pc));
> > diff --git a/drivers/gpu/drm/xe/xe_defaults.h
> > b/drivers/gpu/drm/xe/xe_defaults.h
> > index 0884224ef7c7..9c7e89a169c5 100644
> > --- a/drivers/gpu/drm/xe/xe_defaults.h
> > +++ b/drivers/gpu/drm/xe/xe_defaults.h
> > @@ -14,6 +14,7 @@
> >  #endif
> >  
> >  #define
> > XE_DEFAULT_PROBE_DISPLAY		IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> > +#define XE_DEFAULT_ULLS_ENABLE			true
> >  #define XE_DEFAULT_VRAM_BAR_SIZE		0
> >  #define
> > XE_DEFAULT_FORCE_PROBE			CONFIG_DRM_XE_FORCE_PROBE
> >  #define XE_DEFAULT_MAX_VFS			~0
> > diff --git a/drivers/gpu/drm/xe/xe_device.c
> > b/drivers/gpu/drm/xe/xe_device.c
> > index ade971de1652..9b81759af28a 100644
> > --- a/drivers/gpu/drm/xe/xe_device.c
> > +++ b/drivers/gpu/drm/xe/xe_device.c
> > @@ -520,6 +520,7 @@ static void xe_device_parse_modparam(struct
> > xe_device *xe)
> >  	xe->atomic_svm_timeslice_ms = 5;
> >  	xe->min_run_period_lr_ms = 5;
> >  	xe->info.num_pf_work = xe_modparam.num_pf_work;
> > +	xe->info.ulls_enable = xe_modparam.ulls_enable;
> 
> migrate_ulls_enable?
> 
> >  	if (xe->info.num_pf_work < 1)
> >  		xe->info.num_pf_work = 1;
> >  	else if (xe->info.num_pf_work > XE_PAGEFAULT_WORK_MAX)
> > diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> > b/drivers/gpu/drm/xe/xe_device_types.h
> > index 997ac82fd571..fd4560378f5b 100644
> > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > @@ -245,6 +245,11 @@ struct xe_device {
> >  		u8 skip_pcode:1;
> >  		/** @info.needs_shared_vf_gt_wq: needs shared GT WQ
> > on VF */
> >  		u8 needs_shared_vf_gt_wq:1;
> > +		/**
> > +		 * @info.ulls_enable: Enable ULLS on migration queue
> > in LR VM
> > +		 * open
> > +		 */
> > +		u8 ulls_enable:1;
> >  	} info;
> >  
> >  	/** @wa_active: keep track of active workarounds */
> > diff --git a/drivers/gpu/drm/xe/xe_migrate.c
> > b/drivers/gpu/drm/xe/xe_migrate.c
> > index 3e59aeeca614..3bc78f761f23 100644
> > --- a/drivers/gpu/drm/xe/xe_migrate.c
> > +++ b/drivers/gpu/drm/xe/xe_migrate.c
> > @@ -523,7 +523,7 @@ void xe_migrate_ulls_enter(struct xe_migrate *m)
> >  
> >  	xe_assert(xe, xe->info.has_usm);
> >  
> > -	if (!IS_DGFX(xe))
> > +	if (!IS_DGFX(xe) || !xe->info.ulls_enable)
> >  		return;
> >  
> >  job_alloc:
> > diff --git a/drivers/gpu/drm/xe/xe_module.c
> > b/drivers/gpu/drm/xe/xe_module.c
> > index 4bc28dfc1992..a8b546550ead 100644
> > --- a/drivers/gpu/drm/xe/xe_module.c
> > +++ b/drivers/gpu/drm/xe/xe_module.c
> > @@ -23,6 +23,7 @@
> >  
> >  struct xe_modparam xe_modparam = {
> >  	.probe_display =	XE_DEFAULT_PROBE_DISPLAY,
> > +	.ulls_enable =		XE_DEFAULT_ULLS_ENABLE,
> >  	.guc_log_level =	XE_DEFAULT_GUC_LOG_LEVEL,
> >  	.force_probe =		XE_DEFAULT_FORCE_PROBE,
> >  #ifdef CONFIG_PCI_IOV
> > @@ -44,6 +45,9 @@ MODULE_PARM_DESC(probe_display, "Probe display HW,
> > otherwise it's left untouched
> >  		 "[default=" __stringify(XE_DEFAULT_PROBE_DISPLAY)
> > "])");
> >  #endif
> >  
> > +module_param_named(ulls_enable, xe_modparam.ulls_enable, bool,
> > 0444);
> > +MODULE_PARM_DESC(ulls_enable, "Enable ULLS on migration queue if LR
> > VM open (default: true)");
> > +
> >  module_param_named(vram_bar_size, xe_modparam.force_vram_bar_size,
> > int, 0600);
> >  MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size in MiB
> > (<0=disable-resize, 0=max-needed-size, >0=force-size "
> >  		 "[default=" __stringify(XE_DEFAULT_VRAM_BAR_SIZE)
> > "])");
> > diff --git a/drivers/gpu/drm/xe/xe_module.h
> > b/drivers/gpu/drm/xe/xe_module.h
> > index 6272d9e41207..5d88448c298a 100644
> > --- a/drivers/gpu/drm/xe/xe_module.h
> > +++ b/drivers/gpu/drm/xe/xe_module.h
> > @@ -13,6 +13,7 @@ struct work_struct;
> >  /* Module modprobe variables */
> >  struct xe_modparam {
> >  	bool probe_display;
> > +	bool ulls_enable;
> 
> Shouldn't this be per device rather than per driver? So sysfs knob,
> perhaps with a modparam default?
> 

I didn't really want to add a userspace ABI, such as a sysfs interface,
at this point, so I went with a module parameter instead. It also seems
a bit odd to enable this on some devices but not others.

The main reason for having this at all is to allow quick performance
comparisons and, of course, to give us an easy way to disable it and
retest if we encounter workloads where kernel jobs appear to hang.

I'm open to changing this as the series receives more review and we get
closer to merging.

Matt

> Thanks,
> Thomas
> 
> 
> 
> >  	int force_vram_bar_size;
> >  	int guc_log_level;
> >  	char *guc_firmware_path;

Re: [PATCH v6 06/24] drm/xe: Add XE_BO_FLAG_PUT_VM_ASYNC

[Francois Dugast]

On Fri, Sep 04, 2026 at 02:15:55PM -0700, Matthew Brost wrote:
> Add XE_BO_FLAG_PUT_VM_ASYNC, which indicates that an async BO put must
> also drop an additional reference to the BO’s VM. This is useful when a
> kernel BO, one that does not normally hold a VM reference, needs to be
> put asynchronously, ensuring the shared dma-resv object does not
> disappear before the BO.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Link: https://patch.msgid.link/20260228013501.106680-7-matthew.brost@intel.com
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/xe/xe_bo.c | 8 +++++++-
>  drivers/gpu/drm/xe/xe_bo.h | 1 +
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index b162753cebb7..aea4b0fee8e3 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -3998,8 +3998,14 @@ void xe_bo_put_commit(struct llist_head *deferred)
>  	if (!freed)
>  		return;
>  
> -	llist_for_each_entry_safe(bo, next, freed, freed)
> +	llist_for_each_entry_safe(bo, next, freed, freed) {
> +		struct xe_vm *vm = bo->vm;
> +		bool async = bo->flags & XE_BO_FLAG_PUT_VM_ASYNC;
> +
>  		drm_gem_object_free(&bo->ttm.base.refcount);
> +		if (async)
> +			xe_vm_put(vm);

You had mentioned reworking this part:
https://patchwork.freedesktop.org/patch/750807/?series=149888&rev=6#comment_1383757

Sashiko seems consistent here.

Francois

> +	}
>  }
>  
>  static void xe_bo_dev_work_func(struct work_struct *work)
> diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
> index 01975586ee88..2168aac1ed1e 100644
> --- a/drivers/gpu/drm/xe/xe_bo.h
> +++ b/drivers/gpu/drm/xe/xe_bo.h
> @@ -54,6 +54,7 @@
>  #define XE_BO_FLAG_FORCE_USER_VRAM	BIT(25)
>  #define XE_BO_FLAG_NO_COMPRESSION	BIT(26)
>  #define XE_BO_FLAG_NEEDS_1G		BIT(27)
> +#define XE_BO_FLAG_PUT_VM_ASYNC		BIT(28)
>  
>  /* this one is trigger internally only */
>  #define XE_BO_FLAG_INTERNAL_TEST	BIT(30)
> -- 
> 2.34.1
> 

Re: [PATCH v6 07/24] drm/xe: Update scheduler job layer to support PT jobs

[Francois Dugast]

On Fri, Sep 04, 2026 at 02:15:56PM -0700, Matthew Brost wrote:
> Update the scheduler job layer to support PT jobs. PT jobs are executed
> entirely on the CPU and do not require LRC fences or a batch address.
> Repurpose the LRC fence storage to hold PT‑job arguments and update the
> scheduler job layer to distinguish between PT jobs and jobs that require
> an LRC.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Link: https://patch.msgid.link/20260228013501.106680-8-matthew.brost@intel.com
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/xe/xe_sched_job.c       | 95 ++++++++++++++++---------
>  drivers/gpu/drm/xe/xe_sched_job_types.h | 31 +++++++-
>  drivers/gpu/drm/xe/xe_trace.h           |  2 +-
>  3 files changed, 92 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
> index a4fa00632a30..841d67ebd5b0 100644
> --- a/drivers/gpu/drm/xe/xe_sched_job.c
> +++ b/drivers/gpu/drm/xe/xe_sched_job.c
> @@ -26,19 +26,22 @@ static struct kmem_cache *xe_sched_job_parallel_slab;
>  
>  int __init xe_sched_job_module_init(void)
>  {
> +	struct xe_sched_job *job;
> +	size_t size;
> +
> +	size = struct_size(job, ptrs, 1);
>  	xe_sched_job_slab =
> -		kmem_cache_create("xe_sched_job",
> -				  sizeof(struct xe_sched_job) +
> -				  sizeof(struct xe_job_ptrs), 0,
> +		kmem_cache_create("xe_sched_job", size, 0,
>  				  SLAB_HWCACHE_ALIGN, NULL);
>  	if (!xe_sched_job_slab)
>  		return -ENOMEM;
>  
> +	size = max_t(size_t,
> +		     struct_size(job, ptrs,
> +				 XE_HW_ENGINE_MAX_INSTANCE),
> +		     struct_size(job, pt_update, 1));
>  	xe_sched_job_parallel_slab =
> -		kmem_cache_create("xe_sched_job_parallel",
> -				  sizeof(struct xe_sched_job) +
> -				  sizeof(struct xe_job_ptrs) *
> -				  XE_HW_ENGINE_MAX_INSTANCE, 0,
> +		kmem_cache_create("xe_sched_job_parallel", size, 0,
>  				  SLAB_HWCACHE_ALIGN, NULL);
>  	if (!xe_sched_job_parallel_slab) {
>  		kmem_cache_destroy(xe_sched_job_slab);
> @@ -84,6 +87,9 @@ static void xe_sched_job_free_fences(struct xe_sched_job *job)
>  {
>  	int i;
>  
> +	if (job->is_pt_job)
> +		return;
> +
>  	for (i = 0; i < job->q->width; ++i) {
>  		struct xe_job_ptrs *ptrs = &job->ptrs[i];
>  
> @@ -93,10 +99,23 @@ static void xe_sched_job_free_fences(struct xe_sched_job *job)
>  	}
>  }
>  
> +/**
> + * xe_sched_job_create() - Create a scheduler job
> + * @q: exec queue to create the scheduler job for
> + * @batch_addr: array of batch addresses for the job; must match the width of
> + * @q, or NULL to indicate a PT job that does not require a batch address
> + *
> + * Create a scheduler job for submission.
> + *
> + * Context: Reclaim
> + *
> + * Return: a &xe_sched_job object on success, or an ERR_PTR on failure.
> + */
>  struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
>  					 u64 *batch_addr)
>  {
>  	bool is_migration = xe_sched_job_is_migration(q);
> +	struct xe_device *xe = gt_to_xe(q->gt);
>  	struct xe_sched_job *job;
>  	int err;
>  	int i;
> @@ -105,6 +124,9 @@ struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
>  	/* only a kernel context can submit a vm-less job */
>  	XE_WARN_ON(!q->vm && !(q->flags & EXEC_QUEUE_FLAG_KERNEL));
>  
> +	xe_assert(xe, batch_addr ||
> +		  q->flags & (EXEC_QUEUE_FLAG_VM | EXEC_QUEUE_FLAG_MIGRATE));
> +
>  	job = job_alloc(xe_exec_queue_is_parallel(q) || is_migration);
>  	if (!job)
>  		return ERR_PTR(-ENOMEM);
> @@ -119,34 +141,39 @@ struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
>  	if (err)
>  		goto err_free;
>  
> -	for (i = 0; i < q->width; ++i) {
> -		struct dma_fence *fence = xe_lrc_alloc_seqno_fence();
> -		struct dma_fence_chain *chain;
> -
> -		if (IS_ERR(fence)) {
> -			err = PTR_ERR(fence);
> -			goto err_sched_job;
> +	if (!batch_addr) {
> +		job->fence = dma_fence_get_stub();
> +		job->is_pt_job = true;
> +	} else {
> +		for (i = 0; i < q->width; ++i) {
> +			struct dma_fence *fence = xe_lrc_alloc_seqno_fence();
> +			struct dma_fence_chain *chain;
> +
> +			if (IS_ERR(fence)) {
> +				err = PTR_ERR(fence);
> +				goto err_sched_job;
> +			}
> +			job->ptrs[i].lrc_fence = fence;
> +
> +			if (i + 1 == q->width)
> +				continue;
> +
> +			chain = dma_fence_chain_alloc();
> +			if (!chain) {
> +				err = -ENOMEM;
> +				goto err_sched_job;
> +			}
> +			job->ptrs[i].chain_fence = chain;
>  		}
> -		job->ptrs[i].lrc_fence = fence;
>  
> -		if (i + 1 == q->width)
> -			continue;
> +		width = q->width;
> +		if (is_migration)
> +			width = 2;
>  
> -		chain = dma_fence_chain_alloc();
> -		if (!chain) {
> -			err = -ENOMEM;
> -			goto err_sched_job;
> -		}
> -		job->ptrs[i].chain_fence = chain;
> +		for (i = 0; i < width; ++i)
> +			job->ptrs[i].batch_addr = batch_addr[i];
>  	}
>  
> -	width = q->width;
> -	if (is_migration)
> -		width = 2;
> -
> -	for (i = 0; i < width; ++i)
> -		job->ptrs[i].batch_addr = batch_addr[i];
> -
>  	atomic_inc(&q->job_cnt);
>  	xe_pm_runtime_get_noresume(job_to_xe(job));
>  	trace_xe_sched_job_create(job);
> @@ -246,7 +273,7 @@ bool xe_sched_job_completed(struct xe_sched_job *job)
>  void xe_sched_job_arm(struct xe_sched_job *job)
>  {
>  	struct xe_exec_queue *q = job->q;
> -	struct dma_fence *fence, *prev;
> +	struct dma_fence *fence = job->fence, *prev;
>  	struct xe_vm *vm = q->vm;
>  	u64 seqno = 0;
>  	int i;
> @@ -266,6 +293,9 @@ void xe_sched_job_arm(struct xe_sched_job *job)
>  		job->ring_ops_flush_tlb = true;
>  	}
>  
> +	if (job->is_pt_job)
> +		goto arm;
> +

I think Sashiko's warning is valid, we should move this ^ one block
above to skip touching q->tlb_flush_seqno and ring_ops_flush_tlb for
PT jobs.

Francois

>  	/* Arm the pre-allocated fences */
>  	for (i = 0; i < q->width; prev = fence, ++i) {
>  		struct dma_fence_chain *chain;
> @@ -286,6 +316,7 @@ void xe_sched_job_arm(struct xe_sched_job *job)
>  		fence = &chain->base;
>  	}
>  
> +arm:
>  	job->fence = dma_fence_get(fence);	/* Pairs with put in scheduler */
>  	drm_sched_job_arm(&job->drm);
>  }
> @@ -329,7 +360,7 @@ xe_sched_job_snapshot_capture(struct xe_sched_job *job)
>  
>  	snapshot->batch_addr_len = q->width;
>  	for (i = 0; i < q->width; i++)
> -		snapshot->batch_addr[i] =
> +		snapshot->batch_addr[i] = job->is_pt_job ? 0 :
>  			xe_device_uncanonicalize_addr(xe, job->ptrs[i].batch_addr);
>  
>  	return snapshot;
> diff --git a/drivers/gpu/drm/xe/xe_sched_job_types.h b/drivers/gpu/drm/xe/xe_sched_job_types.h
> index 0490b1247a6e..5e1824c36c74 100644
> --- a/drivers/gpu/drm/xe/xe_sched_job_types.h
> +++ b/drivers/gpu/drm/xe/xe_sched_job_types.h
> @@ -10,10 +10,29 @@
>  
>  #include <drm/gpu_scheduler.h>
>  
> -struct xe_exec_queue;
>  struct dma_fence;
>  struct dma_fence_chain;
>  
> +struct xe_exec_queue;
> +struct xe_migrate_pt_update_ops;
> +struct xe_pt_job_ops;
> +struct xe_tile;
> +struct xe_vm;
> +
> +/**
> + * struct xe_pt_update_args - PT update arguments
> + */
> +struct xe_pt_update_args {
> +	/** @vm: VM which is being bound */
> +	struct xe_vm *vm;
> +	/** @tile: Tile which page tables belong to */
> +	struct xe_tile *tile;
> +	/** @ops: Migrate PT update ops */
> +	const struct xe_migrate_pt_update_ops *ops;
> +	/** @pt_job_ops: PT job ops state */
> +	struct xe_pt_job_ops *pt_job_ops;
> +};
> +
>  /**
>   * struct xe_job_ptrs - Per hw engine instance data
>   */
> @@ -71,8 +90,14 @@ struct xe_sched_job {
>  	bool restore_replay;
>  	/** @last_replay: last job being replayed */
>  	bool last_replay;
> -	/** @ptrs: per instance pointers. */
> -	struct xe_job_ptrs ptrs[];
> +	/** @is_pt_job: is a PT job */
> +	bool is_pt_job;
> +	union {
> +		/** @ptrs: per instance pointers. */
> +		DECLARE_FLEX_ARRAY(struct xe_job_ptrs, ptrs);
> +		/** @pt_update: PT update arguments */
> +		DECLARE_FLEX_ARRAY(struct xe_pt_update_args, pt_update);
> +	};
>  };
>  
>  struct xe_sched_job_snapshot {
> diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
> index 2fe8f89a1e34..d4e9d91f6f7f 100644
> --- a/drivers/gpu/drm/xe/xe_trace.h
> +++ b/drivers/gpu/drm/xe/xe_trace.h
> @@ -261,7 +261,7 @@ DECLARE_EVENT_CLASS(xe_sched_job,
>  			   __entry->flags = job->q->flags;
>  			   __entry->error = job->fence ? job->fence->error : 0;
>  			   __entry->fence = job->fence;
> -			   __entry->batch_addr = (u64)job->ptrs[0].batch_addr;
> +			   __entry->batch_addr = job->is_pt_job ? 0 : (u64)job->ptrs[0].batch_addr;
>  			   ),
>  
>  		    TP_printk("dev=%s, fence=%p, seqno=%u, lrc_seqno=%u, gt=%u, guc_id=%d, batch_addr=0x%012llx, guc_state=0x%x, flags=0x%x, error=%d",
> -- 
> 2.34.1
> 

Re: [PATCH v6 07/24] drm/xe: Update scheduler job layer to support PT jobs

[Matthew Brost]

On Fri, Sep 11, 2026 at 05:24:23PM +0200, Francois Dugast wrote:
> On Fri, Sep 04, 2026 at 02:15:56PM -0700, Matthew Brost wrote:
> > Update the scheduler job layer to support PT jobs. PT jobs are executed
> > entirely on the CPU and do not require LRC fences or a batch address.
> > Repurpose the LRC fence storage to hold PT‑job arguments and update the
> > scheduler job layer to distinguish between PT jobs and jobs that require
> > an LRC.
> > 
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > Link: https://patch.msgid.link/20260228013501.106680-8-matthew.brost@intel.com
> > Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> > ---
> >  drivers/gpu/drm/xe/xe_sched_job.c       | 95 ++++++++++++++++---------
> >  drivers/gpu/drm/xe/xe_sched_job_types.h | 31 +++++++-
> >  drivers/gpu/drm/xe/xe_trace.h           |  2 +-
> >  3 files changed, 92 insertions(+), 36 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
> > index a4fa00632a30..841d67ebd5b0 100644
> > --- a/drivers/gpu/drm/xe/xe_sched_job.c
> > +++ b/drivers/gpu/drm/xe/xe_sched_job.c
> > @@ -26,19 +26,22 @@ static struct kmem_cache *xe_sched_job_parallel_slab;
> >  
> >  int __init xe_sched_job_module_init(void)
> >  {
> > +	struct xe_sched_job *job;
> > +	size_t size;
> > +
> > +	size = struct_size(job, ptrs, 1);
> >  	xe_sched_job_slab =
> > -		kmem_cache_create("xe_sched_job",
> > -				  sizeof(struct xe_sched_job) +
> > -				  sizeof(struct xe_job_ptrs), 0,
> > +		kmem_cache_create("xe_sched_job", size, 0,
> >  				  SLAB_HWCACHE_ALIGN, NULL);
> >  	if (!xe_sched_job_slab)
> >  		return -ENOMEM;
> >  
> > +	size = max_t(size_t,
> > +		     struct_size(job, ptrs,
> > +				 XE_HW_ENGINE_MAX_INSTANCE),
> > +		     struct_size(job, pt_update, 1));
> >  	xe_sched_job_parallel_slab =
> > -		kmem_cache_create("xe_sched_job_parallel",
> > -				  sizeof(struct xe_sched_job) +
> > -				  sizeof(struct xe_job_ptrs) *
> > -				  XE_HW_ENGINE_MAX_INSTANCE, 0,
> > +		kmem_cache_create("xe_sched_job_parallel", size, 0,
> >  				  SLAB_HWCACHE_ALIGN, NULL);
> >  	if (!xe_sched_job_parallel_slab) {
> >  		kmem_cache_destroy(xe_sched_job_slab);
> > @@ -84,6 +87,9 @@ static void xe_sched_job_free_fences(struct xe_sched_job *job)
> >  {
> >  	int i;
> >  
> > +	if (job->is_pt_job)
> > +		return;
> > +
> >  	for (i = 0; i < job->q->width; ++i) {
> >  		struct xe_job_ptrs *ptrs = &job->ptrs[i];
> >  
> > @@ -93,10 +99,23 @@ static void xe_sched_job_free_fences(struct xe_sched_job *job)
> >  	}
> >  }
> >  
> > +/**
> > + * xe_sched_job_create() - Create a scheduler job
> > + * @q: exec queue to create the scheduler job for
> > + * @batch_addr: array of batch addresses for the job; must match the width of
> > + * @q, or NULL to indicate a PT job that does not require a batch address
> > + *
> > + * Create a scheduler job for submission.
> > + *
> > + * Context: Reclaim
> > + *
> > + * Return: a &xe_sched_job object on success, or an ERR_PTR on failure.
> > + */
> >  struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
> >  					 u64 *batch_addr)
> >  {
> >  	bool is_migration = xe_sched_job_is_migration(q);
> > +	struct xe_device *xe = gt_to_xe(q->gt);
> >  	struct xe_sched_job *job;
> >  	int err;
> >  	int i;
> > @@ -105,6 +124,9 @@ struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
> >  	/* only a kernel context can submit a vm-less job */
> >  	XE_WARN_ON(!q->vm && !(q->flags & EXEC_QUEUE_FLAG_KERNEL));
> >  
> > +	xe_assert(xe, batch_addr ||
> > +		  q->flags & (EXEC_QUEUE_FLAG_VM | EXEC_QUEUE_FLAG_MIGRATE));
> > +
> >  	job = job_alloc(xe_exec_queue_is_parallel(q) || is_migration);
> >  	if (!job)
> >  		return ERR_PTR(-ENOMEM);
> > @@ -119,34 +141,39 @@ struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q,
> >  	if (err)
> >  		goto err_free;
> >  
> > -	for (i = 0; i < q->width; ++i) {
> > -		struct dma_fence *fence = xe_lrc_alloc_seqno_fence();
> > -		struct dma_fence_chain *chain;
> > -
> > -		if (IS_ERR(fence)) {
> > -			err = PTR_ERR(fence);
> > -			goto err_sched_job;
> > +	if (!batch_addr) {
> > +		job->fence = dma_fence_get_stub();
> > +		job->is_pt_job = true;
> > +	} else {
> > +		for (i = 0; i < q->width; ++i) {
> > +			struct dma_fence *fence = xe_lrc_alloc_seqno_fence();
> > +			struct dma_fence_chain *chain;
> > +
> > +			if (IS_ERR(fence)) {
> > +				err = PTR_ERR(fence);
> > +				goto err_sched_job;
> > +			}
> > +			job->ptrs[i].lrc_fence = fence;
> > +
> > +			if (i + 1 == q->width)
> > +				continue;
> > +
> > +			chain = dma_fence_chain_alloc();
> > +			if (!chain) {
> > +				err = -ENOMEM;
> > +				goto err_sched_job;
> > +			}
> > +			job->ptrs[i].chain_fence = chain;
> >  		}
> > -		job->ptrs[i].lrc_fence = fence;
> >  
> > -		if (i + 1 == q->width)
> > -			continue;
> > +		width = q->width;
> > +		if (is_migration)
> > +			width = 2;
> >  
> > -		chain = dma_fence_chain_alloc();
> > -		if (!chain) {
> > -			err = -ENOMEM;
> > -			goto err_sched_job;
> > -		}
> > -		job->ptrs[i].chain_fence = chain;
> > +		for (i = 0; i < width; ++i)
> > +			job->ptrs[i].batch_addr = batch_addr[i];
> >  	}
> >  
> > -	width = q->width;
> > -	if (is_migration)
> > -		width = 2;
> > -
> > -	for (i = 0; i < width; ++i)
> > -		job->ptrs[i].batch_addr = batch_addr[i];
> > -
> >  	atomic_inc(&q->job_cnt);
> >  	xe_pm_runtime_get_noresume(job_to_xe(job));
> >  	trace_xe_sched_job_create(job);
> > @@ -246,7 +273,7 @@ bool xe_sched_job_completed(struct xe_sched_job *job)
> >  void xe_sched_job_arm(struct xe_sched_job *job)
> >  {
> >  	struct xe_exec_queue *q = job->q;
> > -	struct dma_fence *fence, *prev;
> > +	struct dma_fence *fence = job->fence, *prev;
> >  	struct xe_vm *vm = q->vm;
> >  	u64 seqno = 0;
> >  	int i;
> > @@ -266,6 +293,9 @@ void xe_sched_job_arm(struct xe_sched_job *job)
> >  		job->ring_ops_flush_tlb = true;
> >  	}
> >  
> > +	if (job->is_pt_job)
> > +		goto arm;
> > +
> 
> I think Sashiko's warning is valid, we should move this ^ one block
> above to skip touching q->tlb_flush_seqno and ring_ops_flush_tlb for
> PT jobs.
> 

Those are completely unused for PT jobs / queues which run PT jobs so
the ordering is harmless but for clarity it would be better. Will
adjust.

Matt 

> Francois
> 
> >  	/* Arm the pre-allocated fences */
> >  	for (i = 0; i < q->width; prev = fence, ++i) {
> >  		struct dma_fence_chain *chain;
> > @@ -286,6 +316,7 @@ void xe_sched_job_arm(struct xe_sched_job *job)
> >  		fence = &chain->base;
> >  	}
> >  
> > +arm:
> >  	job->fence = dma_fence_get(fence);	/* Pairs with put in scheduler */
> >  	drm_sched_job_arm(&job->drm);
> >  }
> > @@ -329,7 +360,7 @@ xe_sched_job_snapshot_capture(struct xe_sched_job *job)
> >  
> >  	snapshot->batch_addr_len = q->width;
> >  	for (i = 0; i < q->width; i++)
> > -		snapshot->batch_addr[i] =
> > +		snapshot->batch_addr[i] = job->is_pt_job ? 0 :
> >  			xe_device_uncanonicalize_addr(xe, job->ptrs[i].batch_addr);
> >  
> >  	return snapshot;
> > diff --git a/drivers/gpu/drm/xe/xe_sched_job_types.h b/drivers/gpu/drm/xe/xe_sched_job_types.h
> > index 0490b1247a6e..5e1824c36c74 100644
> > --- a/drivers/gpu/drm/xe/xe_sched_job_types.h
> > +++ b/drivers/gpu/drm/xe/xe_sched_job_types.h
> > @@ -10,10 +10,29 @@
> >  
> >  #include <drm/gpu_scheduler.h>
> >  
> > -struct xe_exec_queue;
> >  struct dma_fence;
> >  struct dma_fence_chain;
> >  
> > +struct xe_exec_queue;
> > +struct xe_migrate_pt_update_ops;
> > +struct xe_pt_job_ops;
> > +struct xe_tile;
> > +struct xe_vm;
> > +
> > +/**
> > + * struct xe_pt_update_args - PT update arguments
> > + */
> > +struct xe_pt_update_args {
> > +	/** @vm: VM which is being bound */
> > +	struct xe_vm *vm;
> > +	/** @tile: Tile which page tables belong to */
> > +	struct xe_tile *tile;
> > +	/** @ops: Migrate PT update ops */
> > +	const struct xe_migrate_pt_update_ops *ops;
> > +	/** @pt_job_ops: PT job ops state */
> > +	struct xe_pt_job_ops *pt_job_ops;
> > +};
> > +
> >  /**
> >   * struct xe_job_ptrs - Per hw engine instance data
> >   */
> > @@ -71,8 +90,14 @@ struct xe_sched_job {
> >  	bool restore_replay;
> >  	/** @last_replay: last job being replayed */
> >  	bool last_replay;
> > -	/** @ptrs: per instance pointers. */
> > -	struct xe_job_ptrs ptrs[];
> > +	/** @is_pt_job: is a PT job */
> > +	bool is_pt_job;
> > +	union {
> > +		/** @ptrs: per instance pointers. */
> > +		DECLARE_FLEX_ARRAY(struct xe_job_ptrs, ptrs);
> > +		/** @pt_update: PT update arguments */
> > +		DECLARE_FLEX_ARRAY(struct xe_pt_update_args, pt_update);
> > +	};
> >  };
> >  
> >  struct xe_sched_job_snapshot {
> > diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
> > index 2fe8f89a1e34..d4e9d91f6f7f 100644
> > --- a/drivers/gpu/drm/xe/xe_trace.h
> > +++ b/drivers/gpu/drm/xe/xe_trace.h
> > @@ -261,7 +261,7 @@ DECLARE_EVENT_CLASS(xe_sched_job,
> >  			   __entry->flags = job->q->flags;
> >  			   __entry->error = job->fence ? job->fence->error : 0;
> >  			   __entry->fence = job->fence;
> > -			   __entry->batch_addr = (u64)job->ptrs[0].batch_addr;
> > +			   __entry->batch_addr = job->is_pt_job ? 0 : (u64)job->ptrs[0].batch_addr;
> >  			   ),
> >  
> >  		    TP_printk("dev=%s, fence=%p, seqno=%u, lrc_seqno=%u, gt=%u, guc_id=%d, batch_addr=0x%012llx, guc_state=0x%x, flags=0x%x, error=%d",
> > -- 
> > 2.34.1
> > 

Re: [PATCH v6 06/24] drm/xe: Add XE_BO_FLAG_PUT_VM_ASYNC

[Matthew Brost]

On Fri, Sep 11, 2026 at 03:10:48PM +0200, Francois Dugast wrote:
> On Fri, Sep 04, 2026 at 02:15:55PM -0700, Matthew Brost wrote:
> > Add XE_BO_FLAG_PUT_VM_ASYNC, which indicates that an async BO put must
> > also drop an additional reference to the BO’s VM. This is useful when a
> > kernel BO, one that does not normally hold a VM reference, needs to be
> > put asynchronously, ensuring the shared dma-resv object does not
> > disappear before the BO.
> > 
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > Link: https://patch.msgid.link/20260228013501.106680-7-matthew.brost@intel.com
> > Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> > ---
> >  drivers/gpu/drm/xe/xe_bo.c | 8 +++++++-
> >  drivers/gpu/drm/xe/xe_bo.h | 1 +
> >  2 files changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> > index b162753cebb7..aea4b0fee8e3 100644
> > --- a/drivers/gpu/drm/xe/xe_bo.c
> > +++ b/drivers/gpu/drm/xe/xe_bo.c
> > @@ -3998,8 +3998,14 @@ void xe_bo_put_commit(struct llist_head *deferred)
> >  	if (!freed)
> >  		return;
> >  
> > -	llist_for_each_entry_safe(bo, next, freed, freed)
> > +	llist_for_each_entry_safe(bo, next, freed, freed) {
> > +		struct xe_vm *vm = bo->vm;
> > +		bool async = bo->flags & XE_BO_FLAG_PUT_VM_ASYNC;
> > +
> >  		drm_gem_object_free(&bo->ttm.base.refcount);
> > +		if (async)
> > +			xe_vm_put(vm);
> 
> You had mentioned reworking this part:
> https://patchwork.freedesktop.org/patch/750807/?series=149888&rev=6#comment_1383757
> 

I reworked the PT BO reference count reinitialization in the PT layer. The
Sashiko feedback was not correct in its original context, but it was
right that transitioning a BO reference count from zero to one on the
driver side is unsafe.

This change follows patch [1] in xe_pt_destroy. Compare it to the prior
revision [2]; note that the kref_init in [2] is gone in [1].

[1] https://patchwork.freedesktop.org/patch/751032/?series=149888&rev=8
[2] https://patchwork.freedesktop.org/patch/750792/?series=149888&rev=6

Wrt. the comment about ttm_bo_individualize_resv() failing, if that occurs
in ttm_bo_release() (we get here from drm_gem_object_free()), the fences
are waited on directly before returning. See the dma_resv_wait_timeout()
for 30 seconds, after which the BO is destroyed inline if VM lock can be
taken. I guess the VM lock can fall on a trylock, triggering the delayed
worker...

We could look at PT BOs holding a VM reference until xe_ttm_bo_destroy(),
similar to user BOs, but there is some convoluted reason why only user BOs
have held a VM reference from early on in Xe that may or may not still
be true. Let me see if I can make this work as after typing this out it
seems like an extreme corner case of posisble memory safety bug. 

Thanks,
Matt

> Sashiko seems consistent here.
> 
> Francois
> 
> > +	}
> >  }
> >  
> >  static void xe_bo_dev_work_func(struct work_struct *work)
> > diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
> > index 01975586ee88..2168aac1ed1e 100644
> > --- a/drivers/gpu/drm/xe/xe_bo.h
> > +++ b/drivers/gpu/drm/xe/xe_bo.h
> > @@ -54,6 +54,7 @@
> >  #define XE_BO_FLAG_FORCE_USER_VRAM	BIT(25)
> >  #define XE_BO_FLAG_NO_COMPRESSION	BIT(26)
> >  #define XE_BO_FLAG_NEEDS_1G		BIT(27)
> > +#define XE_BO_FLAG_PUT_VM_ASYNC		BIT(28)
> >  
> >  /* this one is trigger internally only */
> >  #define XE_BO_FLAG_INTERNAL_TEST	BIT(30)
> > -- 
> > 2.34.1
> > 

Re: [PATCH v6 06/24] drm/xe: Add XE_BO_FLAG_PUT_VM_ASYNC

[Matthew Brost]

On Fri, Sep 11, 2026 at 12:54:19PM -0700, Matthew Brost wrote:
> On Fri, Sep 11, 2026 at 03:10:48PM +0200, Francois Dugast wrote:
> > On Fri, Sep 04, 2026 at 02:15:55PM -0700, Matthew Brost wrote:
> > > Add XE_BO_FLAG_PUT_VM_ASYNC, which indicates that an async BO put must
> > > also drop an additional reference to the BO’s VM. This is useful when a
> > > kernel BO, one that does not normally hold a VM reference, needs to be
> > > put asynchronously, ensuring the shared dma-resv object does not
> > > disappear before the BO.
> > > 
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > Link: https://patch.msgid.link/20260228013501.106680-7-matthew.brost@intel.com
> > > Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> > > ---
> > >  drivers/gpu/drm/xe/xe_bo.c | 8 +++++++-
> > >  drivers/gpu/drm/xe/xe_bo.h | 1 +
> > >  2 files changed, 8 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> > > index b162753cebb7..aea4b0fee8e3 100644
> > > --- a/drivers/gpu/drm/xe/xe_bo.c
> > > +++ b/drivers/gpu/drm/xe/xe_bo.c
> > > @@ -3998,8 +3998,14 @@ void xe_bo_put_commit(struct llist_head *deferred)
> > >  	if (!freed)
> > >  		return;
> > >  
> > > -	llist_for_each_entry_safe(bo, next, freed, freed)
> > > +	llist_for_each_entry_safe(bo, next, freed, freed) {
> > > +		struct xe_vm *vm = bo->vm;
> > > +		bool async = bo->flags & XE_BO_FLAG_PUT_VM_ASYNC;
> > > +
> > >  		drm_gem_object_free(&bo->ttm.base.refcount);
> > > +		if (async)
> > > +			xe_vm_put(vm);
> > 
> > You had mentioned reworking this part:
> > https://patchwork.freedesktop.org/patch/750807/?series=149888&rev=6#comment_1383757
> > 
> 
> I reworked the PT BO reference count reinitialization in the PT layer. The
> Sashiko feedback was not correct in its original context, but it was
> right that transitioning a BO reference count from zero to one on the
> driver side is unsafe.
> 
> This change follows patch [1] in xe_pt_destroy. Compare it to the prior
> revision [2]; note that the kref_init in [2] is gone in [1].
> 
> [1] https://patchwork.freedesktop.org/patch/751032/?series=149888&rev=8
> [2] https://patchwork.freedesktop.org/patch/750792/?series=149888&rev=6
> 
> Wrt. the comment about ttm_bo_individualize_resv() failing, if that occurs
> in ttm_bo_release() (we get here from drm_gem_object_free()), the fences
> are waited on directly before returning. See the dma_resv_wait_timeout()
> for 30 seconds, after which the BO is destroyed inline if VM lock can be
> taken. I guess the VM lock can fall on a trylock, triggering the delayed
> worker...
> 
> We could look at PT BOs holding a VM reference until xe_ttm_bo_destroy(),
> similar to user BOs, but there is some convoluted reason why only user BOs
> have held a VM reference from early on in Xe that may or may not still
> be true. Let me see if I can make this work as after typing this out it
> seems like an extreme corner case of posisble memory safety bug. 

It is also worth noting Christian's series here [3] is actually the proper
way to ensure what Sashiko is flagging isn't possible - ref count the
dma-resv. Hopefully we get Christian's series in soon as it nice a
cleanup and makes dma-resv sharing betweens BOs inherently safe +
ownership clear.

Matt

[3] https://patchwork.freedesktop.org/series/173312/

> 
> Thanks,
> Matt
> 
> > Sashiko seems consistent here.
> > 
> > Francois
> > 
> > > +	}
> > >  }
> > >  
> > >  static void xe_bo_dev_work_func(struct work_struct *work)
> > > diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
> > > index 01975586ee88..2168aac1ed1e 100644
> > > --- a/drivers/gpu/drm/xe/xe_bo.h
> > > +++ b/drivers/gpu/drm/xe/xe_bo.h
> > > @@ -54,6 +54,7 @@
> > >  #define XE_BO_FLAG_FORCE_USER_VRAM	BIT(25)
> > >  #define XE_BO_FLAG_NO_COMPRESSION	BIT(26)
> > >  #define XE_BO_FLAG_NEEDS_1G		BIT(27)
> > > +#define XE_BO_FLAG_PUT_VM_ASYNC		BIT(28)
> > >  
> > >  /* this one is trigger internally only */
> > >  #define XE_BO_FLAG_INTERNAL_TEST	BIT(30)
> > > -- 
> > > 2.34.1
> > >