From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: "sashiko-reviews@lists.linux.dev" <sashiko-reviews@lists.linux.dev>
Cc: "maz@kernel.org" <maz@kernel.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"oupton@kernel.org" <oupton@kernel.org>, nd <nd@arm.com>
Subject: Re: [PATCH v3 14/40] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells
Date: Wed, 8 Jul 2026 14:56:26 +0000 [thread overview]
Message-ID: <83bfe680be3dd3fe6199790de0fea09e02638932.camel@arm.com> (raw)
In-Reply-To: <20260703162738.4DA701F000E9@smtp.kernel.org>
On Fri, 2026-07-03 at 16:27 +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential
> issue(s) to consider:
> - [High] Early returns in `vgic_v5_teardown()` on hardware command
> failure skip software cleanup, leaking doorbell IRQs and causing a
> Use-After-Free of VCPU structures.
> --
>
> commit 0e7cc2cc83975127589c6dbceb977e9f1bd837a2
> Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
>
> KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells
>
> This commit introduces the initialization and teardown paths for
> GICv5 VM Table
> Entries and VPE doorbells. It allocates a VM ID, configures a per-VM
> doorbell
> IRQ domain, and creates handlers for managing doorbell interrupts per
> VCPU.
>
> > diff --git a/arch/arm64/kvm/vgic/vgic-v5.c
> > b/arch/arm64/kvm/vgic/vgic-v5.c
> > index 6d7d9e6ed9dbf..f1cc36696669d 100644
> > --- a/arch/arm64/kvm/vgic/vgic-v5.c
> > +++ b/arch/arm64/kvm/vgic/vgic-v5.c
>
> [ ... ]
>
> > +void vgic_v5_teardown(struct kvm *kvm)
> > +{
> > + struct vgic_dist *dist = &kvm->arch.vgic;
> > + struct kvm_vcpu *vcpu, *vcpu0;
> > + unsigned long i;
> > + int rc;
> > +
> > + /*
> > + * If the VM's ID isn't valid, then we either failed init
> > very early or
> > + * we've been called a second time. Nothing to do here in
> > either case.
> > + */
> > + if (kvm->arch.vgic.gicv5_vm.vm_id == VGIC_V5_VM_ID_INVAL)
> > + return;
> > +
> > + if (kvm->arch.vgic.gicv5_vm.vmte_allocated) {
> > + /* Make the VM invalid */
> > + vcpu0 = kvm_get_vcpu(kvm, 0);
> > + rc = vgic_v5_send_command(vcpu0,
> > VMTE_MAKE_INVALID);
> > + if (rc) {
> > + kvm_err("could not make VMTE invalid\n");
> > + return;
>
> [Severity: High]
> If the hardware command fails, this early return skips the rest of
> the
> software cleanup including vgic_v5_free_doorbells(). The same applies
> to the
> early return below if vgic_v5_vmte_release() fails.
>
> If this happens during VM destruction, the VCPU structures will
> eventually
> be freed. Since the doorbell IRQs are left active and registered with
> the
> VCPU pointers, could a subsequent hardware doorbell IRQ fire and
> cause
> db_handler() to write to the freed VCPU pointer, leading to a
> use-after-free?
>
> Is it possible to continue tearing down the software resources (like
> freeing the doorbells) even if the hardware invalidation or release
> fails?
Right, that's actually a good point. I've reworked this to always free
the doorbells, even if other bits of the teardown fail.
I hope that we're never going to be in this situation as it implies
broken hardware, but it is always better to not leave dangling pointers
around.
>
> > + }
> > +
> > + kvm_for_each_vcpu(i, vcpu, kvm) {
> > + if (vgic_v5_vmte_free_vpe(vcpu))
> > + kvm_err("Failed to free VPE\n");
> > + }
> > +
> > + if (vgic_v5_vmte_release(kvm)) {
> > + kvm_err("Failed to release VM 0x%x\n",
> > dist->gicv5_vm.vm_id);
> > + return;
> > + }
> > + }
> > +
> > + vgic_v5_free_doorbells(kvm, atomic_read(&kvm-
> > >online_vcpus));
>
Thanks,
Sascha
next prev parent reply other threads:[~2026-07-08 14:57 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-03 15:50 [PATCH v3 00/40] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-03 15:51 ` [PATCH v3 01/40] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-03 16:33 ` sashiko-bot
2026-07-07 12:30 ` Sascha Bischoff
2026-07-03 15:51 ` [PATCH v3 02/40] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-03 16:24 ` sashiko-bot
2026-07-07 12:48 ` Sascha Bischoff
2026-07-03 15:52 ` [PATCH v3 03/40] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-03 15:52 ` [PATCH v3 04/40] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-03 15:53 ` [PATCH v3 05/40] arm64/sysreg: Add GICv5 GIC VDPEND and VDRCFG encodings Sascha Bischoff
2026-07-03 16:28 ` sashiko-bot
2026-07-07 14:28 ` Sascha Bischoff
2026-07-03 15:53 ` [PATCH v3 06/40] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-03 16:22 ` sashiko-bot
2026-07-07 15:08 ` Sascha Bischoff
2026-07-03 15:54 ` [PATCH v3 07/40] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-03 15:54 ` [PATCH v3 08/40] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-03 16:25 ` sashiko-bot
2026-07-07 15:11 ` Sascha Bischoff
2026-07-03 15:55 ` [PATCH v3 09/40] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-03 16:31 ` sashiko-bot
2026-07-08 14:44 ` Sascha Bischoff
2026-07-03 15:55 ` [PATCH v3 10/40] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-03 16:34 ` sashiko-bot
2026-07-08 14:46 ` Sascha Bischoff
2026-07-03 15:56 ` [PATCH v3 11/40] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-03 16:39 ` sashiko-bot
2026-07-08 14:49 ` Sascha Bischoff
2026-07-03 15:56 ` [PATCH v3 12/40] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-03 15:57 ` [PATCH v3 13/40] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-03 16:26 ` sashiko-bot
2026-07-08 14:53 ` Sascha Bischoff
2026-07-03 15:57 ` [PATCH v3 14/40] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-03 16:27 ` sashiko-bot
2026-07-08 14:56 ` Sascha Bischoff [this message]
2026-07-03 15:58 ` [PATCH v3 15/40] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-03 16:23 ` sashiko-bot
2026-07-08 15:00 ` Sascha Bischoff
2026-07-03 15:58 ` [PATCH v3 16/40] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-03 16:35 ` sashiko-bot
2026-07-08 15:35 ` Sascha Bischoff
2026-07-03 15:59 ` [PATCH v3 17/40] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-03 15:59 ` [PATCH v3 18/40] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-03 16:00 ` [PATCH v3 19/40] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-03 16:00 ` [PATCH v3 20/40] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-03 16:38 ` sashiko-bot
2026-07-03 16:01 ` [PATCH v3 21/40] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-03 16:01 ` [PATCH v3 22/40] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-03 16:47 ` sashiko-bot
2026-07-03 16:02 ` [PATCH v3 23/40] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-03 16:34 ` sashiko-bot
2026-07-03 16:02 ` [PATCH v3 24/40] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-03 16:03 ` [PATCH v3 25/40] KVM: arm64: gic-v5: Introduce SPI AP list Sascha Bischoff
2026-07-03 16:03 ` [PATCH v3 26/40] KVM: arm64: gic-v5: Add GIC VDPEND and GIC VDRCFG hyp calls Sascha Bischoff
2026-07-03 16:31 ` sashiko-bot
2026-07-03 16:04 ` [PATCH v3 27/40] KVM: arm64: gic-v5: Track SPI state for in-flight SPIs Sascha Bischoff
2026-07-03 16:41 ` sashiko-bot
2026-07-03 16:04 ` [PATCH v3 28/40] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-03 16:32 ` sashiko-bot
2026-07-03 16:05 ` [PATCH v3 29/40] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-03 16:53 ` sashiko-bot
2026-07-03 16:05 ` [PATCH v3 30/40] Documentation: KVM: Extend VGICv5 docs for KVM_VGIC_V5_ADDR_TYPE_IRS Sascha Bischoff
2026-07-03 16:27 ` sashiko-bot
2026-07-03 16:06 ` [PATCH v3 31/40] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-07-03 16:36 ` sashiko-bot
2026-07-03 16:06 ` [PATCH v3 32/40] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-07-03 16:07 ` [PATCH v3 33/40] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-07-03 16:07 ` [PATCH v3 34/40] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-07-03 16:42 ` sashiko-bot
2026-07-03 16:08 ` [PATCH v3 35/40] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-07-03 16:41 ` sashiko-bot
2026-07-03 16:08 ` [PATCH v3 36/40] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-07-03 16:43 ` sashiko-bot
2026-07-03 16:09 ` [PATCH v3 37/40] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-07-03 16:36 ` sashiko-bot
2026-07-03 16:09 ` [PATCH v3 38/40] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-07-03 16:37 ` sashiko-bot
2026-07-03 16:10 ` [PATCH v3 39/40] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-07-03 16:10 ` [PATCH v3 40/40] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-07-03 16:33 ` sashiko-bot
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