From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: "sashiko-reviews@lists.linux.dev" <sashiko-reviews@lists.linux.dev>
Cc: "maz@kernel.org" <maz@kernel.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"oupton@kernel.org" <oupton@kernel.org>, nd <nd@arm.com>
Subject: Re: [PATCH v5 19/49] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI
Date: Fri, 4 Sep 2026 08:42:46 +0000 [thread overview]
Message-ID: <bfc53cc46cd7f1e2901ec1afa0e5a30335cbe036.camel@arm.com> (raw)
In-Reply-To: <20260807142757.784E41F00A3A@smtp.kernel.org>
On Fri, 2026-08-07 at 14:27 +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential
> issue(s) to consider:
> - [High] The patch defines the UAPI constant
> KVM_VGIC_V5_ADDR_TYPE_IRS for userspace to specify the IRS location,
> but provides no corresponding kernel implementation to handle it.
> - [Low] The newly added UAPI macro KVM_VGIC_V5_IRS_SIZE uses the
> kernel-internal macro SZ_64K, which is not exported to userspace and
> will cause compilation errors.
> --
>
> --- Patch [19]: [PATCH v5 19/49] KVM: arm64: gic-v5: Add
> KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI ---
> commit 2deebb3b97ce3e2f88f0cdf0452104edbd0a7ea6
> Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
>
> KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI
>
> This patch adds the UAPI definitions for the GICv5 IRS address type
> and size
> to the arm64 KVM headers. It reserves 2x64kB in the GPA space for the
> IRS
> CONFIG_FRAME and SETLPI_FRAME.
>
> > diff --git a/arch/arm64/include/uapi/asm/kvm.h
> > b/arch/arm64/include/uapi/asm/kvm.h
> > index 1c13bfa2d38aa..d1b2ca317f586 100644
> > --- a/arch/arm64/include/uapi/asm/kvm.h
> > +++ b/arch/arm64/include/uapi/asm/kvm.h
> [ ... ]
> > @@ -97,6 +97,11 @@ struct kvm_regs {
> > #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
> > #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
> >
> > +/* Supported VGICv5 address types */
> > +#define KVM_VGIC_V5_ADDR_TYPE_IRS 6
> > +
>
> [Severity: High]
> Does this patch provide the kernel implementation to handle
> KVM_VGIC_V5_ADDR_TYPE_IRS?
No, it does not.
>
> If userspace attempts to use this UAPI definition with the
> KVM_DEV_ARM_VGIC_GRP_ADDR attribute group, vgic_v5_set_attr()
> explicitly
> returns -ENXIO for that group:
>
> arch/arm64/kvm/vgic/vgic-kvm-device.c:vgic_v5_set_attr() {
> switch (attr->group) {
> case KVM_DEV_ARM_VGIC_GRP_ADDR:
> case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS:
> case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
> return -ENXIO;
> ...
> }
>
> Similarly, kvm_vgic_addr() lacks a case for KVM_VGIC_V5_ADDR_TYPE_IRS
> and
> would reject it with -ENODEV:
>
> arch/arm64/kvm/vgic/vgic-kvm-device.c:kvm_vgic_addr() {
> ...
> default:
> r = -ENODEV;
> }
> ...
> }
>
> Without handling in the kernel, userspace cannot configure the base
> address
> of the GICv5 IRS, which renders the GICv5 IRS emulation feature
> unusable.
See next commits in series.
>
> > +#define KVM_VGIC_V5_IRS_SIZE (2 * SZ_64K)
> > +
>
> [Severity: Low]
> Does this newly added UAPI definition rely on the kernel-internal
> macro
> SZ_64K?
This matches the existing defines for GICv3. I don't think that this is
an issue.
>
> Since <linux/sizes.h> is not exported to userspace, userspace
> programs
> attempting to use KVM_VGIC_V5_IRS_SIZE will fail to compile with an
> undeclared identifier error for SZ_64K.
>
> While this pattern already exists in the file for GICv3 sizes,
> introducing a
> new instance perpetuates the UAPI breakage.
>
> > #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF
> > state */
> > #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit
> > VM */
> > #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
> > diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h
> > b/tools/arch/arm64/include/uapi/asm/kvm.h
> > index 1c13bfa2d38aa..d1b2ca317f586 100644
> > --- a/tools/arch/arm64/include/uapi/asm/kvm.h
> > +++ b/tools/arch/arm64/include/uapi/asm/kvm.h
> [ ... ]
> > @@ -97,6 +97,11 @@ struct kvm_regs {
> > #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
> > #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
> >
> > +/* Supported VGICv5 address types */
> > +#define KVM_VGIC_V5_ADDR_TYPE_IRS 6
> > +
> > +#define KVM_VGIC_V5_IRS_SIZE (2 * SZ_64K)
> > +
>
> [Severity: Low]
> Are the same SZ_64K and missing implementation issues applicable to
> this
> mirrored tools UAPI header?
See above.
>
> > #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF
> > state */
> > #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit
> > VM */
> > #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
>
Thanks,
Sascha
next prev parent reply other threads:[~2026-09-04 8:43 UTC|newest]
Thread overview: 118+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-07 11:12 [PATCH v5 00/49] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-08-07 11:13 ` [PATCH v5 01/49] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-08-07 11:13 ` [PATCH v5 02/49] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-08-07 11:53 ` sashiko-bot
2026-09-03 14:20 ` Sascha Bischoff
2026-08-07 11:14 ` [PATCH v5 03/49] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-08-07 12:01 ` sashiko-bot
2026-09-03 14:22 ` Sascha Bischoff
2026-08-07 13:44 ` Lorenzo Pieralisi
2026-09-03 14:25 ` Sascha Bischoff
2026-08-07 11:14 ` [PATCH v5 04/49] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-08-07 12:05 ` sashiko-bot
2026-09-03 14:34 ` Sascha Bischoff
2026-08-07 11:15 ` [PATCH v5 05/49] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-08-07 11:15 ` [PATCH v5 06/49] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-08-07 12:17 ` sashiko-bot
2026-09-03 16:33 ` Sascha Bischoff
2026-08-07 11:16 ` [PATCH v5 07/49] KVM: arm64: gic-v5: Cache host IRS ID registers Sascha Bischoff
2026-08-07 12:27 ` sashiko-bot
2026-09-04 6:36 ` Sascha Bischoff
2026-08-07 11:16 ` [PATCH v5 08/49] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-08-07 12:45 ` sashiko-bot
2026-09-04 7:27 ` Sascha Bischoff
2026-08-07 11:17 ` [PATCH v5 09/49] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-08-07 12:50 ` sashiko-bot
2026-09-04 8:00 ` Sascha Bischoff
2026-08-07 11:17 ` [PATCH v5 10/49] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-08-07 13:07 ` sashiko-bot
2026-09-04 8:08 ` Sascha Bischoff
2026-08-07 11:18 ` [PATCH v5 11/49] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-08-07 13:13 ` sashiko-bot
2026-09-04 8:15 ` Sascha Bischoff
2026-08-07 11:18 ` [PATCH v5 12/49] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-08-07 13:30 ` sashiko-bot
2026-09-04 10:03 ` Sascha Bischoff
2026-08-07 11:19 ` [PATCH v5 13/49] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-08-07 11:19 ` [PATCH v5 14/49] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-08-07 13:42 ` sashiko-bot
2026-09-04 8:22 ` Sascha Bischoff
2026-08-07 11:20 ` [PATCH v5 15/49] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-08-07 11:20 ` [PATCH v5 16/49] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-08-07 14:17 ` sashiko-bot
2026-09-04 8:31 ` Sascha Bischoff
2026-08-07 11:21 ` [PATCH v5 17/49] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-08-07 11:21 ` [PATCH v5 18/49] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-08-07 11:22 ` [PATCH v5 19/49] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-08-07 14:27 ` sashiko-bot
2026-09-04 8:42 ` Sascha Bischoff [this message]
2026-08-07 11:22 ` [PATCH v5 20/49] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-08-07 14:34 ` sashiko-bot
2026-09-04 8:47 ` Sascha Bischoff
2026-08-07 11:23 ` [PATCH v5 21/49] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-08-07 14:49 ` sashiko-bot
2026-09-04 8:51 ` Sascha Bischoff
2026-08-07 11:23 ` [PATCH v5 22/49] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-08-07 14:52 ` sashiko-bot
2026-09-04 8:57 ` Sascha Bischoff
2026-08-07 11:24 ` [PATCH v5 23/49] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-08-07 11:24 ` [PATCH v5 24/49] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-08-07 15:04 ` sashiko-bot
2026-09-04 9:03 ` Sascha Bischoff
2026-08-07 11:25 ` [PATCH v5 25/49] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-08-07 11:25 ` [PATCH v5 26/49] KVM: arm64: gic: Introduce set_pending_state() to irq_ops Sascha Bischoff
2026-08-07 15:14 ` sashiko-bot
2026-09-04 9:28 ` Sascha Bischoff
2026-08-07 11:26 ` [PATCH v5 27/49] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-08-07 15:23 ` sashiko-bot
2026-09-04 9:22 ` Sascha Bischoff
2026-08-07 11:26 ` [PATCH v5 28/49] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-08-07 15:29 ` sashiko-bot
2026-09-04 9:30 ` Sascha Bischoff
2026-08-07 11:27 ` [PATCH v5 29/49] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-08-07 15:40 ` sashiko-bot
2026-09-04 9:47 ` Sascha Bischoff
2026-08-07 11:27 ` [PATCH v5 30/49] KVM: arm64: gic-v5: Mask per-vCPU PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-08-07 11:28 ` [PATCH v5 31/49] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-08-07 16:27 ` sashiko-bot
2026-09-04 10:01 ` Sascha Bischoff
2026-08-07 11:28 ` [PATCH v5 32/49] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-08-07 16:20 ` sashiko-bot
2026-09-04 9:59 ` Sascha Bischoff
2026-08-07 11:29 ` [PATCH v5 33/49] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-08-07 11:29 ` [PATCH v5 34/49] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-08-07 16:30 ` sashiko-bot
2026-09-04 10:06 ` Sascha Bischoff
2026-08-07 11:30 ` [PATCH v5 35/49] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-08-07 16:48 ` sashiko-bot
2026-09-04 10:23 ` Sascha Bischoff
2026-08-07 11:30 ` [PATCH v5 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-08-07 16:55 ` sashiko-bot
2026-09-04 11:04 ` Sascha Bischoff
2026-08-07 11:31 ` [PATCH v5 37/49] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-08-07 16:52 ` sashiko-bot
2026-09-04 10:09 ` Sascha Bischoff
2026-08-07 11:31 ` [PATCH v5 38/49] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-08-07 11:32 ` [PATCH v5 39/49] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-08-07 11:32 ` [PATCH v5 40/49] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-08-07 11:33 ` [PATCH v5 41/49] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-08-07 17:12 ` sashiko-bot
2026-09-04 10:15 ` Sascha Bischoff
2026-08-07 11:33 ` [PATCH v5 42/49] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-08-07 17:17 ` sashiko-bot
2026-09-04 10:38 ` Sascha Bischoff
2026-08-07 11:34 ` [PATCH v5 43/49] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-08-07 17:21 ` sashiko-bot
2026-09-04 10:45 ` Sascha Bischoff
2026-08-07 11:35 ` [PATCH v5 44/49] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-08-07 11:35 ` [PATCH v5 45/49] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-08-07 11:36 ` [PATCH v5 46/49] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-08-07 11:36 ` [PATCH v5 47/49] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-08-07 17:39 ` sashiko-bot
2026-09-04 10:48 ` Sascha Bischoff
2026-08-07 11:37 ` [PATCH v5 48/49] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
2026-08-07 17:50 ` sashiko-bot
2026-09-04 10:54 ` Sascha Bischoff
2026-08-07 11:37 ` [PATCH v5 49/49] KVM: selftests: Add VGICv5 sparse vCPU IDs test Sascha Bischoff
2026-08-07 17:56 ` sashiko-bot
2026-09-04 10:57 ` Sascha Bischoff
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