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From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: "lpieralisi@kernel.org" <lpieralisi@kernel.org>
Cc: "yuzenghui@huawei.com" <yuzenghui@huawei.com>,
	"fuad.tabba@linux.dev" <fuad.tabba@linux.dev>,
	Timothy Hayes <Timothy.Hayes@arm.com>,
	Suzuki Poulose <Suzuki.Poulose@arm.com>, nd <nd@arm.com>,
	"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
	"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	Joey Gouly <Joey.Gouly@arm.com>,
	"maz@kernel.org" <maz@kernel.org>,
	"oliver.upton@linux.dev" <oliver.upton@linux.dev>
Subject: Re: [PATCH v5 03/49] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts
Date: Thu, 3 Sep 2026 14:25:30 +0000	[thread overview]
Message-ID: <eba5b5f5b0185c47e880bccabcf1bcef2de0b5dd.camel@arm.com> (raw)
In-Reply-To: <anXhPp9QUH_rOn2X@red-moon>

On Fri, 2026-08-07 at 15:44 +0200, Lorenzo Pieralisi wrote:
> On Fri, Aug 07, 2026 at 11:14:07AM +0000, Sascha Bischoff wrote:
> > Device-tree based GICv5 probing already passes the IRS details and
> > maintenance interrupt to KVM, but the ACPI path only initialises
> > the
> > irqchip and installs the ACPI IRQ model. As a result, KVM never
> > sees
> > the GICv5 host information required to probe the vGIC on ACPI
> > systems.
> > 
> > Add the ACPI equivalent of the DT KVM setup. Parse the MADT GICC
> > entries for the maintenance interrupt, retaining the value from the
> > first relevant entry and warning if later entries disagree. Warn if
> > firmware describes the interrupt as edge-triggered, but register it
> > as
> > a level-sensitive, active-high GSI. Pass the resulting IRQ together
> > with the IRS base and coherency information to KVM.
> > 
> > Native GICv5 does not require a maintenance interrupt unless the
> > legacy GICv3-compatible CPU interface is present, so preserve the
> > existing no-maintenance-IRQ handling for that case.
> > 
> > Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
> > ---
> >  drivers/irqchip/irq-gic-v5.c | 95
> > ++++++++++++++++++++++++++++++++++--
> >  1 file changed, 91 insertions(+), 4 deletions(-)
> 
> Just a bunch of nits below.
> 
> > diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-
> > gic-v5.c
> > index e7a7aedcfaf78..5b8ea8551d832 100644
> > --- a/drivers/irqchip/irq-gic-v5.c
> > +++ b/drivers/irqchip/irq-gic-v5.c
> > @@ -1126,7 +1126,7 @@ static void gicv5_set_cpuif_idbits(void)
> >  #ifdef CONFIG_KVM
> >  static struct gic_kvm_info gic_v5_kvm_info __initdata;
> >  
> > -static void __init gic_of_setup_kvm_info(struct device_node *node)
> > +static void __init gic_setup_kvm_info(unsigned int maint_irq)
> >  {
> >  	struct gicv5_irs_chip_data *irs_data =
> > gicv5_irs_get_chip_data();
> >  
> > @@ -1137,17 +1137,19 @@ static void __init
> > gic_of_setup_kvm_info(struct device_node *node)
> >  	 */
> >  	if (!gicv5_global_data.virt_capable) {
> >  		pr_info("GIC implementation is not virtualization
> > capable\n");
> > -		return;
> > +		goto out_dispose_maint_irq;
> 
> Isn't it cleaner to dispose the mapping in the caller (by returning
> an
> error value) rather than here ?
> 
> I appreciate this keeps the IRQ mapping disposal in one place but it
> decouples the allocation from the failure path.

That's a good point. I've moved the disposal to the callers.

> 
> >  	}
> >  
> > -	gic_v5_kvm_info.type = GIC_V5;
> > +	if (WARN_ON(!irs_data))
> > +		goto out_dispose_maint_irq;
> >  
> > +	gic_v5_kvm_info.type = GIC_V5;
> >  	gic_v5_kvm_info.gicv5_irs.base = irs_data->irs_base;
> >  	gic_v5_kvm_info.gicv5_irs.non_coherent = !!(irs_data-
> > >flags & IRS_FLAGS_NON_COHERENT);
> >  
> >  	/* GIC Virtual CPU interface maintenance interrupt */
> >  	gic_v5_kvm_info.no_maint_irq_mask = false;
> > -	gic_v5_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
> > +	gic_v5_kvm_info.maint_irq = maint_irq;
> >  
> >  	/*
> >  	 * We require an MI if we have legacy support, but don't,
> > otherwise.
> > @@ -1162,11 +1164,95 @@ static void __init
> > gic_of_setup_kvm_info(struct device_node *node)
> >  		gic_v5_kvm_info.no_maint_irq_mask = true;
> >  
> >  	vgic_set_kvm_info(&gic_v5_kvm_info);
> > +	return;
> > +
> > +out_dispose_maint_irq:
> > +	irq_dispose_mapping(maint_irq);
> > +}
> > +
> > +static void __init gic_of_setup_kvm_info(struct device_node *node)
> > +{
> > +	/* GIC Virtual CPU interface maintenance interrupt */
> > +	gic_setup_kvm_info(irq_of_parse_and_map(node, 0));
> > +}
> > +
> > +#ifdef CONFIG_ACPI
> > +struct gicv5_acpi_kvm_info {
> > +	u32 maint_irq;
> > +};
> > +
> > +static struct gicv5_acpi_kvm_info acpi_v5_kvm_info __initdata;
> > +
> > +static int __init gic_acpi_parse_virt_madt_gicc(union
> > acpi_subtable_headers *header,
> > +						const unsigned
> > long end)
> > +{
> > +	struct acpi_madt_generic_interrupt *gicc =
> > +		(struct acpi_madt_generic_interrupt *)header;
> > +	static int first_madt = true;
> > +
> > +	if (!(gicc->flags &
> > +	      (ACPI_MADT_ENABLED |
> > ACPI_MADT_GICC_ONLINE_CAPABLE)))
> > +		return 0;
> 
> This would count as a valid parsed entry even though you don't
> retrieve the
> maintanance interrupt number, more below.
> 
> > +
> > +	if (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE)
> > +		pr_warn_once(FW_BUG "MI wrongly advertised as
> > Edge-triggered\n");
> > +
> > +	if (first_madt) {
> > +		first_madt = false;
> > +
> > +		acpi_v5_kvm_info.maint_irq = gicc->vgic_interrupt;
> > +		return 0;
> > +	}
> > +
> > +	if (acpi_v5_kvm_info.maint_irq != gicc->vgic_interrupt)
> > +		pr_warn_once(FW_BUG "MI not the same on all
> > CPUs\n");
> > +
> > +	return 0;
> > +}
> > +
> > +static bool __init gic_acpi_collect_virt_info(void)
> > +{
> > +	int count;
> > +
> > +	count =
> > acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
> > +				     
> > gic_acpi_parse_virt_madt_gicc, 0);
> > +
> > +	return count > 0;
> >  }
> > +
> > +static void __init gic_acpi_setup_kvm_info(void)
> > +{
> > +	unsigned int maint_irq = 0;
> > +	int irq;
> > +
> > +	if (!gic_acpi_collect_virt_info()) {
> > +		pr_warn("Unable to get hardware information used
> > for virtualization\n");
> > +		return;
> > +	}
> 
> Nit: gic_acpi_collect_virt_info() might return true and you still
> don't get
> the info you need. Now, at least one GICC entry should be enabled and
> online
> capable (we are booting on a core after all but never overestimate
> ACPI tables :))
> so this is theory but I thought I would mention it.

I've added an explicit valid flag, which is set true when an enabled
(or online_capable) GICC entry is actually processed. I've made
gic_acpi_collect_virt_info() return that flag directly so now a
disabled entry can't falsely return success.

> 
> > +
> > +	if (acpi_v5_kvm_info.maint_irq) {
> > +		irq = acpi_register_gsi(NULL,
> > acpi_v5_kvm_info.maint_irq,
> > +					ACPI_LEVEL_SENSITIVE,
> > +					ACPI_ACTIVE_HIGH);
> > +		if (irq > 0)
> > +			maint_irq = irq;
> > +		else
> > +			pr_warn("Failed to register GSI for GICv5
> > maintenance IRQ\n");
> 
> Another nit: do we really need the maint_irq variable ?

No, I've removed it.

> 
> Thanks,
> Lorenzo

Thanks,
Sascha

> 
> > +	}
> > +
> > +	gic_setup_kvm_info(maint_irq);
> > +}
> > +#endif // CONFIG_ACPI
> >  #else
> >  static inline void __init gic_of_setup_kvm_info(struct device_node
> > *node)
> >  {
> >  }
> > +
> > +#ifdef CONFIG_ACPI
> > +static inline void __init gic_acpi_setup_kvm_info(void)
> > +{
> > +}
> > +#endif
> >  #endif // CONFIG_KVM
> >  
> >  static int __init gicv5_init_common(struct fwnode_handle
> > *parent_domain)
> > @@ -1265,6 +1351,7 @@ static int __init gic_acpi_init(union
> > acpi_subtable_headers *header, const unsig
> >  		goto out_irs;
> >  
> >  	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC_V5,
> > gic_v5_get_gsi_domain_id);
> > +	gic_acpi_setup_kvm_info();
> >  
> >  	return 0;
> >  
> > -- 
> > 2.34.1


  reply	other threads:[~2026-09-03 14:26 UTC|newest]

Thread overview: 118+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-07 11:12 [PATCH v5 00/49] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-08-07 11:13 ` [PATCH v5 01/49] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-08-07 11:13 ` [PATCH v5 02/49] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-08-07 11:53   ` sashiko-bot
2026-09-03 14:20     ` Sascha Bischoff
2026-08-07 11:14 ` [PATCH v5 03/49] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-08-07 12:01   ` sashiko-bot
2026-09-03 14:22     ` Sascha Bischoff
2026-08-07 13:44   ` Lorenzo Pieralisi
2026-09-03 14:25     ` Sascha Bischoff [this message]
2026-08-07 11:14 ` [PATCH v5 04/49] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-08-07 12:05   ` sashiko-bot
2026-09-03 14:34     ` Sascha Bischoff
2026-08-07 11:15 ` [PATCH v5 05/49] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-08-07 11:15 ` [PATCH v5 06/49] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-08-07 12:17   ` sashiko-bot
2026-09-03 16:33     ` Sascha Bischoff
2026-08-07 11:16 ` [PATCH v5 07/49] KVM: arm64: gic-v5: Cache host IRS ID registers Sascha Bischoff
2026-08-07 12:27   ` sashiko-bot
2026-09-04  6:36     ` Sascha Bischoff
2026-08-07 11:16 ` [PATCH v5 08/49] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-08-07 12:45   ` sashiko-bot
2026-09-04  7:27     ` Sascha Bischoff
2026-08-07 11:17 ` [PATCH v5 09/49] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-08-07 12:50   ` sashiko-bot
2026-09-04  8:00     ` Sascha Bischoff
2026-08-07 11:17 ` [PATCH v5 10/49] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-08-07 13:07   ` sashiko-bot
2026-09-04  8:08     ` Sascha Bischoff
2026-08-07 11:18 ` [PATCH v5 11/49] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-08-07 13:13   ` sashiko-bot
2026-09-04  8:15     ` Sascha Bischoff
2026-08-07 11:18 ` [PATCH v5 12/49] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-08-07 13:30   ` sashiko-bot
2026-09-04 10:03     ` Sascha Bischoff
2026-08-07 11:19 ` [PATCH v5 13/49] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-08-07 11:19 ` [PATCH v5 14/49] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-08-07 13:42   ` sashiko-bot
2026-09-04  8:22     ` Sascha Bischoff
2026-08-07 11:20 ` [PATCH v5 15/49] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-08-07 11:20 ` [PATCH v5 16/49] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-08-07 14:17   ` sashiko-bot
2026-09-04  8:31     ` Sascha Bischoff
2026-08-07 11:21 ` [PATCH v5 17/49] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-08-07 11:21 ` [PATCH v5 18/49] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-08-07 11:22 ` [PATCH v5 19/49] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-08-07 14:27   ` sashiko-bot
2026-09-04  8:42     ` Sascha Bischoff
2026-08-07 11:22 ` [PATCH v5 20/49] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-08-07 14:34   ` sashiko-bot
2026-09-04  8:47     ` Sascha Bischoff
2026-08-07 11:23 ` [PATCH v5 21/49] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-08-07 14:49   ` sashiko-bot
2026-09-04  8:51     ` Sascha Bischoff
2026-08-07 11:23 ` [PATCH v5 22/49] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-08-07 14:52   ` sashiko-bot
2026-09-04  8:57     ` Sascha Bischoff
2026-08-07 11:24 ` [PATCH v5 23/49] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-08-07 11:24 ` [PATCH v5 24/49] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-08-07 15:04   ` sashiko-bot
2026-09-04  9:03     ` Sascha Bischoff
2026-08-07 11:25 ` [PATCH v5 25/49] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-08-07 11:25 ` [PATCH v5 26/49] KVM: arm64: gic: Introduce set_pending_state() to irq_ops Sascha Bischoff
2026-08-07 15:14   ` sashiko-bot
2026-09-04  9:28     ` Sascha Bischoff
2026-08-07 11:26 ` [PATCH v5 27/49] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-08-07 15:23   ` sashiko-bot
2026-09-04  9:22     ` Sascha Bischoff
2026-08-07 11:26 ` [PATCH v5 28/49] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-08-07 15:29   ` sashiko-bot
2026-09-04  9:30     ` Sascha Bischoff
2026-08-07 11:27 ` [PATCH v5 29/49] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-08-07 15:40   ` sashiko-bot
2026-09-04  9:47     ` Sascha Bischoff
2026-08-07 11:27 ` [PATCH v5 30/49] KVM: arm64: gic-v5: Mask per-vCPU PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-08-07 11:28 ` [PATCH v5 31/49] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-08-07 16:27   ` sashiko-bot
2026-09-04 10:01     ` Sascha Bischoff
2026-08-07 11:28 ` [PATCH v5 32/49] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-08-07 16:20   ` sashiko-bot
2026-09-04  9:59     ` Sascha Bischoff
2026-08-07 11:29 ` [PATCH v5 33/49] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-08-07 11:29 ` [PATCH v5 34/49] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-08-07 16:30   ` sashiko-bot
2026-09-04 10:06     ` Sascha Bischoff
2026-08-07 11:30 ` [PATCH v5 35/49] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-08-07 16:48   ` sashiko-bot
2026-09-04 10:23     ` Sascha Bischoff
2026-08-07 11:30 ` [PATCH v5 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-08-07 16:55   ` sashiko-bot
2026-09-04 11:04     ` Sascha Bischoff
2026-08-07 11:31 ` [PATCH v5 37/49] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-08-07 16:52   ` sashiko-bot
2026-09-04 10:09     ` Sascha Bischoff
2026-08-07 11:31 ` [PATCH v5 38/49] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-08-07 11:32 ` [PATCH v5 39/49] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-08-07 11:32 ` [PATCH v5 40/49] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-08-07 11:33 ` [PATCH v5 41/49] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-08-07 17:12   ` sashiko-bot
2026-09-04 10:15     ` Sascha Bischoff
2026-08-07 11:33 ` [PATCH v5 42/49] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-08-07 17:17   ` sashiko-bot
2026-09-04 10:38     ` Sascha Bischoff
2026-08-07 11:34 ` [PATCH v5 43/49] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-08-07 17:21   ` sashiko-bot
2026-09-04 10:45     ` Sascha Bischoff
2026-08-07 11:35 ` [PATCH v5 44/49] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-08-07 11:35 ` [PATCH v5 45/49] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-08-07 11:36 ` [PATCH v5 46/49] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-08-07 11:36 ` [PATCH v5 47/49] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-08-07 17:39   ` sashiko-bot
2026-09-04 10:48     ` Sascha Bischoff
2026-08-07 11:37 ` [PATCH v5 48/49] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
2026-08-07 17:50   ` sashiko-bot
2026-09-04 10:54     ` Sascha Bischoff
2026-08-07 11:37 ` [PATCH v5 49/49] KVM: selftests: Add VGICv5 sparse vCPU IDs test Sascha Bischoff
2026-08-07 17:56   ` sashiko-bot
2026-09-04 10:57     ` Sascha Bischoff

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