Re: [RFC PATCH 26/36] arm64: ptrace: Add PSR_ALLINT_BIT

[Vladimir Murzin <vladimir.murzin@arm.com>]

On 7/10/26 03:16, Jinjie Ruan wrote:
> 
> On 7/9/2026 8:13 PM, Vladimir Murzin wrote:
>> From: Ada Couprie Diaz <ada.coupriediaz@arm.com>
>>
>> When FEAT_NMI is implemented, ALLINT is part of PSTATE and will be saved
>> to SPSR on exception entry.
>> As it can mask interrupts, depending on configuration, we will need to
>> check its value in interruted tasks, so add the corresponding bit
>> to ptrace.h.
>>
>> Given its impact on interrupt and NMI masking, use it to update
>> `print_pstate()` so that it displays ALLINT state.
>> Display it after DAIF so that interrupt masking fields are together.
>>
>> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>> ---
>>  arch/arm64/include/uapi/asm/ptrace.h | 1 +
>>  arch/arm64/kernel/process.c          | 3 ++-
>>  2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
>> index 6fed93fb2536..99352dd823cc 100644
>> --- a/arch/arm64/include/uapi/asm/ptrace.h
>> +++ b/arch/arm64/include/uapi/asm/ptrace.h
>> @@ -48,6 +48,7 @@
>>  #define PSR_D_BIT	0x00000200
>>  #define PSR_BTYPE_MASK	0x00000c00
>>  #define PSR_SSBS_BIT	0x00001000
>> +#define PSR_ALLINT_BIT	0x00002000
>>  #define PSR_PAN_BIT	0x00400000
>>  #define PSR_UAO_BIT	0x00800000
>>  #define PSR_DIT_BIT	0x01000000
>> diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
>> index ddda8d7aee24..8d4ceef4f67f 100644
>> --- a/arch/arm64/kernel/process.c
>> +++ b/arch/arm64/kernel/process.c
>> @@ -183,7 +183,7 @@ static void print_pstate(struct pt_regs *regs)
>>  		const char *btype_str = btypes[(pstate & PSR_BTYPE_MASK) >>
>>  					       PSR_BTYPE_SHIFT];
>>  
>> -		printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cPAN %cUAO %cTCO %cDIT %cSSBS BTYPE=%s)\n",
>> +		printk("pstate: %08llx (%c%c%c%c %c%c%c%c %cALLINT %cPAN %cUAO %cTCO %cDIT %cSSBS BTYPE=%s)\n",
>>  			pstate,
>>  			pstate & PSR_N_BIT ? 'N' : 'n',
>>  			pstate & PSR_Z_BIT ? 'Z' : 'z',
>> @@ -193,6 +193,7 @@ static void print_pstate(struct pt_regs *regs)
>>  			pstate & PSR_A_BIT ? 'A' : 'a',
>>  			pstate & PSR_I_BIT ? 'I' : 'i',
>>  			pstate & PSR_F_BIT ? 'F' : 'f',
>> +			pstate & PSR_ALLINT_BIT ? '+' : '-',
> Hi Vladimir,
> 
> This seems to be correct, but the status of the ALLINT bit
> should not be displayed if FEAT_NMI is not enabled (system_uses_nmi()).
> 
> According to the ARM64 ALLINT manual,
> 
> 	"On a Warm reset, this field resets to an architecturally UNKNOWN value."
> 
> If the hardware supports FEAT_NMI but the config is not enabled, the
> value of the ALLINT bit is a random value, which is very misleading to
> show it.
> 

On FEAT_NMI hardware PSTATE.ALLINT is always set to the inverse of
SCTLR_ELx.SPINTMASK on taking the exception regardless of the value
of SCTLR_ELx.NMI. So I fail to see how it could be a random value.

I agree that it could be slightly confusing to see ALLINT even if NMI
is not enabled, such as when the user has forced pNMI or hidden NMI
via id_aa64pfr1.nmi=0 or disabled NMI via config option.

Guarding this with supports_nmi() indeed could help. However, I think
the general direction is to keep this function lean and not add extra
conditionals.

Thanks
Vladimir

> Best regards,
> Jinjie
> 
> 
>>  			pstate & PSR_PAN_BIT ? '+' : '-',
>>  			pstate & PSR_UAO_BIT ? '+' : '-',
>>  			pstate & PSR_TCO_BIT ? '+' : '-',
>