From: Fenghua Yu <fenghuay@nvidia.com>
To: Reinette Chatre <reinette.chatre@intel.com>,
Tony Luck <tony.luck@intel.com>, Ben Horgan <ben.horgan@arm.com>,
James Morse <james.morse@arm.com>,
Dave Martin <Dave.Martin@arm.com>,
Shaopeng Tan <tan.shaopeng@fujitsu.com>,
Chen Yu <yu.c.chen@intel.com>, Babu Moger <babu.moger@amd.com>,
Drew Fustini <fustini@kernel.org>,
Vikram Sethi <vsethi@nvidia.com>,
Shanker Donthineni <sdonthineni@nvidia.com>,
Newton Liu <newtonl@nvidia.com>, Gavin Shan <gshan@redhat.com>
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Fenghua Yu <fenghuay@nvidia.com>
Subject: [PATCH 14/23] arm_mpam: Support memory-level MSCs and ABMC per class
Date: Thu, 16 Jul 2026 14:03:04 -0700 [thread overview]
Message-ID: <20260716210329.2914625-14-fenghuay@nvidia.com> (raw)
In-Reply-To: <cover.1784217438.git.fenghuay@nvidia.com>
Some platforms place MBWU counters on a memory MSC above L3 while CSU
occupancy may remain on the L3 cache MSC. The driver previously assumed
all monitors and ABMC state lived on the L3 resource, which
mis-associates MBA counters, breaks mbm_L3_assignments when multiple
events share a class, and uses the wrong domain ID space for
memory-level MSCs.
Teach MPAM resctrl to map monitor classes to L3 or MBA resources,
initialise ABMC on the resource that owns the MBWU monitor, select the
node-scope MBM total event for memory-side counters, and test
mbm_cntr_assignable instead of inferring assignment support from
whichever monitor happens to share res->class first.
Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com>
Signed-off-by: Fenghua Yu <fenghuay@nvidia.com>
---
drivers/resctrl/mpam_resctrl.c | 112 ++++++++++++++++++++++++---------
1 file changed, 81 insertions(+), 31 deletions(-)
diff --git a/drivers/resctrl/mpam_resctrl.c b/drivers/resctrl/mpam_resctrl.c
index e2cb3384820a..953412f11995 100644
--- a/drivers/resctrl/mpam_resctrl.c
+++ b/drivers/resctrl/mpam_resctrl.c
@@ -45,7 +45,7 @@ static struct mpam_resctrl_res mpam_resctrl_controls[RDT_NUM_RESOURCES];
* to those supported by MPAM.
* Class pointer may be NULL.
*/
-#define MPAM_MAX_EVENT QOS_L3_MBM_TOTAL_EVENT_ID
+#define MPAM_MAX_EVENT QOS_NODE_MBM_TOTAL_EVENT_ID
static struct mpam_resctrl_mon mpam_resctrl_counters[MPAM_MAX_EVENT + 1];
#define for_each_mpam_resctrl_mon(mon, eventid) \
@@ -88,6 +88,11 @@ bool resctrl_arch_alloc_capable(void)
return false;
}
+static bool mpam_class_memory(struct mpam_class *class)
+{
+ return class && class->type == MPAM_CLASS_MEMORY && class->level > 3;
+}
+
bool resctrl_arch_mon_capable(void)
{
struct mpam_resctrl_res *res = &mpam_resctrl_controls[RDT_RESOURCE_L3];
@@ -121,7 +126,13 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_l3_mon_domain *d
bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r)
{
- return (r == &mpam_resctrl_controls[RDT_RESOURCE_L3].resctrl_res);
+ /*
+ * mbm_cntr_assignable is set only when ABMC is initialised on this
+ * resource. Multiple monitor events may share res->class (e.g.
+ * occupancy and MBWU), so assignment support must not be inferred
+ * from mon->assigned_counters via a class lookup on the wrong event.
+ */
+ return r->mon.mbm_cntr_assignable;
}
int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable)
@@ -170,24 +181,41 @@ static void resctrl_reset_task_closids(void)
read_unlock(&tasklist_lock);
}
-static void mpam_resctrl_monitor_sync_abmc_vals(struct rdt_resource *l3)
+static struct
+mpam_resctrl_res *mpam_resctrl_res_from_mon(struct mpam_resctrl_mon *mon)
{
- struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[QOS_L3_MBM_TOTAL_EVENT_ID];
+ struct mpam_resctrl_res *res;
+ enum resctrl_res_level rid;
if (!mon->class)
- return;
+ return NULL;
+
+ for_each_mpam_resctrl_control(res, rid) {
+ if (res->class == mon->class)
+ return res;
+ }
+
+ return NULL;
+}
+
+static struct mpam_resctrl_mon *mpam_resctrl_mbm_total_mon(void)
+{
+ if (mpam_resctrl_counters[QOS_NODE_MBM_TOTAL_EVENT_ID].class)
+ return &mpam_resctrl_counters[QOS_NODE_MBM_TOTAL_EVENT_ID];
+
+ return &mpam_resctrl_counters[QOS_L3_MBM_TOTAL_EVENT_ID];
+}
+
+static void mpam_resctrl_monitor_sync_abmc_vals(struct rdt_resource *r)
+{
+ struct mpam_resctrl_mon *mon = mpam_resctrl_mbm_total_mon();
- if (!mon->assigned_counters)
+ if (!mon->class || !mon->assigned_counters)
return;
- l3->mon.num_mbm_cntrs = mon->class->props.num_mbwu_mon;
+ r->mon.num_mbm_cntrs = mon->class->props.num_mbwu_mon;
if (cdp_enabled)
- l3->mon.num_mbm_cntrs /= 2;
-
- /*
- * Continue as normal even if enabling cdp causes there to be
- * zero counters. This avoids giving resctrl mixed messages.
- */
+ r->mon.num_mbm_cntrs /= 2;
}
int resctrl_arch_set_cdp_enabled(struct rdt_resource *r, struct resctrl_ctrl *ctrl,
@@ -393,6 +421,7 @@ static int resctrl_arch_mon_ctx_alloc_no_wait(enum resctrl_event_id evtid)
return mpam_alloc_csu_mon(mon->class);
case QOS_L3_MBM_LOCAL_EVENT_ID:
case QOS_L3_MBM_TOTAL_EVENT_ID:
+ case QOS_NODE_MBM_TOTAL_EVENT_ID:
return USE_PRE_ALLOCATED;
default:
return -EOPNOTSUPP;
@@ -1149,7 +1178,10 @@ static void mpam_resctrl_pick_counters(void)
* and it's equivalent to mbm_total and so always use
* mbm_total.
*/
- counter_update_class(QOS_L3_MBM_TOTAL_EVENT_ID, class);
+ if (class->type == MPAM_CLASS_MEMORY)
+ counter_update_class(QOS_NODE_MBM_TOTAL_EVENT_ID, class);
+ else
+ counter_update_class(QOS_L3_MBM_TOTAL_EVENT_ID, class);
}
}
}
@@ -1176,7 +1208,7 @@ void resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_l3_mon_domain *
{
struct mpam_resctrl_mon *mon = &mpam_resctrl_counters[evtid];
- if (evtid != QOS_L3_MBM_TOTAL_EVENT_ID) {
+ if (!resctrl_is_mbm_total_event(evtid)) {
pr_debug("unexpected event id\n");
return;
}
@@ -1193,7 +1225,7 @@ void resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_l3_mon_domain *
__config_cntr(mon, cntr_id, CDP_NONE, closid, rmid, assign);
}
- resctrl_arch_reset_cntr(r, d, closid, rmid, cntr_id, QOS_L3_MBM_TOTAL_EVENT_ID);
+ resctrl_arch_reset_cntr(r, d, closid, rmid, cntr_id, evtid);
}
static int mpam_resctrl_control_init(struct mpam_resctrl_res *res)
@@ -1291,10 +1323,10 @@ static int mpam_resctrl_pick_domain_id(int cpu, struct mpam_component *comp)
*/
static int mpam_resctrl_monitor_init_abmc(struct mpam_resctrl_mon *mon)
{
- struct mpam_resctrl_res *res = &mpam_resctrl_controls[RDT_RESOURCE_L3];
size_t num_rmid = resctrl_arch_system_num_rmid_idx();
- struct rdt_resource *l3 = &res->resctrl_res;
struct mpam_class *class = mon->class;
+ struct mpam_resctrl_res *res;
+ struct rdt_resource *r;
u16 num_mbwu_mon;
int *cntrs;
@@ -1305,6 +1337,12 @@ static int mpam_resctrl_monitor_init_abmc(struct mpam_resctrl_mon *mon)
}
memset(rmid_array, -1, num_rmid * sizeof(*rmid_array));
+ res = mpam_resctrl_res_from_mon(mon);
+ if (!res)
+ return -EINVAL;
+
+ r = &res->resctrl_res;
+
num_mbwu_mon = class->props.num_mbwu_mon;
cntrs = __alloc_mbwu_array(mon->class, num_mbwu_mon);
if (IS_ERR(cntrs))
@@ -1312,12 +1350,12 @@ static int mpam_resctrl_monitor_init_abmc(struct mpam_resctrl_mon *mon)
mon->assigned_counters = cntrs;
mon->mbwu_idx_to_mon = no_free_ptr(rmid_array);
- l3->mon.mbm_cntr_assignable = true;
- l3->mon.mbm_assign_on_mkdir = true;
- l3->mon.mbm_cntr_configurable = false;
- l3->mon.mbm_cntr_assign_fixed = true;
+ r->mon.mbm_cntr_assignable = true;
+ r->mon.mbm_assign_on_mkdir = true;
+ r->mon.mbm_cntr_configurable = false;
+ r->mon.mbm_cntr_assign_fixed = true;
- mpam_resctrl_monitor_sync_abmc_vals(l3);
+ mpam_resctrl_monitor_sync_abmc_vals(r);
return 0;
}
@@ -1325,8 +1363,15 @@ static int mpam_resctrl_monitor_init_abmc(struct mpam_resctrl_mon *mon)
static int mpam_resctrl_monitor_init(struct mpam_resctrl_mon *mon,
enum resctrl_event_id type)
{
- struct mpam_resctrl_res *res = &mpam_resctrl_controls[RDT_RESOURCE_L3];
- struct rdt_resource *l3 = &res->resctrl_res;
+ struct mpam_resctrl_res *res;
+ struct rdt_resource *r;
+
+ if (mpam_class_memory(mon->class))
+ res = &mpam_resctrl_controls[RDT_RESOURCE_MBA];
+ else
+ res = &mpam_resctrl_controls[RDT_RESOURCE_L3];
+
+ r = &res->resctrl_res;
lockdep_assert_cpus_held();
@@ -1353,8 +1398,13 @@ static int mpam_resctrl_monitor_init(struct mpam_resctrl_mon *mon,
* monitoring class.
* Setting name is necessary on monitor only platforms.
*/
- l3->name = "L3";
- l3->mon_scope = RESCTRL_L3_CACHE;
+ if (mpam_class_memory(mon->class)) {
+ r->name = "MB";
+ r->mon_scope = RESCTRL_NODE;
+ } else {
+ r->name = "L3";
+ r->mon_scope = RESCTRL_L3_CACHE;
+ }
/*
* num-rmid is the upper bound for the number of monitoring groups that
@@ -1364,9 +1414,9 @@ static int mpam_resctrl_monitor_init(struct mpam_resctrl_mon *mon,
* this does mean userspace needs to know the architecture to correctly
* interpret this value.
*/
- l3->mon.num_rmid = resctrl_arch_system_num_rmid_idx();
+ r->mon.num_rmid = resctrl_arch_system_num_rmid_idx();
- if (type == QOS_L3_MBM_TOTAL_EVENT_ID) {
+ if (type == QOS_L3_MBM_TOTAL_EVENT_ID || type == QOS_NODE_MBM_TOTAL_EVENT_ID) {
int err;
err = mpam_resctrl_monitor_init_abmc(mon);
@@ -1374,13 +1424,13 @@ static int mpam_resctrl_monitor_init(struct mpam_resctrl_mon *mon,
return err;
static_assert(MAX_EVT_CONFIG_BITS == 0x7f);
- l3->mon.mbm_cfg_mask = MAX_EVT_CONFIG_BITS;
+ r->mon.mbm_cfg_mask = MAX_EVT_CONFIG_BITS;
}
if (!resctrl_enable_mon_event(type, false, 0, NULL))
return -EINVAL;
- l3->mon_capable = true;
+ r->mon_capable = true;
return 0;
}
--
2.43.0
next prev parent reply other threads:[~2026-07-16 21:04 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-16 21:02 [PATCH RFC 00/23] resctrl: MBA control emulation and ARM MPAM MB_NODE support Fenghua Yu
2026-07-16 21:02 ` [PATCH 01/23] resctrl: Fix ownership of resource_schemata control subdirectories Fenghua Yu
2026-07-16 21:02 ` [PATCH 02/23] arm_mpam: Fix NULL address access issue Fenghua Yu
2026-07-16 21:02 ` [PATCH 03/23] resctrl: Expose MBA resource_schemata mode sysfs Fenghua Yu
2026-07-16 21:02 ` [PATCH 04/23] resctrl: Expose per-control status in resource_schemata Fenghua Yu
2026-07-16 21:02 ` [PATCH 05/23] resctrl: Add nested resource_schemata support for emulated controls Fenghua Yu
2026-07-16 21:02 ` [PATCH 06/23] resctrl: Mirror schemata for controls without MBW hardware Fenghua Yu
2026-07-16 21:02 ` [PATCH 07/23] resctrl: Rebuild resource_schemata subdirs on MBA mode change Fenghua Yu
2026-07-16 21:02 ` [PATCH 08/23] Documentation: resctrl: document MBA control emulation Fenghua Yu
2026-07-16 21:02 ` [PATCH 09/23] resctrl: De-hardcode L3 monitor infrastructure Fenghua Yu
2026-07-16 21:03 ` [PATCH 10/23] resctrl: Expose MBA MBM counter assignment sysfs Fenghua Yu
2026-07-16 21:03 ` [PATCH 11/23] resctrl: name node-scoped monitor domains mon_NODE_<id> Fenghua Yu
2026-07-16 21:03 ` [PATCH 12/23] resctrl: Add node-scope MBM total event Fenghua Yu
2026-07-16 21:03 ` [PATCH 13/23] resctrl: Make MBM paths resource-aware Fenghua Yu
2026-07-16 21:03 ` Fenghua Yu [this message]
2026-07-16 21:03 ` [PATCH 15/23] arm_mpam: Refine L3 topology and class selection Fenghua Yu
2026-07-16 21:03 ` [PATCH 16/23] arm_mpam: Include all MSC components during domain setup Fenghua Yu
2026-07-16 21:03 ` [PATCH 17/23] arm_mpam: Handle CPU-less numa nodes Fenghua Yu
2026-07-16 21:03 ` [PATCH 18/23] arm_mpam: Emulate MB control with node-scoped MB_NODE control Fenghua Yu
2026-07-16 21:03 ` [PATCH 19/23] Documentation: arm64: mpam: document memory-level MB control and NUMA nodes Fenghua Yu
2026-07-16 21:03 ` [PATCH 20/23] Documentation: resctrl: document NODE-scoped MBA domains and mon_NODE monitoring Fenghua Yu
2026-07-16 21:03 ` [PATCH 21/23] Documentation: resctrl: document MB_NODE emulation example on ARM MPAM Fenghua Yu
2026-07-16 21:03 ` [PATCH 22/23] arm_mpam: Add KUnit test for CPU-less NUMA node affinity Fenghua Yu
2026-07-16 21:03 ` [PATCH 23/23] selftests/resctrl: Add MB emulation test for ARM MPAM Fenghua Yu
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