Re: [PATCH v2 15/24] net: mdio: Add ZTE ZX279128S MDIO controller

[Navid Ghahremani <ghahramani.navid@gmail.com>]

Hi Andrew,

Andrew Lunn wrote:
> > +	writel(0, base + ZX_MDIO_STATUS);
> > +	writel(readl(base + ZX_MDIO_CMD) & ~ZX_MDIO_CMD_START,
> > +	       base + ZX_MDIO_CMD);
>
> This is the same as what you did at the beginning, but in the opposite
> order. Is it actually needed, and can the same order be used?

It is not needed. That clear came over from the first driver I wrote
for this board. There is no public documentation for the MDIO block, so
that driver was put together by reverse engineering, and I never
checked whether every step was needed. I removed the clear after the
transfer, so only the one before the start is left, and tested it on my
board. All five PHYs probe with the same IDs and link states as before,
and a few minutes of PHY polling plus traffic gave no MDIO timeouts.

> Is this the bus clock? Does it need setting to 2.5Mhz?

wclk is the MDIO block's work clock from the LSP1 clock controller. The
driver sets bit 12 of the command register, which I took to be an MDC
divider. The 50 MHz and 2.5 MHz in my comment are not measured, and the
wclk rate is not confirmed yet either. I will find out the real MDC rate
before I resend the MDIO driver and fix the comment and the code to
match.

> It needs a device tree binding. But that is mostly boilerplate.

The binding is patch 14/24 of this series and Rob gave a Reviewed-by.
The MDIO, PHY and switch patches will go to netdev as their own series
like you asked.

Best regards,
Navid