[PATCH v3 00/14] This series fixes the errors of MediaTek display driver found by IGT.

[PATCH v3 00/14] This series fixes the errors of MediaTek display driver found by IGT.

[Hsiao Chien Sung via B4 Relay]

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
Changes in v3:
- Modify the commit message
- Add a patch to fix destination alpha error in OVL
- Link to v2: https://lore.kernel.org/all/20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com

---
Changes in v2:
- Seperate the changes that belong to another repo (driver/soc/mediatek)
- Move the fix patches to the front of the series
- Link to v1: https://lore.kernel.org/r/20240616-mediatek-drm-next-v1-0-7e8f9cf785d8@mediatek.com

---
Hsiao Chien Sung (14):
      drm/mediatek: Add missing plane settings when async update
      drm/mediatek: Disable 9-bit alpha in ETHDR
      drm/mediatek: Fix XRGB setting error in OVL
      drm/mediatek: Fix XRGB setting error in Mixer
      drm/mediatek: Turn off the layers with zero width or height
      drm/mediatek: Add OVL compatible name for MT8195
      drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property
      drm/mediatek: Add new color format MACROs in OVL
      drm/mediatek: Set DRM mode configs accordingly
      drm/mediatek: Support more 10bit formats in OVL
      drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195
      drm/mediatek: Support DRM plane alpha in OVL
      drm/mediatek: Support DRM plane alpha in Mixer
      drm/mediatek: Fix XRGB setting error in OVL

 drivers/gpu/drm/mediatek/mtk_ddp_comp.h         |  6 +-
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c         | 93 ++++++++++++++++++-------
 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c |  2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c          | 24 +++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.h          |  4 ++
 drivers/gpu/drm/mediatek/mtk_ethdr.c            | 27 +++++--
 drivers/gpu/drm/mediatek/mtk_plane.c            |  4 +-
 7 files changed, 126 insertions(+), 34 deletions(-)
---
base-commit: 62fe4b067581d480e863191305f108bebffbc0e9
change-id: 20240615-mediatek-drm-next-ad601b349f23

Best regards,

---
Hsiao Chien Sung (14):
      drm/mediatek: Add missing plane settings when async update
      drm/mediatek: Use 8-bit alpha in ETHDR
      drm/mediatek: Fix XRGB setting error in OVL
      drm/mediatek: Fix XRGB setting error in Mixer
      drm/mediatek: Fix destination alpha error in OVL
      drm/mediatek: Turn off the layers with zero width or height
      drm/mediatek: Add OVL compatible name for MT8195
      drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property
      drm/mediatek: Add new color format MACROs in OVL
      drm/mediatek: Set DRM mode configs accordingly
      drm/mediatek: Support more 10bit formats in OVL
      drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195
      drm/mediatek: Support DRM plane alpha in OVL
      drm/mediatek: Support DRM plane alpha in Mixer

 drivers/gpu/drm/mediatek/mtk_ddp_comp.h         |  6 +-
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c         | 95 ++++++++++++++++++-------
 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c |  2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c          | 24 +++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.h          |  4 ++
 drivers/gpu/drm/mediatek/mtk_ethdr.c            | 27 +++++--
 drivers/gpu/drm/mediatek/mtk_plane.c            |  4 +-
 7 files changed, 127 insertions(+), 35 deletions(-)
---
base-commit: 62fe4b067581d480e863191305f108bebffbc0e9
change-id: 20240619-igt-49195e21404d

Best regards,
-- 
Hsiao Chien Sung <shawn.sung@mediatek.com>

[PATCH v3 01/14] drm/mediatek: Add missing plane settings when async update

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Fix an issue that plane coordinate was not saved when
calling async update.

Fixes: 920fffcc8912 ("drm/mediatek: update cursors by using async atomic update")

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_plane.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c
index 4625deb21d40..a74b26d35985 100644
--- a/drivers/gpu/drm/mediatek/mtk_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_plane.c
@@ -227,6 +227,8 @@ static void mtk_plane_atomic_async_update(struct drm_plane *plane,
 	plane->state->src_y = new_state->src_y;
 	plane->state->src_h = new_state->src_h;
 	plane->state->src_w = new_state->src_w;
+	plane->state->dst.x1 = new_state->dst.x1;
+	plane->state->dst.y1 = new_state->dst.y1;
 
 	mtk_plane_update_new_state(new_state, new_plane_state);
 	swap(plane->state->fb, new_state->fb);

-- 
Git-146)

[PATCH v3 02/14] drm/mediatek: Use 8-bit alpha in ETHDR

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

9-bit alpha (max=0x100) is designed for special HDR related
calculation, which should be disabled by default.
Change the alpha value from 0x100 to 0xff in 8-bit form.

Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ethdr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index 156c6ff547e8..d7d16482c947 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -50,7 +50,6 @@
 
 #define MIXER_INX_MODE_BYPASS			0
 #define MIXER_INX_MODE_EVEN_EXTEND		1
-#define DEFAULT_9BIT_ALPHA			0x100
 #define	MIXER_ALPHA_AEN				BIT(8)
 #define	MIXER_ALPHA				0xff
 #define ETHDR_CLK_NUM				13
@@ -169,7 +168,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
 		alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
 
 	mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true,
-				  DEFAULT_9BIT_ALPHA,
+				  MIXER_ALPHA,
 				  pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND :
 				  MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);
 

-- 
Git-146)

[PATCH v3 03/14] drm/mediatek: Fix XRGB setting error in OVL

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

CONST_BLD must be enabled for XRGB formats although the alpha channel
can be ignored, or OVL will still read the value from memory.
This error only affects CRC generation.

Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index b552a02d7eae..bd00e5e85deb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -38,6 +38,7 @@
 #define DISP_REG_OVL_PITCH_MSB(n)		(0x0040 + 0x20 * (n))
 #define OVL_PITCH_MSB_2ND_SUBBUF			BIT(16)
 #define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20 * (n))
+#define OVL_CONST_BLEND					BIT(28)
 #define DISP_REG_OVL_RDMA_CTRL(n)		(0x00c0 + 0x20 * (n))
 #define DISP_REG_OVL_RDMA_GMC(n)		(0x00c8 + 0x20 * (n))
 #define DISP_REG_OVL_ADDR_MT2701		0x0040
@@ -407,6 +408,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 	unsigned int fmt = pending->format;
 	unsigned int offset = (pending->y << 16) | pending->x;
 	unsigned int src_size = (pending->height << 16) | pending->width;
+	unsigned int ignore_pixel_alpha = 0;
 	unsigned int con;
 	bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
 	union overlay_pitch {
@@ -428,6 +430,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 	if (state->base.fb && state->base.fb->format->has_alpha)
 		con |= OVL_CON_AEN | OVL_CON_ALPHA;
 
+	/* CONST_BLD must be enabled for XRGB formats although the alpha channel
+	 * can be ignored, or OVL will still read the value from memory.
+	 * For RGB888 related formats, whether CONST_BLD is enabled or not won't
+	 * affect the result. Therefore we use !has_alpha as the condition.
+	 */
+	if (state->base.fb && !state->base.fb->format->has_alpha)
+		ignore_pixel_alpha = OVL_CONST_BLEND;
+
 	if (pending->rotation & DRM_MODE_REFLECT_Y) {
 		con |= OVL_CON_VIRT_FLIP;
 		addr += (pending->height - 1) * pending->pitch;
@@ -443,8 +453,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 
 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
 			      DISP_REG_OVL_CON(idx));
-	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
-			      DISP_REG_OVL_PITCH(idx));
+	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha,
+			      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
 			      DISP_REG_OVL_SRC_SIZE(idx));
 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,

-- 
Git-146)

[PATCH v3 04/14] drm/mediatek: Fix XRGB setting error in Mixer

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Although the alpha channel in XRGB formats can be ignored, ALPHA_CON
must be configured accordingly when using XRGB formats or it will still
affects CRC generation.

Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195")
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ethdr.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index d7d16482c947..5c52e514ae30 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -153,6 +153,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
 	unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
 	unsigned int align_width = ALIGN_DOWN(pending->width, 2);
 	unsigned int alpha_con = 0;
+	bool replace_src_a = false;
 
 	dev_dbg(dev, "%s+ idx:%d", __func__, idx);
 
@@ -167,7 +168,15 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
 	if (state->base.fb && state->base.fb->format->has_alpha)
 		alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
 
-	mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true,
+	if (state->base.fb && !state->base.fb->format->has_alpha) {
+		/*
+		 * Mixer doesn't support CONST_BLD mode,
+		 * use a trick to make the output equivalent
+		 */
+		replace_src_a = true;
+	}
+
+	mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a,
 				  MIXER_ALPHA,
 				  pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND :
 				  MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);

-- 
Git-146)

Re: [PATCH v3 04/14] drm/mediatek: Fix XRGB setting error in Mixer

[Markus Elfring]

> Although the alpha channel in XRGB formats can be ignored, ALPHA_CON
> must be configured accordingly when using XRGB formats or it will still
> affects CRC generation.

  affect?


Can such a change description become a bit nicer with an additional
imperative wording?
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.12-rc2#n94

Regards,
Markus

Re: [PATCH v3 04/14] drm/mediatek: Fix XRGB setting error in Mixer

[Shawn Sung (宋孝謙)]

On Mon, 2024-10-07 at 13:36 +0200, Markus Elfring wrote:
> > Although the alpha channel in XRGB formats can be ignored,
> > ALPHA_CON
> > must be configured accordingly when using XRGB formats or it will
> > still
> > affects CRC generation.
> 
>   affect?

Yes, didn't notice that.
This is a typo, but the series has been merged.

> 
> 
> Can such a change description become a bit nicer with an additional
> imperative wording?
> 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.12-rc2#n94

Honestly, I wasn't familiar with the term "imerative mood" before this.
After studying it, I now understand. Thank you for pointing this out; I
will keep this in mind for the future.

As a result, I asked AI to refine the description using imperative
wording as a reference example:

"Ensure that ALPHA_CON is configured appropriately when using XRGB
formats, even though the alpha channel can be ignored. Failing to do so
will affect CRC generation."

Regards,
Shawn
> 
> Regards,
> Markus

[PATCH v3 05/14] drm/mediatek: Fix destination alpha error in OVL

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

The formula of Coverage alpha blending is:
dst.a = dst.a * (0xff - src.a * SCA / 0xff) / 0xff
      + src.a * SCA / 0xff

dst.a: destination alpha
src.a: pixel alpha
SCA  : plane alpha

When SCA = 0xff, the formula becomes:
dst.a = dst.a * (0xff - src.a) + src.a

This patch is to set the destination alpha (background) to 0xff:
- When dst.a = 0    (before), dst.a = src.a
- When dst.a = 0xff (after) , dst.a = 0xff * (0xff - src.a) + src.a

According to the fomula above:
- When src.a = 0   , dst.a = 0
- When src.a = 0xff, dst.a = 0xff
This two cases are just still correct. But when src.a is
between 0 and 0xff, the difference starts to appear

Fixes: 616443ca577e ("drm/mediatek: Move cmdq_reg info from struct mtk_ddp_comp to sub driver private data")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index bd00e5e85deb..693560fa34e8 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -72,6 +72,8 @@
 #define	OVL_CON_VIRT_FLIP	BIT(9)
 #define	OVL_CON_HORZ_FLIP	BIT(10)
 
+#define OVL_COLOR_ALPHA		GENMASK(31, 24)
+
 static const u32 mt8173_formats[] = {
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ARGB8888,
@@ -274,7 +276,13 @@ void mtk_ovl_config(struct device *dev, unsigned int w,
 	if (w != 0 && h != 0)
 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,
 				      DISP_REG_OVL_ROI_SIZE);
-	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);
+
+	/*
+	 * The background color must be opaque black (ARGB),
+	 * otherwise the alpha blending will have no effect
+	 */
+	mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg,
+			      ovl->regs, DISP_REG_OVL_ROI_BGCLR);
 
 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);

-- 
Git-146)

[PATCH v3 06/14] drm/mediatek: Turn off the layers with zero width or height

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

We found that IGT (Intel GPU Tool) will try to commit layers with
zero width or height and lead to undefined behaviors in hardware.
Disable the layers in such a situation.

Fixes: 453c3364632a ("drm/mediatek: Add ovl_adaptor support for MT8195")
Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195")
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +-
 drivers/gpu/drm/mediatek/mtk_ethdr.c            | 7 ++++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index 02dd7dcdfedb..2b62d6475918 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -158,7 +158,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
 	merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
 	ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
 
-	if (!pending->enable) {
+	if (!pending->enable || !pending->width || !pending->height) {
 		mtk_merge_stop_cmdq(merge, cmdq_pkt);
 		mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
 		mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index 5c52e514ae30..bf5826b7e776 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -160,7 +160,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
 	if (idx >= 4)
 		return;
 
-	if (!pending->enable) {
+	if (!pending->enable || !pending->width || !pending->height) {
+		/*
+		 * instead of disabling layer with MIX_SRC_CON directly
+		 * set the size to 0 to avoid screen shift due to mixer
+		 * mode switch (hardware behavior)
+		 */
 		mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
 		return;
 	}

-- 
Git-146)

[PATCH v3 07/14] drm/mediatek: Add OVL compatible name for MT8195

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Add OVL compatible name for MT8195.
Without this commit, DRM won't work after modifying the device tree.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b5f605751b0a..8e047043202b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -743,6 +743,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_OVL },
 	{ .compatible = "mediatek,mt8192-disp-ovl",
 	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8195-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
 	  .data = (void *)MTK_DISP_OVL_2L },
 	{ .compatible = "mediatek,mt8192-disp-ovl-2l",

-- 
Git-146)

[PATCH v3 08/14] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Always add DRM_MODE_ROTATE_0 to rotation property to meet
IGT's (Intel GPU Tools) requirement.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  6 +++++-
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++------------
 drivers/gpu/drm/mediatek/mtk_plane.c    |  2 +-
 3 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 26236691ce4c..f7fe2e08dc8e 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -192,7 +192,11 @@ unsigned int mtk_ddp_comp_supported_rotations(struct mtk_ddp_comp *comp)
 	if (comp->funcs && comp->funcs->supported_rotations)
 		return comp->funcs->supported_rotations(comp->dev);
 
-	return 0;
+	/*
+	 * In order to pass IGT tests, DRM_MODE_ROTATE_0 is required when
+	 * rotation is not supported.
+	 */
+	return DRM_MODE_ROTATE_0;
 }
 
 static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 693560fa34e8..26b598b9f71f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -305,27 +305,20 @@ int mtk_ovl_layer_check(struct device *dev, unsigned int idx,
 			struct mtk_plane_state *mtk_state)
 {
 	struct drm_plane_state *state = &mtk_state->base;
-	unsigned int rotation = 0;
 
-	rotation = drm_rotation_simplify(state->rotation,
-					 DRM_MODE_ROTATE_0 |
-					 DRM_MODE_REFLECT_X |
-					 DRM_MODE_REFLECT_Y);
-	rotation &= ~DRM_MODE_ROTATE_0;
-
-	/* We can only do reflection, not rotation */
-	if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
+	/* check if any unsupported rotation is set */
+	if (state->rotation & ~mtk_ovl_supported_rotations(dev))
 		return -EINVAL;
 
 	/*
 	 * TODO: Rotating/reflecting YUV buffers is not supported at this time.
 	 *	 Only RGB[AX] variants are supported.
+	 *	 Since DRM_MODE_ROTATE_0 means "no rotation", we should not
+	 *	 reject layers with this property.
 	 */
-	if (state->fb->format->is_yuv && rotation != 0)
+	if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0))
 		return -EINVAL;
 
-	state->rotation = rotation;
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c
index a74b26d35985..1723d4333f37 100644
--- a/drivers/gpu/drm/mediatek/mtk_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_plane.c
@@ -338,7 +338,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
 		return err;
 	}
 
-	if (supported_rotations & ~DRM_MODE_ROTATE_0) {
+	if (supported_rotations) {
 		err = drm_plane_create_rotation_property(plane,
 							 DRM_MODE_ROTATE_0,
 							 supported_rotations);

-- 
Git-146)

Re: [PATCH v3 08/14] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property

[Doug Anderson]

Hi,

On Wed, Jun 19, 2024 at 9:39 AM Hsiao Chien Sung via B4 Relay
<devnull+shawn.sung.mediatek.com@kernel.org> wrote:
>
> From: Hsiao Chien Sung <shawn.sung@mediatek.com>
>
> Always add DRM_MODE_ROTATE_0 to rotation property to meet
> IGT's (Intel GPU Tools) requirement.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  6 +++++-
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++------------
>  drivers/gpu/drm/mediatek/mtk_plane.c    |  2 +-
>  3 files changed, 11 insertions(+), 14 deletions(-)

FWIW, this patch got into ChromeOS's 5.15 branch via stable merge and
apparently broke things. As a short term fix we've reverted it there:

https://crrev.com/c/5960799

...apparently the patch is fine on newer kernels so maybe there is a
missing dependency? Hopefully someone on this list can dig into this
and either post the revert to stable 5.15 kernels or suggest
additional backports.


-Doug

Re: [PATCH v3 08/14] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property

[Shawn Sung (宋孝謙)]

Hi Doug,

On Thu, 2024-10-24 at 13:47 -0700, Doug Anderson wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Hi,
> 
> On Wed, Jun 19, 2024 at 9:39 AM Hsiao Chien Sung via B4 Relay
> <devnull+shawn.sung.mediatek.com@kernel.org> wrote:
> >
> > From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> >
> > Always add DRM_MODE_ROTATE_0 to rotation property to meet
> > IGT's (Intel GPU Tools) requirement.
> >
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> > Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC
> MT8173.")
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  6 +++++-
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++------------
> >  drivers/gpu/drm/mediatek/mtk_plane.c    |  2 +-
> >  3 files changed, 11 insertions(+), 14 deletions(-)
> 
> FWIW, this patch got into ChromeOS's 5.15 branch via stable merge and
> apparently broke things. As a short term fix we've reverted it there:
> 
> https://crrev.com/c/5960799
 
Thank you for reporting this issue. We are currently investigating the
bug.

Since I am unable to access the Google issue tracker [1], could you
please provide more details about this bug? The message in the revert
commit mentions "hana/sycamore360" (MT8173) and it appears that there
is a rotation issue in tablet mode.

> 
> ...apparently the patch is fine on newer kernels so maybe there is a
> missing dependency? Hopefully someone on this list can dig into this
> and either post the revert to stable 5.15 kernels or suggest
> additional backports.
> 

There are known issues [2] regarding forward compatibility. Could you
confirm whether this patch is unable to resolve the mentioned problem?
Thanks.

[1] https://issuetracker.google.com/issues/369688659
[2] 
https://patchwork.kernel.org/project/linux-mediatek/list/?series=896964

> 
> -Doug

Best regards,
Shawn

Re: [PATCH v3 08/14] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property

[Doug Anderson]

Hi Shawn,

On Thu, Oct 24, 2024 at 6:32 PM Shawn Sung (宋孝謙)
<Shawn.Sung@mediatek.com> wrote:
>
> Hi Doug,
>
> On Thu, 2024-10-24 at 13:47 -0700, Doug Anderson wrote:
> >
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> >  Hi,
> >
> > On Wed, Jun 19, 2024 at 9:39 AM Hsiao Chien Sung via B4 Relay
> > <devnull+shawn.sung.mediatek.com@kernel.org> wrote:
> > >
> > > From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > >
> > > Always add DRM_MODE_ROTATE_0 to rotation property to meet
> > > IGT's (Intel GPU Tools) requirement.
> > >
> > > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > > Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC
> > MT8173.")
> > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  6 +++++-
> > >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++------------
> > >  drivers/gpu/drm/mediatek/mtk_plane.c    |  2 +-
> > >  3 files changed, 11 insertions(+), 14 deletions(-)
> >
> > FWIW, this patch got into ChromeOS's 5.15 branch via stable merge and
> > apparently broke things. As a short term fix we've reverted it there:
> >
> > https://crrev.com/c/5960799
>
> Thank you for reporting this issue. We are currently investigating the
> bug.
>
> Since I am unable to access the Google issue tracker [1], could you
> please provide more details about this bug? The message in the revert
> commit mentions "hana/sycamore360" (MT8173) and it appears that there
> is a rotation issue in tablet mode.

Thanks for the followup. I've only been peripherally involved in the
problem, but I can at least copy the relevant bits over.

It looks as if the problem is somehow only showing up when running
Android apps on those devices, so whatever the problem is it's subtle.
The report says that the apps work OK when the device is in tablet
mode and in one rotation but the problem shows up when rotated 90
degrees. The report says that "Screen content appears inverted". To me
it also sounds _possible_ that the problem is somewhere in our
userspace.

I think Hsin-Yi and Ross are continuing to dig a bit more. Maybe once
they've dug they can add any details they find or can loop in others
as it makes sense?


> > ...apparently the patch is fine on newer kernels so maybe there is a
> > missing dependency? Hopefully someone on this list can dig into this
> > and either post the revert to stable 5.15 kernels or suggest
> > additional backports.
> >
>
> There are known issues [2] regarding forward compatibility. Could you
> confirm whether this patch is unable to resolve the mentioned problem?
> Thanks.
>
> [1] https://issuetracker.google.com/issues/369688659
> [2]
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=896964

The patches in [2] look related to alpha blending but I think they are
seeing issues related to rotation. ...so I'm going to assume it's
different? I don't have this hardware in front of me, so I'm just
going by the report.

-Doug

Re: [PATCH v3 08/14] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property

[Shawn Sung (宋孝謙)]

Hi Doug,

On Fri, 2024-10-25 at 09:35 -0700, Doug Anderson wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Hi Shawn,
> 
> On Thu, Oct 24, 2024 at 6:32 PM Shawn Sung (宋孝謙)
> <Shawn.Sung@mediatek.com> wrote:
> > 
> > Hi Doug,
> > 
> > On Thu, 2024-10-24 at 13:47 -0700, Doug Anderson wrote:
> > > 
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > >  Hi,
> > > 
> > > On Wed, Jun 19, 2024 at 9:39 AM Hsiao Chien Sung via B4 Relay
> > > <devnull+shawn.sung.mediatek.com@kernel.org> wrote:
> > > > 
> > > > From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > > 
> > > > Always add DRM_MODE_ROTATE_0 to rotation property to meet
> > > > IGT's (Intel GPU Tools) requirement.
> > > > 
> > > > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > 
> > > angelogioacchino.delregno@collabora.com>
> > > > Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek
> > > > SoC
> > > 
> > > MT8173.")
> > > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > > ---
> > > >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  6 +++++-
> > > >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++------------
> > > >  drivers/gpu/drm/mediatek/mtk_plane.c    |  2 +-
> > > >  3 files changed, 11 insertions(+), 14 deletions(-)
> > > 
> > > FWIW, this patch got into ChromeOS's 5.15 branch via stable merge
> > > and
> > > apparently broke things. As a short term fix we've reverted it
> > > there:
> > > 
> > > 
https://urldefense.com/v3/__https://crrev.com/c/5960799__;!!CTRNKA9wMg0ARbw!kSI2lyZJ5F8SCpAFfKCeZsL1qie2qRvpXWPhtD4IlHik7uS4q6hdR6EjPbskQxlTNP6OIBSwPOKU2KtFf5NXKQ$
> > 
> > Thank you for reporting this issue. We are currently investigating
> > the
> > bug.
> > 
> > Since I am unable to access the Google issue tracker [1], could you
> > please provide more details about this bug? The message in the
> > revert
> > commit mentions "hana/sycamore360" (MT8173) and it appears that
> > there
> > is a rotation issue in tablet mode.
> 
> Thanks for the followup. I've only been peripherally involved in the
> problem, but I can at least copy the relevant bits over.
> 
> It looks as if the problem is somehow only showing up when running
> Android apps on those devices, so whatever the problem is it's
> subtle.
> The report says that the apps work OK when the device is in tablet
> mode and in one rotation but the problem shows up when rotated 90
> degrees. The report says that "Screen content appears inverted". To
> me
> it also sounds _possible_ that the problem is somewhere in our
> userspace.

Thank you for providing the details. We have also reached out to our
partner at Google and gained a better understanding of the situation.

We discovered that the capability for 180-degree rotation was not
previously claimed. However, we reported this capability by adding
DRM_MODE_ROTATE_180 to the plane property, as combining flip-x and
flip-y effectively results in a 180-degree rotation. Unfortunately, it
appears that we did not properly handle the rotation property in the
driver, which has led to the current issues.

The reason there is no problem after reverting this patch is likely
because, when the driver does not support rotation, Android apps will
handle screen rotation via software. After this patch, since we claim
that our driver supports 180-degree rotation, the app attempts to
utilize hardware for this function, which has resulted in the bug.

> 
> I think Hsin-Yi and Ross are continuing to dig a bit more. Maybe once
> they've dug they can add any details they find or can loop in others
> as it makes sense?

Thank you for your assistance, and we will continue to investigate this
matter. Since I am no longer involved in the related project, Jason-JH
will assist in investigating this issue and will submit a fix once we
confirm the root cause.

> 
> 
> > > ...apparently the patch is fine on newer kernels so maybe there
> > > is a
> > > missing dependency? Hopefully someone on this list can dig into
> > > this
> > > and either post the revert to stable 5.15 kernels or suggest
> > > additional backports.
> > > 
> > 
> > There are known issues [2] regarding forward compatibility. Could
> > you
> > confirm whether this patch is unable to resolve the mentioned
> > problem?
> > Thanks.
> > 
> > [1] 
> > https://urldefense.com/v3/__https://issuetracker.google.com/issues/369688659__;!!CTRNKA9wMg0ARbw!kSI2lyZJ5F8SCpAFfKCeZsL1qie2qRvpXWPhtD4IlHik7uS4q6hdR6EjPbskQxlTNP6OIBSwPOKU2KsGQwdobA$
> > [2]
> > 
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=896964__;!!CTRNKA9wMg0ARbw!kSI2lyZJ5F8SCpAFfKCeZsL1qie2qRvpXWPhtD4IlHik7uS4q6hdR6EjPbskQxlTNP6OIBSwPOKU2KuXChWBjA$
> 
> The patches in [2] look related to alpha blending but I think they
> are
> seeing issues related to rotation. ...so I'm going to assume it's
> different? I don't have this hardware in front of me, so I'm just
> going by the report.

No problem. Based on your detailed description above, it seems we have
identified the possible cause. 

> 
> -Doug

Best regards,
Shawn

[PATCH v3 09/14] drm/mediatek: Add new color format MACROs in OVL

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Define new color formats to hide the bit operation in the MACROs to make
the switch statement more concise.
Change the MACROs to align the naming rule in DRM.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 26b598b9f71f..33c332b29381 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -55,8 +55,10 @@
 #define OVL_CON_BYTE_SWAP	BIT(24)
 #define OVL_CON_MTX_YUV_TO_RGB	(6 << 16)
 #define OVL_CON_CLRFMT_RGB	(1 << 12)
-#define OVL_CON_CLRFMT_RGBA8888	(2 << 12)
-#define OVL_CON_CLRFMT_ARGB8888	(3 << 12)
+#define OVL_CON_CLRFMT_ARGB8888	(2 << 12)
+#define OVL_CON_CLRFMT_RGBA8888	(3 << 12)
+#define OVL_CON_CLRFMT_ABGR8888	(OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP)
+#define OVL_CON_CLRFMT_BGRA8888	(OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP)
 #define OVL_CON_CLRFMT_UYVY	(4 << 12)
 #define OVL_CON_CLRFMT_YUYV	(5 << 12)
 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
@@ -377,18 +379,18 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
 		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
 	case DRM_FORMAT_RGBX8888:
 	case DRM_FORMAT_RGBA8888:
-		return OVL_CON_CLRFMT_ARGB8888;
+		return OVL_CON_CLRFMT_RGBA8888;
 	case DRM_FORMAT_BGRX8888:
 	case DRM_FORMAT_BGRA8888:
 	case DRM_FORMAT_BGRA1010102:
-		return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
+		return OVL_CON_CLRFMT_BGRA8888;
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_ARGB2101010:
-		return OVL_CON_CLRFMT_RGBA8888;
+		return OVL_CON_CLRFMT_ARGB8888;
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ABGR8888:
-		return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
+		return OVL_CON_CLRFMT_ABGR8888;
 	case DRM_FORMAT_UYVY:
 		return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
 	case DRM_FORMAT_YUYV:

-- 
Git-146)

[PATCH v3 10/14] drm/mediatek: Set DRM mode configs accordingly

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Set DRM mode configs limitation according to the hardware capabilities
and pass the IGT checks as below:

- The test "graphics.IgtKms.kms_plane" requires a frame buffer with
  width of 4512 pixels (> 4096).
- The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size is
  defined, and run the test with cursor size from 1x1 to 512x512.

Please notice that the test conditions may change as IGT is updated.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 22 ++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 8e047043202b..c9cad3a82737 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -294,6 +294,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.conn_routes = mt8188_mtk_ddp_main_routes,
 	.num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
 	.mmsys_dev_num = 2,
+	.max_width = 8191,
+	.min_width = 1,
+	.min_height = 1,
 };
 
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -308,6 +311,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
 	.main_path = mt8195_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
 	.mmsys_dev_num = 2,
+	.max_width = 8191,
+	.min_width = 1,
+	.min_height = 1,
 };
 
 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
@@ -315,6 +321,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
 	.mmsys_id = 1,
 	.mmsys_dev_num = 2,
+	.max_width = 8191,
+	.min_width = 2, /* 2-pixel align when ethdr is bypassed */
+	.min_height = 1,
 };
 
 static const struct of_device_id mtk_drm_of_ids[] = {
@@ -493,6 +502,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
 		for (j = 0; j < private->data->mmsys_dev_num; j++) {
 			priv_n = private->all_drm_private[j];
 
+			if (priv_n->data->max_width)
+				drm->mode_config.max_width = priv_n->data->max_width;
+
+			if (priv_n->data->min_width)
+				drm->mode_config.min_width = priv_n->data->min_width;
+
+			if (priv_n->data->min_height)
+				drm->mode_config.min_height = priv_n->data->min_height;
+
 			if (i == CRTC_MAIN && priv_n->data->main_len) {
 				ret = mtk_crtc_create(drm, priv_n->data->main_path,
 						      priv_n->data->main_len, j,
@@ -520,6 +538,10 @@ static int mtk_drm_kms_init(struct drm_device *drm)
 		}
 	}
 
+	/* IGT will check if the cursor size is configured */
+	drm->mode_config.cursor_width = drm->mode_config.max_width;
+	drm->mode_config.cursor_height = drm->mode_config.max_height;
+
 	/* Use OVL device for all DMA memory allocations */
 	crtc = drm_crtc_from_index(drm, 0);
 	if (crtc)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 78d698ede1bf..ce897984de51 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -46,6 +46,10 @@ struct mtk_mmsys_driver_data {
 	bool shadow_register;
 	unsigned int mmsys_id;
 	unsigned int mmsys_dev_num;
+
+	u16 max_width;
+	u16 min_width;
+	u16 min_height;
 };
 
 struct mtk_drm_private {

-- 
Git-146)

[PATCH v3 11/14] drm/mediatek: Support more 10bit formats in OVL

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Support more 10bit formats in OVL.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 +++++++++++++++++++++++++++++---
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 33c332b29381..767338206780 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -76,6 +76,22 @@
 
 #define OVL_COLOR_ALPHA		GENMASK(31, 24)
 
+static inline bool is_10bit_rgb(u32 fmt)
+{
+	switch (fmt) {
+	case DRM_FORMAT_XRGB2101010:
+	case DRM_FORMAT_ARGB2101010:
+	case DRM_FORMAT_RGBX1010102:
+	case DRM_FORMAT_RGBA1010102:
+	case DRM_FORMAT_XBGR2101010:
+	case DRM_FORMAT_ABGR2101010:
+	case DRM_FORMAT_BGRX1010102:
+	case DRM_FORMAT_BGRA1010102:
+		return true;
+	}
+	return false;
+}
+
 static const u32 mt8173_formats[] = {
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ARGB8888,
@@ -93,12 +109,18 @@ static const u32 mt8173_formats[] = {
 static const u32 mt8195_formats[] = {
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XRGB2101010,
 	DRM_FORMAT_ARGB2101010,
 	DRM_FORMAT_BGRX8888,
 	DRM_FORMAT_BGRA8888,
+	DRM_FORMAT_BGRX1010102,
 	DRM_FORMAT_BGRA1010102,
 	DRM_FORMAT_ABGR8888,
 	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_RGBX1010102,
+	DRM_FORMAT_RGBA1010102,
 	DRM_FORMAT_RGB888,
 	DRM_FORMAT_BGR888,
 	DRM_FORMAT_RGB565,
@@ -258,9 +280,7 @@ static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format,
 	reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT);
 	reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx);
 
-	if (format == DRM_FORMAT_RGBA1010102 ||
-	    format == DRM_FORMAT_BGRA1010102 ||
-	    format == DRM_FORMAT_ARGB2101010)
+	if (is_10bit_rgb(format))
 		bit_depth = OVL_CON_CLRFMT_10_BIT;
 
 	reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx);
@@ -379,17 +399,23 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
 		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
 	case DRM_FORMAT_RGBX8888:
 	case DRM_FORMAT_RGBA8888:
+	case DRM_FORMAT_RGBX1010102:
+	case DRM_FORMAT_RGBA1010102:
 		return OVL_CON_CLRFMT_RGBA8888;
 	case DRM_FORMAT_BGRX8888:
 	case DRM_FORMAT_BGRA8888:
+	case DRM_FORMAT_BGRX1010102:
 	case DRM_FORMAT_BGRA1010102:
 		return OVL_CON_CLRFMT_BGRA8888;
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_ARGB8888:
+	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_ARGB2101010:
 		return OVL_CON_CLRFMT_ARGB8888;
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ABGR8888:
+	case DRM_FORMAT_XBGR2101010:
+	case DRM_FORMAT_ABGR2101010:
 		return OVL_CON_CLRFMT_ABGR8888;
 	case DRM_FORMAT_UYVY:
 		return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;

-- 
Git-146)

[PATCH v3 12/14] drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Support RGBA8888 and RGBX8888 formats in OVL on MT8195.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 767338206780..943db4f1bd6b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -119,6 +119,8 @@ static const u32 mt8195_formats[] = {
 	DRM_FORMAT_XBGR8888,
 	DRM_FORMAT_XBGR2101010,
 	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_RGBX8888,
+	DRM_FORMAT_RGBA8888,
 	DRM_FORMAT_RGBX1010102,
 	DRM_FORMAT_RGBA1010102,
 	DRM_FORMAT_RGB888,

-- 
Git-146)

[PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Set the plane alpha according to DRM plane property.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 943db4f1bd6b..4b370bc0746d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -458,8 +458,10 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 	}
 
 	con = ovl_fmt_convert(ovl, fmt);
-	if (state->base.fb && state->base.fb->format->has_alpha)
-		con |= OVL_CON_AEN | OVL_CON_ALPHA;
+	if (state->base.fb) {
+		con |= OVL_CON_AEN;
+		con |= state->base.alpha & OVL_CON_ALPHA;
+	}
 
 	/* CONST_BLD must be enabled for XRGB formats although the alpha channel
 	 * can be ignored, or OVL will still read the value from memory.

-- 
Git-146)

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Adam Thiede]

On 6/19/24 11:38, Hsiao Chien Sung via B4 Relay wrote:
> From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> 
> Set the plane alpha according to DRM plane property.
> 
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>   drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 943db4f1bd6b..4b370bc0746d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -458,8 +458,10 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
>   	}
>   
>   	con = ovl_fmt_convert(ovl, fmt);
> -	if (state->base.fb && state->base.fb->format->has_alpha)
> -		con |= OVL_CON_AEN | OVL_CON_ALPHA;
> +	if (state->base.fb) {
> +		con |= OVL_CON_AEN;
> +		con |= state->base.alpha & OVL_CON_ALPHA;
> +	}
>   
>   	/* CONST_BLD must be enabled for XRGB formats although the alpha channel
>   	 * can be ignored, or OVL will still read the value from memory.
> 
Hello, I believe that this commit has caused a problem for my Lenovo 
C330 Chromebook running postmarketOS.

With kernel 6.11 this device didn't show any text on the tty or splash 
screen during booting, but graphical environments (wayland, xorg) do 
appear. With a few bisects I found it to be this commit. With it 
reverted I'm able to get text on the tty again.

The kernel config is here: 
https://gitlab.com/adamthiede/pmaports/-/tree/mt8173-611/device/community/linux-postmarketos-mediatek-mt8173/
To be perfectly clear, this device is not running Chrome OS.

I'm still rather new at this so it's also likely I got something wrong 
or have a bad configuration option. If there is any more information I 
can provide please let me know. Thank you.

- Adam Thiede

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[CK Hu (胡俊光)]

Hi, Jason:

Would you clarify this problem?

Regards,
CK

On Mon, 2024-09-30 at 12:48 -0500, Adam Thiede wrote:
>  	 
> External email : Please do not click links or open attachments until you have verified the sender or the content.
>  On 6/19/24 11:38, Hsiao Chien Sung via B4 Relay wrote:
> > From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > 
> > Set the plane alpha according to DRM plane property.
> > 
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > ---
> >   drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++--
> >   1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index 943db4f1bd6b..4b370bc0746d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -458,8 +458,10 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
> >   }
> >   
> >   con = ovl_fmt_convert(ovl, fmt);
> > -if (state->base.fb && state->base.fb->format->has_alpha)
> > -con |= OVL_CON_AEN | OVL_CON_ALPHA;
> > +if (state->base.fb) {
> > +con |= OVL_CON_AEN;
> > +con |= state->base.alpha & OVL_CON_ALPHA;
> > +}
> >   
> >   /* CONST_BLD must be enabled for XRGB formats although the alpha channel
> >    * can be ignored, or OVL will still read the value from memory.
> > 
> Hello, I believe that this commit has caused a problem for my Lenovo 
> C330 Chromebook running postmarketOS.
> 
> With kernel 6.11 this device didn't show any text on the tty or splash 
> screen during booting, but graphical environments (wayland, xorg) do 
> appear. With a few bisects I found it to be this commit. With it 
> reverted I'm able to get text on the tty again.
> 
> The kernel config is here: 
> https://gitlab.com/adamthiede/pmaports/-/tree/mt8173-611/device/community/linux-postmarketos-mediatek-mt8173/
> To be perfectly clear, this device is not running Chrome OS.
> 
> I'm still rather new at this so it's also likely I got something wrong 
> or have a bad configuration option. If there is any more information I 
> can provide please let me know. Thank you.
> 
> - Adam Thiede

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Jason-JH Lin (林睿祥)]

On Tue, 2024-10-01 at 08:55 +0000, CK Hu (胡俊光) wrote:
> Hi, Jason:
> 
> Would you clarify this problem?
> 

OK~

> Regards,
> CK
> 
> On Mon, 2024-09-30 at 12:48 -0500, Adam Thiede wrote:
> >  	 
> > External email : Please do not click links or open attachments
> > until you have verified the sender or the content.
> >  On 6/19/24 11:38, Hsiao Chien Sung via B4 Relay wrote:
> > > From: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > 
> > > Set the plane alpha according to DRM plane property.
> > > 
> > > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek
> > > SoC MT8173.")
> > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> > > ---
> > >   drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++--
> > >   1 file changed, 4 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > > index 943db4f1bd6b..4b370bc0746d 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > > @@ -458,8 +458,10 @@ void mtk_ovl_layer_config(struct device
> > > *dev, unsigned int idx,
> > >   }
> > >   
> > >   con = ovl_fmt_convert(ovl, fmt);
> > > -if (state->base.fb && state->base.fb->format->has_alpha)
> > > -con |= OVL_CON_AEN | OVL_CON_ALPHA;
> > > +if (state->base.fb) {
> > > +con |= OVL_CON_AEN;
> > > +con |= state->base.alpha & OVL_CON_ALPHA;

Hi Adam,

Could you print out the "fmt", "state->base.fb->format-
>has_alpha", "state->base.alpha" and "con" here?

pr_info("fmt:0x%x, has_alpha:0x%x, alpha:0x%x, con:0x%x \n",
        fmt, state->base.fb->format->has_alpha,
        state->base.alpha, con);

I'm not sure if it's the color format setting problem, maybe there is
something wire configuration here, such as XRGB8888 with alpha or
ARGB8888 without alpha.

So I want these information to compare with my MT8188. Thanks!

Regards,
Jason-JH.Lin

> > > +}
> > >   
> > >   /* CONST_BLD must be enabled for XRGB formats although the
> > > alpha channel
> > >    * can be ignored, or OVL will still read the value from
> > > memory.
> > > 
> > 
> > Hello, I believe that this commit has caused a problem for my
> > Lenovo 
> > C330 Chromebook running postmarketOS.
> > 
> > With kernel 6.11 this device didn't show any text on the tty or
> > splash 
> > screen during booting, but graphical environments (wayland, xorg)
> > do 
> > appear. With a few bisects I found it to be this commit. With it 
> > reverted I'm able to get text on the tty again.
> > 
> > The kernel config is here: 
> > 
https://gitlab.com/adamthiede/pmaports/-/tree/mt8173-611/device/community/linux-postmarketos-mediatek-mt8173/
> > To be perfectly clear, this device is not running Chrome OS.
> > 
> > I'm still rather new at this so it's also likely I got something
> > wrong 
> > or have a bad configuration option. If there is any more
> > information I 
> > can provide please let me know. Thank you.
> > 
> > - Adam Thiede

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Adam Thiede]

On 10/1/24 13:02, Jason-JH Lin (林睿祥) wrote:
> On Tue, 2024-10-01 at 08:55 +0000, CK Hu (胡俊光) wrote:
>> Hi, Jason:
>> 
>> Would you clarify this problem?
>> 
> 
> OK~
> 
>> Regards,
>> CK
>> 
>> On Mon, 2024-09-30 at 12:48 -0500, Adam Thiede wrote:
>> >   
>> > External email : Please do not click links or open attachments
>> > until you have verified the sender or the content.
>> >  On 6/19/24 11:38, Hsiao Chien Sung via B4 Relay wrote:
>> > > From: Hsiao Chien Sung <shawn.sung@mediatek.com>
>> > > 
>> > > Set the plane alpha according to DRM plane property.
>> > > 
>> > > Reviewed-by: CK Hu <ck.hu@mediatek.com>
>> > > Reviewed-by: AngeloGioacchino Del Regno <
>> > > angelogioacchino.delregno@collabora.com>
>> > > Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek
>> > > SoC MT8173.")
>> > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
>> > > ---
>> > >   drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 6 ++++--
>> > >   1 file changed, 4 insertions(+), 2 deletions(-)
>> > > 
>> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> > > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> > > index 943db4f1bd6b..4b370bc0746d 100644
>> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> > > @@ -458,8 +458,10 @@ void mtk_ovl_layer_config(struct device
>> > > *dev, unsigned int idx,
>> > >   }
>> > >   
>> > >   con = ovl_fmt_convert(ovl, fmt);
>> > > -if (state->base.fb && state->base.fb->format->has_alpha)
>> > > -con |= OVL_CON_AEN | OVL_CON_ALPHA;
>> > > +if (state->base.fb) {
>> > > +con |= OVL_CON_AEN;
>> > > +con |= state->base.alpha & OVL_CON_ALPHA;
> 
> Hi Adam,
> 
> Could you print out the "fmt", "state->base.fb->format-
>>has_alpha", "state->base.alpha" and "con" here?
> 
> pr_info("fmt:0x%x, has_alpha:0x%x, alpha:0x%x, con:0x%x \n",
>          fmt, state->base.fb->format->has_alpha,
>          state->base.alpha, con);
> 
> I'm not sure if it's the color format setting problem, maybe there is
> something wire configuration here, such as XRGB8888 with alpha or
> ARGB8888 without alpha.
> 
> So I want these information to compare with my MT8188. Thanks!
> 
> Regards,
> Jason-JH.Lin
> 
Jason, thank you for your timely reply. I added the code you provided to 
my patch, and now get this line on endless repeat in dmesg:

fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000

This line also shows up sometimes in there, but I have no idea what 
triggers it.

fmt:0x34325241, has_alpha:0x1, alpha:0xffff, con:0x21ff

Does that help?

-Adam

>> > > +}
>> > >   
>> > >   /* CONST_BLD must be enabled for XRGB formats although the
>> > > alpha channel
>> > >    * can be ignored, or OVL will still read the value from
>> > > memory.
>> > > 
>> > 
>> > Hello, I believe that this commit has caused a problem for my
>> > Lenovo 
>> > C330 Chromebook running postmarketOS.
>> > 
>> > With kernel 6.11 this device didn't show any text on the tty or
>> > splash 
>> > screen during booting, but graphical environments (wayland, xorg)
>> > do 
>> > appear. With a few bisects I found it to be this commit. With it 
>> > reverted I'm able to get text on the tty again.
>> > 
>> > The kernel config is here: 
>> > 
> https://gitlab.com/adamthiede/pmaports/-/tree/mt8173-611/device/community/linux-postmarketos-mediatek-mt8173/
>> > To be perfectly clear, this device is not running Chrome OS.
>> > 
>> > I'm still rather new at this so it's also likely I got something
>> > wrong 
>> > or have a bad configuration option. If there is any more
>> > information I 
>> > can provide please let me know. Thank you.
>> > 
>> > - Adam Thiede
> 
> ************* MEDIATEK Confidentiality Notice ********************
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> exempt from disclosure under applicable laws. It is intended to be
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> disclose the content of this e-mail to any other person. Thank you!

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Jason-JH Lin (林睿祥)]

> >> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> >> > > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> >> > > index 943db4f1bd6b..4b370bc0746d 100644
> >> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> >> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> >> > > @@ -458,8 +458,10 @@ void mtk_ovl_layer_config(struct device
> >> > > *dev, unsigned int idx,
> >> > >   }
> >> > >   
> >> > >   con = ovl_fmt_convert(ovl, fmt);
> >> > > -if (state->base.fb && state->base.fb->format->has_alpha)
> >> > > -con |= OVL_CON_AEN | OVL_CON_ALPHA;
> >> > > +if (state->base.fb) {
> >> > > +con |= OVL_CON_AEN;
> >> > > +con |= state->base.alpha & OVL_CON_ALPHA;
> > 
> > Hi Adam,
> > 
> > Could you print out the "fmt", "state->base.fb->format-
> >>has_alpha", "state->base.alpha" and "con" here?
> > 
> > pr_info("fmt:0x%x, has_alpha:0x%x, alpha:0x%x, con:0x%x \n",
> >          fmt, state->base.fb->format->has_alpha,
> >          state->base.alpha, con);
> > 
> > I'm not sure if it's the color format setting problem, maybe there
> is
> > something wire configuration here, such as XRGB8888 with alpha or
> > ARGB8888 without alpha.
> > 
> > So I want these information to compare with my MT8188. Thanks!
> > 
> > Regards,
> > Jason-JH.Lin
> > 
> Jason, thank you for your timely reply. I added the code you provided
> to 
> my patch, and now get this line on endless repeat in dmesg:
> 
> fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000
> 

This function is used to configure the 4 OVL hardware layer per-frame,
so it may be called 4 times in every VSYNC. If your display device is
60fps, then this line would be called N layers times in every 16.66ms.

> This line also shows up sometimes in there, but I have no idea what 
> triggers it.
> 
> fmt:0x34325241, has_alpha:0x1, alpha:0xffff, con:0x21ff
> 

From the DRM color format definition here:

https://elixir.bootlin.com/linux/v6.11.1/source/include/uapi/drm/drm_fourcc.h#L198

We can see the MACROs:
#define fourcc_code(a, b, c, d) \
        (((uint32_t)(a) << 0) | ((uint32_t)(b) << 8) | \
        ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
...
#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4')
...
#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4')

Given the fourcc_code macro as previously described,
the DRM_FORMAT_XRGB8888 macro would translate the characters
'X', 'R', '2', '4' into a 32-bit integer value, with each character
occupying 8 bits in the order from least significant byte to most 
significant byte.

Here are the ASCII values for these characters:

'A' has an ASCII value of 65 (0x41)
'X' has an ASCII value of 88 (0x58)
'R' has an ASCII value of 82 (0x52)
'2' has an ASCII value of 50 (0x32)
'4' has an ASCII value of 52 (0x34)

Therefore, the integer value of XR24 with hex format would be:
0x34325258, and AR24 would be: 0x34325241

> Does that help?
> 
> -Adam

Here is the translation from your logs :

fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000
- DRM color format=XRGB8888
- user set has_alpha=0
- user set alpha value=0xff
- configure value to OVL hardware=0x2000

fmt:0x34325241, has_alpha:0x1, alpha:0xffff, con:0x21ff
- DRM color format=ARGB8888
- user set has_alpha=1
- user set alpha value=0xff
- configure value to OVL hardware=0x21ff

Could you tell me in which log you can see and not see the text on the
tty?



Here is some of my analysis:

In original condition:
if (state->base.fb && state->base.fb->format->has_alpha)
	con |= OVL_CON_AEN | OVL_CON_ALPHA;
- XRGB8888 will get con = 0x2000
- ARGB8888 will get con = 0x21ff
	
In current condition:
if (state->base.fb) {
	con |= OVL_CON_AEN;
	con |= state->base.alpha & OVL_CON_ALPHA;
}
- XRGB8888 will get con = 0x21ff
- ARGB8888 will get con = 0x21ff

But then XRGB8888 will set the ignore_pixel_alpha by the code below:
/* CONST_BLD must be enabled for XRGB formats although the alpha
channel
 * can be ignored, or OVL will still read the value from memory.
 * For RGB888 related formats, whether CONST_BLD is enabled or not
won't
 * affect the result. Therefore we use !has_alpha as the condition.
 */
if ((state->base.fb && !state->base.fb->format->has_alpha) ||
    blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
	ignore_pixel_alpha = OVL_CONST_BLEND;

Does your code include this patch?

https://patchwork.kernel.org/project/linux-mediatek/patch/20240620-igt-v3-3-a9d62d2e2c7e@mediatek.com/

If you have included this patch, I would then check with the OVL
hardware designers whether the MT8173 supports OVL_CONST_BLEND.

Regards,
Jason-JH.Lin

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Adam Thiede]

On 10/2/24 02:50, Jason-JH Lin (林睿祥) wrote:
>> >> > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> >> > > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> >> > > index 943db4f1bd6b..4b370bc0746d 100644
>> >> > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> >> > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> >> > > @@ -458,8 +458,10 @@ void mtk_ovl_layer_config(struct device
>> >> > > *dev, unsigned int idx,
>> >> > >   }
>> >> > >   
>> >> > >   con = ovl_fmt_convert(ovl, fmt);
>> >> > > -if (state->base.fb && state->base.fb->format->has_alpha)
>> >> > > -con |= OVL_CON_AEN | OVL_CON_ALPHA;
>> >> > > +if (state->base.fb) {
>> >> > > +con |= OVL_CON_AEN;
>> >> > > +con |= state->base.alpha & OVL_CON_ALPHA;
>> > 
>> > Hi Adam,
>> > 
>> > Could you print out the "fmt", "state->base.fb->format-
>> >>has_alpha", "state->base.alpha" and "con" here?
>> > 
>> > pr_info("fmt:0x%x, has_alpha:0x%x, alpha:0x%x, con:0x%x \n",
>> >          fmt, state->base.fb->format->has_alpha,
>> >          state->base.alpha, con);
>> > 
>> > I'm not sure if it's the color format setting problem, maybe there
>> is
>> > something wire configuration here, such as XRGB8888 with alpha or
>> > ARGB8888 without alpha.
>> > 
>> > So I want these information to compare with my MT8188. Thanks!
>> > 
>> > Regards,
>> > Jason-JH.Lin
>> > 
>> Jason, thank you for your timely reply. I added the code you provided
>> to 
>> my patch, and now get this line on endless repeat in dmesg:
>> 
>> fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000
>> 
> 
> This function is used to configure the 4 OVL hardware layer per-frame,
> so it may be called 4 times in every VSYNC. If your display device is
> 60fps, then this line would be called N layers times in every 16.66ms.
> 
>> This line also shows up sometimes in there, but I have no idea what 
>> triggers it.
>> 
>> fmt:0x34325241, has_alpha:0x1, alpha:0xffff, con:0x21ff
>> 
> 
>  From the DRM color format definition here:
> 
> https://elixir.bootlin.com/linux/v6.11.1/source/include/uapi/drm/drm_fourcc.h#L198
> 
> We can see the MACROs:
> #define fourcc_code(a, b, c, d) \
>          (((uint32_t)(a) << 0) | ((uint32_t)(b) << 8) | \
>          ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
> ...
> #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4')
> ...
> #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4')
> 
> Given the fourcc_code macro as previously described,
> the DRM_FORMAT_XRGB8888 macro would translate the characters
> 'X', 'R', '2', '4' into a 32-bit integer value, with each character
> occupying 8 bits in the order from least significant byte to most
> significant byte.
> 
> Here are the ASCII values for these characters:
> 
> 'A' has an ASCII value of 65 (0x41)
> 'X' has an ASCII value of 88 (0x58)
> 'R' has an ASCII value of 82 (0x52)
> '2' has an ASCII value of 50 (0x32)
> '4' has an ASCII value of 52 (0x34)
> 
> Therefore, the integer value of XR24 with hex format would be:
> 0x34325258, and AR24 would be: 0x34325241
> 
>> Does that help?
>> 
>> -Adam
> 
> Here is the translation from your logs :
> 
> fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000
> - DRM color format=XRGB8888
> - user set has_alpha=0
> - user set alpha value=0xff
> - configure value to OVL hardware=0x2000
> 
> fmt:0x34325241, has_alpha:0x1, alpha:0xffff, con:0x21ff
> - DRM color format=ARGB8888
> - user set has_alpha=1
> - user set alpha value=0xff
> - configure value to OVL hardware=0x21ff
> 
> Could you tell me in which log you can see and not see the text on the
> tty?
> 
> 
> 
> Here is some of my analysis:
> 
> In original condition:
> if (state->base.fb && state->base.fb->format->has_alpha)
> con |= OVL_CON_AEN | OVL_CON_ALPHA;
> - XRGB8888 will get con = 0x2000
> - ARGB8888 will get con = 0x21ff
> 
> In current condition:
> if (state->base.fb) {
> con |= OVL_CON_AEN;
> con |= state->base.alpha & OVL_CON_ALPHA;
> }
> - XRGB8888 will get con = 0x21ff
> - ARGB8888 will get con = 0x21ff
> 
> But then XRGB8888 will set the ignore_pixel_alpha by the code below:
> /* CONST_BLD must be enabled for XRGB formats although the alpha
> channel
>   * can be ignored, or OVL will still read the value from memory.
>   * For RGB888 related formats, whether CONST_BLD is enabled or not
> won't
>   * affect the result. Therefore we use !has_alpha as the condition.
>   */
> if ((state->base.fb && !state->base.fb->format->has_alpha) ||
>      blend_mode == DRM_MODE_BLEND_PIXEL_NONE)
> ignore_pixel_alpha = OVL_CONST_BLEND;
> 
> Does your code include this patch?
> 
> https://patchwork.kernel.org/project/linux-mediatek/patch/20240620-igt-v3-3-a9d62d2e2c7e@mediatek.com/
> 
> If you have included this patch, I would then check with the OVL
> hardware designers whether the MT8173 supports OVL_CONST_BLEND.
> 
> Regards,
> Jason-JH.Lin
Jason:
That is a lot of information, and quite above my head! Thank you though.

I should note that the log items I sent you are from the "good" kernel - 
6.11 with the commit reverted. Here is a much longer set of logs: 
https://termbin.com/co6v

I've rebuild 6.11 with the log statement enabled and the "bad" behavior.
Here is a dmesg from that: https://termbin.com/xiev

These logs are both from `dmesg`.

I'm fairly certain I've built with the patch you referenced enabled. The 
kernels I run are just release kernels, not RCs or git branches or 
anything. The mainline v6.11 kernel is the one that has this problem. If 
that patch has been merged into 6.11 (which, looks like it has) then 
it's in the kernel I'm building.

- Adam Thiede

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Jason-JH Lin (林睿祥)]

> Jason:
> That is a lot of information, and quite above my head! Thank you
> though.
> 
> I should note that the log items I sent you are from the "good"
> kernel - 
> 6.11 with the commit reverted. Here is a much longer set of logs: 
> https://termbin.com/co6v
> 
> I've rebuild 6.11 with the log statement enabled and the "bad"
> behavior.
> Here is a dmesg from that: https://termbin.com/xiev
> 
Hi Adam,

I think something wrong with your dmesg links, both logs look the same.
We should see this log in the "bad" one:
fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000

But anyway, I think the reason for the downgrade is clear enough to me.
So let's try to figure out the solution.

> These logs are both from `dmesg`.
> 
> I'm fairly certain I've built with the patch you referenced enabled.
> The 
> kernels I run are just release kernels, not RCs or git branches or 
> anything. The mainline v6.11 kernel is the one that has this problem.
> If 
> that patch has been merged into 6.11 (which, looks like it has) then 
> it's in the kernel I'm building.

Got it.
Then OVL_CONST_BLEND might be the unsupported configuration in MT8173,
I think we should remove the XRGB8888 format for MT8173.

Could you please try this modification and see if it'll change to use
others supported format to show the text?

--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -102,12 +102,9 @@ static inline bool is_10bit_rgb(u32 fmt)
 }

 static const u32 mt8173_formats[] = {
-       DRM_FORMAT_XRGB8888,
        DRM_FORMAT_ARGB8888,
-       DRM_FORMAT_BGRX8888,
        DRM_FORMAT_BGRA8888,
        DRM_FORMAT_ABGR8888,
-       DRM_FORMAT_XBGR8888,
        DRM_FORMAT_RGB888,
        DRM_FORMAT_BGR888,
        DRM_FORMAT_RGB565,


Regards,
Jason-JH.Lin

> 
> - Adam Thiede

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Adam Thiede]

On 10/3/24 00:17, Jason-JH Lin (林睿祥) wrote:
>> Jason:
>> That is a lot of information, and quite above my head! Thank you
>> though.
>> 
>> I should note that the log items I sent you are from the "good"
>> kernel - 
>> 6.11 with the commit reverted. Here is a much longer set of logs: 
>> https://termbin.com/co6v
>> 
>> I've rebuild 6.11 with the log statement enabled and the "bad"
>> behavior.
>> Here is a dmesg from that: https://termbin.com/xiev
>> 
> Hi Adam,
> 
> I think something wrong with your dmesg links, both logs look the same.
> We should see this log in the "bad" one:
> fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000

Apologies, I did indeed upload the same file twice. Here is the "good" one:
https://termbin.com/tb33

And the "bad" one:
https://termbin.com/yhxx

I think the fact that we're not seeing that line in the "bad" one is 
part of the problem?
> 
> But anyway, I think the reason for the downgrade is clear enough to me.
> So let's try to figure out the solution.
> 
>> These logs are both from `dmesg`.
>> 
>> I'm fairly certain I've built with the patch you referenced enabled.
>> The 
>> kernels I run are just release kernels, not RCs or git branches or 
>> anything. The mainline v6.11 kernel is the one that has this problem.
>> If 
>> that patch has been merged into 6.11 (which, looks like it has) then 
>> it's in the kernel I'm building.
> 
> Got it.
> Then OVL_CONST_BLEND might be the unsupported configuration in MT8173,
> I think we should remove the XRGB8888 format for MT8173.
> 
> Could you please try this modification and see if it'll change to use
> others supported format to show the text?
> 
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -102,12 +102,9 @@ static inline bool is_10bit_rgb(u32 fmt)
>   }
> 
>   static const u32 mt8173_formats[] = {
> -       DRM_FORMAT_XRGB8888,
>          DRM_FORMAT_ARGB8888,
> -       DRM_FORMAT_BGRX8888,
>          DRM_FORMAT_BGRA8888,
>          DRM_FORMAT_ABGR8888,
> -       DRM_FORMAT_XBGR8888,
>          DRM_FORMAT_RGB888,
>          DRM_FORMAT_BGR888,
>          DRM_FORMAT_RGB565,
> 
I've not been able to get the kernel to build with that patch; it keeps 
segfaulting at the end. I will keep attempting though.

> 
> Regards,
> Jason-JH.Lin
> 
>> 
>> - Adam Thiede

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Yassine Oudjana]

On 03/10/2024 8:17 am, Jason-JH Lin (林睿祥) wrote:
>> Jason:
>> That is a lot of information, and quite above my head! Thank you
>> though.
>>
>> I should note that the log items I sent you are from the "good"
>> kernel -
>> 6.11 with the commit reverted. Here is a much longer set of logs:
>> https://termbin.com/co6v
>>
>> I've rebuild 6.11 with the log statement enabled and the "bad"
>> behavior.
>> Here is a dmesg from that: https://termbin.com/xiev
>>
> Hi Adam,
> 
> I think something wrong with your dmesg links, both logs look the same.
> We should see this log in the "bad" one:
> fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000
> 
> But anyway, I think the reason for the downgrade is clear enough to me.
> So let's try to figure out the solution.
> 
>> These logs are both from `dmesg`.
>>
>> I'm fairly certain I've built with the patch you referenced enabled.
>> The
>> kernels I run are just release kernels, not RCs or git branches or
>> anything. The mainline v6.11 kernel is the one that has this problem.
>> If
>> that patch has been merged into 6.11 (which, looks like it has) then
>> it's in the kernel I'm building.
> 
> Got it.
> Then OVL_CONST_BLEND might be the unsupported configuration in MT8173,
> I think we should remove the XRGB8888 format for MT8173.

I've carried patches that add MT6735 support in my tree for a while and 
MT6735 broke as well with this patch. Turns out MT6735's OVL doesn't 
have the CONST_BLEND bit. It's highly likely MT8173 also doesn't since 
MT8173's DISPSYS is very similar to MT6735's.

> 
> Could you please try this modification and see if it'll change to use
> others supported format to show the text?
> 
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -102,12 +102,9 @@ static inline bool is_10bit_rgb(u32 fmt)
>   }
> 
>   static const u32 mt8173_formats[] = {
> -       DRM_FORMAT_XRGB8888,
>          DRM_FORMAT_ARGB8888,
> -       DRM_FORMAT_BGRX8888,
>          DRM_FORMAT_BGRA8888,
>          DRM_FORMAT_ABGR8888,
> -       DRM_FORMAT_XBGR8888,
>          DRM_FORMAT_RGB888,
>          DRM_FORMAT_BGR888,
>          DRM_FORMAT_RGB565,
> 
> 
> Regards,
> Jason-JH.Lin
> 
>>
>> - Adam Thiede

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Yassine Oudjana]

On 03/10/2024 8:17 am, Jason-JH Lin (林睿祥) wrote:
>> Jason:
>> That is a lot of information, and quite above my head! Thank you
>> though.
>>
>> I should note that the log items I sent you are from the "good"
>> kernel -
>> 6.11 with the commit reverted. Here is a much longer set of logs:
>> https://termbin.com/co6v
>>
>> I've rebuild 6.11 with the log statement enabled and the "bad"
>> behavior.
>> Here is a dmesg from that: https://termbin.com/xiev
>>
> Hi Adam,
> 
> I think something wrong with your dmesg links, both logs look the same.
> We should see this log in the "bad" one:
> fmt:0x34325258, has_alpha:0x0, alpha:0xffff, con:0x2000
> 
> But anyway, I think the reason for the downgrade is clear enough to me.
> So let's try to figure out the solution.
> 
>> These logs are both from `dmesg`.
>>
>> I'm fairly certain I've built with the patch you referenced enabled.
>> The
>> kernels I run are just release kernels, not RCs or git branches or
>> anything. The mainline v6.11 kernel is the one that has this problem.
>> If
>> that patch has been merged into 6.11 (which, looks like it has) then
>> it's in the kernel I'm building.
> 
> Got it.
> Then OVL_CONST_BLEND might be the unsupported configuration in MT8173,
> I think we should remove the XRGB8888 format for MT8173.
> 
> Could you please try this modification and see if it'll change to use
> others supported format to show the text?
> 
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -102,12 +102,9 @@ static inline bool is_10bit_rgb(u32 fmt)
>   }
> 
>   static const u32 mt8173_formats[] = {
> -       DRM_FORMAT_XRGB8888,
>          DRM_FORMAT_ARGB8888,
> -       DRM_FORMAT_BGRX8888,
>          DRM_FORMAT_BGRA8888,
>          DRM_FORMAT_ABGR8888,
> -       DRM_FORMAT_XBGR8888,
>          DRM_FORMAT_RGB888,
>          DRM_FORMAT_BGR888,
>          DRM_FORMAT_RGB565,

This is what I get on MT6735:

[    1.729467] mediatek-drm mediatek-drm.1.auto: [drm] bpp/depth value 
of 32/24 not supported
[    1.737777] mediatek-drm mediatek-drm.1.auto: [drm] No compatible 
format found
[    1.745943] mediatek-drm mediatek-drm.1.auto: [drm] *ERROR* 
fbdev-dma: Failed to setup generic emulation (ret=-22)

> 
> Regards,
> Jason-JH.Lin
> 
>>
>> - Adam Thiede

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Jason-JH Lin (林睿祥)]

> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -102,12 +102,9 @@ static inline bool is_10bit_rgb(u32 fmt)
> >   }
> > 
> >   static const u32 mt8173_formats[] = {
> > -       DRM_FORMAT_XRGB8888,
> >          DRM_FORMAT_ARGB8888,
> > -       DRM_FORMAT_BGRX8888,
> >          DRM_FORMAT_BGRA8888,
> >          DRM_FORMAT_ABGR8888,
> > -       DRM_FORMAT_XBGR8888,
> >          DRM_FORMAT_RGB888,
> >          DRM_FORMAT_BGR888,
> >          DRM_FORMAT_RGB565,
> 
> This is what I get on MT6735:
> 
> [    1.729467] mediatek-drm mediatek-drm.1.auto: [drm] bpp/depth
> value 
> of 32/24 not supported
> [    1.737777] mediatek-drm mediatek-drm.1.auto: [drm] No compatible 
> format found
> [    1.745943] mediatek-drm mediatek-drm.1.auto: [drm] *ERROR* 
> fbdev-dma: Failed to setup generic emulation (ret=-22)
> 

Hi Adam, Yassine,

Please try the patches below and check if they can fix the downgrade
issue:
[1] Fix degradation problem of alpha blending series
- 
https://patchwork.kernel.org/project/linux-mediatek/list/?series=893634
[2] drm/mediatek: Fix XRGB format breakage for blend_modes unsupported
SoCs
- 
https://patchwork.kernel.org/project/linux-mediatek/patch/20241005095234.12925-1-jason-jh.lin@mediatek.com/

Regards,
Jason-JH.Lin

> > 
> > Regards,
> > Jason-JH.Lin
> > 
> >>
> >> - Adam Thiede
> 

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Adam Thiede]

On 10/5/24 05:02, Jason-JH Lin (林睿祥) wrote:
>> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>> > @@ -102,12 +102,9 @@ static inline bool is_10bit_rgb(u32 fmt)
>> >   }
>> > 
>> >   static const u32 mt8173_formats[] = {
>> > -       DRM_FORMAT_XRGB8888,
>> >          DRM_FORMAT_ARGB8888,
>> > -       DRM_FORMAT_BGRX8888,
>> >          DRM_FORMAT_BGRA8888,
>> >          DRM_FORMAT_ABGR8888,
>> > -       DRM_FORMAT_XBGR8888,
>> >          DRM_FORMAT_RGB888,
>> >          DRM_FORMAT_BGR888,
>> >          DRM_FORMAT_RGB565,
>> 
>> This is what I get on MT6735:
>> 
>> [    1.729467] mediatek-drm mediatek-drm.1.auto: [drm] bpp/depth
>> value 
>> of 32/24 not supported
>> [    1.737777] mediatek-drm mediatek-drm.1.auto: [drm] No compatible 
>> format found
>> [    1.745943] mediatek-drm mediatek-drm.1.auto: [drm] *ERROR* 
>> fbdev-dma: Failed to setup generic emulation (ret=-22)
>> 
> 
> Hi Adam, Yassine,
> 
> Please try the patches below and check if they can fix the downgrade
> issue:
> [1] Fix degradation problem of alpha blending series
> -
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=893634
> [2] drm/mediatek: Fix XRGB format breakage for blend_modes unsupported
> SoCs
> -
> https://patchwork.kernel.org/project/linux-mediatek/patch/20241005095234.12925-1-jason-jh.lin@mediatek.com/
> 
> Regards,
> Jason-JH.Lin

Jason,
I've built 6.12-rc1 with those patch series applied. (I am also not 
reverting the other commit.) This fixes the issue - I'm able to see the 
console now. Thank you! Hopefully these can go into 6.12?
- Adam Thiede

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Jason-JH Lin (林睿祥)]

> > 
> > Hi Adam, Yassine,
> > 
> > Please try the patches below and check if they can fix the
> downgrade
> > issue:
> > [1] Fix degradation problem of alpha blending series
> > -
> > 
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=893634
> > [2] drm/mediatek: Fix XRGB format breakage for blend_modes
> unsupported
> > SoCs
> > -
> > 
> https://patchwork.kernel.org/project/linux-mediatek/patch/20241005095234.12925-1-jason-jh.lin@mediatek.com/
> > 
> > Regards,
> > Jason-JH.Lin
> 
> Jason,
> I've built 6.12-rc1 with those patch series applied. (I am also not 
> reverting the other commit.) This fixes the issue - I'm able to see
> the 
> console now. Thank you! Hopefully these can go into 6.12?
> - Adam Thiede

Yes, they will go into 6.12.



Hi Adam, Yassine,

Since the maintainer, CK, had some comments at the [2], I made some
changes for it.

Could you please test again only with this single fix patch:
[3] drm/mediatek: ovl: Fix XRGB format breakage for blend_modes
unsupported SoCs
- 
https://patchwork.kernel.org/project/linux-mediatek/patch/20241007070101.23263-2-jason-jh.lin@mediatek.com/
 
and see if it can fix your problem?

Regards,
Jason-JH.Lin

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Adam Thiede]

On 10/7/24 02:22, Jason-JH Lin (林睿祥) wrote:
>> > 
>> > Hi Adam, Yassine,
>> > 
>> > Please try the patches below and check if they can fix the
>> downgrade
>> > issue:
>> > [1] Fix degradation problem of alpha blending series
>> > -
>> > 
>> https://patchwork.kernel.org/project/linux-mediatek/list/?series=893634
>> > [2] drm/mediatek: Fix XRGB format breakage for blend_modes
>> unsupported
>> > SoCs
>> > -
>> > 
>> https://patchwork.kernel.org/project/linux-mediatek/patch/20241005095234.12925-1-jason-jh.lin@mediatek.com/
>> > 
>> > Regards,
>> > Jason-JH.Lin
>> 
>> Jason,
>> I've built 6.12-rc1 with those patch series applied. (I am also not 
>> reverting the other commit.) This fixes the issue - I'm able to see
>> the 
>> console now. Thank you! Hopefully these can go into 6.12?
>> - Adam Thiede
> 
> Yes, they will go into 6.12.
> 
> 
> 
> Hi Adam, Yassine,
> 
> Since the maintainer, CK, had some comments at the [2], I made some
> changes for it.
> 
> Could you please test again only with this single fix patch:
> [3] drm/mediatek: ovl: Fix XRGB format breakage for blend_modes
> unsupported SoCs
> -
> https://patchwork.kernel.org/project/linux-mediatek/patch/20241007070101.23263-2-jason-jh.lin@mediatek.com/
>   
> and see if it can fix your problem?
> 
> Regards,
> Jason-JH.Lin

Jason,
Just this patch on 6.12-rc1 does fix my problem too.
Thank you.

-Adam

Re: [PATCH v3 13/14] drm/mediatek: Support DRM plane alpha in OVL

[Jason-JH Lin (林睿祥)]

> > Hi Adam, Yassine,
> > 
> > Since the maintainer, CK, had some comments at the [2], I made some
> > changes for it.
> > 
> > Could you please test again only with this single fix patch:
> > [3] drm/mediatek: ovl: Fix XRGB format breakage for blend_modes
> > unsupported SoCs
> > -
> > 
> https://patchwork.kernel.org/project/linux-mediatek/patch/20241007070101.23263-2-jason-jh.lin@mediatek.com/
> >   
> > and see if it can fix your problem?
> > 
> > Regards,
> > Jason-JH.Lin
> 
> Jason,
> Just this patch on 6.12-rc1 does fix my problem too.
> Thank you.

Hi Adam,

Thanks for your verification.
I'll make these fix patches get reviewed soon.

Regards,
Jason-JH.Lin

> 
> -Adam

[PATCH v3 14/14] drm/mediatek: Support DRM plane alpha in Mixer

[Hsiao Chien Sung via B4 Relay]

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Set the plane alpha according to DRM plane property.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_ethdr.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index bf5826b7e776..36021cb8df62 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -170,8 +170,10 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
 		return;
 	}
 
-	if (state->base.fb && state->base.fb->format->has_alpha)
-		alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+	if (state->base.fb) {
+		alpha_con |= MIXER_ALPHA_AEN;
+		alpha_con |= state->base.alpha & MIXER_ALPHA;
+	}
 
 	if (state->base.fb && !state->base.fb->format->has_alpha) {
 		/*

-- 
Git-146)

Re: [PATCH v3 00/14] This series fixes the errors of MediaTek display driver found by IGT.

[Chun-Kuang Hu]

Hi Shawn:

Hsiao Chien Sung via B4 Relay
<devnull+shawn.sung.mediatek.com@kernel.org> 於 2024年6月20日 週四
上午12:38寫道：
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>

For the series, applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

> ---
> Changes in v3:
> - Modify the commit message
> - Add a patch to fix destination alpha error in OVL
> - Link to v2: https://lore.kernel.org/all/20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com
>
> ---
> Changes in v2:
> - Seperate the changes that belong to another repo (driver/soc/mediatek)
> - Move the fix patches to the front of the series
> - Link to v1: https://lore.kernel.org/r/20240616-mediatek-drm-next-v1-0-7e8f9cf785d8@mediatek.com
>
> ---
> Hsiao Chien Sung (14):
>       drm/mediatek: Add missing plane settings when async update
>       drm/mediatek: Disable 9-bit alpha in ETHDR
>       drm/mediatek: Fix XRGB setting error in OVL
>       drm/mediatek: Fix XRGB setting error in Mixer
>       drm/mediatek: Turn off the layers with zero width or height
>       drm/mediatek: Add OVL compatible name for MT8195
>       drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property
>       drm/mediatek: Add new color format MACROs in OVL
>       drm/mediatek: Set DRM mode configs accordingly
>       drm/mediatek: Support more 10bit formats in OVL
>       drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195
>       drm/mediatek: Support DRM plane alpha in OVL
>       drm/mediatek: Support DRM plane alpha in Mixer
>       drm/mediatek: Fix XRGB setting error in OVL
>
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.h         |  6 +-
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c         | 93 ++++++++++++++++++-------
>  drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c |  2 +-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c          | 24 +++++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h          |  4 ++
>  drivers/gpu/drm/mediatek/mtk_ethdr.c            | 27 +++++--
>  drivers/gpu/drm/mediatek/mtk_plane.c            |  4 +-
>  7 files changed, 126 insertions(+), 34 deletions(-)
> ---
> base-commit: 62fe4b067581d480e863191305f108bebffbc0e9
> change-id: 20240615-mediatek-drm-next-ad601b349f23
>
> Best regards,
>
> ---
> Hsiao Chien Sung (14):
>       drm/mediatek: Add missing plane settings when async update
>       drm/mediatek: Use 8-bit alpha in ETHDR
>       drm/mediatek: Fix XRGB setting error in OVL
>       drm/mediatek: Fix XRGB setting error in Mixer
>       drm/mediatek: Fix destination alpha error in OVL
>       drm/mediatek: Turn off the layers with zero width or height
>       drm/mediatek: Add OVL compatible name for MT8195
>       drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property
>       drm/mediatek: Add new color format MACROs in OVL
>       drm/mediatek: Set DRM mode configs accordingly
>       drm/mediatek: Support more 10bit formats in OVL
>       drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195
>       drm/mediatek: Support DRM plane alpha in OVL
>       drm/mediatek: Support DRM plane alpha in Mixer
>
>  drivers/gpu/drm/mediatek/mtk_ddp_comp.h         |  6 +-
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c         | 95 ++++++++++++++++++-------
>  drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c |  2 +-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c          | 24 +++++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h          |  4 ++
>  drivers/gpu/drm/mediatek/mtk_ethdr.c            | 27 +++++--
>  drivers/gpu/drm/mediatek/mtk_plane.c            |  4 +-
>  7 files changed, 127 insertions(+), 35 deletions(-)
> ---
> base-commit: 62fe4b067581d480e863191305f108bebffbc0e9
> change-id: 20240619-igt-49195e21404d
>
> Best regards,
> --
> Hsiao Chien Sung <shawn.sung@mediatek.com>
>
>

Re: [PATCH v3 00/14] This series fixes the errors of MediaTek display driver found by IGT.

[Shawn Sung (宋孝謙)]

Hi CK,

On Thu, 2024-06-20 at 22:16 +0800, Chun-Kuang Hu wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Hi Shawn:
> 
> Hsiao Chien Sung via B4 Relay
> <devnull+shawn.sung.mediatek.com@kernel.org> 於 2024年6月20日 週四
> 上午12:38寫道：
> >
> > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> 
> For the series, applied to mediatek-drm-next [1], thanks.
> 
> [1] 
> https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
> 
> Regards,
> Chun-Kuang.

Thank you for the notification.

Best regards,
Shawn

> 
> > ---
> > Changes in v3:
> > - Modify the commit message
> > - Add a patch to fix destination alpha error in OVL
> > - Link to v2: 
> https://lore.kernel.org/all/20240619-mediatek-drm-next-v2-0-abf68f46f8d2@mediatek.com
> >
> > ---
> > Changes in v2:
> > - Seperate the changes that belong to another repo
> (driver/soc/mediatek)
> > - Move the fix patches to the front of the series
> > - Link to v1: 
> https://lore.kernel.org/r/20240616-mediatek-drm-next-v1-0-7e8f9cf785d8@mediatek.com
> >
> > ---
> > Hsiao Chien Sung (14):
> >       drm/mediatek: Add missing plane settings when async update
> >       drm/mediatek: Disable 9-bit alpha in ETHDR
> >       drm/mediatek: Fix XRGB setting error in OVL
> >       drm/mediatek: Fix XRGB setting error in Mixer
> >       drm/mediatek: Turn off the layers with zero width or height
> >       drm/mediatek: Add OVL compatible name for MT8195
> >       drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property
> >       drm/mediatek: Add new color format MACROs in OVL
> >       drm/mediatek: Set DRM mode configs accordingly
> >       drm/mediatek: Support more 10bit formats in OVL
> >       drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195
> >       drm/mediatek: Support DRM plane alpha in OVL
> >       drm/mediatek: Support DRM plane alpha in Mixer
> >       drm/mediatek: Fix XRGB setting error in OVL
> >
> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h         |  6 +-
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c         | 93
> ++++++++++++++++++-------
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c |  2 +-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c          | 24 +++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h          |  4 ++
> >  drivers/gpu/drm/mediatek/mtk_ethdr.c            | 27 +++++--
> >  drivers/gpu/drm/mediatek/mtk_plane.c            |  4 +-
> >  7 files changed, 126 insertions(+), 34 deletions(-)
> > ---
> > base-commit: 62fe4b067581d480e863191305f108bebffbc0e9
> > change-id: 20240615-mediatek-drm-next-ad601b349f23
> >
> > Best regards,
> >
> > ---
> > Hsiao Chien Sung (14):
> >       drm/mediatek: Add missing plane settings when async update
> >       drm/mediatek: Use 8-bit alpha in ETHDR
> >       drm/mediatek: Fix XRGB setting error in OVL
> >       drm/mediatek: Fix XRGB setting error in Mixer
> >       drm/mediatek: Fix destination alpha error in OVL
> >       drm/mediatek: Turn off the layers with zero width or height
> >       drm/mediatek: Add OVL compatible name for MT8195
> >       drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property
> >       drm/mediatek: Add new color format MACROs in OVL
> >       drm/mediatek: Set DRM mode configs accordingly
> >       drm/mediatek: Support more 10bit formats in OVL
> >       drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195
> >       drm/mediatek: Support DRM plane alpha in OVL
> >       drm/mediatek: Support DRM plane alpha in Mixer
> >
> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h         |  6 +-
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c         | 95
> ++++++++++++++++++-------
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c |  2 +-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c          | 24 +++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h          |  4 ++
> >  drivers/gpu/drm/mediatek/mtk_ethdr.c            | 27 +++++--
> >  drivers/gpu/drm/mediatek/mtk_plane.c            |  4 +-
> >  7 files changed, 127 insertions(+), 35 deletions(-)
> > ---
> > base-commit: 62fe4b067581d480e863191305f108bebffbc0e9
> > change-id: 20240619-igt-49195e21404d
> >
> > Best regards,
> > --
> > Hsiao Chien Sung <shawn.sung@mediatek.com>
> >
> >