Re: [PATCH V2 0/3] aarch64: Enable access for FEAT_D128 registers in EL1/EL2

[Mark Rutland <mark.rutland@arm.com>]

On Mon, Jul 29, 2024 at 10:06:03AM +0530, Anshuman Khandual wrote:
> This series enables access for FEAT_D128 relevant registers in EL1/EL2 via
> setting respective bits in SCR_EL3, when their corresponding features are
> detected.
> 
> --------------------------------------------------------------
> | FEAT_D128   | ID_AA64MMFR3_EL1_D128   |  SCR_EL3_D128En    |
> | FEAT_SCTLR2 | ID_AA64MMFR3_EL1_SCTLRX |  SCR_EL3_SCTLR2En  |
> | FEAT_THE    | ID_AA64PFR1_EL1_THE     |  SCR_EL3_RCWMASKEn |
> --------------------------------------------------------------
> 
> Changes in V2:
> 
> - Moved up the patch related to SCTLR2_ELx from [PATCH 2/3] to [PATCH 1/3]
> - Updated the commit message for the above mentioned patch
> - Fixed the commit message s/D128En/SCTLR2En as the enabling bit
> - Reset SCTLR2_ELx registers so that unaware kernels do not get surprises
> 
> Changes in V1:
> 
> https://lore.kernel.org/all/20240723110630.483871-1-anshuman.khandual@arm.com/
> 
> Anshuman Khandual (3):
>   aarch64: Enable access into SCTLR2_ELx registers from EL2 and below
>   aarch64: Enable access into 128 bit system registers from EL2 and below
>   aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below

Thanks; applied.

Mark.