[PATCH V2 0/3] aarch64: Enable access for FEAT_D128 registers in EL1/EL2

[PATCH V2 0/3] aarch64: Enable access for FEAT_D128 registers in EL1/EL2

[Anshuman Khandual]

This series enables access for FEAT_D128 relevant registers in EL1/EL2 via
setting respective bits in SCR_EL3, when their corresponding features are
detected.

--------------------------------------------------------------
| FEAT_D128   | ID_AA64MMFR3_EL1_D128   |  SCR_EL3_D128En    |
| FEAT_SCTLR2 | ID_AA64MMFR3_EL1_SCTLRX |  SCR_EL3_SCTLR2En  |
| FEAT_THE    | ID_AA64PFR1_EL1_THE     |  SCR_EL3_RCWMASKEn |
--------------------------------------------------------------

Changes in V2:

- Moved up the patch related to SCTLR2_ELx from [PATCH 2/3] to [PATCH 1/3]
- Updated the commit message for the above mentioned patch
- Fixed the commit message s/D128En/SCTLR2En as the enabling bit
- Reset SCTLR2_ELx registers so that unaware kernels do not get surprises

Changes in V1:

https://lore.kernel.org/all/20240723110630.483871-1-anshuman.khandual@arm.com/

Anshuman Khandual (3):
  aarch64: Enable access into SCTLR2_ELx registers from EL2 and below
  aarch64: Enable access into 128 bit system registers from EL2 and below
  aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below

 arch/aarch64/include/asm/cpu.h | 11 ++++++++++-
 arch/aarch64/init.c            | 12 ++++++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)

-- 
2.25.1

[PATCH V2 1/3] aarch64: Enable access into SCTLR2_ELx registers from EL2 and below

[Anshuman Khandual]

FEAT_SCTLR2 adds SCTLR2_EL1 and SCTLR2_EL2 system registers. But access
into these register from EL2 and below exception levels, will trap into EL3
unless SCR_EL3.SCTLR2En is set.

Enable access to SCTLR2_ELx registers when they are implemented. Given that
SCTLR2_ELx registers reset to UNKNOWN values - when the highest implemented
exception level is not ELx, this resets SCTLR2_ELx registers. Otherwise any
kernel which is not aware of these SCTLR2_ELx registers, will be subject to
arbitrary behaviour as a result of the SCTLR2_ELx bits which it will not
have configured.

Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/aarch64/include/asm/cpu.h | 7 ++++++-
 arch/aarch64/init.c            | 6 ++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 846b89f..85e735b 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -20,6 +20,9 @@
 #define TCR2_EL2		s3_4_c2_c0_3
 #define TCR2_EL1		s3_0_c2_c0_3
 
+#define SCTLR2_EL1		s3_0_c1_c0_3
+#define SCTLR2_EL2		s3_4_c1_c0_3
+
 /*
  * RES1 bit definitions definitions as of ARM DDI 0487G.b
  *
@@ -56,6 +59,7 @@
 #define SCR_EL3_HXEn			BIT(38)
 #define SCR_EL3_EnTP2			BIT(41)
 #define SCR_EL3_TCR2EN			BIT(43)
+#define SCR_EL3_SCTLR2En		BIT(44)
 #define SCR_EL3_PIEN			BIT(45)
 
 #define HCR_EL2_RES1			BIT(1)
@@ -80,7 +84,8 @@
 
 #define ID_AA64MMFR1_EL1_HCX		BITS(43, 40)
 
-#define ID_AA64MMFR3_EL1_TCRX		BITS(4, 0)
+#define ID_AA64MMFR3_EL1_TCRX		BITS(3, 0)
+#define ID_AA64MMFR3_EL1_SCTLRX		BITS(7, 4)
 #define ID_AA64MMFR3_EL1_S1PIE		BITS(11, 8)
 #define ID_AA64MMFR3_EL1_S2PIE		BITS(15, 12)
 #define ID_AA64MMFR3_EL1_S1POE		BITS(19, 16)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index 37cb45f..fc0d2e3 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -89,6 +89,12 @@ void cpu_init_el3(void)
 	if (!kernel_is_32bit())
 		scr |= SCR_EL3_RW;
 
+	if (mrs_field(ID_AA64MMFR3_EL1, SCTLRX)) {
+		scr |= SCR_EL3_SCTLR2En;
+		msr(SCTLR2_EL2, 0);
+		msr(SCTLR2_EL1, 0);
+	}
+
 	msr(SCR_EL3, scr);
 
 	msr(CPTR_EL3, cptr);
-- 
2.25.1

[PATCH V2 2/3] aarch64: Enable access into 128 bit system registers from EL2 and below

[Anshuman Khandual]

FEAT_D128 adds 128 bit system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1,
TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and
RCWSMASK_EL1. But access into these register from EL2 and below trap to EL3
unless SCR_EL3.D128En is set.

Enable access to 128 bit registers when they are implemented.

Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/aarch64/include/asm/cpu.h | 2 ++
 arch/aarch64/init.c            | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 85e735b..57c9cf2 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -61,6 +61,7 @@
 #define SCR_EL3_TCR2EN			BIT(43)
 #define SCR_EL3_SCTLR2En		BIT(44)
 #define SCR_EL3_PIEN			BIT(45)
+#define SCR_EL3_D128En			BIT(47)
 
 #define HCR_EL2_RES1			BIT(1)
 
@@ -90,6 +91,7 @@
 #define ID_AA64MMFR3_EL1_S2PIE		BITS(15, 12)
 #define ID_AA64MMFR3_EL1_S1POE		BITS(19, 16)
 #define ID_AA64MMFR3_EL1_S2POE		BITS(23, 20)
+#define ID_AA64MMFR3_EL1_D128		BITS(35, 32)
 
 #define ID_AA64PFR1_EL1_MTE		BITS(11, 8)
 #define ID_AA64PFR1_EL1_SME		BITS(27, 24)
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index fc0d2e3..afe4398 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -95,6 +95,9 @@ void cpu_init_el3(void)
 		msr(SCTLR2_EL1, 0);
 	}
 
+	if (mrs_field(ID_AA64MMFR3_EL1, D128))
+		scr |= SCR_EL3_D128En;
+
 	msr(SCR_EL3, scr);
 
 	msr(CPTR_EL3, cptr);
-- 
2.25.1

[PATCH V2 3/3] aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below

[Anshuman Khandual]

FEAT_THE adds RCW[S]MASK_EL1 system registers. But access into these system
registers from EL2 and below trap to EL3 unless SCR_EL3.RCWMASKEn is set.

Enable access to RCW[S]MASK_EL1 registers when they are implemented.

Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/aarch64/include/asm/cpu.h | 2 ++
 arch/aarch64/init.c            | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 57c9cf2..a5744e1 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -58,6 +58,7 @@
 #define SCR_EL3_TME			BIT(34)
 #define SCR_EL3_HXEn			BIT(38)
 #define SCR_EL3_EnTP2			BIT(41)
+#define SCR_EL3_RCWMASKEn		BIT(42)
 #define SCR_EL3_TCR2EN			BIT(43)
 #define SCR_EL3_SCTLR2En		BIT(44)
 #define SCR_EL3_PIEN			BIT(45)
@@ -95,6 +96,7 @@
 
 #define ID_AA64PFR1_EL1_MTE		BITS(11, 8)
 #define ID_AA64PFR1_EL1_SME		BITS(27, 24)
+#define ID_AA64PFR1_EL1_THE		BITS(51, 48)
 #define ID_AA64PFR0_EL1_SVE		BITS(35, 32)
 
 #define ID_AA64SMFR0_EL1		s3_0_c0_c4_5
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index afe4398..c9fc7f1 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -98,6 +98,9 @@ void cpu_init_el3(void)
 	if (mrs_field(ID_AA64MMFR3_EL1, D128))
 		scr |= SCR_EL3_D128En;
 
+	if (mrs_field(ID_AA64PFR1_EL1, THE))
+		scr |= SCR_EL3_RCWMASKEn;
+
 	msr(SCR_EL3, scr);
 
 	msr(CPTR_EL3, cptr);
-- 
2.25.1

Re: [PATCH V2 0/3] aarch64: Enable access for FEAT_D128 registers in EL1/EL2

[Anshuman Khandual]

On 7/29/24 10:06, Anshuman Khandual wrote:
> This series enables access for FEAT_D128 relevant registers in EL1/EL2 via
> setting respective bits in SCR_EL3, when their corresponding features are
> detected.
> 
> --------------------------------------------------------------
> | FEAT_D128   | ID_AA64MMFR3_EL1_D128   |  SCR_EL3_D128En    |
> | FEAT_SCTLR2 | ID_AA64MMFR3_EL1_SCTLRX |  SCR_EL3_SCTLR2En  |
> | FEAT_THE    | ID_AA64PFR1_EL1_THE     |  SCR_EL3_RCWMASKEn |
> --------------------------------------------------------------
> 
> Changes in V2:
> 
> - Moved up the patch related to SCTLR2_ELx from [PATCH 2/3] to [PATCH 1/3]
> - Updated the commit message for the above mentioned patch
> - Fixed the commit message s/D128En/SCTLR2En as the enabling bit
> - Reset SCTLR2_ELx registers so that unaware kernels do not get surprises
> 
> Changes in V1:
> 
> https://lore.kernel.org/all/20240723110630.483871-1-anshuman.khandual@arm.com/
> 
> Anshuman Khandual (3):
>   aarch64: Enable access into SCTLR2_ELx registers from EL2 and below
>   aarch64: Enable access into 128 bit system registers from EL2 and below
>   aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below
> 
>  arch/aarch64/include/asm/cpu.h | 11 ++++++++++-
>  arch/aarch64/init.c            | 12 ++++++++++++
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 

Oops, forgot to change PATCH as boot-wrapper for differentiation once again.

Re: [PATCH V2 0/3] aarch64: Enable access for FEAT_D128 registers in EL1/EL2

[Mark Rutland]

On Mon, Jul 29, 2024 at 10:06:03AM +0530, Anshuman Khandual wrote:
> This series enables access for FEAT_D128 relevant registers in EL1/EL2 via
> setting respective bits in SCR_EL3, when their corresponding features are
> detected.
> 
> --------------------------------------------------------------
> | FEAT_D128   | ID_AA64MMFR3_EL1_D128   |  SCR_EL3_D128En    |
> | FEAT_SCTLR2 | ID_AA64MMFR3_EL1_SCTLRX |  SCR_EL3_SCTLR2En  |
> | FEAT_THE    | ID_AA64PFR1_EL1_THE     |  SCR_EL3_RCWMASKEn |
> --------------------------------------------------------------
> 
> Changes in V2:
> 
> - Moved up the patch related to SCTLR2_ELx from [PATCH 2/3] to [PATCH 1/3]
> - Updated the commit message for the above mentioned patch
> - Fixed the commit message s/D128En/SCTLR2En as the enabling bit
> - Reset SCTLR2_ELx registers so that unaware kernels do not get surprises
> 
> Changes in V1:
> 
> https://lore.kernel.org/all/20240723110630.483871-1-anshuman.khandual@arm.com/
> 
> Anshuman Khandual (3):
>   aarch64: Enable access into SCTLR2_ELx registers from EL2 and below
>   aarch64: Enable access into 128 bit system registers from EL2 and below
>   aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below

Thanks; applied.

Mark.