* [RFC PATCH 01/13] arm64: preempt: Simplify and optimize __preempt_count_dec_and_test()
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 02/13] arm64: preempt: Treat should_resched() as unlikely Mark Rutland
` (11 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
In arm64's __preempt_count_dec_and_test(), the final conditional load of
'ti->preempt_count' is always executed in the common case. The
conditional load leads to unfortunate code generation for
preempt_enable[_notrace](), and it would be better to unconditionally
load 'ti->preempt_count', as described below.
On arm64, struct thread_info contains the following union:
| union {
| u64 preempt_count;
| struct {
| u32 count;
| u32 need_resched;
| } preempt;
| };
Note: 'need_resched' is encoded so that '0' means a reschedule is
needed, and '1' means a reschedule is NOT needed.
The core logic of __preempt_count_dec_and_test() is:
| static inline bool __preempt_count_dec_and_test(void)
| {
| struct thread_info *ti = current_thread_info();
| u64 pc = READ_ONCE(ti->preempt_count);
|
| WRITE_ONCE(ti->preempt.count, --pc);
|
| return !pc || !READ_ONCE(ti->preempt_count);
| }
The '!pc' condition can only be true when both:
* The initial value of 'need_resched' was 0, meaning that a reschedule
is needed. This should be rare.
* The initial value of 'count' was exactly 1. This cannot be true for a
nested preempt_disable() ... preempt_enable() sequence.
Hence in common cases, '!pc' will be false, and it's necessary to
execute the final READ_ONCE(ti->preempt_count).
This results in a conditional branch in the common case, as can be seen
when __preempt_count_dec_and_test() is outlined:
| <outline___preempt_count_dec_and_test>:
| mrs x2, sp_el0
| ldr x1, [x2, #8]
| mov w0, #0x1
| sub x1, x1, #0x1
| str w1, [x2, #8]
| cbz x1, 1f
| ldr x0, [x2, #8]
| cmp x0, #0x0
| cset w0, eq // eq = none
| 1: ret
It would be better to avoid the special case for 'pc == 0', and to
always load 'ti->preempt_count' after decrementing 'ti->preempt.count'.
For the common cases this will remove a conditional branch. For the rare
cases where preemption is needed initially, this only adds a single
load, whose cost should be dominated by other factors.
Remove the special case for 'pc == 0', and always load the combined
'ti->preempt_count' after decrementing 'ti->preempt.count'.
The removal of the conditional branch helps with code generation, as the
compiler can more easily move a dependent slow path out-of-line, as
demonstrated with the following compiled with GCC 15.2.0:
| void outline_preempt_enable_notrace(void)
| {
| preempt_enable_notrace();
| }
Before this patch:
| <outline_preempt_enable_notrace>:
| mrs x1, sp_el0
| ldr x0, [x1, #8]
| sub x0, x0, #0x1
| str w0, [x1, #8]
| cbz x0, 1f
| ldr x0, [x1, #8]
| cbnz x0, 2f
| 1: paciasp
| stp x29, x30, [sp, #-16]!
| mov x29, sp
| bl preempt_schedule_notrace
| ldp x29, x30, [sp], #16
| autiasp
| ret
| 2: ret
After this patch:
| <outline_preempt_enable_notrace>:
| mrs x0, sp_el0
| ldr w1, [x0, #8]
| sub w1, w1, #0x1
| str w1, [x0, #8]
| ldr x0, [x0, #8]
| cbz x0, 1f
| ret
| 1: paciasp
| stp x29, x30, [sp, #-16]!
| mov x29, sp
| bl preempt_schedule_notrace
| ldp x29, x30, [sp], #16
| autiasp
| ret
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/preempt.h | 29 +++++++++++------------------
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/include/asm/preempt.h b/arch/arm64/include/asm/preempt.h
index 932ea4b620428..ca2ad1a8db095 100644
--- a/arch/arm64/include/asm/preempt.h
+++ b/arch/arm64/include/asm/preempt.h
@@ -55,30 +55,23 @@ static inline void __preempt_count_sub(int val)
WRITE_ONCE(current_thread_info()->preempt.count, pc);
}
-static inline bool __preempt_count_dec_and_test(void)
-{
- struct thread_info *ti = current_thread_info();
- u64 pc = READ_ONCE(ti->preempt_count);
-
- /* Update only the count field, leaving need_resched unchanged */
- WRITE_ONCE(ti->preempt.count, --pc);
-
- /*
- * If we wrote back all zeroes, then we're preemptible and in
- * need of a reschedule. Otherwise, we need to reload the
- * preempt_count in case the need_resched flag was cleared by an
- * interrupt occurring between the non-atomic READ_ONCE/WRITE_ONCE
- * pair.
- */
- return !pc || !READ_ONCE(ti->preempt_count);
-}
-
static inline bool should_resched(int preempt_offset)
{
u64 pc = READ_ONCE(current_thread_info()->preempt_count);
return pc == preempt_offset;
}
+static inline bool __preempt_count_dec_and_test(void)
+{
+ /*
+ * We must load the combined 'prempt_count' after decrementing
+ * 'preempt.count' as an interrupt could modify 'need_resched' before
+ * __preempt_count_sub() writes back to 'preempt.count'.
+ */
+ __preempt_count_sub(1);
+ return should_resched(0);
+}
+
#ifdef CONFIG_PREEMPTION
void preempt_schedule(void);
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 02/13] arm64: preempt: Treat should_resched() as unlikely
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 01/13] arm64: preempt: Simplify and optimize __preempt_count_dec_and_test() Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 03/13] arm64: ptrace: Always inline pt_regs_[read,write}_reg() Mark Rutland
` (10 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
The arm64 implementation of should_resched() doesn't treat the need to
resched as unlikely, while all other implementations do, e.g.
* asm-generic since:
bdb43806589096ac ("sched: Extract the basic add/sub preempt_count modifiers")
* x86 since:
c2daa3bed53a8117 ("sched, x86: Provide a per-cpu preempt_count implementation")
* s390 since:
c360192bf4a8dc72 ("s390/preempt: move preempt_count to the lowcore")
Do the same for arm64.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/preempt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/preempt.h b/arch/arm64/include/asm/preempt.h
index ca2ad1a8db095..3ef24ab8f3399 100644
--- a/arch/arm64/include/asm/preempt.h
+++ b/arch/arm64/include/asm/preempt.h
@@ -58,7 +58,7 @@ static inline void __preempt_count_sub(int val)
static inline bool should_resched(int preempt_offset)
{
u64 pc = READ_ONCE(current_thread_info()->preempt_count);
- return pc == preempt_offset;
+ return unlikely(pc == preempt_offset);
}
static inline bool __preempt_count_dec_and_test(void)
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 03/13] arm64: ptrace: Always inline pt_regs_[read,write}_reg()
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 01/13] arm64: preempt: Simplify and optimize __preempt_count_dec_and_test() Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 02/13] arm64: preempt: Treat should_resched() as unlikely Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 04/13] arm64: percpu: Factor out percpu offset asm Mark Rutland
` (9 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
In subsequent patches we'll want to use pt_regs_read_reg() and
pt_regs_write_reg() in noinstr code.
To ensure noinstr safety, both functions must be inlined into their
caller. As both functions are marked as 'inline' rather than
'__always_inline', that's not strictly guaranteed, and the compiler is
permitted to generate out-of-line copies.
Mark both functions as '__always_inline' to ensure this.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/ptrace.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index 39582511ad72f..a1aa668aad50e 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -268,7 +268,8 @@ static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset)
* Read a register given an architectural register index r.
* This handles the common case where 31 means XZR, not SP.
*/
-static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r)
+static __always_inline unsigned long
+pt_regs_read_reg(const struct pt_regs *regs, int r)
{
return (r == 31) ? 0 : regs->regs[r];
}
@@ -277,8 +278,8 @@ static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r)
* Write a register given an architectural register index r.
* This handles the common case where 31 means XZR, not SP.
*/
-static inline void pt_regs_write_reg(struct pt_regs *regs, int r,
- unsigned long val)
+static __always_inline void
+pt_regs_write_reg(struct pt_regs *regs, int r, unsigned long val)
{
if (r != 31)
regs->regs[r] = val;
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 04/13] arm64: percpu: Factor out percpu offset asm
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (2 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 03/13] arm64: ptrace: Always inline pt_regs_[read,write}_reg() Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 05/13] arm64: gpr-num: Add wxN aliases for wN registers Mark Rutland
` (8 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Depending on whether the kernel runs at EL1 or EL2, the percpu offset is
stored in either TPIDR_EL1 or TPIDR_EL2, and __kern_my_cpu_offset() uses
an ALTERNATIVE() sequence to read the relevant TPIDR_ELx.
In subsequent patches we'll need to read the percpu offset in other
assembly sequences. Factor the ALTERNATIVE sequence out of
__kern_my_cpu_offset() into a new __KERN_ASM_CPU_OFFSET() macro so that
we can share the code sequence.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/percpu.h | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index b57b2bb009677..98823c97d534c 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -29,6 +29,11 @@ static inline unsigned long __hyp_my_cpu_offset(void)
return read_sysreg(tpidr_el2);
}
+#define __KERN_ASM_CPU_OFFSET(dst) \
+ ALTERNATIVE("mrs " dst ", tpidr_el1", \
+ "mrs " dst ", tpidr_el2", \
+ ARM64_HAS_VIRT_HOST_EXTN)
+
static inline unsigned long __kern_my_cpu_offset(void)
{
unsigned long off;
@@ -37,11 +42,11 @@ static inline unsigned long __kern_my_cpu_offset(void)
* We want to allow caching the value, so avoid using volatile and
* instead use a fake stack read to hazard against barrier().
*/
- asm(ALTERNATIVE("mrs %0, tpidr_el1",
- "mrs %0, tpidr_el2",
- ARM64_HAS_VIRT_HOST_EXTN)
- : "=r" (off) :
- "Q" (*(const unsigned long *)current_stack_pointer));
+ asm(
+ __KERN_ASM_CPU_OFFSET("%0")
+ : "=r" (off)
+ : "Q" (*(const unsigned long *)current_stack_pointer)
+ );
return off;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 05/13] arm64: gpr-num: Add wxN aliases for wN registers
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (3 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 04/13] arm64: percpu: Factor out percpu offset asm Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Mark Rutland
` (7 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Some A64 instructions require a W register name for specific register
arguments, and will not accept an X register name. For example:
STRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
This is painful when writing macros for inline assembly, especially
where a single register is used as both an X register and a W register.
We solve this for plain assembly by adding a wxN alias for each xN
register in commit:
4c4dcd3541f83d21 ("arm64: assembler: introduce wxN aliases for wN registers")
Add the same facility for inline assembly, with a new
__DEFINE_ASM_GPR_ALIASES macro.
As with the other macros in gpr-num.h, different escaping is necessary
for inline vs non-inline assembly, so we can't share a single definition
that we stringify().
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/gpr-num.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/include/asm/gpr-num.h b/arch/arm64/include/asm/gpr-num.h
index a114e4f8209b0..240cd25d55c5a 100644
--- a/arch/arm64/include/asm/gpr-num.h
+++ b/arch/arm64/include/asm/gpr-num.h
@@ -21,6 +21,11 @@
" .equ .L__gpr_num_xzr, 31\n" \
" .equ .L__gpr_num_wzr, 31\n"
+#define __DEFINE_ASM_GPR_ALIASES \
+" .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
+" wx\\n .req w\\n\n" \
+" .endr\n"
+
#endif /* __ASSEMBLER__ */
#endif /* __ASM_GPR_NUM_H */
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (4 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 05/13] arm64: gpr-num: Add wxN aliases for wN registers Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 14:19 ` Peter Zijlstra
2026-07-28 16:51 ` Heiko Carstens
2026-07-28 12:38 ` [RFC PATCH 07/13] arm64: percpu: Implement preemptible read/write ops Mark Rutland
` (6 subsequent siblings)
12 siblings, 2 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Currently arm64's this_cpu_*() ops transiently disable preemption in
order to guarantee that the address generation and memory access(es)
occur on the same CPU.
Transiently disabling preemption can be expensive. When re-enabling
preemption it is necessary to make a conditional function call to
preempt_schedule[_notrace]() in order to handle the rare case that the
task needs to be rescheduled. The potential function call has a number
of negative effects on code generation (e.g. due to the need to create a
stack frame and spill registers), and the conditionality can result in
poor code generation and/or poor branch prediction.
This patch adds infrastructure for a scheme where this_cpu_*() ops do
not need to transiently disable preemption, avoiding the negative
impacts described above.
Each operation registers a critical section during which the exception
return code will adjust the offset and addresses if preemption occurs
mid-sequence. The critical section is registered/unregistered with a
small prologue and epilogue which encodes three distinct GPRRs (<pcp>,
<off>, <addr>) into a new thread_info::pcp_gprs field:
// Prologue. Enable fixups for <off> and <addr>.
mrs <tsk>, sp_el0
mov <tmp>, #__VAL_PCPU_GPRS(<pcp>, <off>, <addr>)
strh <tmp>, [<tsk>, #TSK_TI_PCPU_GPRS]
// Generate cpu-specific address
mrs <off>, TPIDR_ELx
add <addr>, <pcp>, <off>
// Perform access sequence
ldr <val>, [<addr>]
// Epilogue. Disable fixups
strh wzr, [<tsk>, #TSK_TI_PCPU_GPRS]
If an exception is taken from within the critical section, the exception
return code will adjust <off> to be the current CPU's offset, and will
adjust <addr> to be (<pcp> + <off>). Distinct registers are used for
<pcp>, <off>, and <addr>, so that the fixup can be applied safely at any
point during the critical section.
To ensure that this_cpu_*() operations within exception handlers work
correctly and do not corrupt state, thread_info::pcpu_gprs is saved
into a new pt_regs::pcpu_gprs field upon exception entry, and restored
upon exception return.
Looking at a simple this_cpu_operation:
| void outline_this_cpu_add_u64(u64 __percpu *p, u64 v)
| {
| this_cpu_add(*p, v);
| }
Atop v7.2-rc4, with GCC 15.2.0 and defconfig, this is compiled as:
| <outline_this_cpu_add_u64>:
| paciasp
| stp x29, x30, [sp, #-16]!
| mrs x2, sp_el0
| mov x29, sp
| ldr w3, [x2, #8]
| add w3, w3, #0x1
| str w3, [x2, #8]
| mrs x3, tpidr_el1
| add x0, x0, x3
| 1: ldxr x5, [x0]
| add x5, x5, x1
| stxr w4, x5, [x0]
| cbnz w4, 1b
| ldr x0, [x2, #8]
| sub x0, x0, #0x1
| str w0, [x2, #8]
| cbz x0, 2f
| ldr x0, [x2, #8]
| cbnz x0, 3f
| 2: bl preempt_schedule_notrace
| 3: ldp x29, x30, [sp], #16
| autiasp
| ret
With the scheme added in this patch, this can be compiled as:
| <outline_this_cpu_add_u64>:
| mrs x2, sp_el0
| mov x4, #0xc80
| strh w4, [x2, #20]
| mrs x4, tpidr_el1
| add x3, x0, x4
| 1: ldxr x6, [x3]
| add x6, x6, x1
| stxr w5, x6, [x3]
| cbnz w5, 1b
| strh wzr, [x2, #20]
| ret
TODO: Save/restore the PCPU GPRs in __sdei_asm_handler(). This will
require some mechanical rework to the __sdei_asm_handler() assembly.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/percpu.h | 43 ++++++++++++++++++++++++++++
arch/arm64/include/asm/ptrace.h | 5 ++++
arch/arm64/include/asm/thread_info.h | 1 +
arch/arm64/kernel/asm-offsets.c | 2 ++
arch/arm64/kernel/entry-common.c | 38 ++++++++++++++++++++++++
arch/arm64/kernel/entry.S | 13 +++++++++
6 files changed, 102 insertions(+)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 98823c97d534c..0871dcc41d759 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -5,10 +5,12 @@
#ifndef __ASM_PERCPU_H
#define __ASM_PERCPU_H
+#include <linux/bits.h>
#include <linux/preempt.h>
#include <asm/alternative.h>
#include <asm/cmpxchg.h>
+#include <asm/gpr-num.h>
#include <asm/stack_pointer.h>
#include <asm/sysreg.h>
@@ -51,6 +53,47 @@ static inline unsigned long __kern_my_cpu_offset(void)
return off;
}
+#define PCPU_GPR_PCP GENMASK(4, 0)
+#define PCPU_GPR_OFF GENMASK(9, 5)
+#define PCPU_GPR_ADDR GENMASK(14, 10)
+
+#define __VAL_PCPU_GPRS(pcp, off, addr) \
+ "(" \
+ "(.L__gpr_num_" pcp " << 0) | " \
+ "(.L__gpr_num_" off " << 5) | " \
+ "(.L__gpr_num_" addr " << 10)" \
+ ")"
+
+#define ____PCPU_GPRS_BEGIN(gprs, pcp, off, addr) \
+ __DEFINE_ASM_GPR_NUMS \
+ __DEFINE_ASM_GPR_ALIASES \
+ " mov w" off ", #" __VAL_PCPU_GPRS(pcp, off, addr) "\n" \
+ " strh w" off ", " gprs "\n" \
+ __KERN_ASM_CPU_OFFSET(off) "\n"
+
+/*
+ * Begin a PCPU GPR critical section which requires <addr> (and <off>).
+ */
+#define __PCPU_GPRS_BEGIN(gprs, pcp, off, addr) \
+ ____PCPU_GPRS_BEGIN(gprs, pcp, off, addr) \
+ " add " addr ", " pcp ", " off "\n" \
+
+/*
+ * Begin a PCPU GPR critical section which only requires <off> and does not
+ * require <addr>.
+ *
+ * This is only for operations that can use register-offset addressing,
+ * e.g. STR <Xt>, [<Xn>, <Xm].
+ */
+#define __PCPU_GPRS_BEGIN_OFFSET(gprs, pcp, off) \
+ ____PCPU_GPRS_BEGIN(gprs, pcp, off, "xzr") \
+
+/*
+ * End a PCU GPR critical section.
+ */
+#define __PCPU_GPRS_END(gprs) \
+ " strh wzr, " gprs "\n"
+
#ifdef __KVM_NVHE_HYPERVISOR__
#define __my_cpu_offset __hyp_my_cpu_offset()
#else
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index a1aa668aad50e..962013df20c7a 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -169,6 +169,11 @@ struct pt_regs {
u64 sdei_ttbr1;
struct frame_record_meta stackframe;
+
+ u16 pcpu_gprs;
+ u16 __unused1;
+ u32 __unused2;
+ u64 __unused3;
};
/* For correct stack alignment, pt_regs has to be a multiple of 16 bytes. */
diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h
index 5d7fe3e153c85..6db5fa72211d1 100644
--- a/arch/arm64/include/asm/thread_info.h
+++ b/arch/arm64/include/asm/thread_info.h
@@ -46,6 +46,7 @@ struct thread_info {
u64 mpam_partid_pmg;
#endif
u32 cpu;
+ u16 pcpu_gprs;
};
#define thread_saved_pc(tsk) \
diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
index b6367ff3a49ca..bde09e9fe3e64 100644
--- a/arch/arm64/kernel/asm-offsets.c
+++ b/arch/arm64/kernel/asm-offsets.c
@@ -36,6 +36,7 @@ int main(void)
DEFINE(TSK_TI_SCS_BASE, offsetof(struct task_struct, thread_info.scs_base));
DEFINE(TSK_TI_SCS_SP, offsetof(struct task_struct, thread_info.scs_sp));
#endif
+ DEFINE(TSK_TI_PCPU_GPRS, offsetof(struct task_struct, thread_info.pcpu_gprs));
DEFINE(TSK_STACK, offsetof(struct task_struct, stack));
#ifdef CONFIG_STACKPROTECTOR
DEFINE(TSK_STACK_CANARY, offsetof(struct task_struct, stack_canary));
@@ -78,6 +79,7 @@ int main(void)
DEFINE(S_PMR, offsetof(struct pt_regs, pmr));
DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));
DEFINE(S_STACKFRAME_TYPE, offsetof(struct pt_regs, stackframe.type));
+ DEFINE(S_PCPU_GPRS, offsetof(struct pt_regs, pcpu_gprs));
DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
BLANK();
#ifdef CONFIG_DYNAMIC_FTRACE_WITH_ARGS
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index ceb4eb11232a6..5bba1359280c3 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -25,12 +25,49 @@
#include <asm/irq_regs.h>
#include <asm/kprobes.h>
#include <asm/mmu.h>
+#include <asm/percpu.h>
#include <asm/processor.h>
#include <asm/sdei.h>
#include <asm/stacktrace.h>
#include <asm/sysreg.h>
#include <asm/system_misc.h>
+/*
+ * Where the context being returned to had an active percpu GPR critical
+ * section, ensure that the offset and address GPRs are updated to match the
+ * current CPU.
+ *
+ * For simplicity we always update the GPRs when a critical section is active
+ * and preemption was *possible*, regardless of whether preemption actually
+ * occurred. Where preemption did not occur, the updates are redundant but not
+ * harmful.
+ */
+static __always_inline void irqentry_exit_pcpu_adjust(struct pt_regs *regs)
+{
+ int reg_pcp, reg_off, reg_addr;
+ unsigned long pcp, off, addr;
+ u16 gprs = regs->pcpu_gprs;
+
+ /*
+ * Zero means no active PCPU GPRs. As the PCPU GPRs must be distinct,
+ * a PCPU critical section cannot possibly use {x0,x0,x0}.
+ */
+ if (likely(!gprs))
+ return;
+
+ reg_pcp = FIELD_GET(PCPU_GPR_PCP, gprs);
+ reg_off = FIELD_GET(PCPU_GPR_OFF, gprs);
+ reg_addr = FIELD_GET(PCPU_GPR_ADDR, gprs);
+
+ pcp = pt_regs_read_reg(regs, reg_pcp);
+
+ off = __kern_my_cpu_offset();
+ pt_regs_write_reg(regs, reg_off, off);
+
+ addr = pcp + off;
+ pt_regs_write_reg(regs, reg_addr, addr);
+}
+
/*
* Handle IRQ/context state management when entering from kernel mode.
* Before this function is called it is not safe to call regular kernel code,
@@ -58,6 +95,7 @@ static void noinstr arm64_exit_to_kernel_mode(struct pt_regs *regs,
local_irq_disable();
irqentry_exit_to_kernel_mode_preempt(regs, state);
local_daif_mask();
+ irqentry_exit_pcpu_adjust(regs);
mte_check_tfsr_exit();
irqentry_exit_to_kernel_mode_after_preempt(regs, state);
}
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index e0db14e9c843a..d26648cd7f280 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -194,6 +194,17 @@ alternative_cb_end
#endif
.endm
+ .macro pcpu_gprs_entry, tsk, regs, tmp
+ ldrh w\tmp, [\tsk, #TSK_TI_PCPU_GPRS]
+ strh w\tmp, [\regs, #S_PCPU_GPRS]
+ strh wzr, [\tsk, #TSK_TI_PCPU_GPRS]
+ .endm
+
+ .macro pcpu_gprs_exit, tsk, regs, tmp
+ ldrh w\tmp, [\regs, #S_PCPU_GPRS]
+ strh w\tmp, [\tsk, #TSK_TI_PCPU_GPRS]
+ .endm
+
.macro kernel_entry, el, regsize = 64
.if \el == 0
alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT
@@ -277,6 +288,7 @@ alternative_else_nop_endif
.else
add x21, sp, #PT_REGS_SIZE
get_current_task tsk
+ pcpu_gprs_entry tsk, sp, x0
.endif /* \el == 0 */
mrs x22, elr_el1
mrs x23, spsr_el1
@@ -335,6 +347,7 @@ alternative_else_nop_endif
.macro kernel_exit, el
.if \el != 0
disable_daif
+ pcpu_gprs_exit tsk, sp, x0
.endif
#ifdef CONFIG_ARM64_PSEUDO_NMI
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
2026-07-28 12:38 ` [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Mark Rutland
@ 2026-07-28 14:19 ` Peter Zijlstra
2026-07-28 14:30 ` Peter Zijlstra
2026-07-28 15:53 ` Mark Rutland
2026-07-28 16:51 ` Heiko Carstens
1 sibling, 2 replies; 22+ messages in thread
From: Peter Zijlstra @ 2026-07-28 14:19 UTC (permalink / raw)
To: Mark Rutland
Cc: vladimir.murzin, catalin.marinas, hca, linux-kernel, ruanjinjie,
yang, maz, will, ardb, linux-arm-kernel
On Tue, Jul 28, 2026 at 01:38:52PM +0100, Mark Rutland wrote:
> With the scheme added in this patch, this can be compiled as:
>
> | <outline_this_cpu_add_u64>:
> | mrs x2, sp_el0
> | mov x4, #0xc80
Perhaps add a comment to that like:
| mov x4, #0xc80 # {x0, x4, x3}
to make the literal less magical?
> | strh w4, [x2, #20]
Anyway, interrupt can hit here, at which point it will:
x4 := this_cpu_offset
x3 := x0 + x4
> | mrs x4, tpidr_el1
> | add x3, x0, x4
Which it then recomputes, and so is harmless.
> | 1: ldxr x6, [x3]
> | add x6, x6, x1
> | stxr w5, x6, [x3]
IIRC any interrupt in between LL/SC will cause the stxr to fail anyway,
irrespective of the fixup, so goto 1b we go.
> | cbnz w5, 1b
If we get here and interrupts happens, we recompute pointlessly, no harm
done.
Anyway, per this sequence there is no point in ever doing the fixup. So
perhaps give a better example?
> | strh wzr, [x2, #20]
> | ret
>
> TODO: Save/restore the PCPU GPRs in __sdei_asm_handler(). This will
> require some mechanical rework to the __sdei_asm_handler() assembly.
>
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> @@ -51,6 +53,47 @@ static inline unsigned long __kern_my_cpu_offset(void)
> return off;
> }
>
> +#define PCPU_GPR_PCP GENMASK(4, 0)
> +#define PCPU_GPR_OFF GENMASK(9, 5)
> +#define PCPU_GPR_ADDR GENMASK(14, 10)
I hate those macros, I can never remember what they all do. Now, esp.
since you then not use them here:
> +#define __VAL_PCPU_GPRS(pcp, off, addr) \
> + "(" \
> + "(.L__gpr_num_" pcp " << 0) | " \
> + "(.L__gpr_num_" off " << 5) | " \
> + "(.L__gpr_num_" addr " << 10)" \
> + ")"
... continue comment at irqentry_exit_pcpu_adjust().
> +#define ____PCPU_GPRS_BEGIN(gprs, pcp, off, addr) \
> + __DEFINE_ASM_GPR_NUMS \
> + __DEFINE_ASM_GPR_ALIASES \
> + " mov w" off ", #" __VAL_PCPU_GPRS(pcp, off, addr) "\n" \
> + " strh w" off ", " gprs "\n" \
> + __KERN_ASM_CPU_OFFSET(off) "\n"
Can this macro also generate a readable comment for those few of us
building the .i file ?
> +/*
> + * Where the context being returned to had an active percpu GPR critical
> + * section, ensure that the offset and address GPRs are updated to match the
> + * current CPU.
> + *
> + * For simplicity we always update the GPRs when a critical section is active
> + * and preemption was *possible*, regardless of whether preemption actually
> + * occurred. Where preemption did not occur, the updates are redundant but not
> + * harmful.
> + */
> +static __always_inline void irqentry_exit_pcpu_adjust(struct pt_regs *regs)
> +{
> + int reg_pcp, reg_off, reg_addr;
> + unsigned long pcp, off, addr;
> + u16 gprs = regs->pcpu_gprs;
> +
> + /*
> + * Zero means no active PCPU GPRs. As the PCPU GPRs must be distinct,
> + * a PCPU critical section cannot possibly use {x0,x0,x0}.
> + */
> + if (likely(!gprs))
> + return;
> +
> + reg_pcp = FIELD_GET(PCPU_GPR_PCP, gprs);
> + reg_off = FIELD_GET(PCPU_GPR_OFF, gprs);
> + reg_addr = FIELD_GET(PCPU_GPR_ADDR, gprs);
Would it not be more readable to write this like:
reg_pcp = (grps >> 0) & 0x1f;
reg_off = (grps >> 5) & 0x1f;
reg_addr = (grps >> 10) & 0x1f;
To better match __VAL_PCPU_GRPS() ?
> + pcp = pt_regs_read_reg(regs, reg_pcp);
> +
> + off = __kern_my_cpu_offset();
> + pt_regs_write_reg(regs, reg_off, off);
> +
> + addr = pcp + off;
> + pt_regs_write_reg(regs, reg_addr, addr);
> +}
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
2026-07-28 14:19 ` Peter Zijlstra
@ 2026-07-28 14:30 ` Peter Zijlstra
2026-07-28 16:03 ` Mark Rutland
2026-07-28 15:53 ` Mark Rutland
1 sibling, 1 reply; 22+ messages in thread
From: Peter Zijlstra @ 2026-07-28 14:30 UTC (permalink / raw)
To: Mark Rutland
Cc: vladimir.murzin, catalin.marinas, hca, linux-kernel, ruanjinjie,
yang, maz, will, ardb, linux-arm-kernel
On Tue, Jul 28, 2026 at 04:19:58PM +0200, Peter Zijlstra wrote:
> On Tue, Jul 28, 2026 at 01:38:52PM +0100, Mark Rutland wrote:
>
> > With the scheme added in this patch, this can be compiled as:
> >
> > | <outline_this_cpu_add_u64>:
> > | mrs x2, sp_el0
> > | mov x4, #0xc80
> > | strh w4, [x2, #20]
> > | mrs x4, tpidr_el1
> > | add x3, x0, x4
>
> Which it then recomputes, and so is harmless.
Here!
> > | 1: ldxr x6, [x3]
> > | add x6, x6, x1
> > | stxr w5, x6, [x3]
> > | cbnz w5, 1b
>
> If we get here and interrupts happens, we recompute pointlessly, no harm
> done.
>
> Anyway, per this sequence there is no point in ever doing the fixup. So
> perhaps give a better example?
Nevermind, brain just wasn't working right, when interrupt happens at
'Here!' above, it needs the fixup, irrespective of the atomic type.
> > | strh wzr, [x2, #20]
> > | ret
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
2026-07-28 14:30 ` Peter Zijlstra
@ 2026-07-28 16:03 ` Mark Rutland
2026-07-28 16:49 ` Peter Zijlstra
0 siblings, 1 reply; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 16:03 UTC (permalink / raw)
To: Peter Zijlstra
Cc: vladimir.murzin, catalin.marinas, hca, linux-kernel, ruanjinjie,
yang, maz, will, ardb, linux-arm-kernel
On Tue, Jul 28, 2026 at 04:30:16PM +0200, Peter Zijlstra wrote:
> On Tue, Jul 28, 2026 at 04:19:58PM +0200, Peter Zijlstra wrote:
> > On Tue, Jul 28, 2026 at 01:38:52PM +0100, Mark Rutland wrote:
> >
> > > With the scheme added in this patch, this can be compiled as:
> > >
> > > | <outline_this_cpu_add_u64>:
> > > | mrs x2, sp_el0
> > > | mov x4, #0xc80
> > > | strh w4, [x2, #20]
> > > | mrs x4, tpidr_el1
> > > | add x3, x0, x4
> >
> > Which it then recomputes, and so is harmless.
>
> Here!
>
> > > | 1: ldxr x6, [x3]
> > > | add x6, x6, x1
> > > | stxr w5, x6, [x3]
> > > | cbnz w5, 1b
> >
> > If we get here and interrupts happens, we recompute pointlessly, no harm
> > done.
> >
> > Anyway, per this sequence there is no point in ever doing the fixup. So
> > perhaps give a better example?
>
> Nevermind, brain just wasn't working right, when interrupt happens at
> 'Here!' above, it needs the fixup, irrespective of the atomic type.
Yep!
Note that the atomic type doesn't change things. We need the fixup even
if preemption happens *within* the LDXR...STXR loop, since the inline
sequences branches back to the LDXR, *without* recalculating the addr or
offset, and the fixup *does not* alter the PC.
It's a bit awkaward to spell that out in the commit message without
unrolling the loop :/
Mark.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
2026-07-28 16:03 ` Mark Rutland
@ 2026-07-28 16:49 ` Peter Zijlstra
0 siblings, 0 replies; 22+ messages in thread
From: Peter Zijlstra @ 2026-07-28 16:49 UTC (permalink / raw)
To: Mark Rutland
Cc: vladimir.murzin, catalin.marinas, hca, linux-kernel, ruanjinjie,
yang, maz, will, ardb, linux-arm-kernel
On Tue, Jul 28, 2026 at 05:03:57PM +0100, Mark Rutland wrote:
> On Tue, Jul 28, 2026 at 04:30:16PM +0200, Peter Zijlstra wrote:
> > On Tue, Jul 28, 2026 at 04:19:58PM +0200, Peter Zijlstra wrote:
> > > On Tue, Jul 28, 2026 at 01:38:52PM +0100, Mark Rutland wrote:
> > >
> > > > With the scheme added in this patch, this can be compiled as:
> > > >
> > > > | <outline_this_cpu_add_u64>:
> > > > | mrs x2, sp_el0
> > > > | mov x4, #0xc80
> > > > | strh w4, [x2, #20]
> > > > | mrs x4, tpidr_el1
> > > > | add x3, x0, x4
> > >
> > > Which it then recomputes, and so is harmless.
> >
> > Here!
> >
> > > > | 1: ldxr x6, [x3]
> > > > | add x6, x6, x1
> > > > | stxr w5, x6, [x3]
> > > > | cbnz w5, 1b
> > >
> > > If we get here and interrupts happens, we recompute pointlessly, no harm
> > > done.
> > >
> > > Anyway, per this sequence there is no point in ever doing the fixup. So
> > > perhaps give a better example?
> >
> > Nevermind, brain just wasn't working right, when interrupt happens at
> > 'Here!' above, it needs the fixup, irrespective of the atomic type.
>
> Yep!
>
> Note that the atomic type doesn't change things. We need the fixup even
> if preemption happens *within* the LDXR...STXR loop, since the inline
> sequences branches back to the LDXR, *without* recalculating the addr or
> offset, and the fixup *does not* alter the PC.
>
> It's a bit awkaward to spell that out in the commit message without
> unrolling the loop :/
Fair enough.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
2026-07-28 14:19 ` Peter Zijlstra
2026-07-28 14:30 ` Peter Zijlstra
@ 2026-07-28 15:53 ` Mark Rutland
2026-07-28 16:46 ` Peter Zijlstra
2026-07-28 16:49 ` Peter Zijlstra
1 sibling, 2 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 15:53 UTC (permalink / raw)
To: Peter Zijlstra
Cc: vladimir.murzin, catalin.marinas, hca, linux-kernel, ruanjinjie,
yang, maz, will, ardb, linux-arm-kernel
On Tue, Jul 28, 2026 at 04:19:58PM +0200, Peter Zijlstra wrote:
> On Tue, Jul 28, 2026 at 01:38:52PM +0100, Mark Rutland wrote:
>
> > With the scheme added in this patch, this can be compiled as:
> >
> > | <outline_this_cpu_add_u64>:
> > | mrs x2, sp_el0
> > | mov x4, #0xc80
>
> Perhaps add a comment to that like:
>
> | mov x4, #0xc80 # {x0, x4, x3}
>
> to make the literal less magical?
>
> > | strh w4, [x2, #20]
Sure, I'll make that:
| mov x4, #0xc80 // __VAL_PCPU_GPRS(x0, x4, x3)
... to match the code we use below.
> > +#define PCPU_GPR_PCP GENMASK(4, 0)
> > +#define PCPU_GPR_OFF GENMASK(9, 5)
> > +#define PCPU_GPR_ADDR GENMASK(14, 10)
>
> I hate those macros, I can never remember what they all do.
Ah. :/
We use them pretty commonly throughout arch/arm64/ (e.g. for all the
sysreg stuff), so the core arm64 folk are all familiar with them.
> Now, esp. since you then not use them here:
>
> > +#define __VAL_PCPU_GPRS(pcp, off, addr) \
> > + "(" \
> > + "(.L__gpr_num_" pcp " << 0) | " \
> > + "(.L__gpr_num_" off " << 5) | " \
> > + "(.L__gpr_num_" addr " << 10)" \
> > + ")"
>
> ... continue comment at irqentry_exit_pcpu_adjust().
I was being lazy here relative to what we do for asm-extable.h. How
about I match the pattern there, and have:
| #define PCPU_GPR_PCP_SHIFT 0
| #define PCPU_GPR_PCP GENMASK(4, 0)
| #define PCPU_GPR_OFF_SHIFT 5
| #define PCPU_GPR_OFF GENMASK(9, 5)
| #define PCPU_GPR_ADDR_SHIFT 10
| #define PCPU_GPR_ADDR GENMASK(14, 10)
|
| #define __VAL_PCPU_GPRS(pcp, off, addr) \
| "(" \
| "(.L__gpr_num_" pcp " << " __stringify(PCPU_GPR_PCP_SHIFT) ") | " \
| "(.L__gpr_num_" off " << " __stringify(PCPU_GPR_OFF_SHIFT) ") | " \
| "(.L__gpr_num_" addr " << " __stringify(PCPU_GPR_ADDR_SHIFT) ")" \
| ")"
... if that's any better?
Regardless of how we define these, I really want to keep the values in one
place (e.g. one header).
[...]
> > +#define ____PCPU_GPRS_BEGIN(gprs, pcp, off, addr) \
> > + __DEFINE_ASM_GPR_NUMS \
> > + __DEFINE_ASM_GPR_ALIASES \
> > + " mov w" off ", #" __VAL_PCPU_GPRS(pcp, off, addr) "\n" \
> > + " strh w" off ", " gprs "\n" \
> > + __KERN_ASM_CPU_OFFSET(off) "\n"
>
> Can this macro also generate a readable comment for those few of us
> building the .i file ?
Do you mean for __VAL_PCPU_GPRS, or ____PCPU_GPRS_BEGIN() ?
I can happily add comments for either (and the corresponding ENDs).
> > +/*
> > + * Where the context being returned to had an active percpu GPR critical
> > + * section, ensure that the offset and address GPRs are updated to match the
> > + * current CPU.
> > + *
> > + * For simplicity we always update the GPRs when a critical section is active
> > + * and preemption was *possible*, regardless of whether preemption actually
> > + * occurred. Where preemption did not occur, the updates are redundant but not
> > + * harmful.
> > + */
> > +static __always_inline void irqentry_exit_pcpu_adjust(struct pt_regs *regs)
> > +{
> > + int reg_pcp, reg_off, reg_addr;
> > + unsigned long pcp, off, addr;
> > + u16 gprs = regs->pcpu_gprs;
> > +
> > + /*
> > + * Zero means no active PCPU GPRs. As the PCPU GPRs must be distinct,
> > + * a PCPU critical section cannot possibly use {x0,x0,x0}.
> > + */
> > + if (likely(!gprs))
> > + return;
> > +
> > + reg_pcp = FIELD_GET(PCPU_GPR_PCP, gprs);
> > + reg_off = FIELD_GET(PCPU_GPR_OFF, gprs);
> > + reg_addr = FIELD_GET(PCPU_GPR_ADDR, gprs);
>
> Would it not be more readable to write this like:
>
> reg_pcp = (grps >> 0) & 0x1f;
> reg_off = (grps >> 5) & 0x1f;
> reg_addr = (grps >> 10) & 0x1f;
>
> To better match __VAL_PCPU_GRPS() ?
I wrote it this way to keep the field definitions in one place, and to
match what we do elsewhere, e.g.
| static bool ex_handler_uaccess_err_zero(const struct exception_table_entry *ex,
| struct pt_regs *regs)
| {
| int reg_err = FIELD_GET(EX_DATA_REG_ERR, ex->data);
| int reg_zero = FIELD_GET(EX_DATA_REG_ZERO, ex->data);
|
| pt_regs_write_reg(regs, reg_err, -EFAULT);
| pt_regs_write_reg(regs, reg_zero, 0);
|
| regs->pc = get_ex_fixup(ex);
| return true;
| }
My preference would be as-is (or with the proposal above), but I'll
defer to Will and Catalin.
If we do open-code the shifts, I'd strongly prefer that we have
<foo>_SHIFT constants to keep those in sync, e.g.
reg_pcp = (gprs >> PCPU_GRP_PCP_SHIFT) & 0x1f;
reg_off = (gprs >> PCPU_GRP_OFF_SHIFT) & 0x1f;
reg_addr = (gprs >> PCPU_GRP_ADDR_SHIFT) & 0x1f;
Mark.
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
2026-07-28 15:53 ` Mark Rutland
@ 2026-07-28 16:46 ` Peter Zijlstra
2026-07-28 16:49 ` Peter Zijlstra
1 sibling, 0 replies; 22+ messages in thread
From: Peter Zijlstra @ 2026-07-28 16:46 UTC (permalink / raw)
To: Mark Rutland
Cc: vladimir.murzin, catalin.marinas, hca, linux-kernel, ruanjinjie,
yang, maz, will, ardb, linux-arm-kernel
On Tue, Jul 28, 2026 at 04:53:52PM +0100, Mark Rutland wrote:
> I was being lazy here relative to what we do for asm-extable.h. How
> about I match the pattern there, and have:
>
> | #define PCPU_GPR_PCP_SHIFT 0
> | #define PCPU_GPR_PCP GENMASK(4, 0)
> | #define PCPU_GPR_OFF_SHIFT 5
> | #define PCPU_GPR_OFF GENMASK(9, 5)
> | #define PCPU_GPR_ADDR_SHIFT 10
> | #define PCPU_GPR_ADDR GENMASK(14, 10)
> |
> | #define __VAL_PCPU_GPRS(pcp, off, addr) \
> | "(" \
> | "(.L__gpr_num_" pcp " << " __stringify(PCPU_GPR_PCP_SHIFT) ") | " \
> | "(.L__gpr_num_" off " << " __stringify(PCPU_GPR_OFF_SHIFT) ") | " \
> | "(.L__gpr_num_" addr " << " __stringify(PCPU_GPR_ADDR_SHIFT) ")" \
> | ")"
>
> ... if that's any better?
#define PCPU_GPR_BITS 5
#define __PCPU_GPR_MASK(_shift) GENMASK((_shift+PCPU_GPR_BITS-1), _shift)
#define PCPU_GPR_PCP_SHIFT (0*PCPU_GPR_BITS)
#define PCPU_GPR_OFF_SHIFT (1*PCPU_GPR_BITS)
#define PCPU_GPR_ADDR_SHIFT (2*PCPU_GPR_BITS)
#define PCPU_GPR_PCP __PCPU_GPR_MASK(PCPU_GPR_PCP_SHIFT)
#define PCPU_GPR_OFF __PCPU_GPR_MASK(PCPU_GPR_OFF_SHIFT)
#define PCPU_GPR_ADDR __PCPU_GPR_MASK(PCPU_GPR_ADDR_SHIFT)
?
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
2026-07-28 15:53 ` Mark Rutland
2026-07-28 16:46 ` Peter Zijlstra
@ 2026-07-28 16:49 ` Peter Zijlstra
1 sibling, 0 replies; 22+ messages in thread
From: Peter Zijlstra @ 2026-07-28 16:49 UTC (permalink / raw)
To: Mark Rutland
Cc: vladimir.murzin, catalin.marinas, hca, linux-kernel, ruanjinjie,
yang, maz, will, ardb, linux-arm-kernel
On Tue, Jul 28, 2026 at 04:53:52PM +0100, Mark Rutland wrote:
> > > +#define ____PCPU_GPRS_BEGIN(gprs, pcp, off, addr) \
> > > + __DEFINE_ASM_GPR_NUMS \
> > > + __DEFINE_ASM_GPR_ALIASES \
> > > + " mov w" off ", #" __VAL_PCPU_GPRS(pcp, off, addr) "\n" \
> > > + " strh w" off ", " gprs "\n" \
> > > + __KERN_ASM_CPU_OFFSET(off) "\n"
> >
> > Can this macro also generate a readable comment for those few of us
> > building the .i file ?
>
> Do you mean for __VAL_PCPU_GPRS, or ____PCPU_GPRS_BEGIN() ?
I was thinking BEGIN, but whatever is easiest, the __VAL thing is only
ever used in BEGIN anyway.
> I can happily add comments for either (and the corresponding ENDs).
Not sure the comment makes sense for end, that's simply storing 0 and
seems clear enough.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops
2026-07-28 12:38 ` [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Mark Rutland
2026-07-28 14:19 ` Peter Zijlstra
@ 2026-07-28 16:51 ` Heiko Carstens
1 sibling, 0 replies; 22+ messages in thread
From: Heiko Carstens @ 2026-07-28 16:51 UTC (permalink / raw)
To: Mark Rutland
Cc: vladimir.murzin, peterz, maz, ruanjinjie, linux-kernel, yang,
catalin.marinas, will, ardb, linux-arm-kernel
On Tue, Jul 28, 2026 at 01:38:52PM +0100, Mark Rutland wrote:
> This patch adds infrastructure for a scheme where this_cpu_*() ops do
> not need to transiently disable preemption, avoiding the negative
> impacts described above.
>
> Each operation registers a critical section during which the exception
> return code will adjust the offset and addresses if preemption occurs
> mid-sequence. The critical section is registered/unregistered with a
> small prologue and epilogue which encodes three distinct GPRRs (<pcp>,
> <off>, <addr>) into a new thread_info::pcp_gprs field:
>
> // Prologue. Enable fixups for <off> and <addr>.
> mrs <tsk>, sp_el0
> mov <tmp>, #__VAL_PCPU_GPRS(<pcp>, <off>, <addr>)
> strh <tmp>, [<tsk>, #TSK_TI_PCPU_GPRS]
>
> // Generate cpu-specific address
> mrs <off>, TPIDR_ELx
> add <addr>, <pcp>, <off>
>
> // Perform access sequence
> ldr <val>, [<addr>]
>
> // Epilogue. Disable fixups
> strh wzr, [<tsk>, #TSK_TI_PCPU_GPRS]
>
> If an exception is taken from within the critical section, the exception
> return code will adjust <off> to be the current CPU's offset, and will
> adjust <addr> to be (<pcp> + <off>). Distinct registers are used for
> <pcp>, <off>, and <addr>, so that the fixup can be applied safely at any
> point during the critical section.
This looks indeed better than that what I came up with for s390.
It works without comparing instruction pointers, also works out-of-the-box
with kprobes, and hence the fixup is much simpler. I guess I'll try to change
s390 to a similar mechanism and see what the result will look like. It will
use one more instruction to the current version, as far as I can tell now, but
the simplicity is probably worth it.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [RFC PATCH 07/13] arm64: percpu: Implement preemptible read/write ops
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (5 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 08/13] arm64: percpu: Implement preemptible void RMW ops Mark Rutland
` (5 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Use the PCPU GPR infrastructure to implement preemptible this_cpu_read()
and this_cpu_write().
Note that this change means that this_cpu_read() will always use a plain
LDR, even in LTO configurations where READ_ONCE() will use LDA[P]R. I
am not sure whether that's ok, or whether we should similarly use
LDA[P]R here.
Generated code before this patch (v7.2-rc4):
| <outline_this_cpu_write_u64>:
| paciasp
| stp x29, x30, [sp, #-16]!
| mrs x2, sp_el0
| mov x29, sp
| ldr w3, [x2, #8]
| add w3, w3, #0x1
| str w3, [x2, #8]
| mrs x3, tpidr_el1
| str x1, [x0, x3]
| ldr x0, [x2, #8]
| sub x0, x0, #0x1
| str w0, [x2, #8]
| cbz x0, 1f
| ldr x0, [x2, #8]
| cbnz x0, 2f
| 1: bl preempt_schedule_notrace
| 2: ldp x29, x30, [sp], #16
| autiasp
| ret
Generated code after this patch:
| <outline_this_cpu_write_u64>:
| mrs x2, sp_el0
| mov w3, #0x7c60
| strh w3, [x2, #20]
| mrs x3, tpidr_el1
| str x1, [x0, x3]
| strh wzr, [x2, #20]
| ret
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/percpu.h | 79 ++++++++++++++++++++++++---------
1 file changed, 58 insertions(+), 21 deletions(-)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 0871dcc41d759..32623ea676b96 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -100,15 +100,42 @@ static inline unsigned long __kern_my_cpu_offset(void)
#define __my_cpu_offset __kern_my_cpu_offset()
#endif
-#define PERCPU_RW_OPS(sz) \
-static inline unsigned long __percpu_read_##sz(void *ptr) \
-{ \
- return READ_ONCE(*(u##sz *)ptr); \
-} \
- \
-static inline void __percpu_write_##sz(void *ptr, unsigned long val) \
-{ \
- WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \
+#define PERCPU_RW_OPS(w, sfx, sz) \
+static inline unsigned long __percpu_read_##sz(void __percpu *pcp) \
+{ \
+ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \
+ unsigned long off; \
+ unsigned long val; \
+ \
+ asm volatile( \
+ __PCPU_GPRS_BEGIN_OFFSET("%[gprs]", "%[pcp]", "%[off]") \
+ " ldr" #sfx "\t%" #w "[val], [%[pcp], %[off]]\n" \
+ __PCPU_GPRS_END("%[gprs]") \
+ : [gprs] "=Qo" (*gprs), \
+ [off] "=&r" (off), \
+ [val] "=&r" (val) \
+ : [pcp] "r" (pcp) \
+ : "memory" \
+ ); \
+ \
+ return val; \
+} \
+ \
+static inline void __percpu_write_##sz(void __percpu *pcp, unsigned long val) \
+{ \
+ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \
+ unsigned long off; \
+ \
+ asm volatile( \
+ __PCPU_GPRS_BEGIN_OFFSET("%[gprs]", "%[pcp]", "%[off]") \
+ " str" #sfx "\t%" #w "[val], [%[pcp], %[off]]\n" \
+ __PCPU_GPRS_END("%[gprs]") \
+ : [gprs] "=Qo" (*gprs), \
+ [off] "=&r" (off) \
+ : [pcp] "r" (pcp), \
+ [val] "r" (val) \
+ : "memory" \
+ ); \
}
#define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \
@@ -168,10 +195,10 @@ __percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \
__PERCPU_RET_OP_CASE(w, , name, 32, op_llsc, op_lse) \
__PERCPU_RET_OP_CASE( , , name, 64, op_llsc, op_lse)
-PERCPU_RW_OPS(8)
-PERCPU_RW_OPS(16)
-PERCPU_RW_OPS(32)
-PERCPU_RW_OPS(64)
+PERCPU_RW_OPS(w, b, 8)
+PERCPU_RW_OPS(w, h, 16)
+PERCPU_RW_OPS(w, , 32)
+PERCPU_RW_OPS( , , 64)
/*
* Use value-returning atomics for CPU-local ops as they are more likely
@@ -217,23 +244,33 @@ PERCPU_RET_OP(add, add, ldadd)
__retval; \
})
+#define _pcp_wrap(op, pcp, ...) \
+({ \
+ op(&(pcp), __VA_ARGS__); \
+})
+
+#define _pcp_wrap_return(op, pcp, args...) \
+({ \
+ (typeof(pcp))op(&(pcp), ##args); \
+})
+
#define this_cpu_read_1(pcp) \
- _pcp_protect_return(__percpu_read_8, pcp)
+ _pcp_wrap_return(__percpu_read_8, pcp)
#define this_cpu_read_2(pcp) \
- _pcp_protect_return(__percpu_read_16, pcp)
+ _pcp_wrap_return(__percpu_read_16, pcp)
#define this_cpu_read_4(pcp) \
- _pcp_protect_return(__percpu_read_32, pcp)
+ _pcp_wrap_return(__percpu_read_32, pcp)
#define this_cpu_read_8(pcp) \
- _pcp_protect_return(__percpu_read_64, pcp)
+ _pcp_wrap_return(__percpu_read_64, pcp)
#define this_cpu_write_1(pcp, val) \
- _pcp_protect(__percpu_write_8, pcp, (unsigned long)val)
+ _pcp_wrap(__percpu_write_8, pcp, (unsigned long)val)
#define this_cpu_write_2(pcp, val) \
- _pcp_protect(__percpu_write_16, pcp, (unsigned long)val)
+ _pcp_wrap(__percpu_write_16, pcp, (unsigned long)val)
#define this_cpu_write_4(pcp, val) \
- _pcp_protect(__percpu_write_32, pcp, (unsigned long)val)
+ _pcp_wrap(__percpu_write_32, pcp, (unsigned long)val)
#define this_cpu_write_8(pcp, val) \
- _pcp_protect(__percpu_write_64, pcp, (unsigned long)val)
+ _pcp_wrap(__percpu_write_64, pcp, (unsigned long)val)
#define this_cpu_add_1(pcp, val) \
_pcp_protect(__percpu_add_case_8, pcp, val)
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 08/13] arm64: percpu: Implement preemptible void RMW ops
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (6 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 07/13] arm64: percpu: Implement preemptible read/write ops Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 09/13] arm64: percpu: Implement preemptible return " Mark Rutland
` (4 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Use the PCPU GPR infrastructure to implement all of the RMW ops which do not
return a value.
Generated code before this patch (v7.2-rc4):
| <outline_this_cpu_add_u64>:
| paciasp
| stp x29, x30, [sp, #-16]!
| mrs x2, sp_el0
| mov x29, sp
| ldr w3, [x2, #8]
| add w3, w3, #0x1
| str w3, [x2, #8]
| mrs x3, tpidr_el1
| add x0, x0, x3
| 1: ldxr x5, [x0]
| add x5, x5, x1
| stxr w4, x5, [x0]
| cbnz w4, 1b
| ldr x0, [x2, #8]
| sub x0, x0, #0x1
| str w0, [x2, #8]
| cbz x0, 2f
| ldr x0, [x2, #8]
| cbnz x0, 3f
| 2: bl preempt_schedule_notrace
| 3: ldp x29, x30, [sp], #16
| autiasp
| ret
Generated code after this patch:
| <outline_this_cpu_add_u64>:
| mrs x2, sp_el0
| mov w4, #0xc80
| strh w4, [x2, #20]
| mrs x4, tpidr_el1
| add x3, x0, x4
| 1: ldxr x6, [x3]
| add x6, x6, x1
| stxr w5, x6, [x3]
| cbnz w5, 1b
| strh wzr, [x2, #20]
| ret
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/percpu.h | 52 ++++++++++++++++++++-------------
1 file changed, 32 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 32623ea676b96..7e9ab51561706 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -140,23 +140,35 @@ static inline void __percpu_write_##sz(void __percpu *pcp, unsigned long val) \
#define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \
static inline void \
-__percpu_##name##_case_##sz(void *ptr, unsigned long val) \
+__percpu_##name##_case_##sz(void __percpu *pcp, unsigned long val) \
{ \
+ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \
+ unsigned long addr; \
+ unsigned long off; \
unsigned int loop; \
u##sz tmp; \
\
- asm volatile (ARM64_LSE_ATOMIC_INSN( \
+ asm volatile ( \
+ __PCPU_GPRS_BEGIN("%[gprs]", "%[pcp]", "%[off]", "%[addr]") \
+ ARM64_LSE_ATOMIC_INSN( \
/* LL/SC */ \
- "1: ldxr" #sfx "\t%" #w "[tmp], %[ptr]\n" \
+ "1: ldxr" #sfx "\t%" #w "[tmp], [%[addr]]\n" \
#op_llsc "\t%" #w "[tmp], %" #w "[tmp], %" #w "[val]\n" \
- " stxr" #sfx "\t%w[loop], %" #w "[tmp], %[ptr]\n" \
+ " stxr" #sfx "\t%w[loop], %" #w "[tmp], [%[addr]]\n" \
" cbnz %w[loop], 1b", \
/* LSE atomics */ \
- #op_lse "\t%" #w "[val], %" #w "[tmp], %[ptr]\n" \
+ #op_lse "\t%" #w "[val], %" #w "[tmp], [%[addr]]\n" \
__nops(3)) \
- : [loop] "=&r" (loop), [tmp] "=&r" (tmp), \
- [ptr] "+Q"(*(u##sz *)ptr) \
- : [val] "r" ((u##sz)(val))); \
+ __PCPU_GPRS_END("%[gprs]") \
+ : [gprs] "=Qo" (*gprs), \
+ [addr] "=&r" (addr), \
+ [off] "=&r" (off), \
+ [loop] "=&r" (loop), \
+ [tmp] "=&r" (tmp) \
+ : [pcp] "r" (pcp), \
+ [val] "r" ((u##sz)(val)) \
+ : "memory" \
+ ); \
}
#define __PERCPU_RET_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \
@@ -273,13 +285,13 @@ PERCPU_RET_OP(add, add, ldadd)
_pcp_wrap(__percpu_write_64, pcp, (unsigned long)val)
#define this_cpu_add_1(pcp, val) \
- _pcp_protect(__percpu_add_case_8, pcp, val)
+ _pcp_wrap(__percpu_add_case_8, pcp, val)
#define this_cpu_add_2(pcp, val) \
- _pcp_protect(__percpu_add_case_16, pcp, val)
+ _pcp_wrap(__percpu_add_case_16, pcp, val)
#define this_cpu_add_4(pcp, val) \
- _pcp_protect(__percpu_add_case_32, pcp, val)
+ _pcp_wrap(__percpu_add_case_32, pcp, val)
#define this_cpu_add_8(pcp, val) \
- _pcp_protect(__percpu_add_case_64, pcp, val)
+ _pcp_wrap(__percpu_add_case_64, pcp, val)
#define this_cpu_add_return_1(pcp, val) \
_pcp_protect_return(__percpu_add_return_case_8, pcp, val)
@@ -291,22 +303,22 @@ PERCPU_RET_OP(add, add, ldadd)
_pcp_protect_return(__percpu_add_return_case_64, pcp, val)
#define this_cpu_and_1(pcp, val) \
- _pcp_protect(__percpu_andnot_case_8, pcp, ~val)
+ _pcp_wrap(__percpu_andnot_case_8, pcp, ~val)
#define this_cpu_and_2(pcp, val) \
- _pcp_protect(__percpu_andnot_case_16, pcp, ~val)
+ _pcp_wrap(__percpu_andnot_case_16, pcp, ~val)
#define this_cpu_and_4(pcp, val) \
- _pcp_protect(__percpu_andnot_case_32, pcp, ~val)
+ _pcp_wrap(__percpu_andnot_case_32, pcp, ~val)
#define this_cpu_and_8(pcp, val) \
- _pcp_protect(__percpu_andnot_case_64, pcp, ~val)
+ _pcp_wrap(__percpu_andnot_case_64, pcp, ~val)
#define this_cpu_or_1(pcp, val) \
- _pcp_protect(__percpu_or_case_8, pcp, val)
+ _pcp_wrap(__percpu_or_case_8, pcp, val)
#define this_cpu_or_2(pcp, val) \
- _pcp_protect(__percpu_or_case_16, pcp, val)
+ _pcp_wrap(__percpu_or_case_16, pcp, val)
#define this_cpu_or_4(pcp, val) \
- _pcp_protect(__percpu_or_case_32, pcp, val)
+ _pcp_wrap(__percpu_or_case_32, pcp, val)
#define this_cpu_or_8(pcp, val) \
- _pcp_protect(__percpu_or_case_64, pcp, val)
+ _pcp_wrap(__percpu_or_case_64, pcp, val)
#define this_cpu_xchg_1(pcp, val) \
_pcp_protect_return(xchg_relaxed, pcp, val)
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 09/13] arm64: percpu: Implement preemptible return RMW ops
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (7 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 08/13] arm64: percpu: Implement preemptible void RMW ops Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 10/13] arm64: percpu: Implement preemptible XCHG ops Mark Rutland
` (3 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Use the PCPU GPR infrastructure to implement all of the RMW ops which
return a value.
Generated code before this patch (v7.2-rc4):
| <outline_this_cpu_add_return_u64>:
| paciasp
| stp x29, x30, [sp, #-32]!
| mrs x3, sp_el0
| mov x29, sp
| ldr w2, [x3, #8]
| add w2, w2, #0x1
| str w2, [x3, #8]
| mov x2, x0
| mrs x4, tpidr_el1
| add x2, x2, x4
| 1: ldxr x0, [x2]
| add x0, x0, x1
| stxr w5, x0, [x2]
| cbnz w5, 1b
| ldr x1, [x3, #8]
| sub x1, x1, #0x1
| str w1, [x3, #8]
| cbz x1, 2f
| ldr x1, [x3, #8]
| cbnz x1, 3f
| 2: str x0, [sp, #24]
| bl 0 <preempt_schedule_notrace>
| ldr x0, [sp, #24]
| 3: ldp x29, x30, [sp], #32
| autiasp
| ret
Generated code after this patch:
| <outline_this_cpu_add_return_u64>:
| mrs x3, sp_el0
| mov w5, #0x10a0
| strh w5, [x3, #20]
| mrs x5, tpidr_el1
| add x4, x0, x5
| 1: ldxr x2, [x4]
| add x2, x2, x1
| stxr w6, x2, [x4]
| cbnz w6, 1b
| strh wzr, [x3, #20]
| mov x0, x2
| ret
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/percpu.h | 36 ++++++++++++++++++++++-----------
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 7e9ab51561706..3e79bb8b6c9d0 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -173,24 +173,36 @@ __percpu_##name##_case_##sz(void __percpu *pcp, unsigned long val) \
#define __PERCPU_RET_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \
static inline u##sz \
-__percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \
+__percpu_##name##_return_case_##sz(void __percpu *pcp, unsigned long val) \
{ \
+ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \
+ unsigned long addr; \
+ unsigned long off; \
unsigned int loop; \
u##sz ret; \
\
- asm volatile (ARM64_LSE_ATOMIC_INSN( \
+ asm volatile ( \
+ __PCPU_GPRS_BEGIN("%[gprs]", "%[pcp]", "%[off]", "%[addr]") \
+ ARM64_LSE_ATOMIC_INSN( \
/* LL/SC */ \
- "1: ldxr" #sfx "\t%" #w "[ret], %[ptr]\n" \
+ "1: ldxr" #sfx "\t%" #w "[ret], [%[addr]]\n" \
#op_llsc "\t%" #w "[ret], %" #w "[ret], %" #w "[val]\n" \
- " stxr" #sfx "\t%w[loop], %" #w "[ret], %[ptr]\n" \
+ " stxr" #sfx "\t%w[loop], %" #w "[ret], [%[addr]]\n" \
" cbnz %w[loop], 1b", \
/* LSE atomics */ \
- #op_lse "\t%" #w "[val], %" #w "[ret], %[ptr]\n" \
+ #op_lse "\t%" #w "[val], %" #w "[ret], [%[addr]]\n" \
#op_llsc "\t%" #w "[ret], %" #w "[ret], %" #w "[val]\n" \
__nops(2)) \
- : [loop] "=&r" (loop), [ret] "=&r" (ret), \
- [ptr] "+Q"(*(u##sz *)ptr) \
- : [val] "r" ((u##sz)(val))); \
+ __PCPU_GPRS_END("%[gprs]") \
+ : [gprs] "=Qo" (*gprs), \
+ [addr] "=&r" (addr), \
+ [off] "=&r" (off), \
+ [loop] "=&r" (loop), \
+ [ret] "=&r" (ret) \
+ : [pcp] "r" (pcp), \
+ [val] "r" ((u##sz)(val)) \
+ : "memory" \
+ ); \
\
return ret; \
}
@@ -294,13 +306,13 @@ PERCPU_RET_OP(add, add, ldadd)
_pcp_wrap(__percpu_add_case_64, pcp, val)
#define this_cpu_add_return_1(pcp, val) \
- _pcp_protect_return(__percpu_add_return_case_8, pcp, val)
+ _pcp_wrap_return(__percpu_add_return_case_8, pcp, val)
#define this_cpu_add_return_2(pcp, val) \
- _pcp_protect_return(__percpu_add_return_case_16, pcp, val)
+ _pcp_wrap_return(__percpu_add_return_case_16, pcp, val)
#define this_cpu_add_return_4(pcp, val) \
- _pcp_protect_return(__percpu_add_return_case_32, pcp, val)
+ _pcp_wrap_return(__percpu_add_return_case_32, pcp, val)
#define this_cpu_add_return_8(pcp, val) \
- _pcp_protect_return(__percpu_add_return_case_64, pcp, val)
+ _pcp_wrap_return(__percpu_add_return_case_64, pcp, val)
#define this_cpu_and_1(pcp, val) \
_pcp_wrap(__percpu_andnot_case_8, pcp, ~val)
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 10/13] arm64: percpu: Implement preemptible XCHG ops
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (8 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 09/13] arm64: percpu: Implement preemptible return " Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 11/13] arm64: percpu: Implement preemptible CMPXCHG ops Mark Rutland
` (2 subsequent siblings)
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Use the PCPU GPR infrastructure to implement all of the xchg ops
Generated code before this patch (v7.2-rc4):
| <outline_this_cpu_xchg_u64>:
| paciasp
| stp x29, x30, [sp, #-32]!
| mrs x3, sp_el0
| mov x29, sp
| ldr w2, [x3, #8]
| add w2, w2, #0x1
| str w2, [x3, #8]
| mov x2, x0
| mrs x4, tpidr_el1
| add x2, x2, x4
| prfm pstl1strm, [x2]
| 1: ldxr x0, [x2]
| stxr w5, x1, [x2]
| cbnz w5, 1b
| ldr x1, [x3, #8]
| sub x1, x1, #0x1
| str w1, [x3, #8]
| cbz x1, 2f
| ldr x1, [x3, #8]
| cbnz x1, 3f
| 2: str x0, [sp, #24]
| bl preempt_schedule_notrace
| ldr x0, [sp, #24]
| 3: ldp x29, x30, [sp], #32
| autiasp
| ret
Generated code after this patch:
| <outline_this_cpu_xchg_u64>:
| mrs x3, sp_el0
| mov w5, #0x10a0
| strh w5, [x3, #20]
| mrs x5, tpidr_el1
| add x4, x0, x5
| prfm pstl1strm, [x4]
| 1: ldxr x2, [x4]
| stxr w6, x1, [x4]
| cbnz w6, 1b
| strh wzr, [x3, #20]
| mov x0, x2
| ret
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/percpu.h | 57 ++++++++++++++++++++++++++++++---
1 file changed, 53 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 3e79bb8b6c9d0..d5b733ce49b07 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -241,6 +241,50 @@ PERCPU_RET_OP(add, add, ldadd)
#undef PERCPU_OP
#undef PERCPU_RET_OP
+#define PERCPU_XCHG_OP(w, sfx, sz) \
+static inline unsigned long \
+__percpu_xchg_case_##sz(void __percpu *pcp, unsigned long val) \
+{ \
+ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \
+ unsigned long addr; \
+ unsigned long off; \
+ unsigned int loop; \
+ unsigned long ret; \
+ \
+ asm volatile ( \
+ __PCPU_GPRS_BEGIN("%[gprs]", "%[pcp]", "%[off]", "%[addr]") \
+ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ " prfm pstl1strm, [%[addr]]\n" \
+ "1: ldxr" #sfx "\t%" #w "[ret], [%[addr]]\n" \
+ " stxr" #sfx "\t%w[loop], %" #w "[val], [%[addr]]\n" \
+ " cbnz %w[loop], 1b\n" \
+ , \
+ /* LSE atomics */ \
+ " swp" #sfx "\t%" #w "[val], %" #w "[ret], [%[addr]]\n" \
+ __nops(3) \
+ ) \
+ __PCPU_GPRS_END("%[gprs]") \
+ : [gprs] "=Qo" (*gprs), \
+ [addr] "=&r" (addr), \
+ [off] "=&r" (off), \
+ [loop] "=&r" (loop), \
+ [ret] "=&r" (ret) \
+ : [pcp] "r" (pcp), \
+ [val] "r" ((u##sz)(val)) \
+ : "memory" \
+ ); \
+ \
+ return ret; \
+}
+
+PERCPU_XCHG_OP(w, b, 8)
+PERCPU_XCHG_OP(w, h, 16)
+PERCPU_XCHG_OP(w, , 32)
+PERCPU_XCHG_OP(x, , 64)
+
+#undef PERCPU_XCHG_OP
+
/*
* It would be nice to avoid the conditional call into the scheduler when
* re-enabling preemption for preemptible kernels, but doing that in a way
@@ -278,6 +322,11 @@ PERCPU_RET_OP(add, add, ldadd)
(typeof(pcp))op(&(pcp), ##args); \
})
+#define _pcp_wrap_xchg(op, pcp, val) \
+({ \
+ (typeof(pcp))op(&(pcp), (unsigned long)(val)); \
+})
+
#define this_cpu_read_1(pcp) \
_pcp_wrap_return(__percpu_read_8, pcp)
#define this_cpu_read_2(pcp) \
@@ -333,13 +382,13 @@ PERCPU_RET_OP(add, add, ldadd)
_pcp_wrap(__percpu_or_case_64, pcp, val)
#define this_cpu_xchg_1(pcp, val) \
- _pcp_protect_return(xchg_relaxed, pcp, val)
+ _pcp_wrap_xchg(__percpu_xchg_case_8, pcp, val)
#define this_cpu_xchg_2(pcp, val) \
- _pcp_protect_return(xchg_relaxed, pcp, val)
+ _pcp_wrap_xchg(__percpu_xchg_case_16, pcp, val)
#define this_cpu_xchg_4(pcp, val) \
- _pcp_protect_return(xchg_relaxed, pcp, val)
+ _pcp_wrap_xchg(__percpu_xchg_case_32, pcp, val)
#define this_cpu_xchg_8(pcp, val) \
- _pcp_protect_return(xchg_relaxed, pcp, val)
+ _pcp_wrap_xchg(__percpu_xchg_case_64, pcp, val)
#define this_cpu_cmpxchg_1(pcp, o, n) \
_pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 11/13] arm64: percpu: Implement preemptible CMPXCHG ops
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (9 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 10/13] arm64: percpu: Implement preemptible XCHG ops Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 12/13] arm64: percpu: Implement preemptible CMPXCHG128 ops Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 13/13] arm64: percpu: Remove _pcp_protect*() wrappers Mark Rutland
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Use the PCPU GPR infrastructure to implement all of the {8,16,32,64}-bit
cmpxchg ops.
Note that before this patch, the LL/SC and LSE implementation was chosen
with an alternative branch. After this patch the implementations are
patched inline, matching the style of the other percpu ops.
Generated code before this patch (v7.2-rc4):
| <outline_this_cpu_cmpxchg_u64>:
| paciasp
| stp x29, x30, [sp, #-32]!
| mrs x4, sp_el0
| mov x29, sp
| ldr w3, [x4, #8]
| add w3, w3, #0x1
| str w3, [x4, #8]
| mrs x3, tpidr_el1
| add x3, x0, x3
| b 4f // alternative branch
| cas x1, x2, [x3]
| mov x0, x1
| 1: mrs x2, sp_el0
| ldr x1, [x2, #8]
| sub x1, x1, #0x1
| str w1, [x2, #8]
| cbz x1, 2f
| ldr x1, [x2, #8]
| cbnz x1, 3f
| 2: str x0, [sp, #24]
| bl preempt_schedule_notrace
| ldr x0, [sp, #24]
| 3: ldp x29, x30, [sp], #32
| autiasp
| ret
| 4: prfm pstl1strm, [x3]
| 5: ldxr x0, [x3]
| eor x4, x0, x1
| cbnz x4, 6f
| stxr w4, x2, [x3]
| cbnz w4, 5b
| 6: b 1b
Generated code after this patch:
| <outline_this_cpu_cmpxchg_u64>:
| mrs x4, sp_el0
| mov w6, #0x14c0
| strh w6, [x4, #20]
| mrs x6, tpidr_el1
| add x5, x0, x6
| prfm pstl1strm, [x5]
| 1: ldxr x3, [x5]
| eor x7, x3, x1
| cbnz x7, 2f
| stxr w7, x2, [x5]
| cbnz w7, 1b
| 2: strh wzr, [x4, #20]
| mov x0, x3
| ret
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/percpu.h | 72 +++++++++++++++++++++++++++++++--
1 file changed, 68 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index d5b733ce49b07..c539303a2c97a 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -278,12 +278,70 @@ __percpu_xchg_case_##sz(void __percpu *pcp, unsigned long val) \
return ret; \
}
+#define PERCPU_CMPXCHG_OP(w, sfx, sz) \
+static inline unsigned long \
+__percpu_cmpxchg_case_##sz(void __percpu *pcp, \
+ unsigned long old, \
+ unsigned long new) \
+{ \
+ u16 *gprs = ¤t_thread_info()->pcpu_gprs; \
+ unsigned long addr; \
+ unsigned long off; \
+ unsigned long tmp; \
+ unsigned long oldval; \
+ \
+ /* \
+ * Sub-word sizes require explicit casting so that the LL/SC \
+ * EOR+CBNZ doesn't end up interpreting non-zero upper bits of \
+ * the register containing "old". \
+ */ \
+ if (sz < 32) \
+ old = (u##sz)old; \
+ \
+ asm volatile ( \
+ __PCPU_GPRS_BEGIN("%[gprs]", "%[pcp]", "%[off]", "%[addr]") \
+ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ " prfm pstl1strm, [%[addr]]\n" \
+ "1: ldxr" #sfx "\t%" #w "[oldval], [%[addr]]\n" \
+ " eor %" #w "[tmp], %" #w "[oldval], %" #w "[old]\n" \
+ " cbnz %" #w "[tmp], 2f\n" \
+ " stxr" #sfx "\t%w[tmp], %" #w "[new], [%[addr]]\n" \
+ " cbnz %w[tmp], 1b\n" \
+ "2:\n" \
+ , \
+ /* LSE atomics */ \
+ " mov %[oldval], %[old]\n" \
+ " cas" #sfx "\t%" #w "[oldval], %" #w "[new], [%[addr]]\n"\
+ __nops(4) \
+ ) \
+ __PCPU_GPRS_END("%[gprs]") \
+ : [gprs] "=Qo" (*gprs), \
+ [addr] "=&r" (addr), \
+ [off] "=&r" (off), \
+ [tmp] "=&r" (tmp), \
+ [oldval] "=&r" (oldval) \
+ : [pcp] "r" (pcp), \
+ [old] "r" (old), \
+ [new] "r" (new) \
+ : "memory" \
+ ); \
+ \
+ return oldval; \
+}
+
PERCPU_XCHG_OP(w, b, 8)
PERCPU_XCHG_OP(w, h, 16)
PERCPU_XCHG_OP(w, , 32)
PERCPU_XCHG_OP(x, , 64)
+PERCPU_CMPXCHG_OP(w, b, 8)
+PERCPU_CMPXCHG_OP(w, h, 16)
+PERCPU_CMPXCHG_OP(w, , 32)
+PERCPU_CMPXCHG_OP(x, , 64)
+
#undef PERCPU_XCHG_OP
+#undef PERCPU_CMPXCHG_OP
/*
* It would be nice to avoid the conditional call into the scheduler when
@@ -327,6 +385,12 @@ PERCPU_XCHG_OP(x, , 64)
(typeof(pcp))op(&(pcp), (unsigned long)(val)); \
})
+#define _pcp_wrap_cmpxchg(op, pcp, old, new) \
+({ \
+ (typeof(pcp))op(&(pcp), (unsigned long)(old), \
+ (unsigned long)(new)); \
+})
+
#define this_cpu_read_1(pcp) \
_pcp_wrap_return(__percpu_read_8, pcp)
#define this_cpu_read_2(pcp) \
@@ -391,13 +455,13 @@ PERCPU_XCHG_OP(x, , 64)
_pcp_wrap_xchg(__percpu_xchg_case_64, pcp, val)
#define this_cpu_cmpxchg_1(pcp, o, n) \
- _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
+ _pcp_wrap_cmpxchg(__percpu_cmpxchg_case_8, pcp, o, n)
#define this_cpu_cmpxchg_2(pcp, o, n) \
- _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
+ _pcp_wrap_cmpxchg(__percpu_cmpxchg_case_16, pcp, o, n)
#define this_cpu_cmpxchg_4(pcp, o, n) \
- _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
+ _pcp_wrap_cmpxchg(__percpu_cmpxchg_case_32, pcp, o, n)
#define this_cpu_cmpxchg_8(pcp, o, n) \
- _pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
+ _pcp_wrap_cmpxchg(__percpu_cmpxchg_case_64, pcp, o, n)
#define this_cpu_cmpxchg64(pcp, o, n) this_cpu_cmpxchg_8(pcp, o, n)
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 12/13] arm64: percpu: Implement preemptible CMPXCHG128 ops
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (10 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 11/13] arm64: percpu: Implement preemptible CMPXCHG ops Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 13/13] arm64: percpu: Remove _pcp_protect*() wrappers Mark Rutland
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Use the PCPU GPR infrastructure to implement this_cpu_cmpxchg128().
Note that before this patch, the LL/SC and LSE implementation was chosen
with an alternative branch. After this patch the implementations are
patched inline, matching the style of the other percpu ops.
The sub-optimal register shuffling before and after this patch occurs
because we hard-code specific registers, as LLVM lacks a way to place a
128-bit type in an even-odd pair of registers for inline assembly. We
should be able to improve this in future.
Generated code before this patch (v7.2-rc4):
| <outline_this_cpu_cmpxchg128>:
| paciasp
| stp x29, x30, [sp, #-32]!
| mov x6, x0
| mov x0, x2
| mov x29, sp
| mov x1, x3
| mrs x2, sp_el0
| ldr w7, [x2, #8]
| add w7, w7, #0x1
| str w7, [x2, #8]
| mrs x2, tpidr_el1
| add x6, x6, x2
| b 4f
| mov x2, x4
| mov x3, x5
| mov x4, x6
| mov x5, x0
| mov x7, x1
| casp x0, x1, x2, x3, [x6]
| 1: mrs x3, sp_el0
| ldr x2, [x3, #8]
| sub x2, x2, #0x1
| str w2, [x3, #8]
| cbz x2, 2f
| ldr x2, [x3, #8]
| cbnz x2, 3f
| 2: stp x0, x1, [sp, #16]
| bl preempt_schedule_notrace
| ldp x0, x1, [sp, #16]
| 3: ldp x29, x30, [sp], #32
| autiasp
| ret
| 4: prfm pstl1strm, [x6]
| 5: ldxp x8, x7, [x6]
| cmp x8, x0
| ccmp x7, x3, #0x0, eq
| b.ne 6f
| stxp w2, x4, x5, [x6]
| cbnz w2, 5b
| 6: mov x0, x8
| mov x1, x7
| b 1b
Generated code after this patch:
| <outline_this_cpu_cmpxchg128>:
| mov x6, x0
| mov x1, x3
| mov x0, x2
| mov x3, x5
| mrs x7, sp_el0
| mov x2, x4
| mov w5, #0x10a6
| strh w5, [x7, #20]
| mrs x5, tpidr_el1
| add x4, x6, x5
| prfm pstl1strm, [x4]
| 1: ldxp x9, x10, [x4]
| cmp x9, x0
| ccmp x10, x1, #0x0, eq
| b.ne 2f
| stxp w8, x2, x3, [x4]
| cbnz w8, 1b
| 2: strh wzr, [x7, #20]
| mov x0, x9
| mov x1, x10
| ret
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/percpu.h | 70 +++++++++++++++++++++++++++------
1 file changed, 57 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index c539303a2c97a..6785d1bc933b9 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -465,19 +465,63 @@ PERCPU_CMPXCHG_OP(x, , 64)
#define this_cpu_cmpxchg64(pcp, o, n) this_cpu_cmpxchg_8(pcp, o, n)
-#define this_cpu_cmpxchg128(pcp, o, n) \
-({ \
- typedef typeof(pcp) pcp_op_T__; \
- u128 old__, new__, ret__; \
- pcp_op_T__ *ptr__; \
- old__ = o; \
- new__ = n; \
- preempt_disable_notrace(); \
- ptr__ = raw_cpu_ptr(&(pcp)); \
- ret__ = cmpxchg128_local((void *)ptr__, old__, new__); \
- preempt_enable_notrace(); \
- ret__; \
-})
+static inline u128
+__percpu_cmpxchg_128(void __percpu *pcp, u128 old, u128 new)
+{
+ u16 *gprs = ¤t_thread_info()->pcpu_gprs;
+ unsigned long addr;
+ unsigned long off;
+ union __u128_halves r, o = { .full = (old) },
+ n = { .full = (new) };
+ register unsigned long ol asm ("x0") = o.low;
+ register unsigned long oh asm ("x1") = o.high;
+ register unsigned long nl asm ("x2") = n.low;
+ register unsigned long nh asm ("x3") = n.high;
+ unsigned long rl, rh;
+ unsigned long tmp;
+
+ asm volatile (
+ __PCPU_GPRS_BEGIN("%[gprs]", "%[pcp]", "%[off]", "%[addr]")
+ ARM64_LSE_ATOMIC_INSN(
+ /* LL/SC */
+ " prfm pstl1strm, [%[addr]]\n"
+ "1: ldxp %[rl], %[rh], [%[addr]]\n"
+ " cmp %[rl], %[ol]\n"
+ " ccmp %[rh], %[oh], 0, eq\n"
+ " b.ne 2f\n"
+ " stxp %w[tmp], %[nl], %[nh], [%[addr]]\n"
+ " cbnz %w[tmp], 1b\n"
+ "2:\n"
+ ,
+ /* LSE atomics */
+ " casp %[ol], %[oh], %[nl], %[nh], [%[addr]]\n"
+ " mov %[rl], %[ol]\n"
+ " mov %[rh], %[oh]\n"
+ __nops(4)
+ )
+ __PCPU_GPRS_END("%[gprs]")
+ : [gprs] "=Qo" (*gprs),
+ [addr] "=&r" (addr),
+ [off] "=&r" (off),
+ [tmp] "=&r" (tmp),
+ [ol] "+&r" (ol),
+ [oh] "+&r" (oh),
+ [rl] "=&r" (rl),
+ [rh] "=&r" (rh)
+ : [pcp] "r" (pcp),
+ [nl] "r" (nl),
+ [nh] "r" (nh)
+ : "memory", "cc"
+ );
+
+ r.low = rl;
+ r.high = rh;
+
+ return r.full;
+}
+
+#define this_cpu_cmpxchg128(pcp, o, n) \
+ _pcp_wrap_return(__percpu_cmpxchg_128, pcp, o, n)
#ifdef __KVM_NVHE_HYPERVISOR__
extern unsigned long __hyp_per_cpu_offset(unsigned int cpu);
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread* [RFC PATCH 13/13] arm64: percpu: Remove _pcp_protect*() wrappers
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
` (11 preceding siblings ...)
2026-07-28 12:38 ` [RFC PATCH 12/13] arm64: percpu: Implement preemptible CMPXCHG128 ops Mark Rutland
@ 2026-07-28 12:38 ` Mark Rutland
12 siblings, 0 replies; 22+ messages in thread
From: Mark Rutland @ 2026-07-28 12:38 UTC (permalink / raw)
To: linux-arm-kernel
Cc: mark.rutland, vladimir.murzin, peterz, catalin.marinas, hca,
linux-kernel, ruanjinjie, yang, maz, will, ardb
Now that all this_cpu_*() operations are preemptible, there are no users
of _pcp_protect() or _pcp_protect_return().
Remove them both, along with the associated comment regarding
preemption.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jinjie Ruan <ruanjinjie@huawei.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
---
arch/arm64/include/asm/percpu.h | 27 ---------------------------
1 file changed, 27 deletions(-)
diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h
index 6785d1bc933b9..aa1fd9a09c7cb 100644
--- a/arch/arm64/include/asm/percpu.h
+++ b/arch/arm64/include/asm/percpu.h
@@ -343,33 +343,6 @@ PERCPU_CMPXCHG_OP(x, , 64)
#undef PERCPU_XCHG_OP
#undef PERCPU_CMPXCHG_OP
-/*
- * It would be nice to avoid the conditional call into the scheduler when
- * re-enabling preemption for preemptible kernels, but doing that in a way
- * which builds inside a module would mean messing directly with the preempt
- * count. If you do this, peterz and tglx will hunt you down.
- *
- * Not to mention it'll break the actual preemption model for missing a
- * preemption point when TIF_NEED_RESCHED gets set while preemption is
- * disabled.
- */
-
-#define _pcp_protect(op, pcp, ...) \
-({ \
- preempt_disable_notrace(); \
- op(raw_cpu_ptr(&(pcp)), __VA_ARGS__); \
- preempt_enable_notrace(); \
-})
-
-#define _pcp_protect_return(op, pcp, args...) \
-({ \
- typeof(pcp) __retval; \
- preempt_disable_notrace(); \
- __retval = (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args); \
- preempt_enable_notrace(); \
- __retval; \
-})
-
#define _pcp_wrap(op, pcp, ...) \
({ \
op(&(pcp), __VA_ARGS__); \
--
2.30.2
^ permalink raw reply related [flat|nested] 22+ messages in thread