* Re: [PATCH 1/1] arm64: dts: rockchip: disable analog audio for rock-5b
From: Pratham Patel @ 2024-03-24 11:43 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh, krzysztof.kozlowski+dt, conor+dt, heiko, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <TbQeSy-AWAKVHo2Alb8hXUvplVNvohDJ2ztRM1x3Fo5PMmGLMsJxtHR-OIms9FlUshfUD9x45EghBCB9gVtcUPlxeMRUJQ_C95DVhu3AJrk=@thefossguy.com>
On Sunday, March 24th, 2024 at 16:51, Pratham Patel <prathampatel@thefossguy.com> wrote:
> On Sunday, March 24th, 2024 at 16:15, Krzysztof Kozlowski krzysztof.kozlowski@linaro.org wrote:
>
> > > + /*
> > > + *analog-sound {
> > > + * compatible = "audio-graph-card";
> > > + * label = "rk3588-es8316";
> >
> > Do not comment out code. Instead disable the nodes and provide
> > appropriate comment describing reason.
>
> I tried changing the status from okay to disabled. That didn't work. The SBC
> still locked up during boot.
I think setting the status to fail should do the trick, instead of setting it to disabled.
Will try that and be back with a v2.
-- Pratham Patel
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^ permalink raw reply
* Re: [PATCH 0/3] Fix EEE support for MT7531 and MT7988 SoC switch
From: Russell King (Oracle) @ 2024-03-24 11:39 UTC (permalink / raw)
To: Arınç ÜNAL
Cc: Florian Fainelli, Daniel Golle, Andrew Lunn, DENG Qingfang,
Sean Wang, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Matthias Brugger,
AngeloGioacchino Del Regno, René van Dorst, SkyLake Huang,
Heiner Kallweit, Bartel Eerdekens, mithat.guner, erkin.bozoglu,
netdev, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <5a4c0436-cd78-419f-af14-9c4e0c0435e3@arinc9.com>
On Sun, Mar 24, 2024 at 12:47:08PM +0300, Arınç ÜNAL wrote:
> On 21/03/2024 18:31, Florian Fainelli wrote:
> > On 3/21/24 09:09, Arınç ÜNAL wrote:
> > > I have started testing MT7531 with EEE enabled and immediately experienced
> > > frames that wouldn't egress the switch or improperly received on the link
> > > partner.
> > >
> > > SoC MAC <-EEE off-> MT7531 P6 MAC (acting as PHY)
> > > MT7531 P0 MAC <-EEE on -> MT7531 P0 PHY
> > > MT7531 P0 PHY <-EEE on -> Computer connected with twisted pair
> >
> > OK, so this is intended to describe that the SoC's Ethernet MAC link to the integrated switch did not use EEE only the user-facing ports. That makes sense because it's all digital logic and you are not going to be seeing much power saving from having EEE enabled between the SoC's Ethernet MAC and CPU port of the switch, that said, however, I wonder if this has an impact on any form of flow control within the switch that is reacting to LPI and you need EEE to be enabled end-to-end?
>
> I've tested pinging between my computers with EEE enabled interfaces. The
> behaviour is identical.
>
> >
> > >
> > > I've tested pinging from the SoC's CPU. Packet capturing on the twisted
> > > pair computer showed very few frames were being received.
> > >
> > > # ping 192.168.2.2
> > > PING 192.168.2.2 (192.168.2.2): 56 data bytes
> > > 64 bytes from 192.168.2.2: seq=36 ttl=64 time=0.486 ms
> > > ^C
> > > --- 192.168.2.2 ping statistics ---
> > > 64 packets transmitted, 1 packets received, 98% packet loss
> > > round-trip min/avg/max = 0.486/0.486/0.486 ms
> > >
> > > It seems there's less loss when frames are passed more frequently.
> >
> > That would point to an issue getting in and out of LPI, do you see these packet losses even with different LPI timeouts?
>
> The NICs on my computers don't seem to allow changing the tx-lpi and
> tx-timer options.
>
> Computer 1 (Intel I219-V, driver: e1000e):
>
> $ sudo ethtool --set-eee eno1 tx-timer 15
> netlink error: Invalid argument
>
> $ sudo ethtool --show-eee eno1
> EEE settings for eno1:
> EEE status: enabled - active
> Tx LPI: 17 (us)
> Supported EEE link modes: 100baseT/Full
> 1000baseT/Full
> Advertised EEE link modes: 100baseT/Full
> 1000baseT/Full
> Link partner advertised EEE link modes: 100baseT/Full
> 1000baseT/Full
>
> Computer 2 (Realtek RTL8111H, driver: r8169):
>
> $ sudo ethtool --set-eee eno1 tx-lpi on
>
> $ sudo ethtool --show-eee eno1
> EEE settings for eno1:
> EEE status: enabled - active
> Tx LPI: disabled
> Supported EEE link modes: 100baseT/Full
> 1000baseT/Full
> Advertised EEE link modes: 100baseT/Full
> 1000baseT/Full
> Link partner advertised EEE link modes: 100baseT/Full
> 1000baseT/Full
>
> I've tested with switch ports interfaces' tx-timer from 0 to 40, same
> tx-timer for both interfaces. Loss is still there.
EEE implementations tend to be a mess in the way drivers implement the
API, so one can't at the moment rely on what ethtool says about the
status. Sadly, this is what happens when driver authors are left to
their own ends. :(
> I suppose the MT7531 switch PHYs need calibration for EEE that is currently
> missing from the mediatek-ge driver.
EEE is quite simple from the software point of view. There is software
negotiation of the modules that EEE supports, and then there is are
one or more timers that affect the behaviour of EEE. The LPI timer is
"how long the link needs to be idle for before _this_ end signals that
it _can_ enter low power state". The link only enters low power state
when *both* ends of the link signal that they can enter low power
state.
What calibration would be necessary?
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
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^ permalink raw reply
* Re: [PATCH 1/1] arm64: dts: rockchip: disable analog audio for rock-5b
From: Pratham Patel @ 2024-03-24 11:21 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: robh, krzysztof.kozlowski+dt, conor+dt, heiko, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <0005257d-8022-4a66-a802-0c920d259ccd@linaro.org>
On Sunday, March 24th, 2024 at 16:15, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
>
>
> On 24/03/2024 07:28, Pratham Patel wrote:
>
> > The addition of `of: property: fw_devlink: Fix stupid bug in remote-endpoint parsing`
>
>
> Please refer to commits using commit sha () syntax, as mentioned in
> submitting patches.
Noticed that in the wiki but didn't do that since the commit hash for the commit
was different in each branch (of the stable tree). Maybe I should have copied the SHA
from Linus' tree. I will do that.
> > + /*
> > + *analog-sound {
> > + * compatible = "audio-graph-card";
> > + * label = "rk3588-es8316";
>
>
> Do not comment out code. Instead disable the nodes and provide
> appropriate comment describing reason.
I tried changing the status from okay to disabled. That didn't work. The SBC
still locked up during boot.
> Anyway, this does not look like correct solution. DTS is independent of
> OS, so bug in fwlink does not matter for DTS. Either DTS is a correct
> hardware representation or not.
I agree, it's not the correct solution. It is a temporary workaround for the regression
caused. I will send more patches once I receive a few more RK3588-based SBCs and investigate.
-- Pratham Patel
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^ permalink raw reply
* Re: [PATCH 1/1] arm64: dts: rockchip: disable analog audio for rock-5b
From: Krzysztof Kozlowski @ 2024-03-24 10:45 UTC (permalink / raw)
To: Pratham Patel, robh
Cc: krzysztof.kozlowski+dt, conor+dt, heiko, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20240324062816.145858-1-prathampatel@thefossguy.com>
On 24/03/2024 07:28, Pratham Patel wrote:
> The addition of `of: property: fw_devlink: Fix stupid bug in remote-endpoint parsing`
Please refer to commits using commit sha () syntax, as mentioned in
submitting patches.
> has surfaced an issue with the analog audio property in the devicetree
> for the rock-5b. Booting kernels v6.7.9+ and v6.8.0+ would cause the
> following call trace:
>
> [ 21.595068] Call trace:
> [ 21.595288] smp_call_function_many_cond+0x174/0x5f8
> [ 21.595728] on_each_cpu_cond_mask+0x2c/0x40
> [ 21.596109] cpuidle_register_driver+0x294/0x318
> [ 21.596524] cpuidle_register+0x24/0x100
> [ 21.596875] psci_cpuidle_probe+0x2e4/0x490
> [ 21.597247] platform_probe+0x70/0xd0
> [ 21.597575] really_probe+0x18c/0x3d8
> [ 21.597905] __driver_probe_device+0x84/0x180
> [ 21.598294] driver_probe_device+0x44/0x120
> [ 21.598669] __device_attach_driver+0xc4/0x168
> [ 21.599063] bus_for_each_drv+0x8c/0xf0
> [ 21.599408] __device_attach+0xa4/0x1c0
> [ 21.599748] device_initial_probe+0x1c/0x30
> [ 21.600118] bus_probe_device+0xb4/0xc0
> [ 21.600462] device_add+0x68c/0x888
> [ 21.600775
> ] platform_device_add+0x19c/0x270
> [ 21.601154] platform_device_register_full+0xdc/0x178
> [ 21.601602] psci_idle_init+0xa0/0xc8
> [ 21.601934] do_one_initcall+0x60/0x290
> [ 21.602275] kernel_init_freeable+0x20c/0x3e0
> [ 21.602664] kernel_init+0x2c/0x1f8
> [ 21.602979] ret_from_fork+0x10/0x20
>
> This is a temporary workaround to at least have the SBC boot. There are
> a few more SBCs that _might_ have this issue. I suspect that the
> rock-5a and nanopc-t6 might also have this issue but I do not own either
> board to verify this claim, yet.
>
> Closes: https://lore.kernel.org/regressions/28S1EMw5YOnQIBpQ8_qaZZ6c9Go-j6-lLuWWbRpe6-MtRUd7Ay-uXq8JHbVVtJv3LzpxjI8jYg7ukNntbN22PVV-hOWbuTY8FNWgvM4zSwI=@thefossguy.com/T/#m69eedea6fbcb0591d54a9ccd478c2782ef045547
>
> Signed-off-by: Pratham Patel <prathampatel@thefossguy.com>
> ---
> .../boot/dts/rockchip/rk3588-rock-5b.dts | 110 +++++++++---------
> 1 file changed, 57 insertions(+), 53 deletions(-)
>
> diff --git a/arch/arm64/boot/d
> ts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> index 1fe8b2a0e..6d3b9f52c 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
> @@ -20,22 +20,24 @@ chosen {
> stdout-path = "serial2:1500000n8";
> };
>
> - analog-sound {
> - compatible = "audio-graph-card";
> - label = "rk3588-es8316";
> -
> - widgets = "Microphone", "Mic Jack",
> - "Headphone", "Headphones";
> -
> - routing = "MIC2", "Mic Jack",
> - "Headphones", "HPOL",
> - "Headphones", "HPOR";
> -
> - dais = <&i2s0_8ch_p0>;
> - hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&hp_detect>;
> - };
> + /*
> + *analog-sound {
> + * compatible = "audio-graph-card";
> + * label = "rk3588-es8316";
Do not comment out code. Instead disable the nodes and provide
appropriate comment describing reason.
Anyway, this does not look like correct solution. DTS is independent of
OS, so bug in fwlink does not matter for DTS. Either DTS is a correct
hardware representation or not.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v5 3/4] firmware: arm_scmi: Add SCMI v3.2 pincontrol protocol basic support
From: Dan Carpenter @ 2024-03-24 10:45 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Oleksii Moisieiev, Linus Walleij, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, linux-arm-kernel, linux-kernel, devicetree,
linux-gpio, AKASHI Takahiro, Peng Fan
In-Reply-To: <7a4a8287-1f86-4ac4-acdf-c02339ba5e1e@moroto.mountain>
On Thu, Mar 21, 2024 at 05:46:53PM +0300, Dan Carpenter wrote:
> On Thu, Mar 14, 2024 at 09:35:20PM +0800, Peng Fan (OSS) wrote:
> > +enum scmi_pinctrl_protocol_cmd {
> > + PINCTRL_ATTRIBUTES = 0x3,
> > + PINCTRL_LIST_ASSOCIATIONS = 0x4,
> > + PINCTRL_CONFIG_GET = 0x5,
> > + PINCTRL_CONFIG_SET = 0x6,
> > + PINCTRL_FUNCTION_SELECT = 0x7,
>
> PINCTRL_FUNCTION_SELECT was removed from the spec so the other cmds were
> renumbered. I'm still going through and reviewing this file. I'll
> hopefully be done tomorrow.
>
I think the rest is okay. It's just updating to the new version of the
spec. CONFIG_GET/SET need to be updated and FUNCTION_SELECT gets
deleted.
regards,
dan carpenter
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^ permalink raw reply
* [PATCH v1] staging: media: remove duplicates
From: coolrrsh @ 2024-03-24 9:29 UTC (permalink / raw)
To: slongerbeam, p.zabel, mchehab, gregkh, shawnguo, s.hauer, kernel,
festevam, linux-imx, linux-media, linux-staging, linux-arm-kernel,
linux-kernel
Cc: linux-kernel-mentees, Rajeshwar R Shinde
From: Rajeshwar R Shinde <coolrrsh@gmail.com>
In Kconfig, the kernel configuration VIDEO_DEV is defined twice.
To prevent doing repeated checks, the redundant code was replaced.
Signed-off-by: Rajeshwar R Shinde <coolrrsh@gmail.com>
---
drivers/staging/media/imx/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/staging/media/imx/Kconfig b/drivers/staging/media/imx/Kconfig
index 21fd79515042..772f49b1fe52 100644
--- a/drivers/staging/media/imx/Kconfig
+++ b/drivers/staging/media/imx/Kconfig
@@ -4,7 +4,6 @@ config VIDEO_IMX_MEDIA
depends on ARCH_MXC || COMPILE_TEST
depends on HAS_DMA
depends on VIDEO_DEV
- depends on VIDEO_DEV
select MEDIA_CONTROLLER
select V4L2_FWNODE
select V4L2_MEM2MEM_DEV
--
2.25.1
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* [PATCH v5 3/4] dt-bindings: clock: add i.MX95 clock header
From: Peng Fan (OSS) @ 2024-03-24 7:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20240324-imx95-blk-ctl-v5-0-7a706174078a@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
Add clock header for i.MX95 BLK CTL modules
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
include/dt-bindings/clock/nxp,imx95-clock.h | 32 +++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h
new file mode 100644
index 000000000000..83fa3ffe78a8
--- /dev/null
+++ b/include/dt-bindings/clock/nxp,imx95-clock.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX95_H
+#define __DT_BINDINGS_CLOCK_IMX95_H
+
+#define IMX95_CLK_VPUBLK_WAVE 0
+#define IMX95_CLK_VPUBLK_JPEG_ENC 1
+#define IMX95_CLK_VPUBLK_JPEG_DEC 2
+#define IMX95_CLK_VPUBLK_END 3
+
+#define IMX95_CLK_CAMBLK_CSI2_FOR0 0
+#define IMX95_CLK_CAMBLK_CSI2_FOR1 1
+#define IMX95_CLK_CAMBLK_ISP_AXI 2
+#define IMX95_CLK_CAMBLK_ISP_PIXEL 3
+#define IMX95_CLK_CAMBLK_ISP 4
+#define IMX95_CLK_CAMBLK_END 5
+
+#define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0
+#define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1
+#define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2
+#define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3
+#define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4
+#define IMX95_CLK_DISPMIX_LVDS_CSR_END 5
+
+#define IMX95_CLK_DISPMIX_ENG0_SEL 0
+#define IMX95_CLK_DISPMIX_ENG1_SEL 1
+#define IMX95_CLK_DISPMIX_END 2
+
+#endif /* __DT_BINDINGS_CLOCK_IMX95_H */
--
2.37.1
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* [PATCH v5 4/4] clk: imx: add i.MX95 BLK CTL clk driver
From: Peng Fan (OSS) @ 2024-03-24 7:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20240324-imx95-blk-ctl-v5-0-7a706174078a@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
i.MX95 has BLK CTL modules in various MIXes, the BLK CTL modules
support clock features such as mux/gate/div. This patch
is to add the clock feature of BLK CTL modules
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/Kconfig | 7 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx95-blk-ctl.c | 438 ++++++++++++++++++++++++++++++++++++
3 files changed, 446 insertions(+)
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index db3bca5f4ec9..6da0fba68225 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -114,6 +114,13 @@ config CLK_IMX93
help
Build the driver for i.MX93 CCM Clock Driver
+config CLK_IMX95_BLK_CTL
+ tristate "IMX95 Clock Driver for BLK CTL"
+ depends on ARCH_MXC || COMPILE_TEST
+ select MXC_CLK
+ help
+ Build the clock driver for i.MX95 BLK CTL
+
config CLK_IMXRT1050
tristate "IMXRT1050 CCM Clock Driver"
depends on SOC_IMXRT || COMPILE_TEST
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index d4b8e10b1970..03f2b2a1ab63 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
+obj-$(CONFIG_CLK_IMX95_BLK_CTL) += clk-imx95-blk-ctl.o
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-acm.o
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
new file mode 100644
index 000000000000..afda463e28b1
--- /dev/null
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/clock/nxp,imx95-clock.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/pm_runtime.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+enum {
+ CLK_GATE,
+ CLK_DIVIDER,
+ CLK_MUX,
+};
+
+struct imx95_blk_ctl {
+ struct device *dev;
+ spinlock_t lock;
+ struct clk *clk_apb;
+
+ void __iomem *base;
+ /* clock gate register */
+ u32 clk_reg_restore;
+};
+
+struct imx95_blk_ctl_clk_dev_data {
+ const char *name;
+ const char * const *parent_names;
+ u32 num_parents;
+ u32 reg;
+ u32 bit_idx;
+ u32 bit_width;
+ u32 clk_type;
+ u32 flags;
+ u32 flags2;
+ u32 type;
+};
+
+struct imx95_blk_ctl_dev_data {
+ const struct imx95_blk_ctl_clk_dev_data *clk_dev_data;
+ u32 num_clks;
+ bool rpm_enabled;
+ u32 clk_reg_offset;
+};
+
+static const struct imx95_blk_ctl_clk_dev_data vpublk_clk_dev_data[] = {
+ [IMX95_CLK_VPUBLK_WAVE] = {
+ .name = "vpublk_wave_vpu",
+ .parent_names = (const char *[]){ "vpu", },
+ .num_parents = 1,
+ .reg = 8,
+ .bit_idx = 0,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_VPUBLK_JPEG_ENC] = {
+ .name = "vpublk_jpeg_enc",
+ .parent_names = (const char *[]){ "vpujpeg", },
+ .num_parents = 1,
+ .reg = 8,
+ .bit_idx = 1,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_VPUBLK_JPEG_DEC] = {
+ .name = "vpublk_jpeg_dec",
+ .parent_names = (const char *[]){ "vpujpeg", },
+ .num_parents = 1,
+ .reg = 8,
+ .bit_idx = 2,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ }
+};
+
+static const struct imx95_blk_ctl_dev_data vpublk_dev_data = {
+ .num_clks = IMX95_CLK_VPUBLK_END,
+ .clk_dev_data = vpublk_clk_dev_data,
+ .rpm_enabled = true,
+ .clk_reg_offset = 8,
+};
+
+static const struct imx95_blk_ctl_clk_dev_data camblk_clk_dev_data[] = {
+ [IMX95_CLK_CAMBLK_CSI2_FOR0] = {
+ .name = "camblk_csi2_for0",
+ .parent_names = (const char *[]){ "camisi", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 0,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_CAMBLK_CSI2_FOR1] = {
+ .name = "camblk_csi2_for1",
+ .parent_names = (const char *[]){ "camisi", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 1,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_CAMBLK_ISP_AXI] = {
+ .name = "camblk_isp_axi",
+ .parent_names = (const char *[]){ "camaxi", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 4,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_CAMBLK_ISP_PIXEL] = {
+ .name = "camblk_isp_pixel",
+ .parent_names = (const char *[]){ "camisi", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 5,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_CAMBLK_ISP] = {
+ .name = "camblk_isp",
+ .parent_names = (const char *[]){ "camisi", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 6,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ }
+};
+
+static const struct imx95_blk_ctl_dev_data camblk_dev_data = {
+ .num_clks = IMX95_CLK_CAMBLK_END,
+ .clk_dev_data = camblk_clk_dev_data,
+ .clk_reg_offset = 0,
+};
+
+static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {
+ [IMX95_CLK_DISPMIX_LVDS_PHY_DIV] = {
+ .name = "ldb_phy_div",
+ .parent_names = (const char *[]){ "ldbpll", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 0,
+ .bit_width = 1,
+ .type = CLK_DIVIDER,
+ .flags2 = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ [IMX95_CLK_DISPMIX_LVDS_CH0_GATE] = {
+ .name = "lvds_ch0_gate",
+ .parent_names = (const char *[]){ "ldb_phy_div", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 1,
+ .bit_width = 1,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_DISPMIX_LVDS_CH1_GATE] = {
+ .name = "lvds_ch1_gate",
+ .parent_names = (const char *[]){ "ldb_phy_div", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 2,
+ .bit_width = 1,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_DISPMIX_PIX_DI0_GATE] = {
+ .name = "lvds_di0_gate",
+ .parent_names = (const char *[]){ "ldb_pll_div7", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 3,
+ .bit_width = 1,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+ [IMX95_CLK_DISPMIX_PIX_DI1_GATE] = {
+ .name = "lvds_di1_gate",
+ .parent_names = (const char *[]){ "ldb_pll_div7", },
+ .num_parents = 1,
+ .reg = 0,
+ .bit_idx = 4,
+ .bit_width = 1,
+ .type = CLK_GATE,
+ .flags = CLK_SET_RATE_PARENT,
+ .flags2 = CLK_GATE_SET_TO_DISABLE,
+ },
+};
+
+static const struct imx95_blk_ctl_dev_data lvds_csr_dev_data = {
+ .num_clks = IMX95_CLK_DISPMIX_LVDS_CSR_END,
+ .clk_dev_data = lvds_clk_dev_data,
+ .clk_reg_offset = 0,
+};
+
+static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
+ [IMX95_CLK_DISPMIX_ENG0_SEL] = {
+ .name = "disp_engine0_sel",
+ .parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", },
+ .num_parents = 4,
+ .reg = 0,
+ .bit_idx = 0,
+ .bit_width = 2,
+ .type = CLK_MUX,
+ .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+ },
+ [IMX95_CLK_DISPMIX_ENG1_SEL] = {
+ .name = "disp_engine1_sel",
+ .parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", },
+ .num_parents = 4,
+ .reg = 0,
+ .bit_idx = 2,
+ .bit_width = 2,
+ .type = CLK_MUX,
+ .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+ }
+};
+
+static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = {
+ .num_clks = IMX95_CLK_DISPMIX_END,
+ .clk_dev_data = dispmix_csr_clk_dev_data,
+ .clk_reg_offset = 0,
+};
+
+static int imx95_bc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct imx95_blk_ctl_dev_data *bc_data;
+ struct imx95_blk_ctl *bc;
+ struct clk_hw_onecell_data *clk_hw_data;
+ struct clk_hw **hws;
+ void __iomem *base;
+ int i, ret;
+
+ bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
+ if (!bc)
+ return -ENOMEM;
+ bc->dev = dev;
+ dev_set_drvdata(&pdev->dev, bc);
+
+ spin_lock_init(&bc->lock);
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ bc->base = base;
+ bc->clk_apb = devm_clk_get(dev, NULL);
+ if (IS_ERR(bc->clk_apb))
+ return dev_err_probe(dev, PTR_ERR(bc->clk_apb), "failed to get APB clock\n");
+
+ ret = clk_prepare_enable(bc->clk_apb);
+ if (ret) {
+ dev_err(dev, "failed to enable apb clock: %d\n", ret);
+ return ret;
+ }
+
+ bc_data = of_device_get_match_data(dev);
+ if (!bc_data)
+ return devm_of_platform_populate(dev);
+
+ clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, bc_data->num_clks),
+ GFP_KERNEL);
+ if (!clk_hw_data)
+ return -ENOMEM;
+
+ if (bc_data->rpm_enabled)
+ pm_runtime_enable(&pdev->dev);
+
+ clk_hw_data->num = bc_data->num_clks;
+ hws = clk_hw_data->hws;
+
+ for (i = 0; i < bc_data->num_clks; i++) {
+ const struct imx95_blk_ctl_clk_dev_data *data = &bc_data->clk_dev_data[i];
+ void __iomem *reg = base + data->reg;
+
+ if (data->type == CLK_MUX) {
+ hws[i] = clk_hw_register_mux(dev, data->name, data->parent_names,
+ data->num_parents, data->flags, reg,
+ data->bit_idx, data->bit_width,
+ data->flags2, &bc->lock);
+ } else if (data->type == CLK_DIVIDER) {
+ hws[i] = clk_hw_register_divider(dev, data->name, data->parent_names[0],
+ data->flags, reg, data->bit_idx,
+ data->bit_width, data->flags2, &bc->lock);
+ } else {
+ hws[i] = clk_hw_register_gate(dev, data->name, data->parent_names[0],
+ data->flags, reg, data->bit_idx,
+ data->flags2, &bc->lock);
+ }
+ if (IS_ERR(hws[i])) {
+ ret = PTR_ERR(hws[i]);
+ dev_err(dev, "failed to register: %s:%d\n", data->name, ret);
+ goto cleanup;
+ }
+ }
+
+ ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_hw_data);
+ if (ret)
+ goto cleanup;
+
+ ret = devm_of_platform_populate(dev);
+ if (ret) {
+ of_clk_del_provider(dev->of_node);
+ goto cleanup;
+ }
+
+ if (pm_runtime_enabled(bc->dev))
+ clk_disable_unprepare(bc->clk_apb);
+
+ return 0;
+
+cleanup:
+ for (i = 0; i < bc_data->num_clks; i++) {
+ if (IS_ERR_OR_NULL(hws[i]))
+ continue;
+ clk_hw_unregister(hws[i]);
+ }
+
+ if (bc_data->rpm_enabled)
+ pm_runtime_disable(&pdev->dev);
+
+ return ret;
+}
+
+#ifdef CONFIG_PM
+static int imx95_bc_runtime_suspend(struct device *dev)
+{
+ struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(bc->clk_apb);
+ return 0;
+}
+
+static int imx95_bc_runtime_resume(struct device *dev)
+{
+ struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
+
+ return clk_prepare_enable(bc->clk_apb);
+}
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static int imx95_bc_suspend(struct device *dev)
+{
+ struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
+ const struct imx95_blk_ctl_dev_data *bc_data;
+ int ret;
+
+ bc_data = of_device_get_match_data(dev);
+ if (!bc_data)
+ return 0;
+
+ if (bc_data->rpm_enabled) {
+ ret = pm_runtime_get_sync(bc->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(bc->dev);
+ return ret;
+ }
+ }
+
+ bc->clk_reg_restore = readl(bc->base + bc_data->clk_reg_offset);
+
+ return 0;
+}
+
+static int imx95_bc_resume(struct device *dev)
+{
+ struct imx95_blk_ctl *bc = dev_get_drvdata(dev);
+ const struct imx95_blk_ctl_dev_data *bc_data;
+
+ bc_data = of_device_get_match_data(dev);
+ if (!bc_data)
+ return 0;
+
+ writel(bc->clk_reg_restore, bc->base + bc_data->clk_reg_offset);
+
+ if (bc_data->rpm_enabled)
+ pm_runtime_put(bc->dev);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops imx95_bc_pm_ops = {
+ SET_RUNTIME_PM_OPS(imx95_bc_runtime_suspend, imx95_bc_runtime_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(imx95_bc_suspend, imx95_bc_resume)
+};
+
+static const struct of_device_id imx95_bc_of_match[] = {
+ { .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
+ { .compatible = "nxp,imx95-display-master-csr", },
+ { .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
+ { .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
+ { .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx95_bc_of_match);
+
+static struct platform_driver imx95_bc_driver = {
+ .probe = imx95_bc_probe,
+ .driver = {
+ .name = "imx95-blk-ctl",
+ .of_match_table = of_match_ptr(imx95_bc_of_match),
+ .pm = &imx95_bc_pm_ops,
+ },
+};
+module_platform_driver(imx95_bc_driver);
+
+MODULE_DESCRIPTION("NXP i.MX95 blk ctl driver");
+MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
+MODULE_LICENSE("GPL");
--
2.37.1
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^ permalink raw reply related
* [PATCH v5 1/4] dt-bindings: clock: support i.MX95 BLK CTL module
From: Peng Fan (OSS) @ 2024-03-24 7:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20240324-imx95-blk-ctl-v5-0-7a706174078a@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
i.MX95 includes BLK CTL module in several MIXes, such as VPU_CSR in
VPUMIX, CAMERA_CSR in CAMERAMIX and etc.
The BLK CTL module is used for various settings of a specific MIX, such
as clock, QoS and etc.
This patch is to add some BLK CTL modules that has clock features.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
.../bindings/clock/nxp,imx95-blk-ctl.yaml | 56 ++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
new file mode 100644
index 000000000000..2dffc02dcd8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nxp,imx95-blk-ctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX95 Block Control
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - nxp,imx95-lvds-csr
+ - nxp,imx95-display-csr
+ - nxp,imx95-camera-csr
+ - nxp,imx95-vpu-csr
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+ description:
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See
+ include/dt-bindings/clock/nxp,imx95-clock.h
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@4c410000 {
+ compatible = "nxp,imx95-vpu-csr", "syscon";
+ reg = <0x4c410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scmi_clk 114>;
+ power-domains = <&scmi_devpd 21>;
+ };
+...
--
2.37.1
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^ permalink raw reply related
* [PATCH v5 2/4] dt-bindings: clock: support i.MX95 Display Master CSR module
From: Peng Fan (OSS) @ 2024-03-24 7:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
In-Reply-To: <20240324-imx95-blk-ctl-v5-0-7a706174078a@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
i.MX95 DISPLAY_MASTER_CSR includes registers to control DSI clock settings,
clock gating, and pixel link select. Add dt-schema for it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
.../clock/nxp,imx95-display-master-csr.yaml | 64 ++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml
new file mode 100644
index 000000000000..07f7412e7658
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX95 Display Master Block Control
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+properties:
+ compatible:
+ items:
+ - const: nxp,imx95-display-master-csr
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+ description:
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See
+ include/dt-bindings/clock/nxp,imx95-clock.h
+
+ mux-controller:
+ type: object
+ $ref: /schemas/mux/reg-mux.yaml
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - mux-controller
+ - power-domains
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@4c410000 {
+ compatible = "nxp,imx95-display-master-csr", "syscon";
+ reg = <0x4c410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scmi_clk 62>;
+ power-domains = <&scmi_devpd 3>;
+
+ mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */
+ idle-states = <0>;
+ };
+ };
+...
--
2.37.1
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^ permalink raw reply related
* [PATCH v5 0/4] Add support i.MX95 BLK CTL module clock features
From: Peng Fan (OSS) @ 2024-03-24 7:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Abel Vesa
Cc: linux-clk, devicetree, imx, linux-arm-kernel, linux-kernel,
Peng Fan
i.MX95's several MIXes has BLK CTL module which could be used for
clk settings, QoS settings, Misc settings for a MIX. This patchset
is to add the clk feature support, including dt-bindings
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Changes in v5:
- Merge bindings except the one has mux-controller
- Separate clock ID headers in a separate patch per Rob's comments
- Link to v4: https://lore.kernel.org/r/20240314-imx95-blk-ctl-v4-0-d23de23b6ff2@nxp.com
Changes in v4:
- Separate binding doc for each modules, I still keep the syscon as node
name, because the module is not just for clock
- Pass dt-schema check
- Update node compatibles
- Link to v3: https://lore.kernel.org/r/20240228-imx95-blk-ctl-v3-0-40ceba01a211@nxp.com
Changes in v3:
- Correct example node compatible string
- Pass "make ARCH=arm64 DT_CHECKER_FLAGS=-m -j32 dt_binding_check"
- Link to v2: https://lore.kernel.org/r/20240228-imx95-blk-ctl-v2-0-ffb7eefb6dcd@nxp.com
Changes in v2:
- Correct example node compatible string
- Link to v1: https://lore.kernel.org/r/20240228-imx95-blk-ctl-v1-0-9b5ae3c14d83@nxp.com
---
Peng Fan (4):
dt-bindings: clock: support i.MX95 BLK CTL module
dt-bindings: clock: support i.MX95 Display Master CSR module
dt-bindings: clock: add i.MX95 clock header
clk: imx: add i.MX95 BLK CTL clk driver
.../bindings/clock/nxp,imx95-blk-ctl.yaml | 56 +++
.../clock/nxp,imx95-display-master-csr.yaml | 64 +++
drivers/clk/imx/Kconfig | 7 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx95-blk-ctl.c | 438 +++++++++++++++++++++
include/dt-bindings/clock/nxp,imx95-clock.h | 32 ++
6 files changed, 598 insertions(+)
---
base-commit: c9c32620af65fee2b1ac8390fe1349b33f9d0888
change-id: 20240228-imx95-blk-ctl-9ef8c1fc4c22
Best regards,
--
Peng Fan <peng.fan@nxp.com>
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^ permalink raw reply
* [PATCH 1/1] arm64: dts: rockchip: disable analog audio for rock-5b
From: Pratham Patel @ 2024-03-24 6:28 UTC (permalink / raw)
To: robh
Cc: krzysztof.kozlowski+dt, conor+dt, heiko, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
[-- Attachment #1.1.1: Type: text/plain, Size: 4719 bytes --]
The addition of `of: property: fw_devlink: Fix stupid bug in remote-endpoint parsing`
has surfaced an issue with the analog audio property in the devicetree
for the rock-5b. Booting kernels v6.7.9+ and v6.8.0+ would cause the
following call trace:
[ 21.595068] Call trace:
[ 21.595288] smp_call_function_many_cond+0x174/0x5f8
[ 21.595728] on_each_cpu_cond_mask+0x2c/0x40
[ 21.596109] cpuidle_register_driver+0x294/0x318
[ 21.596524] cpuidle_register+0x24/0x100
[ 21.596875] psci_cpuidle_probe+0x2e4/0x490
[ 21.597247] platform_probe+0x70/0xd0
[ 21.597575] really_probe+0x18c/0x3d8
[ 21.597905] __driver_probe_device+0x84/0x180
[ 21.598294] driver_probe_device+0x44/0x120
[ 21.598669] __device_attach_driver+0xc4/0x168
[ 21.599063] bus_for_each_drv+0x8c/0xf0
[ 21.599408] __device_attach+0xa4/0x1c0
[ 21.599748] device_initial_probe+0x1c/0x30
[ 21.600118] bus_probe_device+0xb4/0xc0
[ 21.600462] device_add+0x68c/0x888
[ 21.600775
] platform_device_add+0x19c/0x270
[ 21.601154] platform_device_register_full+0xdc/0x178
[ 21.601602] psci_idle_init+0xa0/0xc8
[ 21.601934] do_one_initcall+0x60/0x290
[ 21.602275] kernel_init_freeable+0x20c/0x3e0
[ 21.602664] kernel_init+0x2c/0x1f8
[ 21.602979] ret_from_fork+0x10/0x20
This is a temporary workaround to at least have the SBC boot. There are
a few more SBCs that _might_ have this issue. I suspect that the
rock-5a and nanopc-t6 might also have this issue but I do not own either
board to verify this claim, yet.
Closes: https://lore.kernel.org/regressions/28S1EMw5YOnQIBpQ8_qaZZ6c9Go-j6-lLuWWbRpe6-MtRUd7Ay-uXq8JHbVVtJv3LzpxjI8jYg7ukNntbN22PVV-hOWbuTY8FNWgvM4zSwI=@thefossguy.com/T/#m69eedea6fbcb0591d54a9ccd478c2782ef045547
Signed-off-by: Pratham Patel <prathampatel@thefossguy.com>
---
.../boot/dts/rockchip/rk3588-rock-5b.dts | 110 +++++++++---------
1 file changed, 57 insertions(+), 53 deletions(-)
diff --git a/arch/arm64/boot/d
ts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
index 1fe8b2a0e..6d3b9f52c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
@@ -20,22 +20,24 @@ chosen {
stdout-path = "serial2:1500000n8";
};
- analog-sound {
- compatible = "audio-graph-card";
- label = "rk3588-es8316";
-
- widgets = "Microphone", "Mic Jack",
- "Headphone", "Headphones";
-
- routing = "MIC2", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR";
-
- dais = <&i2s0_8ch_p0>;
- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&hp_detect>;
- };
+ /*
+ *analog-sound {
+ * compatible = "audio-graph-card";
+ * label = "rk3588-es8316";
+ *
+ * widgets = "Microphone", "Mic Jack",
+ * "Headphone", "Headphones";
+ *
+ * routing = "MIC2", "Mic Jack",
+ * "Headphones", "HPOL",
+ * "Headphones", "HPOR";
+ *
+ * dais = <&i2s0_8ch_p0>;
+ * hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ * pinctrl-names = "default";
+ * pinctrl-0 = <&hp_detect>;
+ *};
+ */
leds {
compatible = "gpio-leds";
@@ -236,43 +238,45 @@ hym8563: rtc@51 {
};
};
-&i2c7 {
- status = "okay";
-
- es8316: audio-codec@11 {
- compatible = "everest,es8316";
- reg = <0x11>;
- clocks = <&cru I2S0_8CH_MCLKOUT>;
- clock-names = "mclk";
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
- assigned-clock-rates = <12288000>;
- #sound-dai-cells = <0>;
-
- port {
- es8316_p0_0: endpoint {
- remote-endpoint = <&i2s0_8ch_p0_0>;
- };
- };
- };
-};
-
-&i2s0_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
- &i2s0_mclk
- &i2s0_sclk
- &i2s0_sdi0
- &i2s0_sdo0>;
- status = "okay";
-
- i2s0_8ch_p0: port {
- i2s0_8ch_p0_0: endpoint {
- dai-format = "i2s";
- mclk-fs = <256>;
- remote-endpoint = <&es8316_p0_0>;
- };
- };
-};
+/*
+ *&i2c7 {
+ * status = "okay";
+ *
+ * es8316: audio-codec@11 {
+ * compatible = "everest,es8316";
+ * reg = <0x11>;
+ * clocks = <&cru I2S0_8CH_MCLKOUT>;
+ * clock-names = "mclk";
+ * assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ * assigned-clock-rates = <12288000>;
+ * #sound-dai-cells = <0>;
+ *
+ * port {
+ * es8316_p0_0: endpoint {
+ * remote-endpoint = <&i2s0_8ch_p0_0>;
+ * };
+ * };
+ * };
+ *};
+ *
+ *&i2s0_8ch {
+ * pinctrl-names = "default";
+ * pinctrl-0 = <&i2s0_lrck
+ * &i2s0_mclk
+ * &i2s0_sclk
+ * &i2s0_sdi0
+ * &i2s0_sdo0>;
+ * status = "okay";
+ *
+ * i2s0_8ch_p0: port {
+ * i2s0_8ch_p0_0: endpoint {
+ * dai-format = "i2s";
+ * mclk-fs = <256>;
+ * remote-endpoint = <&es8316_p0_0>;
+ * };
+ * };
+ *};
+ */
&pcie2x1l0 {
pinctrl-names = "default";
--
2.42.0
[-- Attachment #1.1.2: publickey - prathampatel@thefossguy.com - f2dde54d.asc --]
[-- Type: application/pgp-keys, Size: 722 bytes --]
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 249 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply related
* Re: [PATCH 1/4] dt-bindings: rtc: armada-380-rtc: convert to dtschema
From: Javier Carrasco @ 2024-03-24 0:02 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Baruch Siach,
linux-rtc, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20240323233742bfb9ba4a@mail.local>
On 3/24/24 00:37, Alexandre Belloni wrote:
> On 23/03/2024 23:46:13+0100, Javier Carrasco wrote:
>> Convert existing binding to dtschema to support validation.
>>
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - interrupts
>> +
>> +additionalProperties: false
>
> This is not correct because at least start-year is supported. Please
> check for all your other submissions too.
>
allOf:
- $ref: rtc.yaml#
is missing, and then
unvealuatedProperties: false
to account for that.
"start-year" is read in the RTC base class, so I wonder why so many RTC
bindings add a reference to rtc.yaml, but then use
additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + rtc@a3800 {
>> + compatible = "marvell,armada-380-rtc";
>> + reg = <0xa3800 0x20>, <0x184a0 0x0c>;
>> + reg-names = "rtc", "rtc-soc";
>> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>>
>> --
>> 2.40.1
>>
>
Thanks and best regards,
Javier Carrasco
_______________________________________________
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^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: rtc: armada-380-rtc: convert to dtschema
From: Alexandre Belloni @ 2024-03-23 23:37 UTC (permalink / raw)
To: Javier Carrasco
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Baruch Siach,
linux-rtc, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20240323-rtc-yaml-v1-1-0c5d12b1b89d@gmail.com>
On 23/03/2024 23:46:13+0100, Javier Carrasco wrote:
> Convert existing binding to dtschema to support validation.
>
> This is a direct conversion with no additions.
>
> Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
> ---
> .../devicetree/bindings/rtc/armada-380-rtc.txt | 24 -----------
> .../bindings/rtc/marvell,armada-380-rtc.yaml | 48 ++++++++++++++++++++++
> 2 files changed, 48 insertions(+), 24 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
> deleted file mode 100644
> index c3c9a1226f9a..000000000000
> --- a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -* Real Time Clock of the Armada 38x/7K/8K SoCs
> -
> -RTC controller for the Armada 38x, 7K and 8K SoCs
> -
> -Required properties:
> -- compatible : Should be one of the following:
> - "marvell,armada-380-rtc" for Armada 38x SoC
> - "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
> -- reg: a list of base address and size pairs, one for each entry in
> - reg-names
> -- reg names: should contain:
> - * "rtc" for the RTC registers
> - * "rtc-soc" for the SoC related registers and among them the one
> - related to the interrupt.
> -- interrupts: IRQ line for the RTC.
> -
> -Example:
> -
> -rtc@a3800 {
> - compatible = "marvell,armada-380-rtc";
> - reg = <0xa3800 0x20>, <0x184a0 0x0c>;
> - reg-names = "rtc", "rtc-soc";
> - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> -};
> diff --git a/Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml b/Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml
> new file mode 100644
> index 000000000000..388c7d7a044d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/marvell,armada-380-rtc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RTC controller for the Armada 38x, 7K and 8K SoCs
> +
> +maintainers:
> + - Javier Carrasco <javier.carrasco.cruz@gmail.com>
> +
> +properties:
> + compatible:
> + enum:
> + - marvell,armada-380-rtc
> + - marvell,armada-8k-rtc
> +
> + reg:
> + items:
> + - description: RTC base address size
> + - description: Base address and size of SoC related registers
> +
> + reg-names:
> + items:
> + - const: rtc
> + - const: rtc-soc
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> +
> +additionalProperties: false
This is not correct because at least start-year is supported. Please
check for all your other submissions too.
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + rtc@a3800 {
> + compatible = "marvell,armada-380-rtc";
> + reg = <0xa3800 0x20>, <0x184a0 0x0c>;
> + reg-names = "rtc", "rtc-soc";
> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + };
>
> --
> 2.40.1
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* [PATCH v1 3/3] iio: adc: meson: simplify MESON_SAR_ADC_REG11 register access
From: Martin Blumenstingl @ 2024-03-23 23:13 UTC (permalink / raw)
To: linux-amlogic
Cc: linux-arm-kernel, linux-kernel, gnstark, neil.armstrong, lars,
jic23, Martin Blumenstingl
In-Reply-To: <20240323231309.415425-1-martin.blumenstingl@googlemail.com>
Simply check the max_register value to decide whether
MESON_SAR_ADC_REG11 is present on the current IP revision. This allows
dropping two additional bool fields from struct meson_sar_adc_param
which previously had to be manually kept in sync. No functional changes
intended.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/meson_saradc.c | 29 ++++++++---------------------
1 file changed, 8 insertions(+), 21 deletions(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 6b2af0c2bbc7..8c1e542c0ab7 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -320,14 +320,12 @@ static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
struct meson_sar_adc_param {
bool has_bl30_integration;
unsigned long clock_rate;
- u32 bandgap_reg;
unsigned int resolution;
const struct regmap_config *regmap_config;
u8 temperature_trimming_bits;
unsigned int temperature_multiplier;
unsigned int temperature_divider;
bool disable_ring_counter;
- bool has_reg11;
bool has_vref_select;
bool cmv_select;
bool adc_eoc;
@@ -995,7 +993,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
regval);
- if (priv->param->has_reg11) {
+ if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) {
regval = priv->param->adc_eoc ? MESON_SAR_ADC_REG11_EOC : 0;
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_EOC, regval);
@@ -1031,16 +1029,15 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
{
struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
- const struct meson_sar_adc_param *param = priv->param;
- u32 enable_mask;
- if (param->bandgap_reg == MESON_SAR_ADC_REG11)
- enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
+ if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11)
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
+ MESON_SAR_ADC_REG11_BANDGAP_EN,
+ on_off ? MESON_SAR_ADC_REG11_BANDGAP_EN : 0);
else
- enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
-
- regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
- on_off ? enable_mask : 0);
+ regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
+ MESON_SAR_ADC_DELTA_10_TS_VBG_EN,
+ on_off ? MESON_SAR_ADC_DELTA_10_TS_VBG_EN : 0);
}
static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
@@ -1205,7 +1202,6 @@ static const struct iio_info meson_sar_adc_iio_info = {
static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
.has_bl30_integration = false,
.clock_rate = 1150000,
- .bandgap_reg = MESON_SAR_ADC_DELTA_10,
.regmap_config = &meson_sar_adc_regmap_config_meson8,
.resolution = 10,
.temperature_trimming_bits = 4,
@@ -1216,7 +1212,6 @@ static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
.has_bl30_integration = false,
.clock_rate = 1150000,
- .bandgap_reg = MESON_SAR_ADC_DELTA_10,
.regmap_config = &meson_sar_adc_regmap_config_meson8,
.resolution = 10,
.temperature_trimming_bits = 5,
@@ -1227,10 +1222,8 @@ static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
.has_bl30_integration = true,
.clock_rate = 1200000,
- .bandgap_reg = MESON_SAR_ADC_REG11,
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 10,
- .has_reg11 = true,
.vref_voltage = VREF_VOLTAGE_1V8,
.cmv_select = true,
};
@@ -1238,11 +1231,9 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
.has_bl30_integration = true,
.clock_rate = 1200000,
- .bandgap_reg = MESON_SAR_ADC_REG11,
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 12,
.disable_ring_counter = 1,
- .has_reg11 = true,
.vref_voltage = VREF_VOLTAGE_1V8,
.cmv_select = true,
};
@@ -1250,11 +1241,9 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
.has_bl30_integration = true,
.clock_rate = 1200000,
- .bandgap_reg = MESON_SAR_ADC_REG11,
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 12,
.disable_ring_counter = 1,
- .has_reg11 = true,
.vref_voltage = VREF_VOLTAGE_1V8,
.has_vref_select = true,
.vref_select = VREF_VDDA,
@@ -1264,11 +1253,9 @@ static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
.has_bl30_integration = false,
.clock_rate = 1200000,
- .bandgap_reg = MESON_SAR_ADC_REG11,
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 12,
.disable_ring_counter = 1,
- .has_reg11 = true,
.vref_voltage = VREF_VOLTAGE_0V9,
.adc_eoc = true,
.has_vref_select = true,
--
2.44.0
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^ permalink raw reply related
* [PATCH v1 1/3] iio: adc: meson: fix voltage reference selection field name typo
From: Martin Blumenstingl @ 2024-03-23 23:13 UTC (permalink / raw)
To: linux-amlogic
Cc: linux-arm-kernel, linux-kernel, gnstark, neil.armstrong, lars,
jic23, Martin Blumenstingl
In-Reply-To: <20240323231309.415425-1-martin.blumenstingl@googlemail.com>
The field should be called "vref_voltage", without a typo in the word
voltage. No functional changes intended.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/meson_saradc.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 13b473d8c6c7..2615d74534df 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -327,7 +327,7 @@ struct meson_sar_adc_param {
u8 vref_select;
u8 cmv_select;
u8 adc_eoc;
- enum meson_sar_adc_vref_sel vref_volatge;
+ enum meson_sar_adc_vref_sel vref_voltage;
};
struct meson_sar_adc_data {
@@ -1001,7 +1001,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
}
regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE,
- priv->param->vref_volatge);
+ priv->param->vref_voltage);
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);
@@ -1225,7 +1225,7 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 10,
.has_reg11 = true,
- .vref_volatge = 1,
+ .vref_voltage = 1,
.cmv_select = 1,
};
@@ -1237,7 +1237,7 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .vref_volatge = 1,
+ .vref_voltage = 1,
.cmv_select = 1,
};
@@ -1249,7 +1249,7 @@ static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .vref_volatge = 1,
+ .vref_voltage = 1,
.has_vref_select = true,
.vref_select = VREF_VDDA,
.cmv_select = 1,
--
2.44.0
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^ permalink raw reply related
* [PATCH v1 0/3] iio: adc: meson: a few improvements
From: Martin Blumenstingl @ 2024-03-23 23:13 UTC (permalink / raw)
To: linux-amlogic
Cc: linux-arm-kernel, linux-kernel, gnstark, neil.armstrong, lars,
jic23, Martin Blumenstingl
This series contains three improvements to the meson SAR ADC driver.
None of them are meant to change the existing behavior. The goal is
to make the driver code easier to read and understand.
Martin Blumenstingl (3):
iio: adc: meson: fix voltage reference selection field name typo
iio: adc: meson: consistently use bool/enum in struct
meson_sar_adc_param
iio: adc: meson: simplify MESON_SAR_ADC_REG11 register access
drivers/iio/adc/meson_saradc.c | 78 ++++++++++++++++------------------
1 file changed, 36 insertions(+), 42 deletions(-)
--
2.44.0
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* [PATCH v1 2/3] iio: adc: meson: consistently use bool/enum in struct meson_sar_adc_param
From: Martin Blumenstingl @ 2024-03-23 23:13 UTC (permalink / raw)
To: linux-amlogic
Cc: linux-arm-kernel, linux-kernel, gnstark, neil.armstrong, lars,
jic23, Martin Blumenstingl
In-Reply-To: <20240323231309.415425-1-martin.blumenstingl@googlemail.com>
Consistently use bool for any register bit that enables/disables
functionality and enum for register values where there's a choice
between different settings. The aim is to make the code easier to read
and understand by being more consistent. No functional changes intended.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/iio/adc/meson_saradc.c | 47 +++++++++++++++++++---------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 2615d74534df..6b2af0c2bbc7 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -156,9 +156,9 @@
#define MESON_SAR_ADC_REG11 0x2c
#define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
#define MESON_SAR_ADC_REG11_CMV_SEL BIT(6)
- #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5)
- #define MESON_SAR_ADC_REG11_EOC BIT(1)
- #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0)
+ #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5)
+ #define MESON_SAR_ADC_REG11_EOC BIT(1)
+ #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0)
#define MESON_SAR_ADC_REG13 0x34
#define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
@@ -224,6 +224,11 @@ enum meson_sar_adc_vref_sel {
VREF_VDDA = 1,
};
+enum meson_sar_adc_vref_voltage {
+ VREF_VOLTAGE_0V9 = 0,
+ VREF_VOLTAGE_1V8 = 1,
+};
+
enum meson_sar_adc_avg_mode {
NO_AVERAGING = 0x0,
MEAN_AVERAGING = 0x1,
@@ -321,13 +326,13 @@ struct meson_sar_adc_param {
u8 temperature_trimming_bits;
unsigned int temperature_multiplier;
unsigned int temperature_divider;
- u8 disable_ring_counter;
+ bool disable_ring_counter;
bool has_reg11;
bool has_vref_select;
- u8 vref_select;
- u8 cmv_select;
- u8 adc_eoc;
- enum meson_sar_adc_vref_sel vref_voltage;
+ bool cmv_select;
+ bool adc_eoc;
+ enum meson_sar_adc_vref_sel vref_select;
+ enum meson_sar_adc_vref_voltage vref_voltage;
};
struct meson_sar_adc_data {
@@ -982,14 +987,16 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
}
- regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
- priv->param->disable_ring_counter);
+ if (priv->param->disable_ring_counter)
+ regval = MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN;
+ else
+ regval = 0;
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
regval);
if (priv->param->has_reg11) {
- regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);
+ regval = priv->param->adc_eoc ? MESON_SAR_ADC_REG11_EOC : 0;
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_EOC, regval);
@@ -1005,8 +1012,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);
- regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL,
- priv->param->cmv_select);
+ regval = priv->param->cmv_select ? MESON_SAR_ADC_REG11_CMV_SEL : 0;
regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
MESON_SAR_ADC_REG11_CMV_SEL, regval);
}
@@ -1225,8 +1231,8 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
.regmap_config = &meson_sar_adc_regmap_config_gxbb,
.resolution = 10,
.has_reg11 = true,
- .vref_voltage = 1,
- .cmv_select = 1,
+ .vref_voltage = VREF_VOLTAGE_1V8,
+ .cmv_select = true,
};
static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
@@ -1237,8 +1243,8 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .vref_voltage = 1,
- .cmv_select = 1,
+ .vref_voltage = VREF_VOLTAGE_1V8,
+ .cmv_select = true,
};
static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
@@ -1249,10 +1255,10 @@ static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .vref_voltage = 1,
+ .vref_voltage = VREF_VOLTAGE_1V8,
.has_vref_select = true,
.vref_select = VREF_VDDA,
- .cmv_select = 1,
+ .cmv_select = true,
};
static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
@@ -1263,7 +1269,8 @@ static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
.resolution = 12,
.disable_ring_counter = 1,
.has_reg11 = true,
- .adc_eoc = 1,
+ .vref_voltage = VREF_VOLTAGE_0V9,
+ .adc_eoc = true,
.has_vref_select = true,
.vref_select = VREF_VDDA,
};
--
2.44.0
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* [PATCH 4/4] dt-bindings: rtc: nxp,lpc1788-rtc: convert to dtschema
From: Javier Carrasco @ 2024-03-23 22:46 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
In-Reply-To: <20240323-rtc-yaml-v1-0-0c5d12b1b89d@gmail.com>
Convert existing binding to dtschema to support validation.
This is a direct conversion with no additions.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
.../devicetree/bindings/rtc/nxp,lpc1788-rtc.txt | 21 --------
.../devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml | 57 ++++++++++++++++++++++
2 files changed, 57 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt b/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt
deleted file mode 100644
index 3c97bd180592..000000000000
--- a/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-NXP LPC1788 real-time clock
-
-The LPC1788 RTC provides calendar and clock functionality
-together with periodic tick and alarm interrupt support.
-
-Required properties:
-- compatible : must contain "nxp,lpc1788-rtc"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A single interrupt specifier.
-- clocks : Must contain clock specifiers for rtc and register clock
-- clock-names : Must contain "rtc" and "reg"
- See ../clocks/clock-bindings.txt for details.
-
-Example:
-rtc: rtc@40046000 {
- compatible = "nxp,lpc1788-rtc";
- reg = <0x40046000 0x1000>;
- interrupts = <47>;
- clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
- clock-names = "rtc", "reg";
-};
diff --git a/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml b/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml
new file mode 100644
index 000000000000..af157ff24835
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/nxp,lpc1788-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC1788 real-time clock
+
+description:
+ The LPC1788 RTC provides calendar and clock functionality
+ together with periodic tick and alarm interrupt support.
+
+maintainers:
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+properties:
+ compatible:
+ const: nxp,lpc1788-rtc
+
+ reg:
+ description:
+ Base address and length of the register region.
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: RTC clock
+ - description: Register clock
+
+ clock-names:
+ items:
+ - const: rtc
+ - const: reg
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/lpc18xx-ccu.h>
+
+ rtc@40046000 {
+ compatible = "nxp,lpc1788-rtc";
+ reg = <0x40046000 0x1000>;
+ clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
+ clock-names = "rtc", "reg";
+ interrupts = <47>;
+ };
--
2.40.1
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* [PATCH 1/4] dt-bindings: rtc: armada-380-rtc: convert to dtschema
From: Javier Carrasco @ 2024-03-23 22:46 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
In-Reply-To: <20240323-rtc-yaml-v1-0-0c5d12b1b89d@gmail.com>
Convert existing binding to dtschema to support validation.
This is a direct conversion with no additions.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
.../devicetree/bindings/rtc/armada-380-rtc.txt | 24 -----------
.../bindings/rtc/marvell,armada-380-rtc.yaml | 48 ++++++++++++++++++++++
2 files changed, 48 insertions(+), 24 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
deleted file mode 100644
index c3c9a1226f9a..000000000000
--- a/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* Real Time Clock of the Armada 38x/7K/8K SoCs
-
-RTC controller for the Armada 38x, 7K and 8K SoCs
-
-Required properties:
-- compatible : Should be one of the following:
- "marvell,armada-380-rtc" for Armada 38x SoC
- "marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
-- reg: a list of base address and size pairs, one for each entry in
- reg-names
-- reg names: should contain:
- * "rtc" for the RTC registers
- * "rtc-soc" for the SoC related registers and among them the one
- related to the interrupt.
-- interrupts: IRQ line for the RTC.
-
-Example:
-
-rtc@a3800 {
- compatible = "marvell,armada-380-rtc";
- reg = <0xa3800 0x20>, <0x184a0 0x0c>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml b/Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml
new file mode 100644
index 000000000000..388c7d7a044d
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/marvell,armada-380-rtc.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/marvell,armada-380-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RTC controller for the Armada 38x, 7K and 8K SoCs
+
+maintainers:
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - marvell,armada-380-rtc
+ - marvell,armada-8k-rtc
+
+ reg:
+ items:
+ - description: RTC base address size
+ - description: Base address and size of SoC related registers
+
+ reg-names:
+ items:
+ - const: rtc
+ - const: rtc-soc
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rtc@a3800 {
+ compatible = "marvell,armada-380-rtc";
+ reg = <0xa3800 0x20>, <0x184a0 0x0c>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.40.1
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* [PATCH 0/4] dt-bindings: rtc: convert multiple devices to dtschema
From: Javier Carrasco @ 2024-03-23 22:46 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
This series converts the following existing bindings to dtschema:
- armada-380-rtc
- alphascale,asm9260
- digicolor-rtc (renamed to cnxt,cx92755-rtc to match compatible)
- nxp,lpc1788-rtc
All bindings include at least one compatible that is referenced in the
existing dts (arch/arm). Those dts could be tested against the new
bindings.
It might be worth mentioning that the reference to nxp,lpc1788-rtc in
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi also includes another compatible
called nxp,lpc1850-rtc, which is not documented or supported by existing
drivers. That generates a warning when testing against nxp,lpc1788-rtc.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
Javier Carrasco (4):
dt-bindings: rtc: armada-380-rtc: convert to dtschema
dt-bindings: rtc: alphascale,asm9260: convert to dtschema
dt-bindings: rtc: digicolor-rtc: convert to dtschema
dt-bindings: rtc: nxp,lpc1788-rtc: convert to dtschema
.../bindings/rtc/alphascale,asm9260-rtc.txt | 19 --------
.../bindings/rtc/alphascale,asm9260-rtc.yaml | 49 +++++++++++++++++++
.../devicetree/bindings/rtc/armada-380-rtc.txt | 24 ---------
.../devicetree/bindings/rtc/cnxt,cx92755-rtc.yaml | 37 ++++++++++++++
.../devicetree/bindings/rtc/digicolor-rtc.txt | 17 -------
.../bindings/rtc/marvell,armada-380-rtc.yaml | 48 ++++++++++++++++++
.../devicetree/bindings/rtc/nxp,lpc1788-rtc.txt | 21 --------
.../devicetree/bindings/rtc/nxp,lpc1788-rtc.yaml | 57 ++++++++++++++++++++++
8 files changed, 191 insertions(+), 81 deletions(-)
---
base-commit: 70293240c5ce675a67bfc48f419b093023b862b3
change-id: 20240322-rtc-yaml-473335cbf911
Best regards,
--
Javier Carrasco <javier.carrasco.cruz@gmail.com>
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* [PATCH 3/4] dt-bindings: rtc: digicolor-rtc: convert to dtschema
From: Javier Carrasco @ 2024-03-23 22:46 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
In-Reply-To: <20240323-rtc-yaml-v1-0-0c5d12b1b89d@gmail.com>
Convert existing binding to dtschema to support validation.
The binding has been renamed to match its compatible. Apart from that,
it is a direct conversion with no additions.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
.../devicetree/bindings/rtc/cnxt,cx92755-rtc.yaml | 37 ++++++++++++++++++++++
.../devicetree/bindings/rtc/digicolor-rtc.txt | 17 ----------
2 files changed, 37 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/cnxt,cx92755-rtc.yaml b/Documentation/devicetree/bindings/rtc/cnxt,cx92755-rtc.yaml
new file mode 100644
index 000000000000..bdd6f0718b0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/cnxt,cx92755-rtc.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/cnxt,cx92755-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Conexant Digicolor Real Time Clock Controller
+
+maintainers:
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+properties:
+ compatible:
+ const: cnxt,cx92755-rtc
+
+ reg:
+ description:
+ Base address and length of the register region.
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ rtc@f0000c30 {
+ compatible = "cnxt,cx92755-rtc";
+ reg = <0xf0000c30 0x18>;
+ interrupts = <25>;
+ };
diff --git a/Documentation/devicetree/bindings/rtc/digicolor-rtc.txt b/Documentation/devicetree/bindings/rtc/digicolor-rtc.txt
deleted file mode 100644
index d464986012cd..000000000000
--- a/Documentation/devicetree/bindings/rtc/digicolor-rtc.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Conexant Digicolor Real Time Clock controller
-
-This binding currently supports the CX92755 SoC.
-
-Required properties:
-- compatible: should be "cnxt,cx92755-rtc"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- interrupts: rtc alarm interrupt
-
-Example:
-
- rtc@f0000c30 {
- compatible = "cnxt,cx92755-rtc";
- reg = <0xf0000c30 0x18>;
- interrupts = <25>;
- };
--
2.40.1
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* [PATCH 2/4] dt-bindings: rtc: alphascale,asm9260: convert to dtschema
From: Javier Carrasco @ 2024-03-23 22:46 UTC (permalink / raw)
To: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Baruch Siach
Cc: linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
Javier Carrasco
In-Reply-To: <20240323-rtc-yaml-v1-0-0c5d12b1b89d@gmail.com>
Convert existing binding to dtschema to support validation.
This is a direct conversion with no additions.
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
---
.../bindings/rtc/alphascale,asm9260-rtc.txt | 19 ---------
.../bindings/rtc/alphascale,asm9260-rtc.yaml | 49 ++++++++++++++++++++++
2 files changed, 49 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt b/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt
deleted file mode 100644
index 76ebca568db9..000000000000
--- a/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* Alphascale asm9260 SoC Real Time Clock
-
-Required properties:
-- compatible: Should be "alphascale,asm9260-rtc"
-- reg: Physical base address of the controller and length
- of memory mapped region.
-- interrupts: IRQ line for the RTC.
-- clocks: Reference to the clock entry.
-- clock-names: should contain:
- * "ahb" for the SoC RTC clock
-
-Example:
-rtc0: rtc@800a0000 {
- compatible = "alphascale,asm9260-rtc";
- reg = <0x800a0000 0x100>;
- clocks = <&acc CLKID_AHB_RTC>;
- clock-names = "ahb";
- interrupts = <2>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.yaml b/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.yaml
new file mode 100644
index 000000000000..f949634ef56b
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/alphascale,asm9260-rtc.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/alphascale,asm9260-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Alphascale asm9260 SoC Real Time Clock
+
+maintainers:
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+properties:
+ compatible:
+ const: alphascale,asm9260-rtc
+
+ reg:
+ description:
+ Base address and length of the register region.
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ahb
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/alphascale,asm9260.h>
+
+ rtc@800a0000 {
+ compatible = "alphascale,asm9260-rtc";
+ reg = <0x800a0000 0x100>;
+ clocks = <&acc CLKID_AHB_RTC>;
+ clock-names = "ahb";
+ interrupts = <2>;
+ };
--
2.40.1
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* Re: [WIP 0/3] Memory model and atomic API in Rust
From: comex @ 2024-03-23 21:40 UTC (permalink / raw)
To: Linus Torvalds
Cc: Kent Overstreet, Boqun Feng, rust-for-linux, linux-kernel,
linux-arch, llvm, Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho,
Gary Guo, Björn Roy Baron, Benno Lossin, Andreas Hindborg,
Alice Ryhl, Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, linux-arm-kernel, linux-fsdevel
In-Reply-To: <CAHk-=whY5A=S=bLwCFL=043DoR0TTgSDUmfPDx2rXhkk3KANPQ@mail.gmail.com>
> On Mar 22, 2024, at 8:12 PM, Linus Torvalds <torvalds@linux-foundation.org> wrote:
>
> And when the compiler itself is fundamentally buggy, you're kind of
> screwed. When you roll your own, you can work around the bugs in
> compilers.
That may be true, but the LLVM issue you cited isn’t a good example. In that issue, the function being miscompiled doesn’t actually use any barriers or atomics itself; only the scaffolding around it does. The same issue would happen even if the scaffolding used LKMM atomics.
For anyone curious: The problematic optimization involves an allocation (‘p’) that is initially private to the function, but is returned at the end of the function. LLVM moves a non-atomic store to that allocation across an external function call (to ‘foo’). This reordering would be blatantly invalid if any other code could observe the contents of the allocation, but is valid if the allocation is private to the function. LLVM assumes the latter: after all, the pointer to it hasn’t escaped. Yet. Except that in a weak memory model, the escape can ‘time travel’...
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* Re: [PATCH v3 1/5] dt-bindings: mfd: Add rk816 binding
From: Alex Bee @ 2024-03-23 21:17 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lee Jones, Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio, Rob Herring,
Conor Dooley, Heiko Stuebner, Linus Walleij, Liam Girdwood,
Mark Brown
In-Reply-To: <368eb339-4f0f-4471-9367-9263caa3fab7@linaro.org>
Am 23.03.24 um 15:32 schrieb Krzysztof Kozlowski:
> On 23/03/2024 14:27, Alex Bee wrote:
>> Add DT binding document for Rockchip's RK816 PMIC
>>
>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>
>> + regulators:
>> + type: object
>> + patternProperties:
>> + '^(boost|dcdc[1-4]|ldo[1-6]|otg-switch)$':
>> + type: object
>> + $ref: /schemas/regulator/regulator.yaml#
>> + unevaluatedProperties: false
> This is good.
>
>> + unevaluatedProperties: false
> I missed it last time, apologies. This (second) unevaluated should be
> "additionalProperties: false" instead.
Alright. Since there are no driver changes required for this change, I'll
give the other maintainers some time to review and fix it alongside in v4.
Alex
> With this fixed:
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
>
> Best regards,
> Krzysztof
>
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