* Re: [PATCH v2 6/7] media: dt-bindings: add NXP i.MX95 compatible string
From: Frank Li @ 2026-04-24 4:05 UTC (permalink / raw)
To: Guoniu Zhou
Cc: Michael Riesch, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, Sakari Ailus, Bryan O'Donoghue, Mehdi Djait,
Hans Verkuil, linux-media, linux-kernel, devicetree, imx,
linux-arm-kernel, linux-rockchip
In-Reply-To: <20260423-csi2_imx95-v2-6-934c02f3422a@oss.nxp.com>
On Thu, Apr 23, 2026 at 04:23:01PM +0800, Guoniu Zhou wrote:
> The i.MX95 CSI-2 controller is nearly identical to i.MX93, with the
> main difference being the data output interface:
>
> i.MX93 use IPI (Image Pixel Interface), which requires:
> - Pixel clock input
> - Software configuration through registers
>
> i.MX95 uses IDI (Image Data Interface), which:
> - Does not require pixel clock
> - Is software transparent (no register configuration needed)
Nit: Remove "Is", just "Software ... "
>
> Due to these differences in register layout and initialization needs,
> the two variants cannot share the same compatible string. The driver
> needs to distinguish between them to handle the interface correctly.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes in v2:
> - Add dedicated constraint block for i.MX95 to reflect different clock
> requirements (only per clock needed vs i.MX93 which needs both per
> and pixel clocks)
> - Update commit message to include more details about interface differences
> ---
> .../bindings/media/rockchip,rk3568-mipi-csi2.yaml | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml
> index 4ac4a3b6f406..4e0bc75c2136 100644
> --- a/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml
> @@ -18,6 +18,7 @@ properties:
> compatible:
> enum:
> - fsl,imx93-mipi-csi2
> + - fsl,imx95-mipi-csi2
> - rockchip,rk3568-mipi-csi2
>
> reg:
> @@ -135,6 +136,21 @@ allOf:
> clock-names:
> minItems: 2
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,imx95-mipi-csi2
> + then:
> + properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names: false
> + clocks:
> + maxItems: 1
> + clock-names:
> + maxItems: 1
> +
> examples:
> - |
> #include <dt-bindings/clock/rk3568-cru.h>
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v2 5/7] media: synopsys: Add PHY stopstate wait for i.MX93
From: Frank Li @ 2026-04-24 4:02 UTC (permalink / raw)
To: Guoniu Zhou
Cc: Michael Riesch, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, Sakari Ailus, Bryan O'Donoghue, Mehdi Djait,
Hans Verkuil, linux-media, linux-kernel, devicetree, imx,
linux-arm-kernel, linux-rockchip
In-Reply-To: <20260423-csi2_imx95-v2-5-934c02f3422a@oss.nxp.com>
On Thu, Apr 23, 2026 at 04:23:00PM +0800, Guoniu Zhou wrote:
> Implement waiting for D-PHY lanes to enter stop state on i.MX93. This
> ensures proper PHY initialization by verifying that the clock lane and
> all active data lanes have entered the stop state before proceeding with
> further operations.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes in v2:
> - Removes redundant register availability check
> - Uses read_poll_timeout() with dw_mipi_csi2rx_read() instead of
> readl_poll_timeout() with direct register address
> - Fixes stopstate condition logic
> - Check PHY stopstate after sensor enable instead of before to ensure
> correct timing.
> - Optimize PHY stopstate polling parameters (1000us->10us, 2s->1ms) to
> balance performance and responsiveness.
> ---
> drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 36 ++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> index 5a2e74d055c0..8c38fe8a3f06 100644
> --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> @@ -11,6 +11,7 @@
> #include <linux/clk.h>
> #include <linux/delay.h>
> #include <linux/io.h>
> +#include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/phy/phy.h>
> @@ -35,6 +36,8 @@
> #define DW_REG_EXIST BIT(31)
> #define DW_REG(x) (DW_REG_EXIST | (x))
>
> +#define DPHY_STOPSTATE_CLK_LANE BIT(16)
> +
> #define DPHY_TEST_CTRL0_TEST_CLR BIT(0)
>
> #define IPI_VCID_VC(x) FIELD_PREP(GENMASK(1, 0), (x))
> @@ -65,6 +68,7 @@ enum dw_mipi_csi2rx_regs_index {
> DW_MIPI_CSI2RX_PHY_TST_CTRL0,
> DW_MIPI_CSI2RX_PHY_TST_CTRL1,
> DW_MIPI_CSI2RX_PHY_SHUTDOWNZ,
> + DW_MIPI_CSI2RX_PHY_STOPSTATE,
> DW_MIPI_CSI2RX_IPI_DATATYPE,
> DW_MIPI_CSI2RX_IPI_MEM_FLUSH,
> DW_MIPI_CSI2RX_IPI_MODE,
> @@ -87,6 +91,7 @@ struct dw_mipi_csi2rx_drvdata {
> void (*dphy_assert_reset)(struct dw_mipi_csi2rx_device *csi2);
> void (*dphy_deassert_reset)(struct dw_mipi_csi2rx_device *csi2);
> void (*ipi_enable)(struct dw_mipi_csi2rx_device *csi2);
> + int (*wait_for_phy_stopstate)(struct dw_mipi_csi2rx_device *csi2);
> };
>
> struct dw_mipi_csi2rx_format {
> @@ -139,6 +144,7 @@ static const u32 imx93_regs[DW_MIPI_CSI2RX_MAX] = {
> [DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] = DW_REG(0x40),
> [DW_MIPI_CSI2RX_DPHY_RSTZ] = DW_REG(0x44),
> [DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x48),
> + [DW_MIPI_CSI2RX_PHY_STOPSTATE] = DW_REG(0x4c),
> [DW_MIPI_CSI2RX_PHY_TST_CTRL0] = DW_REG(0x50),
> [DW_MIPI_CSI2RX_PHY_TST_CTRL1] = DW_REG(0x54),
> [DW_MIPI_CSI2RX_IPI_MODE] = DW_REG(0x80),
> @@ -550,10 +556,19 @@ static int dw_mipi_csi2rx_enable_streams(struct v4l2_subdev *sd,
> if (ret)
> goto err_csi_stop;
>
> + if (!csi2->enabled_streams &&
> + csi2->drvdata->wait_for_phy_stopstate) {
> + ret = csi2->drvdata->wait_for_phy_stopstate(csi2);
> + if (ret)
> + goto err_disable_streams;
> + }
> +
> csi2->enabled_streams |= streams_mask;
>
> return 0;
>
> +err_disable_streams:
> + v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask);
> err_csi_stop:
> /* Stop CSI hardware if no streams are enabled */
> if (!csi2->enabled_streams)
> @@ -864,11 +879,32 @@ static void imx93_csi2rx_dphy_ipi_enable(struct dw_mipi_csi2rx_device *csi2)
> dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MODE, val);
> }
>
> +static int imx93_csi2rx_wait_for_phy_stopstate(struct dw_mipi_csi2rx_device *csi2)
> +{
> + struct device *dev = csi2->dev;
> + u32 stopstate_mask;
> + u32 val;
> + int ret;
> +
> + stopstate_mask = DPHY_STOPSTATE_CLK_LANE | GENMASK(csi2->lanes_num - 1, 0);
> +
> + ret = read_poll_timeout(dw_mipi_csi2rx_read, val,
> + (val & stopstate_mask) == stopstate_mask,
> + 10, 1000, true,
> + csi2, DW_MIPI_CSI2RX_PHY_STOPSTATE);
> + if (ret)
> + dev_err(dev, "lanes are not in stop state: %#x, expected %#x\n",
> + val, stopstate_mask);
> +
> + return ret;
> +}
> +
> static const struct dw_mipi_csi2rx_drvdata imx93_drvdata = {
> .regs = imx93_regs,
> .dphy_assert_reset = imx93_csi2rx_dphy_assert_reset,
> .dphy_deassert_reset = imx93_csi2rx_dphy_deassert_reset,
> .ipi_enable = imx93_csi2rx_dphy_ipi_enable,
> + .wait_for_phy_stopstate = imx93_csi2rx_wait_for_phy_stopstate,
> };
>
> static const struct of_device_id dw_mipi_csi2rx_of_match[] = {
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v2 4/7] media: synopsys: Add support for multiple streams
From: Frank Li @ 2026-04-24 4:01 UTC (permalink / raw)
To: Guoniu Zhou
Cc: Michael Riesch, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, Sakari Ailus, Bryan O'Donoghue, Mehdi Djait,
Hans Verkuil, linux-media, linux-kernel, devicetree, imx,
linux-arm-kernel, linux-rockchip
In-Reply-To: <20260423-csi2_imx95-v2-4-934c02f3422a@oss.nxp.com>
On Thu, Apr 23, 2026 at 04:22:59PM +0800, Guoniu Zhou wrote:
> The current driver only supports single stream operation. Add support
> for multiple concurrent streams by tracking enabled streams with a
> bitmask and only initializing the hardware once for the first stream.
>
> This enables use cases such as surround view systems where multiple
> camera streams need to be processed simultaneously through the same
> CSI-2 receiver interface.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes in v2:
> - Simplify error handling by keeping goto labels instead of early returns
> ---
> drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 24 ++++++++++++++++++------
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> index d572d2eb3bcb..5a2e74d055c0 100644
> --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> @@ -113,6 +113,7 @@ struct dw_mipi_csi2rx_device {
>
> enum v4l2_mbus_type bus_type;
> u32 lanes_num;
> + u64 enabled_streams;
>
> const struct dw_mipi_csi2rx_drvdata *drvdata;
> };
> @@ -537,20 +538,26 @@ static int dw_mipi_csi2rx_enable_streams(struct v4l2_subdev *sd,
> if (ret)
> goto err;
>
> - ret = dw_mipi_csi2rx_start(csi2);
> - if (ret) {
> - dev_err(dev, "failed to enable CSI hardware\n");
> - goto err_pm_runtime_put;
> + if (!csi2->enabled_streams) {
> + ret = dw_mipi_csi2rx_start(csi2);
> + if (ret) {
> + dev_err(dev, "failed to enable CSI hardware\n");
> + goto err_pm_runtime_put;
> + }
> }
>
> ret = v4l2_subdev_enable_streams(remote_sd, remote_pad->index, mask);
> if (ret)
> goto err_csi_stop;
>
> + csi2->enabled_streams |= streams_mask;
> +
> return 0;
>
> err_csi_stop:
> - dw_mipi_csi2rx_stop(csi2);
> + /* Stop CSI hardware if no streams are enabled */
> + if (!csi2->enabled_streams)
> + dw_mipi_csi2rx_stop(csi2);
> err_pm_runtime_put:
> pm_runtime_put(dev);
> err:
> @@ -577,11 +584,16 @@ static int dw_mipi_csi2rx_disable_streams(struct v4l2_subdev *sd,
> &streams_mask);
>
> ret = v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask);
> + if (ret)
> + dev_err(dev, "failed to disable streams on remote subdev: %d\n", ret);
>
> - dw_mipi_csi2rx_stop(csi2);
> + csi2->enabled_streams &= ~streams_mask;
>
> pm_runtime_put(dev);
>
> + if (!csi2->enabled_streams)
> + dw_mipi_csi2rx_stop(csi2);
> +
> return ret;
> }
>
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v2 3/7] media: synopsys: Add support for RAW16 Bayer formats
From: Frank Li @ 2026-04-24 3:59 UTC (permalink / raw)
To: Guoniu Zhou
Cc: Michael Riesch, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, Sakari Ailus, Bryan O'Donoghue, Mehdi Djait,
Hans Verkuil, linux-media, linux-kernel, devicetree, imx,
linux-arm-kernel, linux-rockchip
In-Reply-To: <20260423-csi2_imx95-v2-3-934c02f3422a@oss.nxp.com>
On Thu, Apr 23, 2026 at 04:22:58PM +0800, Guoniu Zhou wrote:
> Add higher bit-depth raw image data support for the sensors, which supports
> 16-bit output.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes in v2:
> - Update commit message
> ---
> drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> index b3f90da8b43c..d572d2eb3bcb 100644
> --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> @@ -252,6 +252,26 @@ static const struct dw_mipi_csi2rx_format formats[] = {
> .depth = 12,
> .csi_dt = MIPI_CSI2_DT_RAW12,
> },
> + {
> + .code = MEDIA_BUS_FMT_SBGGR16_1X16,
> + .depth = 16,
> + .csi_dt = MIPI_CSI2_DT_RAW16,
> + },
> + {
> + .code = MEDIA_BUS_FMT_SGBRG16_1X16,
> + .depth = 16,
> + .csi_dt = MIPI_CSI2_DT_RAW16,
> + },
> + {
> + .code = MEDIA_BUS_FMT_SGRBG16_1X16,
> + .depth = 16,
> + .csi_dt = MIPI_CSI2_DT_RAW16,
> + },
> + {
> + .code = MEDIA_BUS_FMT_SRGGB16_1X16,
> + .depth = 16,
> + .csi_dt = MIPI_CSI2_DT_RAW16,
> + },
> };
>
> static inline struct dw_mipi_csi2rx_device *to_csi2(struct v4l2_subdev *sd)
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v2 2/7] media: synopsys: Fix IPI using hardcoded datatype
From: Frank Li @ 2026-04-24 3:58 UTC (permalink / raw)
To: Guoniu Zhou
Cc: Michael Riesch, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, Sakari Ailus, Bryan O'Donoghue, Mehdi Djait,
Hans Verkuil, linux-media, linux-kernel, devicetree, imx,
linux-arm-kernel, linux-rockchip
In-Reply-To: <20260423-csi2_imx95-v2-2-934c02f3422a@oss.nxp.com>
On Thu, Apr 23, 2026 at 04:22:57PM +0800, Guoniu Zhou wrote:
> The imx93_csi2rx_dphy_ipi_enable() function configures the IPI datatype
> using csi2->formats->csi_dt, which is initialized during probe but never
> updated in set_fmt(). This causes the IPI to always use the probe-time
> default datatype, ignoring the actual media bus format negotiated at
> runtime. When userspace requests a different format, the IPI hardware is
> configured with the wrong datatype, resulting in incorrect image output.
>
> Fix by updating csi2->formats in the set_fmt callback to reflect the
> currently negotiated format, ensuring the IPI configuration matches the
> runtime datatype.
>
> Fixes: ec40b431f0ab ("media: synopsys: csi2rx: add i.MX93 support")
> Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes in v2:
> - New added in v2
> ---
> drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> index 02eb4a6cafad..b3f90da8b43c 100644
> --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> @@ -470,6 +470,11 @@ static int dw_mipi_csi2rx_set_fmt(struct v4l2_subdev *sd,
>
> *src = *sink;
>
> + /* Store the CSIS format descriptor for active formats. */
> + if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
> + csi2->formats = fmt ? :
> + dw_mipi_csi2rx_find_format(csi2, default_format.code);
> +
> return 0;
> }
>
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v2 1/7] media: synopsys: Fix out-of-bounds check in enum_mbus_code
From: Frank Li @ 2026-04-24 3:57 UTC (permalink / raw)
To: Guoniu Zhou
Cc: Michael Riesch, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Laurent Pinchart, Sakari Ailus, Bryan O'Donoghue, Mehdi Djait,
Hans Verkuil, linux-media, linux-kernel, devicetree, imx,
linux-arm-kernel, linux-rockchip
In-Reply-To: <20260423-csi2_imx95-v2-1-934c02f3422a@oss.nxp.com>
On Thu, Apr 23, 2026 at 04:22:56PM +0800, Guoniu Zhou wrote:
> dw_mipi_csi2rx_enum_mbus_code() contains an off-by-one error in the
> bounds check for code->index, allowing an access past the end of the
> formats array.
>
> Fixes: 355a11004066 ("media: synopsys: add driver for the designware mipi csi-2 receiver")
> Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes in v2:
> - New added in v2
> ---
> drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> index ce17f986279e..02eb4a6cafad 100644
> --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> @@ -430,7 +430,7 @@ dw_mipi_csi2rx_enum_mbus_code(struct v4l2_subdev *sd,
>
> return 0;
> case DW_MIPI_CSI2RX_PAD_SINK:
> - if (code->index > csi2->formats_num)
> + if (code->index >= csi2->formats_num)
> return -EINVAL;
>
> code->code = csi2->formats[code->index].code;
>
> --
> 2.34.1
>
^ permalink raw reply
* Re: [PATCH v1 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts
From: Frank Li @ 2026-04-24 3:45 UTC (permalink / raw)
To: Richard Zhu
Cc: robh, krzk+dt, conor+dt, bhelgaas, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam, linux-pci,
linux-arm-kernel, devicetree, imx, linux-kernel
In-Reply-To: <20260424025735.1490772-2-hongxing.zhu@nxp.com>
On Fri, Apr 24, 2026 at 10:57:33AM +0800, Richard Zhu wrote:
> Add optional 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q
> PCIe binding to support PCIe event-based interrupts for general
> controller events, Advanced Error Reporting, and Power Management Events
> respectively.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index 9d1349855b422..badc7fcbd556c 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -58,12 +58,18 @@ properties:
> items:
> - description: builtin MSI controller.
> - description: builtin DMA controller.
> + - description: PCIe event interrupt.
> + - description: builtin AER SPI standalone interrupter line.
> + - description: builtin PME SPI standalone interrupter line.
>
> interrupt-names:
> minItems: 1
> items:
> - const: msi
> - const: dma
> + - const: intr
> + - const: aer
> + - const: pme
>
> reset-gpio:
> description: Should specify the GPIO for controlling the PCI bus device
> --
> 2.37.1
>
^ permalink raw reply
* Re: [PATCH v3 05/11] iommu: Change group->devices to RCU-protected list
From: Nicolin Chen @ 2026-04-24 3:08 UTC (permalink / raw)
To: Baolu Lu
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Bjorn Helgaas,
Jason Gunthorpe, Rafael J . Wysocki, Len Brown,
Pranjal Shrivastava, Mostafa Saleh, Kevin Tian, linux-arm-kernel,
iommu, linux-kernel, linux-acpi, linux-pci, vsethi, Shuai Xue
In-Reply-To: <779dad61-d7e7-4ae0-83a9-8c5920222219@linux.intel.com>
On Fri, Apr 24, 2026 at 10:53:49AM +0800, Baolu Lu wrote:
> On 4/17/26 07:28, Nicolin Chen wrote:
> mutex_unlock(&group->mutex);
> /*
> * FIXME: Mis-locked because the ops->probe_finalize() call-back
> * of some IOMMU drivers calls arm_iommu_attach_device() which
> * in-turn might call back into IOMMU core code, where it tries
> * to take group->mutex, resulting in a deadlock.
> */
> for_each_group_device(group, gdev)
> iommu_group_do_probe_finalize(gdev->dev);
> }
>
> return 0;
> }
>
> Will the change above trigger a lockdep splat due to this "mis-locked"
> case?"
Oh, I missed this one. That's a good finding!
Perhaps we can just change it to list_for_each_entry_rcu holding
rcu_read_lock() and drop the FIXME.
Thanks!
Nicolin
^ permalink raw reply
* [PATCH v9 9/9] media: mediatek: encoder: Add MT8189 encoder compatible data
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou
In-Reply-To: <20260424030527.10656-1-kyrie.wu@mediatek.com>
add MT8189 compatible data to initialize platform data for encoder.
Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
index d7328d013ff6..f3e1b121e3d8 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c
@@ -478,6 +478,19 @@ static const struct mtk_vcodec_enc_pdata mt8196_pdata = {
.set_dma_bit_mask = true,
};
+static const struct mtk_vcodec_enc_pdata mt8189_pdata = {
+ .venc_model_num = 8189,
+ .capture_formats = mtk_video_formats_capture_h264,
+ .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_h264),
+ .output_formats = mtk_video_formats_output,
+ .num_output_formats = ARRAY_SIZE(mtk_video_formats_output),
+ .min_bitrate = 64,
+ .max_bitrate = 100000000,
+ .core_id = VENC_SYS,
+ .uses_common_fw_iface = true,
+ .set_dma_bit_mask = true,
+};
+
static const struct of_device_id mtk_vcodec_enc_match[] = {
{.compatible = "mediatek,mt8173-vcodec-enc",
.data = &mt8173_avc_pdata},
@@ -488,6 +501,7 @@ static const struct of_device_id mtk_vcodec_enc_match[] = {
{.compatible = "mediatek,mt8192-vcodec-enc", .data = &mt8192_pdata},
{.compatible = "mediatek,mt8195-vcodec-enc", .data = &mt8195_pdata},
{.compatible = "mediatek,mt8196-vcodec-enc", .data = &mt8196_pdata},
+ {.compatible = "mediatek,mt8189-vcodec-enc", .data = &mt8189_pdata},
{},
};
MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match);
--
2.45.2
^ permalink raw reply related
* [PATCH v9 6/9] media: mediatek: vcodec: add decoder compatible to support MT8189
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou
In-Reply-To: <20260424030527.10656-1-kyrie.wu@mediatek.com>
MT8189 is pure single core architecture. Add its compatible to
initialize platform data.
Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 1 +
.../vcodec/decoder/mtk_vcodec_dec_drv.c | 4 ++++
.../vcodec/decoder/mtk_vcodec_dec_stateless.c | 19 +++++++++++++++++++
3 files changed, 24 insertions(+)
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h
index 80cb46f1cded..2bde871c0224 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h
@@ -71,6 +71,7 @@ extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata;
extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata;
extern const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata;
extern const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata;
+extern const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdata;
extern const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata;
extern const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata;
extern const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata;
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
index 6ebd82ba8d23..dc67c2b84776 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
@@ -555,6 +555,10 @@ static const struct of_device_id mtk_vcodec_match[] = {
.compatible = "mediatek,mt8196-vcodec-dec",
.data = &mtk_vdec_8196_pdata,
},
+ {
+ .compatible = "mediatek,mt8189-vcodec-dec",
+ .data = &mtk_vdec_8189_pdata,
+ },
{},
};
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
index 783a988b894a..1c647aef7723 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
@@ -1041,3 +1041,22 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata = {
.prob_size = VP9_PROB_BUF_SIZE,
},
};
+
+const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdata = {
+ MTK_STATELESS_DEC_DATA,
+ .hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
+ .chip_model = 8189,
+ .h264_params = {
+ .level = V4L2_MPEG_VIDEO_H264_LEVEL_5_2,
+ .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10,
+ },
+ .h265_params = {
+ .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,
+ .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
+ },
+ .vp9_params = {
+ .level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2,
+ .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
+ .prob_size = VP9_4K_PROB_BUF_SIZE,
+ },
+};
--
2.45.2
^ permalink raw reply related
* [PATCH v9 7/9] media: mediatek: vcodec: Fix media device node number
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou
In-Reply-To: <20260424030527.10656-1-kyrie.wu@mediatek.com>
change media register device node number to a correct value.
The vfd minor is used to record the number of registered
video device nodes. The mdev_dec.devnode minor counter is
used to record the number of registered media device nodes.
Fixes: 41f03c673cb7b ("media: mediatek: vcodec: replace pr_* with dev_* for v4l2 debug message")
Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
index dc67c2b84776..edf0caf3efce 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
@@ -495,7 +495,8 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
goto err_media_reg;
}
- dev_dbg(&pdev->dev, "media registered as /dev/media%d", vfd_dec->minor);
+ dev_dbg(&pdev->dev, "media registered as /dev/media%d",
+ dev->mdev_dec.devnode->minor);
}
mtk_vcodec_dbgfs_init(dev, false);
--
2.45.2
^ permalink raw reply related
* [PATCH v9 8/9] dt-bindings: media: Add MT8189 mediatek,vcodec-encoder
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou,
Krzysztof Kozlowski
In-Reply-To: <20260424030527.10656-1-kyrie.wu@mediatek.com>
Add MT8189 encoder compatible string to distinguish former ICs
MTK's. Compared with MT8196, the maximum resolution of MT8189
encoder is only 4K, and the fps is only 30, which cannot reach
the highest parameter of MT8196: level6.2, 8K@60fps.
Compared with MT8188, the level can only support 5.1, which is less
than 5.2 of MT8188. But the maximum bitrate is 100Mbps, which is twice
that of MT8188. And MT8189 could support NBM mode.
Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
index 72698456374a..91e1e0151e03 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
@@ -22,6 +22,7 @@ properties:
- mediatek,mt8173-vcodec-enc
- mediatek,mt8183-vcodec-enc
- mediatek,mt8188-vcodec-enc
+ - mediatek,mt8189-vcodec-enc
- mediatek,mt8192-vcodec-enc
- mediatek,mt8195-vcodec-enc
- mediatek,mt8196-vcodec-enc
@@ -105,6 +106,7 @@ allOf:
enum:
- mediatek,mt8183-vcodec-enc
- mediatek,mt8188-vcodec-enc
+ - mediatek,mt8189-vcodec-enc
- mediatek,mt8192-vcodec-enc
- mediatek,mt8195-vcodec-enc
--
2.45.2
^ permalink raw reply related
* [PATCH v9 2/9] media: mediatek: decoder: Add a new platform data member
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou
In-Reply-To: <20260424030527.10656-1-kyrie.wu@mediatek.com>
Move the chip model information into the codec match data
and remove the second compatible matching code.
Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
---
.../mediatek/vcodec/decoder/mtk_vcodec_dec.c | 2 +-
.../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 5 +
.../vcodec/decoder/mtk_vcodec_dec_drv.c | 39 ++-----
.../vcodec/decoder/mtk_vcodec_dec_drv.h | 17 +--
.../vcodec/decoder/mtk_vcodec_dec_hw.c | 2 +-
.../vcodec/decoder/mtk_vcodec_dec_stateful.c | 1 +
.../vcodec/decoder/mtk_vcodec_dec_stateless.c | 104 +++++++++++++-----
7 files changed, 96 insertions(+), 74 deletions(-)
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c
index d76e891f784b..13d70acda88b 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.c
@@ -263,7 +263,7 @@ static int vidioc_vdec_querycap(struct file *file, void *priv,
struct device *dev = &ctx->dev->plat_dev->dev;
strscpy(cap->driver, dev->driver->name, sizeof(cap->driver));
- snprintf(cap->card, sizeof(cap->card), "MT%d video decoder", ctx->dev->chip_name);
+ snprintf(cap->card, sizeof(cap->card), "MT%d video decoder", ctx->dev->chip_model);
return 0;
}
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h
index 1af075fc0194..80cb46f1cded 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h
@@ -69,6 +69,11 @@ extern const struct v4l2_m2m_ops mtk_vdec_m2m_ops;
extern const struct media_device_ops mtk_vcodec_media_ops;
extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata;
extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata;
+extern const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata;
+extern const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata;
+extern const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata;
+extern const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata;
+extern const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata;
extern const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata;
extern const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata;
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
index e7c140b26955..6ebd82ba8d23 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c
@@ -331,26 +331,9 @@ static const struct v4l2_file_operations mtk_vcodec_fops = {
.mmap = v4l2_m2m_fop_mmap,
};
-static void mtk_vcodec_dec_get_chip_name(struct mtk_vcodec_dec_dev *vdec_dev)
+static void mtk_vcodec_dec_get_chip_model(struct mtk_vcodec_dec_dev *vdec_dev)
{
- struct device *dev = &vdec_dev->plat_dev->dev;
-
- if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-dec"))
- vdec_dev->chip_name = MTK_VDEC_MT8173;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-dec"))
- vdec_dev->chip_name = MTK_VDEC_MT8183;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-dec"))
- vdec_dev->chip_name = MTK_VDEC_MT8192;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-dec"))
- vdec_dev->chip_name = MTK_VDEC_MT8195;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8186-vcodec-dec"))
- vdec_dev->chip_name = MTK_VDEC_MT8186;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8188-vcodec-dec"))
- vdec_dev->chip_name = MTK_VDEC_MT8188;
- else if (of_device_is_compatible(dev->of_node, "mediatek,mt8196-vcodec-dec"))
- vdec_dev->chip_name = MTK_VDEC_MT8196;
- else
- vdec_dev->chip_name = MTK_VDEC_INVAL;
+ vdec_dev->chip_model = vdec_dev->vdec_pdata->chip_model;
}
static int mtk_vcodec_probe(struct platform_device *pdev)
@@ -368,11 +351,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
INIT_LIST_HEAD(&dev->ctx_list);
dev->plat_dev = pdev;
- mtk_vcodec_dec_get_chip_name(dev);
- if (dev->chip_name == MTK_VDEC_INVAL) {
- dev_err(&pdev->dev, "Failed to get decoder chip name");
- return -EINVAL;
- }
+ mtk_vcodec_dec_get_chip_model(dev);
dev->vdec_pdata = of_device_get_match_data(&pdev->dev);
if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu",
@@ -389,7 +368,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
return -ENODEV;
}
dma_set_max_seg_size(&pdev->dev, UINT_MAX);
- if (dev->chip_name == MTK_VDEC_MT8196) {
+ if (dev->chip_model == 8196) {
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
if (ret) {
dev_err(&pdev->dev, "Failed to enable 36-bit DMA: %d\n", ret);
@@ -558,23 +537,23 @@ static const struct of_device_id mtk_vcodec_match[] = {
},
{
.compatible = "mediatek,mt8192-vcodec-dec",
- .data = &mtk_lat_sig_core_pdata,
+ .data = &mtk_vdec_8192_pdata,
},
{
.compatible = "mediatek,mt8186-vcodec-dec",
- .data = &mtk_vdec_single_core_pdata,
+ .data = &mtk_vdec_8186_pdata,
},
{
.compatible = "mediatek,mt8195-vcodec-dec",
- .data = &mtk_lat_sig_core_pdata,
+ .data = &mtk_vdec_8195_pdata,
},
{
.compatible = "mediatek,mt8188-vcodec-dec",
- .data = &mtk_lat_sig_core_pdata,
+ .data = &mtk_vdec_8188_pdata,
},
{
.compatible = "mediatek,mt8196-vcodec-dec",
- .data = &mtk_lat_sig_core_pdata,
+ .data = &mtk_vdec_8196_pdata,
},
{},
};
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
index f06dfc1a3455..7921588bf814 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
@@ -21,17 +21,6 @@
#define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_RACING)
#define IS_VDEC_SUPPORT_EXT(capability) ((capability) & MTK_VDEC_IS_SUPPORT_EXT)
-enum mtk_vcodec_dec_chip_name {
- MTK_VDEC_INVAL = 0,
- MTK_VDEC_MT8173 = 8173,
- MTK_VDEC_MT8183 = 8183,
- MTK_VDEC_MT8186 = 8186,
- MTK_VDEC_MT8188 = 8188,
- MTK_VDEC_MT8192 = 8192,
- MTK_VDEC_MT8195 = 8195,
- MTK_VDEC_MT8196 = 8196,
-};
-
/*
* enum mtk_vdec_format_types - Structure used to get supported
* format types according to decoder capability
@@ -108,6 +97,7 @@ struct vdec_pic_info {
*
* @is_subdev_supported: whether support parent-node architecture(subdev)
* @uses_stateless_api: whether the decoder uses the stateless API with requests
+ * @chip_model: platforms configuration values
*/
struct mtk_vcodec_dec_pdata {
void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx);
@@ -129,6 +119,7 @@ struct mtk_vcodec_dec_pdata {
bool is_subdev_supported;
bool uses_stateless_api;
+ unsigned int chip_model;
};
/**
@@ -276,7 +267,7 @@ struct mtk_vcodec_dec_ctx {
* @dec_racing_info_mutex: mutex lock used for inner racing mode
* @dbgfs: debug log related information
*
- * @chip_name: used to distinguish platforms and select the correct codec configuration values
+ * @chip_model: used to distinguish platforms and select the correct codec configuration values
*/
struct mtk_vcodec_dec_dev {
struct v4l2_device v4l2_dev;
@@ -319,7 +310,7 @@ struct mtk_vcodec_dec_dev {
struct mutex dec_racing_info_mutex;
struct mtk_vcodec_dbgfs dbgfs;
- enum mtk_vcodec_dec_chip_name chip_name;
+ unsigned int chip_model;
};
static inline struct mtk_vcodec_dec_ctx *fh_to_dec_ctx(struct v4l2_fh *fh)
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c
index e4e527fe54dc..149f1ad58152 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c
@@ -76,7 +76,7 @@ static void mtk_vdec_hw_clean_xpc(struct mtk_vdec_hw_dev *dev)
{
u32 val, mask, addr = VDEC_XPC_CLEAN_ADDR;
- if (dev->main_dev->chip_name != MTK_VDEC_MT8196)
+ if (dev->main_dev->chip_model != 8196)
return;
val = dev->hw_idx == MTK_VDEC_LAT0 ? VDEC_XPC_LAT_VAL : VDEC_XPC_CORE_VAL;
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
index aa9bdee7a96c..0e702d6a43ed 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
@@ -618,4 +618,5 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = {
.flush_decoder = mtk_vdec_flush_decoder,
.is_subdev_supported = false,
.hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
+ .chip_model = 8173,
};
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
index 472ece5713a5..5ecbfc169805 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
@@ -571,17 +571,17 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = {
static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_name) {
- case MTK_VDEC_MT8192:
- case MTK_VDEC_MT8188:
+ switch (ctx->dev->chip_model) {
+ case 8192:
+ case 8188:
cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2;
break;
- case MTK_VDEC_MT8195:
- case MTK_VDEC_MT8196:
+ case 8195:
+ case 8196:
cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0;
break;
- case MTK_VDEC_MT8183:
- case MTK_VDEC_MT8186:
+ case 8183:
+ case 8186:
cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
break;
default:
@@ -593,10 +593,10 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg,
static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_name) {
- case MTK_VDEC_MT8188:
- case MTK_VDEC_MT8195:
- case MTK_VDEC_MT8196:
+ switch (ctx->dev->chip_model) {
+ case 8188:
+ case 8195:
+ case 8196:
cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10;
break;
default:
@@ -608,12 +608,12 @@ static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg,
static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_name) {
- case MTK_VDEC_MT8188:
+ switch (ctx->dev->chip_model) {
+ case 8188:
cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1;
break;
- case MTK_VDEC_MT8195:
- case MTK_VDEC_MT8196:
+ case 8195:
+ case 8196:
cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2;
break;
default:
@@ -625,10 +625,10 @@ static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg,
static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_name) {
- case MTK_VDEC_MT8188:
- case MTK_VDEC_MT8195:
- case MTK_VDEC_MT8196:
+ switch (ctx->dev->chip_model) {
+ case 8188:
+ case 8195:
+ case 8196:
cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10;
break;
default:
@@ -640,16 +640,16 @@ static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg,
static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_name) {
- case MTK_VDEC_MT8192:
- case MTK_VDEC_MT8188:
+ switch (ctx->dev->chip_model) {
+ case 8192:
+ case 8188:
cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1;
break;
- case MTK_VDEC_MT8195:
- case MTK_VDEC_MT8196:
+ case 8195:
+ case 8196:
cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2;
break;
- case MTK_VDEC_MT8186:
+ case 8186:
cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1;
break;
default:
@@ -661,10 +661,10 @@ static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg,
static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_name) {
- case MTK_VDEC_MT8188:
- case MTK_VDEC_MT8195:
- case MTK_VDEC_MT8196:
+ switch (ctx->dev->chip_model) {
+ case 8188:
+ case 8195:
+ case 8196:
cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_2;
break;
default:
@@ -935,6 +935,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = {
.get_cap_buffer = vdec_get_cap_buffer,
.is_subdev_supported = false,
.hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
+ .chip_model = 8183,
};
/* This platform data is used for one lat and one core architecture. */
@@ -955,6 +956,45 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata = {
.hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
};
+#define MTK_STATELESS_DEC_DATA \
+ .init_vdec_params = mtk_init_vdec_params, \
+ .ctrls_setup = mtk_vcodec_dec_ctrls_setup, \
+ .vdec_vb2_ops = &mtk_vdec_request_vb2_ops, \
+ .vdec_formats = mtk_video_formats, \
+ .num_formats = &num_formats, \
+ .default_out_fmt = &default_out_format, \
+ .default_cap_fmt = &default_cap_format, \
+ .uses_stateless_api = true, \
+ .worker = mtk_vdec_worker, \
+ .flush_decoder = mtk_vdec_flush_decoder, \
+ .cap_to_disp = mtk_vdec_stateless_cap_to_disp, \
+ .get_cap_buffer = vdec_get_cap_buffer, \
+ .is_subdev_supported = true
+
+const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata = {
+ MTK_STATELESS_DEC_DATA,
+ .hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
+ .chip_model = 8188,
+};
+
+const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata = {
+ MTK_STATELESS_DEC_DATA,
+ .hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
+ .chip_model = 8192,
+};
+
+const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata = {
+ MTK_STATELESS_DEC_DATA,
+ .hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
+ .chip_model = 8195,
+};
+
+const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata = {
+ MTK_STATELESS_DEC_DATA,
+ .hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
+ .chip_model = 8196,
+};
+
const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = {
.init_vdec_params = mtk_init_vdec_params,
.ctrls_setup = mtk_vcodec_dec_ctrls_setup,
@@ -971,3 +1011,9 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = {
.is_subdev_supported = true,
.hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
};
+
+const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata = {
+ MTK_STATELESS_DEC_DATA,
+ .hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
+ .chip_model = 8186,
+};
--
2.45.2
^ permalink raw reply related
* [PATCH v9 4/9] media: mediatek: vcodec: Add VP9 Probability Size Configuration
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou
In-Reply-To: <20260424030527.10656-1-kyrie.wu@mediatek.com>
Introduce support for using different probability buffer sizes for
different stateless decoders: in particular, the VP9 decoder can use
a different size on different SoCs because of different
hardware capabilities.
Move the hardcoded single probability buffer size value to
decoder params, introduce a new VP9_4K_PROB_BUF_SIZE and assign:
- VP9_PROB_BUF_SIZE (2560 lines) to legacy SoCs;
- VP9_4K_PROB_BUF_SIZE (3840 lines) to newer SoCs (MT8196, MT8189).
Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h | 2 ++
.../mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c | 1 +
.../mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c | 9 +++++++++
.../mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 4 ++--
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
index 4ffc0eae855b..43dc0b22fdb0 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
@@ -82,10 +82,12 @@ struct vdec_pic_info {
* struct mtk_vcodec_dec_params - decoder supported parameters
* @level: decoder supported vcodec level
* @profile: decoder supported vcodec profile
+ * @prob_size: vp9 decoder probability size
*/
struct mtk_vcodec_dec_params {
s64 level;
s64 profile;
+ size_t prob_size;
};
/**
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
index 64f32976d15e..5dcbe6550419 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
@@ -630,5 +630,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = {
.vp9_params = {
.level = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0,
.profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1,
+ .prob_size = 2560,
},
};
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
index efcd28f5f289..783a988b894a 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
@@ -10,6 +10,9 @@
#include "mtk_vcodec_dec_pm.h"
#include "vdec_drv_if.h"
+#define VP9_PROB_BUF_SIZE 2560
+#define VP9_4K_PROB_BUF_SIZE 3840
+
/**
* struct mtk_stateless_control - CID control type
* @cfg: control configuration
@@ -890,6 +893,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = {
.vp9_params = {
.level = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0,
.profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1,
+ .prob_size = VP9_PROB_BUF_SIZE,
},
};
@@ -941,6 +945,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata = {
.vp9_params = {
.level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1,
.profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
+ .prob_size = VP9_PROB_BUF_SIZE,
},
};
@@ -959,6 +964,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata = {
.vp9_params = {
.level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1,
.profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
+ .prob_size = VP9_PROB_BUF_SIZE,
},
};
@@ -977,6 +983,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata = {
.vp9_params = {
.level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1,
.profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1,
+ .prob_size = VP9_PROB_BUF_SIZE,
},
};
@@ -995,6 +1002,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata = {
.vp9_params = {
.level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2,
.profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
+ .prob_size = VP9_4K_PROB_BUF_SIZE,
},
};
@@ -1030,5 +1038,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata = {
.vp9_params = {
.level = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1,
.profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1,
+ .prob_size = VP9_PROB_BUF_SIZE,
},
};
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
index 3f4b70526754..e02dcf81b3cb 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
@@ -22,7 +22,6 @@
#define VP9_RESET_FRAME_CONTEXT_ALL 3
#define VP9_TILE_BUF_SIZE 4096
-#define VP9_PROB_BUF_SIZE 2560
#define VP9_COUNTS_BUF_SIZE 16384
#define HDR_FLAG(x) (!!((hdr)->flags & V4L2_VP9_FRAME_FLAG_##x))
@@ -551,6 +550,7 @@ static int vdec_vp9_slice_alloc_working_buffer(struct vdec_vp9_slice_instance *i
struct vdec_vp9_slice_vsi *vsi)
{
struct mtk_vcodec_dec_ctx *ctx = instance->ctx;
+ struct mtk_vcodec_dec_dev *pdev = ctx->dev;
enum vdec_vp9_slice_resolution_level level;
/* super blocks */
unsigned int max_sb_w;
@@ -621,7 +621,7 @@ static int vdec_vp9_slice_alloc_working_buffer(struct vdec_vp9_slice_instance *i
}
if (!instance->prob.va) {
- instance->prob.size = VP9_PROB_BUF_SIZE;
+ instance->prob.size = pdev->vdec_pdata->vp9_params.prob_size;
if (mtk_vcodec_mem_alloc(ctx, &instance->prob))
goto err;
}
--
2.45.2
^ permalink raw reply related
* [PATCH v9 5/9] media: mediatek: vcodec: Fix vp9 4096x2176 fail for profile2
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou
In-Reply-To: <20260424030527.10656-1-kyrie.wu@mediatek.com>
The DRAM address of the VP9 decoder tile info buffers may require
as much as 36bits for 4096x2176 resolution. Fold the 4 most significant
bits into the lower (padding) four bits of address.
Fixes: 5d418351ca8f1 ("media: mediatek: vcodec: support stateless VP9 decoding")
Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
---
.../mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
index e02dcf81b3cb..c9eb9ebe4116 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c
@@ -1138,9 +1138,17 @@ static int vdec_vp9_slice_setup_tile_buffer(struct vdec_vp9_slice_instance *inst
return -EINVAL;
}
tiles->size[i][j] = size;
+ /*
+ * If the system supports 64-bit DMA addresses, the upper 4 bits
+ * of the address are also encoded into the buffer entry.
+ * The buffer pointer (tb) is incremented after each entry is written.
+ */
if (tiles->mi_rows[i]) {
*tb++ = (size << 3) + ((offset << 3) & 0x7f);
- *tb++ = pa & ~0xf;
+ *tb = pa & GENMASK(31, 4);
+ if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
+ *tb |= (pa >> 32) & GENMASK(3, 0);
+ tb++;
*tb++ = (pa << 3) & 0x7f;
mi_row = (tiles->mi_rows[i] - 1) & 0x1ff;
mi_col = (tiles->mi_cols[j] - 1) & 0x3f;
--
2.45.2
^ permalink raw reply related
* [PATCH v9 1/9] dt-bindings: media: mediatek: decoder: Add MT8189 mediatek,vcodec-decoder
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou
In-Reply-To: <20260424030527.10656-1-kyrie.wu@mediatek.com>
Add compatible for video decoder on MT8189 platform. Compared with
former ICs, the MT8189 decoder use iommu to instead of smmu, and
use scp architecture, the frequency is only 406MHZ, and cannot reach
more than 700MHZ. It uses only one clock. At the same time, the decoder
supports the vp9 decoding protocol for the first time in single IC.
Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
---
.../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
index 74e1d88d3056..ee2bbbdb2d50 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -75,6 +75,7 @@ properties:
- mediatek,mt8192-vcodec-dec
- mediatek,mt8186-vcodec-dec
- mediatek,mt8188-vcodec-dec
+ - mediatek,mt8189-vcodec-dec
- mediatek,mt8195-vcodec-dec
- mediatek,mt8196-vcodec-dec
@@ -132,11 +133,11 @@ patternProperties:
Refer to bindings/iommu/mediatek,iommu.yaml.
clocks:
- minItems: 4
+ minItems: 1
maxItems: 5
clock-names:
- minItems: 4
+ minItems: 1
maxItems: 5
assigned-clocks:
--
2.45.2
^ permalink raw reply related
* [PATCH v9 3/9] media: mediatek: vcodec: Refactor Decoder profile & level Handling
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou
In-Reply-To: <20260424030527.10656-1-kyrie.wu@mediatek.com>
This commit refactors the handling of decoder parameters for H264,
H265, and VP9 codecs by introducing a new structure to standardize
supported level and profile information. By leveraging this change,
chipset-specific conditional logic in the codec configuration
functions is significantly reduced.
Signed-off-by: Kyrie Wu <kyrie.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../vcodec/decoder/mtk_vcodec_dec_drv.h | 16 ++
.../vcodec/decoder/mtk_vcodec_dec_stateful.c | 12 ++
.../vcodec/decoder/mtk_vcodec_dec_stateless.c | 165 ++++++++++--------
3 files changed, 118 insertions(+), 75 deletions(-)
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
index 7921588bf814..4ffc0eae855b 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h
@@ -78,6 +78,16 @@ struct vdec_pic_info {
unsigned int reserved;
};
+/**
+ * struct mtk_vcodec_dec_params - decoder supported parameters
+ * @level: decoder supported vcodec level
+ * @profile: decoder supported vcodec profile
+ */
+struct mtk_vcodec_dec_params {
+ s64 level;
+ s64 profile;
+};
+
/**
* struct mtk_vcodec_dec_pdata - compatible data for each IC
* @init_vdec_params: init vdec params
@@ -98,6 +108,9 @@ struct vdec_pic_info {
* @is_subdev_supported: whether support parent-node architecture(subdev)
* @uses_stateless_api: whether the decoder uses the stateless API with requests
* @chip_model: platforms configuration values
+ * @h264_params: H264 decoder default supported params
+ * @h265_params: H265 decoder default supported params
+ * @vp9_params: VP9 decoder default supported params
*/
struct mtk_vcodec_dec_pdata {
void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx);
@@ -120,6 +133,9 @@ struct mtk_vcodec_dec_pdata {
bool is_subdev_supported;
bool uses_stateless_api;
unsigned int chip_model;
+ struct mtk_vcodec_dec_params h264_params;
+ struct mtk_vcodec_dec_params h265_params;
+ struct mtk_vcodec_dec_params vp9_params;
};
/**
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
index 0e702d6a43ed..64f32976d15e 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c
@@ -619,4 +619,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = {
.is_subdev_supported = false,
.hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
.chip_model = 8173,
+ .h264_params = {
+ .level = V4L2_MPEG_VIDEO_H264_LEVEL_4_1,
+ .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+ },
+ .h265_params = {
+ .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,
+ .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
+ },
+ .vp9_params = {
+ .level = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0,
+ .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1,
+ },
};
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
index 5ecbfc169805..efcd28f5f289 100644
--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
@@ -571,106 +571,49 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctrl_ops = {
static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_model) {
- case 8192:
- case 8188:
- cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_5_2;
- break;
- case 8195:
- case 8196:
- cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_6_0;
- break;
- case 8183:
- case 8186:
- cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
- break;
- default:
- cfg->max = V4L2_MPEG_VIDEO_H264_LEVEL_4_1;
- break;
- }
+ struct mtk_vcodec_dec_dev *pdev = ctx->dev;
+
+ cfg->max = pdev->vdec_pdata->h264_params.level;
}
static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_model) {
- case 8188:
- case 8195:
- case 8196:
- cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10;
- break;
- default:
- cfg->max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH;
- break;
- }
+ struct mtk_vcodec_dec_dev *pdev = ctx->dev;
+
+ cfg->max = pdev->vdec_pdata->h264_params.profile;
}
static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_model) {
- case 8188:
- cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1;
- break;
- case 8195:
- case 8196:
- cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2;
- break;
- default:
- cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4;
- break;
- }
+ struct mtk_vcodec_dec_dev *pdev = ctx->dev;
+
+ cfg->max = pdev->vdec_pdata->h265_params.level;
}
static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_model) {
- case 8188:
- case 8195:
- case 8196:
- cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10;
- break;
- default:
- cfg->max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE;
- break;
- }
+ struct mtk_vcodec_dec_dev *pdev = ctx->dev;
+
+ cfg->max = pdev->vdec_pdata->h265_params.profile;
}
static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_model) {
- case 8192:
- case 8188:
- cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1;
- break;
- case 8195:
- case 8196:
- cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2;
- break;
- case 8186:
- cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1;
- break;
- default:
- cfg->max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0;
- break;
- }
+ struct mtk_vcodec_dec_dev *pdev = ctx->dev;
+
+ cfg->max = pdev->vdec_pdata->vp9_params.level;
}
static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg,
struct mtk_vcodec_dec_ctx *ctx)
{
- switch (ctx->dev->chip_model) {
- case 8188:
- case 8195:
- case 8196:
- cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_2;
- break;
- default:
- cfg->max = V4L2_MPEG_VIDEO_VP9_PROFILE_1;
- break;
- }
+ struct mtk_vcodec_dec_dev *pdev = ctx->dev;
+
+ cfg->max = pdev->vdec_pdata->vp9_params.profile;
}
static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg,
@@ -936,6 +879,18 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = {
.is_subdev_supported = false,
.hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
.chip_model = 8183,
+ .h264_params = {
+ .level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
+ .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+ },
+ .h265_params = {
+ .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,
+ .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
+ },
+ .vp9_params = {
+ .level = V4L2_MPEG_VIDEO_VP9_LEVEL_4_0,
+ .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1,
+ },
};
/* This platform data is used for one lat and one core architecture. */
@@ -975,24 +930,72 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata = {
MTK_STATELESS_DEC_DATA,
.hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
.chip_model = 8188,
+ .h264_params = {
+ .level = V4L2_MPEG_VIDEO_H264_LEVEL_5_2,
+ .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10,
+ },
+ .h265_params = {
+ .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
+ .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+ },
+ .vp9_params = {
+ .level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1,
+ .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
+ },
};
const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata = {
MTK_STATELESS_DEC_DATA,
.hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
.chip_model = 8192,
+ .h264_params = {
+ .level = V4L2_MPEG_VIDEO_H264_LEVEL_5_2,
+ .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+ },
+ .h265_params = {
+ .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,
+ .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
+ },
+ .vp9_params = {
+ .level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1,
+ .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
+ },
};
const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata = {
MTK_STATELESS_DEC_DATA,
.hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
.chip_model = 8195,
+ .h264_params = {
+ .level = V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
+ .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10,
+ },
+ .h265_params = {
+ .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2,
+ .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+ },
+ .vp9_params = {
+ .level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_1,
+ .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1,
+ },
};
const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata = {
MTK_STATELESS_DEC_DATA,
.hw_arch = MTK_VDEC_LAT_SINGLE_CORE,
.chip_model = 8196,
+ .h264_params = {
+ .level = V4L2_MPEG_VIDEO_H264_LEVEL_6_0,
+ .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10,
+ },
+ .h265_params = {
+ .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2,
+ .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+ },
+ .vp9_params = {
+ .level = V4L2_MPEG_VIDEO_VP9_LEVEL_5_2,
+ .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_2,
+ },
};
const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata = {
@@ -1016,4 +1019,16 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata = {
MTK_STATELESS_DEC_DATA,
.hw_arch = MTK_VDEC_PURE_SINGLE_CORE,
.chip_model = 8186,
+ .h264_params = {
+ .level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
+ .profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+ },
+ .h265_params = {
+ .level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,
+ .profile = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
+ },
+ .vp9_params = {
+ .level = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1,
+ .profile = V4L2_MPEG_VIDEO_VP9_PROFILE_1,
+ },
};
--
2.45.2
^ permalink raw reply related
* [PATCH v9 0/9] Enable video decoder & encoder for MT8189
From: Kyrie Wu @ 2026-04-24 3:05 UTC (permalink / raw)
To: Tiffany Lin, Andrew-CT Chen, Yunfei Dong, Mauro Carvalho Chehab,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Kyrie Wu, Hans Verkuil,
Nicolas Dufresne, Nathan Hebert, Arnd Bergmann, Irui Wang,
George Sun, linux-media, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
Cc: Neil Armstrong, Andrzej Pietrasiewicz, Yilong Zhou
This series have the follow changing:
Firstly add mt8189 video decoder compatible, profile and level to support
MT8189 kernel driver.
Secondly fix some bugs, including vp 4K profile2 and media device node
number bug.
Lastly, add mt8189 video encoder compatible.
This series has been tested with MT8189 tast test.
Encoding and decoding worked for this chip.
Patches 1 Add decoder compatible.
Patches 1 fix decoder chip model.
Patches 3-4 Add profile, level and probability size supporting.
Patches 6 add decoder platform data to support MT8189.
Patches 5 & 7 fix some bugs.
Patches 8-9 Adds encoder compatible.
---
H264 test results:
./fluster.py run -d GStreamer-H.264-V4L2SL-Gst1.0 -j2 -t 90
JVT-AVC_V1 Ran 96/135 tests successfully
VP9 test results:
./fluster.py run -d GStreamer-VP9-V4L2SL-Gst1.0 -j2 -t 90
VP9-TEST-VECTORS Ran 276/305 tests successfully
v4l2-compliance test results:
Compliance test for mtk-vcodec-enc device /dev/video2:
Total for mtk-vcodec-enc device /dev/video2: 47, Succeeded: 46, Failed: 1, Warnings: 0
Compliance test for mtk-vcodec-dec device /dev/video3:
Total for mtk-vcodec-dec device /dev/video3: 48, Succeeded: 48, Failed: 0, Warnings: 0
scp upstream link:
https://patchwork.kernel.org/project/linux-mediatek/patch/20250811015922.32680-1-huayu.zong@mediatek.com/
dtsi upstream link:
https://lore.kernel.org/linux-mediatek/20251030134541.784011-12-jh.hsu@mediatek.com/T/#m847e35de0a5b18fac0ca0624a8559d84964ad5c7
Changes compared with v8:
--Rebased on top of the latest media tree
Changes compared with v7:
--relocate the patches set
--refactor decoder platform data patch
--fix commit message errors
Changes compared with v6:
--refactor the patches of set compatible data, profile and level
--add reviewer to commit messages
--fix commit message errors
Changes compared with v5:
--refactor the patches of set compatible data, profile and level
--add reviewer to commit messages
--fix commit message errors
Changes compared with v4:
--update H264 & vp9 fluster test results
--update vp9 single core decoder prob size setting and commit messages
Changes compared with v3:
--add reviewer to commit messages
--Rebased on top of the latest media tree
Changes compared with v2:
--add H264 fluster test results
--reorder compatible string for dt-bindings
Changes compared with v1:
--add v4l2-compliance test results
--add scp upstream link
--add HW difference discriptions for dt-bindings commit messages
This series patches dependent on:
[1]
https://patchwork.linuxtv.org/project/linux-media/patch/20260328051630.7937-2-yunfei.dong@mediatek.com/
[2]
https://patchwork.linuxtv.org/project/linux-media/patch/20260423073345.27402-2-irui.wang@mediatek.com/
Kyrie Wu (9):
dt-bindings: media: mediatek: decoder: Add MT8189
mediatek,vcodec-decoder
media: mediatek: decoder: Add a new platform data member
media: mediatek: vcodec: Refactor Decoder profile & level Handling
media: mediatek: vcodec: Add VP9 Probability Size Configuration
media: mediatek: vcodec: Fix vp9 4096x2176 fail for profile2
media: mediatek: vcodec: add decoder compatible to support MT8189
media: mediatek: vcodec: Fix media device node number
dt-bindings: media: Add MT8189 mediatek,vcodec-encoder
media: mediatek: encoder: Add MT8189 encoder compatible data
.../media/mediatek,vcodec-encoder.yaml | 2 +
.../media/mediatek,vcodec-subdev-decoder.yaml | 5 +-
.../mediatek/vcodec/decoder/mtk_vcodec_dec.c | 2 +-
.../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 6 +
.../vcodec/decoder/mtk_vcodec_dec_drv.c | 46 ++--
.../vcodec/decoder/mtk_vcodec_dec_drv.h | 35 ++-
.../vcodec/decoder/mtk_vcodec_dec_hw.c | 2 +-
.../vcodec/decoder/mtk_vcodec_dec_stateful.c | 14 +
.../vcodec/decoder/mtk_vcodec_dec_stateless.c | 239 ++++++++++++------
.../vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 14 +-
.../vcodec/encoder/mtk_vcodec_enc_drv.c | 14 +
11 files changed, 253 insertions(+), 126 deletions(-)
--
2.45.2
^ permalink raw reply
* Re: [PATCH v3 02/11] iommu: Pass in reset result to pci_dev_reset_iommu_done()
From: Baolu Lu @ 2026-04-24 2:56 UTC (permalink / raw)
To: Nicolin Chen
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Bjorn Helgaas,
Jason Gunthorpe, Rafael J . Wysocki, Len Brown,
Pranjal Shrivastava, Mostafa Saleh, Kevin Tian, linux-arm-kernel,
iommu, linux-kernel, linux-acpi, linux-pci, vsethi, Shuai Xue
In-Reply-To: <aerZa3aQBMCwzzT8@Asurada-Nvidia>
On 4/24/26 10:46, Nicolin Chen wrote:
> On Fri, Apr 24, 2026 at 10:38:09AM +0800, Baolu Lu wrote:
>> On 4/17/26 07:28, Nicolin Chen wrote:
>>> @@ -4083,6 +4093,18 @@ void pci_dev_reset_iommu_done(struct pci_dev *pdev)
>>> if (WARN_ON(!group->blocking_domain))
>>> return;
>>> + /*
>>> + * A reset failure implies that the device might be unreliable. E.g. its
>>> + * device cache might retain stale entries, which potentially results in
>>> + * memory corruption. Thus, do not unblock the device until a successful
>>> + * reset.
>>> + */
>>> + if (!reset_succeeds) {
>>> + pci_err(pdev,
>>> + "Reset failed. Keep it blocked to protect memory\n");
>>> + return;
>>> + }
>>
>> Nit: pci_dev_reset_iommu_done() does nothing if reset_succeeds is false.
>> Would it be better to handle this in the caller instead? Something like:
>>
>> if (reset_succeeds)
>> pci_dev_reset_iommu_done(dev);
>>
>> ?
>
> It would also need a print and some duplicated comments. Actually,
> that would be my v2, which Kevin suggested this against:
> https://lore.kernel.org/all/BN9PR11MB5276706AE4E0BBE86F0F6E158C4EA@BN9PR11MB5276.namprd11.prod.outlook.com/
Oh, I forgot that comment.
> Though I don't have a strong personal reference here, I do see this
> version slightly cleaner than doing in the callers.
Okay, you own the decision.
> Thanks
> Nicolin
Thanks,
baolu
^ permalink raw reply
* [PATCH v1 3/3] PCI: imx6: Add root port reset to support link recovery
From: Richard Zhu @ 2026-04-24 2:57 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu
In-Reply-To: <20260424025735.1490772-1-hongxing.zhu@nxp.com>
The PCIe link can go down due to various unexpected circumstances. Add
root port reset support to enable link recovery for the i.MX PCIe
controller when the optional "intr" interrupt is present.
Reset root port to uninitialize, initialize the PCIe controller, and
restart the PCIe link at end when a link down event happens.
On i.MX95 platforms, link events and PME share the same interrupt line.
The link event interrupt cannot use a threaded-only IRQ handler because
the PME driver uses request_irq() with only the IRQF_SHARED flag set,
which requires a primary handler.
To handle this shared interrupt scenario, register a primary interrupt
handler with IRQF_SHARED for link events and manipulate the link event
enable bits to ensure the shared interrupt source triggers only one
handler at a time.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 122 ++++++++++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index e35044cc52185..0fb75d4b4e636 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -34,6 +34,7 @@
#include <linux/pm_runtime.h>
#include "../../pci.h"
+#include "../pci-host-common.h"
#include "pcie-designware.h"
#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
@@ -78,6 +79,10 @@
#define IMX95_SID_MASK GENMASK(5, 0)
#define IMX95_MAX_LUT 32
+#define IMX95_LINK_INT_CTRL_STS 0x1040
+#define IMX95_LINK_DOWN_INT_STS BIT(11)
+#define IMX95_LINK_DOWN_INT_EN BIT(10)
+
#define IMX95_PCIE_RST_CTRL 0x3010
#define IMX95_PCIE_COLD_RST BIT(0)
@@ -125,6 +130,8 @@ enum imx_pcie_variants {
#define IMX_PCIE_MAX_INSTANCES 2
struct imx_pcie;
+static int imx_pcie_reset_root_port(struct pci_host_bridge *bridge,
+ struct pci_dev *pdev);
struct imx_pcie_drvdata {
enum imx_pcie_variants variant;
@@ -158,6 +165,7 @@ struct imx_pcie {
bool supports_clkreq;
bool enable_ext_refclk;
struct regmap *iomuxc_gpr;
+ u32 lnk_intr;
u16 msi_ctrl;
u32 controller_id;
struct reset_control *pciephy_reset;
@@ -1306,6 +1314,13 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
imx_setup_phy_mpll(imx_pcie);
+ /*
+ * Callback invoked by PCI core when link down is detected and
+ * recovery is needed.
+ */
+ if (pp->bridge)
+ pp->bridge->reset_root_port = imx_pcie_reset_root_port;
+
return 0;
err_phy_off:
@@ -1573,6 +1588,9 @@ static int imx_pcie_suspend_noirq(struct device *dev)
if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND))
return 0;
+ if (imx_pcie->lnk_intr)
+ regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,
+ IMX95_LINK_DOWN_INT_EN);
imx_pcie_msi_save_restore(imx_pcie, true);
if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))
imx_pcie_lut_save(imx_pcie);
@@ -1623,6 +1641,9 @@ static int imx_pcie_resume_noirq(struct device *dev)
if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))
imx_pcie_lut_restore(imx_pcie);
imx_pcie_msi_save_restore(imx_pcie, false);
+ if (imx_pcie->lnk_intr)
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,
+ IMX95_LINK_DOWN_INT_EN);
return 0;
}
@@ -1632,6 +1653,84 @@ static const struct dev_pm_ops imx_pcie_pm_ops = {
imx_pcie_resume_noirq)
};
+static irqreturn_t imx_pcie_link_irq_handler(int irq, void *priv)
+{
+ struct imx_pcie *imx_pcie = priv;
+ struct dw_pcie *pci = imx_pcie->pci;
+ struct device *dev = pci->dev;
+ u32 val;
+
+ regmap_read(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS, &val);
+ if (val & IMX95_LINK_DOWN_INT_STS) {
+ dev_dbg(dev, "PCIe link down detected, initiating recovery\n");
+ regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,
+ IMX95_LINK_DOWN_INT_EN);
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,
+ IMX95_LINK_DOWN_INT_STS);
+
+ return IRQ_WAKE_THREAD;
+ } else {
+ return IRQ_NONE;
+ }
+}
+
+static irqreturn_t imx_pcie_link_irq_thread(int irq, void *priv)
+{
+ struct imx_pcie *imx_pcie = priv;
+ struct dw_pcie *pci = imx_pcie->pci;
+ struct dw_pcie_rp *pp = &pci->pp;
+ struct pci_dev *port;
+
+ for_each_pci_bridge(port, pp->bridge->bus)
+ if (pci_pcie_type(port) == PCI_EXP_TYPE_ROOT_PORT)
+ pci_host_handle_link_down(port);
+
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,
+ IMX95_LINK_DOWN_INT_EN);
+
+ return IRQ_HANDLED;
+}
+
+static int imx_pcie_reset_root_port(struct pci_host_bridge *bridge,
+ struct pci_dev *pdev)
+{
+ struct pci_bus *bus = bridge->bus;
+ struct dw_pcie_rp *pp = bus->sysdata;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct imx_pcie *imx_pcie = to_imx_pcie(pci);
+ int ret;
+
+ imx_pcie_msi_save_restore(imx_pcie, true);
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))
+ imx_pcie_lut_save(imx_pcie);
+ imx_pcie_stop_link(pci);
+ imx_pcie_host_exit(pp);
+
+ ret = imx_pcie_host_init(pp);
+ if (ret) {
+ dev_err(pci->dev, "Failed to re-init PCIe\n");
+ return ret;
+ }
+ ret = dw_pcie_setup_rc(pp);
+ if (ret)
+ goto err_host_deinit;
+
+ imx_pcie_start_link(pci);
+ dw_pcie_wait_for_link(pci);
+
+ if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT))
+ imx_pcie_lut_restore(imx_pcie);
+ imx_pcie_msi_save_restore(imx_pcie, false);
+
+ dev_dbg(pci->dev, "Root port reset completed\n");
+ return 0;
+
+err_host_deinit:
+ imx_pcie_host_exit(pp);
+
+ return ret;
+}
+
static int imx_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1834,9 +1933,32 @@ static int imx_pcie_probe(struct platform_device *pdev)
val |= PCI_MSI_FLAGS_ENABLE;
dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
}
+
+ /* Get link event irq if it is present */
+ imx_pcie->lnk_intr = platform_get_irq_byname(pdev, "intr");
+ if (imx_pcie->lnk_intr < 0)
+ return 0;
+
+ ret = devm_request_threaded_irq(dev, imx_pcie->lnk_intr,
+ imx_pcie_link_irq_handler,
+ imx_pcie_link_irq_thread,
+ IRQF_SHARED,
+ "lnk", imx_pcie);
+ if (ret) {
+ dev_err_probe(dev, ret, "Unable to request LNK IRQ\n");
+ goto err_host_deinit;
+ }
+
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS,
+ IMX95_LINK_DOWN_INT_EN);
}
return 0;
+
+err_host_deinit:
+ dw_pcie_host_deinit(&pci->pp);
+
+ return ret;
}
static void imx_pcie_shutdown(struct platform_device *pdev)
--
2.37.1
^ permalink raw reply related
* [PATCH v1 2/3] arm64: dts: imx95: Add dma, intr, aer and pme interrupters for pcie{0,1}
From: Richard Zhu @ 2026-04-24 2:57 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu
In-Reply-To: <20260424025735.1490772-1-hongxing.zhu@nxp.com>
Add dma, intr, aer and pme interrupters for pcie{0,1}.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx95.dtsi | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 71394871d8dd0..6896d9c15bf53 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1861,8 +1861,12 @@ pcie0: pcie@4c300000 {
bus-range = <0x00 0xff>;
num-lanes = <1>;
num-viewport = <8>;
- interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "intr", "aer", "pme";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
@@ -1936,8 +1940,12 @@ pcie1: pcie@4c380000 {
bus-range = <0x00 0xff>;
num-lanes = <1>;
num-viewport = <8>;
- interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "intr", "aer", "pme";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
--
2.37.1
^ permalink raw reply related
* [PATCH v1 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme interrupts
From: Richard Zhu @ 2026-04-24 2:57 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel,
Richard Zhu
In-Reply-To: <20260424025735.1490772-1-hongxing.zhu@nxp.com>
Add optional 'intr', 'aer', and 'pme' interrupt entries to the i.MX6Q
PCIe binding to support PCIe event-based interrupts for general
controller events, Advanced Error Reporting, and Power Management Events
respectively.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 9d1349855b422..badc7fcbd556c 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -58,12 +58,18 @@ properties:
items:
- description: builtin MSI controller.
- description: builtin DMA controller.
+ - description: PCIe event interrupt.
+ - description: builtin AER SPI standalone interrupter line.
+ - description: builtin PME SPI standalone interrupter line.
interrupt-names:
minItems: 1
items:
- const: msi
- const: dma
+ - const: intr
+ - const: aer
+ - const: pme
reset-gpio:
description: Should specify the GPIO for controlling the PCI bus device
--
2.37.1
^ permalink raw reply related
* [PATCH v1 0/3] Add root port reset to support link recovery
From: Richard Zhu @ 2026-04-24 2:57 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, bhelgaas, frank.li, l.stach, lpieralisi,
kwilczynski, mani, s.hauer, kernel, festevam
Cc: linux-pci, linux-arm-kernel, devicetree, imx, linux-kernel
Based on the following patch-set[1] issued by Mani.
Add support for resetting the Root Port for i.MX PCIe to enable link recovery.
[1] https://patchwork.kernel.org/project/linux-pci/cover/20260310-pci-port-reset-v7-0-9dd00ccc25ab@oss.qualcomm.com/
PCIe links can go down due to various unexpected circumstances. This patch series
adds root port reset support for link recovery on i.MX PCIe controllers when the
optional "intr" interrupt is present.
When a link down event is detected, the root port reset uninitializes and
reinitializes the PCIe controller, then restarts the PCIe link.
On i.MX95 platforms, link events and PME share the same interrupt line.
Link event interrupts cannot use only an IRQ thread handler because the PME
driver uses request_irq() to bind the PME interrupt directly with only the
IRQF_SHARED flag set.
To address this, we register one handler with IRQF_SHARED for link event
interrupts and manipulate the enable bits of link events to ensure the same
interrupt source is triggered only once at a time.
Additionally, this series adds 'intr', 'aer', and 'pme' interrupt entries to
the i.MX6Q PCIe binding to support PCIe event-based interrupts for general
controller events, Advanced Error Reporting, and Power Management Events
respectively.
[PATCH v1 1/3] dt-bindings: PCI: imx6q-pcie: Add intr, aer and pme
[PATCH v1 2/3] arm64: dts: imx95: Add dma, intr, aer and pme
[PATCH v1 3/3] PCI: imx6: Add root port reset to support link
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 +++++
arch/arm64/boot/dts/freescale/imx95.dtsi | 16 +++++++++---
drivers/pci/controller/dwc/pci-imx6.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 140 insertions(+), 4 deletions(-)
^ permalink raw reply
* Re: [PATCH v3 05/11] iommu: Change group->devices to RCU-protected list
From: Baolu Lu @ 2026-04-24 2:53 UTC (permalink / raw)
To: Nicolin Chen, Will Deacon, Robin Murphy, Joerg Roedel,
Bjorn Helgaas, Jason Gunthorpe
Cc: Rafael J . Wysocki, Len Brown, Pranjal Shrivastava, Mostafa Saleh,
Kevin Tian, linux-arm-kernel, iommu, linux-kernel, linux-acpi,
linux-pci, vsethi, Shuai Xue
In-Reply-To: <12a224061de4fff9e0725909fd0ba4e14996ff08.1776381841.git.nicolinc@nvidia.com>
On 4/17/26 07:28, Nicolin Chen wrote:
> To allow lockless iterations of the group->devices list in an ISR context
> that cannot hold the group->mutex, change the list to be RCU protected.
>
> Signed-off-by: Nicolin Chen<nicolinc@nvidia.com>
> ---
> drivers/iommu/iommu.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
> index 768ac728b4cc3..d1be62a07904a 100644
> --- a/drivers/iommu/iommu.c
> +++ b/drivers/iommu/iommu.c
> @@ -84,18 +84,20 @@ struct group_device {
> */
> bool blocked;
> unsigned int reset_depth;
> + struct rcu_head rcu;
> };
>
> /* Iterate over each struct group_device in a struct iommu_group */
> #define for_each_group_device(group, pos) \
> - list_for_each_entry(pos, &(group)->devices, list)
> + list_for_each_entry_rcu(pos, &(group)->devices, list, \
> + lockdep_is_held(&(group)->mutex))
for_each_group_device() is used in bus_iommu_probe() without holding
either the mutex or the rcu lock:
static int bus_iommu_probe(const struct bus_type *bus)
{
struct iommu_group *group, *next;
LIST_HEAD(group_list);
int ret;
[-- cut for short --]
mutex_unlock(&group->mutex);
/*
* FIXME: Mis-locked because the ops->probe_finalize()
call-back
* of some IOMMU drivers calls arm_iommu_attach_device() which
* in-turn might call back into IOMMU core code, where it tries
* to take group->mutex, resulting in a deadlock.
*/
for_each_group_device(group, gdev)
iommu_group_do_probe_finalize(gdev->dev);
}
return 0;
}
Will the change above trigger a lockdep splat due to this "mis-locked"
case?"
Thanks,
baolu
^ permalink raw reply
* [PATCH v3 9/9] ARM: dts: mediatek: mt7623n-bananapi-bpi-r2: add HDMI audio machine node
From: Daniel Golle @ 2026-04-24 2:50 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno,
Jaroslav Kysela, Takashi Iwai, Cyril Chao, Arnd Bergmann,
Nícolas F. R. A. Prado, Kuninori Morimoto, Daniel Golle,
Eugen Hristev, linux-sound, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek
In-Reply-To: <cover.1776998727.git.daniel@makrotopia.org>
Instantiate the mediatek,mt2701-hdmi-audio machine on the
BananaPi BPI-R2, binding the AFE HDMI playback path to the
on-chip HDMI transmitter acting as the generic HDMI codec.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
v3: no changes
v2: no changes
arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
index a37f3fa223c7..139a76764faa 100644
--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
@@ -132,6 +132,13 @@ memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x80000000>;
};
+
+ sound-hdmi {
+ compatible = "mediatek,mt7623n-hdmi-audio",
+ "mediatek,mt2701-hdmi-audio";
+ mediatek,platform = <&afe>;
+ mediatek,audio-codec = <&hdmi0>;
+ };
};
&bls {
--
2.54.0
^ permalink raw reply related
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