* [PATCH v2 4/6] arm64: dts: imx8mp-evk: add usb3_phy1 tuning properties
From: Xu Yang @ 2026-04-27 8:27 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, jun.li
In-Reply-To: <20260427082728.3641872-1-xu.yang_2@nxp.com>
Add some tuning properties for usb3_phy1 to improve signal.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v2:
- new patch
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 9ffbb5c04f69..9dab374e425a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -909,6 +909,8 @@ usb3_data_hs: endpoint {
};
&usb3_phy1 {
+ fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+ fsl,phy-tx-vref-tune-percent = <116>;
status = "okay";
};
--
2.34.1
^ permalink raw reply related
* Re: [GIT PULL] KVM/arm64 fixes for 7.1, take #1
From: Paolo Bonzini @ 2026-04-27 8:25 UTC (permalink / raw)
To: Marc Zyngier
Cc: Ben Simner, David Woodhouse, Fuad Tabba, Quentin Perret,
Sebastian Ene, Vincent Donnefort, Will Deacon, Joey Gouly,
Suzuki K Poulose, Oliver Upton, Zenghui Yu, kvmarm,
linux-arm-kernel, kvm
In-Reply-To: <20260424151443.750077-1-maz@kernel.org>
On Fri, Apr 24, 2026 at 5:15 PM Marc Zyngier <maz@kernel.org> wrote:
>
> Paolo,
>
> This is the first drop of KVM/arm64 fixes for 7.1. Nothing really
> major so far, but a rather wide range of fixes for idreg handling,
> long standing regressions, SMCCC compliance and more. Add a few
> cleanups to the fix, and that's about it. As usual, gory details in
> the tag below.
>
> Please pull,
Pulled, thanks.
Paolo
> M.
>
> The following changes since commit 94b4ae79ebb42a8a6f2124b4d4b033b15a98e4f9:
>
> Merge branch kvm-arm64/misc-7.1 into kvmarm-master/next (2026-04-08 12:26:11 +0100)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git tags/kvmarm-fixes-7.1-1
>
> for you to fetch changes up to 4ce98bf0865c349e7026ad9c14f48da264920953:
>
> KVM: arm64: Wake-up from WFI when iqrchip is in userspace (2026-04-24 12:03:57 +0100)
>
> ----------------------------------------------------------------
> KVM/arm64 fixes for 7.1, take #1
>
> - Allow tracing for non-pKVM, which was accidentally disabled when
> the series was merged
>
> - Rationalise the way the pKVM hypercall ranges are defined by using
> the same mechanism as already used for the vcpu_sysreg enum
>
> - Enforce that SMCCC function numbers relayed by the pKVM proxy are
> actually compliant with the specification
>
> - Fix a couple of feature to idreg mappings which resulted in the
> wrong sanitisation being applied
>
> - Fix the GICD_IIDR revision number field that could never been
> written correctly by userspace
>
> - Make kvm_vcpu_initialized() correctly use its parameter instead
> of relying on the surrounding context
>
> - Enforce correct ordering in __pkvm_init_vcpu(), plugging a
> potential pin leak at the same time
>
> - Move __pkvm_init_finalise() to a less dangerous spot, avoiding
> future problems
>
> - Restore functional userspace irqchip support after a four year
> breakage (last functional kernel was 5.18...). This is obviously
> ripe for garbage collection.
>
> - ... and the usual lot of spelling fixes
>
> ----------------------------------------------------------------
> David Woodhouse (1):
> KVM: arm64: vgic: Fix IIDR revision field extracted from wrong value
>
> Fuad Tabba (5):
> KVM: arm64: Fix FEAT_Debugv8p9 to check DebugVer, not PMUVer
> KVM: arm64: Fix typo in feature check comments
> KVM: arm64: Fix FEAT_SPE_FnE to use PMSIDR_EL1.FnE, not PMSVer
> KVM: arm64: Fix kvm_vcpu_initialized() macro parameter
> KVM: arm64: Fix pin leak and publication ordering in __pkvm_init_vcpu()
>
> Marc Zyngier (2):
> KVM: arm64: pkvm: Adopt MARKER() to define host hypercall ranges
> KVM: arm64: Wake-up from WFI when iqrchip is in userspace
>
> Quentin Perret (1):
> KVM: arm64: Fix initialisation order in __pkvm_init_finalise()
>
> Sebastian Ene (1):
> KVM: arm64: Reject non compliant SMCCC function calls in pKVM
>
> Vincent Donnefort (1):
> KVM: arm64: Re-allow hyp tracing HVCs for [nh]VHE
>
> arch/arm64/include/asm/kvm_asm.h | 28 ++++++++++++++++++----------
> arch/arm64/include/asm/kvm_host.h | 5 +----
> arch/arm64/kvm/arm.c | 4 ++++
> arch/arm64/kvm/config.c | 23 ++++++++++++++++-------
> arch/arm64/kvm/hyp/nvhe/hyp-main.c | 30 +++++++++++++++++-------------
> arch/arm64/kvm/hyp/nvhe/pkvm.c | 38 +++++++++++++++++++++++++-------------
> arch/arm64/kvm/hyp/nvhe/setup.c | 6 +++---
> arch/arm64/kvm/vgic/vgic-mmio-v2.c | 2 +-
> arch/arm64/kvm/vgic/vgic-mmio-v3.c | 2 +-
> 9 files changed, 86 insertions(+), 52 deletions(-)
>
^ permalink raw reply
* [PATCH v2 3/6] arm64: dts: imx8mp-evk: add typec node
From: Xu Yang @ 2026-04-27 8:27 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, jun.li
In-Reply-To: <20260427082728.3641872-1-xu.yang_2@nxp.com>
The first USB port features a Type-C connector with dual data role
and dual power role capabilities. Add the Type-C device node and
enable the corresponding USB controller and phy node.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v2:
- remove usb3_phy1 tuning property added by mistake
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 69 ++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index d0a2bd975a18..9ffbb5c04f69 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
@@ -636,6 +637,35 @@ adv7535_out: endpoint {
};
};
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ orientation-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+
+ port {
+ typec_con_hs: endpoint {
+ remote-endpoint = <&usb3_data_hs>;
+ };
+ };
+ };
+ };
};
&i2c3 {
@@ -846,6 +876,38 @@ &uart2 {
status = "okay";
};
+&usb3_phy0 {
+ fsl,phy-tx-vref-tune-percent = <122>;
+ fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+ fsl,phy-tx-vboost-level-microvolt = <1156>;
+ fsl,phy-comp-dis-tune-percent = <115>;
+ fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>;
+ fsl,phy-pcs-tx-swing-full-percent = <100>;
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ role-switch-default-mode = "peripheral";
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ status = "okay";
+
+ port {
+ usb3_data_hs: endpoint {
+ remote-endpoint = <&typec_con_hs>;
+ };
+ };
+};
+
&usb3_phy1 {
status = "okay";
};
@@ -1174,6 +1236,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
+ pinctrl_typec: typecgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4
+ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16
+ >;
+ };
+
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/6] arm64: dts: imx8mp: switch usb controller to flattened model
From: Xu Yang @ 2026-04-27 8:27 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, jun.li
In-Reply-To: <20260427082728.3641872-1-xu.yang_2@nxp.com>
Switch to use flattened model for all USB controllers. To enable USB
controllers with restricted DMA access range to work correctly, add a
simple-bus to constrain the DMA address.
Note:
This changes the USB controller compatible string from "fsl,imx8mp-dwc3"
to "nxp,imx8mp-dwc3". This requires a kernel with CONFIG_USB_DWC3_IMX
enabled; otherwise, the new DTB will not be compatible with older one.
See commit 76fc9452a6bf ("usb: dwc3: introduce flatten model driver of
i.MX Soc")
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v2:
- add note in the commit message
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 113 ++++++++++------------
1 file changed, 52 insertions(+), 61 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index cc0246a9c003..8b3aab14ccf1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -2229,67 +2229,6 @@ hdmi_tx_phy: phy@32fdff00 {
};
};
- usb3_0: usb@32f10100 {
- compatible = "fsl,imx8mp-dwc3";
- reg = <0x32f10100 0x8>,
- <0x381f0000 0x20>;
- clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
- <&clk IMX8MP_CLK_USB_SUSP>;
- clock-names = "hsio", "suspend";
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
- #address-cells = <1>;
- #size-cells = <1>;
- dma-ranges = <0x40000000 0x40000000 0xc0000000>;
- ranges;
- status = "disabled";
-
- usb_dwc3_0: usb@38100000 {
- compatible = "snps,dwc3";
- reg = <0x38100000 0x10000>;
- clocks = <&clk IMX8MP_CLK_USB_ROOT>,
- <&clk IMX8MP_CLK_USB_CORE_REF>,
- <&clk IMX8MP_CLK_USB_SUSP>;
- clock-names = "bus_early", "ref", "suspend";
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy0>, <&usb3_phy0>;
- phy-names = "usb2-phy", "usb3-phy";
- snps,gfladj-refclk-lpm-sel-quirk;
- snps,parkmode-disable-ss-quirk;
- };
-
- };
-
- usb3_1: usb@32f10108 {
- compatible = "fsl,imx8mp-dwc3";
- reg = <0x32f10108 0x8>,
- <0x382f0000 0x20>;
- clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
- <&clk IMX8MP_CLK_USB_SUSP>;
- clock-names = "hsio", "suspend";
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
- #address-cells = <1>;
- #size-cells = <1>;
- dma-ranges = <0x40000000 0x40000000 0xc0000000>;
- ranges;
- status = "disabled";
-
- usb_dwc3_1: usb@38200000 {
- compatible = "snps,dwc3";
- reg = <0x38200000 0x10000>;
- clocks = <&clk IMX8MP_CLK_USB_ROOT>,
- <&clk IMX8MP_CLK_USB_CORE_REF>,
- <&clk IMX8MP_CLK_USB_SUSP>;
- clock-names = "bus_early", "ref", "suspend";
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy1>, <&usb3_phy1>;
- phy-names = "usb2-phy", "usb3-phy";
- snps,gfladj-refclk-lpm-sel-quirk;
- snps,parkmode-disable-ss-quirk;
- };
- };
-
pcie0: pcie: pcie@33800000 {
compatible = "fsl,imx8mp-pcie";
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
@@ -2390,6 +2329,58 @@ gpu2d: gpu@38008000 {
power-domains = <&pgc_gpu2d>;
};
+ bus@38100000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+ ranges;
+
+ usb3_0: usb_dwc3_0: usb@38100000 {
+ compatible = "nxp,imx8mp-dwc3";
+ reg = <0x38100000 0x10000>,
+ <0x32f10100 0x8>,
+ <0x381f0000 0x20>;
+ reg-names = "core", "blkctl", "glue";
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_USB_ROOT>,
+ <&clk IMX8MP_CLK_USB_CORE_REF>,
+ <&clk IMX8MP_CLK_USB_SUSP>;
+ clock-names = "hsio", "bus_early", "ref", "suspend";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3", "wakeup";
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
+ phys = <&usb3_phy0>, <&usb3_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,gfladj-refclk-lpm-sel-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "disabled";
+ };
+
+ usb3_1: usb_dwc3_1: usb@38200000 {
+ compatible = "nxp,imx8mp-dwc3";
+ reg = <0x38200000 0x10000>,
+ <0x32f10108 0x8>,
+ <0x382f0000 0x20>;
+ reg-names = "core", "blkctl", "glue";
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_USB_ROOT>,
+ <&clk IMX8MP_CLK_USB_CORE_REF>,
+ <&clk IMX8MP_CLK_USB_SUSP>;
+ clock-names = "hsio", "bus_early", "ref", "suspend";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3", "wakeup";
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
+ phys = <&usb3_phy1>, <&usb3_phy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,gfladj-refclk-lpm-sel-quirk;
+ snps,parkmode-disable-ss-quirk;
+ status = "disabled";
+ };
+ };
+
usb3_phy0: usb-phy@381f0040 {
compatible = "fsl,imx8mp-usb-phy";
reg = <0x381f0040 0x40>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/6] arm64: dts: imx8mp: reorder usb related nodes
From: Xu Yang @ 2026-04-27 8:27 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Frank.Li, s.hauer, kernel, festevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, jun.li
Reorder USB related nodes to improve nodes organization.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
Changes in v2:
- new patch
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 170 +++++++++++-----------
1 file changed, 85 insertions(+), 85 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 90d7bb8f5619..cc0246a9c003 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -2229,6 +2229,67 @@ hdmi_tx_phy: phy@32fdff00 {
};
};
+ usb3_0: usb@32f10100 {
+ compatible = "fsl,imx8mp-dwc3";
+ reg = <0x32f10100 0x8>,
+ <0x381f0000 0x20>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_USB_SUSP>;
+ clock-names = "hsio", "suspend";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+ ranges;
+ status = "disabled";
+
+ usb_dwc3_0: usb@38100000 {
+ compatible = "snps,dwc3";
+ reg = <0x38100000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_USB_ROOT>,
+ <&clk IMX8MP_CLK_USB_CORE_REF>,
+ <&clk IMX8MP_CLK_USB_SUSP>;
+ clock-names = "bus_early", "ref", "suspend";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy0>, <&usb3_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,gfladj-refclk-lpm-sel-quirk;
+ snps,parkmode-disable-ss-quirk;
+ };
+
+ };
+
+ usb3_1: usb@32f10108 {
+ compatible = "fsl,imx8mp-dwc3";
+ reg = <0x32f10108 0x8>,
+ <0x382f0000 0x20>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_USB_SUSP>;
+ clock-names = "hsio", "suspend";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+ ranges;
+ status = "disabled";
+
+ usb_dwc3_1: usb@38200000 {
+ compatible = "snps,dwc3";
+ reg = <0x38200000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_USB_ROOT>,
+ <&clk IMX8MP_CLK_USB_CORE_REF>,
+ <&clk IMX8MP_CLK_USB_SUSP>;
+ clock-names = "bus_early", "ref", "suspend";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy1>, <&usb3_phy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,gfladj-refclk-lpm-sel-quirk;
+ snps,parkmode-disable-ss-quirk;
+ };
+ };
+
pcie0: pcie: pcie@33800000 {
compatible = "fsl,imx8mp-pcie";
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
@@ -2329,6 +2390,30 @@ gpu2d: gpu@38008000 {
power-domains = <&pgc_gpu2d>;
};
+ usb3_phy0: usb-phy@381f0040 {
+ compatible = "fsl,imx8mp-usb-phy";
+ reg = <0x381f0040 0x40>;
+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb3_phy1: usb-phy@382f0040 {
+ compatible = "fsl,imx8mp-usb-phy";
+ reg = <0x382f0040 0x40>;
+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mm-vpu-g1";
reg = <0x38300000 0x10000>;
@@ -2407,91 +2492,6 @@ ddr-pmu@3d800000 {
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
- usb3_phy0: usb-phy@381f0040 {
- compatible = "fsl,imx8mp-usb-phy";
- reg = <0x381f0040 0x40>;
- clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
- clock-names = "phy";
- assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
- power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usb3_0: usb@32f10100 {
- compatible = "fsl,imx8mp-dwc3";
- reg = <0x32f10100 0x8>,
- <0x381f0000 0x20>;
- clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
- <&clk IMX8MP_CLK_USB_SUSP>;
- clock-names = "hsio", "suspend";
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
- #address-cells = <1>;
- #size-cells = <1>;
- dma-ranges = <0x40000000 0x40000000 0xc0000000>;
- ranges;
- status = "disabled";
-
- usb_dwc3_0: usb@38100000 {
- compatible = "snps,dwc3";
- reg = <0x38100000 0x10000>;
- clocks = <&clk IMX8MP_CLK_USB_ROOT>,
- <&clk IMX8MP_CLK_USB_CORE_REF>,
- <&clk IMX8MP_CLK_USB_SUSP>;
- clock-names = "bus_early", "ref", "suspend";
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy0>, <&usb3_phy0>;
- phy-names = "usb2-phy", "usb3-phy";
- snps,gfladj-refclk-lpm-sel-quirk;
- snps,parkmode-disable-ss-quirk;
- };
-
- };
-
- usb3_phy1: usb-phy@382f0040 {
- compatible = "fsl,imx8mp-usb-phy";
- reg = <0x382f0040 0x40>;
- clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
- clock-names = "phy";
- assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
- power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usb3_1: usb@32f10108 {
- compatible = "fsl,imx8mp-dwc3";
- reg = <0x32f10108 0x8>,
- <0x382f0000 0x20>;
- clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
- <&clk IMX8MP_CLK_USB_SUSP>;
- clock-names = "hsio", "suspend";
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
- #address-cells = <1>;
- #size-cells = <1>;
- dma-ranges = <0x40000000 0x40000000 0xc0000000>;
- ranges;
- status = "disabled";
-
- usb_dwc3_1: usb@38200000 {
- compatible = "snps,dwc3";
- reg = <0x38200000 0x10000>;
- clocks = <&clk IMX8MP_CLK_USB_ROOT>,
- <&clk IMX8MP_CLK_USB_CORE_REF>,
- <&clk IMX8MP_CLK_USB_SUSP>;
- clock-names = "bus_early", "ref", "suspend";
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy1>, <&usb3_phy1>;
- phy-names = "usb2-phy", "usb3-phy";
- snps,gfladj-refclk-lpm-sel-quirk;
- snps,parkmode-disable-ss-quirk;
- };
- };
-
dsp: dsp@3b6e8000 {
compatible = "fsl,imx8mp-hifi4";
reg = <0x3b6e8000 0x88000>;
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: thermal: mediatek: Add MT8189 LVTS bindings
From: Rob Herring (Arm) @ 2026-04-27 8:24 UTC (permalink / raw)
To: mtk36707
Cc: Krzysztof Kozlowski, Conor Dooley, AngeloGioacchino Del Regno,
Rafael J . Wysocki, devicetree, Matthias Brugger, Balsam CHIHI,
linux-arm-kernel, vince-wl.liu, Philipp Zabel, justin.yeh,
linux-mediatek, jarried.lin, Daniel Lezcano, Lukasz Luba,
linux-kernel, Zhang Rui, linux-pm
In-Reply-To: <20260427065236.1685057-1-kuanfu.lu@mediatek.com>
On Mon, 27 Apr 2026 14:48:29 +0800, mtk36707 wrote:
> From: Kuanfu Lu <kuanfu.lu@mediatek.com>
>
> Add support for the MediaTek MT8189 LVTS thermal controller to
> the device tree bindings. This includes new compatible strings
> and required properties for MT8189.
>
> Signed-off-by: Kuanfu Lu <kuanfu.lu@mediatek.com>
> ---
> .../thermal/mediatek,lvts-thermal.yaml | 27 +++++++++++++++++--
> .../thermal/mediatek,lvts-thermal.h | 20 ++++++++++++++
> 2 files changed, 45 insertions(+), 2 deletions(-)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml:99:11: [warning] wrong indentation: expected 8 but found 10 (indentation)
./Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml:119:11: [warning] wrong indentation: expected 8 but found 10 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260427065236.1685057-1-kuanfu.lu@mediatek.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH] net: stmmac: fix RX DMA leak on TX alloc failure
From: Maxime Chevallier @ 2026-04-27 8:07 UTC (permalink / raw)
To: dev.taqnialabs, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20260425-stmmac-rx-desc-cleanup-v1-1-1a18a704c422@gmail.com>
On 25/04/2026 14:38, Abid Ali via B4 Relay wrote:
> From: Abid Ali <dev.taqnialabs@gmail.com>
>
> Free RX DMA resources when alloc_dma_tx_desc_resources() fails in
> alloc_dma_desc_resources().
>
> Signed-off-by: Abid Ali <dev.taqnialabs@gmail.com>
> ---
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 13d3cac05..8bb843b55 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -2370,8 +2370,12 @@ static int alloc_dma_desc_resources(struct stmmac_priv *priv,
> return ret;
>
> ret = alloc_dma_tx_desc_resources(priv, dma_conf);
> + if (ret) {
> + free_dma_rx_desc_resources(priv, dma_conf);
> + return ret;
> + }
>
> - return ret;
> + return 0;
> }
This change looks correct, however you're missing a Fixes: tag
indicating when was this issue introduced. You must also indicate what
tree you're targetting (in this case, net) :
Please look here for the process information :
https://docs.kernel.org/process/maintainer-netdev.html
Maxime
>
> /**
>
> ---
> base-commit: 028ef9c96e96197026887c0f092424679298aae8
> change-id: 20260425-stmmac-rx-desc-cleanup-440f05845492
>
> Best regards,
^ permalink raw reply
* [PATCH v2 0/2] arm64: dts: imx8mp-skov: add new 7" variant
From: Steffen Trumtrar @ 2026-04-27 7:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Steffen Trumtrar, devicetree, linux-kernel, imx, linux-arm-kernel
Add a new board variant for the Skov i.MX8MP based family of boards.
This variant uses a different 7" panel than the existing ones.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
Changes in v2:
- rebase to v7.1-rc1
- Link to v1: https://patch.msgid.link/20260325-v7-0-topic-imx8mp-skov-dts-jutouch-7inch-v1-0-10255d236439@pengutronix.de
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Shawn Guo <shawnguo@kernel.org>
To: Frank Li <Frank.Li@nxp.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
To: Pengutronix Kernel Team <kernel@pengutronix.de>
To: Fabio Estevam <festevam@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: imx@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
---
Steffen Trumtrar (2):
dt-bindings: arm: fsl: add compatible for new Skov I.MX8MP variant
arm64: dts: imx8mp-skov: support new 7inch panel board
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../imx8mp-skov-revc-jutouch-jt070tm041.dts | 79 ++++++++++++++++++++++
3 files changed, 81 insertions(+)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20260325-v7-0-topic-imx8mp-skov-dts-jutouch-7inch-3dbcb450a39c
Best regards,
--
Steffen Trumtrar <s.trumtrar@pengutronix.de>
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: imx8mp-skov: support new 7inch panel board
From: Steffen Trumtrar @ 2026-04-27 7:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Steffen Trumtrar, devicetree, linux-kernel, imx, linux-arm-kernel
In-Reply-To: <20260427-v7-0-topic-imx8mp-skov-dts-jutouch-7inch-v2-0-e2b79fc24391@pengutronix.de>
This board is similar to the already upstream
imx8mp-skov-revc-tian-g07017.dts but uses a different 7" panel with a
different touch controller.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../imx8mp-skov-revc-jutouch-jt070tm041.dts | 79 ++++++++++++++++++++++
2 files changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 711e36cc2c990..cc337cc4745bc 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -320,6 +320,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-bd500.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-tian-g07017.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-jutouch-jt070tm041.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-jutouch-jt101tm023.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt070tm041.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt070tm041.dts
new file mode 100644
index 0000000000000..56374f1e67663
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revc-jutouch-jt070tm041.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "imx8mp-skov-reva.dtsi"
+
+/ {
+ model = "SKOV IMX8MP CPU revC - JuTouch JT070TM041";
+ compatible = "skov,imx8mp-skov-revc-jutouch-jt070tm041", "fsl,imx8mp";
+
+ panel {
+ compatible = "jutouch,jt070tm041";
+ backlight = <&backlight>;
+ power-supply = <®_tft_vcom>;
+
+ port {
+ in_lvds0: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+ };
+};
+
+&backlight {
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ touchscreen@2a {
+ compatible = "eeti,exc81w32";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchscreen>;
+ interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <600>;
+ vdd-supply = <®_vdd_3v3>;
+ };
+};
+
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>,
+ <&clk IMX8MP_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+ /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */
+ assigned-clock-rates = <0>, <358400000>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ ldb_lvds_ch0: endpoint {
+ remote-endpoint = <&in_lvds0>;
+ };
+ };
+ };
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+®_tft_vcom {
+ regulator-min-microvolt = <3160000>;
+ regulator-max-microvolt = <3160000>;
+ voltage-table = <3160000 73>;
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: arm: fsl: add compatible for new Skov I.MX8MP variant
From: Steffen Trumtrar @ 2026-04-27 7:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Steffen Trumtrar, devicetree, linux-kernel, imx, linux-arm-kernel
In-Reply-To: <20260427-v7-0-topic-imx8mp-skov-dts-jutouch-7inch-v2-0-e2b79fc24391@pengutronix.de>
In preparation for adding a new device tree variant with a different 7"
panel, describe the DT compatible in the binding.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0023cd1268075..1a0ee5dbb4214 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1139,6 +1139,7 @@ properties:
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
- skov,imx8mp-skov-revc-hdmi # SKOV i.MX8MP climate control without panel
- skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate
+ - skov,imx8mp-skov-revc-jutouch-jt070tm041 # SKOV i.MX8MP climate control with 7" JuTouch panel
- skov,imx8mp-skov-revc-jutouch-jt101tm023 # SKOV i.MX8MP climate control with 10" JuTouch panel
- skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel
- ultratronik,imx8mp-ultra-mach-sbc # Ultratronik SBC i.MX8MP based board
--
2.51.0
^ permalink raw reply related
* [PATCH v1] pmdomain: ti_sci: re-sync TIFS with genpd on resume
From: Vitor Soares @ 2026-04-27 7:48 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Ulf Hansson
Cc: Vitor Soares, linux-arm-kernel, linux-pm, linux-kernel,
Tomi Valkeinen, Kevin Hilman, vishalm, sebin.francis, d-gole,
Devarsh Thakkar, Vignesh Raghavendra, stable
From: Vitor Soares <vitor.soares@toradex.com>
When a device in a TI SCI power domain is on the wakeup path of a
wakeup-capable child, the suspend path skips genpd_sync_power_off().
No put_device is sent to TIFS and the domain's genpd status remains
ON.
TIFS powers off the hardware during deep sleep regardless, since it
was never informed to keep the domain active. On resume, because the
domain's genpd status is ON, no get_device is issued. The driver
then accesses registers of a powered-off domain, causing a
synchronous external abort (AXI bus error, ESR 0x96000010).
Commit 0b5fe1c4ab3c ("pmdomain: ti-sci: Set PD on/off state according
to the HW state") exposed this. Before, domain status was initialized
to OFF, so get_device was always issued on resume.
Add a .resume hook that queries the domain's state from TIFS and
re-syncs TIFS with get_device when genpd has it ON but TIFS has it
OFF. The hook is only registered when the is_on op is available,
since detection depends on it.
Move ti_sci_pm_pd_is_on() earlier in the file so it is available to
the resume hook.
Fixes: 0b5fe1c4ab3c ("pmdomain: ti-sci: Set PD on/off state according to the HW state")
Cc: stable@vger.kernel.org # 6.18+
Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
---
drivers/pmdomain/ti/ti_sci_pm_domains.c | 66 ++++++++++++++++++-------
1 file changed, 49 insertions(+), 17 deletions(-)
diff --git a/drivers/pmdomain/ti/ti_sci_pm_domains.c b/drivers/pmdomain/ti/ti_sci_pm_domains.c
index e5d1934f78d9..ec976d77b818 100644
--- a/drivers/pmdomain/ti/ti_sci_pm_domains.c
+++ b/drivers/pmdomain/ti/ti_sci_pm_domains.c
@@ -131,6 +131,23 @@ static int ti_sci_pd_power_on(struct generic_pm_domain *domain)
return ti_sci->ops.dev_ops.get_device(ti_sci, pd->idx);
}
+static bool ti_sci_pm_pd_is_on(struct ti_sci_genpd_provider *pd_provider,
+ int pd_idx)
+{
+ bool is_on;
+ int ret;
+
+ if (!pd_provider->ti_sci->ops.dev_ops.is_on)
+ return false;
+
+ ret = pd_provider->ti_sci->ops.dev_ops.is_on(pd_provider->ti_sci,
+ pd_idx, NULL, &is_on);
+ if (ret)
+ return false;
+
+ return is_on;
+}
+
#ifdef CONFIG_PM_SLEEP
static int ti_sci_pd_suspend(struct device *dev)
{
@@ -149,8 +166,37 @@ static int ti_sci_pd_suspend(struct device *dev)
return 0;
}
+
+static int ti_sci_pd_resume(struct device *dev)
+{
+ struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain);
+ struct ti_sci_pm_domain *pd = genpd_to_ti_sci_pd(genpd);
+ const struct ti_sci_handle *ti_sci = pd->parent->ti_sci;
+ int ret;
+
+ /*
+ * If genpd's domain state is ON but TIFS powered it OFF during
+ * suspend, re-sync by issuing get_device before the driver resumes.
+ */
+ if (genpd->status == GENPD_STATE_ON &&
+ !ti_sci_pm_pd_is_on(pd->parent, pd->idx)) {
+ dev_dbg(dev, "ti_sci_pd: ID:%d genpd/TIFS out of sync on resume, re-syncing\n",
+ pd->idx);
+ if (pd->exclusive)
+ ret = ti_sci->ops.dev_ops.get_device_exclusive(ti_sci,
+ pd->idx);
+ else
+ ret = ti_sci->ops.dev_ops.get_device(ti_sci, pd->idx);
+ if (ret)
+ return ret;
+ }
+
+ return pm_generic_resume(dev);
+}
+
#else
#define ti_sci_pd_suspend NULL
+#define ti_sci_pd_resume NULL
#endif
/*
@@ -200,23 +246,6 @@ static bool ti_sci_pm_idx_exists(struct ti_sci_genpd_provider *pd_provider, u32
return false;
}
-static bool ti_sci_pm_pd_is_on(struct ti_sci_genpd_provider *pd_provider,
- int pd_idx)
-{
- bool is_on;
- int ret;
-
- if (!pd_provider->ti_sci->ops.dev_ops.is_on)
- return false;
-
- ret = pd_provider->ti_sci->ops.dev_ops.is_on(pd_provider->ti_sci,
- pd_idx, NULL, &is_on);
- if (ret)
- return false;
-
- return is_on;
-}
-
static int ti_sci_pm_domain_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -283,6 +312,9 @@ static int ti_sci_pm_domain_probe(struct platform_device *pdev)
pd_provider->ti_sci->ops.pm_ops.set_latency_constraint)
pd->pd.domain.ops.suspend = ti_sci_pd_suspend;
+ if (pd_provider->ti_sci->ops.dev_ops.is_on)
+ pd->pd.domain.ops.resume = ti_sci_pd_resume;
+
is_on = ti_sci_pm_pd_is_on(pd_provider,
pd->idx);
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v8 0/2] arm64: dts/defconfig: enable BST C1200 eMMC
From: Albert Yang @ 2026-04-27 7:46 UTC (permalink / raw)
To: krzk
Cc: arnd, bst-upstream, catalin.marinas, conor+dt, devicetree,
gordon.ge, krzk+dt, linux-arm-kernel, linux-kernel, robh, will,
yangzh0906
In-Reply-To: <d78e5b19-c380-4fd6-9ae7-e2b20b74474f@kernel.org>
On 27/04/2026 08:36, Krzysztof Kozlowski wrote:
> You sent it already three times within one hour. Please stop.
Apologies for the noise. Sending is stopped on my side and the root
cause is still under investigation. Please use the canonical v8 for
review:
https://lore.kernel.org/r/20260427055555.3693459-1-yangzh0906@thundersoft.com
Thanks,
Albert
^ permalink raw reply
* Re: [PATCH] iio: adc: meson-saradc: fix calibration buffer leak on error
From: Andy Shevchenko @ 2026-04-27 7:44 UTC (permalink / raw)
To: Felix Gu
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rosen Penev, linux-iio, linux-arm-kernel, linux-amlogic,
linux-kernel
In-Reply-To: <20260426-meson_saradc-v1-1-6e96b2982c43@gmail.com>
On Sun, Apr 26, 2026 at 12:07:24AM +0800, Felix Gu wrote:
> meson_sar_adc_temp_sensor_init() allocates a buffer with
> nvmem_cell_read(), but the old code leaked it if
> syscon_regmap_lookup_by_phandle() failed.
> Switch buf to __free(kfree) so all return paths release it.
__free() is defined in cleanup.h which is missing in the driver. Please add the
include to it.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v8 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks
From: Yingchao Deng (Consultant) @ 2026-04-27 7:42 UTC (permalink / raw)
To: Jie Gan, Yingchao Deng, Suzuki K Poulose, Mike Leach, James Clark,
Leo Yan, Alexander Shishkin
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
Jinlong Mao, Tingwei Zhang, Yingchao Deng
In-Reply-To: <337789c5-7311-4613-9daf-915fcae0c6fc@oss.qualcomm.com>
On 4/27/2026 3:39 PM, Jie Gan wrote:
>
>
> On 4/26/2026 5:44 PM, Yingchao Deng wrote:
>> Qualcomm implements an extended variant of the ARM CoreSight CTI with a
>> different register layout and vendor-specific behavior. While the
>> programming model remains largely compatible, the register offsets
>> differ
>> from the standard ARM CTI and require explicit handling.
>>
>> Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI
>> driver data. Introduce a small mapping layer to translate standard CTI
>> register offsets to Qualcomm-specific offsets, allowing the rest of the
>> driver to use a common register access path.
>>
>> Additionally, handle a Qualcomm-specific quirk where the CLAIMSET
>> register is incorrectly initialized to a non-zero value, which can cause
>> tools or drivers to assume the component is already claimed. Clear the
>> register during probe to reflect the actual unclaimed state.
>>
>> No functional change is intended for standard ARM CTI devices.
>>
>> Co-developed-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
>> Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
>> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
>> ---
>> drivers/hwtracing/coresight/coresight-cti-core.c | 28 +++++++++-
>> drivers/hwtracing/coresight/coresight-cti.h | 4 +-
>> drivers/hwtracing/coresight/qcom-cti.h | 65
>> ++++++++++++++++++++++++
>> 3 files changed, 95 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c
>> b/drivers/hwtracing/coresight/coresight-cti-core.c
>> index c4cbeb64365b..b1c69a3e9b99 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-cti-core.c
>> @@ -21,6 +21,7 @@
>> #include "coresight-priv.h"
>> #include "coresight-cti.h"
>> +#include "qcom-cti.h"
>> /*
>> * CTI devices can be associated with a PE, or be connected to
>> CoreSight
>> @@ -47,6 +48,10 @@ static void __iomem *cti_reg_addr(struct
>> cti_drvdata *drvdata, int reg)
>> u32 offset = CTI_REG_CLR_NR(reg);
>> u32 nr = CTI_REG_GET_NR(reg);
>> + /* convert to qcom specific offset */
>> + if (unlikely(drvdata->is_qcom_cti))
>
> I prefer to drop the unlikely here, let the cpu do the branch predictor.
>
>> + offset = cti_qcom_reg_off(offset);
>> +
>> return drvdata->base + offset + sizeof(u32) * nr;
>> }
>> @@ -170,6 +175,9 @@ void cti_write_intack(struct device *dev, u32
>> ackval)
>> /* DEVID[19:16] - number of CTM channels */
>> #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val,
>> 16, 19))
>> +/* DEVARCH[31:21] - ARCHITECT */
>> +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val,
>> 21, 31))
>> +
>> static int cti_set_default_config(struct device *dev,
>> struct cti_drvdata *drvdata)
>> {
>> @@ -700,6 +708,7 @@ static int cti_probe(struct amba_device *adev,
>> const struct amba_id *id)
>> struct coresight_desc cti_desc;
>> struct coresight_platform_data *pdata = NULL;
>> struct resource *res = &adev->res;
>> + u32 devarch;
>> /* driver data*/
>> drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>> @@ -724,6 +733,22 @@ static int cti_probe(struct amba_device *adev,
>> const struct amba_id *id)
>> raw_spin_lock_init(&drvdata->spinlock);
>> + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH);
>> + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) {
>> + drvdata->is_qcom_cti = true;
>> + /*
>> + * QCOM CTI does not implement Claimtag functionality as
>> + * per CoreSight specification, but its CLAIMSET register
>> + * is incorrectly initialized to 0xF. This can mislead
>> + * tools or drivers into thinking the component is claimed.
>> + *
>> + * Reset CLAIMSET to 0 to reflect that no claims are active.
>> + */
>> + CS_UNLOCK(drvdata->base);
>> + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET);
>> + CS_LOCK(drvdata->base);
>> + }
>> +
>> /* initialise CTI driver config values */
>> ret = cti_set_default_config(dev, drvdata);
>> if (ret)
>> @@ -780,7 +805,8 @@ static int cti_probe(struct amba_device *adev,
>> const struct amba_id *id)
>> /* all done - dec pm refcount */
>> pm_runtime_put(&adev->dev);
>> - dev_info(&drvdata->csdev->dev, "CTI initialized\n");
>> + dev_info(&drvdata->csdev->dev,
>> + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : "");
>> return 0;
>> }
>> diff --git a/drivers/hwtracing/coresight/coresight-cti.h
>> b/drivers/hwtracing/coresight/coresight-cti.h
>> index dd1ba44518c4..2598601e7b93 100644
>> --- a/drivers/hwtracing/coresight/coresight-cti.h
>> +++ b/drivers/hwtracing/coresight/coresight-cti.h
>> @@ -55,10 +55,11 @@ struct fwnode_handle;
>> /*
>> * CTI CSSoc 600 has a max of 32 trigger signals per direction.
>> * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
>> + * QCOM CTI supports up to 128 trigger signals per direction.
>> * Max of in and out defined in the DEVID register.
>> * - pick up actual number used from .dts parameters if present.
>> */
>> -#define CTIINOUTEN_MAX 32
>> +#define CTIINOUTEN_MAX 128
>> /*
>> * Encode CTI register offset and register index in one u32:
>> @@ -188,6 +189,7 @@ struct cti_drvdata {
>> raw_spinlock_t spinlock;
>> struct cti_config config;
>> struct list_head node;
>> + bool is_qcom_cti;
>
> missed document.
>
> Thanks,
> Jie
>
will update.
Thanks,
Yingchao
>> };
>> /*
>> diff --git a/drivers/hwtracing/coresight/qcom-cti.h
>> b/drivers/hwtracing/coresight/qcom-cti.h
>> new file mode 100644
>> index 000000000000..fd1bf07d7cb4
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/qcom-cti.h
>> @@ -0,0 +1,65 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +
>> +#ifndef _CORESIGHT_QCOM_CTI_H
>> +#define _CORESIGHT_QCOM_CTI_H
>> +
>> +#include "coresight-cti.h"
>> +
>> +#define ARCHITECT_QCOM 0x477
>> +
>> +/* CTI programming registers */
>> +#define QCOM_CTIINTACK 0x020
>> +#define QCOM_CTIAPPSET 0x004
>> +#define QCOM_CTIAPPCLEAR 0x008
>> +#define QCOM_CTIAPPPULSE 0x00C
>> +#define QCOM_CTIINEN 0x400
>> +#define QCOM_CTIOUTEN 0x800
>> +#define QCOM_CTITRIGINSTATUS 0x040
>> +#define QCOM_CTITRIGOUTSTATUS 0x060
>> +#define QCOM_CTICHINSTATUS 0x080
>> +#define QCOM_CTICHOUTSTATUS 0x084
>> +#define QCOM_CTIGATE 0x088
>> +#define QCOM_ASICCTL 0x08C
>> +/* Integration test registers */
>> +#define QCOM_ITCHINACK 0xE70
>> +#define QCOM_ITTRIGINACK 0xE80
>> +#define QCOM_ITCHOUT 0xE74
>> +#define QCOM_ITTRIGOUT 0xEA0
>> +#define QCOM_ITCHOUTACK 0xE78
>> +#define QCOM_ITTRIGOUTACK 0xEC0
>> +#define QCOM_ITCHIN 0xE7C
>> +#define QCOM_ITTRIGIN 0xEE0
>> +
>> +static noinline u32 cti_qcom_reg_off(u32 offset)
>> +{
>> + switch (offset) {
>> + case CTIINTACK: return QCOM_CTIINTACK;
>> + case CTIAPPSET: return QCOM_CTIAPPSET;
>> + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR;
>> + case CTIAPPPULSE: return QCOM_CTIAPPPULSE;
>> + case CTIINEN: return QCOM_CTIINEN;
>> + case CTIOUTEN: return QCOM_CTIOUTEN;
>> + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS;
>> + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS;
>> + case CTICHINSTATUS: return QCOM_CTICHINSTATUS;
>> + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS;
>> + case CTIGATE: return QCOM_CTIGATE;
>> + case ASICCTL: return QCOM_ASICCTL;
>> + case ITCHINACK: return QCOM_ITCHINACK;
>> + case ITTRIGINACK: return QCOM_ITTRIGINACK;
>> + case ITCHOUT: return QCOM_ITCHOUT;
>> + case ITTRIGOUT: return QCOM_ITTRIGOUT;
>> + case ITCHOUTACK: return QCOM_ITCHOUTACK;
>> + case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK;
>> + case ITCHIN: return QCOM_ITCHIN;
>> + case ITTRIGIN: return QCOM_ITTRIGIN;
>> +
>> + default:
>> + return offset;
>> + }
>> +}
>> +
>> +#endif /* _CORESIGHT_QCOM_CTI_H */
>>
>
^ permalink raw reply
* Re: [REGRESSION] rseq: refactoring in v6.19 broke everyone on arm64 and tcmalloc everywhere
From: Florian Weimer @ 2026-04-27 7:40 UTC (permalink / raw)
To: Thomas Gleixner
Cc: Peter Zijlstra, Mathias Stearn, Dmitry Vyukov, Jinjie Ruan,
linux-man, Mark Rutland, Mathieu Desnoyers, Catalin Marinas,
Will Deacon, Boqun Feng, Paul E. McKenney, Chris Kennelly,
regressions, linux-kernel, linux-arm-kernel, Ingo Molnar,
Blake Oler, Rich Felker, Matthew Wilcox, Greg Kroah-Hartman,
Linus Torvalds, criu
In-Reply-To: <87jyttz8cf.ffs@tglx>
* Thomas Gleixner:
> The real question is how to differentiate between the legacy and the
> optimized mode. I have two working variants to achieve that:
>
> 1) The fully safe option requires a new flag for RSEQ
> registration. It obviously requires a glibc update. (Suggested by
> PeterZ)
Without glibc changes, RSEQ would keep working, but with the old,
problematic performance, right?
If we don't have a notification in the auxiliary vector, we'd have to do
two system calls at process start, which isn't ideal, but is probably
not a significant issue, either.
I haven't verified this, but it looks like introducing the flag breaks
CRIU? In dump_thread_rseq, we have this:
if (rseqc.flags != 0) {
pr_err("something wrong with ptrace(PTRACE_GET_RSEQ_CONFIGURATION, %d) flags = 0x%x\n", tid,
rseqc.flags);
return -1;
}
I suppose a workaround could make this behavior flag a prctl flag. CRIU
wouldn't dump and restore that until taught about it. If the new
behavior is switched on explicitly by the flag, it would be
backwards-compatible, except that restoring with unpatched CRIU would
lead to a performance loss.
> 2) Determine the requirements of the registering task via the size of
> the registered RSEQ area.
>
> The original implementation, which TCMalloc depends on, registers
> a 32 byte region (ORIG_RSEG_SIZE). This region has 32 byte
> alignment requirement.
>
> The extension safe newer variant exposes the kernel RSEQ feature
> size via getauxval(AT_RSEQ_FEATURE_SIZE) and the alignment
> requirement via getauxval(AT_RSEQ_ALIGN). The alignment
> requirement is that the registered rseq region is aligned to the
> next power of two of the feature size. The kernel currently has a
> feature size of 33 bytes, which means the alignment requirement is
> 64 bytes.
There are still glibc builds in use that do not use AT_RSEQ_ALIGN, and
instead unconditionally reserve a size of 32. In some builds, the RSEQ
area is not aligned to a multiple of 64, which makes glibc
indistinguishable from tcmalloc. You could look at the location of the
thread pointer relative to the RSEQ area at registration to tell them
apart, but that is perhaps too nasty.
Switching to the new extensible RSEQ allocation code in older glibc
builds is not entirely trivial, and I would prefer not doing that.
Registering with a new flag is comparatively simple, and we could
backport it, except that it might not be compatible with CRIU.
Thanks,
Florian
^ permalink raw reply
* Re: [PATCH v8 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks
From: Jie Gan @ 2026-04-27 7:39 UTC (permalink / raw)
To: Yingchao Deng, Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
quic_yingdeng, Jinlong Mao, Tingwei Zhang
In-Reply-To: <20260426-extended-cti-v8-3-23b900a4902f@oss.qualcomm.com>
On 4/26/2026 5:44 PM, Yingchao Deng wrote:
> Qualcomm implements an extended variant of the ARM CoreSight CTI with a
> different register layout and vendor-specific behavior. While the
> programming model remains largely compatible, the register offsets differ
> from the standard ARM CTI and require explicit handling.
>
> Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI
> driver data. Introduce a small mapping layer to translate standard CTI
> register offsets to Qualcomm-specific offsets, allowing the rest of the
> driver to use a common register access path.
>
> Additionally, handle a Qualcomm-specific quirk where the CLAIMSET
> register is incorrectly initialized to a non-zero value, which can cause
> tools or drivers to assume the component is already claimed. Clear the
> register during probe to reflect the actual unclaimed state.
>
> No functional change is intended for standard ARM CTI devices.
>
> Co-developed-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> Signed-off-by: Jinlong Mao <jinlong.mao@oss.qualcomm.com>
> Signed-off-by: Yingchao Deng <yingchao.deng@oss.qualcomm.com>
> ---
> drivers/hwtracing/coresight/coresight-cti-core.c | 28 +++++++++-
> drivers/hwtracing/coresight/coresight-cti.h | 4 +-
> drivers/hwtracing/coresight/qcom-cti.h | 65 ++++++++++++++++++++++++
> 3 files changed, 95 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
> index c4cbeb64365b..b1c69a3e9b99 100644
> --- a/drivers/hwtracing/coresight/coresight-cti-core.c
> +++ b/drivers/hwtracing/coresight/coresight-cti-core.c
> @@ -21,6 +21,7 @@
>
> #include "coresight-priv.h"
> #include "coresight-cti.h"
> +#include "qcom-cti.h"
>
> /*
> * CTI devices can be associated with a PE, or be connected to CoreSight
> @@ -47,6 +48,10 @@ static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg)
> u32 offset = CTI_REG_CLR_NR(reg);
> u32 nr = CTI_REG_GET_NR(reg);
>
> + /* convert to qcom specific offset */
> + if (unlikely(drvdata->is_qcom_cti))
I prefer to drop the unlikely here, let the cpu do the branch predictor.
> + offset = cti_qcom_reg_off(offset);
> +
> return drvdata->base + offset + sizeof(u32) * nr;
> }
>
> @@ -170,6 +175,9 @@ void cti_write_intack(struct device *dev, u32 ackval)
> /* DEVID[19:16] - number of CTM channels */
> #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19))
>
> +/* DEVARCH[31:21] - ARCHITECT */
> +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31))
> +
> static int cti_set_default_config(struct device *dev,
> struct cti_drvdata *drvdata)
> {
> @@ -700,6 +708,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
> struct coresight_desc cti_desc;
> struct coresight_platform_data *pdata = NULL;
> struct resource *res = &adev->res;
> + u32 devarch;
>
> /* driver data*/
> drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> @@ -724,6 +733,22 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
>
> raw_spin_lock_init(&drvdata->spinlock);
>
> + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH);
> + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) {
> + drvdata->is_qcom_cti = true;
> + /*
> + * QCOM CTI does not implement Claimtag functionality as
> + * per CoreSight specification, but its CLAIMSET register
> + * is incorrectly initialized to 0xF. This can mislead
> + * tools or drivers into thinking the component is claimed.
> + *
> + * Reset CLAIMSET to 0 to reflect that no claims are active.
> + */
> + CS_UNLOCK(drvdata->base);
> + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET);
> + CS_LOCK(drvdata->base);
> + }
> +
> /* initialise CTI driver config values */
> ret = cti_set_default_config(dev, drvdata);
> if (ret)
> @@ -780,7 +805,8 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
>
> /* all done - dec pm refcount */
> pm_runtime_put(&adev->dev);
> - dev_info(&drvdata->csdev->dev, "CTI initialized\n");
> + dev_info(&drvdata->csdev->dev,
> + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : "");
> return 0;
> }
>
> diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h
> index dd1ba44518c4..2598601e7b93 100644
> --- a/drivers/hwtracing/coresight/coresight-cti.h
> +++ b/drivers/hwtracing/coresight/coresight-cti.h
> @@ -55,10 +55,11 @@ struct fwnode_handle;
> /*
> * CTI CSSoc 600 has a max of 32 trigger signals per direction.
> * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def.
> + * QCOM CTI supports up to 128 trigger signals per direction.
> * Max of in and out defined in the DEVID register.
> * - pick up actual number used from .dts parameters if present.
> */
> -#define CTIINOUTEN_MAX 32
> +#define CTIINOUTEN_MAX 128
>
> /*
> * Encode CTI register offset and register index in one u32:
> @@ -188,6 +189,7 @@ struct cti_drvdata {
> raw_spinlock_t spinlock;
> struct cti_config config;
> struct list_head node;
> + bool is_qcom_cti;
missed document.
Thanks,
Jie
> };
>
> /*
> diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h
> new file mode 100644
> index 000000000000..fd1bf07d7cb4
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/qcom-cti.h
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#ifndef _CORESIGHT_QCOM_CTI_H
> +#define _CORESIGHT_QCOM_CTI_H
> +
> +#include "coresight-cti.h"
> +
> +#define ARCHITECT_QCOM 0x477
> +
> +/* CTI programming registers */
> +#define QCOM_CTIINTACK 0x020
> +#define QCOM_CTIAPPSET 0x004
> +#define QCOM_CTIAPPCLEAR 0x008
> +#define QCOM_CTIAPPPULSE 0x00C
> +#define QCOM_CTIINEN 0x400
> +#define QCOM_CTIOUTEN 0x800
> +#define QCOM_CTITRIGINSTATUS 0x040
> +#define QCOM_CTITRIGOUTSTATUS 0x060
> +#define QCOM_CTICHINSTATUS 0x080
> +#define QCOM_CTICHOUTSTATUS 0x084
> +#define QCOM_CTIGATE 0x088
> +#define QCOM_ASICCTL 0x08C
> +/* Integration test registers */
> +#define QCOM_ITCHINACK 0xE70
> +#define QCOM_ITTRIGINACK 0xE80
> +#define QCOM_ITCHOUT 0xE74
> +#define QCOM_ITTRIGOUT 0xEA0
> +#define QCOM_ITCHOUTACK 0xE78
> +#define QCOM_ITTRIGOUTACK 0xEC0
> +#define QCOM_ITCHIN 0xE7C
> +#define QCOM_ITTRIGIN 0xEE0
> +
> +static noinline u32 cti_qcom_reg_off(u32 offset)
> +{
> + switch (offset) {
> + case CTIINTACK: return QCOM_CTIINTACK;
> + case CTIAPPSET: return QCOM_CTIAPPSET;
> + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR;
> + case CTIAPPPULSE: return QCOM_CTIAPPPULSE;
> + case CTIINEN: return QCOM_CTIINEN;
> + case CTIOUTEN: return QCOM_CTIOUTEN;
> + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS;
> + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS;
> + case CTICHINSTATUS: return QCOM_CTICHINSTATUS;
> + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS;
> + case CTIGATE: return QCOM_CTIGATE;
> + case ASICCTL: return QCOM_ASICCTL;
> + case ITCHINACK: return QCOM_ITCHINACK;
> + case ITTRIGINACK: return QCOM_ITTRIGINACK;
> + case ITCHOUT: return QCOM_ITCHOUT;
> + case ITTRIGOUT: return QCOM_ITTRIGOUT;
> + case ITCHOUTACK: return QCOM_ITCHOUTACK;
> + case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK;
> + case ITCHIN: return QCOM_ITCHIN;
> + case ITTRIGIN: return QCOM_ITTRIGIN;
> +
> + default:
> + return offset;
> + }
> +}
> +
> +#endif /* _CORESIGHT_QCOM_CTI_H */
>
^ permalink raw reply
* [PATCH net-next v7 4/4] riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet controller
From: lizhi2 @ 2026-04-27 7:26 UTC (permalink / raw)
To: devicetree, andrew+netdev, davem, edumazet, kuba, robh, krzk+dt,
conor+dt, netdev, pabeni, mcoquelin.stm32, alexandre.torgue,
rmk+kernel, pjw, palmer, aou, alex, linux-riscv, linux-stm32,
linux-arm-kernel, linux-kernel, maxime.chevallier
Cc: ningyu, linmin, pinkesh.vaghela, pritesh.patel, weishangjuan,
horms, Zhi Li
In-Reply-To: <20260427072353.1114-1-lizhi2@eswincomputing.com>
From: Zhi Li <lizhi2@eswincomputing.com>
Enable the on-board Gigabit Ethernet controller on the
HiFive Premier P550 development board.
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
---
.../dts/eswin/eic7700-hifive-premier-p550.dts | 239 ++++++++++++++++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 105 ++++++++
2 files changed, 344 insertions(+)
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
index 131ed1fc6b2e..4e09ad738d3d 100644
--- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -13,11 +13,250 @@ / {
aliases {
serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ vcc_1v8: vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&xtal24m {
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal24m";
+};
+
+&pinctrl {
+ status = "okay";
+ vrgmii-supply = <&vcc_1v8>;
+
+ pinctrl_gpio0: gpio0-grp {
+ gpio0-pins {
+ pins = "gpio0";
+ function = "gpio";
+ input-enable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio5: gpio5-grp {
+ gpio5-pins {
+ pins = "gpio5";
+ function = "gpio";
+ input-enable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio11: gpio11-grp {
+ gpio11-pins {
+ pins = "gpio11";
+ function = "gpio";
+ input-enable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio14: gpio14-grp {
+ gpio14-pins {
+ pins = "mode_set1";
+ function = "gpio";
+ input-disable;
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_gpio15: gpio15-grp {
+ gpio15-pins {
+ pins = "mode_set2";
+ function = "gpio";
+ input-enable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio28: gpio28-grp {
+ gpio28-pins {
+ pins = "gpio28";
+ function = "gpio";
+ input-enable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio43: gpio43-grp {
+ gpio43-pins {
+ pins = "usb1_pwren";
+ function = "gpio";
+ input-disable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio71: gpio71-grp {
+ gpio71-pins {
+ pins = "mipi_csi0_xhs";
+ function = "gpio";
+ input-disable;
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_gpio74: gpio74-grp {
+ gpio74-pins {
+ pins = "mipi_csi1_xhs";
+ function = "gpio";
+ input-disable;
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_gpio76: gpio76-grp {
+ gpio76-pins {
+ pins = "mipi_csi2_xvs";
+ function = "gpio";
+ input-disable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio77: gpio77-grp {
+ gpio77-pins {
+ pins = "mipi_csi2_xhs";
+ function = "gpio";
+ input-disable;
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_gpio79: gpio79-grp {
+ gpio79-pins {
+ pins = "mipi_csi3_xvs";
+ function = "gpio";
+ input-disable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio80: gpio80-grp {
+ gpio80-pins {
+ pins = "mipi_csi3_xhs";
+ function = "gpio";
+ input-disable;
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_gpio82: gpio82-grp {
+ gpio82-pins {
+ pins = "mipi_csi4_xvs";
+ function = "gpio";
+ input-disable;
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_gpio84: gpio84-grp {
+ gpio84-pins {
+ pins = "mipi_csi4_mclk";
+ function = "gpio";
+ input-disable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio85: gpio85-grp {
+ gpio85-pins {
+ pins = "mipi_csi5_xvs";
+ function = "gpio";
+ input-disable;
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_gpio94: gpio94-grp {
+ gpio94-pins {
+ pins = "s_mode";
+ function = "gpio";
+ input-disable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio106: gpio106-grp {
+ gpio106-pins {
+ pins = "gpio106";
+ function = "gpio";
+ input-disable;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio111: gpio111-grp {
+ gpio111-pins {
+ pins = "gpio111";
+ function = "gpio";
+ input-disable;
+ bias-disable;
+ };
+ };
+};
+
+&gmac0 {
+ phy-handle = <&gmac0_phy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio106>;
+ rx-internal-delay-ps = <20>;
+ tx-internal-delay-ps = <100>;
+ status = "okay";
+};
+
+&gmac0_mdio {
+ gmac0_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0>;
+ reset-gpios = <&gpioD 10 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ };
+};
+
+&gmac1 {
+ phy-handle = <&gmac1_phy0>;
+ /*
+ * For the TX path of gmac1, there is a skew between the TX clock
+ * and data on the MAC controller inside the silicon. This skew happens
+ * to be approximately 2 ns. Therefore, it can be considered that the
+ * 2 ns delay of TX is provided by the MAC.
+ * No delay configuration for tx is needed in software via PHY driver.
+ */
+ phy-mode = "rgmii-rxid";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio111>;
+ rx-internal-delay-ps = <200>;
+ tx-internal-delay-ps = <200>;
+ status = "okay";
+};
+
+&gmac1_mdio {
+ gmac1_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0>;
+ reset-gpios = <&gpioD 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ };
};
&uart0 {
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
index c3ed93008bca..c77bc8b1b7bc 100644
--- a/arch/riscv/boot/dts/eswin/eic7700.dtsi
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -5,6 +5,9 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/eswin,eic7700-reset.h>
+
/ {
#address-cells = <2>;
#size-cells = <2>;
@@ -202,6 +205,11 @@ pmu {
<0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
};
+ xtal24m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
ranges;
@@ -245,6 +253,85 @@ plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
};
+ hsp_power_domain: bus@50400000 {
+ compatible = "simple-pm-bus";
+ ranges;
+ clocks = <&clk 171>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ hsp_sp_csr: hsp-sp-top-csr@50440000 {
+ compatible = "eswin,eic7700-syscfg", "syscon";
+ reg = <0x0 0x50440000 0x0 0x2000>;
+ };
+
+ gmac0: ethernet@50400000 {
+ compatible = "eswin,eic7700-qos-eth",
+ "snps,dwmac-5.20";
+ reg = <0x0 0x50400000 0x0 0x10000>;
+ interrupts = <61>;
+ interrupt-names = "macirq";
+ clocks = <&clk 186>,
+ <&clk 171>,
+ <&clk 40>,
+ <&clk 193>;
+ clock-names = "axi", "cfg", "stmmaceth", "tx";
+ resets = <&reset EIC7700_RESET_HSP_ETH0_ARST>;
+ reset-names = "stmmaceth";
+ eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>;
+ snps,aal;
+ snps,fixed-burst;
+ snps,tso;
+ snps,axi-config = <&stmmac_axi_setup_gmac0>;
+ status = "disabled";
+
+ gmac0_mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ stmmac_axi_setup_gmac0: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <2>;
+ snps,wr_osr_lmt = <2>;
+ };
+ };
+
+ gmac1: ethernet@50410000 {
+ compatible = "eswin,eic7700-qos-eth-clk-inversion",
+ "snps,dwmac-5.20";
+ reg = <0x0 0x50410000 0x0 0x10000>;
+ interrupts = <70>;
+ interrupt-names = "macirq";
+ clocks = <&clk 186>,
+ <&clk 171>,
+ <&clk 40>,
+ <&clk 194>;
+ clock-names = "axi", "cfg", "stmmaceth", "tx";
+ resets = <&reset EIC7700_RESET_HSP_ETH1_ARST>;
+ reset-names = "stmmaceth";
+ eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x218 0x214 0x21c>;
+ snps,aal;
+ snps,fixed-burst;
+ snps,tso;
+ snps,axi-config = <&stmmac_axi_setup_gmac1>;
+ status = "disabled";
+
+ gmac1_mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ stmmac_axi_setup_gmac1: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <2>;
+ snps,wr_osr_lmt = <2>;
+ };
+ };
+ };
+
uart0: serial@50900000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x50900000 0x0 0x10000>;
@@ -341,5 +428,23 @@ gpioD: gpio-port@3 {
#gpio-cells = <2>;
};
};
+
+ pinctrl: pinctrl@51600080 {
+ compatible = "eswin,eic7700-pinctrl";
+ reg = <0x0 0x51600080 0x0 0x1fff80>;
+ };
+
+ clk: clock-controller@51828000 {
+ compatible = "eswin,eic7700-clock";
+ reg = <0x0 0x51828000 0x0 0x300>;
+ clocks = <&xtal24m>;
+ #clock-cells = <1>;
+ };
+
+ reset: reset-controller@51828300 {
+ compatible = "eswin,eic7700-reset";
+ reg = <0x0 0x51828300 0x0 0x200>;
+ #reset-cells = <1>;
+ };
};
};
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v7 3/4] dt-bindings: mfd: syscon: add ESWIN EIC7700 compatible
From: lizhi2 @ 2026-04-27 7:25 UTC (permalink / raw)
To: devicetree, andrew+netdev, davem, edumazet, kuba, robh, krzk+dt,
conor+dt, netdev, pabeni, mcoquelin.stm32, alexandre.torgue,
rmk+kernel, pjw, palmer, aou, alex, linux-riscv, linux-stm32,
linux-arm-kernel, linux-kernel, maxime.chevallier
Cc: ningyu, linmin, pinkesh.vaghela, pritesh.patel, weishangjuan,
horms, Zhi Li
In-Reply-To: <20260427072353.1114-1-lizhi2@eswincomputing.com>
From: Zhi Li <lizhi2@eswincomputing.com>
Document ESWIN EIC7700 SoC compatible for syscon registers.
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index e22867088063..7d3365601249 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -62,6 +62,7 @@ select:
- cirrus,ep7209-syscon3
- cnxt,cx92755-uc
- econet,en751221-chip-scu
+ - eswin,eic7700-syscfg
- freecom,fsg-cs2-system-controller
- fsl,imx93-aonmix-ns-syscfg
- fsl,imx93-wakeupmix-syscfg
@@ -175,6 +176,7 @@ properties:
- cirrus,ep7209-syscon3
- cnxt,cx92755-uc
- econet,en751221-chip-scu
+ - eswin,eic7700-syscfg
- freecom,fsg-cs2-system-controller
- fsl,imx93-aonmix-ns-syscfg
- fsl,imx93-wakeupmix-syscfg
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v7 2/4] net: stmmac: eic7700: enable clocks before syscon access and correct RX sampling timing
From: lizhi2 @ 2026-04-27 7:25 UTC (permalink / raw)
To: devicetree, andrew+netdev, davem, edumazet, kuba, robh, krzk+dt,
conor+dt, netdev, pabeni, mcoquelin.stm32, alexandre.torgue,
rmk+kernel, pjw, palmer, aou, alex, linux-riscv, linux-stm32,
linux-arm-kernel, linux-kernel, maxime.chevallier
Cc: ningyu, linmin, pinkesh.vaghela, pritesh.patel, weishangjuan,
horms, Zhi Li
In-Reply-To: <20260427072353.1114-1-lizhi2@eswincomputing.com>
From: Zhi Li <lizhi2@eswincomputing.com>
The second Ethernet controller (eth1) on the Eswin EIC7700 SoC may fail
to sample RX data correctly at Gigabit speed due to EIC7700-specific
receive clock to data skew at the MAC input in the silicon.
The existing internal delay configuration does not provide sufficient
adjustment range to compensate for this condition at 1000Mbps.
Update the EIC7700 DWMAC glue driver to apply EIC7700-specific clock
sampling inversion only during Gigabit operation on MAC instances
that require it.
TXD and RXD delay registers are explicitly cleared during initialization
to override any residual configuration left by the bootloader. All HSP
CSR register accesses are performed only after the required clocks are
enabled.
Fixes: ea77dbbdbc4e ("net: stmmac: add Eswin EIC7700 glue driver")
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
---
.../ethernet/stmicro/stmmac/dwmac-eic7700.c | 183 ++++++++++++++----
1 file changed, 140 insertions(+), 43 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
index bcb8e000e720..33144611da8d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c
@@ -28,20 +28,40 @@
/*
* TX/RX Clock Delay Bit Masks:
- * - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.1ns per bit)
- * - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.1ns per bit)
+ * - TX Delay: bits [14:8] — TX_CLK delay (unit: 0.02ns per bit)
+ * - TX Invert : bit [15]
+ * - RX Delay: bits [30:24] — RX_CLK delay (unit: 0.02ns per bit)
+ * - RX Invert : bit [31]
*/
#define EIC7700_ETH_TX_ADJ_DELAY GENMASK(14, 8)
#define EIC7700_ETH_RX_ADJ_DELAY GENMASK(30, 24)
+#define EIC7700_ETH_TX_INV_DELAY BIT(15)
+#define EIC7700_ETH_RX_INV_DELAY BIT(31)
-#define EIC7700_MAX_DELAY_UNIT 0x7F
+#define EIC7700_MAX_DELAY_STEPS 0x7F
+#define EIC7700_DELAY_STEP_PS 20
+#define EIC7700_MAX_DELAY_PS \
+ (EIC7700_MAX_DELAY_STEPS * EIC7700_DELAY_STEP_PS)
static const char * const eic7700_clk_names[] = {
"tx", "axi", "cfg",
};
+struct eic7700_dwmac_data {
+ bool rgmii_rx_clk_invert;
+};
+
struct eic7700_qos_priv {
+ struct device *dev;
struct plat_stmmacenet_data *plat_dat;
+ struct regmap *eic7700_hsp_regmap;
+ u32 eth_axi_lp_ctrl_offset;
+ u32 eth_phy_ctrl_offset;
+ u32 eth_txd_offset;
+ u32 eth_clk_offset;
+ u32 eth_rxd_offset;
+ u32 eth_clk_dly_param;
+ bool eth_rx_clk_inv;
};
static int eic7700_clks_config(void *priv, bool enabled)
@@ -61,8 +81,28 @@ static int eic7700_clks_config(void *priv, bool enabled)
static int eic7700_dwmac_init(struct device *dev, void *priv)
{
struct eic7700_qos_priv *dwc = priv;
+ int ret;
+
+ ret = eic7700_clks_config(dwc, true);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(dwc->eic7700_hsp_regmap,
+ dwc->eth_phy_ctrl_offset,
+ EIC7700_ETH_TX_CLK_SEL |
+ EIC7700_ETH_PHY_INTF_SELI);
+ if (ret) {
+ eic7700_clks_config(dwc, false);
+ return ret;
+ }
+
+ regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_axi_lp_ctrl_offset,
+ EIC7700_ETH_CSYSREQ_VAL);
+
+ regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_txd_offset, 0);
+ regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_rxd_offset, 0);
- return eic7700_clks_config(dwc, true);
+ return 0;
}
static void eic7700_dwmac_exit(struct device *dev, void *priv)
@@ -88,18 +128,35 @@ static int eic7700_dwmac_resume(struct device *dev, void *priv)
return ret;
}
+static void eic7700_dwmac_fix_speed(void *priv, phy_interface_t interface,
+ int speed, unsigned int mode)
+{
+ struct eic7700_qos_priv *dwc = (struct eic7700_qos_priv *)priv;
+ u32 dly_param = dwc->eth_clk_dly_param;
+
+ switch (speed) {
+ case SPEED_1000:
+ if (dwc->eth_rx_clk_inv)
+ dly_param |= EIC7700_ETH_RX_INV_DELAY;
+ break;
+ case SPEED_100:
+ case SPEED_10:
+ break;
+ default:
+ dev_err(dwc->dev, "invalid speed %u\n", speed);
+ break;
+ }
+
+ regmap_write(dwc->eic7700_hsp_regmap, dwc->eth_clk_offset, dly_param);
+}
+
static int eic7700_dwmac_probe(struct platform_device *pdev)
{
+ const struct eic7700_dwmac_data *data;
struct plat_stmmacenet_data *plat_dat;
struct stmmac_resources stmmac_res;
struct eic7700_qos_priv *dwc_priv;
- struct regmap *eic7700_hsp_regmap;
- u32 eth_axi_lp_ctrl_offset;
- u32 eth_phy_ctrl_offset;
- u32 eth_phy_ctrl_regset;
- u32 eth_rxd_dly_offset;
- u32 eth_dly_param = 0;
- u32 delay_ps;
+ u32 delay_ps, val;
int i, ret;
ret = stmmac_get_platform_resources(pdev, &stmmac_res);
@@ -116,70 +173,95 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
if (!dwc_priv)
return -ENOMEM;
+ dwc_priv->dev = &pdev->dev;
+
+ data = device_get_match_data(&pdev->dev);
+ if (!data)
+ return dev_err_probe(&pdev->dev,
+ -EINVAL, "no match data found\n");
+
+ dwc_priv->eth_rx_clk_inv = data->rgmii_rx_clk_invert;
+
/* Read rx-internal-delay-ps and update rx_clk delay */
if (!of_property_read_u32(pdev->dev.of_node,
"rx-internal-delay-ps", &delay_ps)) {
- u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
+ if (delay_ps % EIC7700_DELAY_STEP_PS)
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "rx delay must be multiple of %dps\n",
+ EIC7700_DELAY_STEP_PS);
+
+ if (delay_ps > EIC7700_MAX_DELAY_PS)
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "rx delay out of range\n");
- eth_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
- eth_dly_param |= FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
- } else {
- return dev_err_probe(&pdev->dev, -EINVAL,
- "missing required property rx-internal-delay-ps\n");
+ val = delay_ps / EIC7700_DELAY_STEP_PS;
+
+ dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_RX_ADJ_DELAY;
+ dwc_priv->eth_clk_dly_param |=
+ FIELD_PREP(EIC7700_ETH_RX_ADJ_DELAY, val);
}
/* Read tx-internal-delay-ps and update tx_clk delay */
if (!of_property_read_u32(pdev->dev.of_node,
"tx-internal-delay-ps", &delay_ps)) {
- u32 val = min(delay_ps / 100, EIC7700_MAX_DELAY_UNIT);
+ if (delay_ps % EIC7700_DELAY_STEP_PS)
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "tx delay must be multiple of %dps\n",
+ EIC7700_DELAY_STEP_PS);
+
+ if (delay_ps > EIC7700_MAX_DELAY_PS)
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "tx delay out of range\n");
+
+ val = delay_ps / EIC7700_DELAY_STEP_PS;
- eth_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
- eth_dly_param |= FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
- } else {
- return dev_err_probe(&pdev->dev, -EINVAL,
- "missing required property tx-internal-delay-ps\n");
+ dwc_priv->eth_clk_dly_param &= ~EIC7700_ETH_TX_ADJ_DELAY;
+ dwc_priv->eth_clk_dly_param |=
+ FIELD_PREP(EIC7700_ETH_TX_ADJ_DELAY, val);
}
- eic7700_hsp_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
- "eswin,hsp-sp-csr");
- if (IS_ERR(eic7700_hsp_regmap))
+ dwc_priv->eic7700_hsp_regmap =
+ syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "eswin,hsp-sp-csr");
+ if (IS_ERR(dwc_priv->eic7700_hsp_regmap))
return dev_err_probe(&pdev->dev,
- PTR_ERR(eic7700_hsp_regmap),
+ PTR_ERR(dwc_priv->eic7700_hsp_regmap),
"Failed to get hsp-sp-csr regmap\n");
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
- 1, ð_phy_ctrl_offset);
+ 1, &dwc_priv->eth_phy_ctrl_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"can't get eth_phy_ctrl_offset\n");
- regmap_read(eic7700_hsp_regmap, eth_phy_ctrl_offset,
- ð_phy_ctrl_regset);
- eth_phy_ctrl_regset |=
- (EIC7700_ETH_TX_CLK_SEL | EIC7700_ETH_PHY_INTF_SELI);
- regmap_write(eic7700_hsp_regmap, eth_phy_ctrl_offset,
- eth_phy_ctrl_regset);
-
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
- 2, ð_axi_lp_ctrl_offset);
+ 2, &dwc_priv->eth_axi_lp_ctrl_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"can't get eth_axi_lp_ctrl_offset\n");
- regmap_write(eic7700_hsp_regmap, eth_axi_lp_ctrl_offset,
- EIC7700_ETH_CSYSREQ_VAL);
+ ret = of_property_read_u32_index(pdev->dev.of_node,
+ "eswin,hsp-sp-csr",
+ 3, &dwc_priv->eth_clk_offset);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "can't get eth_clk_offset\n");
ret = of_property_read_u32_index(pdev->dev.of_node,
"eswin,hsp-sp-csr",
- 3, ð_rxd_dly_offset);
+ 4, &dwc_priv->eth_txd_offset);
if (ret)
return dev_err_probe(&pdev->dev, ret,
- "can't get eth_rxd_dly_offset\n");
+ "can't get eth_txd_offset\n");
- regmap_write(eic7700_hsp_regmap, eth_rxd_dly_offset,
- eth_dly_param);
+ ret = of_property_read_u32_index(pdev->dev.of_node,
+ "eswin,hsp-sp-csr",
+ 5, &dwc_priv->eth_rxd_offset);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "can't get eth_rxd_offset\n");
plat_dat->num_clks = ARRAY_SIZE(eic7700_clk_names);
plat_dat->clks = devm_kcalloc(&pdev->dev,
@@ -208,12 +290,27 @@ static int eic7700_dwmac_probe(struct platform_device *pdev)
plat_dat->exit = eic7700_dwmac_exit;
plat_dat->suspend = eic7700_dwmac_suspend;
plat_dat->resume = eic7700_dwmac_resume;
+ plat_dat->fix_mac_speed = eic7700_dwmac_fix_speed;
return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
}
+static const struct eic7700_dwmac_data eic7700_dwmac_data = {
+ .rgmii_rx_clk_invert = false,
+};
+
+static const struct eic7700_dwmac_data eic7700_dwmac_data_clk_inversion = {
+ .rgmii_rx_clk_invert = true,
+};
+
static const struct of_device_id eic7700_dwmac_match[] = {
- { .compatible = "eswin,eic7700-qos-eth" },
+ { .compatible = "eswin,eic7700-qos-eth",
+ .data = &eic7700_dwmac_data,
+ },
+ {
+ .compatible = "eswin,eic7700-qos-eth-clk-inversion",
+ .data = &eic7700_dwmac_data_clk_inversion,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, eic7700_dwmac_match);
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v7 1/4] dt-bindings: ethernet: eswin: add clock sampling control
From: lizhi2 @ 2026-04-27 7:24 UTC (permalink / raw)
To: devicetree, andrew+netdev, davem, edumazet, kuba, robh, krzk+dt,
conor+dt, netdev, pabeni, mcoquelin.stm32, alexandre.torgue,
rmk+kernel, pjw, palmer, aou, alex, linux-riscv, linux-stm32,
linux-arm-kernel, linux-kernel, maxime.chevallier
Cc: ningyu, linmin, pinkesh.vaghela, pritesh.patel, weishangjuan,
horms, Zhi Li, Conor Dooley
In-Reply-To: <20260427072353.1114-1-lizhi2@eswincomputing.com>
From: Zhi Li <lizhi2@eswincomputing.com>
Due to chip backend reasons, there is already an approximately 4-5 ns
skew between the RX clock and data of the eth1 MAC controller inside
the silicon.
For 1000M, the RX clock must be inverted since it is not possible to
meet the RGMII timing requirements using only rx-internal-delay-ps on
the MAC together with the standard 2 ns delay on the PHY. Therefore,
even on a properly designed board, eth1 still requires RX clock
inversion.
This behaviour effectively breaks the RGMII timing assumptions at the
SoC level.
For the TX path of eth1, there is also a skew between the TX clock
and data on the MAC controller inside the silicon. This skew happens
to be approximately 2 ns. Therefore, it can be considered that the
2 ns delay of TX is provided by the MAC, so the TX is compliant with
the RGMII standard.
For 10/100 operation, the approximately 4-5 ns skew in the chip does
not break the standard. The RGMII timing table (Section 3.3) specifies
that for 10/100 operation the maximum value is unspecified:
https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-processors/20655/1/RGMIIv2_0_final_hp.pdf
Due to the eth1 silicon behavior described above, a new compatible
string "eswin,eic7700-qos-eth-clk-inversion" is added to the device
tree. This allows the driver to handle the differences between eth1
and eth0 through dedicated logic.
The rx-internal-delay-ps and tx-internal-delay-ps properties now use
minimum and maximum constraints to reflect the actual hardware delay
range (0-2540 ps) applied in 20 ps steps. This relaxes the binding
validation compared to the previous enum-based definition and avoids
regressions for existing DTBs while keeping the same hardware limits.
Treat the RX/TX internal delay properties as optional, board-specific
tuning knobs and remove them from the example to avoid encouraging
their use.
In addition, the binding now includes additional background information
about the HSP CSR registers accessed by the MAC. The TXD and RXD delay
control registers are included so the driver can explicitly clear any
residual configuration left by the bootloader.
Background reference for the High-Speed Subsystem and HSP CSR block is
available in Chapter 10 ("High-Speed Interface") of the EIC7700X SoC
Technical Reference Manual, Part 4
(EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
There are currently no in-tree users of the EIC7700 Ethernet driver, so
these changes are safe.
Fixes: 888bd0eca93c ("dt-bindings: ethernet: eswin: Document for EIC7700 SoC")
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/net/eswin,eic7700-eth.yaml | 69 +++++++++++++++----
1 file changed, 55 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
index 91e8cd1db67b..0b27719feb7d 100644
--- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
+++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
@@ -20,6 +20,7 @@ select:
contains:
enum:
- eswin,eic7700-qos-eth
+ - eswin,eic7700-qos-eth-clk-inversion
required:
- compatible
@@ -29,7 +30,9 @@ allOf:
properties:
compatible:
items:
- - const: eswin,eic7700-qos-eth
+ - enum:
+ - eswin,eic7700-qos-eth
+ - eswin,eic7700-qos-eth-clk-inversion
- const: snps,dwmac-5.20
reg:
@@ -63,16 +66,29 @@ properties:
- const: stmmaceth
rx-internal-delay-ps:
- enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
+ minimum: 0
+ maximum: 2540
+ multipleOf: 20
tx-internal-delay-ps:
- enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400]
+ minimum: 0
+ maximum: 2540
+ multipleOf: 20
eswin,hsp-sp-csr:
description:
HSP CSR is to control and get status of different high-speed peripherals
(such as Ethernet, USB, SATA, etc.) via register, which can tune
board-level's parameters of PHY, etc.
+
+ Additional background information about the High-Speed Subsystem
+ and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
+ of the EIC7700X SoC Technical Reference Manual, Part 4
+ (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
+ publicly available at
+ https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
+
+ This reference is provided for background information only.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
@@ -82,6 +98,8 @@ properties:
- description: Offset of AXI clock controller Low-Power request
register
- description: Offset of register controlling TX/RX clock delay
+ - description: Offset of register controlling TXD delay
+ - description: Offset of register controlling RXD delay
required:
- compatible
@@ -93,8 +111,6 @@ required:
- phy-mode
- resets
- reset-names
- - rx-internal-delay-ps
- - tx-internal-delay-ps
- eswin,hsp-sp-csr
unevaluatedProperties: false
@@ -104,24 +120,49 @@ examples:
ethernet@50400000 {
compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
reg = <0x50400000 0x10000>;
+ interrupt-parent = <&plic>;
+ interrupts = <61>;
+ interrupt-names = "macirq";
clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
<&d0_clock 193>;
clock-names = "axi", "cfg", "stmmaceth", "tx";
+ resets = <&reset 95>;
+ reset-names = "stmmaceth";
+ eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>;
+ phy-handle = <&gmac0_phy0>;
+ phy-mode = "rgmii-id";
+ snps,aal;
+ snps,fixed-burst;
+ snps,tso;
+ snps,axi-config = <&stmmac_axi_setup_gmac0>;
+
+ stmmac_axi_setup_gmac0: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <2>;
+ snps,wr_osr_lmt = <2>;
+ };
+ };
+
+ ethernet@50410000 {
+ compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20";
+ reg = <0x50410000 0x10000>;
interrupt-parent = <&plic>;
- interrupts = <61>;
+ interrupts = <70>;
interrupt-names = "macirq";
- phy-mode = "rgmii-id";
- phy-handle = <&phy0>;
- resets = <&reset 95>;
+ clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
+ <&d0_clock 194>;
+ clock-names = "axi", "cfg", "stmmaceth", "tx";
+ resets = <&reset 94>;
reset-names = "stmmaceth";
- rx-internal-delay-ps = <200>;
- tx-internal-delay-ps = <200>;
- eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>;
- snps,axi-config = <&stmmac_axi_setup>;
+ eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x218 0x214 0x21c>;
+ phy-handle = <&gmac1_phy0>;
+ phy-mode = "rgmii-id";
snps,aal;
snps,fixed-burst;
snps,tso;
- stmmac_axi_setup: stmmac-axi-config {
+ snps,axi-config = <&stmmac_axi_setup_gmac1>;
+
+ stmmac_axi_setup_gmac1: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <2>;
snps,wr_osr_lmt = <2>;
--
2.25.1
^ permalink raw reply related
* [PATCH net-next v7 0/4] net: stmmac: eic7700: fix EIC7700 eth1 RX sampling timing
From: lizhi2 @ 2026-04-27 7:23 UTC (permalink / raw)
To: devicetree, andrew+netdev, davem, edumazet, kuba, robh, krzk+dt,
conor+dt, netdev, pabeni, mcoquelin.stm32, alexandre.torgue,
rmk+kernel, pjw, palmer, aou, alex, linux-riscv, linux-stm32,
linux-arm-kernel, linux-kernel, maxime.chevallier
Cc: ningyu, linmin, pinkesh.vaghela, pritesh.patel, weishangjuan,
horms, Zhi Li
From: Zhi Li <lizhi2@eswincomputing.com>
v6 -> v7:
- Address checkpatch.pl --strict warnings for DTS changes:
- Split DT binding documentation and DTS board description into separate patches
- Fix DTS style issues reported by checkpatch:
- Reduce line length where applicable
- Add required description for rgmii-rxid
- DTS changes in this series are split into:
- Patch 3/4: syscon binding update (documentation / reference only)
- Patch 4/4: board DTS changes (architecture overview only)
These patches (3/4 and 4/4) are provided to facilitate review of the overall
Ethernet integration across binding, driver, and device tree, and are not
intended as final upstream submission in their current form.
A cleaned-up, upstream-ready DTS series will be submitted separately once
all dependencies and final hardware integration are completed.
- Note:
- Clock-related bindings referenced in earlier revisions are now already merged
into net-next, so dtbs_check warnings related to clock are no longer present
and are not relevant to this revision.
- No functional changes in the stmmac driver or binding semantics in this revision.
- Link to v6:
https://lore.kernel.org/lkml/20260423085501.760-1-lizhi2@eswincomputing.com/
v5 -> v6:
- Update DTS/DTSI descriptions to fix invalid phandle references reported by DTC:
- Add missing GMAC provider nodes required for proper hardware description:
- HSP power domain: GMAC nodes moved under this domain to reflect
hardware power hierarchy.
- Clock nodes: added to provide clk phandles referenced by GMAC.
- Reset nodes: added to provide reset phandles referenced by GMAC.
- Pinctrl nodes: defines pinctrl settings for GMAC signals
(pinctrl_gpio106, pinctrl_gpio111).
- Move GMAC nodes under the correct HSP power domain.
- Ensure DTS builds without dtc errors and all phandle references
(clk/reset/pinctrl/power-domain) are valid.
- This update does not change runtime behavior; it only improves DTS
consistency and resolves issues reported by dtc.
- Note:
- The patch 3/3 for DTS changes in this series provide an overview of the GMAC
integration and its dependencies, as discussed previously:
https://lore.kernel.org/lkml/64bf6b40-b947-4ffa-8d48-4d6341931327@lunn.ch/
- It is **not intended for upstream inclusion** in its current form,
and is provided solely for architecture overview and integration
context.
- A fully cleaned and upstream-ready DTS series will be submitted
separately once all related components (pinctrl, clock, power-domain,
etc.) are finalized.
- dtbs_check has been run on top of net-next for reference purposes.
Remaining warnings are expected due to missing EIC7700 clock bindings[1]
in net-next and do not reflect issues in the DTS design itself.
- One remaining warning:
- eswin,eic7700-clock
- The clock binding has already been applied to upstream and is present
in mainline, but not yet available in net-next.
- The syscon binding is extended in this series to include the
eswin,eic7700-syscfg compatible.
- Any further refinement of the syscfg binding will be handled in
separate patches if needed.
- Dependencies:
- [1]EIC7700 clock binding:
https://lore.kernel.org/lkml/20260303080637.2100-1-dongxuyang@eswincomputing.com/
(already applied to upstream)
- Link to v5:
https://lore.kernel.org/lkml/20260324073017.376-1-lizhi2@eswincomputing.com/
v4 -> v5:
- eswin,eic7700-eth.yaml:
- Add Acked-by from Conor Dooley
- No functional changes
- Update dwmac-eic7700.c:
- Disable clocks on the error path to fix a clock leak in
eic7700_dwmac_init() when regmap_set_bits() fails
(reported by Simon Horman <horms@kernel.org>)
- Link to v4:
https://lore.kernel.org/lkml/20260313075234.1567-1-lizhi2@eswincomputing.com/
v3 -> v4:
- Update eswin,eic7700-eth.yaml:
- Improve commit message in dt-bindings patch to clarify the
hardware difference of the eth1 MAC and why a new compatible
string is required.
- Move the newly added eswin,hsp-sp-csr item to the end of the list
to avoid inserting entries in the middle of the binding schema.
- Simplify the compatible schema by replacing the previous oneOf
construct with an enum.
- Update dwmac-eic7700.c:
- Fix build issues.
- Adjust code to match the updated binding definition.
- Update DTS/DTSI descriptions:
- Move SoC-level descriptions to the .dtsi file.
- Keep board-specific configuration in the .dts file.
- Link to v3:
https://lore.kernel.org/lkml/20260303061525.846-1-lizhi2@eswincomputing.com/
v2 -> v3:
- Update eswin,eic7700-eth.yaml:
- Extend rx-internal-delay-ps and tx-internal-delay-ps range
from 0-2400 to 0-2540 to match the full 7-bit hardware delay
field (127 * 20 ps).
- Add "multipleOf: 20" constraint to reflect the 20 ps hardware
step size.
- Make rx-internal-delay-ps and tx-internal-delay-ps optional.
A well-designed board should not require internal delay tuning.
- Remove rx-internal-delay-ps and tx-internal-delay-ps from the
example to avoid encouraging blind copy into board DTs.
- Update dwmac-eic7700.c:
- Treat rx-internal-delay-ps and tx-internal-delay-ps as optional
DT properties.
- Apply delay configuration only when properties are present.
- Keep TX/RX delay registers cleared by default to ensure a
deterministic state when no delay is specified.
- Describe Ethernet configuration for the HiFive Premier P550 board:
- Add GMAC controller nodes for the HiFive Premier P550 board
to describe the on-board Ethernet configuration.
The Ethernet controller depends on clock, reset, pinctrl
and HSP subsystem providers which are currently under
upstream review. These dependent nodes will be submitted
separately once the corresponding drivers are merged.
Due to these missing dependencies, dt-binding-check may
report warnings or failures for this series.
- No functional changes to RX clock inversion logic.
- Link to v2:
https://lore.kernel.org/lkml/20260209094628.886-1-lizhi2@eswincomputing.com/
- This series is based on the EIC7700 clock support series:
https://lore.kernel.org/all/20260210095008.726-1-dongxuyang@eswincomputing.com/
The clock series is currently under review.
v1 -> v2:
- Update eswin,eic7700-eth.yaml:
- Drop the vendor-specific properties eswin,rx-clk-invert and
eswin,tx-clk-invert.
- Introduce a distinct compatible string
"eswin,eic7700-qos-eth-clk-inversion" to describe MAC instances that
require internal RGMII clock inversion.
This models the SoC-specific hardware difference directly via the
compatible string and avoids per-board configuration properties.
- Change rx-internal-delay-ps and tx-internal-delay-ps from enum to
minimum/maximum to reflect the actual delay range (0-2400 ps)
- Add reference to High-Speed Subsystem documentation in eswin,hsp-sp-csr
description. The HSP CSR block is described in Chapter 10
("High-Speed Interface") of the EIC7700X SoC Technical Reference Manual,
Part 4 (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf):
https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
- Update dwmac-eic7700.c:
- Remove handling of eswin,rx-clk-invert and eswin,tx-clk-invert
properties.
- Select RX clock inversion based on the new
"eswin,eic7700-qos-eth-clk-inversion" compatible string, using
match data to apply the required configuration for affected MAC
instances (eth1).
- Link to v1:
https://lore.kernel.org/lkml/20260109080601.1262-1-lizhi2@eswincomputing.com/
Zhi Li (4):
dt-bindings: ethernet: eswin: add clock sampling control
net: stmmac: eic7700: enable clocks before syscon access and correct
RX sampling timing
dt-bindings: mfd: syscon: add ESWIN EIC7700 compatible
riscv: dts: eswin: eic7700-hifive-premier-p550: enable Ethernet
controller
.../devicetree/bindings/mfd/syscon.yaml | 2 +
.../bindings/net/eswin,eic7700-eth.yaml | 69 ++++-
.../dts/eswin/eic7700-hifive-premier-p550.dts | 239 ++++++++++++++++++
arch/riscv/boot/dts/eswin/eic7700.dtsi | 105 ++++++++
.../ethernet/stmicro/stmmac/dwmac-eic7700.c | 183 ++++++++++----
5 files changed, 541 insertions(+), 57 deletions(-)
--
2.25.1
^ permalink raw reply
* Re: [REGRESSION] rseq: refactoring in v6.19 broke everyone on arm64 and tcmalloc everywhere
From: Florian Weimer @ 2026-04-27 7:06 UTC (permalink / raw)
To: Linus Torvalds
Cc: Thomas Gleixner, Mathias Stearn, Peter Zijlstra,
Mathieu Desnoyers, Catalin Marinas, Will Deacon, Boqun Feng,
Paul E. McKenney, Chris Kennelly, Dmitry Vyukov, regressions,
linux-kernel, linux-arm-kernel, Ingo Molnar, Mark Rutland,
Jinjie Ruan, Blake Oler
In-Reply-To: <CAHk-=wh=B3fqU9AaBsyViZR=eVTG5qa2CGyN=qxPROVxu9Gctg@mail.gmail.com>
* Linus Torvalds:
>> // Note: this makes __rseq_abi.cpu_id_start unusable for its original purpose.
>>
>> Do you seriously want to proliferate that?
>
> Absolutely.
>
> That's how clever hacks work - they take advantage of things past
> their design parameters. "If it works, it's not stupid".
>
> We don't then turn around and say "you were clever, and we did
> something stupid, so now we'll hurt you".
>
> This is all 100% on the RSEQ kernel code, not on users who took
> advantage of it.
RSEQ was intended to be modular, with more than one library using it
within a process, without coordination (beyond sticking to the RSEQ
protocol). The tcmalloc approach is incompatible with that. Once
tcmalloc starts using RSEQ in its peculiar way, nothing else in the
process can, and vice versa. This is far from ideal because the
particular descheduling notification that tcmalloc uses could be
implemented in a much simpler way than full RSEQ, given its non-modular
nature.
Thanks,
Florian
^ permalink raw reply
* [RESEND,v2 2/2] memory: mtk-smi: Add mt8189 support
From: mtk20898 @ 2026-04-27 7:04 UTC (permalink / raw)
To: Yong Wu, Krzysztof Kozlowski, Rob Herring, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, Zhengnan Chen
In-Reply-To: <20260427070444.20247-1-zhengnan.chen@mediatek.com>
From: Zhengnan Chen <zhengnan.chen@mediatek.com>
Add the necessary platform data and ostdl setting to enable support
for mt8189 smi.
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/memory/mtk-smi.c | 44 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index aaeba8ab211e..f2d5462af681 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -401,6 +401,30 @@ static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
[25] = {0x01},
};
+static const u8 mtk_smi_larb_mt8189_ostd[][SMI_LARB_PORT_NR_MAX] = {
+ [0] = {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,},
+ [1] = {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,},
+ [2] = {0x7, 0x7, 0x4, 0x4, 0x0, 0x0, 0x2, 0x2, 0x7, 0x7, 0x0,},
+ [4] = {0x2F, 0x1E, 0x9, 0x1, 0x1, 0x1, 0x1, 0x2, 0x2, 0x5, 0x1, 0x17,},
+ [7] = {0x20, 0x2, 0x1, 0x1, 0x1, 0x4, 0x2, 0x1, 0x1, 0x2, 0x3, 0x2,
+ 0xA, 0xF, 0x4, 0x6, 0x5, 0x1,},
+ [9] = {0x6, 0x3, 0xC, 0x6, 0x1, 0x4, 0x3, 0x1, 0x2, 0x4, 0x5, 0x2,
+ 0x4, 0x2, 0x3, 0xB, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1,},
+ [11] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
+ 0x1, 0x1, 0x1, 0xB, 0x1, 0x4, 0x6, 0x5, 0x6, 0x1, 0x5, 0x2,
+ 0x9, 0x5,},
+ [13] = {0x2, 0x8, 0x8, 0x8, 0x4, 0x4, 0x4, 0x4, 0x4, 0xE, 0x4, 0x1,
+ 0x6, 0x6, 0x2,},
+ [14] = {0x1, 0x1, 0x1, 0x20, 0xE, 0x4, 0x8, 0x8, 0x6, 0x4,},
+ [16] = {0x1E, 0xC, 0x2, 0x8, 0xE, 0x2, 0x1E, 0x10, 0x4, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x4, 0x2, 0x4,},
+ [17] = {0x1E, 0xC, 0x2, 0x8, 0xE, 0x2, 0x1E, 0x10, 0x4, 0x2, 0x2, 0x2,
+ 0x2, 0x2, 0x4, 0x2, 0x4,},
+ [19] = {0x2, 0x1, 0x3, 0x1,},
+ [20] = {0x7, 0x7, 0x3, 0x3, 0x1, 0x1,},
+};
+
static const u8 mtk_smi_larb_mt8192_ostd[][SMI_LARB_PORT_NR_MAX] = {
[0] = {0x2, 0x2, 0x28, 0xa, 0xc, 0x28,},
[1] = {0x2, 0x2, 0x18, 0x18, 0x18, 0xa, 0xc, 0x28,},
@@ -533,6 +557,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {
.ostd = mtk_smi_larb_mt8188_ostd,
};
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt8189 = {
+ .config_port = mtk_smi_larb_config_port_gen2_general,
+ .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
+ MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL,
+ .ostd = mtk_smi_larb_mt8189_ostd,
+};
+
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
.config_port = mtk_smi_larb_config_port_gen2_general,
.ostd = mtk_smi_larb_mt8192_ostd,
@@ -556,6 +587,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = {
{.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
{.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
{.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
+ {.compatible = "mediatek,mt8189-smi-larb", .data = &mtk_smi_larb_mt8189},
{.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
{.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
{}
@@ -808,6 +840,16 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8188_vpp = {
.init = mtk_smi_common_mt8195_init,
};
+static const struct mtk_smi_common_plat mtk_smi_common_mt8189 = {
+ .type = MTK_SMI_GEN2,
+ .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
+ F_MMU1_LARB(7),
+};
+
+static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8189 = {
+ .type = MTK_SMI_GEN2_SUB_COMM,
+};
+
static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
.type = MTK_SMI_GEN2,
.has_gals = true,
@@ -852,6 +894,8 @@ static const struct of_device_id mtk_smi_common_of_ids[] = {
{.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
{.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
{.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
+ {.compatible = "mediatek,mt8189-smi-common", .data = &mtk_smi_common_mt8189},
+ {.compatible = "mediatek,mt8189-smi-sub-common", .data = &mtk_smi_sub_common_mt8189},
{.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
{.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
{.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
--
2.46.0
^ permalink raw reply related
* [RESEND,v2 1/2] dt-bindings: memory-controllers: mtk-smi: Add support for mt8189
From: mtk20898 @ 2026-04-27 7:04 UTC (permalink / raw)
To: Yong Wu, Krzysztof Kozlowski, Rob Herring, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, Zhengnan Chen
In-Reply-To: <20260427070444.20247-1-zhengnan.chen@mediatek.com>
From: Zhengnan Chen <zhengnan.chen@mediatek.com>
Add binding description for mt8189.
The clocks number of mt8189 smi-sub common has a bit difference.
Its clock count is 2, while mt8195 has 3. Therefore, the minimum
number of clocks is changed to 2, with the third one being optional.
About what smi-sub-common is, please check the below diagram,
we add it in mediatek,smi-common.yaml file.
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../mediatek,smi-common.yaml | 25 +++++++++++++++++--
.../memory-controllers/mediatek,smi-larb.yaml | 3 +++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index 0762e0ff66ef..454d11a83973 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -25,6 +25,21 @@ description: |
SMI generation 1 to transform the smi clock into emi clock domain, but that is
not needed for SMI generation 2.
+ The smi-common connects with smi-larb and IOMMU. The maximum inputs number of
+ a smi-common is 8. In SMI generation 2, the engines number may be over 8.
+ In this case, we use a smi-sub-common to merge some larbs.
+ The block diagram something is like:
+
+ IOMMU
+ | |
+ smi-common
+ ---------------------------
+ | | ...
+ larb0 sub-common ... <-max number is 8
+ ----------------
+ | | ...
+ larb1 larbX ... <-max number is 8
+
properties:
compatible:
oneOf:
@@ -40,6 +55,8 @@ properties:
- mediatek,mt8186-smi-common
- mediatek,mt8188-smi-common-vdo
- mediatek,mt8188-smi-common-vpp
+ - mediatek,mt8189-smi-common
+ - mediatek,mt8189-smi-sub-common
- mediatek,mt8192-smi-common
- mediatek,mt8195-smi-common-vdo
- mediatek,mt8195-smi-common-vpp
@@ -108,19 +125,23 @@ allOf:
compatible:
contains:
enum:
+ - mediatek,mt8189-smi-sub-common
- mediatek,mt8195-smi-sub-common
then:
required:
- mediatek,smi
properties:
clocks:
- minItems: 3
+ minItems: 2
maxItems: 3
clock-names:
+ minItems: 2
+ maxItems: 3
items:
- const: apb
- const: smi
- - const: gals0
+ additionalItems:
+ const: gals0
else:
properties:
mediatek,smi: false
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
index 2e7fac4b5094..9a5dafd7c07e 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -27,6 +27,7 @@ properties:
- mediatek,mt8183-smi-larb
- mediatek,mt8186-smi-larb
- mediatek,mt8188-smi-larb
+ - mediatek,mt8189-smi-larb
- mediatek,mt8192-smi-larb
- mediatek,mt8195-smi-larb
@@ -85,6 +86,7 @@ allOf:
- mediatek,mt8183-smi-larb
- mediatek,mt8186-smi-larb
- mediatek,mt8188-smi-larb
+ - mediatek,mt8189-smi-larb
- mediatek,mt8195-smi-larb
then:
@@ -119,6 +121,7 @@ allOf:
- mediatek,mt6779-smi-larb
- mediatek,mt8186-smi-larb
- mediatek,mt8188-smi-larb
+ - mediatek,mt8189-smi-larb
- mediatek,mt8192-smi-larb
- mediatek,mt8195-smi-larb
--
2.46.0
^ permalink raw reply related
* [RESEND,v2 0/2] MT8189 SMI SUPPORT
From: mtk20898 @ 2026-04-27 7:04 UTC (permalink / raw)
To: Yong Wu, Krzysztof Kozlowski, Rob Herring, Conor Dooley,
Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-mediatek, linux-kernel, devicetree, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, mtk20898
Based on tag: next-20260424, linux-next/master
This patchset add mt8189 smi support.
---
Changes in v2:
Just modify the mediatek,smi-common.yaml file as follows:
- Add schematic diagram explanation between smi-common and smi-sub-common
- Change the clock numbers of smi-sub-common to minimum 2, the third clock
is optional
- Link to v1:
https://lore.kernel.org/all/20250919081014.14100-1-zhengnan.chen@mediatek.com/
---
Zhengnan Chen (2):
dt-bindings: memory-controllers: mtk-smi: Add support for mt8189
memory: mtk-smi: Add mt8189 support
.../mediatek,smi-common.yaml | 25 ++++++++++-
.../memory-controllers/mediatek,smi-larb.yaml | 3 ++
drivers/memory/mtk-smi.c | 44 +++++++++++++++++++
3 files changed, 70 insertions(+), 2 deletions(-)
--
2.46.0
^ permalink raw reply
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