* Re: [PATCH v3 2/8] dt-bindings: rtc: sun6i: add sun60i-a733 support
From: Conor Dooley @ 2026-07-02 18:45 UTC (permalink / raw)
To: Jerome Brunet
Cc: Junhui Liu, Alexandre Belloni, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Michael Turquette, Stephen Boyd, Maxime Ripard, linux-rtc,
devicetree, linux-arm-kernel, linux-sunxi, linux-kernel,
linux-clk
In-Reply-To: <20260702-a733-rtc-v3-2-eb2580374de6@baylibre.com>
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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
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^ permalink raw reply
* Re: [PATCH v2] iommu/arm-smmu-v3: Shrink command/event/PRI queues in kdump kernel
From: Nicolin Chen @ 2026-07-02 18:54 UTC (permalink / raw)
To: Kiryl Shutsemau (Meta)
Cc: Will Deacon, Robin Murphy, Joerg Roedel, Jason Gunthorpe,
Kyle McMartin, Breno Leitao, Usama Arif, linux-arm-kernel, iommu,
linux-kernel
In-Reply-To: <20260702112825.781750-1-kas@kernel.org>
On Thu, Jul 02, 2026 at 12:28:25PM +0100, Kiryl Shutsemau (Meta) wrote:
> The command, event and PRI queues are sized from the maxima the hardware
> advertises in IDR1, which can be several megabytes each. On systems with
> many SMMUv3 instances that cost is paid per instance and adds up to tens
> of megabytes of coherent DMA in the capture kernel.
>
> A kdump capture kernel runs from a small crashkernel reservation and only
> has to drive the few devices used to save the dump, so deep queues serve
> no purpose. The queues carry invalidation commands and fault records, not
> DMA data, so dump throughput is unaffected; a shallower queue only bounds
> how many commands may be in flight before a sync, which does not matter for
> the capture kernel's small device count and modest I/O.
>
> Clamp every queue to a single page when is_kdump_kernel() is true. Doing
> it in arm_smmu_init_one_queue() covers the command, event and PRI queues
> in one place. The command queue still holds at least one batch plus a sync
> (256 entries on a 4K-page kernel, well above CMDQ_BATCH_ENTRIES), so
> command batching keeps working.
>
> Suggested-by: Kyle McMartin <jkkm@meta.com>
> Signed-off-by: Kiryl Shutsemau (Meta) <kas@kernel.org>
> Reviewed-by: Breno Leitao <leitao@debian.org>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
^ permalink raw reply
* Re: [PATCH v5 11/14] dt-bindings: media: mediatek: vcodec: add decoder dt-bindings for mt8196
From: Conor Dooley @ 2026-07-02 18:55 UTC (permalink / raw)
To: Kyrie Wu (吴晗)
Cc: AngeloGioacchino Del Regno,
laurent.pinchart+renesas@ideasonboard.com,
nicolas.dufresne@collabora.com, jacopo.mondi@ideasonboard.com,
Yunfei Dong (董云飞), conor+dt@kernel.org,
Irui Wang (王瑞), rongqianfeng@vivo.com,
tzungbi@kernel.org, tfiga@chromium.org, robh@kernel.org,
wenst@chromium.org, benjamin.gaignard@collabora.com,
matthias.bgg@gmail.com, haoxiang_li2024@163.com,
ribalda@chromium.org, Tiffany Lin (林慧珊),
linux-mediatek@lists.infradead.org, p.zabel@pengutronix.de,
sebastian.fricke@collabora.com, fshao@chromium.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
mchehab@kernel.org, fanwu01@zju.edu.cn,
linux-arm-kernel@lists.infradead.org,
Andrew-CT Chen (陳智迪), krzk+dt@kernel.org,
hverkuil+cisco@kernel.org, linux-kernel@vger.kernel.org,
kees@kernel.org, sakari.ailus@linux.intel.com
In-Reply-To: <6cb7ae4a09d476a04ceefca50564646712ad391b.camel@mediatek.com>
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On Thu, Jul 02, 2026 at 05:39:24AM +0000, Kyrie Wu (吴晗) wrote:
> On Wed, 2026-06-03 at 17:14 +0100, Conor Dooley wrote:
> > On Wed, Jun 03, 2026 at 04:40:41PM +0800, Kyrie Wu wrote:
> > > From: Yunfei Dong <yunfei.dong@mediatek.com>
> > >
> > > The MT8196 decoder differs from previous generations in several
> > > key aspects, most notably in its use of VCP instead of SCP.
> > > Additionally, the MT8196 enhances codec capabilities by supporting
> > > HEVC Main10 profile decoding. To accommodate these hardware
> > > changes,
> > > the binding constraints specify a total of 12 clock inputs,
> > > consisting of 9 decoder clocks and 3 VCP interface clocks,
> > > along with 2 power domains covering both the decoder and VCP
> > > subsystems.
> >
> > I'm pretty pretty confused by this statement about constraints, since
> > there's none added?
> > The vcodec-dec node doesn't even seem to permit clocks at all?
> >
> Dear Conor,
>
> I apologize for any confusion my commit message caused. What I wanted
> to convey was the hardware differences between the MT8196 and previous
> ICs. If you feel that the VCP and clock information are not suitable
> for this location, I would like to rewrite the commit message as
> follows:
> Compared to previous ICs, the MT8196 supports a 10-bit decoder and has
> a decoding capability of 4K@120fps, using a dual hardware decoding
> architecture of LAT+CORE.
Sure? But your comments about the constraints are odd and I do not know
if that means you omitted changing constraints when you should have?
For example, using lat+core only permits you 10 input clocks but your
commit message talks about 12.
>
> Thanks.
>
> Regards,
> Kyrie.
> > >
> > > Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
> > > Acked-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
> > > ---
> > > .../bindings/media/mediatek,vcodec-subdev-decoder.yaml |
> > > 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> > > decoder.yaml
> > > b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-
> > > decoder.yaml
> > > index bf8082d87ac0..74e1d88d3056 100644
> > > --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-
> > > subdev-decoder.yaml
> > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-
> > > subdev-decoder.yaml
> > > @@ -76,6 +76,7 @@ properties:
> > > - mediatek,mt8186-vcodec-dec
> > > - mediatek,mt8188-vcodec-dec
> > > - mediatek,mt8195-vcodec-dec
> > > + - mediatek,mt8196-vcodec-dec
> > >
> > > reg:
> > > minItems: 1
> > > --
> > > 2.45.2
> > >
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^ permalink raw reply
* Re: [PATCH v7 2/8] media: subdev: Add media_async_register_subdev() helper
From: Frank Li @ 2026-07-02 18:59 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Sakari Ailus, Mauro Carvalho Chehab, Michael Riesch, Frank Li,
Martin Kepplinger-Novakovic, Rui Miguel Silva, Purism Kernel Team,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-media, linux-kernel,
imx, Guoniu Zhou, devicetree, linux-arm-kernel
In-Reply-To: <20260702181920.GJ3534761@killaraus.ideasonboard.com>
On Thu, Jul 02, 2026 at 09:19:20PM +0300, Laurent Pinchart wrote:
> On Thu, Jul 02, 2026 at 01:11:03PM -0500, Frank Li wrote:
> > On Thu, Jul 02, 2026 at 07:15:19PM +0300, Laurent Pinchart wrote:
> > > Hi Frank,
> > >
> > > Have you missed the comment in v6 ?
> > >
> > > https://lore.kernel.org/all/20260629084654.GB3054459@killaraus.ideasonboard.com/
> >
> > Sorry, I forget emphased it in change log.
> >
> > "For the reason stated by Sakari in patch 1/9 (dependency from MC to
> > V4L2), I don't think a "media_async_register_subdev()" function is a
> > good idea."
> >
> > The reason already NOT existed in v7, I removed v4l2_fwnode_endpoint from
> > media_pad. So MC will not depdent to V4L2.
> >
> > So this comments is not suit for this version.
>
> media_async_register_subdev(), with its "media_" prefix, appears part of
> the MC API, but it operates on a subdev. At least the function name
> should be changed in my opinion.
Name is easy to fix. The key is if the overall direction and method is
good enough to go futher.
Optional naming here
v4l2_async_register_subdev_with_created_pad()
v4l2_create_pad_and_async_register_subdev()
v4l2_async_register_subdev_from_fw_ports()
...
Frank
>
> --
> Regards,
>
> Laurent Pinchart
^ permalink raw reply
* [PATCH v2 2/3] KVM: arm64: Expose PMMIR_EL1.SLOTS under strict PMUv3 UAPI
From: Congkai Tan @ 2026-07-02 19:04 UTC (permalink / raw)
To: Oliver Upton, kvmarm, linux-arm-kernel
Cc: Congkai Tan, Marc Zyngier, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Catalin Marinas, Will Deacon, Paolo Bonzini,
Jonathan Corbet, Haris Okanovic, Geoff Blake, Stanislav Spassov,
kvm, linux-doc, linux-kselftest, linux-kernel
In-Reply-To: <20260702190421.420992-1-congkai@amazon.com>
Introduce a new field pmmir_slots in struct kvm_arch to store
PMMIR_EL1.SLOTS. It only saves the actual hardware PMU value when
the VMM explicitly selects a PMU under KVM_ARM_VCPU_PMU_V3_STRICT.
Otherwise, it stays 0 after allocation.
Use this field to implement guest access, userspace get, and userspace
set for PMMIR_EL1:
- access_pmmir(): uses the value in kvm->arch.pmmir_slots directly. If
the VMM selected a PMU and KVM_ARM_VCPU_PMU_V3_STRICT is set, the guest
can correctly read the underlying core's SLOTS. Otherwise, it continues
to read 0 since the true SLOTS value can be nondeterministic.
- get_pmmir(): same as access_pmmir().
- set_pmmir(): only the SLOTS field is writable; a value setting any
other bit is rejected with -EINVAL, since get_pmmir() returns SLOTS
zero-extended. A value of 0 resets kvm->arch.pmmir_slots to 0 for
backward compatibility, as the register is RAZ in older KVM, a value
matching the current SLOTS is accepted as a no-op, and anything else is
rejected with -EINVAL. Once the VM has run PMMIR_EL1 is immutable, so a
mismatching write then returns -EBUSY.
The register is now exposed via KVM_GET_REG_LIST for PMUv3 vCPUs, so add
it to the get-reg-list selftest's PMU register list.
Signed-off-by: Congkai Tan <congkai@amazon.com>
Reviewed-by: Geoff Blake <blakgeof@amazon.com>
Reviewed-by: Haris Okanovic <harisokn@amazon.com>
Reviewed-by: Stanislav Spassov <stanspas@amazon.de>
---
arch/arm64/include/asm/kvm_host.h | 3 +
arch/arm64/kvm/pmu-emul.c | 11 ++++
arch/arm64/kvm/sys_regs.c | 63 ++++++++++++++++++-
.../selftests/kvm/arm64/get-reg-list.c | 1 +
4 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index a6e33aaf400d..b896d6eef822 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -387,6 +387,9 @@ struct kvm_arch {
/* Maximum number of counters for the guest */
u8 nr_pmu_counters;
+ /* PMMIR_EL1.SLOTS value exposed to the guest. */
+ u8 pmmir_slots;
+
/* Hypercall features firmware registers' descriptor */
struct kvm_smccc_features smccc_feat;
struct maple_tree smccc_filter;
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index 1f24169505a9..9595bce6519f 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -1117,6 +1117,17 @@ static int kvm_arm_pmu_v3_set_pmu(struct kvm_vcpu *vcpu, int pmu_id)
kvm_arm_set_pmu(kvm, arm_pmu);
cpumask_copy(kvm->arch.supported_cpus, &arm_pmu->supported_cpus);
+
+ /*
+ * Since a specific PMU is explicitly selected,
+ * PMMIR_EL1.SLOTS is deterministic to the guest.
+ * If KVM_ARM_VCPU_PMU_V3_STRICT is set, snapshot
+ * the value to allow the guest to read it.
+ */
+ if (kvm_vcpu_has_pmuv3_strict(vcpu))
+ kvm->arch.pmmir_slots =
+ FIELD_GET(ARMV8_PMU_SLOTS,
+ arm_pmu->reg_pmmir);
ret = 0;
break;
}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 148fc3400ea8..edfbb8de1528 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1370,6 +1370,64 @@ static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
return true;
}
+static bool access_pmmir(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+ const struct sys_reg_desc *r)
+{
+ if (p->is_write)
+ return write_to_read_only(vcpu, p, r);
+
+ /*
+ * If KVM_ARM_VCPU_PMU_V3_STRICT is set and PMU was explicitly
+ * selected, the underlying hardware SLOTS value was read into this
+ * field. Otherwise, it stays 0. All other PMMIR_EL1 fields are RAZ.
+ */
+ p->regval = FIELD_PREP(ARMV8_PMU_SLOTS, vcpu->kvm->arch.pmmir_slots);
+ return true;
+}
+
+static int get_pmmir(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
+ u64 *val)
+{
+ *val = FIELD_PREP(ARMV8_PMU_SLOTS, vcpu->kvm->arch.pmmir_slots);
+ return 0;
+}
+
+static int set_pmmir(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
+ u64 val)
+{
+ struct kvm *kvm = vcpu->kvm;
+ u8 slots = FIELD_GET(ARMV8_PMU_SLOTS, val);
+
+ /*
+ * Only the SLOTS field is exposed (get_pmmir returns just that field),
+ * so reject a write that sets any other bit rather than silently
+ * masking it.
+ */
+ if (val & ~(u64)ARMV8_PMU_SLOTS)
+ return -EINVAL;
+
+ guard(mutex)(&kvm->arch.config_lock);
+
+ /*
+ * Once the VM has started PMMIR_EL1 is immutable. Reject any write
+ * that does not match the current value.
+ */
+ if (kvm_vm_has_ran_once(kvm))
+ return slots == kvm->arch.pmmir_slots ? 0 : -EBUSY;
+
+ /*
+ * Only SLOTS = 0 is honored for backwards compatibility with the
+ * old RAZ behavior. Reject any non-zero write that does not match
+ * the current value.
+ */
+ if (!slots)
+ kvm->arch.pmmir_slots = 0;
+ else if (slots != kvm->arch.pmmir_slots)
+ return -EINVAL;
+
+ return 0;
+}
+
static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
const struct sys_reg_desc *r)
{
@@ -3456,7 +3514,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ PMU_SYS_REG(PMINTENCLR_EL1),
.access = access_pminten, .reg = PMINTENSET_EL1,
.get_user = get_pmreg, .set_user = set_pmreg },
- { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
+ { PMU_SYS_REG(PMMIR_EL1), .access = access_pmmir, .reset = NULL,
+ .get_user = get_pmmir, .set_user = set_pmmir },
{ SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
{ SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1,
@@ -4600,7 +4659,7 @@ static const struct sys_reg_desc cp15_regs[] = {
{ CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
{ CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
/* PMMIR */
- { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
+ { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = access_pmmir },
/* PRRR/MAIR0 */
{ AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c b/tools/testing/selftests/kvm/arm64/get-reg-list.c
index 0a3a94c4cca1..cfa99979d57c 100644
--- a/tools/testing/selftests/kvm/arm64/get-reg-list.c
+++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c
@@ -532,6 +532,7 @@ static __u64 base_regs[] = {
static __u64 pmu_regs[] = {
ARM64_SYS_REG(3, 0, 9, 14, 1), /* PMINTENSET_EL1 */
ARM64_SYS_REG(3, 0, 9, 14, 2), /* PMINTENCLR_EL1 */
+ ARM64_SYS_REG(3, 0, 9, 14, 6), /* PMMIR_EL1 */
ARM64_SYS_REG(3, 3, 9, 12, 0), /* PMCR_EL0 */
ARM64_SYS_REG(3, 3, 9, 12, 1), /* PMCNTENSET_EL0 */
ARM64_SYS_REG(3, 3, 9, 12, 2), /* PMCNTENCLR_EL0 */
--
2.50.1
^ permalink raw reply related
* [PATCH v2 1/3] KVM: arm64: Add KVM_ARM_VCPU_PMU_V3_STRICT vCPU feature
From: Congkai Tan @ 2026-07-02 19:04 UTC (permalink / raw)
To: Oliver Upton, kvmarm, linux-arm-kernel
Cc: Congkai Tan, Marc Zyngier, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Catalin Marinas, Will Deacon, Paolo Bonzini,
Jonathan Corbet, Haris Okanovic, Geoff Blake, Stanislav Spassov,
kvm, linux-doc, linux-kselftest, linux-kernel
In-Reply-To: <20260702190421.420992-1-congkai@amazon.com>
Introduce a new vCPU feature KVM_ARM_VCPU_PMU_V3_STRICT. When set, KVM
does not create a default PMU when initializing the vCPU, and userspace
must select one explicitly via KVM_ARM_VCPU_PMU_V3_SET_PMU before the
first KVM_RUN.
The flag forces the VMM to be aware of the PMU implementation of the
guest to be created, so that certain information about the PMU becomes
deterministic (if on a heterogeneous system) and becomes safe to be
exposed to the guest. It can be used as an umbrella flag to gate future
PMUv3 UAPI changes.
When no default PMU is created, kvm->arch.arm_pmu stays NULL until SET_PMU
runs, so kvm_arm_pmu_v3_enable() now refuses to run if kvm->arch.arm_pmu
is NULL.
Signed-off-by: Congkai Tan <congkai@amazon.com>
Reviewed-by: Geoff Blake <blakgeof@amazon.com>
Reviewed-by: Haris Okanovic <harisokn@amazon.com>
Reviewed-by: Stanislav Spassov <stanspas@amazon.de>
---
Documentation/virt/kvm/api.rst | 5 +++++
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/include/uapi/asm/kvm.h | 1 +
arch/arm64/kvm/arm.c | 18 ++++++++++++++----
arch/arm64/kvm/pmu-emul.c | 14 +++++++++++++-
include/kvm/arm_pmu.h | 4 ++++
tools/arch/arm64/include/uapi/asm/kvm.h | 1 +
7 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst
index 52bbbb553ce1..79b024a7ba16 100644
--- a/Documentation/virt/kvm/api.rst
+++ b/Documentation/virt/kvm/api.rst
@@ -3515,6 +3515,11 @@ Possible features:
Depends on KVM_CAP_ARM_PSCI_0_2.
- KVM_ARM_VCPU_PMU_V3: Emulate PMUv3 for the CPU.
Depends on KVM_CAP_ARM_PMU_V3.
+ - KVM_ARM_VCPU_PMU_V3_STRICT: Enable strict PMUv3 UAPI.
+ Requires KVM_ARM_VCPU_PMU_V3. If set, KVM does not create a default
+ PMU; userspace must select a PMU implementation with
+ KVM_ARM_VCPU_PMU_V3_SET_PMU before the first KVM_RUN. The selected
+ PMU exposes the SLOTS field of its PMMIR_EL1 register to the guest.
- KVM_ARM_VCPU_PTRAUTH_ADDRESS: Enables Address Pointer authentication
for arm64 only.
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 65eead8362e0..a6e33aaf400d 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -39,7 +39,7 @@
#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
-#define KVM_VCPU_MAX_FEATURES 9
+#define KVM_VCPU_MAX_FEATURES 10
#define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1)
#define KVM_REQ_SLEEP \
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 1c13bfa2d38a..019e5e3d892e 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -106,6 +106,7 @@ struct kvm_regs {
#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
#define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */
#define KVM_ARM_VCPU_HAS_EL2_E2H0 8 /* Limit NV support to E2H RES0 */
+#define KVM_ARM_VCPU_PMU_V3_STRICT 9 /* No default PMU creation */
struct kvm_vcpu_init {
__u32 target;
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 9453321ef8c6..d1914bee1e76 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -1548,8 +1548,10 @@ static unsigned long system_supported_vcpu_features(void)
if (!cpus_have_final_cap(ARM64_HAS_32BIT_EL1))
clear_bit(KVM_ARM_VCPU_EL1_32BIT, &features);
- if (!kvm_supports_guest_pmuv3())
+ if (!kvm_supports_guest_pmuv3()) {
clear_bit(KVM_ARM_VCPU_PMU_V3, &features);
+ clear_bit(KVM_ARM_VCPU_PMU_V3_STRICT, &features);
+ }
if (!system_supports_sve())
clear_bit(KVM_ARM_VCPU_SVE, &features);
@@ -1590,6 +1592,11 @@ static int kvm_vcpu_init_check_features(struct kvm_vcpu *vcpu,
test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, &features))
return -EINVAL;
+ /* Strict PMUv3 UAPI requires PMUv3. */
+ if (test_bit(KVM_ARM_VCPU_PMU_V3_STRICT, &features) &&
+ !test_bit(KVM_ARM_VCPU_PMU_V3, &features))
+ return -EINVAL;
+
if (!test_bit(KVM_ARM_VCPU_EL1_32BIT, &features))
return 0;
@@ -1619,10 +1626,13 @@ static int kvm_setup_vcpu(struct kvm_vcpu *vcpu)
int ret = 0;
/*
- * When the vCPU has a PMU, but no PMU is set for the guest
- * yet, set the default one.
+ * When the vCPU has a PMU, but no PMU is set for the guest yet, set
+ * the default one. If KVM_ARM_VCPU_PMU_V3_STRICT is set, no default
+ * PMU is created, and userspace must select a PMU via
+ * KVM_ARM_VCPU_PMU_V3_SET_PMU.
*/
- if (kvm_vcpu_has_pmu(vcpu) && !kvm->arch.arm_pmu)
+ if (kvm_vcpu_has_pmu(vcpu) && !kvm->arch.arm_pmu &&
+ !kvm_vcpu_has_pmuv3_strict(vcpu))
ret = kvm_arm_set_default_pmu(kvm);
/* Prepare for nested if required */
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index e1860acae641..1f24169505a9 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -923,6 +923,9 @@ void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu)
int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
{
+ if (!vcpu->kvm->arch.arm_pmu)
+ return -EINVAL;
+
if (!vcpu->arch.pmu.created)
return -EINVAL;
@@ -1021,6 +1024,14 @@ u8 kvm_arm_pmu_get_max_counters(struct kvm *kvm)
{
struct arm_pmu *arm_pmu = kvm->arch.arm_pmu;
+ /*
+ * Under KVM_ARM_VCPU_PMU_V3_STRICT no PMU exists until userspace sets
+ * one, so this can be reached before arm_pmu is set. Report no
+ * counters in that case.
+ */
+ if (!arm_pmu)
+ return 0;
+
/*
* PMUv3 requires that all event counters are capable of counting any
* event, though the same may not be true of non-PMUv3 hardware.
@@ -1062,7 +1073,8 @@ static void kvm_arm_set_pmu(struct kvm *kvm, struct arm_pmu *arm_pmu)
}
/**
- * kvm_arm_set_default_pmu - No PMU set, get the default one.
+ * kvm_arm_set_default_pmu - No PMU set and KVM_ARM_VCPU_PMU_V3_STRICT not
+ * set, get the default one.
* @kvm: The kvm pointer
*
* The observant among you will notice that the supported_cpus
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 0a36a3d5c894..13468bd5bbf2 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -76,6 +76,9 @@ void kvm_vcpu_pmu_resync_el0(void);
#define kvm_vcpu_has_pmu(vcpu) \
(vcpu_has_feature(vcpu, KVM_ARM_VCPU_PMU_V3))
+#define kvm_vcpu_has_pmuv3_strict(vcpu) \
+ (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PMU_V3_STRICT))
+
/*
* Updates the vcpu's view of the pmu events for this cpu.
* Must be called before every vcpu run after disabling interrupts, to ensure
@@ -161,6 +164,7 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
}
#define kvm_vcpu_has_pmu(vcpu) ({ false; })
+#define kvm_vcpu_has_pmuv3_strict(vcpu) ({ false; })
static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {}
static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h
index 1c13bfa2d38a..019e5e3d892e 100644
--- a/tools/arch/arm64/include/uapi/asm/kvm.h
+++ b/tools/arch/arm64/include/uapi/asm/kvm.h
@@ -106,6 +106,7 @@ struct kvm_regs {
#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
#define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */
#define KVM_ARM_VCPU_HAS_EL2_E2H0 8 /* Limit NV support to E2H RES0 */
+#define KVM_ARM_VCPU_PMU_V3_STRICT 9 /* No default PMU creation */
struct kvm_vcpu_init {
__u32 target;
--
2.50.1
^ permalink raw reply related
* [PATCH v2 0/3] KVM: arm64: Expose PMMIR_EL1.SLOTS to guests
From: Congkai Tan @ 2026-07-02 19:04 UTC (permalink / raw)
To: Oliver Upton, kvmarm, linux-arm-kernel
Cc: Congkai Tan, Marc Zyngier, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Catalin Marinas, Will Deacon, Paolo Bonzini,
Jonathan Corbet, Haris Okanovic, Geoff Blake, Stanislav Spassov,
kvm, linux-doc, linux-kselftest, linux-kernel
Today when the perf tool runs in a guest on cores with PMUv3p4, it fails
to parse the default metrics with "Failure to read '#slots'", since perf
can only read 0 from sysfs caps/slots, which is backed by PMMIR_EL1.SLOTS
that KVM traps as RAZ/WI.
Taking into account backward compatibility and heterogeneous systems, the
exposure of PMMIR_EL1.SLOTS is gated behind a new vCPU feature flag:
- Patch 1 adds the new flag KVM_ARM_VCPU_PMU_V3_STRICT. When set, KVM does
not create a default PMU during vCPU init, and the VMM must select one
explicitly via KVM_ARM_VCPU_PMU_V3_SET_PMU before the first KVM_RUN.
- Patch 2 exposes PMMIR_EL1.SLOTS of the selected PMU under the flag, and
adds userspace get/set for PMMIR_EL1 so that SLOTS can be reset to 0
for backward compatibility.
- Patch 3 stops masking STALL_SLOT* in PMCEID1 under the flag.
When the flag is not set, behaviors are unchanged.
v1: https://lore.kernel.org/r/20260601193954.2103455-1-congkai@amazon.com
v1 -> v2 changes:
- Gate the whole feature behind a new KVM_ARM_VCPU_PMU_V3_STRICT vCPU
feature flag, instead of unconditionally exposing PMMIR_EL1.SLOTS.
- When the flag is set, skip creating a default PMU during vCPU init.
- Split the PMCEID1 unmask into its own patch, also gated by the flag.
- Snapshot SLOTS into a new field pmmir_slots in kvm_arch during the
handling of KVM_ARM_VCPU_PMU_V3_SET_PMU when the flag is set;
access_pmmir()/get_pmmir() return it and set_pmmir() only accepts the
SLOTS field (rejecting other bits with -EINVAL).
- Add get_user and set_user for PMMIR_EL1 to support setting the SLOTS
back to 0, and add PMMIR_EL1 to the get-reg-list selftest.
Congkai Tan (3):
KVM: arm64: Add KVM_ARM_VCPU_PMU_V3_STRICT vCPU feature
KVM: arm64: Expose PMMIR_EL1.SLOTS under strict PMUv3 UAPI
KVM: arm64: Advertise STALL_SLOT* in PMCEID1 under strict PMUv3 UAPI
Documentation/virt/kvm/api.rst | 5 ++
arch/arm64/include/asm/kvm_host.h | 5 +-
arch/arm64/include/uapi/asm/kvm.h | 1 +
arch/arm64/kvm/arm.c | 18 +++++--
arch/arm64/kvm/pmu-emul.c | 50 ++++++++++++++-----
arch/arm64/kvm/sys_regs.c | 63 +++++++++++++++++++++++-
include/kvm/arm_pmu.h | 4 ++
tools/arch/arm64/include/uapi/asm/kvm.h | 1 +
tools/testing/selftests/kvm/arm64/get-reg-list.c | 1 +
9 files changed, 128 insertions(+), 20 deletions(-)
base-commit: 1702da76e017ae0fbe1a92b07bc332972c293e89
--
2.50.1
^ permalink raw reply
* [PATCH v2 3/3] KVM: arm64: Advertise STALL_SLOT* in PMCEID1 under strict PMUv3 UAPI
From: Congkai Tan @ 2026-07-02 19:04 UTC (permalink / raw)
To: Oliver Upton, kvmarm, linux-arm-kernel
Cc: Congkai Tan, Marc Zyngier, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Catalin Marinas, Will Deacon, Paolo Bonzini,
Jonathan Corbet, Haris Okanovic, Geoff Blake, Stanislav Spassov,
kvm, linux-doc, linux-kselftest, linux-kernel
In-Reply-To: <20260702190421.420992-1-congkai@amazon.com>
Skip masking STALL_SLOT, STALL_SLOT_FRONTEND and STALL_SLOT_BACKEND out
of PMCEID1 when KVM_ARM_VCPU_PMU_V3_STRICT is set, because this is when
PMMIR_EL1.SLOTS is exposed to guests, making these events meaningful for
collection.
Change the parameter of compute_pmceid1() from arm_pmu to kvm_vcpu, to
check if KVM_ARM_VCPU_PMU_V3_STRICT is set. Also updated the signature of
compute_pmceid0() for consistency.
Signed-off-by: Congkai Tan <congkai@amazon.com>
Reviewed-by: Geoff Blake <blakgeof@amazon.com>
Reviewed-by: Haris Okanovic <harisokn@amazon.com>
Reviewed-by: Stanislav Spassov <stanspas@amazon.de>
---
arch/arm64/kvm/pmu-emul.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index 9595bce6519f..89eec5a1a499 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -851,9 +851,9 @@ static u64 __compute_pmceid(struct arm_pmu *pmu, bool pmceid1)
return ((u64)hi[pmceid1] << 32) | lo[pmceid1];
}
-static u64 compute_pmceid0(struct arm_pmu *pmu)
+static u64 compute_pmceid0(struct kvm_vcpu *vcpu)
{
- u64 val = __compute_pmceid(pmu, 0);
+ u64 val = __compute_pmceid(vcpu->kvm->arch.arm_pmu, 0);
/* always support SW_INCR */
val |= BIT(ARMV8_PMUV3_PERFCTR_SW_INCR);
@@ -862,32 +862,33 @@ static u64 compute_pmceid0(struct arm_pmu *pmu)
return val;
}
-static u64 compute_pmceid1(struct arm_pmu *pmu)
+static u64 compute_pmceid1(struct kvm_vcpu *vcpu)
{
- u64 val = __compute_pmceid(pmu, 1);
+ u64 val = __compute_pmceid(vcpu->kvm->arch.arm_pmu, 1);
/*
- * Don't advertise STALL_SLOT*, as PMMIR_EL0 is handled
- * as RAZ
+ * If KVM_ARM_VCPU_PMU_V3_STRICT is not set, PMMIR_EL1 is
+ * unconditionally RAZ, so don't advertise STALL_SLOT* events.
*/
- val &= ~(BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32) |
- BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND - 32) |
- BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND - 32));
+ if (!kvm_vcpu_has_pmuv3_strict(vcpu))
+ val &= ~(BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32) |
+ BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND - 32) |
+ BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND - 32));
+
return val;
}
u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
{
- struct arm_pmu *cpu_pmu = vcpu->kvm->arch.arm_pmu;
unsigned long *bmap = vcpu->kvm->arch.pmu_filter;
u64 val, mask = 0;
int base, i, nr_events;
if (!pmceid1) {
- val = compute_pmceid0(cpu_pmu);
+ val = compute_pmceid0(vcpu);
base = 0;
} else {
- val = compute_pmceid1(cpu_pmu);
+ val = compute_pmceid1(vcpu);
base = 32;
}
--
2.50.1
^ permalink raw reply related
* Re: [PATCH v7 0/2] arm64: dts: rockchip: add Vicharak Axon board support
From: Heiko Stuebner @ 2026-07-02 19:04 UTC (permalink / raw)
To: Hrushiraj Gandhi
Cc: Heiko Stuebner, Krzysztof Kozlowski, Rob Herring, Conor Dooley,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20260608060940.52549-1-hrushirajg23@gmail.com>
On Mon, 08 Jun 2026 11:39:38 +0530, Hrushiraj Gandhi wrote:
> This series adds initial device tree support for the Vicharak Axon
> single-board computer, which is based on the Rockchip RK3588 SoC.
>
> The Vicharak Axon is a feature-rich SBC targeting developer and embedded
> use cases. It ships with:
>
> - Rockchip RK3588 (4x Cortex-A76 + 4x Cortex-A55)
> - RK806 PMIC providing all SoC power domains
> - eMMC 5.1 (on-board) and microSD slot
> - Gigabit Ethernet via RGMII (RTL8211F)
> - Dual HDMI 2.1 output and one HDMI 2.0 input (receiver)
> - PCIe 3.0 x4 and two PCIe 2.0 slots
> - SATA 3.0
> - USB 2.0 host ports (EHCI/OHCI)
> - NXP PCA9554 I/O expander for status LEDs
> - Haoyu HYM8563 RTC
>
> [...]
Applied, thanks!
[1/2] dt-bindings: arm: rockchip: add Vicharak Axon board
commit: e0008b108aaf8c5aa22930b2ceadf8f894562acb
[2/2] arm64: dts: rockchip: add Vicharak Axon board
commit: e08c3389c78dbefd31a57df8807cf57ef6f3c9b1
Please check for double empty lines and ordering in future patches.
I've cleaned up some things.
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Add Vicharak Vaaman2 board support
From: Heiko Stuebner @ 2026-07-02 19:04 UTC (permalink / raw)
To: linux-rockchip, devicetree, linux-arm-kernel, linux-kernel,
Hrushiraj Gandhi
Cc: Heiko Stuebner, robh, krzk+dt, conor+dt
In-Reply-To: <20260627102633.86222-1-hrushirajg23@gmail.com>
On Sat, 27 Jun 2026 15:56:31 +0530, Hrushiraj Gandhi wrote:
> This patch series adds device tree support for the Vicharak Vaaman2,
> a single-board computer based on the Rockchip RK3588 SoC.
>
> The Vaaman2 board features include:
> - RK3588 SoC
> - eMMC storage and microSD support
> - RK806 PMIC and multiple RK8602/RK8603 regulators
> - Real-time clock and status LED
> - UART serial console and SARADC
>
> [...]
Applied, thanks!
[1/2] dt-bindings: arm: rockchip: Add Vicharak Vaaman2
commit: b4a5e628936cc01ccfa713115bc56b46e798ebff
[2/2] arm64: dts: rockchip: Add Vicharak Vaaman2 board
commit: 0aec094dff13ab5526a3e602243576c3ac993ec3
Please check for double empty lines and ordering in future patches.
I've cleaned up some things.
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH] arm64: dts: rockchip: fix eMMC reset polarity on PX30 Ringneck
From: Heiko Stuebner @ 2026-07-02 19:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Quentin Schulz,
Quentin Schulz
Cc: Heiko Stuebner, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Quentin Schulz, stable
In-Reply-To: <20260626-ringneck-emmc-polarity-v1-1-90cefe57b316@cherry.de>
On Fri, 26 Jun 2026 16:40:38 +0200, Quentin Schulz wrote:
> According to the Jedec 5.1 specification, the device is held in reset
> when RST_n is low, therefore the polarity of the line must be that, as
> specified in the Device Tree binding (mmc/mmc-pwrseq-emmc.yaml).
>
> Due to the wrong polarity, eMMC devices with RST_n_FUNCTION[162]
> bitfield [1:0] set to 0x1 (the default is 0x0) will be held in reset
> forever.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: fix eMMC reset polarity on PX30 Ringneck
commit: 549081d9af61cf046cac15281e9a6ceb9b2592e9
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH] arm64: dts: rockchip: fix regulator names on NanoPC-T6
From: Heiko Stuebner @ 2026-07-02 19:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ricardo Pardini
Cc: Heiko Stuebner, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Sebastian Reichel
In-Reply-To: <20260605-rk3588-dts-rockchip-nanopct6-fix-schematic-names-v1-1-15dd3b23ab1a@pardini.net>
On Fri, 05 Jun 2026 13:54:35 +0200, Ricardo Pardini wrote:
> Three fixed-regulator names on the NanoPC-T6 don't match the board
> schematic [1].
>
> - vcc3v3_pcie2x1l0 -> vdd_mpcie_3v3
> This GPIO-switched 3v3 regulator is labeled vcc3v3_pcie2x1l0, but
> it is wired to and consumed by &pcie2x1l1. Per the schematic,
> the GPIO PCIE_M2_1_PWREN controls the power net VDD_MPCIE_3.3V;
> rename to match.
> - vdd_2v0_pldo_s3 -> vcc_2v0_pldo_s3
> Typo in the regulator-name property of RK806-1 DCDC reg7. The node
> label and the schematic power-net name both already use the vcc_
> form; only the regulator-name string had vdd_.
> - vcc3v3_pcie30 -> vcc3v3_pcie_m2_0
> The GPIO-switched 3v3 feeding the M.2 M-Key (NVMe) slot is named
> after the PCIe controller it sits behind rather than the schematic
> power net. The schematic names it VCC3V3_PCIE_M2_0 (produced by an
> MP2143-based buck off VCC_5V0, enabled by PCIE_M2_0_PWREN); rename
> to match.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: fix regulator names on NanoPC-T6
commit: e53bb7bffd4d359b68e8256bc0ebf5a119ba3c71
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH v11 0/3] Add eDP support for RK3576
From: Heiko Stuebner @ 2026-07-02 19:04 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, Damon Ding
Cc: Heiko Stuebner, sebastian.reichel, nicolas.frattaroli, alchark,
detlev.casanova, cristian.ciocaltea, michael.riesch, andy.yan,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20260605022305.3058853-1-damon.ding@rock-chips.com>
On Fri, 05 Jun 2026 10:23:02 +0800, Damon Ding wrote:
> Picked from:
> https://lore.kernel.org/all/20260601065100.1103873-1-damon.ding@rock-chips.com/
>
> Patch 1-2 are to add missing clock "hclk" for RK3588 eDP nodes.
> Patch 3 is to add the RK3576 eDP node.
>
> Damon Ding (3):
> arm64: dts: rockchip: Add missing hclk for RK3588 eDP0
> arm64: dts: rockchip: Add missing hclk for RK3588 eDP1
> arm64: dts: rockchip: Add eDP node for RK3576
>
> [...]
Applied, thanks!
[1/3] arm64: dts: rockchip: Add missing hclk for RK3588 eDP0
commit: 5603ce4f1d470af29e0cc76e36ea99e62fa07151
[2/3] arm64: dts: rockchip: Add missing hclk for RK3588 eDP1
commit: 6f1ed82b7f084c13bffcaa9e2c7acf5bc64b659b
[3/3] arm64: dts: rockchip: Add eDP node for RK3576
commit: 65bdf72f7fda3b1a24bd6f5ea15ce40ec2cc3e0a
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Add HINLINK H28K
From: Heiko Stuebner @ 2026-07-02 19:04 UTC (permalink / raw)
To: Chukun Pan
Cc: Heiko Stuebner, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-arm-kernel, linux-rockchip, linux-kernel, devicetree
In-Reply-To: <20260610100006.366963-1-amadeus@jmu.edu.cn>
On Wed, 10 Jun 2026 18:00:04 +0800, Chukun Pan wrote:
> The HINLINK H28K is a dual-gigabit SBC based on the RK3528 SoC.
>
> There is a version that SeeedStudio distributes called LinkStar-H28K.
> It's no different from the HINLINK H28K. The schematic can be found here:
>
> https://www.hinlink.cn/wp-content/uploads/2024/03/20240428015024130824.pdf
> https://files.seeedstudio.com/wiki/H28K/Open_source/H28K-SCH.zip
>
> [...]
Applied, thanks!
[1/2] dt-bindings: arm: rockchip: Add HINLINK H28K
commit: dce1f5a78a4f645ec3fae9b45b1453b989d3fc69
[2/2] arm64: dts: rockchip: Add HINLINK H28K
commit: 145d4af4b204e1fb565a498c6c8f801525cc0a4e
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH 0/3] arm64: dts: rockchip: Add Youyeetoo YY3588
From: Heiko Stuebner @ 2026-07-02 19:04 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Daniele Briguglio
Cc: Heiko Stuebner, devicetree, linux-kernel, linux-arm-kernel,
linux-rockchip
In-Reply-To: <20260610-yy3588-board-v1-0-4bb7176b6826@superkali.me>
On Wed, 10 Jun 2026 15:58:57 +0200, Daniele Briguglio wrote:
> This series adds support for the Youyeetoo YY3588, a single board
> computer built around the Rockchip RK3588.
>
> Both Ethernet ports, eMMC, SD card, USB, Type-C, HDMI output, WiFi on
> the Mini PCIe slot, audio, the recovery key and the fan have been
> tested on the board.
>
> [...]
Applied, thanks!
[1/3] dt-bindings: vendor-prefixes: Add youyeetoo
commit: fe76e3493f9ea5e927f9ce6bfe7f8785ba2d0c44
[2/3] dt-bindings: arm: rockchip: Add Youyeetoo YY3588
commit: 1e476370fbb1def308e6da3785843f1d34529721
[3/3] arm64: dts: rockchip: Add Youyeetoo YY3588
commit: 19847bde695f7bc65b16840c91cda4c2e35b36ce
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH RFC v5 00/12] ZTE zx297520v3 clock bindings and driver
From: Conor Dooley @ 2026-07-02 19:05 UTC (permalink / raw)
To: Stefan Dösinger
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <ihPM7P2dSn-oiyaL8fageA@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2303 bytes --]
On Wed, Jul 01, 2026 at 08:22:21PM +0300, Stefan Dösinger wrote:
> Am Montag, 29. Juni 2026, 18:49:08 Ostafrikanische Zeit schrieb Conor Dooley:
>
> > Bindings seem fine to me, I'll be happy to give you some r-b tags when
> > you go non-RFC. To be frank, I think you should drop them as you've got
> > no significant questions here I think and you'll be taken a bt more
> > seriously.
>
> Thanks for all the advice so far!
>
> Here's one more binding related question: Philipp's request to give the PHY
> reset its own reset ID means I need a node and driver to consume that reset.
> My question is if it should be another MFD subdevice of topcrm or not. I am
> leaning towards not:
>
> usb_phy: phy@2 {
> compatible = "zte,zx29-usb2-phy";
> interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 43
> IRQ_TYPE_EDGE_RISING>;
> interrupt-names = "powerup", "powerdown";
> syscon = <&topcrm 0x84 0x2>;
> resets = <&topcrm ZX297520V3_USB_PHY_RESET>;
> reset-names = "phy";
> #phy-cells = <0>;
Where is this node's reg property?
What bus is this node on?
It looks like the answer to both is that it should be a child of the
topcrm and this "syscon" property should be replaced by "reg".
> };
>
> usb0: usb@1500000 {
> compatible = "snps,dwc2";
> reg = <0x01500000 0x1000>;
> ...
> phys = <&usb_phy>;
> phy-names = "usb2-phy";
> };
>
> I am not aware of any IO region to configure the PHY, although one may exist.
> topcrm + 0x84 has two status bits reporting if USB and HSIC are powered and
> out of reset. Nevertheless, the PHY feels distinct enough from topcrm that it
> should have its own binding. The phy driver would merely deassert the reset
This is the sort of thing that should be a child node of the syscon,
rather than integrated into the parent, given it consumes resources from
another feature of the syscon.
> and wait for the ready bit and maybe in the future do something useful with
> the connect/disconnect IRQs.
>
> Interestingly the USB IO region is actually downstream of the AHB bus and
> matrix controller, but it has its clocks and resets in topcrm. I suspect the
> purpose of this setup is to allow wake-by-USB IRQs while shutting down the
> main data path.
>
> Cheers,
> Stefan
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [PATCH] arm64: dts: rockchip: add HYM8563 RTC to Radxa CM5 IO board
From: Brian Mayer @ 2026-07-02 19:09 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, heiko
Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 357 bytes --]
Hi kernel team.
I was testing building the kernel for my radxa cm5+io shield, and it turns
out there is no rtc in the DTS, so I got it from the radxa files.
This is my first email to you, please help me correct it if something is
off the standards.
The commit attached does the trick. I used AI to assist me in this in
case you're
wondering.
Best, Brian
[-- Attachment #2: 0001-arm64-dts-rockchip-add-HYM8563-RTC-to-Radxa-CM5-IO-b.patch --]
[-- Type: application/octet-stream, Size: 1999 bytes --]
From 8841981021b5f98522ad44fe40e11d0c0e756534 Mon Sep 17 00:00:00 2001
From: Brian Mayer <bleemayer@gmail.com>
Date: Thu, 2 Jul 2026 14:51:51 -0300
Subject: [PATCH] arm64: dts: rockchip: add HYM8563 RTC to Radxa CM5 IO board
The Radxa CM5 IO carrier has a Haoyu HYM8563 real-time clock on I2C6 at
address 0x51, with its interrupt line on GPIO0_B0 and a CR1220 backup
battery holder. Without a device tree node, no /dev/rtc* appears even
when CONFIG_RTC_DRV_HYM8563 is enabled.
Describe the RTC, wire the interrupt pin with a pull-up, mark it as a
wakeup source, and point the rtc0 alias at it so RTC_HCTOSYS/SYSTOHC use
the external clock. Wiring matches Radxa's downstream board support.
Signed-off-by: Brian Mayer <bleemayer@gmail.com>
Tested-by: Brian Mayer <bleemayer@gmail.com>
---
.../dts/rockchip/rk3588s-radxa-cm5-io.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts
index af4a9bc01..1a2c72831 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts
@@ -19,6 +19,7 @@ / {
aliases {
ethernet0 = &gmac1;
mmc1 = &sdmmc;
+ rtc0 = &hym8563;
};
chosen {
@@ -198,6 +199,18 @@ usbc0_dp_altmode_mux: endpoint {
};
};
};
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int>;
+ wakeup-source;
+ };
};
&i2s5_8ch {
@@ -221,6 +234,12 @@ usbc0_int: usbc0-int {
};
};
+ hym8563 {
+ rtc_int: rtc-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
base-commit: 87320be9f0d24fce67631b7eef919f0b79c3e45c
--
2.54.0
^ permalink raw reply related
* [PATCH v2 0/4] arm64: Fixes and cleanups for cpu-feature-registers.rst
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
Peter Maydell noticed some missing updates to cpu-feature-registers.rst,
while looking at these a number of other other omissions and some
maintainability problems were observed. Several registers and many
bitfields have not been added.
Following discussion with Catalin we remove the numbering of the
registers in the first patch so that when we add the registers we can
add them in a roughly sorted order, then fix up the missing
documentation before sorting the existing entries in the file.
This whole area should have much better tooling, rather than having to
update multiple places and manually cross check several different places
including rarely used documentation we should be marking up the sysreg
descriptions and then either generating the data or validating against
manually updated copies. Manually updated copies seem like a good idea
for the ABI documentation since while it's more work that would force
review. I did start on some sketches, it seemed like it might make
sense to tackle along with using the MRS but the libraries for that
seem not to be progressing at any great rate, I'll dig the sketches out.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Changes in v2:
- Remove documentation for hidden registers.
- Fix typos.
- Link to v1: https://patch.msgid.link/20260522-arm64-cpu-ftr-regs-v1-0-19775b40faf0@kernel.org
---
Mark Brown (4):
arm64: Don't number registers in cpu-feature-registers.rst
arm64: Document missing bitfields in cpu-feature-registers.rst
arm64: Sort registers in cpu-feature-registers.rst
arm64: Remove hidden bitfields from cpu-feature-registers.rst
Documentation/arch/arm64/cpu-feature-registers.rst | 593 +++++++++++++--------
1 file changed, 364 insertions(+), 229 deletions(-)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260521-arm64-cpu-ftr-regs-bceb2d34376f
Best regards,
--
Mark Brown <broonie@kernel.org>
^ permalink raw reply
* [PATCH v2 1/4] arm64: Don't number registers in cpu-feature-registers.rst
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
In-Reply-To: <20260702-arm64-cpu-ftr-regs-v2-0-fe0b78f1bd93@kernel.org>
cpu-feature-regsters.rst documents the set of userspace visible ID
registers. At present the section for each register is numbered, this has
lead to the registers being documented in a haphazard order as new ones
have been added to the end of the list to avoid renumbering. Remove the
numbers so we can avoid this problem in future.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arch/arm64/cpu-feature-registers.rst | 26 +++++++++++-----------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index add66afc7b03..c6e5bc053c09 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -113,7 +113,7 @@ infrastructure:
4. List of registers with visible features
-------------------------------------------
- 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+ ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -146,7 +146,7 @@ infrastructure:
+------------------------------+---------+---------+
- 2) ID_AA64PFR0_EL1 - Processor Feature Register 0
+ ID_AA64PFR0_EL1 - Processor Feature Register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -173,7 +173,7 @@ infrastructure:
+------------------------------+---------+---------+
- 3) ID_AA64PFR1_EL1 - Processor Feature Register 1
+ ID_AA64PFR1_EL1 - Processor Feature Register 1
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -188,7 +188,7 @@ infrastructure:
+------------------------------+---------+---------+
- 4) MIDR_EL1 - Main ID Register
+ MIDR_EL1 - Main ID Register
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -208,7 +208,7 @@ infrastructure:
as available on the CPU where it is fetched and is not a system
wide safe value.
- 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+ ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -240,7 +240,7 @@ infrastructure:
| DPB | [3-0] | y |
+------------------------------+---------+---------+
- 6) ID_AA64MMFR0_EL1 - Memory model feature register 0
+ ID_AA64MMFR0_EL1 - Memory model feature register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -248,7 +248,7 @@ infrastructure:
| ECV | [63-60] | y |
+------------------------------+---------+---------+
- 7) ID_AA64MMFR2_EL1 - Memory model feature register 2
+ ID_AA64MMFR2_EL1 - Memory model feature register 2
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -256,7 +256,7 @@ infrastructure:
| AT | [35-32] | y |
+------------------------------+---------+---------+
- 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0
+ ID_AA64ZFR0_EL1 - SVE feature ID register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -282,7 +282,7 @@ infrastructure:
| SVEVer | [3-0] | y |
+------------------------------+---------+---------+
- 8) ID_AA64MMFR1_EL1 - Memory model feature register 1
+ ID_AA64MMFR1_EL1 - Memory model feature register 1
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -290,7 +290,7 @@ infrastructure:
| AFP | [47-44] | y |
+------------------------------+---------+---------+
- 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+ ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -312,7 +312,7 @@ infrastructure:
| WFXT | [3-0] | y |
+------------------------------+---------+---------+
- 10) MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+ MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -320,7 +320,7 @@ infrastructure:
| FPDP | [11-8] | y |
+------------------------------+---------+---------+
- 11) MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
+ MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
+------------------------------+---------+---------+
| Name | bits | visible |
@@ -334,7 +334,7 @@ infrastructure:
| SIMDLS | [11-8] | y |
+------------------------------+---------+---------+
- 12) ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+ ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+------------------------------+---------+---------+
| Name | bits | visible |
--
2.47.3
^ permalink raw reply related
* [PATCH v2 2/4] arm64: Document missing bitfields in cpu-feature-registers.rst
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
In-Reply-To: <20260702-arm64-cpu-ftr-regs-v2-0-fe0b78f1bd93@kernel.org>
We have been rather lax in updating the list of visible bitfields in the
ID registers in cpu-feature-registers.rst, it is currently missing several
of the registers and quite a few bitfields in existing registers. Bring it
into sync with current -next.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arch/arm64/cpu-feature-registers.rst | 146 +++++++++++++++++++++
1 file changed, 146 insertions(+)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index c6e5bc053c09..4b10980d4a40 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -113,6 +113,30 @@ infrastructure:
4. List of registers with visible features
-------------------------------------------
+ ID_AA64FPFR0_EL1 - Floating Point feature ID register 0
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | F8CVT | [31] | y |
+ +------------------------------+---------+---------+
+ | F8FMA | [30] | y |
+ +------------------------------+---------+---------+
+ | F8DP4 | [29] | y |
+ +------------------------------+---------+---------+
+ | F8DP2 | [28] | y |
+ +------------------------------+---------+---------+
+ | F8MM8 | [27] | y |
+ +------------------------------+---------+---------+
+ | F8MM4 | [26] | y |
+ +------------------------------+---------+---------+
+ | F16MM2 | [15] | y |
+ +------------------------------+---------+---------+
+ | F8E4M3 | [1] | y |
+ +------------------------------+---------+---------+
+ | F8E5M2 | [0] | y |
+ +------------------------------+---------+---------+
+
ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+------------------------------+---------+---------+
@@ -178,6 +202,8 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
+ | GCS | [47-44] | y |
+ +------------------------------+---------+---------+
| SME | [27-24] | y |
+------------------------------+---------+---------+
| MTE | [11-8] | y |
@@ -187,6 +213,17 @@ infrastructure:
| BT | [3-0] | y |
+------------------------------+---------+---------+
+ ID_AA64PFR2_EL1 - Processor Feature Register 2
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | FPMR | [35-32] | y |
+ +------------------------------+---------+---------+
+ | MTEFAR | [11-8] | y |
+ +------------------------------+---------+---------+
+ | MTESTOREONLY | [7-4] | y |
+ +------------------------------+---------+---------+
MIDR_EL1 - Main ID Register
@@ -213,6 +250,8 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
+ | LS64 | [63-60] | y |
+ +------------------------------+---------+---------+
| I8MM | [55-52] | y |
+------------------------------+---------+---------+
| DGH | [51-48] | y |
@@ -256,6 +295,68 @@ infrastructure:
| AT | [35-32] | y |
+------------------------------+---------+---------+
+ ID_AA64MMFR3_EL1 - Memory model feature register 3
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | S1POE | [19-16] | y |
+ +------------------------------+---------+---------+
+
+ ID_AA64SMFR0_EL1 - SME feature ID register 0
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | FA64 | [63] | y |
+ +------------------------------+---------+---------+
+ | LUT6 | [61] | y |
+ +------------------------------+---------+---------+
+ | LUTv2 | [60] | y |
+ +------------------------------+---------+---------+
+ | SMEver | [59-56] | y |
+ +------------------------------+---------+---------+
+ | I16I64 | [55-52] | y |
+ +------------------------------+---------+---------+
+ | F64F64 | [48] | y |
+ +------------------------------+---------+---------+
+ | I16I32 | [47-44] | y |
+ +------------------------------+---------+---------+
+ | B16B16 | [43] | y |
+ +------------------------------+---------+---------+
+ | F16F16 | [42] | y |
+ +------------------------------+---------+---------+
+ | F8F16 | [41] | y |
+ +------------------------------+---------+---------+
+ | F8F32 | [40] | y |
+ +------------------------------+---------+---------+
+ | I8I32 | [39-36] | y |
+ +------------------------------+---------+---------+
+ | F16F32 | [35] | y |
+ +------------------------------+---------+---------+
+ | B16F32 | [34] | y |
+ +------------------------------+---------+---------+
+ | BI32I32 | [33] | y |
+ +------------------------------+---------+---------+
+ | F32F32 | [32] | y |
+ +------------------------------+---------+---------+
+ | SF8FMA | [30] | y |
+ +------------------------------+---------+---------+
+ | SF8DP4 | [29] | y |
+ +------------------------------+---------+---------+
+ | SF8DP2 | [28] | y |
+ +------------------------------+---------+---------+
+ | SBitPerm | [25] | y |
+ +------------------------------+---------+---------+
+ | AES | [24] | y |
+ +------------------------------+---------+---------+
+ | SFEXPA | [23] | y |
+ +------------------------------+---------+---------+
+ | STMOP | [16] | y |
+ +------------------------------+---------+---------+
+ | SMOP4 | [0] | y |
+ +------------------------------+---------+---------+
+
ID_AA64ZFR0_EL1 - SVE feature ID register 0
+------------------------------+---------+---------+
@@ -265,6 +366,8 @@ infrastructure:
+------------------------------+---------+---------+
| F32MM | [55-52] | y |
+------------------------------+---------+---------+
+ | F16MM | [51-48] | y |
+ +------------------------------+---------+---------+
| I8MM | [47-44] | y |
+------------------------------+---------+---------+
| SM4 | [43-40] | y |
@@ -277,6 +380,8 @@ infrastructure:
+------------------------------+---------+---------+
| BitPerm | [19-16] | y |
+------------------------------+---------+---------+
+ | EltPerm | [15-12] | y |
+ +------------------------------+---------+---------+
| AES | [7-4] | y |
+------------------------------+---------+---------+
| SVEVer | [3-0] | y |
@@ -295,6 +400,8 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
+ | LUT | [59-56] | y |
+ +------------------------------+---------+---------+
| CSSC | [55-52] | y |
+------------------------------+---------+---------+
| RPRFM | [51-48] | y |
@@ -312,6 +419,18 @@ infrastructure:
| WFXT | [3-0] | y |
+------------------------------+---------+---------+
+ ID_AA64ISAR3_EL1 - Instruction set attribute register 3
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | FPRCVT | [31-28] | y |
+ +------------------------------+---------+---------+
+ | LSFE | [19-16] | y |
+ +------------------------------+---------+---------+
+ | FAMINMAX | [7-4] | y |
+ +------------------------------+---------+---------+
+
MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+------------------------------+---------+---------+
@@ -327,6 +446,10 @@ infrastructure:
+------------------------------+---------+---------+
| SIMDFMAC | [31-28] | y |
+------------------------------+---------+---------+
+ | FPHP | [27-24] | y |
+ +------------------------------+---------+---------+
+ | SIMDHP | [23-20] | y |
+ +------------------------------+---------+---------+
| SIMDSP | [19-16] | y |
+------------------------------+---------+---------+
| SIMDInt | [15-12] | y |
@@ -348,6 +471,29 @@ infrastructure:
| AES | [7-4] | y |
+------------------------------+---------+---------+
+ ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | I8MM | [27-24] | y |
+ +------------------------------+---------+---------+
+ | BF16 | [23-20] | y |
+ +------------------------------+---------+---------+
+ | SB | [15-12] | y |
+ +------------------------------+---------+---------+
+ | FHM | [11-8] | y |
+ +------------------------------+---------+---------+
+ | DP | [7-4] | y |
+ +------------------------------+---------+---------+
+
+ ID_PFR2_EL1 - AArch32 Processor Feature Register 2
+
+ +------------------------------+---------+---------+
+ | Name | bits | visible |
+ +------------------------------+---------+---------+
+ | SSBS | [7-4] | y |
+ +------------------------------+---------+---------+
Appendix I: Example
-------------------
--
2.47.3
^ permalink raw reply related
* [PATCH v2 3/4] arm64: Sort registers in cpu-feature-registers.rst
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
In-Reply-To: <20260702-arm64-cpu-ftr-regs-v2-0-fe0b78f1bd93@kernel.org>
In order to make it a bit easier to work with sort the list of registers in
cpu-feature-registers.rst lexically. There should be no content changes
resulting from this patch.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arch/arm64/cpu-feature-registers.rst | 223 +++++++++++----------
1 file changed, 112 insertions(+), 111 deletions(-)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index 4b10980d4a40..683bdd90c705 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -170,137 +170,161 @@ infrastructure:
+------------------------------+---------+---------+
- ID_AA64PFR0_EL1 - Processor Feature Register 0
+ ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | DIT | [51-48] | y |
+ | LS64 | [63-60] | y |
+------------------------------+---------+---------+
- | MPAM | [43-40] | n |
+ | I8MM | [55-52] | y |
+------------------------------+---------+---------+
- | SVE | [35-32] | y |
+ | DGH | [51-48] | y |
+------------------------------+---------+---------+
- | GIC | [27-24] | n |
+ | BF16 | [47-44] | y |
+------------------------------+---------+---------+
- | AdvSIMD | [23-20] | y |
+ | SB | [39-36] | y |
+------------------------------+---------+---------+
- | FP | [19-16] | y |
+ | FRINTTS | [35-32] | y |
+------------------------------+---------+---------+
- | EL3 | [15-12] | n |
+ | GPI | [31-28] | y |
+------------------------------+---------+---------+
- | EL2 | [11-8] | n |
+ | GPA | [27-24] | y |
+------------------------------+---------+---------+
- | EL1 | [7-4] | n |
+ | LRCPC | [23-20] | y |
+------------------------------+---------+---------+
- | EL0 | [3-0] | n |
+ | FCMA | [19-16] | y |
+ +------------------------------+---------+---------+
+ | JSCVT | [15-12] | y |
+ +------------------------------+---------+---------+
+ | API | [11-8] | y |
+ +------------------------------+---------+---------+
+ | APA | [7-4] | y |
+ +------------------------------+---------+---------+
+ | DPB | [3-0] | y |
+------------------------------+---------+---------+
-
- ID_AA64PFR1_EL1 - Processor Feature Register 1
+ ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | GCS | [47-44] | y |
+ | LUT | [59-56] | y |
+------------------------------+---------+---------+
- | SME | [27-24] | y |
+ | CSSC | [55-52] | y |
+------------------------------+---------+---------+
- | MTE | [11-8] | y |
+ | RPRFM | [51-48] | y |
+------------------------------+---------+---------+
- | SSBS | [7-4] | y |
+ | BC | [23-20] | y |
+------------------------------+---------+---------+
- | BT | [3-0] | y |
+ | MOPS | [19-16] | y |
+ +------------------------------+---------+---------+
+ | APA3 | [15-12] | y |
+ +------------------------------+---------+---------+
+ | GPA3 | [11-8] | y |
+ +------------------------------+---------+---------+
+ | RPRES | [7-4] | y |
+ +------------------------------+---------+---------+
+ | WFXT | [3-0] | y |
+------------------------------+---------+---------+
- ID_AA64PFR2_EL1 - Processor Feature Register 2
+ ID_AA64ISAR3_EL1 - Instruction set attribute register 3
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | FPMR | [35-32] | y |
+ | FPRCVT | [31-28] | y |
+------------------------------+---------+---------+
- | MTEFAR | [11-8] | y |
+ | LSFE | [19-16] | y |
+------------------------------+---------+---------+
- | MTESTOREONLY | [7-4] | y |
+ | FAMINMAX | [7-4] | y |
+------------------------------+---------+---------+
- MIDR_EL1 - Main ID Register
+ ID_AA64MMFR0_EL1 - Memory model feature register 0
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | Implementer | [31-24] | y |
- +------------------------------+---------+---------+
- | Variant | [23-20] | y |
+ | ECV | [63-60] | y |
+------------------------------+---------+---------+
- | Architecture | [19-16] | y |
+
+ ID_AA64MMFR1_EL1 - Memory model feature register 1
+
+------------------------------+---------+---------+
- | PartNum | [15-4] | y |
+ | Name | bits | visible |
+------------------------------+---------+---------+
- | Revision | [3-0] | y |
+ | AFP | [47-44] | y |
+------------------------------+---------+---------+
- NOTE: The 'visible' fields of MIDR_EL1 will contain the value
- as available on the CPU where it is fetched and is not a system
- wide safe value.
-
- ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+ ID_AA64MMFR2_EL1 - Memory model feature register 2
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | LS64 | [63-60] | y |
+ | AT | [35-32] | y |
+------------------------------+---------+---------+
- | I8MM | [55-52] | y |
+
+ ID_AA64MMFR3_EL1 - Memory model feature register 3
+
+------------------------------+---------+---------+
- | DGH | [51-48] | y |
+ | Name | bits | visible |
+------------------------------+---------+---------+
- | BF16 | [47-44] | y |
+ | S1POE | [19-16] | y |
+------------------------------+---------+---------+
- | SB | [39-36] | y |
+
+ ID_AA64PFR0_EL1 - Processor Feature Register 0
+
+------------------------------+---------+---------+
- | FRINTTS | [35-32] | y |
+ | Name | bits | visible |
+------------------------------+---------+---------+
- | GPI | [31-28] | y |
+ | DIT | [51-48] | y |
+------------------------------+---------+---------+
- | GPA | [27-24] | y |
+ | MPAM | [43-40] | n |
+------------------------------+---------+---------+
- | LRCPC | [23-20] | y |
+ | SVE | [35-32] | y |
+------------------------------+---------+---------+
- | FCMA | [19-16] | y |
+ | GIC | [27-24] | n |
+------------------------------+---------+---------+
- | JSCVT | [15-12] | y |
+ | AdvSIMD | [23-20] | y |
+------------------------------+---------+---------+
- | API | [11-8] | y |
+ | FP | [19-16] | y |
+------------------------------+---------+---------+
- | APA | [7-4] | y |
+ | EL3 | [15-12] | n |
+------------------------------+---------+---------+
- | DPB | [3-0] | y |
+ | EL2 | [11-8] | n |
+ +------------------------------+---------+---------+
+ | EL1 | [7-4] | n |
+ +------------------------------+---------+---------+
+ | EL0 | [3-0] | n |
+------------------------------+---------+---------+
- ID_AA64MMFR0_EL1 - Memory model feature register 0
+
+ ID_AA64PFR1_EL1 - Processor Feature Register 1
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | ECV | [63-60] | y |
+ | GCS | [47-44] | y |
+------------------------------+---------+---------+
-
- ID_AA64MMFR2_EL1 - Memory model feature register 2
-
+ | SME | [27-24] | y |
+------------------------------+---------+---------+
- | Name | bits | visible |
+ | MTE | [11-8] | y |
+------------------------------+---------+---------+
- | AT | [35-32] | y |
+ | SSBS | [7-4] | y |
+ +------------------------------+---------+---------+
+ | BT | [3-0] | y |
+------------------------------+---------+---------+
- ID_AA64MMFR3_EL1 - Memory model feature register 3
+ ID_AA64PFR2_EL1 - Processor Feature Register 2
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | S1POE | [19-16] | y |
+ | FPMR | [35-32] | y |
+ +------------------------------+---------+---------+
+ | MTEFAR | [11-8] | y |
+ +------------------------------+---------+---------+
+ | MTESTOREONLY | [7-4] | y |
+------------------------------+---------+---------+
ID_AA64SMFR0_EL1 - SME feature ID register 0
@@ -387,50 +411,64 @@ infrastructure:
| SVEVer | [3-0] | y |
+------------------------------+---------+---------+
- ID_AA64MMFR1_EL1 - Memory model feature register 1
+ ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | AFP | [47-44] | y |
+ | CRC32 | [19-16] | y |
+ +------------------------------+---------+---------+
+ | SHA2 | [15-12] | y |
+ +------------------------------+---------+---------+
+ | SHA1 | [11-8] | y |
+ +------------------------------+---------+---------+
+ | AES | [7-4] | y |
+------------------------------+---------+---------+
- ID_AA64ISAR2_EL1 - Instruction set attribute register 2
+ ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | LUT | [59-56] | y |
- +------------------------------+---------+---------+
- | CSSC | [55-52] | y |
+ | I8MM | [27-24] | y |
+------------------------------+---------+---------+
- | RPRFM | [51-48] | y |
+ | BF16 | [23-20] | y |
+------------------------------+---------+---------+
- | BC | [23-20] | y |
+ | SB | [15-12] | y |
+------------------------------+---------+---------+
- | MOPS | [19-16] | y |
+ | FHM | [11-8] | y |
+------------------------------+---------+---------+
- | APA3 | [15-12] | y |
+ | DP | [7-4] | y |
+------------------------------+---------+---------+
- | GPA3 | [11-8] | y |
+
+ ID_PFR2_EL1 - AArch32 Processor Feature Register 2
+
+------------------------------+---------+---------+
- | RPRES | [7-4] | y |
+ | Name | bits | visible |
+------------------------------+---------+---------+
- | WFXT | [3-0] | y |
+ | SSBS | [7-4] | y |
+------------------------------+---------+---------+
- ID_AA64ISAR3_EL1 - Instruction set attribute register 3
+ MIDR_EL1 - Main ID Register
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | FPRCVT | [31-28] | y |
+ | Implementer | [31-24] | y |
+------------------------------+---------+---------+
- | LSFE | [19-16] | y |
+ | Variant | [23-20] | y |
+------------------------------+---------+---------+
- | FAMINMAX | [7-4] | y |
+ | Architecture | [19-16] | y |
+ +------------------------------+---------+---------+
+ | PartNum | [15-4] | y |
+ +------------------------------+---------+---------+
+ | Revision | [3-0] | y |
+------------------------------+---------+---------+
+ NOTE: The 'visible' fields of MIDR_EL1 will contain the value
+ as available on the CPU where it is fetched and is not a system
+ wide safe value.
+
MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+------------------------------+---------+---------+
@@ -457,43 +495,6 @@ infrastructure:
| SIMDLS | [11-8] | y |
+------------------------------+---------+---------+
- ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
-
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | CRC32 | [19-16] | y |
- +------------------------------+---------+---------+
- | SHA2 | [15-12] | y |
- +------------------------------+---------+---------+
- | SHA1 | [11-8] | y |
- +------------------------------+---------+---------+
- | AES | [7-4] | y |
- +------------------------------+---------+---------+
-
- ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
-
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | I8MM | [27-24] | y |
- +------------------------------+---------+---------+
- | BF16 | [23-20] | y |
- +------------------------------+---------+---------+
- | SB | [15-12] | y |
- +------------------------------+---------+---------+
- | FHM | [11-8] | y |
- +------------------------------+---------+---------+
- | DP | [7-4] | y |
- +------------------------------+---------+---------+
-
- ID_PFR2_EL1 - AArch32 Processor Feature Register 2
-
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | SSBS | [7-4] | y |
- +------------------------------+---------+---------+
Appendix I: Example
-------------------
--
2.47.3
^ permalink raw reply related
* [PATCH v2 4/4] arm64: Remove hidden bitfields from cpu-feature-registers.rst
From: Mark Brown @ 2026-07-02 19:11 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Jonathan Corbet, Shuah Khan
Cc: Peter Maydell, Joey Gouly, linux-arm-kernel, linux-doc,
linux-kernel, Mark Brown
In-Reply-To: <20260702-arm64-cpu-ftr-regs-v2-0-fe0b78f1bd93@kernel.org>
We currently have a visibility column in the tables for the registers in
cpu-feature-registers.rst but this is always "y" for every register other
than ID_AA64PFR0_EL1. Given that the documentation of the full set of
bitfields is readily available in the architecture documentation it is
redundant for us to explicitly document things we don't advertise, and the
kernel documentation will inevitably lag the architecture.
Just remove the visibility column and hidden bitfields.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arch/arm64/cpu-feature-registers.rst | 618 ++++++++++-----------
1 file changed, 303 insertions(+), 315 deletions(-)
diff --git a/Documentation/arch/arm64/cpu-feature-registers.rst b/Documentation/arch/arm64/cpu-feature-registers.rst
index 683bdd90c705..fc63ccb666bf 100644
--- a/Documentation/arch/arm64/cpu-feature-registers.rst
+++ b/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -115,355 +115,343 @@ infrastructure:
ID_AA64FPFR0_EL1 - Floating Point feature ID register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | F8CVT | [31] | y |
- +------------------------------+---------+---------+
- | F8FMA | [30] | y |
- +------------------------------+---------+---------+
- | F8DP4 | [29] | y |
- +------------------------------+---------+---------+
- | F8DP2 | [28] | y |
- +------------------------------+---------+---------+
- | F8MM8 | [27] | y |
- +------------------------------+---------+---------+
- | F8MM4 | [26] | y |
- +------------------------------+---------+---------+
- | F16MM2 | [15] | y |
- +------------------------------+---------+---------+
- | F8E4M3 | [1] | y |
- +------------------------------+---------+---------+
- | F8E5M2 | [0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | F8CVT | [31] |
+ +------------------------------+---------+
+ | F8FMA | [30] |
+ +------------------------------+---------+
+ | F8DP4 | [29] |
+ +------------------------------+---------+
+ | F8DP2 | [28] |
+ +------------------------------+---------+
+ | F8MM8 | [27] |
+ +------------------------------+---------+
+ | F8MM4 | [26] |
+ +------------------------------+---------+
+ | F16MM2 | [15] |
+ +------------------------------+---------+
+ | F8E4M3 | [1] |
+ +------------------------------+---------+
+ | F8E5M2 | [0] |
+ +------------------------------+---------+
ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | RNDR | [63-60] | y |
- +------------------------------+---------+---------+
- | TS | [55-52] | y |
- +------------------------------+---------+---------+
- | FHM | [51-48] | y |
- +------------------------------+---------+---------+
- | DP | [47-44] | y |
- +------------------------------+---------+---------+
- | SM4 | [43-40] | y |
- +------------------------------+---------+---------+
- | SM3 | [39-36] | y |
- +------------------------------+---------+---------+
- | SHA3 | [35-32] | y |
- +------------------------------+---------+---------+
- | RDM | [31-28] | y |
- +------------------------------+---------+---------+
- | ATOMICS | [23-20] | y |
- +------------------------------+---------+---------+
- | CRC32 | [19-16] | y |
- +------------------------------+---------+---------+
- | SHA2 | [15-12] | y |
- +------------------------------+---------+---------+
- | SHA1 | [11-8] | y |
- +------------------------------+---------+---------+
- | AES | [7-4] | y |
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | RNDR | [63-60] |
+ +------------------------------+---------+
+ | TS | [55-52] |
+ +------------------------------+---------+
+ | FHM | [51-48] |
+ +------------------------------+---------+
+ | DP | [47-44] |
+ +------------------------------+---------+
+ | SM4 | [43-40] |
+ +------------------------------+---------+
+ | SM3 | [39-36] |
+ +------------------------------+---------+
+ | SHA3 | [35-32] |
+ +------------------------------+---------+
+ | RDM | [31-28] |
+ +------------------------------+---------+
+ | ATOMICS | [23-20] |
+ +------------------------------+---------+
+ | CRC32 | [19-16] |
+ +------------------------------+---------+
+ | SHA2 | [15-12] |
+ +------------------------------+---------+
+ | SHA1 | [11-8] |
+ +------------------------------+---------+
+ | AES | [7-4] |
+------------------------------+---------+---------+
ID_AA64ISAR1_EL1 - Instruction set attribute register 1
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | LS64 | [63-60] | y |
- +------------------------------+---------+---------+
- | I8MM | [55-52] | y |
- +------------------------------+---------+---------+
- | DGH | [51-48] | y |
- +------------------------------+---------+---------+
- | BF16 | [47-44] | y |
- +------------------------------+---------+---------+
- | SB | [39-36] | y |
- +------------------------------+---------+---------+
- | FRINTTS | [35-32] | y |
- +------------------------------+---------+---------+
- | GPI | [31-28] | y |
- +------------------------------+---------+---------+
- | GPA | [27-24] | y |
- +------------------------------+---------+---------+
- | LRCPC | [23-20] | y |
- +------------------------------+---------+---------+
- | FCMA | [19-16] | y |
- +------------------------------+---------+---------+
- | JSCVT | [15-12] | y |
- +------------------------------+---------+---------+
- | API | [11-8] | y |
- +------------------------------+---------+---------+
- | APA | [7-4] | y |
- +------------------------------+---------+---------+
- | DPB | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | LS64 | [63-60] |
+ +------------------------------+---------+
+ | I8MM | [55-52] |
+ +------------------------------+---------+
+ | DGH | [51-48] |
+ +------------------------------+---------+
+ | BF16 | [47-44] |
+ +------------------------------+---------+
+ | SB | [39-36] |
+ +------------------------------+---------+
+ | FRINTTS | [35-32] |
+ +------------------------------+---------+
+ | GPI | [31-28] |
+ +------------------------------+---------+
+ | GPA | [27-24] |
+ +------------------------------+---------+
+ | LRCPC | [23-20] |
+ +------------------------------+---------+
+ | FCMA | [19-16] |
+ +------------------------------+---------+
+ | JSCVT | [15-12] |
+ +------------------------------+---------+
+ | API | [11-8] |
+ +------------------------------+---------+
+ | APA | [7-4] |
+ +------------------------------+---------+
+ | DPB | [3-0] |
+ +------------------------------+---------+
ID_AA64ISAR2_EL1 - Instruction set attribute register 2
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | LUT | [59-56] | y |
- +------------------------------+---------+---------+
- | CSSC | [55-52] | y |
- +------------------------------+---------+---------+
- | RPRFM | [51-48] | y |
- +------------------------------+---------+---------+
- | BC | [23-20] | y |
- +------------------------------+---------+---------+
- | MOPS | [19-16] | y |
- +------------------------------+---------+---------+
- | APA3 | [15-12] | y |
- +------------------------------+---------+---------+
- | GPA3 | [11-8] | y |
- +------------------------------+---------+---------+
- | RPRES | [7-4] | y |
- +------------------------------+---------+---------+
- | WFXT | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | LUT | [59-56] |
+ +------------------------------+---------+
+ | CSSC | [55-52] |
+ +------------------------------+---------+
+ | RPRFM | [51-48] |
+ +------------------------------+---------+
+ | BC | [23-20] |
+ +------------------------------+---------+
+ | MOPS | [19-16] |
+ +------------------------------+---------+
+ | APA3 | [15-12] |
+ +------------------------------+---------+
+ | GPA3 | [11-8] |
+ +------------------------------+---------+
+ | RPRES | [7-4] |
+ +------------------------------+---------+
+ | WFXT | [3-0] |
+ +------------------------------+---------+
ID_AA64ISAR3_EL1 - Instruction set attribute register 3
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | FPRCVT | [31-28] | y |
- +------------------------------+---------+---------+
- | LSFE | [19-16] | y |
- +------------------------------+---------+---------+
- | FAMINMAX | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | FPRCVT | [31-28] |
+ +------------------------------+---------+
+ | LSFE | [19-16] |
+ +------------------------------+---------+
+ | FAMINMAX | [7-4] |
+ +------------------------------+---------+
ID_AA64MMFR0_EL1 - Memory model feature register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | ECV | [63-60] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | ECV | [63-60] |
+ +------------------------------+---------+
ID_AA64MMFR1_EL1 - Memory model feature register 1
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | AFP | [47-44] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | AFP | [47-44] |
+ +------------------------------+---------+
ID_AA64MMFR2_EL1 - Memory model feature register 2
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | AT | [35-32] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | AT | [35-32] |
+ +------------------------------+---------+
ID_AA64MMFR3_EL1 - Memory model feature register 3
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | S1POE | [19-16] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | S1POE | [19-16] |
+ +------------------------------+---------+
ID_AA64PFR0_EL1 - Processor Feature Register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | DIT | [51-48] | y |
- +------------------------------+---------+---------+
- | MPAM | [43-40] | n |
- +------------------------------+---------+---------+
- | SVE | [35-32] | y |
- +------------------------------+---------+---------+
- | GIC | [27-24] | n |
- +------------------------------+---------+---------+
- | AdvSIMD | [23-20] | y |
- +------------------------------+---------+---------+
- | FP | [19-16] | y |
- +------------------------------+---------+---------+
- | EL3 | [15-12] | n |
- +------------------------------+---------+---------+
- | EL2 | [11-8] | n |
- +------------------------------+---------+---------+
- | EL1 | [7-4] | n |
- +------------------------------+---------+---------+
- | EL0 | [3-0] | n |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | DIT | [51-48] |
+ +------------------------------+---------+
+ | SVE | [35-32] |
+ +------------------------------+---------+
+ | AdvSIMD | [23-20] |
+ +------------------------------+---------+
+ | FP | [19-16] |
+ +------------------------------+---------+
ID_AA64PFR1_EL1 - Processor Feature Register 1
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | GCS | [47-44] | y |
- +------------------------------+---------+---------+
- | SME | [27-24] | y |
- +------------------------------+---------+---------+
- | MTE | [11-8] | y |
- +------------------------------+---------+---------+
- | SSBS | [7-4] | y |
- +------------------------------+---------+---------+
- | BT | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | GCS | [47-44] |
+ +------------------------------+---------+
+ | SME | [27-24] |
+ +------------------------------+---------+
+ | MTE | [11-8] |
+ +------------------------------+---------+
+ | SSBS | [7-4] |
+ +------------------------------+---------+
+ | BT | [3-0] |
+ +------------------------------+---------+
ID_AA64PFR2_EL1 - Processor Feature Register 2
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | FPMR | [35-32] | y |
- +------------------------------+---------+---------+
- | MTEFAR | [11-8] | y |
- +------------------------------+---------+---------+
- | MTESTOREONLY | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | FPMR | [35-32] |
+ +------------------------------+---------+
+ | MTEFAR | [11-8] |
+ +------------------------------+---------+
+ | MTESTOREONLY | [7-4] |
+ +------------------------------+---------+
ID_AA64SMFR0_EL1 - SME feature ID register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | FA64 | [63] | y |
- +------------------------------+---------+---------+
- | LUT6 | [61] | y |
- +------------------------------+---------+---------+
- | LUTv2 | [60] | y |
- +------------------------------+---------+---------+
- | SMEver | [59-56] | y |
- +------------------------------+---------+---------+
- | I16I64 | [55-52] | y |
- +------------------------------+---------+---------+
- | F64F64 | [48] | y |
- +------------------------------+---------+---------+
- | I16I32 | [47-44] | y |
- +------------------------------+---------+---------+
- | B16B16 | [43] | y |
- +------------------------------+---------+---------+
- | F16F16 | [42] | y |
- +------------------------------+---------+---------+
- | F8F16 | [41] | y |
- +------------------------------+---------+---------+
- | F8F32 | [40] | y |
- +------------------------------+---------+---------+
- | I8I32 | [39-36] | y |
- +------------------------------+---------+---------+
- | F16F32 | [35] | y |
- +------------------------------+---------+---------+
- | B16F32 | [34] | y |
- +------------------------------+---------+---------+
- | BI32I32 | [33] | y |
- +------------------------------+---------+---------+
- | F32F32 | [32] | y |
- +------------------------------+---------+---------+
- | SF8FMA | [30] | y |
- +------------------------------+---------+---------+
- | SF8DP4 | [29] | y |
- +------------------------------+---------+---------+
- | SF8DP2 | [28] | y |
- +------------------------------+---------+---------+
- | SBitPerm | [25] | y |
- +------------------------------+---------+---------+
- | AES | [24] | y |
- +------------------------------+---------+---------+
- | SFEXPA | [23] | y |
- +------------------------------+---------+---------+
- | STMOP | [16] | y |
- +------------------------------+---------+---------+
- | SMOP4 | [0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | FA64 | [63] |
+ +------------------------------+---------+
+ | LUT6 | [61] |
+ +------------------------------+---------+
+ | LUTv2 | [60] |
+ +------------------------------+---------+
+ | SMEver | [59-56] |
+ +------------------------------+---------+
+ | I16I64 | [55-52] |
+ +------------------------------+---------+
+ | F64F64 | [48] |
+ +------------------------------+---------+
+ | I16I32 | [47-44] |
+ +------------------------------+---------+
+ | B16B16 | [43] |
+ +------------------------------+---------+
+ | F16F16 | [42] |
+ +------------------------------+---------+
+ | F8F16 | [41] |
+ +------------------------------+---------+
+ | F8F32 | [40] |
+ +------------------------------+---------+
+ | I8I32 | [39-36] |
+ +------------------------------+---------+
+ | F16F32 | [35] |
+ +------------------------------+---------+
+ | B16F32 | [34] |
+ +------------------------------+---------+
+ | BI32I32 | [33] |
+ +------------------------------+---------+
+ | F32F32 | [32] |
+ +------------------------------+---------+
+ | SF8FMA | [30] |
+ +------------------------------+---------+
+ | SF8DP4 | [29] |
+ +------------------------------+---------+
+ | SF8DP2 | [28] |
+ +------------------------------+---------+
+ | SBitPerm | [25] |
+ +------------------------------+---------+
+ | AES | [24] |
+ +------------------------------+---------+
+ | SFEXPA | [23] |
+ +------------------------------+---------+
+ | STMOP | [16] |
+ +------------------------------+---------+
+ | SMOP4 | [0] |
+ +------------------------------+---------+
ID_AA64ZFR0_EL1 - SVE feature ID register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | F64MM | [59-56] | y |
- +------------------------------+---------+---------+
- | F32MM | [55-52] | y |
- +------------------------------+---------+---------+
- | F16MM | [51-48] | y |
- +------------------------------+---------+---------+
- | I8MM | [47-44] | y |
- +------------------------------+---------+---------+
- | SM4 | [43-40] | y |
- +------------------------------+---------+---------+
- | SHA3 | [35-32] | y |
- +------------------------------+---------+---------+
- | B16B16 | [27-24] | y |
- +------------------------------+---------+---------+
- | BF16 | [23-20] | y |
- +------------------------------+---------+---------+
- | BitPerm | [19-16] | y |
- +------------------------------+---------+---------+
- | EltPerm | [15-12] | y |
- +------------------------------+---------+---------+
- | AES | [7-4] | y |
- +------------------------------+---------+---------+
- | SVEVer | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | F64MM | [59-56] |
+ +------------------------------+---------+
+ | F32MM | [55-52] |
+ +------------------------------+---------+
+ | F16MM | [51-48] |
+ +------------------------------+---------+
+ | I8MM | [47-44] |
+ +------------------------------+---------+
+ | SM4 | [43-40] |
+ +------------------------------+---------+
+ | SHA3 | [35-32] |
+ +------------------------------+---------+
+ | B16B16 | [27-24] |
+ +------------------------------+---------+
+ | BF16 | [23-20] |
+ +------------------------------+---------+
+ | BitPerm | [19-16] |
+ +------------------------------+---------+
+ | EltPerm | [15-12] |
+ +------------------------------+---------+
+ | AES | [7-4] |
+ +------------------------------+---------+
+ | SVEVer | [3-0] |
+ +------------------------------+---------+
ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | CRC32 | [19-16] | y |
- +------------------------------+---------+---------+
- | SHA2 | [15-12] | y |
- +------------------------------+---------+---------+
- | SHA1 | [11-8] | y |
- +------------------------------+---------+---------+
- | AES | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | CRC32 | [19-16] |
+ +------------------------------+---------+
+ | SHA2 | [15-12] |
+ +------------------------------+---------+
+ | SHA1 | [11-8] |
+ +------------------------------+---------+
+ | AES | [7-4] |
+ +------------------------------+---------+
ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | I8MM | [27-24] | y |
- +------------------------------+---------+---------+
- | BF16 | [23-20] | y |
- +------------------------------+---------+---------+
- | SB | [15-12] | y |
- +------------------------------+---------+---------+
- | FHM | [11-8] | y |
- +------------------------------+---------+---------+
- | DP | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | I8MM | [27-24] |
+ +------------------------------+---------+
+ | BF16 | [23-20] |
+ +------------------------------+---------+
+ | SB | [15-12] |
+ +------------------------------+---------+
+ | FHM | [11-8] |
+ +------------------------------+---------+
+ | DP | [7-4] |
+ +------------------------------+---------+
ID_PFR2_EL1 - AArch32 Processor Feature Register 2
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | SSBS | [7-4] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | SSBS | [7-4] |
+ +------------------------------+---------+
MIDR_EL1 - Main ID Register
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | Implementer | [31-24] | y |
- +------------------------------+---------+---------+
- | Variant | [23-20] | y |
- +------------------------------+---------+---------+
- | Architecture | [19-16] | y |
- +------------------------------+---------+---------+
- | PartNum | [15-4] | y |
- +------------------------------+---------+---------+
- | Revision | [3-0] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | Implementer | [31-24] |
+ +------------------------------+---------+
+ | Variant | [23-20] |
+ +------------------------------+---------+
+ | Architecture | [19-16] |
+ +------------------------------+---------+
+ | PartNum | [15-4] |
+ +------------------------------+---------+
+ | Revision | [3-0] |
+ +------------------------------+---------+
NOTE: The 'visible' fields of MIDR_EL1 will contain the value
as available on the CPU where it is fetched and is not a system
@@ -471,29 +459,29 @@ infrastructure:
MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | FPDP | [11-8] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | FPDP | [11-8] |
+ +------------------------------+---------+
MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
- +------------------------------+---------+---------+
- | Name | bits | visible |
- +------------------------------+---------+---------+
- | SIMDFMAC | [31-28] | y |
- +------------------------------+---------+---------+
- | FPHP | [27-24] | y |
- +------------------------------+---------+---------+
- | SIMDHP | [23-20] | y |
- +------------------------------+---------+---------+
- | SIMDSP | [19-16] | y |
- +------------------------------+---------+---------+
- | SIMDInt | [15-12] | y |
- +------------------------------+---------+---------+
- | SIMDLS | [11-8] | y |
- +------------------------------+---------+---------+
+ +------------------------------+---------+
+ | Name | bits |
+ +------------------------------+---------+
+ | SIMDFMAC | [31-28] |
+ +------------------------------+---------+
+ | FPHP | [27-24] |
+ +------------------------------+---------+
+ | SIMDHP | [23-20] |
+ +------------------------------+---------+
+ | SIMDSP | [19-16] |
+ +------------------------------+---------+
+ | SIMDInt | [15-12] |
+ +------------------------------+---------+
+ | SIMDLS | [11-8] |
+ +------------------------------+---------+
Appendix I: Example
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v6 3/5] mfd: aaeon: Add SRG-IMX8P MCU driver
From: Julian Braha @ 2026-07-02 19:12 UTC (permalink / raw)
To: Thomas Perrot (Schneider Electric), Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Linus Walleij,
Bartosz Golaszewski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
Jérémie Dautheribes, Wim Van Sebroeck, Guenter Roeck,
Lee Jones
Cc: devicetree, linux-kernel, linux-gpio, imx, linux-arm-kernel,
linux-watchdog, Thomas Petazzoni, Miquel Raynal
In-Reply-To: <20260630-dev-b4-aaeon-mcu-driver-v6-3-d66b5fcbd2f0@bootlin.com>
Hi Thomas,
On 6/30/26 13:51, Thomas Perrot (Schneider Electric) wrote:
> +config MFD_AAEON_MCU
> + tristate "Aaeon SRG-IMX8P MCU Driver"
> + depends on I2C
> + select MFD_CORE
> + select REGMAP
> + help
Your REGMAP select here strangely indents with spaces, while the rest
of your kconfig attributes (and this file) are using a tab.
- Julian Braha
^ permalink raw reply
* [PATCH] arm64: mm: When logging data aborts only decode Xs when ISV=1
From: Mark Brown @ 2026-07-02 19:13 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon; +Cc: linux-arm-kernel, linux-kernel, Mark Brown
When logging the decode of a data abort we currently unconditionally decode
and display Xs. Currently the only defined non-RES0 values for this field
are for cases where ISV=1, move the decode of Xs into our existing check
for ISV=1. This avoids potential confusion if some other use is assigned to
these bits for ISV=0 cases in future, or misleading someone into thinking
there is a meaningful value there with currently defined architecture.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/mm/fault.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 85e23388f9bb..0b52557652be 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -76,6 +76,8 @@ static void data_abort_decode(unsigned long esr)
pr_alert(" SF = %lu, AR = %lu\n",
(esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
(esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
+ pr_alert(" Xs = %llu\n",
+ (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT);
} else {
pr_alert(" ISV = 0, ISS = 0x%08lx, ISS2 = 0x%08lx\n",
esr & ESR_ELx_ISS_MASK, iss2);
@@ -87,11 +89,10 @@ static void data_abort_decode(unsigned long esr)
(iss2 & ESR_ELx_TnD) >> ESR_ELx_TnD_SHIFT,
(iss2 & ESR_ELx_TagAccess) >> ESR_ELx_TagAccess_SHIFT);
- pr_alert(" GCS = %ld, Overlay = %lu, DirtyBit = %lu, Xs = %llu\n",
+ pr_alert(" GCS = %ld, Overlay = %lu, DirtyBit = %lu\n",
(iss2 & ESR_ELx_GCS) >> ESR_ELx_GCS_SHIFT,
(iss2 & ESR_ELx_Overlay) >> ESR_ELx_Overlay_SHIFT,
- (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT,
- (iss2 & ESR_ELx_Xs_MASK) >> ESR_ELx_Xs_SHIFT);
+ (iss2 & ESR_ELx_DirtyBit) >> ESR_ELx_DirtyBit_SHIFT);
}
static void mem_abort_decode(unsigned long esr)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260618-arm64-xs-decode-aa1316410455
Best regards,
--
Mark Brown <broonie@kernel.org>
^ permalink raw reply related
* Re: [PATCH 1/3] dt-bindings: soc: apple: Add bindings for apple PMGR misc controls
From: Conor Dooley @ 2026-07-02 19:18 UTC (permalink / raw)
To: Sasha Finkelstein
Cc: Sven Peter, Janne Grunau, Neal Gompa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, asahi, linux-arm-kernel,
devicetree, linux-kernel
In-Reply-To: <20260702-pmgr-misc-v1-1-4f075a3a95c1@chaosmail.tech>
[-- Attachment #1: Type: text/plain, Size: 3293 bytes --]
On Thu, Jul 02, 2026 at 02:06:26PM +0200, Sasha Finkelstein wrote:
> Certain Apple SoCs include additional PMGR power states that are
> controlled via a different "misc" control block. On existing SoCs, this
> includes the fabric and memory controller state.
>
> Signed-off-by: Sasha Finkelstein <k@chaosmail.tech>
> ---
> Documentation/devicetree/bindings/soc/apple/apple,t6000-pmgr-misc.yaml | 45 +++++++++++++++++++++++++++++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 46 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/apple/apple,t6000-pmgr-misc.yaml b/Documentation/devicetree/bindings/soc/apple/apple,t6000-pmgr-misc.yaml
> new file mode 100644
> index 000000000000..30abedc67fa4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/apple/apple,t6000-pmgr-misc.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/apple/apple,t6000-pmgr-misc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Apple SoC PMGR Misc Power States
> +
> +maintainers:
> + - Sasha Finkelstein <k@chaosmail.tech>
> +
> +description: |
> + Certain Apple SoCs include additional PMGR power states that are controlled
> + via a different "misc" control block. On existing SoCs, this includes the
> + fabric and memory controller state.
Are t6000 and t6020 the "certain Apple SoCs"? I assume so. The bit about
"existing SoCs" is confusing in a binding (although it would be ok in the
commit message), because you run into language semantics that imply that
this sentence is about devices to the ones you're addressing here. I
think you can just do s/. On existing SoCs//. And add an s to the final
"state" to make it "states".
> +
> +properties:
> + compatible:
> + enum:
> + - apple,t6000-pmgr-misc
> + - apple,t6020-pmgr-misc
> +
> + reg:
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: fabric-ps
> + - const: dcs-ps
"dcs" means memory controller then?
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pmgr_misc: power-management@8e20c000 {
If there's a new version, drop the unused label here please.
> + compatible = "apple,t6000-pmgr-misc";
> + reg = <0x8e20c000 0x400>,
> + <0x8e20c800 0x400>;
> + reg-names = "fabric-ps", "dcs-ps";
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 15011f5752a9..5a29bb86499f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2607,6 +2607,7 @@ F: Documentation/devicetree/bindings/power/apple*
> F: Documentation/devicetree/bindings/power/reset/apple,smc-reboot.yaml
> F: Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml
> F: Documentation/devicetree/bindings/rtc/apple,smc-rtc.yaml
> +F: Documentation/devicetree/bindings/soc/apple/apple,t6000-pmgr-misc.yaml
> F: Documentation/devicetree/bindings/spi/apple,spi.yaml
> F: Documentation/devicetree/bindings/spmi/apple,spmi.yaml
> F: Documentation/devicetree/bindings/usb/apple,dwc3.yaml
>
> --
> 2.55.0
>
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