* [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC
@ 2024-10-30 18:58 Jishnu Prakash
2024-10-30 18:58 ` [PATCH V4 1/4] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder Jishnu Prakash
` (4 more replies)
0 siblings, 5 replies; 26+ messages in thread
From: Jishnu Prakash @ 2024-10-30 18:58 UTC (permalink / raw)
To: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, dmitry.baryshkov, konrad.dybcio, daniel.lezcano, sboyd,
quic_subbaram, quic_collinsd, quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers, Jishnu Prakash
PMIC5 Gen3 has a similar ADC architecture to that on PMIC5 Gen2,
with all SW communication to ADC going through PMK8550 which
communicates with other PMICs through PBS. The major difference is
that the register interface used here is that of an SDAM present on
PMK8550, rather than a dedicated ADC peripheral. There may be more than one
SDAM used for ADC5 Gen3. Each ADC SDAM has eight channels, each of which may
be used for either immediate reads (same functionality as previous PMIC5 and
PMIC5 Gen2 ADC peripherals) or recurring measurements (same as PMIC5 and PMIC5
Gen2 ADC_TM functionality). In this case, we have VADC and ADC_TM functionality
combined into the same driver.
Patch 1 is a cleanup, to move the QCOM ADC dt-bindings files from
dt-bindings/iio to dt-bindings/iio/adc folder, as they are
specifically for ADC devices. It also fixes all compilation errors
with this change in driver and devicetree files and similar errors
in documentation for dtbinding check.
Patch 2 adds bindings for ADC5 Gen3 peripheral.
Patch 3 adds the main driver for ADC5 Gen3.
Patch 4 adds the auxiliary thermal driver which supports the ADC_TM
functionality of ADC5 Gen3.
Changes since v3:
- Updated files affected by adc file path change in /arch/arm folder,
which were missed earlier.
- Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file
instead of adding separate file and addressed reviewer comments for all bindings.
- Addressed review comments in driver patch. Split out TM functionality into
auxiliary driver in separate patch and added required changes in main driver.
- Link to v3: https://lore.kernel.org/all/20231231171237.3322376-1-quic_jprakash@quicinc.com/
Changes since v2:
- Reordered patches to keep cleanup change for ADC files first.
- Moved ADC5 Gen3 documentation into a separate file
Changes since v1:
- Dropped patches 1-5 for changing 'ADC7' peripheral name to 'ADC5 Gen2'.
- Addressed reviewer comments for binding and driver patches for ADC5 Gen3.
- Combined patches 8-11 into a single patch as requested by reviewers to make
the change clearer and made all fixes required in same patch.
Jishnu Prakash (4):
dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder
dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
iio: adc: Add support for QCOM PMIC5 Gen3 ADC
thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
.../bindings/iio/adc/qcom,spmi-vadc.yaml | 226 +++++-
.../bindings/mfd/qcom,spmi-pmic.yaml | 2 +-
.../bindings/thermal/qcom-spmi-adc-tm-hc.yaml | 2 +-
.../bindings/thermal/qcom-spmi-adc-tm5.yaml | 6 +-
arch/arm/boot/dts/qcom/pm8226.dtsi | 2 +-
arch/arm/boot/dts/qcom/pm8941.dtsi | 2 +-
arch/arm/boot/dts/qcom/pma8084.dtsi | 2 +-
arch/arm/boot/dts/qcom/pmx55.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm4125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm7250b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8953.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi632.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +-
.../boot/dts/qcom/qcm6490-fairphone-fp5.dts | 4 +-
.../boot/dts/qcom/qcm6490-shift-otter.dts | 4 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 2 +-
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 6 +-
.../boot/dts/qcom/sm7225-fairphone-fp4.dts | 2 +-
.../boot/dts/qcom/sm7325-nothing-spacewar.dts | 6 +-
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 8 +-
drivers/iio/adc/Kconfig | 25 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/qcom-spmi-adc5-gen3.c | 724 ++++++++++++++++++
drivers/iio/adc/qcom-spmi-adc5.c | 2 +-
drivers/iio/adc/qcom-spmi-vadc.c | 2 +-
drivers/thermal/qcom/Kconfig | 11 +
drivers/thermal/qcom/Makefile | 1 +
drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 489 ++++++++++++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 46 ++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 85 ++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 +
.../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 52 ++
.../iio/{ => adc}/qcom,spmi-adc7-pm7325.h | 2 +-
.../iio/{ => adc}/qcom,spmi-adc7-pm8350.h | 2 +-
.../iio/{ => adc}/qcom,spmi-adc7-pm8350b.h | 2 +-
.../iio/{ => adc}/qcom,spmi-adc7-pmk8350.h | 2 +-
.../iio/{ => adc}/qcom,spmi-adc7-pmr735a.h | 2 +-
.../iio/{ => adc}/qcom,spmi-adc7-pmr735b.h | 2 +-
.../iio/{ => adc}/qcom,spmi-adc7-smb139x.h | 2 +-
.../iio/{ => adc}/qcom,spmi-vadc.h | 81 ++
include/linux/iio/adc/qcom-adc5-gen3-common.h | 233 ++++++
60 files changed, 2032 insertions(+), 82 deletions(-)
create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c
create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm7325.h (98%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350.h (98%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350b.h (99%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmk8350.h (97%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735a.h (95%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735b.h (95%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h (93%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h (77%)
create mode 100644 include/linux/iio/adc/qcom-adc5-gen3-common.h
base-commit: 6fb2fa9805c501d9ade047fc511961f3273cdcb5
--
2.25.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH V4 1/4] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder
2024-10-30 18:58 [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Jishnu Prakash
@ 2024-10-30 18:58 ` Jishnu Prakash
2024-10-30 20:20 ` Rob Herring (Arm)
2024-10-30 18:58 ` [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Jishnu Prakash
` (3 subsequent siblings)
4 siblings, 1 reply; 26+ messages in thread
From: Jishnu Prakash @ 2024-10-30 18:58 UTC (permalink / raw)
To: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, dmitry.baryshkov, konrad.dybcio, daniel.lezcano, sboyd,
quic_subbaram, quic_collinsd, quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers, Jishnu Prakash,
Rob Herring
There are several files containing QCOM ADC macros for channel names
right now in the include/dt-bindings/iio folder. Since all of these
are specifically for adc, move the files to the
include/dt-bindings/iio/adc folder.
Also update all affected devicetree and driver files to fix compilation
errors seen with this move and update documentation files to fix
dtbinding check errors for the same.
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
---
Changes since v3:
- Updated files affected by adc file path change in /arch/arm, which
were missed earlier. Updated some more new devicetree files requiring
this change in /arch/arm64.
Changes since v2:
- Updated some more new devicetree files requiring this change.
.../devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml | 8 ++++----
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 2 +-
.../devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml | 2 +-
.../devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml | 6 +++---
arch/arm/boot/dts/qcom/pm8226.dtsi | 2 +-
arch/arm/boot/dts/qcom/pm8941.dtsi | 2 +-
arch/arm/boot/dts/qcom/pma8084.dtsi | 2 +-
arch/arm/boot/dts/qcom/pmx55.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm4125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm6150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm7250b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8953.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi632.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmi8950.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pmp8074.dtsi | 2 +-
arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +-
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 4 ++--
arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 4 ++--
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 2 +-
.../arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 6 +++---
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 2 +-
arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts | 6 +++---
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 8 ++++----
drivers/iio/adc/qcom-spmi-adc5.c | 2 +-
drivers/iio/adc/qcom-spmi-vadc.c | 2 +-
include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm7325.h | 2 +-
include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350.h | 2 +-
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350b.h | 2 +-
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmk8350.h | 2 +-
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735a.h | 2 +-
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735b.h | 2 +-
.../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h | 2 +-
include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h | 0
49 files changed, 63 insertions(+), 63 deletions(-)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm7325.h (98%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350.h (98%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350b.h (99%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmk8350.h (97%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735a.h (95%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735b.h (95%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h (93%)
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h (100%)
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
index c28db0d635a0..a4f72c0c1ec6 100644
--- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -70,9 +70,9 @@ patternProperties:
maxItems: 1
description: |
ADC channel number.
- See include/dt-bindings/iio/qcom,spmi-vadc.h
+ See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
For PMIC7 ADC, the channel numbers are specified separately per PMIC
- in the PMIC-specific files in include/dt-bindings/iio/.
+ in the PMIC-specific files in include/dt-bindings/iio/adc.
label:
description: |
@@ -276,8 +276,8 @@ examples:
};
- |
- #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
- #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>
pmic {
diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
index a2b2fbf77d5c..eed4f6d3c889 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
@@ -274,7 +274,7 @@ examples:
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/iio/qcom,spmi-vadc.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/spmi/spmi.h>
pmic@0 {
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml
index bfad8130a042..65b8c8cf802f 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml
@@ -110,7 +110,7 @@ unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/iio/qcom,spmi-vadc.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
pmic {
diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
index 4470a5942fb2..5d19a82b0319 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml
@@ -163,7 +163,7 @@ unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/iio/qcom,spmi-vadc.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
pmic {
@@ -204,8 +204,8 @@ examples:
};
- |
- #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
- #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>
pmic {
diff --git a/arch/arm/boot/dts/qcom/pm8226.dtsi b/arch/arm/boot/dts/qcom/pm8226.dtsi
index 2fd4f135ed84..774120aa50bc 100644
--- a/arch/arm/boot/dts/qcom/pm8226.dtsi
+++ b/arch/arm/boot/dts/qcom/pm8226.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: BSD-3-Clause
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm/boot/dts/qcom/pm8941.dtsi b/arch/arm/boot/dts/qcom/pm8941.dtsi
index aca0052a02b7..d995cc6eaebf 100644
--- a/arch/arm/boot/dts/qcom/pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom/pm8941.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm/boot/dts/qcom/pma8084.dtsi b/arch/arm/boot/dts/qcom/pma8084.dtsi
index 309f5256754b..f8790bbc225e 100644
--- a/arch/arm/boot/dts/qcom/pma8084.dtsi
+++ b/arch/arm/boot/dts/qcom/pma8084.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm/boot/dts/qcom/pmx55.dtsi b/arch/arm/boot/dts/qcom/pmx55.dtsi
index da0851173c69..af05ec5a009c 100644
--- a/arch/arm/boot/dts/qcom/pmx55.dtsi
+++ b/arch/arm/boot/dts/qcom/pmx55.dtsi
@@ -5,7 +5,7 @@
* Copyright (c) 2020, Linaro Limited
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm4125.dtsi b/arch/arm64/boot/dts/qcom/pm4125.dtsi
index cf8c822e80ce..db175a55035c 100644
--- a/arch/arm64/boot/dts/qcom/pm4125.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm4125.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2023, Linaro Ltd
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi
index d0db28336fa9..2bc669e8763b 100644
--- a/arch/arm64/boot/dts/qcom/pm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi
index 59524609fb1e..24fbfee8de79 100644
--- a/arch/arm64/boot/dts/qcom/pm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
index 334f976f1154..5c0ae7a06bd0 100644
--- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi
index 156b2ddff0dc..0ae38647ec49 100644
--- a/arch/arm64/boot/dts/qcom/pm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2020, Konrad Dybcio
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi
index 0094e0ef058b..38f329712079 100644
--- a/arch/arm64/boot/dts/qcom/pm660l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi
@@ -3,7 +3,7 @@
* Copyright (c) 2020, Konrad Dybcio
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
index 0761e6b5fd8d..6ad46722ae38 100644
--- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi
@@ -3,7 +3,7 @@
* Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com>
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
index a74a7ff660d2..206077d09d48 100644
--- a/arch/arm64/boot/dts/qcom/pm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
@@ -7,7 +7,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/ {
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
index 3f7b0b6a1d10..5192ab94e75e 100644
--- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi
@@ -4,7 +4,7 @@
* Copyright (c) 2019, Linaro Limited
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
index 3911d6d0d2e2..7822214f07b0 100644
--- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi
@@ -4,7 +4,7 @@
* Copyright (c) 2019, Linaro Limited
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index f8e4829ff7f7..3a709095cda7 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi
index ed72c6101813..c1462d659ff2 100644
--- a/arch/arm64/boot/dts/qcom/pm8950.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi
@@ -5,7 +5,7 @@
* Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org>
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi
index 64258505f9ba..9427062b8af5 100644
--- a/arch/arm64/boot/dts/qcom/pm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi
index 353e4a6bd088..26cbcfd06d05 100644
--- a/arch/arm64/boot/dts/qcom/pm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi
index 3ecb330590e5..b948b98835a9 100644
--- a/arch/arm64/boot/dts/qcom/pm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* Copyright 2018 Google LLC. */
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi
index 8c899d148e46..eff176851b83 100644
--- a/arch/arm64/boot/dts/qcom/pmi632.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi
@@ -3,7 +3,7 @@
* Copyright (C) 2023 Luca Weiss <luca@z3ntu.xyz>
*/
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
index 4aff437263a2..051c995e9f2e 100644
--- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019, AngeloGioacchino Del Regno <kholk11@gmail.com>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
index 5084de66fc46..3dd3adfa096b 100644
--- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi
@@ -6,7 +6,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/ {
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
index 0d0a846ac8d9..9f3e4121d834 100644
--- a/arch/arm64/boot/dts/qcom/pmp8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
&spmi_bus {
pmic@0 {
diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi
index 3f9100c7eff4..86c17094a92a 100644
--- a/arch/arm64/boot/dts/qcom/pms405.dtsi
+++ b/arch/arm64/boot/dts/qcom/pms405.dtsi
@@ -5,7 +5,7 @@
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
index fdc62f1b1c5a..b34c900439b9 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
@@ -9,8 +9,8 @@
#define PM7250B_SID 8
#define PM7250B_SID1 9
-#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
index 4667e47a74bc..f376dbaeed2d 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts
@@ -9,8 +9,8 @@
#define PM7250B_SID 8
#define PM7250B_SID1 9
-#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index b5fe7356be48..1dd4aa300f7f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -7,7 +7,7 @@
/dts-v1/;
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h>
#include "sc7280-idp.dtsi"
#include "pmr735a.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 7370aa0dbf0e..00d68a9588d3 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -5,7 +5,7 @@
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "sc7280.dtsi"
#include "pm7325.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
index 7d1d5bbbbbd9..8fcd3e1bb815 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
@@ -11,8 +11,8 @@
* Copyright 2022 Google LLC.
*/
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
index 451c9b984f1f..ed1fcfdc3584 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
@@ -7,7 +7,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/ {
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 83208b10f994..839204918fd4 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
index 1e3babf2e40d..080ae9e037a2 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
@@ -3,9 +3,9 @@
* Copyright (c) 2022, Linaro Limited
*/
-#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
index 2ee2561b57b1..b8609ad1bd86 100644
--- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
+++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
@@ -14,7 +14,7 @@
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts
index a5cda478bd78..5308b1ef85b6 100644
--- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts
+++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts
@@ -8,9 +8,9 @@
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
index 67443822653d..88f394dc4867 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts
@@ -6,10 +6,10 @@
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include "sm8450.dtsi"
#include "pm8350.dtsi"
diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c
index af3c2f659f5e..389454edbf75 100644
--- a/drivers/iio/adc/qcom-spmi-adc5.c
+++ b/drivers/iio/adc/qcom-spmi-adc5.c
@@ -20,7 +20,7 @@
#include <linux/regmap.h>
#include <linux/slab.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#define ADC5_USR_REVISION1 0x0
#define ADC5_USR_STATUS1 0x8
diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c
index 00a7f0982025..e4878770f88c 100644
--- a/drivers/iio/adc/qcom-spmi-vadc.c
+++ b/drivers/iio/adc/qcom-spmi-vadc.c
@@ -20,7 +20,7 @@
#include <linux/slab.h>
#include <linux/log2.h>
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/* VADC register and bit definitions */
#define VADC_REVISION2 0x1
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h
similarity index 98%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h
index 96908014e09e..f0ab57078ca4 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm7325.h
@@ -10,7 +10,7 @@
#define PM7325_SID 1
#endif
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/* ADC channels for PM7325_ADC for PMIC7 */
#define PM7325_ADC7_REF_GND (PM7325_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h
similarity index 98%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h
index 5d98f7d48a1e..ef818248ec8c 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350.h
@@ -6,7 +6,7 @@
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/* ADC channels for PM8350_ADC for PMIC7 */
#define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h
similarity index 99%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h
index 57c7977666d3..d841bf00b7b0 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pm8350b.h
@@ -10,7 +10,7 @@
#define PM8350B_SID 3
#endif
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/* ADC channels for PM8350B_ADC for PMIC7 */
#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h
similarity index 97%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h
index 3d1a41a22cef..161b211ec126 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h
@@ -10,7 +10,7 @@
#define PMK8350_SID 0
#endif
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/* ADC channels for PMK8350_ADC for PMIC7 */
#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h
similarity index 95%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h
index c5adfa82b20d..fedc9e3882b8 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735a.h
@@ -10,7 +10,7 @@
#define PMR735A_SID 4
#endif
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/* ADC channels for PMR735A_ADC for PMIC7 */
#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
similarity index 95%
rename from include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
index fdb8dd9ae541..812f33872e5e 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-pmr735b.h
@@ -10,7 +10,7 @@
#define PMR735B_SID 5
#endif
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
/* ADC channels for PMR735B_ADC for PMIC7 */
#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND)
diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
similarity index 93%
rename from include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h
rename to include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
index c0680d1285cf..750a526af2c1 100644
--- a/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc7-smb139x.h
@@ -6,7 +6,7 @@
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
-#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
#define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP)
#define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB)
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
similarity index 100%
rename from include/dt-bindings/iio/qcom,spmi-vadc.h
rename to include/dt-bindings/iio/adc/qcom,spmi-vadc.h
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-30 18:58 [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Jishnu Prakash
2024-10-30 18:58 ` [PATCH V4 1/4] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder Jishnu Prakash
@ 2024-10-30 18:58 ` Jishnu Prakash
2024-10-30 20:20 ` Rob Herring (Arm)
` (2 more replies)
2024-10-30 18:58 ` [PATCH V4 3/4] " Jishnu Prakash
` (2 subsequent siblings)
4 siblings, 3 replies; 26+ messages in thread
From: Jishnu Prakash @ 2024-10-30 18:58 UTC (permalink / raw)
To: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, dmitry.baryshkov, konrad.dybcio, daniel.lezcano, sboyd,
quic_subbaram, quic_collinsd, quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers, Jishnu Prakash
For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
going through PBS(Programmable Boot Sequence) firmware through a single
register interface. This interface is implemented on an SDAM (Shared
Direct Access Memory) peripheral on the master PMIC PMK8550 rather
than a dedicated ADC peripheral.
Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
channels and virtual channels (combination of ADC channel number and
PMIC SID number) per PMIC, to be used by clients of this device.
Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
---
Changes since v3:
- Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file
instead of adding separate file and updated top-level constraints in documentation
file based on discussion with reviewers.
- Dropped default SID definitions.
- Addressed other reviewer comments.
Changes since v2:
- Moved ADC5 Gen3 documentation into a separate new file.
Changes since v1:
- Updated properties separately for all compatibles to clarify usage
of new properties and updates in usage of old properties for ADC5 Gen3.
- Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
mentioning this convention.
- Used predefined channel IDs in individual PMIC channel definitions
instead of numeric IDs.
- Addressed other comments from reviewers.
.../bindings/iio/adc/qcom,spmi-vadc.yaml | 220 ++++++++++++++++--
.../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 46 ++++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 85 +++++++
.../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++
.../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 52 +++++
include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++
6 files changed, 486 insertions(+), 20 deletions(-)
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
index a4f72c0c1ec6..e6e1795af886 100644
--- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -13,8 +13,12 @@ maintainers:
description: |
SPMI PMIC voltage ADC (VADC) provides interface to clients to read
voltage. The VADC is a 15-bit sigma-delta ADC.
- SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read
- voltage. The VADC is a 16-bit sigma-delta ADC.
+ SPMI PMIC5/PMIC7/PMIC5 Gen3 voltage ADC voltage ADC (ADC) provides
+ interface to clients to read voltage. The VADC is a 16-bit sigma-delta ADC.
+ Note that PMIC7 ADC is the generation between PMIC5 and PMIC5 Gen3 ADC,
+ it can be considered like PMIC5 Gen2.
+ In addition, PMIC5 Gen3 ADC also performs the same thermal monitoring function
+ as the existing ADC_TM devices.
properties:
compatible:
@@ -23,14 +27,20 @@ properties:
- const: qcom,pms405-adc
- const: qcom,spmi-adc-rev2
- enum:
- - qcom,spmi-vadc
- - qcom,spmi-adc5
- qcom,spmi-adc-rev2
+ - qcom,spmi-adc5
+ - qcom,spmi-adc5-gen3
- qcom,spmi-adc7
+ - qcom,spmi-vadc
reg:
- description: VADC base address in the SPMI PMIC register map
- maxItems: 1
+ description:
+ For compatible properties "qcom,spmi-vadc", "qcom,spmi-adc5", "qcom,spmi-adc-rev2"
+ and "qcom,spmi-adc7", reg is the VADC base address in the SPMI PMIC register map.
+ For compatible property "qcom,spmi-adc5-gen3", each reg corresponds to an SDAM
+ peripheral base address that is being used for ADC functionality.
+ minItems: 1
+ maxItems: 2
'#address-cells':
const: 1
@@ -38,20 +48,28 @@ properties:
'#size-cells':
const: 0
+ "#thermal-sensor-cells":
+ const: 1
+ description:
+ Number of cells required to uniquely identify the thermal sensors.
+ For compatible property "qcom,spmi-adc5-gen3", this property is
+ required for if any channels under it are used for ADC_TM.
+ Since we have multiple sensors this is set to 1.
+
'#io-channel-cells':
const: 1
interrupts:
- maxItems: 1
description:
End of conversion interrupt.
+ For compatible property "qcom,spmi-adc5-gen3", interrupts are defined
+ for each SDAM being used.
+ minItems: 1
+ maxItems: 2
-required:
- - compatible
- - reg
- - '#address-cells'
- - '#size-cells'
- - '#io-channel-cells'
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
patternProperties:
"^channel@[0-9a-f]+$":
@@ -71,8 +89,8 @@ patternProperties:
description: |
ADC channel number.
See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
- For PMIC7 ADC, the channel numbers are specified separately per PMIC
- in the PMIC-specific files in include/dt-bindings/iio/adc.
+ For PMIC7 and PMIC5 Gen3 ADC, the channel numbers are specified separately
+ per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
label:
description: |
@@ -113,11 +131,11 @@ patternProperties:
channel calibration. If property is not found, channel will be
calibrated with 0.625V and 1.25V reference channels, also
known as absolute calibration.
- - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
- "qcom,spmi-adc-rev2", if this property is specified VADC will use
- the VDD reference (1.875V) and GND for channel calibration. If
- property is not found, channel will be calibrated with 0V and 1.25V
- reference channels, also known as absolute calibration.
+ - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7",
+ "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property is
+ specified VADC will use the VDD reference (1.875V) and GND for channel
+ calibration. If property is not found, channel will be calibrated with
+ 0V and 1.25V reference channels, also known as absolute calibration.
type: boolean
qcom,hw-settle-time:
@@ -135,9 +153,24 @@ patternProperties:
from the ADC that is an average of multiple samples. The value
selected is 2^(value).
+ qcom,adc-tm:
+ description:
+ Indicates if ADC_TM monitoring is done on this channel.
+ Defined for compatible property "qcom,spmi-adc5-gen3".
+ This is the same functionality as in the existing QCOM ADC_TM
+ device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
+ type: boolean
+
required:
- reg
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - '#io-channel-cells'
+
allOf:
- if:
properties:
@@ -146,6 +179,15 @@ allOf:
const: qcom,spmi-vadc
then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 1
+ interrupts:
+ minItems: 1
+ maxItems: 1
+ "#thermal-sensor-cells": false
+ interrupt-names: false
patternProperties:
"^channel@[0-9a-f]+$":
properties:
@@ -162,6 +204,8 @@ allOf:
enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 ]
default: 1
+ qcom,adc-tm: false
+
- if:
properties:
compatible:
@@ -169,6 +213,15 @@ allOf:
const: qcom,spmi-adc-rev2
then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 1
+ interrupts:
+ minItems: 1
+ maxItems: 1
+ "#thermal-sensor-cells": false
+ interrupt-names: false
patternProperties:
"^channel@[0-9a-f]+$":
properties:
@@ -185,6 +238,8 @@ allOf:
enum: [ 1, 2, 4, 8, 16 ]
default: 1
+ qcom,adc-tm: false
+
- if:
properties:
compatible:
@@ -192,6 +247,15 @@ allOf:
const: qcom,spmi-adc5
then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 1
+ interrupts:
+ minItems: 1
+ maxItems: 1
+ "#thermal-sensor-cells": false
+ interrupt-names: false
patternProperties:
"^channel@[0-9a-f]+$":
properties:
@@ -208,6 +272,8 @@ allOf:
enum: [ 1, 2, 4, 8, 16 ]
default: 1
+ qcom,adc-tm: false
+
- if:
properties:
compatible:
@@ -215,6 +281,59 @@ allOf:
const: qcom,spmi-adc7
then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 1
+ interrupts:
+ minItems: 1
+ maxItems: 1
+ "#thermal-sensor-cells": false
+ interrupt-names: false
+ patternProperties:
+ "^channel@[0-9a-f]+$":
+ properties:
+ qcom,decimation:
+ enum: [ 85, 340, 1360 ]
+ default: 1360
+
+ qcom,hw-settle-time:
+ enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
+ 8000, 16000, 32000, 64000, 128000 ]
+ default: 15
+
+ qcom,avg-samples:
+ enum: [ 1, 2, 4, 8, 16 ]
+ default: 1
+
+ qcom,adc-tm: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,spmi-adc5-gen3
+
+ then:
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: SDAM0 base address in the SPMI PMIC register map
+ - description: SDAM1 base address
+ interrupts:
+ minItems: 1
+ items:
+ - description: SDAM0 end of conversion (EOC) interrupt
+ - description: SDAM1 EOC interrupt
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: adc-sdam0
+ - const: adc-sdam1
+ required:
+ - interrupts
+ - interrupt-names
patternProperties:
"^channel@[0-9a-f]+$":
properties:
@@ -307,3 +426,64 @@ examples:
};
};
};
+
+ - |
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h>
+ #include <dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@9000 {
+ compatible = "qcom,spmi-adc5-gen3";
+ reg = <0x9000>, <0x9100>;
+ interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "adc-sdam0", "adc-sdam1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
+
+ /* PMK8550 Channel nodes */
+ channel@3 {
+ reg = <PMK8550_ADC5_GEN3_DIE_TEMP(0)>;
+ label = "pmk8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ channel@44 {
+ reg = <PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU(0)>;
+ label = "pmk8550_xo_therm";
+ qcom,pre-scaling = <1 1>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,adc-tm;
+ };
+
+ /* PM8550 Channel nodes */
+ channel@103 {
+ reg = <PM8550_ADC5_GEN3_DIE_TEMP(1)>;
+ label = "pm8550_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ /* PM8550B Channel nodes */
+ channel@78f {
+ reg = <PM8550B_ADC5_GEN3_VBAT_SNS_QBG(7)>;
+ label = "pm8550b_vbat_sns_qbg";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ /* PM8550VS_C Channel nodes */
+ channel@203 {
+ reg = <PM8550VS_ADC5_GEN3_DIE_TEMP(2)>;
+ label = "pm8550vs_c_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+ };
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
new file mode 100644
index 000000000000..21cc607ce40e
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+/* ADC channels for PM8550_ADC for PMIC5 Gen3 */
+#define PM8550_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
+#define PM8550_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
+#define PM8550_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8550_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PM8550_ADC5_GEN3_AMUX_THM1(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM2(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM3(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM4(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM5(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM)
+#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM)
+#define PM8550_ADC5_GEN3_AMUX1_GPIO3(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO)
+#define PM8550_ADC5_GEN3_AMUX2_GPIO4(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO)
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO)
+
+/* 100k pull-up */
+#define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU)
+
+/* 1/3 Divider */
+#define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3)
+#define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_DIV3)
+
+#define PM8550_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
new file mode 100644
index 000000000000..ae5677a26434
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+/* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
+#define PM8550B_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
+#define PM8550B_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
+#define PM8550B_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8550B_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO)
+
+#define PM8550B_ADC5_GEN3_CHG_TEMP(sid) ((sid) << 8 | ADC5_GEN3_CHG_TEMP)
+#define PM8550B_ADC5_GEN3_USB_SNS_V_16(sid) ((sid) << 8 | ADC5_GEN3_USB_SNS_V_16)
+#define PM8550B_ADC5_GEN3_VIN_DIV16_MUX(sid) ((sid) << 8 | ADC5_GEN3_VIN_DIV16_MUX)
+#define PM8550B_ADC5_GEN3_VREF_BAT_THERM(sid) ((sid) << 8 | ADC5_GEN3_VREF_BAT_THERM)
+#define PM8550B_ADC5_GEN3_IIN_FB(sid) ((sid) << 8 | ADC5_GEN3_IIN_FB)
+#define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE(sid) ((sid) << 8 | ADC5_GEN3_TEMP_ALARM_LITE)
+#define PM8550B_ADC5_GEN3_SMB_IIN(sid) ((sid) << 8 | ADC5_GEN3_IIN_SMB)
+#define PM8550B_ADC5_GEN3_SMB_ICHG(sid) ((sid) << 8 | ADC5_GEN3_ICHG_SMB)
+#define PM8550B_ADC5_GEN3_ICHG_FB(sid) ((sid) << 8 | ADC5_GEN3_ICHG_FB)
+
+/* 30k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_30K_PU)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_30K_PU)
+
+/* 100k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_100K_PU)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_100K_PU)
+
+/* 400k pull-up */
+#define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_400K_PU)
+#define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_GPIO_400K_PU)
+
+/* 1/3 Divider */
+#define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_DIV3)
+#define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_GPIO_DIV3)
+#define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_GPIO_DIV3)
+
+#define PM8550B_ADC5_GEN3_VPH_PWR(sid) ((sid) << 8 | ADC5_GEN3_VPH_PWR)
+#define PM8550B_ADC5_GEN3_VBAT_SNS_QBG(sid) ((sid) << 8 | ADC5_GEN3_VBAT_SNS_QBG)
+#define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR(sid) ((sid) << 8 | ADC5_GEN3_VBAT_SNS_CHGR)
+#define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG(sid) ((sid) << 8 | ADC5_GEN3_VBAT_2S_MID_QBG)
+#define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR(sid) ((sid) << 8 | ADC5_GEN3_VBAT_2S_MID_CHGR)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
new file mode 100644
index 000000000000..c6d2857d5c0c
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
+#define PM8550VS_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
+#define PM8550VS_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
+#define PM8550VS_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8550VS_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PM8550VE_ADC5_GEN3_OFFSET_REF(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
+#define PM8550VE_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
+#define PM8550VE_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
+#define PM8550VE_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
new file mode 100644
index 000000000000..2e43f7e3acb8
--- /dev/null
+++ b/include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+/* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
+#define PMK8550_ADC5_GEN3_REF_GND(sid) ((sid) << 8 | ADC5_GEN3_REF_GND)
+#define PMK8550_ADC5_GEN3_1P25VREF(sid) ((sid) << 8 | ADC5_GEN3_1P25VREF)
+#define PMK8550_ADC5_GEN3_VREF_VADC(sid) ((sid) << 8 | ADC5_GEN3_VREF_VADC)
+#define PMK8550_ADC5_GEN3_DIE_TEMP(sid) ((sid) << 8 | ADC5_GEN3_DIE_TEMP)
+
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO)
+
+/* 30k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_30K_PU)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_30K_PU)
+
+/* 100k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_100K_PU)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_100K_PU)
+
+/* 400k pull-up */
+#define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX2_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX3_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX4_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX5_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX6_THM_400K_PU)
+#define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU(sid) ((sid) << 8 | ADC5_GEN3_AMUX1_GPIO_400K_PU)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */
diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
index ef07ecd4d585..ed786f6c3425 100644
--- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
+++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
@@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
+ *
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
@@ -300,4 +302,83 @@
#define ADC7_SBUx 0x94
#define ADC7_VBAT_2S_MID 0x96
+/* ADC channels for PMIC5 Gen3 */
+
+#define ADC5_GEN3_REF_GND 0x00
+#define ADC5_GEN3_1P25VREF 0x01
+#define ADC5_GEN3_VREF_VADC 0x02
+#define ADC5_GEN3_DIE_TEMP 0x03
+
+#define ADC5_GEN3_AMUX1_THM 0x04
+#define ADC5_GEN3_AMUX2_THM 0x05
+#define ADC5_GEN3_AMUX3_THM 0x06
+#define ADC5_GEN3_AMUX4_THM 0x07
+#define ADC5_GEN3_AMUX5_THM 0x08
+#define ADC5_GEN3_AMUX6_THM 0x09
+#define ADC5_GEN3_AMUX1_GPIO 0x0a
+#define ADC5_GEN3_AMUX2_GPIO 0x0b
+#define ADC5_GEN3_AMUX3_GPIO 0x0c
+#define ADC5_GEN3_AMUX4_GPIO 0x0d
+
+#define ADC5_GEN3_CHG_TEMP 0x10
+#define ADC5_GEN3_USB_SNS_V_16 0x11
+#define ADC5_GEN3_VIN_DIV16_MUX 0x12
+#define ADC5_GEN3_VREF_BAT_THERM 0x15
+#define ADC5_GEN3_IIN_FB 0x17
+#define ADC5_GEN3_TEMP_ALARM_LITE 0x18
+#define ADC5_GEN3_IIN_SMB 0x19
+#define ADC5_GEN3_ICHG_SMB 0x1b
+#define ADC5_GEN3_ICHG_FB 0xa1
+
+/* 30k pull-up1 */
+#define ADC5_GEN3_AMUX1_THM_30K_PU 0x24
+#define ADC5_GEN3_AMUX2_THM_30K_PU 0x25
+#define ADC5_GEN3_AMUX3_THM_30K_PU 0x26
+#define ADC5_GEN3_AMUX4_THM_30K_PU 0x27
+#define ADC5_GEN3_AMUX5_THM_30K_PU 0x28
+#define ADC5_GEN3_AMUX6_THM_30K_PU 0x29
+#define ADC5_GEN3_AMUX1_GPIO_30K_PU 0x2a
+#define ADC5_GEN3_AMUX2_GPIO_30K_PU 0x2b
+#define ADC5_GEN3_AMUX3_GPIO_30K_PU 0x2c
+#define ADC5_GEN3_AMUX4_GPIO_30K_PU 0x2d
+
+/* 100k pull-up2 */
+#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44
+#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45
+#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46
+#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47
+#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48
+#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49
+#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a
+#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b
+#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c
+#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d
+
+/* 400k pull-up3 */
+#define ADC5_GEN3_AMUX1_THM_400K_PU 0x64
+#define ADC5_GEN3_AMUX2_THM_400K_PU 0x65
+#define ADC5_GEN3_AMUX3_THM_400K_PU 0x66
+#define ADC5_GEN3_AMUX4_THM_400K_PU 0x67
+#define ADC5_GEN3_AMUX5_THM_400K_PU 0x68
+#define ADC5_GEN3_AMUX6_THM_400K_PU 0x69
+#define ADC5_GEN3_AMUX1_GPIO_400K_PU 0x6a
+#define ADC5_GEN3_AMUX2_GPIO_400K_PU 0x6b
+#define ADC5_GEN3_AMUX3_GPIO_400K_PU 0x6c
+#define ADC5_GEN3_AMUX4_GPIO_400K_PU 0x6d
+
+/* 1/3 Divider */
+#define ADC5_GEN3_AMUX1_GPIO_DIV3 0x8a
+#define ADC5_GEN3_AMUX2_GPIO_DIV3 0x8b
+#define ADC5_GEN3_AMUX3_GPIO_DIV3 0x8c
+#define ADC5_GEN3_AMUX4_GPIO_DIV3 0x8d
+
+#define ADC5_GEN3_VPH_PWR 0x8e
+#define ADC5_GEN3_VBAT_SNS_QBG 0x8f
+
+#define ADC5_GEN3_VBAT_SNS_CHGR 0x94
+#define ADC5_GEN3_VBAT_2S_MID_QBG 0x96
+#define ADC5_GEN3_VBAT_2S_MID_CHGR 0x9d
+
+#define ADC5_GEN3_OFFSET_EXT2 0xf8
+
#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V4 3/4] iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-30 18:58 [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Jishnu Prakash
2024-10-30 18:58 ` [PATCH V4 1/4] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder Jishnu Prakash
2024-10-30 18:58 ` [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Jishnu Prakash
@ 2024-10-30 18:58 ` Jishnu Prakash
2024-10-31 11:03 ` Krzysztof Kozlowski
2024-11-02 10:46 ` kernel test robot
2024-10-30 18:58 ` [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
2024-10-31 7:36 ` [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Krzysztof Kozlowski
4 siblings, 2 replies; 26+ messages in thread
From: Jishnu Prakash @ 2024-10-30 18:58 UTC (permalink / raw)
To: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, dmitry.baryshkov, konrad.dybcio, daniel.lezcano, sboyd,
quic_subbaram, quic_collinsd, quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers, Jishnu Prakash
The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2,
with all SW communication to ADC going through PMK8550 which
communicates with other PMICs through PBS.
One major difference is that the register interface used here is that
of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550.
There may be more than one SDAM used for ADC5 Gen3 and each has eight
channels, which may be used for either immediate reads (same functionality
as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements
(same as ADC_TM functionality).
By convention, we reserve the first channel of the first SDAM for all
immediate reads and use the remaining channels across all SDAMs for
ADC_TM monitoring functionality.
Add support for PMIC5 Gen3 ADC driver for immediate read functionality.
ADC_TM is implemented as an auxiliary thermal driver under this ADC
driver.
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
---
Changes since v3:
- Split out TM functionality into auxiliary driver in separate patch and
added required changes in main driver.
- Addressed other reviewer comments in main driver patch.
Changes since v1:
- Removed datashet_name usage and implemented read_label() function
- In probe, updated channel property in iio_chan_spec from individual
channel to virtual channel and set indexed property to 1, due to the
above change.
- Updated order of checks in ISR
- Removed the driver remove callback and replaced with callbacks in a
devm_add_action call in probe.
- Addressed other comments from reviewers.
drivers/iio/adc/Kconfig | 25 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/qcom-spmi-adc5-gen3.c | 724 ++++++++++++++++++
include/linux/iio/adc/qcom-adc5-gen3-common.h | 233 ++++++
4 files changed, 983 insertions(+)
create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c
create mode 100644 include/linux/iio/adc/qcom-adc5-gen3-common.h
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 849c90203071..11f8cb1de085 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -1165,6 +1165,31 @@ config QCOM_SPMI_ADC5
To compile this driver as a module, choose M here: the module will
be called qcom-spmi-adc5.
+config QCOM_SPMI_ADC5_GEN3
+ tristate "Qualcomm Technologies Inc. SPMI PMIC5 GEN3 ADC"
+ depends on SPMI && THERMAL
+ select REGMAP_SPMI
+ select QCOM_VADC_COMMON
+ help
+ This is the IIO Voltage PMIC5 Gen3 ADC driver for Qualcomm Technologies Inc. PMICs.
+
+ The driver supports reading multiple channels. The ADC is a 16-bit
+ sigma-delta ADC. The hardware supports calibrated results for
+ conversion requests and clients include reading phone power supply
+ voltage, on board system thermistors connected to the PMIC ADC,
+ PMIC die temperature, charger temperature, battery current, USB voltage
+ input and voltage signals connected to supported PMIC GPIO pins. The
+ hardware supports internal pull-up for thermistors and can choose between
+ a 30k, 100k or 400k ohm pull up using the ADC channels.
+
+ In addition, the same driver supports ADC thermal monitoring devices too.
+ They appear as thermal zones with multiple trip points. A thermal client sets
+ threshold temperature for both warm and cool trips and gets updated when a
+ threshold is reached.
+
+ To compile this driver as a module, choose M here: the module will
+ be called qcom-spmi-adc5-gen3.
+
config RCAR_GYRO_ADC
tristate "Renesas R-Car GyroADC driver"
depends on ARCH_RCAR_GEN2 || COMPILE_TEST
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index ee19afba62b7..1f8a02e608dd 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_PAC1934) += pac1934.o
obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o
obj-$(CONFIG_QCOM_SPMI_ADC5) += qcom-spmi-adc5.o
+obj-$(CONFIG_QCOM_SPMI_ADC5_GEN3) += qcom-spmi-adc5-gen3.o
obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
obj-$(CONFIG_QCOM_SPMI_RRADC) += qcom-spmi-rradc.o
obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o
diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-spmi-adc5-gen3.c
new file mode 100644
index 000000000000..41f7f6534745
--- /dev/null
+++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c
@@ -0,0 +1,724 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/iio/adc/qcom-adc5-gen3-common.h>
+#include <linux/iio/iio.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/slab.h>
+#include <linux/thermal.h>
+#include <linux/unaligned.h>
+
+#include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
+
+#define ADC5_GEN3_VADC_SDAM 0x0
+
+struct adc5_chip;
+
+/**
+ * @adc_tm: indicates TM type if the channel is used for TM measurements.
+ * @chip: pointer to top-level ADC device structure.
+ */
+
+struct adc5_channel_prop {
+ struct adc5_channel_common_prop common_props;
+ int adc_tm;
+ struct adc5_chip *chip;
+};
+
+/**
+ * struct adc5_chip - ADC private structure.
+ * @dev: SPMI ADC5 Gen3 device.
+ * @num_sdams: number of SDAMs (Shared Direct Access Memory Module) being used.
+ * @nchannels: number of ADC channels.
+ * @chan_props: array of ADC channel properties.
+ * @iio_chans: array of IIO channels specification.
+ * @complete: ADC result notification after interrupt is received.
+ * @lock: ADC lock for access to the peripheral, to prevent concurrent
+ * requests from multiple clients.
+ * @n_tm_channels: number of ADC channels used for TM measurements.
+ * @data: software configuration data.
+ */
+struct adc5_chip {
+ struct device *dev;
+ struct adc5_device_data dev_data;
+ unsigned int num_sdams;
+ unsigned int nchannels;
+ struct adc5_channel_prop *chan_props;
+ struct iio_chan_spec *iio_chans;
+ struct completion complete;
+ /*
+ * lock for access to the peripheral, to prevent concurrent
+ * requests from multiple clients.
+ */
+ struct mutex lock;
+ const struct adc5_data *data;
+ unsigned int n_tm_channels;
+ struct auxiliary_device *tm_aux;
+};
+
+static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data)
+{
+ u8 rslt[2];
+ int ret;
+
+ ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_CH_DATA0(0), rslt, 2);
+ if (ret)
+ return ret;
+
+ *data = get_unaligned_le16(rslt);
+
+ if (*data == ADC5_USR_DATA_CHECK) {
+ dev_err(adc->dev, "Invalid data:%#x\n", *data);
+ return -EINVAL;
+ }
+
+ dev_dbg(adc->dev, "voltage raw code:%#x\n", *data);
+
+ return 0;
+}
+
+#define ADC5_GEN3_READ_CONFIG_REGS 7
+
+static int adc5_gen3_configure(struct adc5_chip *adc, struct adc5_channel_common_prop *prop)
+{
+ u8 buf[ADC5_GEN3_READ_CONFIG_REGS];
+ u8 conv_req = 0;
+ int ret;
+
+ ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SID, buf, sizeof(buf));
+ if (ret)
+ return ret;
+
+ /* Write SID */
+ buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid);
+
+ /*
+ * Use channel 0 by default for immediate conversion and
+ * to indicate there is an actual conversion request
+ */
+ buf[1] = ADC5_GEN3_CHAN_CONV_REQ | 0;
+
+ buf[2] = ADC5_GEN3_TIME_IMMEDIATE;
+
+ /* Digital param selection */
+ adc5_gen3_update_dig_param(prop, &buf[3]);
+
+ /* Update fast average sample value */
+ buf[4] = FIELD_PREP(ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK, prop->avg_samples)
+ | ADC5_GEN3_FAST_AVG_CTL_EN;
+
+ /* Select ADC channel */
+ buf[5] = prop->channel;
+
+ /* Select HW settle delay for channel */
+ buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, prop->hw_settle_time);
+
+ reinit_completion(&adc->complete);
+
+ ret = adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SID, buf, sizeof(buf));
+ if (ret)
+ return ret;
+
+ conv_req = ADC5_GEN3_CONV_REQ_REQ;
+ return adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_CONV_REQ, &conv_req,
+ 1);
+}
+
+/*
+ * Worst case delay from PBS for conversion time can be
+ * up to 500ms, when PBS has timed out twice, once for
+ * the initial attempt and once for a retry of the same
+ * transaction.
+ */
+
+#define ADC5_GEN3_CONV_TIMEOUT_MS 501
+
+static int adc5_gen3_do_conversion(struct adc5_chip *adc,
+ struct adc5_channel_common_prop *prop, u16 *data_volt)
+{
+ unsigned long rc;
+ int ret;
+ u8 val;
+
+ guard(mutex)(&adc->lock);
+ ret = adc5_gen3_poll_wait_hs(&adc->dev_data, ADC5_GEN3_VADC_SDAM);
+ if (ret)
+ return ret;
+
+ ret = adc5_gen3_configure(adc, prop);
+ if (ret) {
+ dev_err(adc->dev, "ADC configure failed with %d\n", ret);
+ return ret;
+ }
+
+ /* No support for polling mode at present */
+ rc = wait_for_completion_timeout(&adc->complete,
+ msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS));
+ if (!rc) {
+ dev_err(adc->dev, "Reading ADC channel %s timed out\n",
+ prop->label);
+ return -ETIMEDOUT;
+ }
+
+ ret = adc5_gen3_read_voltage_data(adc, data_volt);
+ if (ret)
+ return ret;
+
+ val = BIT(0);
+ return adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_EOC_CLR, &val,
+ 1);
+}
+
+static irqreturn_t adc5_gen3_isr(int irq, void *dev_id)
+{
+ u8 status, tm_status[2], eoc_status, val;
+ struct adc_tm5_auxiliary_drv *adrv_tm;
+ struct adc5_chip *adc = dev_id;
+ struct auxiliary_device *adev;
+ int ret;
+
+ ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_STATUS1, &status, 1);
+ if (ret) {
+ dev_err(adc->dev, "adc read status1 failed with %d\n", ret);
+ return IRQ_HANDLED;
+ }
+
+ ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_EOC_STS, &eoc_status,
+ 1);
+ if (ret) {
+ dev_err(adc->dev, "adc read eoc status failed with %d\n", ret);
+ return IRQ_HANDLED;
+ }
+
+ if (status & ADC5_GEN3_STATUS1_CONV_FAULT) {
+ dev_err_ratelimited(adc->dev, "Unexpected conversion fault, status:%#x, eoc_status:%#x\n",
+ status, eoc_status);
+ val = ADC5_GEN3_CONV_ERR_CLR_REQ;
+ adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_CONV_ERR_CLR,
+ &val, 1);
+ return IRQ_HANDLED;
+ }
+
+ /* CHAN0 is the preconfigured channel for immediate conversion */
+ if (eoc_status & ADC5_GEN3_EOC_CHAN_0)
+ complete(&adc->complete);
+
+ ret = adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_TM_HIGH_STS,
+ tm_status, 2);
+ if (ret) {
+ dev_err(adc->dev, "adc read TM status failed with %d\n", ret);
+ return IRQ_HANDLED;
+ }
+
+ if (tm_status[0] || tm_status[1]) {
+ adev = adc->tm_aux;
+ if (!adev || !adev->dev.driver) {
+ dev_err(adc->dev, "adc_tm auxiliary device not initialized\n");
+ return IRQ_HANDLED;
+ }
+
+ adrv_tm = container_of(adev->dev.driver, struct adc_tm5_auxiliary_drv, adrv.driver);
+
+ if (adrv_tm && adrv_tm->tm_event_notify)
+ adrv_tm->tm_event_notify(adev);
+ else
+ dev_err(adc->dev, "adc_tm auxiliary driver not initialized\n");
+ }
+
+ dev_dbg(adc->dev, "Interrupt status:%#x, EOC status:%#x, high:%#x, low:%#x\n",
+ status, eoc_status, tm_status[0], tm_status[1]);
+
+ return IRQ_HANDLED;
+}
+
+static int adc5_gen3_fwnode_xlate(struct iio_dev *indio_dev,
+ const struct fwnode_reference_args *iiospec)
+{
+ struct adc5_chip *adc = iio_priv(indio_dev);
+ int i, v_channel;
+
+ for (i = 0; i < adc->nchannels; i++) {
+ v_channel = V_CHAN(adc->chan_props[i].common_props);
+ if (v_channel == iiospec->args[0])
+ return i;
+ }
+
+ return -ENOENT;
+}
+
+static int adc5_gen3_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan, int *val, int *val2,
+ long mask)
+{
+ struct adc5_chip *adc = iio_priv(indio_dev);
+ struct adc5_channel_common_prop *prop;
+ u16 adc_code_volt;
+ int ret;
+
+ prop = &adc->chan_props[chan->address].common_props;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_PROCESSED:
+ ret = adc5_gen3_do_conversion(adc, prop, &adc_code_volt);
+ if (ret)
+ return ret;
+
+ ret = qcom_adc5_hw_scale(prop->scale_fn_type, prop->prescale,
+ adc->data, adc_code_volt, val);
+ if (ret)
+ return ret;
+
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_RAW:
+ ret = adc5_gen3_do_conversion(adc, prop, &adc_code_volt);
+ if (ret)
+ return ret;
+ *val = (int)adc_code_volt;
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int adc5_gen3_read_label(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan, char *label)
+{
+ struct adc5_chip *adc = iio_priv(indio_dev);
+ struct adc5_channel_prop *prop;
+
+ prop = &adc->chan_props[chan->address];
+ return sprintf(label, "%s\n", prop->common_props.label);
+}
+
+static const struct iio_info adc5_gen3_info = {
+ .read_raw = adc5_gen3_read_raw,
+ .read_label = adc5_gen3_read_label,
+ .fwnode_xlate = adc5_gen3_fwnode_xlate,
+};
+
+struct adc5_channels {
+ unsigned int prescale_index;
+ enum iio_chan_type type;
+ long info_mask;
+ enum vadc_scale_fn_type scale_fn_type;
+};
+
+/* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
+#define ADC5_CHAN(_type, _mask, _pre, _scale) \
+ { \
+ .prescale_index = _pre, \
+ .type = _type, \
+ .info_mask = _mask, \
+ .scale_fn_type = _scale, \
+ }, \
+
+#define ADC5_CHAN_TEMP(_pre, _scale) \
+ ADC5_CHAN(IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
+
+#define ADC5_CHAN_VOLT(_pre, _scale) \
+ ADC5_CHAN(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
+
+#define ADC5_CHAN_CUR(_pre, _scale) \
+ ADC5_CHAN(IIO_CURRENT, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \
+
+static const struct adc5_channels adc5_gen3_chans_pmic[ADC5_MAX_CHANNEL] = {
+ [ADC5_GEN3_REF_GND] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_1P25VREF] = ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_VPH_PWR] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_VBAT_SNS_QBG] = ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_USB_SNS_V_16] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_VIN_DIV16_MUX] = ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT)
+ [ADC5_GEN3_DIE_TEMP] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_PMIC_THERM_PM7)
+ [ADC5_GEN3_TEMP_ALARM_LITE] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_PMIC_THERM_PM7)
+ [ADC5_GEN3_AMUX1_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX2_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX3_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX4_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX5_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX6_THM_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX1_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX2_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX3_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+ [ADC5_GEN3_AMUX4_GPIO_100K_PU] = ADC5_CHAN_TEMP(0,
+ SCALE_HW_CALIB_THERM_100K_PU_PM7)
+};
+
+static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc,
+ struct adc5_channel_prop *prop,
+ struct fwnode_handle *fwnode)
+{
+ const char *name = fwnode_get_name(fwnode);
+ const struct adc5_data *data = adc->data;
+ u32 chan, value, varr[2], sid = 0;
+ struct device *dev = adc->dev;
+ const char *channel_name;
+ int ret;
+
+ ret = fwnode_property_read_u32(fwnode, "reg", &chan);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "invalid channel number %s\n", name);
+
+ /*
+ * Value read from "reg" is virtual channel number
+ * virtual channel number = sid << 8 | channel number
+ */
+ sid = FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan);
+ chan = FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan);
+
+ if (chan > ADC5_GEN3_OFFSET_EXT2)
+ return dev_err_probe(dev, -EINVAL, "%s invalid channel number %d\n", name, chan);
+
+ prop->common_props.channel = chan;
+ prop->common_props.sid = sid;
+
+ channel_name = name;
+ fwnode_property_read_string(fwnode, "label", &channel_name);
+ prop->common_props.label = channel_name;
+
+ value = data->decimation[ADC5_DECIMATION_DEFAULT];
+ fwnode_property_read_u32(fwnode, "qcom,decimation", &value);
+ ret = qcom_adc5_decimation_from_dt(value, data->decimation);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "%#x invalid decimation %d\n",
+ chan, value);
+ prop->common_props.decimation = ret;
+
+ prop->common_props.prescale = adc->data->adc_chans[chan].prescale_index;
+ ret = fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, 2);
+ if (!ret) {
+ ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "%#x invalid pre-scaling <%d %d>\n",
+ chan, varr[0], varr[1]);
+ prop->common_props.prescale = ret;
+ }
+
+ value = data->hw_settle_1[VADC_DEF_HW_SETTLE_TIME];
+ fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value);
+ ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "%#x invalid hw-settle-time %d us\n",
+ chan, value);
+ prop->common_props.hw_settle_time = ret;
+
+ value = BIT(VADC_DEF_AVG_SAMPLES);
+ fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value);
+ ret = qcom_adc5_avg_samples_from_dt(value);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "%#x invalid avg-samples %d\n",
+ chan, value);
+ prop->common_props.avg_samples = ret;
+
+ if (fwnode_property_read_bool(fwnode, "qcom,ratiometric"))
+ prop->common_props.cal_method = ADC5_RATIOMETRIC_CAL;
+ else
+ prop->common_props.cal_method = ADC5_ABSOLUTE_CAL;
+
+ prop->adc_tm = fwnode_property_read_bool(fwnode, "qcom,adc-tm");
+ if (prop->adc_tm) {
+ adc->n_tm_channels++;
+ if (adc->n_tm_channels > ((adc->num_sdams * 8) - 1))
+ return dev_err_probe(dev, -EINVAL,
+ "Number of TM nodes %u greater than channels supported:%u\n",
+ adc->n_tm_channels, (adc->num_sdams * 8) - 1);
+ }
+
+ return 0;
+}
+
+static const struct adc5_data adc5_gen3_data_pmic = {
+ .full_scale_code_volt = 0x70e4,
+ .adc_chans = adc5_gen3_chans_pmic,
+ .info = &adc5_gen3_info,
+ .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
+ {85, 340, 1360},
+ .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
+ {15, 100, 200, 300, 400, 500, 600, 700,
+ 1000, 2000, 4000, 8000, 16000, 32000,
+ 64000, 128000},
+};
+
+static const struct of_device_id adc5_match_table[] = {
+ {
+ .compatible = "qcom,spmi-adc5-gen3",
+ .data = &adc5_gen3_data_pmic,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, adc5_match_table);
+
+static int adc5_get_fw_data(struct adc5_chip *adc)
+{
+ const struct adc5_channels *adc_chan;
+ struct adc5_channel_prop *chan_props;
+ struct fwnode_handle *child = NULL;
+ struct iio_chan_spec *iio_chan;
+ unsigned int index = 0;
+ int ret;
+
+ adc->nchannels = device_get_child_node_count(adc->dev);
+ if (!adc->nchannels) {
+ dev_err(adc->dev, "No ADC channels found\n");
+ return -EINVAL;
+ }
+
+ adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
+ sizeof(*adc->iio_chans), GFP_KERNEL);
+ if (!adc->iio_chans)
+ return -ENOMEM;
+
+ adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
+ sizeof(*adc->chan_props), GFP_KERNEL);
+ if (!adc->chan_props)
+ return -ENOMEM;
+
+ chan_props = adc->chan_props;
+ adc->n_tm_channels = 0;
+ iio_chan = adc->iio_chans;
+ adc->data = device_get_match_data(adc->dev);
+
+ device_for_each_child_node(adc->dev, child) {
+ ret = adc5_gen3_get_fw_channel_data(adc, chan_props, child);
+ if (ret < 0)
+ return ret;
+
+ chan_props->chip = adc;
+ adc_chan = &adc->data->adc_chans[chan_props->common_props.channel];
+ chan_props->common_props.scale_fn_type = adc_chan->scale_fn_type;
+
+ iio_chan->channel = V_CHAN(chan_props->common_props);
+ iio_chan->info_mask_separate = adc_chan->info_mask;
+ iio_chan->type = adc_chan->type;
+ iio_chan->address = index;
+ iio_chan->indexed = 1;
+ iio_chan++;
+ chan_props++;
+ index++;
+ }
+
+ return 0;
+}
+
+static void adc5_gen3_uninit_aux(void *data)
+{
+ auxiliary_device_uninit(data);
+}
+
+static void adc5_gen3_delete_aux(void *data)
+{
+ auxiliary_device_delete(data);
+}
+
+static void adc5_gen3_aux_device_release(struct device *dev)
+{
+ struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev);
+
+ kfree(aux);
+}
+
+static int adc5_gen3_add_aux_tm_device(struct adc5_chip *adc)
+{
+ struct tm5_aux_dev_wrapper *aux_device;
+ int i, ret, i_tm = 0;
+
+ aux_device = devm_kzalloc(adc->dev, sizeof(*aux_device), GFP_KERNEL);
+ if (!aux_device)
+ return -ENOMEM;
+
+ aux_device->aux_dev.name = "adc5_tm_gen3";
+ aux_device->aux_dev.dev.parent = adc->dev;
+ aux_device->aux_dev.dev.release = adc5_gen3_aux_device_release;
+
+ aux_device->tm_props = devm_kcalloc(adc->dev, adc->n_tm_channels,
+ sizeof(*aux_device->tm_props), GFP_KERNEL);
+ if (!aux_device->tm_props)
+ return -ENOMEM;
+
+ aux_device->dev_data = &adc->dev_data;
+
+ for (i = 0; i < adc->nchannels; i++) {
+ if (!adc->chan_props[i].adc_tm)
+ continue;
+ aux_device->tm_props[i_tm] = adc->chan_props[i].common_props;
+ i_tm++;
+ }
+
+ device_set_of_node_from_dev(&aux_device->aux_dev.dev, adc->dev);
+
+ aux_device->n_tm_channels = adc->n_tm_channels;
+
+ ret = auxiliary_device_init(&aux_device->aux_dev);
+ if (ret) {
+ kfree(&aux_device->aux_dev);
+ return ret;
+ }
+ ret = devm_add_action_or_reset(adc->dev, adc5_gen3_uninit_aux, &aux_device->aux_dev);
+ if (ret)
+ return ret;
+
+ ret = auxiliary_device_add(&aux_device->aux_dev);
+ if (ret)
+ return ret;
+ ret = devm_add_action_or_reset(adc->dev, adc5_gen3_delete_aux, &aux_device->aux_dev);
+ if (!ret)
+ adc->tm_aux = &aux_device->aux_dev;
+
+ return ret;
+}
+
+void adc5_take_mutex_lock(struct device *dev, bool lock)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
+ struct adc5_chip *adc = iio_priv(indio_dev);
+
+ if (lock)
+ mutex_lock(&adc->lock);
+ else
+ mutex_unlock(&adc->lock);
+}
+EXPORT_SYMBOL_NS_GPL(adc5_take_mutex_lock, IIO_ADC5_GEN3);
+
+int adc5_gen3_get_scaled_reading(struct device *dev, struct adc5_channel_common_prop *common_props,
+ int *val)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
+ struct adc5_chip *adc = iio_priv(indio_dev);
+ u16 adc_code_volt;
+ int ret;
+
+ ret = adc5_gen3_do_conversion(adc, common_props, &adc_code_volt);
+ if (ret)
+ return ret;
+
+ return qcom_adc5_hw_scale(common_props->scale_fn_type, common_props->prescale,
+ adc->data, adc_code_volt, val);
+}
+EXPORT_SYMBOL_NS_GPL(adc5_gen3_get_scaled_reading, IIO_ADC5_GEN3);
+
+int adc5_gen3_therm_code_to_temp(struct device *dev, struct adc5_channel_common_prop *common_props,
+ u16 code, int *val)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
+ struct adc5_chip *adc = iio_priv(indio_dev);
+
+ return qcom_adc5_hw_scale(common_props->scale_fn_type, common_props->prescale,
+ adc->data, code, val);
+}
+EXPORT_SYMBOL_NS_GPL(adc5_gen3_therm_code_to_temp, IIO_ADC5_GEN3);
+
+static int adc5_gen3_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iio_dev *indio_dev;
+ struct adc5_chip *adc;
+ struct regmap *regmap;
+ int ret, i;
+ u32 *reg;
+
+ regmap = dev_get_regmap(dev->parent, NULL);
+ if (!regmap)
+ return -ENODEV;
+
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ adc = iio_priv(indio_dev);
+ adc->dev_data.regmap = regmap;
+ adc->dev = dev;
+
+ ret = device_property_count_u32(dev, "reg");
+ if (ret < 0)
+ return ret;
+
+ adc->num_sdams = ret;
+ adc->dev_data.num_sdams = adc->num_sdams;
+
+ reg = devm_kcalloc(dev, adc->num_sdams, sizeof(u32), GFP_KERNEL);
+ if (!reg)
+ return -ENOMEM;
+
+ ret = device_property_read_u32_array(dev, "reg", reg, adc->num_sdams);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to read reg property, ret = %d\n", ret);
+
+ adc->dev_data.base = devm_kcalloc(dev, adc->num_sdams, sizeof(*adc->dev_data.base),
+ GFP_KERNEL);
+ if (!adc->dev_data.base)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, indio_dev);
+ init_completion(&adc->complete);
+ mutex_init(&adc->lock);
+
+ for (i = 0; i < adc->num_sdams; i++) {
+ adc->dev_data.base[i].base_addr = reg[i];
+
+ adc->dev_data.base[i].irq_name = devm_kasprintf(dev, GFP_KERNEL, "adc-sdam%d", i);
+ if (!adc->dev_data.base[i].irq_name)
+ return -ENOMEM;
+
+ ret = platform_get_irq_byname(pdev, adc->dev_data.base[i].irq_name);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Getting IRQ %d by name failed, ret = %d\n",
+ adc->dev_data.base[i].irq, ret);
+ adc->dev_data.base[i].irq = ret;
+ }
+
+ ret = devm_request_irq(dev, adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq, adc5_gen3_isr,
+ 0, adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq_name, adc);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to request SDAM%d irq, ret = %d\n",
+ ADC5_GEN3_VADC_SDAM, ret);
+
+ ret = adc5_get_fw_data(adc);
+ if (ret < 0)
+ return ret;
+
+ if (adc->n_tm_channels > 0)
+ adc5_gen3_add_aux_tm_device(adc);
+
+ indio_dev->name = pdev->name;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &adc5_gen3_info;
+ indio_dev->channels = adc->iio_chans;
+ indio_dev->num_channels = adc->nchannels;
+
+ return devm_iio_device_register(dev, indio_dev);
+}
+
+static struct platform_driver adc5_gen3_driver = {
+ .driver = {
+ .name = "qcom-spmi-adc5-gen3",
+ .of_match_table = adc5_match_table,
+ },
+ .probe = adc5_gen3_probe,
+};
+module_platform_driver(adc5_gen3_driver);
+
+MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 Gen3 ADC driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/iio/adc/qcom-adc5-gen3-common.h b/include/linux/iio/adc/qcom-adc5-gen3-common.h
new file mode 100644
index 000000000000..785669d62caf
--- /dev/null
+++ b/include/linux/iio/adc/qcom-adc5-gen3-common.h
@@ -0,0 +1,233 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Code shared between the main and auxiliary Qualcomm PMIC voltage ADCs
+ * of type ADC5 Gen3.
+ */
+
+#ifndef QCOM_ADC5_GEN3_COMMON_H
+#define QCOM_ADC5_GEN3_COMMON_H
+
+#include <linux/auxiliary_bus.h>
+#include <linux/delay.h>
+#include <linux/regmap.h>
+#include <linux/iio/adc/qcom-vadc-common.h>
+
+#define ADC5_GEN3_HS 0x45
+#define ADC5_GEN3_HS_BUSY BIT(7)
+#define ADC5_GEN3_HS_READY BIT(0)
+
+#define ADC5_GEN3_STATUS1 0x46
+#define ADC5_GEN3_STATUS1_CONV_FAULT BIT(7)
+#define ADC5_GEN3_STATUS1_THR_CROSS BIT(6)
+#define ADC5_GEN3_STATUS1_EOC BIT(0)
+
+#define ADC5_GEN3_TM_EN_STS 0x47
+#define ADC5_GEN3_TM_HIGH_STS 0x48
+#define ADC5_GEN3_TM_LOW_STS 0x49
+
+#define ADC5_GEN3_EOC_STS 0x4a
+#define ADC5_GEN3_EOC_CHAN_0 BIT(0)
+
+#define ADC5_GEN3_EOC_CLR 0x4b
+#define ADC5_GEN3_TM_HIGH_STS_CLR 0x4c
+#define ADC5_GEN3_TM_LOW_STS_CLR 0x4d
+#define ADC5_GEN3_CONV_ERR_CLR 0x4e
+#define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0)
+
+#define ADC5_GEN3_SID 0x4f
+#define ADC5_GEN3_SID_MASK GENMASK(3, 0)
+
+#define ADC5_GEN3_PERPH_CH 0x50
+#define ADC5_GEN3_CHAN_CONV_REQ BIT(7)
+
+#define ADC5_GEN3_TIMER_SEL 0x51
+#define ADC5_GEN3_TIME_IMMEDIATE 0x1
+
+#define ADC5_GEN3_DIG_PARAM 0x52
+#define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4)
+#define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2)
+
+#define ADC5_GEN3_FAST_AVG 0x53
+#define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7)
+#define ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK GENMASK(2, 0)
+
+#define ADC5_GEN3_ADC_CH_SEL_CTL 0x54
+#define ADC5_GEN3_DELAY_CTL 0x55
+#define ADC5_GEN3_HW_SETTLE_DELAY_MASK GENMASK(3, 0)
+
+#define ADC5_GEN3_CH_EN 0x56
+#define ADC5_GEN3_HIGH_THR_INT_EN BIT(1)
+#define ADC5_GEN3_LOW_THR_INT_EN BIT(0)
+
+#define ADC5_GEN3_LOW_THR0 0x57
+#define ADC5_GEN3_LOW_THR1 0x58
+#define ADC5_GEN3_HIGH_THR0 0x59
+#define ADC5_GEN3_HIGH_THR1 0x5a
+
+#define ADC5_GEN3_CH_DATA0(channel) (0x5c + (channel) * 2)
+#define ADC5_GEN3_CH_DATA1(channel) (0x5d + (channel) * 2)
+
+#define ADC5_GEN3_CONV_REQ 0xe5
+#define ADC5_GEN3_CONV_REQ_REQ BIT(0)
+
+#define ADC5_GEN3_VIRTUAL_SID_MASK GENMASK(15, 8)
+#define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0)
+#define V_CHAN(x) \
+ (FIELD_PREP(ADC5_GEN3_VIRTUAL_SID_MASK, (x).sid) | (x).channel) \
+
+enum adc5_cal_method {
+ ADC5_NO_CAL = 0,
+ ADC5_RATIOMETRIC_CAL,
+ ADC5_ABSOLUTE_CAL
+};
+
+enum adc5_time_select {
+ MEAS_INT_DISABLE = 0,
+ MEAS_INT_IMMEDIATE,
+ MEAS_INT_50MS,
+ MEAS_INT_100MS,
+ MEAS_INT_1S,
+ MEAS_INT_NONE,
+};
+
+struct adc5_sdam_data {
+ u16 base_addr;
+ const char *irq_name;
+ int irq;
+};
+
+struct adc5_device_data {
+ struct regmap *regmap;
+ struct adc5_sdam_data *base;
+ int num_sdams;
+};
+
+/**
+ * struct adc5_channel_prop - ADC channel property.
+ * @channel: channel number, refer to the channel list.
+ * @cal_method: calibration method.
+ * @decimation: sampling rate supported for the channel.
+ * @sid: slave id of PMIC owning the channel.
+ * @label: Channel name used in device tree.
+ * @prescale: channel scaling performed on the input signal.
+ * @hw_settle_time: the time between AMUX being configured and the
+ * start of conversion.
+ * @avg_samples: ability to provide single result from the ADC
+ * that is an average of multiple measurements.
+ * @scale_fn_type: Represents the scaling function to convert voltage
+ * physical units desired by the client for the channel.
+ */
+struct adc5_channel_common_prop {
+ unsigned int channel;
+ enum adc5_cal_method cal_method;
+ unsigned int decimation;
+ unsigned int sid;
+ const char *label;
+ unsigned int prescale;
+ unsigned int hw_settle_time;
+ unsigned int avg_samples;
+ enum vadc_scale_fn_type scale_fn_type;
+};
+
+struct tm5_aux_dev_wrapper {
+ struct auxiliary_device aux_dev;
+ struct adc5_device_data *dev_data;
+ struct adc5_channel_common_prop *tm_props;
+ unsigned int n_tm_channels;
+};
+
+struct adc_tm5_auxiliary_drv {
+ struct auxiliary_driver adrv;
+ void (*tm_event_notify)(struct auxiliary_device *adev);
+};
+
+static int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index,
+ u16 offset, u8 *data, int len)
+{
+ return regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
+}
+
+static int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index,
+ u16 offset, u8 *data, int len)
+{
+ return regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
+}
+
+/*
+ * Worst case delay from PBS in readying handshake bit
+ * can be up to 15ms, when PBS is busy running other
+ * simultaneous transactions, while in the best case, it is
+ * already ready at this point. Assigning polling delay and
+ * retry count accordingly.
+ */
+
+#define ADC5_GEN3_HS_DELAY_MIN_US 100
+#define ADC5_GEN3_HS_DELAY_MAX_US 110
+#define ADC5_GEN3_HS_RETRY_COUNT 150
+
+static int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc,
+ unsigned int sdam_index)
+{
+ u8 conv_req = ADC5_GEN3_CONV_REQ_REQ;
+ int ret, count;
+ u8 status = 0;
+
+ for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) {
+ ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, 1);
+ if (ret)
+ return ret;
+
+ if (status == ADC5_GEN3_HS_READY) {
+ ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ,
+ &conv_req, 1);
+ if (ret)
+ return ret;
+
+ if (!conv_req)
+ return 0;
+ }
+
+ usleep_range(ADC5_GEN3_HS_DELAY_MIN_US, ADC5_GEN3_HS_DELAY_MAX_US);
+ }
+
+ pr_err("Setting HS ready bit timed out, sdam_index:%d, status:%#x\n", sdam_index, status);
+ return -ETIMEDOUT;
+}
+
+static void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, u8 *data)
+{
+ /* Update calibration select and decimation ratio select */
+ *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK);
+ *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method);
+ *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation);
+}
+
+static int adc5_gen3_status_clear(struct adc5_device_data *adc,
+ int sdam_index, u16 offset, u8 *val, int len)
+{
+ u8 value;
+ int ret;
+
+ ret = adc5_gen3_write(adc, sdam_index, offset, val, len);
+ if (ret)
+ return ret;
+
+ /* To indicate conversion request is only to clear a status */
+ value = 0;
+ ret = adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &value, 1);
+ if (ret)
+ return ret;
+
+ value = ADC5_GEN3_CONV_REQ_REQ;
+ return adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &value, 1);
+}
+
+void adc5_take_mutex_lock(struct device *dev, bool lock);
+int adc5_gen3_get_scaled_reading(struct device *dev, struct adc5_channel_common_prop *common_props,
+ int *val);
+int adc5_gen3_therm_code_to_temp(struct device *dev, struct adc5_channel_common_prop *common_props,
+ u16 code, int *val);
+
+#endif /* QCOM_VADC5_GEN3_COMMON_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
2024-10-30 18:58 [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Jishnu Prakash
` (2 preceding siblings ...)
2024-10-30 18:58 ` [PATCH V4 3/4] " Jishnu Prakash
@ 2024-10-30 18:58 ` Jishnu Prakash
2024-10-31 11:00 ` Krzysztof Kozlowski
` (2 more replies)
2024-10-31 7:36 ` [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Krzysztof Kozlowski
4 siblings, 3 replies; 26+ messages in thread
From: Jishnu Prakash @ 2024-10-30 18:58 UTC (permalink / raw)
To: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, dmitry.baryshkov, konrad.dybcio, daniel.lezcano, sboyd,
quic_subbaram, quic_collinsd, quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers, Jishnu Prakash
Add support for ADC_TM part of PMIC5 Gen3.
This is an auxiliary driver under the Gen3 ADC driver, which
implements the threshold setting and interrupt generating
functionalities of QCOM ADC_TM drivers, used to support thermal
trip points.
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
---
drivers/thermal/qcom/Kconfig | 11 +
drivers/thermal/qcom/Makefile | 1 +
drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 489 ++++++++++++++++++
3 files changed, 501 insertions(+)
create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig
index 2c7f3f9a26eb..f9876fb8606d 100644
--- a/drivers/thermal/qcom/Kconfig
+++ b/drivers/thermal/qcom/Kconfig
@@ -21,6 +21,17 @@ config QCOM_SPMI_ADC_TM5
Thermal client sets threshold temperature for both warm and cool and
gets updated when a threshold is reached.
+config QCOM_SPMI_ADC_TM5_GEN3
+ tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3"
+ depends on OF && SPMI && IIO && QCOM_SPMI_ADC5_GEN3
+ select REGMAP_SPMI
+ select QCOM_VADC_COMMON
+ help
+ This enables the auxiliary thermal driver for the ADC5 Gen3 thermal
+ monitoring device. It shows up as a thermal zone with multiple trip points.
+ Thermal client sets threshold temperature for both warm and cool and
+ gets updated when a threshold is reached.
+
config QCOM_SPMI_TEMP_ALARM
tristate "Qualcomm SPMI PMIC Temperature Alarm"
depends on OF && SPMI && IIO
diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile
index 0fa2512042e7..828d9e7bc797 100644
--- a/drivers/thermal/qcom/Makefile
+++ b/drivers/thermal/qcom/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
qcom_tsens-y += tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \
tsens-8960.o
obj-$(CONFIG_QCOM_SPMI_ADC_TM5) += qcom-spmi-adc-tm5.o
+obj-$(CONFIG_QCOM_SPMI_ADC_TM5_GEN3) += qcom-spmi-adc-tm5-gen3.o
obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
obj-$(CONFIG_QCOM_LMH) += lmh.o
diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
new file mode 100644
index 000000000000..fa57f417d833
--- /dev/null
+++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/iio/adc/qcom-adc5-gen3-common.h>
+#include <linux/iio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/thermal.h>
+#include <linux/unaligned.h>
+
+#include "../thermal_hwmon.h"
+
+struct adc_tm5_gen3_chip;
+
+/**
+ * @adc_tm: indicates if the channel is used for TM measurements.
+ * @tm_chan_index: TM channel number used (ranging from 1-7).
+ * @timer: time period of recurring TM measurement.
+ * @tzd: pointer to thermal device corresponding to TM channel.
+ * @high_thr_en: TM high threshold crossing detection enabled.
+ * @low_thr_en: TM low threshold crossing detection enabled.
+ * @last_temp: last temperature that caused threshold violation,
+ * or a thermal TM channel.
+ * @last_temp_set: indicates if last_temp is stored.
+ */
+
+struct adc_tm5_gen3_channel_props {
+ struct device *dev;
+ unsigned int timer;
+ unsigned int tm_chan_index;
+ unsigned int sdam_index;
+ struct adc5_channel_common_prop common_props;
+ bool high_thr_en;
+ bool low_thr_en;
+ bool meas_en;
+ struct adc_tm5_gen3_chip *chip;
+ struct thermal_zone_device *tzd;
+ int last_temp;
+ bool last_temp_set;
+};
+
+struct adc_tm5_gen3_chip {
+ struct adc5_device_data *dev_data;
+ struct adc_tm5_gen3_channel_props *chan_props;
+ unsigned int nchannels;
+ struct device *dev;
+ struct work_struct tm_handler_work;
+};
+
+static int get_sdam_from_irq(struct adc_tm5_gen3_chip *adc_tm5, int irq)
+{
+ int i;
+
+ for (i = 0; i < adc_tm5->dev_data->num_sdams; i++) {
+ if (adc_tm5->dev_data->base[i].irq == irq)
+ return i;
+ }
+ return -ENOENT;
+}
+
+static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id)
+{
+ struct adc_tm5_gen3_chip *adc_tm5 = dev_id;
+ u8 status, tm_status[2], val;
+ int ret, sdam_num;
+
+ sdam_num = get_sdam_from_irq(adc_tm5, irq);
+ if (sdam_num < 0) {
+ dev_err(adc_tm5->dev, "adc irq %d not associated with an sdam\n", irq);
+ return IRQ_HANDLED;
+ }
+
+ ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1, &status, 1);
+ if (ret) {
+ dev_err(adc_tm5->dev, "adc read status1 failed with %d\n", ret);
+ return IRQ_HANDLED;
+ }
+
+ if (status & ADC5_GEN3_STATUS1_CONV_FAULT) {
+ dev_err_ratelimited(adc_tm5->dev, "Unexpected conversion fault, status:%#x\n",
+ status);
+ val = ADC5_GEN3_CONV_ERR_CLR_REQ;
+ adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val,
+ 1);
+ return IRQ_HANDLED;
+ }
+
+ ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
+ if (ret) {
+ dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret);
+ return IRQ_HANDLED;
+ }
+
+ if (tm_status[0] || tm_status[1])
+ schedule_work(&adc_tm5->tm_handler_work);
+
+ dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
+ status, tm_status, tm_status[0], tm_status[1]);
+
+ return IRQ_HANDLED;
+}
+
+static int adc5_gen3_tm_status_check(struct adc_tm5_gen3_chip *adc_tm5,
+ int sdam_index, u8 *tm_status, u8 *buf)
+{
+ int ret;
+
+ ret = adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
+ if (ret) {
+ dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret);
+ return ret;
+ }
+
+ ret = adc5_gen3_status_clear(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR,
+ tm_status, 2);
+ if (ret) {
+ dev_err(adc_tm5->dev, "adc status clear conv_req failed with %d\n", ret);
+ return ret;
+ }
+
+ ret = adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_CH_DATA0(0), buf, 16);
+ if (ret)
+ dev_err(adc_tm5->dev, "adc read data failed with %d\n", ret);
+
+ return ret;
+}
+
+static void tm_handler_work(struct work_struct *work)
+{
+ struct adc_tm5_gen3_chip *adc_tm5 = container_of(work, struct adc_tm5_gen3_chip,
+ tm_handler_work);
+ struct adc_tm5_gen3_channel_props *chan_prop;
+ u8 tm_status[2] = {0};
+ u8 buf[16] = {0};
+ int i, ret = 0, sdam_index = -1;
+
+ for (i = 0; i < adc_tm5->nchannels; i++) {
+ bool upper_set = false, lower_set = false;
+ int temp, offset;
+ u16 code = 0;
+
+ chan_prop = &adc_tm5->chan_props[i];
+ offset = chan_prop->tm_chan_index;
+
+ adc5_take_mutex_lock(adc_tm5->dev, true);
+ if (chan_prop->sdam_index != sdam_index) {
+ sdam_index = chan_prop->sdam_index;
+ ret = adc5_gen3_tm_status_check(adc_tm5, sdam_index, tm_status, buf);
+ if (ret) {
+ adc5_take_mutex_lock(adc_tm5->dev, false);
+ break;
+ }
+ }
+
+ if ((tm_status[0] & BIT(offset)) && chan_prop->high_thr_en)
+ upper_set = true;
+
+ if ((tm_status[1] & BIT(offset)) && chan_prop->low_thr_en)
+ lower_set = true;
+ adc5_take_mutex_lock(adc_tm5->dev, false);
+
+ if (!(upper_set || lower_set))
+ continue;
+
+ code = get_unaligned_le16(&buf[2 * offset]);
+ pr_debug("ADC_TM threshold code:%#x\n", code);
+
+ ret = adc5_gen3_therm_code_to_temp(adc_tm5->dev, &chan_prop->common_props, code,
+ &temp);
+ if (ret) {
+ dev_err(adc_tm5->dev, "Invalid temperature reading, ret = %d, code=%#x\n",
+ ret, code);
+ continue;
+ }
+
+ chan_prop->last_temp = temp;
+ chan_prop->last_temp_set = true;
+ thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED);
+ }
+}
+
+static int adc_tm5_gen3_get_temp(struct thermal_zone_device *tz, int *temp)
+{
+ struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz);
+ struct adc_tm5_gen3_chip *adc_tm5;
+
+ if (!prop || !prop->chip)
+ return -EINVAL;
+
+ adc_tm5 = prop->chip;
+
+ if (prop->last_temp_set) {
+ pr_debug("last_temp: %d\n", prop->last_temp);
+ prop->last_temp_set = false;
+ *temp = prop->last_temp;
+ return 0;
+ }
+
+ return adc5_gen3_get_scaled_reading(adc_tm5->dev, &prop->common_props, temp);
+}
+
+static int _adc_tm5_gen3_disable_channel(struct adc_tm5_gen3_channel_props *prop)
+{
+ struct adc_tm5_gen3_chip *adc_tm5 = prop->chip;
+ int ret;
+ u8 val;
+
+ prop->high_thr_en = false;
+ prop->low_thr_en = false;
+
+ ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index);
+ if (ret)
+ return ret;
+
+ val = BIT(prop->tm_chan_index);
+ ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_TM_HIGH_STS_CLR,
+ &val, 1);
+ if (ret)
+ return ret;
+
+ val = MEAS_INT_DISABLE;
+ ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_TIMER_SEL, &val, 1);
+ if (ret)
+ return ret;
+
+ /* To indicate there is an actual conversion request */
+ val = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index;
+ ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_PERPH_CH, &val, 1);
+ if (ret)
+ return ret;
+
+ val = ADC5_GEN3_CONV_REQ_REQ;
+ return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_CONV_REQ, &val, 1);
+}
+
+static int adc_tm5_gen3_disable_channel(struct adc_tm5_gen3_channel_props *prop)
+{
+ return _adc_tm5_gen3_disable_channel(prop);
+}
+
+# define ADC_TM5_GEN3_CONFIG_REGS 12
+
+static int adc_tm5_gen3_configure(struct adc_tm5_gen3_channel_props *prop,
+ int low_temp, int high_temp)
+{
+ struct adc_tm5_gen3_chip *adc_tm5 = prop->chip;
+ u8 conv_req = 0, buf[ADC_TM5_GEN3_CONFIG_REGS];
+ u16 adc_code;
+ int ret;
+
+ ret = adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index);
+ if (ret < 0)
+ return ret;
+
+ ret = adc5_gen3_read(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ /* Write SID */
+ buf[0] = FIELD_PREP(ADC5_GEN3_SID_MASK, prop->common_props.sid);
+
+ /*
+ * Select TM channel and indicate there is an actual
+ * conversion request
+ */
+ buf[1] = ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index;
+
+ buf[2] = prop->timer;
+
+ /* Digital param selection */
+ adc5_gen3_update_dig_param(&prop->common_props, &buf[3]);
+
+ /* Update fast average sample value */
+ buf[4] &= ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK;
+ buf[4] |= prop->common_props.avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN;
+
+ /* Select ADC channel */
+ buf[5] = prop->common_props.channel;
+
+ /* Select HW settle delay for channel */
+ buf[6] = FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, prop->common_props.hw_settle_time);
+
+ /* High temperature corresponds to low voltage threshold */
+ if (high_temp != INT_MAX) {
+ prop->low_thr_en = true;
+ adc_code = qcom_adc_tm5_gen2_temp_res_scale(high_temp);
+ put_unaligned_le16(adc_code, &buf[8]);
+ } else {
+ prop->low_thr_en = false;
+ }
+
+ /* Low temperature corresponds to high voltage threshold */
+ if (low_temp != -INT_MAX) {
+ prop->high_thr_en = true;
+ adc_code = qcom_adc_tm5_gen2_temp_res_scale(low_temp);
+ put_unaligned_le16(adc_code, &buf[10]);
+ } else {
+ prop->high_thr_en = false;
+ }
+
+ buf[7] = 0;
+ if (prop->high_thr_en)
+ buf[7] |= ADC5_GEN3_HIGH_THR_INT_EN;
+ if (prop->low_thr_en)
+ buf[7] |= ADC5_GEN3_LOW_THR_INT_EN;
+
+ ret = adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_SID, buf, sizeof(buf));
+ if (ret < 0)
+ return ret;
+
+ conv_req = ADC5_GEN3_CONV_REQ_REQ;
+ return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_CONV_REQ, &conv_req,
+ 1);
+}
+
+static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz,
+ int low_temp, int high_temp)
+{
+ struct adc_tm5_gen3_channel_props *prop = thermal_zone_device_priv(tz);
+ struct adc_tm5_gen3_chip *adc_tm5;
+ int ret;
+
+ if (!prop || !prop->chip)
+ return -EINVAL;
+
+ adc_tm5 = prop->chip;
+
+ dev_dbg(adc_tm5->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%d\n",
+ prop->common_props.label, low_temp, high_temp);
+
+ adc5_take_mutex_lock(adc_tm5->dev, true);
+ if (high_temp == INT_MAX && low_temp <= -INT_MAX)
+ ret = adc_tm5_gen3_disable_channel(prop);
+ else
+ ret = adc_tm5_gen3_configure(prop, low_temp, high_temp);
+ adc5_take_mutex_lock(adc_tm5->dev, false);
+
+ return ret;
+}
+
+static const struct thermal_zone_device_ops adc_tm_ops = {
+ .get_temp = adc_tm5_gen3_get_temp,
+ .set_trips = adc_tm5_gen3_set_trip_temp,
+};
+
+static int adc_tm5_register_tzd(struct adc_tm5_gen3_chip *adc_tm5)
+{
+ unsigned int i, channel;
+ struct thermal_zone_device *tzd;
+
+ for (i = 0; i < adc_tm5->nchannels; i++) {
+ channel = V_CHAN(adc_tm5->chan_props[i].common_props);
+ tzd = devm_thermal_of_zone_register(adc_tm5->dev, channel,
+ &adc_tm5->chan_props[i], &adc_tm_ops);
+
+ if (IS_ERR(tzd)) {
+ if (PTR_ERR(tzd) == -ENODEV) {
+ dev_warn(adc_tm5->dev, "thermal sensor on channel %d is not used\n",
+ channel);
+ continue;
+ }
+ return dev_err_probe(adc_tm5->dev, PTR_ERR(tzd),
+ "Error registering TZ zone:%ld for channel:%d\n",
+ PTR_ERR(tzd), channel);
+ }
+ adc_tm5->chan_props[i].tzd = tzd;
+ devm_thermal_add_hwmon_sysfs(adc_tm5->dev, tzd);
+ }
+ return 0;
+}
+
+static void adc5_gen3_clear_work(void *data)
+{
+ struct adc_tm5_gen3_chip *adc_tm5 = data;
+
+ cancel_work_sync(&adc_tm5->tm_handler_work);
+}
+
+static void adc5_gen3_disable(void *data)
+{
+ struct adc_tm5_gen3_chip *adc_tm5 = data;
+ int i;
+
+ adc5_take_mutex_lock(adc_tm5->dev, true);
+ /* Disable all available TM channels */
+ for (i = 0; i < adc_tm5->nchannels; i++)
+ _adc_tm5_gen3_disable_channel(&adc_tm5->chan_props[i]);
+
+ adc5_take_mutex_lock(adc_tm5->dev, false);
+}
+
+static void adctm_event_handler(struct auxiliary_device *adev)
+{
+ struct adc_tm5_gen3_chip *adc_tm5 = auxiliary_get_drvdata(adev);
+
+ schedule_work(&adc_tm5->tm_handler_work);
+}
+
+static int adc_tm5_probe(struct auxiliary_device *aux_dev, const struct auxiliary_device_id *id)
+{
+ struct adc_tm5_gen3_chip *adc_tm5;
+ struct tm5_aux_dev_wrapper *aux_dev_wrapper;
+ struct device *dev = &aux_dev->dev;
+ int i, ret;
+
+ adc_tm5 = devm_kzalloc(&aux_dev->dev, sizeof(*adc_tm5), GFP_KERNEL);
+ if (!adc_tm5)
+ return -ENOMEM;
+
+ aux_dev_wrapper = container_of(aux_dev, struct tm5_aux_dev_wrapper, aux_dev);
+
+ adc_tm5->dev = dev;
+ adc_tm5->dev_data = aux_dev_wrapper->dev_data;
+ adc_tm5->nchannels = aux_dev_wrapper->n_tm_channels;
+ adc_tm5->chan_props = devm_kcalloc(adc_tm5->dev, aux_dev_wrapper->n_tm_channels,
+ sizeof(*adc_tm5->chan_props), GFP_KERNEL);
+ if (!adc_tm5->chan_props)
+ return -ENOMEM;
+
+ for (i = 0; i < adc_tm5->nchannels; i++) {
+ adc_tm5->chan_props[i].common_props = aux_dev_wrapper->tm_props[i];
+ adc_tm5->chan_props[i].timer = MEAS_INT_1S;
+ adc_tm5->chan_props[i].sdam_index = (i + 1) / 8;
+ adc_tm5->chan_props[i].tm_chan_index = (i + 1) % 8;
+ adc_tm5->chan_props[i].chip = adc_tm5;
+ }
+
+ ret = devm_add_action_or_reset(adc_tm5->dev, adc5_gen3_disable, adc_tm5);
+ if (ret)
+ return ret;
+
+ for (i = 1; i < adc_tm5->dev_data->num_sdams; i++) {
+ ret = devm_request_threaded_irq(adc_tm5->dev, adc_tm5->dev_data->base[i].irq, NULL,
+ adctm5_gen3_isr, IRQF_ONESHOT,
+ adc_tm5->dev_data->base[i].irq_name, adc_tm5);
+ if (ret < 0)
+ return ret;
+ }
+
+ INIT_WORK(&adc_tm5->tm_handler_work, tm_handler_work);
+ ret = devm_add_action(adc_tm5->dev, adc5_gen3_clear_work, adc_tm5);
+ if (ret)
+ return ret;
+
+ ret = adc_tm5_register_tzd(adc_tm5);
+ if (ret)
+ return ret;
+
+ auxiliary_set_drvdata(aux_dev, adc_tm5);
+ return 0;
+}
+
+static const struct auxiliary_device_id adctm5_auxiliary_id_table[] = {
+ { .name = "qcom_spmi_adc5_gen3.adc5_tm_gen3", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(auxiliary, adctm5_auxiliary_id_table);
+
+static struct adc_tm5_auxiliary_drv adctm5gen3_auxiliary_drv = {
+ .adrv = {
+ .id_table = adctm5_auxiliary_id_table,
+ .probe = adc_tm5_probe,
+ },
+ .tm_event_notify = adctm_event_handler,
+};
+
+static int __init adctm5_init_module(void)
+{
+ return auxiliary_driver_register(&adctm5gen3_auxiliary_drv.adrv);
+}
+
+static void __exit adctm5_exit_module(void)
+{
+ auxiliary_driver_unregister(&adctm5gen3_auxiliary_drv.adrv);
+}
+
+module_init(adctm5_init_module);
+module_exit(adctm5_exit_module);
+
+MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS(IIO_ADC5_GEN3);
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH V4 1/4] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder
2024-10-30 18:58 ` [PATCH V4 1/4] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder Jishnu Prakash
@ 2024-10-30 20:20 ` Rob Herring (Arm)
2024-11-04 10:21 ` Jishnu Prakash
0 siblings, 1 reply; 26+ messages in thread
From: Rob Herring (Arm) @ 2024-10-30 20:20 UTC (permalink / raw)
To: Jishnu Prakash
Cc: quic_skakitap, daniel.lezcano, andersson, lee,
cros-qcom-dts-watchers, linux-kernel, lars, robh+dt,
quic_subbaram, rafael, quic_kamalw, agross, amitk, linux-pm,
linux-arm-msm, dmitry.baryshkov, quic_amelende, neil.armstrong,
conor+dt, linux-iio, krzysztof.kozlowski+dt, quic_collinsd,
konrad.dybcio, jic23, devicetree, lukasz.luba, rui.zhang, sboyd
On Thu, 31 Oct 2024 00:28:51 +0530, Jishnu Prakash wrote:
> There are several files containing QCOM ADC macros for channel names
> right now in the include/dt-bindings/iio folder. Since all of these
> are specifically for adc, move the files to the
> include/dt-bindings/iio/adc folder.
>
> Also update all affected devicetree and driver files to fix compilation
> errors seen with this move and update documentation files to fix
> dtbinding check errors for the same.
>
> Acked-by: Lee Jones <lee@kernel.org>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> ---
> Changes since v3:
> - Updated files affected by adc file path change in /arch/arm, which
> were missed earlier. Updated some more new devicetree files requiring
> this change in /arch/arm64.
>
> Changes since v2:
> - Updated some more new devicetree files requiring this change.
>
> .../devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml | 8 ++++----
> Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 2 +-
> .../devicetree/bindings/thermal/qcom-spmi-adc-tm-hc.yaml | 2 +-
> .../devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml | 6 +++---
> arch/arm/boot/dts/qcom/pm8226.dtsi | 2 +-
> arch/arm/boot/dts/qcom/pm8941.dtsi | 2 +-
> arch/arm/boot/dts/qcom/pma8084.dtsi | 2 +-
> arch/arm/boot/dts/qcom/pmx55.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm4125.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm6125.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm6150l.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm7250b.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm8150l.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm8950.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm8953.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pmi632.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pmi8950.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pmp8074.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 4 ++--
> arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 4 ++--
> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +-
> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +-
> arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++--
> arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 2 +-
> .../arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +-
> arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 6 +++---
> arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 2 +-
> arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts | 6 +++---
> arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 8 ++++----
> drivers/iio/adc/qcom-spmi-adc5.c | 2 +-
> drivers/iio/adc/qcom-spmi-vadc.c | 2 +-
> include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm7325.h | 2 +-
> include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350.h | 2 +-
> .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350b.h | 2 +-
> .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmk8350.h | 2 +-
> .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735a.h | 2 +-
> .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735b.h | 2 +-
> .../dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h | 2 +-
> include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h | 0
> 49 files changed, 63 insertions(+), 63 deletions(-)
> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm7325.h (98%)
> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350.h (98%)
> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pm8350b.h (99%)
> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmk8350.h (97%)
> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735a.h (95%)
> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-pmr735b.h (95%)
> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h (93%)
> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h (100%)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
In file included from Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.example.dts:80:
./scripts/dtc/include-prefixes/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h:13:10: fatal error: dt-bindings/iio/adc/qcom,spmi-vadc.h: No such file or directory
13 | #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.dtbs:129: Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1442: dt_binding_check] Error 2
make: *** [Makefile:224: __sub-make] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241030185854.4015348-2-quic_jprakash@quicinc.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-30 18:58 ` [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Jishnu Prakash
@ 2024-10-30 20:20 ` Rob Herring (Arm)
2024-10-31 10:58 ` Krzysztof Kozlowski
2024-10-31 17:57 ` Dmitry Baryshkov
2 siblings, 0 replies; 26+ messages in thread
From: Rob Herring (Arm) @ 2024-10-30 20:20 UTC (permalink / raw)
To: Jishnu Prakash
Cc: rafael, daniel.lezcano, quic_amelende, konrad.dybcio,
linux-arm-msm, quic_subbaram, dmitry.baryshkov, agross,
krzysztof.kozlowski+dt, quic_kamalw, conor+dt, quic_collinsd,
andersson, devicetree, rui.zhang, lars, jic23, amitk, linux-iio,
linux-kernel, cros-qcom-dts-watchers, neil.armstrong, linux-pm,
quic_skakitap, sboyd, lee, lukasz.luba, robh+dt
On Thu, 31 Oct 2024 00:28:52 +0530, Jishnu Prakash wrote:
> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS(Programmable Boot Sequence) firmware through a single
> register interface. This interface is implemented on an SDAM (Shared
> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
> than a dedicated ADC peripheral.
>
> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
> channels and virtual channels (combination of ADC channel number and
> PMIC SID number) per PMIC, to be used by clients of this device.
>
> Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> ---
> Changes since v3:
> - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file
> instead of adding separate file and updated top-level constraints in documentation
> file based on discussion with reviewers.
> - Dropped default SID definitions.
> - Addressed other reviewer comments.
>
> Changes since v2:
> - Moved ADC5 Gen3 documentation into a separate new file.
>
> Changes since v1:
> - Updated properties separately for all compatibles to clarify usage
> of new properties and updates in usage of old properties for ADC5 Gen3.
> - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
> mentioning this convention.
> - Used predefined channel IDs in individual PMIC channel definitions
> instead of numeric IDs.
> - Addressed other comments from reviewers.
>
> .../bindings/iio/adc/qcom,spmi-vadc.yaml | 220 ++++++++++++++++--
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550.h | 46 ++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550b.h | 85 +++++++
> .../iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h | 22 ++
> .../iio/adc/qcom,spmi-adc5-gen3-pmk8550.h | 52 +++++
> include/dt-bindings/iio/adc/qcom,spmi-vadc.h | 81 +++++++
> 6 files changed, 486 insertions(+), 20 deletions(-)
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550b.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pm8550vx.h
> create mode 100644 include/dt-bindings/iio/adc/qcom,spmi-adc5-gen3-pmk8550.h
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.example.dts:88:18: fatal error: dt-bindings/iio/adc/qcom,spmi-vadc.h: No such file or directory
88 | #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
make[2]: *** [scripts/Makefile.dtbs:129: Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.example.dtb] Error 1
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241030185854.4015348-3-quic_jprakash@quicinc.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC
2024-10-30 18:58 [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Jishnu Prakash
` (3 preceding siblings ...)
2024-10-30 18:58 ` [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
@ 2024-10-31 7:36 ` Krzysztof Kozlowski
2024-11-13 14:07 ` Jishnu Prakash
4 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-31 7:36 UTC (permalink / raw)
To: Jishnu Prakash
Cc: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, dmitry.baryshkov, konrad.dybcio, daniel.lezcano, sboyd,
quic_subbaram, quic_collinsd, quic_amelende, quic_kamalw, amitk,
lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
On Thu, Oct 31, 2024 at 12:28:50AM +0530, Jishnu Prakash wrote:
> PMIC5 Gen3 has a similar ADC architecture to that on PMIC5 Gen2,
> with all SW communication to ADC going through PMK8550 which
> communicates with other PMICs through PBS. The major difference is
> that the register interface used here is that of an SDAM present on
> PMK8550, rather than a dedicated ADC peripheral. There may be more than one
> SDAM used for ADC5 Gen3. Each ADC SDAM has eight channels, each of which may
> be used for either immediate reads (same functionality as previous PMIC5 and
> PMIC5 Gen2 ADC peripherals) or recurring measurements (same as PMIC5 and PMIC5
> Gen2 ADC_TM functionality). In this case, we have VADC and ADC_TM functionality
> combined into the same driver.
>
> Patch 1 is a cleanup, to move the QCOM ADC dt-bindings files from
> dt-bindings/iio to dt-bindings/iio/adc folder, as they are
> specifically for ADC devices. It also fixes all compilation errors
> with this change in driver and devicetree files and similar errors
> in documentation for dtbinding check.
>
> Patch 2 adds bindings for ADC5 Gen3 peripheral.
>
> Patch 3 adds the main driver for ADC5 Gen3.
>
> Patch 4 adds the auxiliary thermal driver which supports the ADC_TM
> functionality of ADC5 Gen3.
>
> Changes since v3:
> - Updated files affected by adc file path change in /arch/arm folder,
> which were missed earlier.
I don't think this was tested afterwards...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-30 18:58 ` [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Jishnu Prakash
2024-10-30 20:20 ` Rob Herring (Arm)
@ 2024-10-31 10:58 ` Krzysztof Kozlowski
2024-11-13 14:05 ` Jishnu Prakash
2024-10-31 17:57 ` Dmitry Baryshkov
2 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-31 10:58 UTC (permalink / raw)
To: Jishnu Prakash, jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt,
agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
On 30/10/2024 19:58, Jishnu Prakash wrote:
> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS(Programmable Boot Sequence) firmware through a single
> register interface. This interface is implemented on an SDAM (Shared
> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
> than a dedicated ADC peripheral.
>
> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
> channels and virtual channels (combination of ADC channel number and
> PMIC SID number) per PMIC, to be used by clients of this device.
>
> Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> ---
This has still test failures, so limited review follows.
> properties:
> compatible:
> @@ -23,14 +27,20 @@ properties:
> - const: qcom,pms405-adc
> - const: qcom,spmi-adc-rev2
> - enum:
> - - qcom,spmi-vadc
> - - qcom,spmi-adc5
> - qcom,spmi-adc-rev2
> + - qcom,spmi-adc5
> + - qcom,spmi-adc5-gen3
> - qcom,spmi-adc7
> + - qcom,spmi-vadc
>
> reg:
> - description: VADC base address in the SPMI PMIC register map
> - maxItems: 1
> + description:
> + For compatible properties "qcom,spmi-vadc", "qcom,spmi-adc5", "qcom,spmi-adc-rev2"
> + and "qcom,spmi-adc7", reg is the VADC base address in the SPMI PMIC register map.
> + For compatible property "qcom,spmi-adc5-gen3", each reg corresponds to an SDAM
> + peripheral base address that is being used for ADC functionality.
This description is not really needed. You need to provide constraints
in schema.
> + minItems: 1
> + maxItems: 2
>
> '#address-cells':
> const: 1
> @@ -38,20 +48,28 @@ properties:
> '#size-cells':
> const: 0
>
> + "#thermal-sensor-cells":
> + const: 1
> + description:
> + Number of cells required to uniquely identify the thermal sensors.
Drop, redundant.
> + For compatible property "qcom,spmi-adc5-gen3", this property is
> + required for if any channels under it are used for ADC_TM.
> + Since we have multiple sensors this is set to 1.
Drop sentence, redundant.
> +
> '#io-channel-cells':
> const: 1
>
> interrupts:
> - maxItems: 1
> description:
> End of conversion interrupt.
> + For compatible property "qcom,spmi-adc5-gen3", interrupts are defined
> + for each SDAM being used.
Drop descriptions and instead rather list and describe items. You keep
repeating schema in free form text. That's not the point.
> + minItems: 1
> + maxItems: 2
>
> -required:
> - - compatible
> - - reg
> - - '#address-cells'
> - - '#size-cells'
> - - '#io-channel-cells'
> + interrupt-names:
> + minItems: 1
> + maxItems: 2
>
> patternProperties:
> "^channel@[0-9a-f]+$":
> @@ -71,8 +89,8 @@ patternProperties:
> description: |
> ADC channel number.
> See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> - For PMIC7 ADC, the channel numbers are specified separately per PMIC
> - in the PMIC-specific files in include/dt-bindings/iio/adc.
> + For PMIC7 and PMIC5 Gen3 ADC, the channel numbers are specified separately
> + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
>
> label:
> description: |
> @@ -113,11 +131,11 @@ patternProperties:
> channel calibration. If property is not found, channel will be
> calibrated with 0.625V and 1.25V reference channels, also
> known as absolute calibration.
> - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
> - "qcom,spmi-adc-rev2", if this property is specified VADC will use
> - the VDD reference (1.875V) and GND for channel calibration. If
> - property is not found, channel will be calibrated with 0V and 1.25V
> - reference channels, also known as absolute calibration.
> + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7",
> + "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property is
> + specified VADC will use the VDD reference (1.875V) and GND for channel
> + calibration. If property is not found, channel will be calibrated with
> + 0V and 1.25V reference channels, also known as absolute calibration.
> type: boolean
>
> qcom,hw-settle-time:
> @@ -135,9 +153,24 @@ patternProperties:
> from the ADC that is an average of multiple samples. The value
> selected is 2^(value).
>
> + qcom,adc-tm:
> + description:
> + Indicates if ADC_TM monitoring is done on this channel.
What is "ADC_TM"? Why this would be property of a board? This does not
look like suitable for DT, at least based on such very vague explanation.
> + Defined for compatible property "qcom,spmi-adc5-gen3".
Drop redundant.
> + This is the same functionality as in the existing QCOM ADC_TM
> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
What does it mean? How property can represent functionality of entire
binding?
BTW, use full paths when refering to files.
> + type: boolean
> +
> required:
> - reg
>
> +required:
> + - compatible
> + - reg
> + - '#address-cells'
> + - '#size-cells'
> + - '#io-channel-cells'
> +
> allOf:
> - if:
> properties:
> @@ -146,6 +179,15 @@ allOf:
> const: qcom,spmi-vadc
>
> then:
> + properties:
> + reg:
> + minItems: 1
min is redundant.
> + maxItems: 1
> + interrupts:
> + minItems: 1
> + maxItems: 1
So here you list and describe items instead.
> + "#thermal-sensor-cells": false
> + interrupt-names: false
Keep things properly ordered. xxx-names is always next to xxx.
> patternProperties:
> "^channel@[0-9a-f]+$":
> properties:
> @@ -162,6 +204,8 @@ allOf:
> enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 ]
> default: 1
>
> + qcom,adc-tm: false
> +
> - if:
> properties:
> compatible:
> @@ -169,6 +213,15 @@ allOf:
> const: qcom,spmi-adc-rev2
>
> then:
> + properties:
> + reg:
> + minItems: 1
> + maxItems: 1
> + interrupts:
> + minItems: 1
> + maxItems: 1
> + "#thermal-sensor-cells": false
> + interrupt-names: false
> patternProperties:
> "^channel@[0-9a-f]+$":
> properties:
> @@ -185,6 +238,8 @@ allOf:
> enum: [ 1, 2, 4, 8, 16 ]
> default: 1
>
> + qcom,adc-tm: false
> +
> - if:
> properties:
> compatible:
> @@ -192,6 +247,15 @@ allOf:
> const: qcom,spmi-adc5
>
> then:
> + properties:
> + reg:
> + minItems: 1
> + maxItems: 1
> + interrupts:
> + minItems: 1
> + maxItems: 1
> + "#thermal-sensor-cells": false
> + interrupt-names: false
> patternProperties:
> "^channel@[0-9a-f]+$":
> properties:
> @@ -208,6 +272,8 @@ allOf:
> enum: [ 1, 2, 4, 8, 16 ]
> default: 1
>
> + qcom,adc-tm: false
> +
> - if:
> properties:
> compatible:
> @@ -215,6 +281,59 @@ allOf:
> const: qcom,spmi-adc7
>
> then:
> + properties:
> + reg:
> + minItems: 1
> + maxItems: 1
> + interrupts:
> + minItems: 1
> + maxItems: 1
> + "#thermal-sensor-cells": false
> + interrupt-names: false
> + patternProperties:
> + "^channel@[0-9a-f]+$":
> + properties:
> + qcom,decimation:
> + enum: [ 85, 340, 1360 ]
> + default: 1360
> +
> + qcom,hw-settle-time:
> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
> + 8000, 16000, 32000, 64000, 128000 ]
> + default: 15
> +
> + qcom,avg-samples:
> + enum: [ 1, 2, 4, 8, 16 ]
> + default: 1
> +
> + qcom,adc-tm: false
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: qcom,spmi-adc5-gen3
> +
> + then:
> + properties:
> + reg:
> + minItems: 1
Why this is flexible?
> + items:
> + - description: SDAM0 base address in the SPMI PMIC register map
> + - description: SDAM1 base address
> + interrupts:
> + minItems: 1
Why this is flexible?
> + items:
> + - description: SDAM0 end of conversion (EOC) interrupt
> + - description: SDAM1 EOC interrupt
> + interrupt-names:
> + minItems: 1
> + items:
> + - const: adc-sdam0
sdam0
> + - const: adc-sdam1
sdam1
> + required:
> + - interrupts
> + - interrupt-names
> patternProperties:
> "^channel@[0-9a-f]+$":
> properties:
> @@ -307,3 +426,64 @@ examples:
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
2024-10-30 18:58 ` [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
@ 2024-10-31 11:00 ` Krzysztof Kozlowski
2024-11-13 14:06 ` Jishnu Prakash
2024-11-02 11:07 ` kernel test robot
2024-11-02 11:39 ` kernel test robot
2 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-31 11:00 UTC (permalink / raw)
To: Jishnu Prakash, jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt,
agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
On 30/10/2024 19:58, Jishnu Prakash wrote:
> Add support for ADC_TM part of PMIC5 Gen3.
>
> This is an auxiliary driver under the Gen3 ADC driver, which
> implements the threshold setting and interrupt generating
> functionalities of QCOM ADC_TM drivers, used to support thermal
> trip points.
>
> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> ---
> drivers/thermal/qcom/Kconfig | 11 +
> drivers/thermal/qcom/Makefile | 1 +
> drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 489 ++++++++++++++++++
> 3 files changed, 501 insertions(+)
> create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
>
> diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig
> index 2c7f3f9a26eb..f9876fb8606d 100644
> --- a/drivers/thermal/qcom/Kconfig
> +++ b/drivers/thermal/qcom/Kconfig
> @@ -21,6 +21,17 @@ config QCOM_SPMI_ADC_TM5
> Thermal client sets threshold temperature for both warm and cool and
> gets updated when a threshold is reached.
>
> +config QCOM_SPMI_ADC_TM5_GEN3
> + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3"
> + depends on OF && SPMI && IIO && QCOM_SPMI_ADC5_GEN3
|| COMPILE_TEST won't work?
> + select REGMAP_SPMI
> + select QCOM_VADC_COMMON
> + help
> + This enables the auxiliary thermal driver for the ADC5 Gen3 thermal
> + monitoring device. It shows up as a thermal zone with multiple trip points.
> + Thermal client sets threshold temperature for both warm and cool and
> + gets updated when a threshold is reached.
> +
...
> +
> +static const struct auxiliary_device_id adctm5_auxiliary_id_table[] = {
> + { .name = "qcom_spmi_adc5_gen3.adc5_tm_gen3", },
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(auxiliary, adctm5_auxiliary_id_table);
> +
> +static struct adc_tm5_auxiliary_drv adctm5gen3_auxiliary_drv = {
> + .adrv = {
> + .id_table = adctm5_auxiliary_id_table,
> + .probe = adc_tm5_probe,
> + },
> + .tm_event_notify = adctm_event_handler,
> +};
> +
> +static int __init adctm5_init_module(void)
> +{
> + return auxiliary_driver_register(&adctm5gen3_auxiliary_drv.adrv);
> +}
> +
> +static void __exit adctm5_exit_module(void)
> +{
> + auxiliary_driver_unregister(&adctm5gen3_auxiliary_drv.adrv);
> +}
> +
> +module_init(adctm5_init_module);
> +module_exit(adctm5_exit_module);
Why not module_auxiliary_driver?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/4] iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-30 18:58 ` [PATCH V4 3/4] " Jishnu Prakash
@ 2024-10-31 11:03 ` Krzysztof Kozlowski
2024-11-13 14:06 ` Jishnu Prakash
2024-11-02 10:46 ` kernel test robot
1 sibling, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-31 11:03 UTC (permalink / raw)
To: Jishnu Prakash, jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt,
agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
On 30/10/2024 19:58, Jishnu Prakash wrote:
> +
> +static int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index,
> + u16 offset, u8 *data, int len)
> +{
> + return regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
> +}
> +
> +static int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index,
> + u16 offset, u8 *data, int len)
> +{
> + return regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
> +}
> +
> +/*
> + * Worst case delay from PBS in readying handshake bit
> + * can be up to 15ms, when PBS is busy running other
> + * simultaneous transactions, while in the best case, it is
> + * already ready at this point. Assigning polling delay and
> + * retry count accordingly.
> + */
> +
> +#define ADC5_GEN3_HS_DELAY_MIN_US 100
> +#define ADC5_GEN3_HS_DELAY_MAX_US 110
> +#define ADC5_GEN3_HS_RETRY_COUNT 150
> +
> +static int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc,
> + unsigned int sdam_index)
> +{
> + u8 conv_req = ADC5_GEN3_CONV_REQ_REQ;
> + int ret, count;
> + u8 status = 0;
> +
> + for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) {
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, 1);
> + if (ret)
> + return ret;
> +
> + if (status == ADC5_GEN3_HS_READY) {
> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ,
> + &conv_req, 1);
> + if (ret)
> + return ret;
> +
> + if (!conv_req)
> + return 0;
> + }
> +
> + usleep_range(ADC5_GEN3_HS_DELAY_MIN_US, ADC5_GEN3_HS_DELAY_MAX_US);
> + }
> +
> + pr_err("Setting HS ready bit timed out, sdam_index:%d, status:%#x\n", sdam_index, status);
> + return -ETIMEDOUT;
> +}
> +
> +static void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, u8 *data)
> +{
> + /* Update calibration select and decimation ratio select */
> + *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK);
> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method);
> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation);
> +}
> +
> +static int adc5_gen3_status_clear(struct adc5_device_data *adc,
> + int sdam_index, u16 offset, u8 *val, int len)
> +{
Wait, what? Why are you defining functions in header causing multiple
copies of them? And even if: why this is not inline? But regardless:
this is a strong NAK from me.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-30 18:58 ` [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Jishnu Prakash
2024-10-30 20:20 ` Rob Herring (Arm)
2024-10-31 10:58 ` Krzysztof Kozlowski
@ 2024-10-31 17:57 ` Dmitry Baryshkov
2024-11-13 14:06 ` Jishnu Prakash
2 siblings, 1 reply; 26+ messages in thread
From: Dmitry Baryshkov @ 2024-10-31 17:57 UTC (permalink / raw)
To: Jishnu Prakash
Cc: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, konrad.dybcio, daniel.lezcano, sboyd, quic_subbaram,
quic_collinsd, quic_amelende, quic_kamalw, amitk, lee, rafael,
rui.zhang, lukasz.luba, lars, quic_skakitap, neil.armstrong,
devicetree, linux-arm-msm, linux-iio, linux-kernel, linux-pm,
cros-qcom-dts-watchers
On Thu, Oct 31, 2024 at 12:28:52AM +0530, Jishnu Prakash wrote:
> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>
> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> going through PBS(Programmable Boot Sequence) firmware through a single
> register interface. This interface is implemented on an SDAM (Shared
> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
> than a dedicated ADC peripheral.
>
> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
> channels and virtual channels (combination of ADC channel number and
> PMIC SID number) per PMIC, to be used by clients of this device.
>
> Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> ---
> Changes since v3:
> - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file
> instead of adding separate file and updated top-level constraints in documentation
> file based on discussion with reviewers.
I think it has been better, when it was a separate file. Krzysztof asked
for rationale, not for merging it back. Two different things.
> - Dropped default SID definitions.
> - Addressed other reviewer comments.
>
> Changes since v2:
> - Moved ADC5 Gen3 documentation into a separate new file.
>
> Changes since v1:
> - Updated properties separately for all compatibles to clarify usage
> of new properties and updates in usage of old properties for ADC5 Gen3.
> - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
> mentioning this convention.
> - Used predefined channel IDs in individual PMIC channel definitions
> instead of numeric IDs.
> - Addressed other comments from reviewers.
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/4] iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-30 18:58 ` [PATCH V4 3/4] " Jishnu Prakash
2024-10-31 11:03 ` Krzysztof Kozlowski
@ 2024-11-02 10:46 ` kernel test robot
1 sibling, 0 replies; 26+ messages in thread
From: kernel test robot @ 2024-11-02 10:46 UTC (permalink / raw)
To: Jishnu Prakash, jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt,
agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: oe-kbuild-all, lee, rafael, rui.zhang, lukasz.luba, lars,
quic_skakitap, neil.armstrong, devicetree, linux-arm-msm,
linux-iio, linux-kernel, linux-pm, cros-qcom-dts-watchers,
Jishnu Prakash
Hi Jishnu,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 6fb2fa9805c501d9ade047fc511961f3273cdcb5]
url: https://github.com/intel-lab-lkp/linux/commits/Jishnu-Prakash/dt-bindings-iio-adc-Move-QCOM-ADC-bindings-to-iio-adc-folder/20241031-030237
base: 6fb2fa9805c501d9ade047fc511961f3273cdcb5
patch link: https://lore.kernel.org/r/20241030185854.4015348-4-quic_jprakash%40quicinc.com
patch subject: [PATCH V4 3/4] iio: adc: Add support for QCOM PMIC5 Gen3 ADC
config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20241102/202411021830.6iNtNN1E-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241102/202411021830.6iNtNN1E-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411021830.6iNtNN1E-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/iio/adc/qcom-spmi-adc5-gen3.c:31: warning: Cannot understand * @adc_tm: indicates TM type if the channel is used for TM measurements.
on line 31 - I thought it was a doc line
>> drivers/iio/adc/qcom-spmi-adc5-gen3.c:70: warning: Function parameter or struct member 'dev_data' not described in 'adc5_chip'
>> drivers/iio/adc/qcom-spmi-adc5-gen3.c:70: warning: Function parameter or struct member 'tm_aux' not described in 'adc5_chip'
vim +31 drivers/iio/adc/qcom-spmi-adc5-gen3.c
29
30 /**
> 31 * @adc_tm: indicates TM type if the channel is used for TM measurements.
32 * @chip: pointer to top-level ADC device structure.
33 */
34
35 struct adc5_channel_prop {
36 struct adc5_channel_common_prop common_props;
37 int adc_tm;
38 struct adc5_chip *chip;
39 };
40
41 /**
42 * struct adc5_chip - ADC private structure.
43 * @dev: SPMI ADC5 Gen3 device.
44 * @num_sdams: number of SDAMs (Shared Direct Access Memory Module) being used.
45 * @nchannels: number of ADC channels.
46 * @chan_props: array of ADC channel properties.
47 * @iio_chans: array of IIO channels specification.
48 * @complete: ADC result notification after interrupt is received.
49 * @lock: ADC lock for access to the peripheral, to prevent concurrent
50 * requests from multiple clients.
51 * @n_tm_channels: number of ADC channels used for TM measurements.
52 * @data: software configuration data.
53 */
54 struct adc5_chip {
55 struct device *dev;
56 struct adc5_device_data dev_data;
57 unsigned int num_sdams;
58 unsigned int nchannels;
59 struct adc5_channel_prop *chan_props;
60 struct iio_chan_spec *iio_chans;
61 struct completion complete;
62 /*
63 * lock for access to the peripheral, to prevent concurrent
64 * requests from multiple clients.
65 */
66 struct mutex lock;
67 const struct adc5_data *data;
68 unsigned int n_tm_channels;
69 struct auxiliary_device *tm_aux;
> 70 };
71
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
2024-10-30 18:58 ` [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
2024-10-31 11:00 ` Krzysztof Kozlowski
@ 2024-11-02 11:07 ` kernel test robot
2024-11-02 11:39 ` kernel test robot
2 siblings, 0 replies; 26+ messages in thread
From: kernel test robot @ 2024-11-02 11:07 UTC (permalink / raw)
To: Jishnu Prakash, jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt,
agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: llvm, oe-kbuild-all, lee, rafael, rui.zhang, lukasz.luba, lars,
quic_skakitap, neil.armstrong, devicetree, linux-arm-msm,
linux-iio, linux-kernel, linux-pm, cros-qcom-dts-watchers,
Jishnu Prakash
Hi Jishnu,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 6fb2fa9805c501d9ade047fc511961f3273cdcb5]
url: https://github.com/intel-lab-lkp/linux/commits/Jishnu-Prakash/dt-bindings-iio-adc-Move-QCOM-ADC-bindings-to-iio-adc-folder/20241031-030237
base: 6fb2fa9805c501d9ade047fc511961f3273cdcb5
patch link: https://lore.kernel.org/r/20241030185854.4015348-5-quic_jprakash%40quicinc.com
patch subject: [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20241102/202411021848.djIzD89X-lkp@intel.com/config)
compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241102/202411021848.djIzD89X-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411021848.djIzD89X-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:104:11: warning: format specifies type 'unsigned int' but the argument has type 'u8 *' (aka 'unsigned char *') [-Wformat]
103 | dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
| ~~~
| %s
104 | status, tm_status, tm_status[0], tm_status[1]);
| ^~~~~~~~~
include/linux/dev_printk.h:165:39: note: expanded from macro 'dev_dbg'
165 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ~~~ ^~~~~~~~~~~
include/linux/dynamic_debug.h:274:19: note: expanded from macro 'dynamic_dev_dbg'
274 | dev, fmt, ##__VA_ARGS__)
| ~~~ ^~~~~~~~~~~
include/linux/dynamic_debug.h:250:59: note: expanded from macro '_dynamic_func_call'
250 | _dynamic_func_call_cls(_DPRINTK_CLASS_DFLT, fmt, func, ##__VA_ARGS__)
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:248:65: note: expanded from macro '_dynamic_func_call_cls'
248 | __dynamic_func_call_cls(__UNIQUE_ID(ddebug), cls, fmt, func, ##__VA_ARGS__)
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:224:15: note: expanded from macro '__dynamic_func_call_cls'
224 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
1 warning generated.
vim +104 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
66
67 static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id)
68 {
69 struct adc_tm5_gen3_chip *adc_tm5 = dev_id;
70 u8 status, tm_status[2], val;
71 int ret, sdam_num;
72
73 sdam_num = get_sdam_from_irq(adc_tm5, irq);
74 if (sdam_num < 0) {
75 dev_err(adc_tm5->dev, "adc irq %d not associated with an sdam\n", irq);
76 return IRQ_HANDLED;
77 }
78
79 ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1, &status, 1);
80 if (ret) {
81 dev_err(adc_tm5->dev, "adc read status1 failed with %d\n", ret);
82 return IRQ_HANDLED;
83 }
84
85 if (status & ADC5_GEN3_STATUS1_CONV_FAULT) {
86 dev_err_ratelimited(adc_tm5->dev, "Unexpected conversion fault, status:%#x\n",
87 status);
88 val = ADC5_GEN3_CONV_ERR_CLR_REQ;
89 adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val,
90 1);
91 return IRQ_HANDLED;
92 }
93
94 ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
95 if (ret) {
96 dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret);
97 return IRQ_HANDLED;
98 }
99
100 if (tm_status[0] || tm_status[1])
101 schedule_work(&adc_tm5->tm_handler_work);
102
103 dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
> 104 status, tm_status, tm_status[0], tm_status[1]);
105
106 return IRQ_HANDLED;
107 }
108
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
2024-10-30 18:58 ` [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
2024-10-31 11:00 ` Krzysztof Kozlowski
2024-11-02 11:07 ` kernel test robot
@ 2024-11-02 11:39 ` kernel test robot
2 siblings, 0 replies; 26+ messages in thread
From: kernel test robot @ 2024-11-02 11:39 UTC (permalink / raw)
To: Jishnu Prakash, jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt,
agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: oe-kbuild-all, lee, rafael, rui.zhang, lukasz.luba, lars,
quic_skakitap, neil.armstrong, devicetree, linux-arm-msm,
linux-iio, linux-kernel, linux-pm, cros-qcom-dts-watchers,
Jishnu Prakash
Hi Jishnu,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 6fb2fa9805c501d9ade047fc511961f3273cdcb5]
url: https://github.com/intel-lab-lkp/linux/commits/Jishnu-Prakash/dt-bindings-iio-adc-Move-QCOM-ADC-bindings-to-iio-adc-folder/20241031-030237
base: 6fb2fa9805c501d9ade047fc511961f3273cdcb5
patch link: https://lore.kernel.org/r/20241030185854.4015348-5-quic_jprakash%40quicinc.com
patch subject: [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20241102/202411021924.bHINpnCr-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241102/202411021924.bHINpnCr-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202411021924.bHINpnCr-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/printk.h:599,
from include/asm-generic/bug.h:22,
from arch/x86/include/asm/bug.h:99,
from include/linux/bug.h:5,
from include/linux/fortify-string.h:6,
from include/linux/string.h:390,
from arch/x86/include/asm/page_32.h:18,
from arch/x86/include/asm/page.h:14,
from arch/x86/include/asm/processor.h:20,
from include/linux/sched.h:13,
from include/linux/ratelimit.h:6,
from include/linux/dev_printk.h:16,
from include/linux/device.h:15,
from include/linux/auxiliary_bus.h:11,
from include/linux/iio/adc/qcom-adc5-gen3-common.h:12,
from drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:7:
drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c: In function 'adctm5_gen3_isr':
>> drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:103:31: warning: format '%x' expects argument of type 'unsigned int', but argument 5 has type 'u8 *' {aka 'unsigned char *'} [-Wformat=]
103 | dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dynamic_debug.h:224:29: note: in definition of macro '__dynamic_func_call_cls'
224 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:250:9: note: in expansion of macro '_dynamic_func_call_cls'
250 | _dynamic_func_call_cls(_DPRINTK_CLASS_DFLT, fmt, func, ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~~~~~~~~
include/linux/dynamic_debug.h:273:9: note: in expansion of macro '_dynamic_func_call'
273 | _dynamic_func_call(fmt, __dynamic_dev_dbg, \
| ^~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:165:9: note: in expansion of macro 'dynamic_dev_dbg'
165 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~
include/linux/dev_printk.h:165:30: note: in expansion of macro 'dev_fmt'
165 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:103:9: note: in expansion of macro 'dev_dbg'
103 | dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
| ^~~~~~~
drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:103:66: note: format string is defined here
103 | dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
| ~~^
| |
| unsigned int
| %#hhn
--
>> drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c:22: warning: Cannot understand * @adc_tm: indicates if the channel is used for TM measurements.
on line 22 - I thought it was a doc line
vim +103 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
> 7 #include <linux/iio/adc/qcom-adc5-gen3-common.h>
8 #include <linux/iio/consumer.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/thermal.h>
15 #include <linux/unaligned.h>
16
17 #include "../thermal_hwmon.h"
18
19 struct adc_tm5_gen3_chip;
20
21 /**
> 22 * @adc_tm: indicates if the channel is used for TM measurements.
23 * @tm_chan_index: TM channel number used (ranging from 1-7).
24 * @timer: time period of recurring TM measurement.
25 * @tzd: pointer to thermal device corresponding to TM channel.
26 * @high_thr_en: TM high threshold crossing detection enabled.
27 * @low_thr_en: TM low threshold crossing detection enabled.
28 * @last_temp: last temperature that caused threshold violation,
29 * or a thermal TM channel.
30 * @last_temp_set: indicates if last_temp is stored.
31 */
32
33 struct adc_tm5_gen3_channel_props {
34 struct device *dev;
35 unsigned int timer;
36 unsigned int tm_chan_index;
37 unsigned int sdam_index;
38 struct adc5_channel_common_prop common_props;
39 bool high_thr_en;
40 bool low_thr_en;
41 bool meas_en;
42 struct adc_tm5_gen3_chip *chip;
43 struct thermal_zone_device *tzd;
44 int last_temp;
45 bool last_temp_set;
46 };
47
48 struct adc_tm5_gen3_chip {
49 struct adc5_device_data *dev_data;
50 struct adc_tm5_gen3_channel_props *chan_props;
51 unsigned int nchannels;
52 struct device *dev;
53 struct work_struct tm_handler_work;
54 };
55
56 static int get_sdam_from_irq(struct adc_tm5_gen3_chip *adc_tm5, int irq)
57 {
58 int i;
59
60 for (i = 0; i < adc_tm5->dev_data->num_sdams; i++) {
61 if (adc_tm5->dev_data->base[i].irq == irq)
62 return i;
63 }
64 return -ENOENT;
65 }
66
67 static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id)
68 {
69 struct adc_tm5_gen3_chip *adc_tm5 = dev_id;
70 u8 status, tm_status[2], val;
71 int ret, sdam_num;
72
73 sdam_num = get_sdam_from_irq(adc_tm5, irq);
74 if (sdam_num < 0) {
75 dev_err(adc_tm5->dev, "adc irq %d not associated with an sdam\n", irq);
76 return IRQ_HANDLED;
77 }
78
79 ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1, &status, 1);
80 if (ret) {
81 dev_err(adc_tm5->dev, "adc read status1 failed with %d\n", ret);
82 return IRQ_HANDLED;
83 }
84
85 if (status & ADC5_GEN3_STATUS1_CONV_FAULT) {
86 dev_err_ratelimited(adc_tm5->dev, "Unexpected conversion fault, status:%#x\n",
87 status);
88 val = ADC5_GEN3_CONV_ERR_CLR_REQ;
89 adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num, ADC5_GEN3_CONV_ERR_CLR, &val,
90 1);
91 return IRQ_HANDLED;
92 }
93
94 ret = adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS, tm_status, 2);
95 if (ret) {
96 dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret);
97 return IRQ_HANDLED;
98 }
99
100 if (tm_status[0] || tm_status[1])
101 schedule_work(&adc_tm5->tm_handler_work);
102
> 103 dev_dbg(adc_tm5->dev, "Interrupt status:%#x, TM status:%#x, high:%#x, low:%#x\n",
104 status, tm_status, tm_status[0], tm_status[1]);
105
106 return IRQ_HANDLED;
107 }
108
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 1/4] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder
2024-10-30 20:20 ` Rob Herring (Arm)
@ 2024-11-04 10:21 ` Jishnu Prakash
0 siblings, 0 replies; 26+ messages in thread
From: Jishnu Prakash @ 2024-11-04 10:21 UTC (permalink / raw)
To: Rob Herring (Arm)
Cc: quic_skakitap, daniel.lezcano, andersson, lee,
cros-qcom-dts-watchers, linux-kernel, lars, robh+dt,
quic_subbaram, rafael, quic_kamalw, agross, amitk, linux-pm,
linux-arm-msm, dmitry.baryshkov, quic_amelende, neil.armstrong,
conor+dt, linux-iio, krzysztof.kozlowski+dt, quic_collinsd,
konrad.dybcio, jic23, devicetree, lukasz.luba, rui.zhang, sboyd
Hi Rob,
On 10/31/2024 1:50 AM, Rob Herring (Arm) wrote:
>
> On Thu, 31 Oct 2024 00:28:51 +0530, Jishnu Prakash wrote:
>> There are several files containing QCOM ADC macros for channel names
>> right now in the include/dt-bindings/iio folder. Since all of these
>> are specifically for adc, move the files to the
>> include/dt-bindings/iio/adc folder.
>>
>> Also update all affected devicetree and driver files to fix compilation
>> errors seen with this move and update documentation files to fix
>> dtbinding check errors for the same.
>>
>> Acked-by: Lee Jones <lee@kernel.org>
>> Acked-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>> ---
>> Changes since v3:
>> - Updated files affected by adc file path change in /arch/arm, which
>> were missed earlier. Updated some more new devicetree files requiring
>> this change in /arch/arm64.
>>
>> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-adc7-smb139x.h (93%)
>> rename include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h (100%)
>>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> In file included from Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.example.dts:80:
> ./scripts/dtc/include-prefixes/dt-bindings/iio/adc/qcom,spmi-adc7-pmk8350.h:13:10: fatal error: dt-bindings/iio/adc/qcom,spmi-vadc.h: No such file or directory
> 13 | #include <dt-bindings/iio/adc/qcom,spmi-vadc.h>
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I think there must be some mistake here because my patch does add the file include/dt-bindings/iio/adc/qcom,spmi-vadc.h, through a rename. This is seen at the very end of my patch:
> diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h
> similarity index 100%
> rename from include/dt-bindings/iio/qcom,spmi-vadc.h
> rename to include/dt-bindings/iio/adc/qcom,spmi-vadc.h
This patch moves our ADC-related header files from 'include/dt-bindings/iio/' folder to 'include/dt-bindings/iio/adc' folder
and fixes this path change in all affected files in the same patch....I think this should be expected to pass compilation.
Is it possible something went wrong from your end in this case? I see that both the files mentioned in the above error, qcom,spmi-adc7-pmk8350.h and qcom,spmi-vadc.h
are moved from 'include/dt-bindings/iio/' folder to 'include/dt-bindings/iio/adc' folder in my patch, could the tool be confused due to qcom,spmi-adc7-pmk8350.h
containing the updated path of qcom,spmi-vadc.h?
> compilation terminated.
> make[2]: *** [scripts/Makefile.dtbs:129: Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.example.dtb] Error 1
> make[2]: *** Waiting for unfinished jobs....
> make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1442: dt_binding_check] Error 2
> make: *** [Makefile:224: __sub-make] Error 2
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241030185854.4015348-2-quic_jprakash@quicinc.com
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
I have also followed the above instructions to update dt-schema and run 'make dt_binding_check' again and I did not see the above error.
I'm also not getting any errors when building with this patch applied.
Thanks,
Jishnu
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-31 10:58 ` Krzysztof Kozlowski
@ 2024-11-13 14:05 ` Jishnu Prakash
2024-11-19 9:02 ` Krzysztof Kozlowski
0 siblings, 1 reply; 26+ messages in thread
From: Jishnu Prakash @ 2024-11-13 14:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, jic23, robh+dt, krzysztof.kozlowski+dt,
conor+dt, agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
Hi Krzysztof,
On 10/31/2024 4:28 PM, Krzysztof Kozlowski wrote:
> On 30/10/2024 19:58, Jishnu Prakash wrote:
>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>
>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>> going through PBS(Programmable Boot Sequence) firmware through a single
>> register interface. This interface is implemented on an SDAM (Shared
>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
>> than a dedicated ADC peripheral.
>>
>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>> channels and virtual channels (combination of ADC channel number and
>> PMIC SID number) per PMIC, to be used by clients of this device.
>>
>> Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
>> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>> ---
>
> This has still test failures, so limited review follows.
>
>> properties:
>> compatible:
>> @@ -23,14 +27,20 @@ properties:
>> - const: qcom,pms405-adc
>> - const: qcom,spmi-adc-rev2
>> - enum:
>> - - qcom,spmi-vadc
>> - - qcom,spmi-adc5
>> - qcom,spmi-adc-rev2
>> + - qcom,spmi-adc5
>> + - qcom,spmi-adc5-gen3
>> - qcom,spmi-adc7
>> + - qcom,spmi-vadc
>>
>> reg:
>> - description: VADC base address in the SPMI PMIC register map
>> - maxItems: 1
>> + description:
>> + For compatible properties "qcom,spmi-vadc", "qcom,spmi-adc5", "qcom,spmi-adc-rev2"
>> + and "qcom,spmi-adc7", reg is the VADC base address in the SPMI PMIC register map.
>> + For compatible property "qcom,spmi-adc5-gen3", each reg corresponds to an SDAM
>> + peripheral base address that is being used for ADC functionality.
>
> This description is not really needed. You need to provide constraints
> in schema.
>
>> + minItems: 1
>> + maxItems: 2
>>
>> '#address-cells':
>> const: 1
>> @@ -38,20 +48,28 @@ properties:
>> '#size-cells':
>> const: 0
>>
>> + "#thermal-sensor-cells":
>> + const: 1
>> + description:
>> + Number of cells required to uniquely identify the thermal sensors.
>
> Drop, redundant.
>
>> + For compatible property "qcom,spmi-adc5-gen3", this property is
>> + required for if any channels under it are used for ADC_TM.
>> + Since we have multiple sensors this is set to 1.
>
> Drop sentence, redundant.
>
>> +
>> '#io-channel-cells':
>> const: 1
>>
>> interrupts:
>> - maxItems: 1
>> description:
>> End of conversion interrupt.
>> + For compatible property "qcom,spmi-adc5-gen3", interrupts are defined
>> + for each SDAM being used.
>
> Drop descriptions and instead rather list and describe items. You keep
> repeating schema in free form text. That's not the point.
>
>> + minItems: 1
>> + maxItems: 2
>>
>> -required:
>> - - compatible
>> - - reg
>> - - '#address-cells'
>> - - '#size-cells'
>> - - '#io-channel-cells'
>> + interrupt-names:
>> + minItems: 1
>> + maxItems: 2
>>
>> patternProperties:
>> "^channel@[0-9a-f]+$":
>> @@ -71,8 +89,8 @@ patternProperties:
>> description: |
>> ADC channel number.
>> See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
>> - For PMIC7 ADC, the channel numbers are specified separately per PMIC
>> - in the PMIC-specific files in include/dt-bindings/iio/adc.
>> + For PMIC7 and PMIC5 Gen3 ADC, the channel numbers are specified separately
>> + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
>>
>> label:
>> description: |
>> @@ -113,11 +131,11 @@ patternProperties:
>> channel calibration. If property is not found, channel will be
>> calibrated with 0.625V and 1.25V reference channels, also
>> known as absolute calibration.
>> - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
>> - "qcom,spmi-adc-rev2", if this property is specified VADC will use
>> - the VDD reference (1.875V) and GND for channel calibration. If
>> - property is not found, channel will be calibrated with 0V and 1.25V
>> - reference channels, also known as absolute calibration.
>> + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7",
>> + "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property is
>> + specified VADC will use the VDD reference (1.875V) and GND for channel
>> + calibration. If property is not found, channel will be calibrated with
>> + 0V and 1.25V reference channels, also known as absolute calibration.
>> type: boolean
>>
>> qcom,hw-settle-time:
>> @@ -135,9 +153,24 @@ patternProperties:
>> from the ADC that is an average of multiple samples. The value
>> selected is 2^(value).
>>
>> + qcom,adc-tm:
>> + description:
>> + Indicates if ADC_TM monitoring is done on this channel.
>
> What is "ADC_TM"? Why this would be property of a board? This does not
> look like suitable for DT, at least based on such very vague explanation.
>
>> + Defined for compatible property "qcom,spmi-adc5-gen3".
>
> Drop redundant.
>
>> + This is the same functionality as in the existing QCOM ADC_TM
>> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
>
> What does it mean? How property can represent functionality of entire
> binding?
>
> BTW, use full paths when refering to files.
>
To address all your above questions for ADC_TM:
The file "Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml" describes
the Qualcomm ADC thermal monitoring device, which existed as a separate device on older
PMIC generations. ADC_TM refers to this functionality.
In ADC5 Gen3, ADC_TM functionality is combined with the existing ADC read functionality
described in this file, under a single device.
In the earlier ADC_TM DT nodes, each child node would describe one of the IIO ADC channels being
monitored by ADC_TM HW. In this ADC5 Gen3 device, setting the property 'qcom,adc-tm' for a channel
node means that it will also be monitored in HW exactly like an ADC_TM channel.
It can be considered a hardware property as the monitoring is done by a sequence under
PBS (Programmable Boot Sequence, can be considered firmware), which periodically gets the
channel reading and checks it against upper/lower thresholds set by clients of this driver,
for threshold violations.
>> + type: boolean
>> +
>> required:
>> - reg
>>
>> +required:
>> + - compatible
>> + - reg
>> + - '#address-cells'
>> + - '#size-cells'
>> + - '#io-channel-cells'
>> +
>> allOf:
>> - if:
>> properties:
>> @@ -146,6 +179,15 @@ allOf:
>> const: qcom,spmi-vadc
>>
>> then:
>> + properties:
>> + reg:
>> + minItems: 1
>
> min is redundant.
>
>> + maxItems: 1
>> + interrupts:
>> + minItems: 1
>> + maxItems: 1
>
> So here you list and describe items instead.
Do you mean interrupts should be updated to something like this?
interrupts:
maxItems: 1
description:
End of conversion interrupt.
Does this look right?
>
>> + "#thermal-sensor-cells": false
>> + interrupt-names: false
>
> Keep things properly ordered. xxx-names is always next to xxx.
>
>> patternProperties:
>> "^channel@[0-9a-f]+$":
>> properties:
>> @@ -162,6 +204,8 @@ allOf:
>> enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 ]
>> default: 1
>>
>> + qcom,adc-tm: false
>> +
>> - if:
>> properties:
>> compatible:
>> @@ -169,6 +213,15 @@ allOf:
>> const: qcom,spmi-adc-rev2
>>
>> then:
>> + properties:
>> + reg:
>> + minItems: 1
>> + maxItems: 1
>> + interrupts:
>> + minItems: 1
>> + maxItems: 1
>> + "#thermal-sensor-cells": false
>> + interrupt-names: false
>> patternProperties:
>> "^channel@[0-9a-f]+$":
>> properties:
>> @@ -185,6 +238,8 @@ allOf:
>> enum: [ 1, 2, 4, 8, 16 ]
>> default: 1
>>
>> + qcom,adc-tm: false
>> +
>> - if:
>> properties:
>> compatible:
>> @@ -192,6 +247,15 @@ allOf:
>> const: qcom,spmi-adc5
>>
>> then:
>> + properties:
>> + reg:
>> + minItems: 1
>> + maxItems: 1
>> + interrupts:
>> + minItems: 1
>> + maxItems: 1
>> + "#thermal-sensor-cells": false
>> + interrupt-names: false
>> patternProperties:
>> "^channel@[0-9a-f]+$":
>> properties:
>> @@ -208,6 +272,8 @@ allOf:
>> enum: [ 1, 2, 4, 8, 16 ]
>> default: 1
>>
>> + qcom,adc-tm: false
>> +
>> - if:
>> properties:
>> compatible:
>> @@ -215,6 +281,59 @@ allOf:
>> const: qcom,spmi-adc7
>>
>> then:
>> + properties:
>> + reg:
>> + minItems: 1
>> + maxItems: 1
>> + interrupts:
>> + minItems: 1
>> + maxItems: 1
>> + "#thermal-sensor-cells": false
>> + interrupt-names: false
>> + patternProperties:
>> + "^channel@[0-9a-f]+$":
>> + properties:
>> + qcom,decimation:
>> + enum: [ 85, 340, 1360 ]
>> + default: 1360
>> +
>> + qcom,hw-settle-time:
>> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
>> + 8000, 16000, 32000, 64000, 128000 ]
>> + default: 15
>> +
>> + qcom,avg-samples:
>> + enum: [ 1, 2, 4, 8, 16 ]
>> + default: 1
>> +
>> + qcom,adc-tm: false
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: qcom,spmi-adc5-gen3
>> +
>> + then:
>> + properties:
>> + reg:
>> + minItems: 1
>
> Why this is flexible?
I'm assuming you are asking why it can be either 1 or 2 instead of exactly 2.
Both configurations can be supported in HW and it varies between boards. Some of them
have exactly one SDAM peripheral assigned for ADC usage and some may have two.
>
>> + items:
>> + - description: SDAM0 base address in the SPMI PMIC register map
>> + - description: SDAM1 base address
>> + interrupts:
>> + minItems: 1
>
>
> Why this is flexible?
reg, interrupts and interrupt-names are all added per SDAM, so they can all be
either 1 or 2.
Will address all your other comments in the next patch version.
Thanks,
Jishnu
>
>
>> + items:
>> + - description: SDAM0 end of conversion (EOC) interrupt
>> + - description: SDAM1 EOC interrupt
>> + interrupt-names:
>> + minItems: 1
>> + items:
>> + - const: adc-sdam0
>
> sdam0
>
>> + - const: adc-sdam1
>
> sdam1
>
>> + required:
>> + - interrupts
>> + - interrupt-names
>> patternProperties:
>> "^channel@[0-9a-f]+$":
>> properties:
>> @@ -307,3 +426,64 @@ examples:
>
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-31 17:57 ` Dmitry Baryshkov
@ 2024-11-13 14:06 ` Jishnu Prakash
2024-11-15 16:44 ` Dmitry Baryshkov
0 siblings, 1 reply; 26+ messages in thread
From: Jishnu Prakash @ 2024-11-13 14:06 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, konrad.dybcio, daniel.lezcano, sboyd, quic_subbaram,
quic_collinsd, quic_amelende, quic_kamalw, amitk, lee, rafael,
rui.zhang, lukasz.luba, lars, quic_skakitap, neil.armstrong,
devicetree, linux-arm-msm, linux-iio, linux-kernel, linux-pm,
cros-qcom-dts-watchers
Hi Dmitry,
On 10/31/2024 11:27 PM, Dmitry Baryshkov wrote:
> On Thu, Oct 31, 2024 at 12:28:52AM +0530, Jishnu Prakash wrote:
>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>
>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>> going through PBS(Programmable Boot Sequence) firmware through a single
>> register interface. This interface is implemented on an SDAM (Shared
>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
>> than a dedicated ADC peripheral.
>>
>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>> channels and virtual channels (combination of ADC channel number and
>> PMIC SID number) per PMIC, to be used by clients of this device.
>>
>> Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
>> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>> ---
>> Changes since v3:
>> - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file
>> instead of adding separate file and updated top-level constraints in documentation
>> file based on discussion with reviewers.
>
> I think it has been better, when it was a separate file. Krzysztof asked
> for rationale, not for merging it back. Two different things.
Actually I made that change in a separate file due to a misunderstanding at that time -
I thought a separate file was the only way to accommodate a change in the top-level 'reg' and 'interrupts'
constraints, but I realized later that they could be updated.
From our side, we would prefer to add ADC5 Gen3 documentation in the same file, as it is
mostly the same functionality which reuses all the existing properties present in this file.
Thanks,
Jishnu
>
>> - Dropped default SID definitions.
>> - Addressed other reviewer comments.
>>
>> Changes since v2:
>> - Moved ADC5 Gen3 documentation into a separate new file.
>>
>> Changes since v1:
>> - Updated properties separately for all compatibles to clarify usage
>> of new properties and updates in usage of old properties for ADC5 Gen3.
>> - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment
>> mentioning this convention.
>> - Used predefined channel IDs in individual PMIC channel definitions
>> instead of numeric IDs.
>> - Addressed other comments from reviewers.
>>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/4] iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-10-31 11:03 ` Krzysztof Kozlowski
@ 2024-11-13 14:06 ` Jishnu Prakash
2024-11-19 9:04 ` Krzysztof Kozlowski
0 siblings, 1 reply; 26+ messages in thread
From: Jishnu Prakash @ 2024-11-13 14:06 UTC (permalink / raw)
To: Krzysztof Kozlowski, jic23, robh+dt, krzysztof.kozlowski+dt,
conor+dt, agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
Hi Krzysztof,
On 10/31/2024 4:33 PM, Krzysztof Kozlowski wrote:
> On 30/10/2024 19:58, Jishnu Prakash wrote:
>> +
>> +static int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index,
>> + u16 offset, u8 *data, int len)
>> +{
>> + return regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
>> +}
>> +
>> +static int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index,
>> + u16 offset, u8 *data, int len)
>> +{
>> + return regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
>> +}
>> +
>> +/*
>> + * Worst case delay from PBS in readying handshake bit
>> + * can be up to 15ms, when PBS is busy running other
>> + * simultaneous transactions, while in the best case, it is
>> + * already ready at this point. Assigning polling delay and
>> + * retry count accordingly.
>> + */
>> +
>> +#define ADC5_GEN3_HS_DELAY_MIN_US 100
>> +#define ADC5_GEN3_HS_DELAY_MAX_US 110
>> +#define ADC5_GEN3_HS_RETRY_COUNT 150
>> +
>> +static int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc,
>> + unsigned int sdam_index)
>> +{
>> + u8 conv_req = ADC5_GEN3_CONV_REQ_REQ;
>> + int ret, count;
>> + u8 status = 0;
>> +
>> + for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) {
>> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, 1);
>> + if (ret)
>> + return ret;
>> +
>> + if (status == ADC5_GEN3_HS_READY) {
>> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ,
>> + &conv_req, 1);
>> + if (ret)
>> + return ret;
>> +
>> + if (!conv_req)
>> + return 0;
>> + }
>> +
>> + usleep_range(ADC5_GEN3_HS_DELAY_MIN_US, ADC5_GEN3_HS_DELAY_MAX_US);
>> + }
>> +
>> + pr_err("Setting HS ready bit timed out, sdam_index:%d, status:%#x\n", sdam_index, status);
>> + return -ETIMEDOUT;
>> +}
>> +
>> +static void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, u8 *data)
>> +{
>> + /* Update calibration select and decimation ratio select */
>> + *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK);
>> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method);
>> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation);
>> +}
>> +
>> +static int adc5_gen3_status_clear(struct adc5_device_data *adc,
>> + int sdam_index, u16 offset, u8 *val, int len)
>> +{
>
> Wait, what? Why are you defining functions in header causing multiple
> copies of them? And even if: why this is not inline? But regardless:
> this is a strong NAK from me.
This was meant to hold macros and some helper functions used in both main and auxiliary driver files.
I see what you mean - I'll move the function definitions into a new .c file and mark them inline.
Thanks,
Jishnu
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
2024-10-31 11:00 ` Krzysztof Kozlowski
@ 2024-11-13 14:06 ` Jishnu Prakash
0 siblings, 0 replies; 26+ messages in thread
From: Jishnu Prakash @ 2024-11-13 14:06 UTC (permalink / raw)
To: Krzysztof Kozlowski, jic23, robh+dt, krzysztof.kozlowski+dt,
conor+dt, agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
Hi Krzysztof,
On 10/31/2024 4:30 PM, Krzysztof Kozlowski wrote:
> On 30/10/2024 19:58, Jishnu Prakash wrote:
>> Add support for ADC_TM part of PMIC5 Gen3.
>>
>> This is an auxiliary driver under the Gen3 ADC driver, which
>> implements the threshold setting and interrupt generating
>> functionalities of QCOM ADC_TM drivers, used to support thermal
>> trip points.
>>
>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>> ---
>> drivers/thermal/qcom/Kconfig | 11 +
>> drivers/thermal/qcom/Makefile | 1 +
>> drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 489 ++++++++++++++++++
>> 3 files changed, 501 insertions(+)
>> create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
>>
>> diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig
>> index 2c7f3f9a26eb..f9876fb8606d 100644
>> --- a/drivers/thermal/qcom/Kconfig
>> +++ b/drivers/thermal/qcom/Kconfig
>> @@ -21,6 +21,17 @@ config QCOM_SPMI_ADC_TM5
>> Thermal client sets threshold temperature for both warm and cool and
>> gets updated when a threshold is reached.
>>
>> +config QCOM_SPMI_ADC_TM5_GEN3
>> + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3"
>> + depends on OF && SPMI && IIO && QCOM_SPMI_ADC5_GEN3
>
> || COMPILE_TEST won't work?
Checking again, it looks like most of these dependencies are not needed and making it dependent on QCOM_SPMI_ADC5_GEN3 alone should be sufficient.
Will update this in the next patch version.
>
>> + select REGMAP_SPMI
>> + select QCOM_VADC_COMMON
>> + help
>> + This enables the auxiliary thermal driver for the ADC5 Gen3 thermal
>> + monitoring device. It shows up as a thermal zone with multiple trip points.
>> + Thermal client sets threshold temperature for both warm and cool and
>> + gets updated when a threshold is reached.
>> +
>
>
> ...
>
>> +
>> +static const struct auxiliary_device_id adctm5_auxiliary_id_table[] = {
>> + { .name = "qcom_spmi_adc5_gen3.adc5_tm_gen3", },
>> + {},
>> +};
>> +
>> +MODULE_DEVICE_TABLE(auxiliary, adctm5_auxiliary_id_table);
>> +
>> +static struct adc_tm5_auxiliary_drv adctm5gen3_auxiliary_drv = {
>> + .adrv = {
>> + .id_table = adctm5_auxiliary_id_table,
>> + .probe = adc_tm5_probe,
>> + },
>> + .tm_event_notify = adctm_event_handler,
>> +};
>> +
>> +static int __init adctm5_init_module(void)
>> +{
>> + return auxiliary_driver_register(&adctm5gen3_auxiliary_drv.adrv);
>> +}
>> +
>> +static void __exit adctm5_exit_module(void)
>> +{
>> + auxiliary_driver_unregister(&adctm5gen3_auxiliary_drv.adrv);
>> +}
>> +
>> +module_init(adctm5_init_module);
>> +module_exit(adctm5_exit_module);
>
> Why not module_auxiliary_driver?
module_auxiliary_driver should work, will update it in next patch version.
Thanks,
Jishnu
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC
2024-10-31 7:36 ` [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Krzysztof Kozlowski
@ 2024-11-13 14:07 ` Jishnu Prakash
0 siblings, 0 replies; 26+ messages in thread
From: Jishnu Prakash @ 2024-11-13 14:07 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, dmitry.baryshkov, konrad.dybcio, daniel.lezcano, sboyd,
quic_subbaram, quic_collinsd, quic_amelende, quic_kamalw, amitk,
lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
Hi Krzysztof,
On 10/31/2024 1:06 PM, Krzysztof Kozlowski wrote:
> On Thu, Oct 31, 2024 at 12:28:50AM +0530, Jishnu Prakash wrote:
>> PMIC5 Gen3 has a similar ADC architecture to that on PMIC5 Gen2,
>> with all SW communication to ADC going through PMK8550 which
>> communicates with other PMICs through PBS. The major difference is
>> that the register interface used here is that of an SDAM present on
>> PMK8550, rather than a dedicated ADC peripheral. There may be more than one
>> SDAM used for ADC5 Gen3. Each ADC SDAM has eight channels, each of which may
>> be used for either immediate reads (same functionality as previous PMIC5 and
>> PMIC5 Gen2 ADC peripherals) or recurring measurements (same as PMIC5 and PMIC5
>> Gen2 ADC_TM functionality). In this case, we have VADC and ADC_TM functionality
>> combined into the same driver.
>>
>> Patch 1 is a cleanup, to move the QCOM ADC dt-bindings files from
>> dt-bindings/iio to dt-bindings/iio/adc folder, as they are
>> specifically for ADC devices. It also fixes all compilation errors
>> with this change in driver and devicetree files and similar errors
>> in documentation for dtbinding check.
>>
>> Patch 2 adds bindings for ADC5 Gen3 peripheral.
>>
>> Patch 3 adds the main driver for ADC5 Gen3.
>>
>> Patch 4 adds the auxiliary thermal driver which supports the ADC_TM
>> functionality of ADC5 Gen3.
>>
>> Changes since v3:
>> - Updated files affected by adc file path change in /arch/arm folder,
>> which were missed earlier.
>
> I don't think this was tested afterwards...
If you are referring to the error found by the bot in my V4 patches 1 and 2, I think the error is invalid.
In both cases, this is the error:
fatal error: dt-bindings/iio/adc/qcom,spmi-vadc.h: No such file or directory
But this file is added in patch 1, through a renaming:
rename include/dt-bindings/iio/{ => adc}/qcom,spmi-vadc.h (100%)
I have replied to Rob on the patch 1 mail pointing this out, but I did not get any reply yet.
I have also tried updating dtschema and running 'make dt_binding_check' again myself and I did not get this error.
If this was some rare error on the bot's side, which may not always happen, I'm thinking of pushing the same patch
again in the next patch series, as I think there is nothing to fix from my side. Please let me know if you have any other suggestions.
Thanks,
Jishnu
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-11-13 14:06 ` Jishnu Prakash
@ 2024-11-15 16:44 ` Dmitry Baryshkov
2024-12-10 6:04 ` Jishnu Prakash
0 siblings, 1 reply; 26+ messages in thread
From: Dmitry Baryshkov @ 2024-11-15 16:44 UTC (permalink / raw)
To: Jishnu Prakash
Cc: jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt, agross,
andersson, konrad.dybcio, daniel.lezcano, sboyd, quic_subbaram,
quic_collinsd, quic_amelende, quic_kamalw, amitk, lee, rafael,
rui.zhang, lukasz.luba, lars, quic_skakitap, neil.armstrong,
devicetree, linux-arm-msm, linux-iio, linux-kernel, linux-pm,
cros-qcom-dts-watchers
On Wed, Nov 13, 2024 at 07:36:13PM +0530, Jishnu Prakash wrote:
> Hi Dmitry,
>
> On 10/31/2024 11:27 PM, Dmitry Baryshkov wrote:
> > On Thu, Oct 31, 2024 at 12:28:52AM +0530, Jishnu Prakash wrote:
> >> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
> >> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
> >>
> >> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
> >> going through PBS(Programmable Boot Sequence) firmware through a single
> >> register interface. This interface is implemented on an SDAM (Shared
> >> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
> >> than a dedicated ADC peripheral.
> >>
> >> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
> >> channels and virtual channels (combination of ADC channel number and
> >> PMIC SID number) per PMIC, to be used by clients of this device.
> >>
> >> Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
> >> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
> >> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> >> ---
> >> Changes since v3:
> >> - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file
> >> instead of adding separate file and updated top-level constraints in documentation
> >> file based on discussion with reviewers.
> >
> > I think it has been better, when it was a separate file. Krzysztof asked
> > for rationale, not for merging it back. Two different things.
>
> Actually I made that change in a separate file due to a misunderstanding at that time -
> I thought a separate file was the only way to accommodate a change in the top-level 'reg' and 'interrupts'
> constraints, but I realized later that they could be updated.
>
> From our side, we would prefer to add ADC5 Gen3 documentation in the same file, as it is
> mostly the same functionality which reuses all the existing properties present in this file.
Export the existing properties and reuse them in the new file. Gen3 (in
my opinion) changed the hardware too much. Having all the differences
via conditionals bloats the schema and makes it significantly unreadable
in my opinion.
But please refer to DT maintainers (Rob/Krzysztof/Conor) for the final
opinion.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-11-13 14:05 ` Jishnu Prakash
@ 2024-11-19 9:02 ` Krzysztof Kozlowski
2024-12-10 6:05 ` Jishnu Prakash
0 siblings, 1 reply; 26+ messages in thread
From: Krzysztof Kozlowski @ 2024-11-19 9:02 UTC (permalink / raw)
To: Jishnu Prakash, jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt,
agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
On 13/11/2024 15:05, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 10/31/2024 4:28 PM, Krzysztof Kozlowski wrote:
>> On 30/10/2024 19:58, Jishnu Prakash wrote:
>>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>>
>>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>>> going through PBS(Programmable Boot Sequence) firmware through a single
>>> register interface. This interface is implemented on an SDAM (Shared
>>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
>>> than a dedicated ADC peripheral.
>>>
>>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>>> channels and virtual channels (combination of ADC channel number and
>>> PMIC SID number) per PMIC, to be used by clients of this device.
>>>
>>> Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
>>> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
>>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>>> ---
>>
>> This has still test failures, so limited review follows.
>>
>>> properties:
>>> compatible:
>>> @@ -23,14 +27,20 @@ properties:
>>> - const: qcom,pms405-adc
>>> - const: qcom,spmi-adc-rev2
>>> - enum:
>>> - - qcom,spmi-vadc
>>> - - qcom,spmi-adc5
>>> - qcom,spmi-adc-rev2
>>> + - qcom,spmi-adc5
>>> + - qcom,spmi-adc5-gen3
>>> - qcom,spmi-adc7
>>> + - qcom,spmi-vadc
>>>
>>> reg:
>>> - description: VADC base address in the SPMI PMIC register map
>>> - maxItems: 1
>>> + description:
>>> + For compatible properties "qcom,spmi-vadc", "qcom,spmi-adc5", "qcom,spmi-adc-rev2"
>>> + and "qcom,spmi-adc7", reg is the VADC base address in the SPMI PMIC register map.
>>> + For compatible property "qcom,spmi-adc5-gen3", each reg corresponds to an SDAM
>>> + peripheral base address that is being used for ADC functionality.
>>
>> This description is not really needed. You need to provide constraints
>> in schema.
>>
>>> + minItems: 1
>>> + maxItems: 2
>>>
>>> '#address-cells':
>>> const: 1
>>> @@ -38,20 +48,28 @@ properties:
>>> '#size-cells':
>>> const: 0
>>>
>>> + "#thermal-sensor-cells":
>>> + const: 1
>>> + description:
>>> + Number of cells required to uniquely identify the thermal sensors.
>>
>> Drop, redundant.
>>
>>> + For compatible property "qcom,spmi-adc5-gen3", this property is
>>> + required for if any channels under it are used for ADC_TM.
>>> + Since we have multiple sensors this is set to 1.
>>
>> Drop sentence, redundant.
>>
>>> +
>>> '#io-channel-cells':
>>> const: 1
>>>
>>> interrupts:
>>> - maxItems: 1
>>> description:
>>> End of conversion interrupt.
>>> + For compatible property "qcom,spmi-adc5-gen3", interrupts are defined
>>> + for each SDAM being used.
>>
>> Drop descriptions and instead rather list and describe items. You keep
>> repeating schema in free form text. That's not the point.
>>
>>> + minItems: 1
>>> + maxItems: 2
>>>
>>> -required:
>>> - - compatible
>>> - - reg
>>> - - '#address-cells'
>>> - - '#size-cells'
>>> - - '#io-channel-cells'
>>> + interrupt-names:
>>> + minItems: 1
>>> + maxItems: 2
>>>
>>> patternProperties:
>>> "^channel@[0-9a-f]+$":
>>> @@ -71,8 +89,8 @@ patternProperties:
>>> description: |
>>> ADC channel number.
>>> See include/dt-bindings/iio/adc/qcom,spmi-vadc.h
>>> - For PMIC7 ADC, the channel numbers are specified separately per PMIC
>>> - in the PMIC-specific files in include/dt-bindings/iio/adc.
>>> + For PMIC7 and PMIC5 Gen3 ADC, the channel numbers are specified separately
>>> + per PMIC in the PMIC-specific files in include/dt-bindings/iio/adc.
>>>
>>> label:
>>> description: |
>>> @@ -113,11 +131,11 @@ patternProperties:
>>> channel calibration. If property is not found, channel will be
>>> calibrated with 0.625V and 1.25V reference channels, also
>>> known as absolute calibration.
>>> - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
>>> - "qcom,spmi-adc-rev2", if this property is specified VADC will use
>>> - the VDD reference (1.875V) and GND for channel calibration. If
>>> - property is not found, channel will be calibrated with 0V and 1.25V
>>> - reference channels, also known as absolute calibration.
>>> + - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7",
>>> + "qcom,spmi-adc-rev2" and "qcom,spmi-adc5-gen3", if this property is
>>> + specified VADC will use the VDD reference (1.875V) and GND for channel
>>> + calibration. If property is not found, channel will be calibrated with
>>> + 0V and 1.25V reference channels, also known as absolute calibration.
>>> type: boolean
>>>
>>> qcom,hw-settle-time:
>>> @@ -135,9 +153,24 @@ patternProperties:
>>> from the ADC that is an average of multiple samples. The value
>>> selected is 2^(value).
>>>
>>> + qcom,adc-tm:
>>> + description:
>>> + Indicates if ADC_TM monitoring is done on this channel.
>>
>> What is "ADC_TM"? Why this would be property of a board? This does not
>> look like suitable for DT, at least based on such very vague explanation.
>>
>>> + Defined for compatible property "qcom,spmi-adc5-gen3".
>>
>> Drop redundant.
>>
>>> + This is the same functionality as in the existing QCOM ADC_TM
>>> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
>>
>> What does it mean? How property can represent functionality of entire
>> binding?
>>
>> BTW, use full paths when refering to files.
>>
>
> To address all your above questions for ADC_TM:
>
> The file "Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml" describes
> the Qualcomm ADC thermal monitoring device, which existed as a separate device on older
> PMIC generations. ADC_TM refers to this functionality.
>
> In ADC5 Gen3, ADC_TM functionality is combined with the existing ADC read functionality
> described in this file, under a single device.
>
> In the earlier ADC_TM DT nodes, each child node would describe one of the IIO ADC channels being
> monitored by ADC_TM HW. In this ADC5 Gen3 device, setting the property 'qcom,adc-tm' for a channel
> node means that it will also be monitored in HW exactly like an ADC_TM channel.
>
> It can be considered a hardware property as the monitoring is done by a sequence under
> PBS (Programmable Boot Sequence, can be considered firmware), which periodically gets the
> channel reading and checks it against upper/lower thresholds set by clients of this driver,
> for threshold violations.
So you want to configure channels in different way? Then specify it
precisely - what is the nature of this feature/configuration. I have no
clue what is ADC TM and you keep using it over and over.
I still wait for answer why this is a property of a board.
>
>
>>> + type: boolean
>>> +
>>> required:
>>> - reg
>>>
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - '#address-cells'
>>> + - '#size-cells'
>>> + - '#io-channel-cells'
>>> +
>>> allOf:
>>> - if:
>>> properties:
>>> @@ -146,6 +179,15 @@ allOf:
>>> const: qcom,spmi-vadc
>>>
>>> then:
>>> + properties:
>>> + reg:
>>> + minItems: 1
>>
>> min is redundant.
>>
>>> + maxItems: 1
>>> + interrupts:
>>> + minItems: 1
>>> + maxItems: 1
>>
>> So here you list and describe items instead.
>
> Do you mean interrupts should be updated to something like this?
>
> interrupts:
> maxItems: 1
> description:
> End of conversion interrupt.
>
> Does this look right?
No, you need to list the items. Look at qcom clocks.
>
>>
>>> + "#thermal-sensor-cells": false
>>> + interrupt-names: false
>>
>> Keep things properly ordered. xxx-names is always next to xxx.
>>
>>> patternProperties:
>>> "^channel@[0-9a-f]+$":
>>> properties:
>>> @@ -162,6 +204,8 @@ allOf:
>>> enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 ]
>>> default: 1
>>>
>>> + qcom,adc-tm: false
>>> +
>>> - if:
>>> properties:
>>> compatible:
>>> @@ -169,6 +213,15 @@ allOf:
>>> const: qcom,spmi-adc-rev2
>>>
>>> then:
>>> + properties:
>>> + reg:
>>> + minItems: 1
>>> + maxItems: 1
>>> + interrupts:
>>> + minItems: 1
>>> + maxItems: 1
>>> + "#thermal-sensor-cells": false
>>> + interrupt-names: false
>>> patternProperties:
>>> "^channel@[0-9a-f]+$":
>>> properties:
>>> @@ -185,6 +238,8 @@ allOf:
>>> enum: [ 1, 2, 4, 8, 16 ]
>>> default: 1
>>>
>>> + qcom,adc-tm: false
>>> +
>>> - if:
>>> properties:
>>> compatible:
>>> @@ -192,6 +247,15 @@ allOf:
>>> const: qcom,spmi-adc5
>>>
>>> then:
>>> + properties:
>>> + reg:
>>> + minItems: 1
>>> + maxItems: 1
>>> + interrupts:
>>> + minItems: 1
>>> + maxItems: 1
>>> + "#thermal-sensor-cells": false
>>> + interrupt-names: false
>>> patternProperties:
>>> "^channel@[0-9a-f]+$":
>>> properties:
>>> @@ -208,6 +272,8 @@ allOf:
>>> enum: [ 1, 2, 4, 8, 16 ]
>>> default: 1
>>>
>>> + qcom,adc-tm: false
>>> +
>>> - if:
>>> properties:
>>> compatible:
>>> @@ -215,6 +281,59 @@ allOf:
>>> const: qcom,spmi-adc7
>>>
>>> then:
>>> + properties:
>>> + reg:
>>> + minItems: 1
>>> + maxItems: 1
>>> + interrupts:
>>> + minItems: 1
>>> + maxItems: 1
>>> + "#thermal-sensor-cells": false
>>> + interrupt-names: false
>>> + patternProperties:
>>> + "^channel@[0-9a-f]+$":
>>> + properties:
>>> + qcom,decimation:
>>> + enum: [ 85, 340, 1360 ]
>>> + default: 1360
>>> +
>>> + qcom,hw-settle-time:
>>> + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
>>> + 8000, 16000, 32000, 64000, 128000 ]
>>> + default: 15
>>> +
>>> + qcom,avg-samples:
>>> + enum: [ 1, 2, 4, 8, 16 ]
>>> + default: 1
>>> +
>>> + qcom,adc-tm: false
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: qcom,spmi-adc5-gen3
>>> +
>>> + then:
>>> + properties:
>>> + reg:
>>> + minItems: 1
>>
>> Why this is flexible?
>
> I'm assuming you are asking why it can be either 1 or 2 instead of exactly 2.
> Both configurations can be supported in HW and it varies between boards. Some of them
> have exactly one SDAM peripheral assigned for ADC usage and some may have two.
That's odd. How this can vary between boards with the same, exactly the
same PMIC? Do you program entirely different FW for different boards
with the same hardware (PMIC)?
This is programming model, so any differences here must be obvious.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 3/4] iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-11-13 14:06 ` Jishnu Prakash
@ 2024-11-19 9:04 ` Krzysztof Kozlowski
0 siblings, 0 replies; 26+ messages in thread
From: Krzysztof Kozlowski @ 2024-11-19 9:04 UTC (permalink / raw)
To: Jishnu Prakash, jic23, robh+dt, krzysztof.kozlowski+dt, conor+dt,
agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
On 13/11/2024 15:06, Jishnu Prakash wrote:
> Hi Krzysztof,
>
> On 10/31/2024 4:33 PM, Krzysztof Kozlowski wrote:
>> On 30/10/2024 19:58, Jishnu Prakash wrote:
>>> +
>>> +static int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index,
>>> + u16 offset, u8 *data, int len)
>>> +{
>>> + return regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
>>> +}
>>> +
>>> +static int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index,
>>> + u16 offset, u8 *data, int len)
>>> +{
>>> + return regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len);
>>> +}
>>> +
>>> +/*
>>> + * Worst case delay from PBS in readying handshake bit
>>> + * can be up to 15ms, when PBS is busy running other
>>> + * simultaneous transactions, while in the best case, it is
>>> + * already ready at this point. Assigning polling delay and
>>> + * retry count accordingly.
>>> + */
>>> +
>>> +#define ADC5_GEN3_HS_DELAY_MIN_US 100
>>> +#define ADC5_GEN3_HS_DELAY_MAX_US 110
>>> +#define ADC5_GEN3_HS_RETRY_COUNT 150
>>> +
>>> +static int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc,
>>> + unsigned int sdam_index)
>>> +{
>>> + u8 conv_req = ADC5_GEN3_CONV_REQ_REQ;
>>> + int ret, count;
>>> + u8 status = 0;
>>> +
>>> + for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) {
>>> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, 1);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + if (status == ADC5_GEN3_HS_READY) {
>>> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ,
>>> + &conv_req, 1);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + if (!conv_req)
>>> + return 0;
>>> + }
>>> +
>>> + usleep_range(ADC5_GEN3_HS_DELAY_MIN_US, ADC5_GEN3_HS_DELAY_MAX_US);
>>> + }
>>> +
>>> + pr_err("Setting HS ready bit timed out, sdam_index:%d, status:%#x\n", sdam_index, status);
>>> + return -ETIMEDOUT;
>>> +}
>>> +
>>> +static void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, u8 *data)
>>> +{
>>> + /* Update calibration select and decimation ratio select */
>>> + *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK);
>>> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method);
>>> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation);
>>> +}
>>> +
>>> +static int adc5_gen3_status_clear(struct adc5_device_data *adc,
>>> + int sdam_index, u16 offset, u8 *val, int len)
>>> +{
>>
>> Wait, what? Why are you defining functions in header causing multiple
>> copies of them? And even if: why this is not inline? But regardless:
>> this is a strong NAK from me.
>
> This was meant to hold macros and some helper functions used in both main and auxiliary driver files.
> I see what you mean - I'll move the function definitions into a new .c file and mark them inline.
This is a very odd coding style. Look around other header files: do you
see such patterns? No, because it leads to potential issues I mentioned
above..
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-11-15 16:44 ` Dmitry Baryshkov
@ 2024-12-10 6:04 ` Jishnu Prakash
0 siblings, 0 replies; 26+ messages in thread
From: Jishnu Prakash @ 2024-12-10 6:04 UTC (permalink / raw)
To: Dmitry Baryshkov, robh+dt@kernel.org >> Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: jic23, agross, andersson, konrad.dybcio, daniel.lezcano, sboyd,
quic_subbaram, quic_collinsd, quic_amelende, quic_kamalw, amitk,
lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
Hi Dmitry,
On 11/15/2024 10:14 PM, Dmitry Baryshkov wrote:
> On Wed, Nov 13, 2024 at 07:36:13PM +0530, Jishnu Prakash wrote:
>> Hi Dmitry,
>>
>> On 10/31/2024 11:27 PM, Dmitry Baryshkov wrote:
>>> On Thu, Oct 31, 2024 at 12:28:52AM +0530, Jishnu Prakash wrote:
>>>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>>>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>>>
>>>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>>>> going through PBS(Programmable Boot Sequence) firmware through a single
>>>> register interface. This interface is implemented on an SDAM (Shared
>>>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
>>>> than a dedicated ADC peripheral.
>>>>
>>>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>>>> channels and virtual channels (combination of ADC channel number and
>>>> PMIC SID number) per PMIC, to be used by clients of this device.
>>>>
>>>> Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
>>>> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
>>>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>>>> ---
>>>> Changes since v3:
>>>> - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file
>>>> instead of adding separate file and updated top-level constraints in documentation
>>>> file based on discussion with reviewers.
>>>
>>> I think it has been better, when it was a separate file. Krzysztof asked
>>> for rationale, not for merging it back. Two different things.
>>
>> Actually I made that change in a separate file due to a misunderstanding at that time -
>> I thought a separate file was the only way to accommodate a change in the top-level 'reg' and 'interrupts'
>> constraints, but I realized later that they could be updated.
>>
>> From our side, we would prefer to add ADC5 Gen3 documentation in the same file, as it is
>> mostly the same functionality which reuses all the existing properties present in this file.
>
> Export the existing properties and reuse them in the new file. Gen3 (in
> my opinion) changed the hardware too much. Having all the differences
> via conditionals bloats the schema and makes it significantly unreadable
> in my opinion.
I can do something like this - Krzysztof mentioned in my V3 documentation change that I should put duplicated properties in a common schema, so
I'm thinking of adding a new file named “qcom,spmi-vadc-common.yaml”, which would hold the common properties. This can be used as
a reference in this existing file (qcom,spmi-vadc.yaml) as well as in the new file I will add for Gen3 ADC(qcom,spmi-adc5-gen3.yaml).
>
> But please refer to DT maintainers (Rob/Krzysztof/Conor) for the final
> opinion.
>
Rob/Krzysztof/Conor - please let me know if you have any objections to the change mentioned above.
If there's no issue, I'll do this in the next patch series.
Thanks,
Jishnu
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
2024-11-19 9:02 ` Krzysztof Kozlowski
@ 2024-12-10 6:05 ` Jishnu Prakash
0 siblings, 0 replies; 26+ messages in thread
From: Jishnu Prakash @ 2024-12-10 6:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, jic23, robh+dt, krzysztof.kozlowski+dt,
conor+dt, agross, andersson, dmitry.baryshkov, konrad.dybcio,
daniel.lezcano, sboyd, quic_subbaram, quic_collinsd,
quic_amelende, quic_kamalw, amitk
Cc: lee, rafael, rui.zhang, lukasz.luba, lars, quic_skakitap,
neil.armstrong, devicetree, linux-arm-msm, linux-iio,
linux-kernel, linux-pm, cros-qcom-dts-watchers
Hi Krzysztof,
On 11/19/2024 2:32 PM, Krzysztof Kozlowski wrote:
> On 13/11/2024 15:05, Jishnu Prakash wrote:
>> Hi Krzysztof,
>>
>> On 10/31/2024 4:28 PM, Krzysztof Kozlowski wrote:
>>> On 30/10/2024 19:58, Jishnu Prakash wrote:
>>>> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the
>>>> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs.
>>>>
>>>> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs
>>>> going through PBS(Programmable Boot Sequence) firmware through a single
>>>> register interface. This interface is implemented on an SDAM (Shared
>>>> Direct Access Memory) peripheral on the master PMIC PMK8550 rather
>>>> than a dedicated ADC peripheral.
>>>>
>>>> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC
>>>> channels and virtual channels (combination of ADC channel number and
>>>> PMIC SID number) per PMIC, to be used by clients of this device.
>>>>
>>>> Co-developed-by: Anjelique Melendez <quic_amelende@quicinc.com>
>>>> Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
>>>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>>>> ---
>>>
>>> This has still test failures, so limited review follows.
>>>
>>>> properties:
>>>> compatible:
>>>> @@ -23,14 +27,20 @@ properties:
>>>> - const: qcom,pms405-adc
>>>> - const: qcom,spmi-adc-rev2
>>>> - enum:
>>>> - - qcom,spmi-vadc
>>>> - - qcom,spmi-adc5
>>>> - qcom,spmi-adc-rev2
>>>> + - qcom,spmi-adc5
>>>> + - qcom,spmi-adc5-gen3
>>>> - qcom,spmi-adc7
>>>> + - qcom,spmi-vadc
>>>>
>>>> reg:
>>>> - description: VADC base address in the SPMI PMIC register map
>>>> - maxItems: 1
>>>> + description:
>>>> + For compatible properties "qcom,spmi-vadc", "qcom,spmi-adc5", "qcom,spmi-adc-rev2"
>>>> + and "qcom,spmi-adc7", reg is the VADC base address in the SPMI PMIC register map.
>>>> + For compatible property "qcom,spmi-adc5-gen3", each reg corresponds to an SDAM
>>>> + peripheral base address that is being used for ADC functionality.
>>>
>>> This description is not really needed. You need to provide constraints
>>> in schema.
...
>>>> qcom,hw-settle-time:
>>>> @@ -135,9 +153,24 @@ patternProperties:
>>>> from the ADC that is an average of multiple samples. The value
>>>> selected is 2^(value).
>>>>
>>>> + qcom,adc-tm:
>>>> + description:
>>>> + Indicates if ADC_TM monitoring is done on this channel.
>>>
>>> What is "ADC_TM"? Why this would be property of a board? This does not
>>> look like suitable for DT, at least based on such very vague explanation.
>>>
>>>> + Defined for compatible property "qcom,spmi-adc5-gen3".
>>>
>>> Drop redundant.
>>>
>>>> + This is the same functionality as in the existing QCOM ADC_TM
>>>> + device, documented at devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.
>>>
>>> What does it mean? How property can represent functionality of entire
>>> binding?
>>>
>>> BTW, use full paths when refering to files.
>>>
>>
>> To address all your above questions for ADC_TM:
>>
>> The file "Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml" describes
>> the Qualcomm ADC thermal monitoring device, which existed as a separate device on older
>> PMIC generations. ADC_TM refers to this functionality.
>>
>> In ADC5 Gen3, ADC_TM functionality is combined with the existing ADC read functionality
>> described in this file, under a single device.
>>
>> In the earlier ADC_TM DT nodes, each child node would describe one of the IIO ADC channels being
>> monitored by ADC_TM HW. In this ADC5 Gen3 device, setting the property 'qcom,adc-tm' for a channel
>> node means that it will also be monitored in HW exactly like an ADC_TM channel.
>>
>> It can be considered a hardware property as the monitoring is done by a sequence under
>> PBS (Programmable Boot Sequence, can be considered firmware), which periodically gets the
>> channel reading and checks it against upper/lower thresholds set by clients of this driver,
>> for threshold violations.
>
> So you want to configure channels in different way? Then specify it
> precisely - what is the nature of this feature/configuration. I have no
> clue what is ADC TM and you keep using it over and over.
>
Yes, it is a different channel configuration, I'll update the explanation in the next patch.
For now, to explain the ADC_TM functionality:
ADC_TM is a *threshold monitoring* feature in HW which can be enabled on *any* ADC channel, to trigger an IRQ for threshold violation.
It was implemented in a separate device earlier, for which we had a separate ADC_TM driver.
In Gen3, this feature can be enabled in the same ADC device for any channel and threshold monitoring/IRQ triggering is handled in FW (PBS)
instead of having another dedicated HW block (old design).
> I still wait for answer why this is a property of a board.
>
Setting this property on a channel indicates that HW is capable of monitoring that channel and this monitoring requirement would be based on board design.
>>
>>
>>>> + type: boolean
>>>> +
>>>> required:
>>>> - reg
>>>>
>>>> +required:
>>>> + - compatible
>>>> + - reg
>>>> + - '#address-cells'
>>>> + - '#size-cells'
>>>> + - '#io-channel-cells'
>>>> +
...
>>>> +
>>>> + - if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: qcom,spmi-adc5-gen3
>>>> +
>>>> + then:
>>>> + properties:
>>>> + reg:
>>>> + minItems: 1
>>>
>>> Why this is flexible?
>>
>> I'm assuming you are asking why it can be either 1 or 2 instead of exactly 2.
>> Both configurations can be supported in HW and it varies between boards. Some of them
>> have exactly one SDAM peripheral assigned for ADC usage and some may have two.
>
> That's odd. How this can vary between boards with the same, exactly the
> same PMIC? Do you program entirely different FW for different boards
> with the same hardware (PMIC)?
That is actually true, the FW can be different per SOC.
The number of PMIC SDAM peripherals allocated for ADC is not correlated with the PMIC used,
it is programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements.
The number of ADC SDAMs used on a given SOC with a given PMIC (like PMK8550) will be fixed, but it is possible for
the same PMIC to have 1 of its SDAMs allocated for ADC when used on one SOC and 2 SDAMs allocated for ADC when the PMIC is used on another SOC.
All boards using a particular (SOC + PMIC) combination will have the same number of ADC SDAMs supported on that PMIC.
Thanks,
Jishnu
>
> This is programming model, so any differences here must be obvious.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2024-12-10 6:05 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-30 18:58 [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Jishnu Prakash
2024-10-30 18:58 ` [PATCH V4 1/4] dt-bindings: iio/adc: Move QCOM ADC bindings to iio/adc folder Jishnu Prakash
2024-10-30 20:20 ` Rob Herring (Arm)
2024-11-04 10:21 ` Jishnu Prakash
2024-10-30 18:58 ` [PATCH V4 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Jishnu Prakash
2024-10-30 20:20 ` Rob Herring (Arm)
2024-10-31 10:58 ` Krzysztof Kozlowski
2024-11-13 14:05 ` Jishnu Prakash
2024-11-19 9:02 ` Krzysztof Kozlowski
2024-12-10 6:05 ` Jishnu Prakash
2024-10-31 17:57 ` Dmitry Baryshkov
2024-11-13 14:06 ` Jishnu Prakash
2024-11-15 16:44 ` Dmitry Baryshkov
2024-12-10 6:04 ` Jishnu Prakash
2024-10-30 18:58 ` [PATCH V4 3/4] " Jishnu Prakash
2024-10-31 11:03 ` Krzysztof Kozlowski
2024-11-13 14:06 ` Jishnu Prakash
2024-11-19 9:04 ` Krzysztof Kozlowski
2024-11-02 10:46 ` kernel test robot
2024-10-30 18:58 ` [PATCH V4 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
2024-10-31 11:00 ` Krzysztof Kozlowski
2024-11-13 14:06 ` Jishnu Prakash
2024-11-02 11:07 ` kernel test robot
2024-11-02 11:39 ` kernel test robot
2024-10-31 7:36 ` [PATCH V4 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Krzysztof Kozlowski
2024-11-13 14:07 ` Jishnu Prakash
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